projects / mesa.git / blob
? search:


3630911be76aeb6d83f748f1f3215397a22fe3c4
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_ureg.h"
34 #include "util/hash_table.h"
35 #include "util/crc32.h"
36 #include "util/u_memory.h"
37 #include "util/u_prim.h"
38
39 /* SHADER_CACHE */
40
41 /**
42 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
43 * integer.
44 */
45 static void *si_get_tgsi_binary(struct si_shader_selector *sel)
46 {
47 unsigned tgsi_size = tgsi_num_tokens(sel->tokens) *
48 sizeof(struct tgsi_token);
49 unsigned size = 4 + tgsi_size + sizeof(sel->so);
50 char *result = (char*)MALLOC(size);
51
52 if (!result)
53 return NULL;
54
55 *((uint32_t*)result) = size;
56 memcpy(result + 4, sel->tokens, tgsi_size);
57 memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so));
58 return result;
59 }
60
61 /** Copy "data" to "ptr" and return the next dword following copied data. */
62 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
63 {
64 /* data may be NULL if size == 0 */
65 if (size)
66 memcpy(ptr, data, size);
67 ptr += DIV_ROUND_UP(size, 4);
68 return ptr;
69 }
70
71 /** Read data from "ptr". Return the next dword following the data. */
72 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
73 {
74 memcpy(data, ptr, size);
75 ptr += DIV_ROUND_UP(size, 4);
76 return ptr;
77 }
78
79 /**
80 * Write the size as uint followed by the data. Return the next dword
81 * following the copied data.
82 */
83 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
84 {
85 *ptr++ = size;
86 return write_data(ptr, data, size);
87 }
88
89 /**
90 * Read the size as uint followed by the data. Return both via parameters.
91 * Return the next dword following the data.
92 */
93 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
94 {
95 *size = *ptr++;
96 assert(*data == NULL);
97 if (!*size)
98 return ptr;
99 *data = malloc(*size);
100 return read_data(ptr, *data, *size);
101 }
102
103 /**
104 * Return the shader binary in a buffer. The first 4 bytes contain its size
105 * as integer.
106 */
107 static void *si_get_shader_binary(struct si_shader *shader)
108 {
109 /* There is always a size of data followed by the data itself. */
110 unsigned relocs_size = shader->binary.reloc_count *
111 sizeof(shader->binary.relocs[0]);
112 unsigned disasm_size = strlen(shader->binary.disasm_string) + 1;
113 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
114 strlen(shader->binary.llvm_ir_string) + 1 : 0;
115 unsigned size =
116 4 + /* total size */
117 4 + /* CRC32 of the data below */
118 align(sizeof(shader->config), 4) +
119 align(sizeof(shader->info), 4) +
120 4 + align(shader->binary.code_size, 4) +
121 4 + align(shader->binary.rodata_size, 4) +
122 4 + align(relocs_size, 4) +
123 4 + align(disasm_size, 4) +
124 4 + align(llvm_ir_size, 4);
125 void *buffer = CALLOC(1, size);
126 uint32_t *ptr = (uint32_t*)buffer;
127
128 if (!buffer)
129 return NULL;
130
131 *ptr++ = size;
132 ptr++; /* CRC32 is calculated at the end. */
133
134 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
135 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
136 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
137 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
138 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
139 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
140 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
141 assert((char *)ptr - (char *)buffer == size);
142
143 /* Compute CRC32. */
144 ptr = (uint32_t*)buffer;
145 ptr++;
146 *ptr = util_hash_crc32(ptr + 1, size - 8);
147
148 return buffer;
149 }
150
151 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
152 {
153 uint32_t *ptr = (uint32_t*)binary;
154 uint32_t size = *ptr++;
155 uint32_t crc32 = *ptr++;
156 unsigned chunk_size;
157
158 if (util_hash_crc32(ptr, size - 8) != crc32) {
159 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
160 return false;
161 }
162
163 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
164 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
165 ptr = read_chunk(ptr, (void**)&shader->binary.code,
166 &shader->binary.code_size);
167 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
168 &shader->binary.rodata_size);
169 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
170 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
171 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
172 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
173
174 return true;
175 }
176
177 /**
178 * Insert a shader into the cache. It's assumed the shader is not in the cache.
179 * Use si_shader_cache_load_shader before calling this.
180 *
181 * Returns false on failure, in which case the tgsi_binary should be freed.
182 */
183 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
184 void *tgsi_binary,
185 struct si_shader *shader)
186 {
187 void *hw_binary;
188 struct hash_entry *entry;
189
190 entry = _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
191 if (entry)
192 return false; /* already added */
193
194 hw_binary = si_get_shader_binary(shader);
195 if (!hw_binary)
196 return false;
197
198 if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
199 hw_binary) == NULL) {
200 FREE(hw_binary);
201 return false;
202 }
203
204 return true;
205 }
206
207 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
208 void *tgsi_binary,
209 struct si_shader *shader)
210 {
211 struct hash_entry *entry =
212 _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
213 if (!entry)
214 return false;
215
216 if (!si_load_shader_binary(shader, entry->data))
217 return false;
218
219 p_atomic_inc(&sscreen->b.num_shader_cache_hits);
220 return true;
221 }
222
223 static uint32_t si_shader_cache_key_hash(const void *key)
224 {
225 /* The first dword is the key size. */
226 return util_hash_crc32(key, *(uint32_t*)key);
227 }
228
229 static bool si_shader_cache_key_equals(const void *a, const void *b)
230 {
231 uint32_t *keya = (uint32_t*)a;
232 uint32_t *keyb = (uint32_t*)b;
233
234 /* The first dword is the key size. */
235 if (*keya != *keyb)
236 return false;
237
238 return memcmp(keya, keyb, *keya) == 0;
239 }
240
241 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
242 {
243 FREE((void*)entry->key);
244 FREE(entry->data);
245 }
246
247 bool si_init_shader_cache(struct si_screen *sscreen)
248 {
249 pipe_mutex_init(sscreen->shader_cache_mutex);
250 sscreen->shader_cache =
251 _mesa_hash_table_create(NULL,
252 si_shader_cache_key_hash,
253 si_shader_cache_key_equals);
254 return sscreen->shader_cache != NULL;
255 }
256
257 void si_destroy_shader_cache(struct si_screen *sscreen)
258 {
259 if (sscreen->shader_cache)
260 _mesa_hash_table_destroy(sscreen->shader_cache,
261 si_destroy_shader_cache_entry);
262 pipe_mutex_destroy(sscreen->shader_cache_mutex);
263 }
264
265 /* SHADER STATES */
266
267 static void si_set_tesseval_regs(struct si_screen *sscreen,
268 struct si_shader *shader,
269 struct si_pm4_state *pm4)
270 {
271 struct tgsi_shader_info *info = &shader->selector->info;
272 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
273 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
274 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
275 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
276 unsigned type, partitioning, topology, distribution_mode;
277
278 switch (tes_prim_mode) {
279 case PIPE_PRIM_LINES:
280 type = V_028B6C_TESS_ISOLINE;
281 break;
282 case PIPE_PRIM_TRIANGLES:
283 type = V_028B6C_TESS_TRIANGLE;
284 break;
285 case PIPE_PRIM_QUADS:
286 type = V_028B6C_TESS_QUAD;
287 break;
288 default:
289 assert(0);
290 return;
291 }
292
293 switch (tes_spacing) {
294 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
295 partitioning = V_028B6C_PART_FRAC_ODD;
296 break;
297 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
298 partitioning = V_028B6C_PART_FRAC_EVEN;
299 break;
300 case PIPE_TESS_SPACING_EQUAL:
301 partitioning = V_028B6C_PART_INTEGER;
302 break;
303 default:
304 assert(0);
305 return;
306 }
307
308 if (tes_point_mode)
309 topology = V_028B6C_OUTPUT_POINT;
310 else if (tes_prim_mode == PIPE_PRIM_LINES)
311 topology = V_028B6C_OUTPUT_LINE;
312 else if (tes_vertex_order_cw)
313 /* for some reason, this must be the other way around */
314 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
315 else
316 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
317
318 if (sscreen->has_distributed_tess) {
319 if (sscreen->b.family == CHIP_FIJI ||
320 sscreen->b.family >= CHIP_POLARIS10)
321 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
322 else
323 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
324 } else
325 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
326
327 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
328 S_028B6C_TYPE(type) |
329 S_028B6C_PARTITIONING(partitioning) |
330 S_028B6C_TOPOLOGY(topology) |
331 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
332 }
333
334 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
335 * whether the "fractional odd" tessellation spacing is used.
336 *
337 * Possible VGT configurations and which state should set the register:
338 *
339 * Reg set in | VGT shader configuration | Value
340 * ------------------------------------------------------
341 * VS as VS | VS | 30
342 * VS as ES | ES -> GS -> VS | 30
343 * TES as VS | LS -> HS -> VS | 14 or 30
344 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
345 */
346 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
347 struct si_shader *shader,
348 struct si_pm4_state *pm4)
349 {
350 unsigned type = shader->selector->type;
351
352 if (sscreen->b.family < CHIP_POLARIS10)
353 return;
354
355 /* VS as VS, or VS as ES: */
356 if ((type == PIPE_SHADER_VERTEX &&
357 !shader->key.as_ls &&
358 !shader->is_gs_copy_shader) ||
359 /* TES as VS, or TES as ES: */
360 type == PIPE_SHADER_TESS_EVAL) {
361 unsigned vtx_reuse_depth = 30;
362
363 if (type == PIPE_SHADER_TESS_EVAL &&
364 shader->selector->info.properties[TGSI_PROPERTY_TES_SPACING] ==
365 PIPE_TESS_SPACING_FRACTIONAL_ODD)
366 vtx_reuse_depth = 14;
367
368 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
369 vtx_reuse_depth);
370 }
371 }
372
373 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
374 {
375 if (shader->pm4)
376 si_pm4_clear_state(shader->pm4);
377 else
378 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
379
380 return shader->pm4;
381 }
382
383 static void si_shader_ls(struct si_shader *shader)
384 {
385 struct si_pm4_state *pm4;
386 unsigned vgpr_comp_cnt;
387 uint64_t va;
388
389 pm4 = si_get_shader_pm4_state(shader);
390 if (!pm4)
391 return;
392
393 va = shader->bo->gpu_address;
394 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
395
396 /* We need at least 2 components for LS.
397 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
398 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 1;
399
400 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
401 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
402
403 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
404 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
405 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
406 S_00B528_DX10_CLAMP(1) |
407 S_00B528_FLOAT_MODE(shader->config.float_mode);
408 shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_LS_NUM_USER_SGPR) |
409 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
410 }
411
412 static void si_shader_hs(struct si_shader *shader)
413 {
414 struct si_pm4_state *pm4;
415 uint64_t va;
416
417 pm4 = si_get_shader_pm4_state(shader);
418 if (!pm4)
419 return;
420
421 va = shader->bo->gpu_address;
422 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
423
424 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
425 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
426 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
427 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
428 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
429 S_00B428_DX10_CLAMP(1) |
430 S_00B428_FLOAT_MODE(shader->config.float_mode));
431 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
432 S_00B42C_USER_SGPR(SI_TCS_NUM_USER_SGPR) |
433 S_00B42C_OC_LDS_EN(1) |
434 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
435 }
436
437 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
438 {
439 struct si_pm4_state *pm4;
440 unsigned num_user_sgprs;
441 unsigned vgpr_comp_cnt;
442 uint64_t va;
443 unsigned oc_lds_en;
444
445 pm4 = si_get_shader_pm4_state(shader);
446 if (!pm4)
447 return;
448
449 va = shader->bo->gpu_address;
450 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
451
452 if (shader->selector->type == PIPE_SHADER_VERTEX) {
453 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
454 num_user_sgprs = SI_ES_NUM_USER_SGPR;
455 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
456 vgpr_comp_cnt = 3; /* all components are needed for TES */
457 num_user_sgprs = SI_TES_NUM_USER_SGPR;
458 } else
459 unreachable("invalid shader selector type");
460
461 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
462
463 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
464 shader->selector->esgs_itemsize / 4);
465 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
466 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
467 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
468 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
469 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
470 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
471 S_00B328_DX10_CLAMP(1) |
472 S_00B328_FLOAT_MODE(shader->config.float_mode));
473 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
474 S_00B32C_USER_SGPR(num_user_sgprs) |
475 S_00B32C_OC_LDS_EN(oc_lds_en) |
476 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
477
478 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
479 si_set_tesseval_regs(sscreen, shader, pm4);
480
481 polaris_set_vgt_vertex_reuse(sscreen, shader, pm4);
482 }
483
484 /**
485 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
486 * geometry shader.
487 */
488 static uint32_t si_vgt_gs_mode(struct si_shader_selector *sel)
489 {
490 unsigned gs_max_vert_out = sel->gs_max_out_vertices;
491 unsigned cut_mode;
492
493 if (gs_max_vert_out <= 128) {
494 cut_mode = V_028A40_GS_CUT_128;
495 } else if (gs_max_vert_out <= 256) {
496 cut_mode = V_028A40_GS_CUT_256;
497 } else if (gs_max_vert_out <= 512) {
498 cut_mode = V_028A40_GS_CUT_512;
499 } else {
500 assert(gs_max_vert_out <= 1024);
501 cut_mode = V_028A40_GS_CUT_1024;
502 }
503
504 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
505 S_028A40_CUT_MODE(cut_mode)|
506 S_028A40_ES_WRITE_OPTIMIZE(1) |
507 S_028A40_GS_WRITE_OPTIMIZE(1);
508 }
509
510 static void si_shader_gs(struct si_shader *shader)
511 {
512 struct si_shader_selector *sel = shader->selector;
513 const ubyte *num_components = sel->info.num_stream_output_components;
514 unsigned gs_num_invocations = sel->gs_num_invocations;
515 struct si_pm4_state *pm4;
516 uint64_t va;
517 unsigned max_stream = sel->max_gs_stream;
518 unsigned offset;
519
520 pm4 = si_get_shader_pm4_state(shader);
521 if (!pm4)
522 return;
523
524 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(shader->selector));
525
526 offset = num_components[0] * sel->gs_max_out_vertices;
527 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, offset);
528 if (max_stream >= 1)
529 offset += num_components[1] * sel->gs_max_out_vertices;
530 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, offset);
531 if (max_stream >= 2)
532 offset += num_components[2] * sel->gs_max_out_vertices;
533 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, offset);
534 if (max_stream >= 3)
535 offset += num_components[3] * sel->gs_max_out_vertices;
536 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
537
538 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
539 assert(offset < (1 << 15));
540
541 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, shader->selector->gs_max_out_vertices);
542
543 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, num_components[0]);
544 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? num_components[1] : 0);
545 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? num_components[2] : 0);
546 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? num_components[3] : 0);
547
548 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
549 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
550 S_028B90_ENABLE(gs_num_invocations > 0));
551
552 va = shader->bo->gpu_address;
553 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
554 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
555 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
556
557 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
558 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
559 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
560 S_00B228_DX10_CLAMP(1) |
561 S_00B228_FLOAT_MODE(shader->config.float_mode));
562 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
563 S_00B22C_USER_SGPR(SI_GS_NUM_USER_SGPR) |
564 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
565 }
566
567 /**
568 * Compute the state for \p shader, which will run as a vertex shader on the
569 * hardware.
570 *
571 * If \p gs is non-NULL, it points to the geometry shader for which this shader
572 * is the copy shader.
573 */
574 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
575 struct si_shader_selector *gs)
576 {
577 struct si_pm4_state *pm4;
578 unsigned num_user_sgprs;
579 unsigned nparams, vgpr_comp_cnt;
580 uint64_t va;
581 unsigned oc_lds_en;
582 unsigned window_space =
583 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
584 bool enable_prim_id = si_vs_exports_prim_id(shader);
585
586 pm4 = si_get_shader_pm4_state(shader);
587 if (!pm4)
588 return;
589
590 /* We always write VGT_GS_MODE in the VS state, because every switch
591 * between different shader pipelines involving a different GS or no
592 * GS at all involves a switch of the VS (different GS use different
593 * copy shaders). On the other hand, when the API switches from a GS to
594 * no GS and then back to the same GS used originally, the GS state is
595 * not sent again.
596 */
597 if (!gs) {
598 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
599 S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
600 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
601 } else {
602 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
603 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
604 }
605
606 va = shader->bo->gpu_address;
607 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
608
609 if (gs) {
610 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
611 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
612 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
613 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
614 num_user_sgprs = SI_VS_NUM_USER_SGPR;
615 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
616 vgpr_comp_cnt = 3; /* all components are needed for TES */
617 num_user_sgprs = SI_TES_NUM_USER_SGPR;
618 } else
619 unreachable("invalid shader selector type");
620
621 /* VS is required to export at least one param. */
622 nparams = MAX2(shader->info.nr_param_exports, 1);
623 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
624 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
625
626 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
627 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
628 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
629 V_02870C_SPI_SHADER_4COMP :
630 V_02870C_SPI_SHADER_NONE) |
631 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
632 V_02870C_SPI_SHADER_4COMP :
633 V_02870C_SPI_SHADER_NONE) |
634 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
635 V_02870C_SPI_SHADER_4COMP :
636 V_02870C_SPI_SHADER_NONE));
637
638 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
639
640 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
641 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
642 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
643 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
644 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
645 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
646 S_00B128_DX10_CLAMP(1) |
647 S_00B128_FLOAT_MODE(shader->config.float_mode));
648 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
649 S_00B12C_USER_SGPR(num_user_sgprs) |
650 S_00B12C_OC_LDS_EN(oc_lds_en) |
651 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
652 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
653 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
654 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
655 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
656 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
657 if (window_space)
658 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
659 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
660 else
661 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
662 S_028818_VTX_W0_FMT(1) |
663 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
664 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
665 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
666
667 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
668 si_set_tesseval_regs(sscreen, shader, pm4);
669
670 polaris_set_vgt_vertex_reuse(sscreen, shader, pm4);
671 }
672
673 static unsigned si_get_ps_num_interp(struct si_shader *ps)
674 {
675 struct tgsi_shader_info *info = &ps->selector->info;
676 unsigned num_colors = !!(info->colors_read & 0x0f) +
677 !!(info->colors_read & 0xf0);
678 unsigned num_interp = ps->selector->info.num_inputs +
679 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
680
681 assert(num_interp <= 32);
682 return MIN2(num_interp, 32);
683 }
684
685 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
686 {
687 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
688 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
689
690 /* If the i-th target format is set, all previous target formats must
691 * be non-zero to avoid hangs.
692 */
693 for (i = 0; i < num_targets; i++)
694 if (!(value & (0xf << (i * 4))))
695 value |= V_028714_SPI_SHADER_32_R << (i * 4);
696
697 return value;
698 }
699
700 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
701 {
702 unsigned i, cb_shader_mask = 0;
703
704 for (i = 0; i < 8; i++) {
705 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
706 case V_028714_SPI_SHADER_ZERO:
707 break;
708 case V_028714_SPI_SHADER_32_R:
709 cb_shader_mask |= 0x1 << (i * 4);
710 break;
711 case V_028714_SPI_SHADER_32_GR:
712 cb_shader_mask |= 0x3 << (i * 4);
713 break;
714 case V_028714_SPI_SHADER_32_AR:
715 cb_shader_mask |= 0x9 << (i * 4);
716 break;
717 case V_028714_SPI_SHADER_FP16_ABGR:
718 case V_028714_SPI_SHADER_UNORM16_ABGR:
719 case V_028714_SPI_SHADER_SNORM16_ABGR:
720 case V_028714_SPI_SHADER_UINT16_ABGR:
721 case V_028714_SPI_SHADER_SINT16_ABGR:
722 case V_028714_SPI_SHADER_32_ABGR:
723 cb_shader_mask |= 0xf << (i * 4);
724 break;
725 default:
726 assert(0);
727 }
728 }
729 return cb_shader_mask;
730 }
731
732 static void si_shader_ps(struct si_shader *shader)
733 {
734 struct tgsi_shader_info *info = &shader->selector->info;
735 struct si_pm4_state *pm4;
736 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
737 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
738 uint64_t va;
739 unsigned input_ena = shader->config.spi_ps_input_ena;
740
741 /* we need to enable at least one of them, otherwise we hang the GPU */
742 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
743 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
744 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
745 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
746 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
747 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
748 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
749 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
750 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
751 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
752 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
753 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
754 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
755 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
756
757 /* Validate interpolation optimization flags (read as implications). */
758 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
759 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
760 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
761 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
762 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
763 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
764 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
765 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
766 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
767 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
768 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
769 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
770 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
771 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
772 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
773 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
774 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
775 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
776
777 /* Validate cases when the optimizations are off (read as implications). */
778 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
779 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
780 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
781 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
782 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
783 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
784
785 pm4 = si_get_shader_pm4_state(shader);
786 if (!pm4)
787 return;
788
789 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
790 * Possible vaules:
791 * 0 -> Position = pixel center
792 * 1 -> Position = pixel centroid
793 * 2 -> Position = at sample position
794 *
795 * From GLSL 4.5 specification, section 7.1:
796 * "The variable gl_FragCoord is available as an input variable from
797 * within fragment shaders and it holds the window relative coordinates
798 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
799 * value can be for any location within the pixel, or one of the
800 * fragment samples. The use of centroid does not further restrict
801 * this value to be inside the current primitive."
802 *
803 * Meaning that centroid has no effect and we can return anything within
804 * the pixel. Thus, return the value at sample position, because that's
805 * the most accurate one shaders can get.
806 */
807 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
808
809 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
810 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
811 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
812
813 spi_shader_col_format = si_get_spi_shader_col_format(shader);
814 cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
815
816 /* Ensure that some export memory is always allocated, for two reasons:
817 *
818 * 1) Correctness: The hardware ignores the EXEC mask if no export
819 * memory is allocated, so KILL and alpha test do not work correctly
820 * without this.
821 * 2) Performance: Every shader needs at least a NULL export, even when
822 * it writes no color/depth output. The NULL export instruction
823 * stalls without this setting.
824 *
825 * Don't add this to CB_SHADER_MASK.
826 */
827 if (!spi_shader_col_format &&
828 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
829 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
830
831 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
832 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
833 shader->config.spi_ps_input_addr);
834
835 /* Set interpolation controls. */
836 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
837
838 /* Set registers. */
839 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
840 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
841
842 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
843 si_get_spi_shader_z_format(info->writes_z,
844 info->writes_stencil,
845 info->writes_samplemask));
846
847 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
848 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
849
850 va = shader->bo->gpu_address;
851 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
852 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
853 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
854
855 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
856 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
857 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
858 S_00B028_DX10_CLAMP(1) |
859 S_00B028_FLOAT_MODE(shader->config.float_mode));
860 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
861 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
862 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
863 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
864 }
865
866 static void si_shader_init_pm4_state(struct si_screen *sscreen,
867 struct si_shader *shader)
868 {
869 switch (shader->selector->type) {
870 case PIPE_SHADER_VERTEX:
871 if (shader->key.as_ls)
872 si_shader_ls(shader);
873 else if (shader->key.as_es)
874 si_shader_es(sscreen, shader);
875 else
876 si_shader_vs(sscreen, shader, NULL);
877 break;
878 case PIPE_SHADER_TESS_CTRL:
879 si_shader_hs(shader);
880 break;
881 case PIPE_SHADER_TESS_EVAL:
882 if (shader->key.as_es)
883 si_shader_es(sscreen, shader);
884 else
885 si_shader_vs(sscreen, shader, NULL);
886 break;
887 case PIPE_SHADER_GEOMETRY:
888 si_shader_gs(shader);
889 break;
890 case PIPE_SHADER_FRAGMENT:
891 si_shader_ps(shader);
892 break;
893 default:
894 assert(0);
895 }
896 }
897
898 static unsigned si_get_alpha_test_func(struct si_context *sctx)
899 {
900 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
901 if (sctx->queued.named.dsa)
902 return sctx->queued.named.dsa->alpha_func;
903
904 return PIPE_FUNC_ALWAYS;
905 }
906
907 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
908 struct si_shader_selector *vs,
909 struct si_shader_key *key)
910 {
911 struct si_shader_selector *ps = sctx->ps_shader.cso;
912
913 key->opt.hw_vs.clip_disable =
914 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
915 (vs->info.clipdist_writemask ||
916 vs->info.writes_clipvertex) &&
917 !vs->info.culldist_writemask;
918
919 /* Find out if PS is disabled. */
920 bool ps_disabled = true;
921 if (ps) {
922 bool ps_modifies_zs = ps->info.uses_kill ||
923 ps->info.writes_z ||
924 ps->info.writes_stencil ||
925 ps->info.writes_samplemask ||
926 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
927
928 unsigned ps_colormask = sctx->framebuffer.colorbuf_enabled_4bit &
929 sctx->queued.named.blend->cb_target_mask;
930 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
931 ps_colormask &= ps->colors_written_4bit;
932
933 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
934 (!ps_colormask &&
935 !ps_modifies_zs &&
936 !ps->info.writes_memory);
937 }
938
939 /* Find out which VS outputs aren't used by the PS. */
940 uint64_t outputs_written = vs->outputs_written;
941 uint32_t outputs_written2 = vs->outputs_written2;
942 uint64_t inputs_read = 0;
943 uint32_t inputs_read2 = 0;
944
945 outputs_written &= ~0x3; /* ignore POSITION, PSIZE */
946
947 if (!ps_disabled) {
948 inputs_read = ps->inputs_read;
949 inputs_read2 = ps->inputs_read2;
950 }
951
952 uint64_t linked = outputs_written & inputs_read;
953 uint32_t linked2 = outputs_written2 & inputs_read2;
954
955 key->opt.hw_vs.kill_outputs = ~linked & outputs_written;
956 key->opt.hw_vs.kill_outputs2 = ~linked2 & outputs_written2;
957 }
958
959 /* Compute the key for the hw shader variant */
960 static inline void si_shader_selector_key(struct pipe_context *ctx,
961 struct si_shader_selector *sel,
962 struct si_shader_key *key)
963 {
964 struct si_context *sctx = (struct si_context *)ctx;
965 unsigned i;
966
967 memset(key, 0, sizeof(*key));
968
969 switch (sel->type) {
970 case PIPE_SHADER_VERTEX:
971 if (sctx->vertex_elements) {
972 unsigned count = MIN2(sel->info.num_inputs,
973 sctx->vertex_elements->count);
974 for (i = 0; i < count; ++i)
975 key->part.vs.prolog.instance_divisors[i] =
976 sctx->vertex_elements->elements[i].instance_divisor;
977
978 memcpy(key->mono.vs.fix_fetch,
979 sctx->vertex_elements->fix_fetch, count);
980 }
981 if (sctx->tes_shader.cso)
982 key->as_ls = 1;
983 else if (sctx->gs_shader.cso)
984 key->as_es = 1;
985 else {
986 si_shader_selector_key_hw_vs(sctx, sel, key);
987
988 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
989 key->part.vs.epilog.export_prim_id = 1;
990 }
991 break;
992 case PIPE_SHADER_TESS_CTRL:
993 key->part.tcs.epilog.prim_mode =
994 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
995
996 if (sel == sctx->fixed_func_tcs_shader.cso)
997 key->mono.tcs.inputs_to_copy = sctx->vs_shader.cso->outputs_written;
998 break;
999 case PIPE_SHADER_TESS_EVAL:
1000 if (sctx->gs_shader.cso)
1001 key->as_es = 1;
1002 else {
1003 si_shader_selector_key_hw_vs(sctx, sel, key);
1004
1005 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1006 key->part.tes.epilog.export_prim_id = 1;
1007 }
1008 break;
1009 case PIPE_SHADER_GEOMETRY:
1010 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1011 break;
1012 case PIPE_SHADER_FRAGMENT: {
1013 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1014 struct si_state_blend *blend = sctx->queued.named.blend;
1015
1016 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1017 sel->info.colors_written == 0x1)
1018 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1019
1020 if (blend) {
1021 /* Select the shader color format based on whether
1022 * blending or alpha are needed.
1023 */
1024 key->part.ps.epilog.spi_shader_col_format =
1025 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1026 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1027 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1028 sctx->framebuffer.spi_shader_col_format_blend) |
1029 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1030 sctx->framebuffer.spi_shader_col_format_alpha) |
1031 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1032 sctx->framebuffer.spi_shader_col_format);
1033
1034 /* The output for dual source blending should have
1035 * the same format as the first output.
1036 */
1037 if (blend->dual_src_blend)
1038 key->part.ps.epilog.spi_shader_col_format |=
1039 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1040 } else
1041 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1042
1043 /* If alpha-to-coverage is enabled, we have to export alpha
1044 * even if there is no color buffer.
1045 */
1046 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1047 blend && blend->alpha_to_coverage)
1048 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1049
1050 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1051 * to the range supported by the type if a channel has less
1052 * than 16 bits and the export format is 16_ABGR.
1053 */
1054 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII)
1055 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1056
1057 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1058 if (!key->part.ps.epilog.last_cbuf) {
1059 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1060 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1061 }
1062
1063 if (rs) {
1064 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
1065 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
1066 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
1067 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
1068
1069 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1070 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1071
1072 if (sctx->queued.named.blend) {
1073 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1074 rs->multisample_enable;
1075 }
1076
1077 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1078 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1079 (is_line && rs->line_smooth)) &&
1080 sctx->framebuffer.nr_samples <= 1;
1081 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1082
1083 if (rs->force_persample_interp &&
1084 rs->multisample_enable &&
1085 sctx->framebuffer.nr_samples > 1 &&
1086 sctx->ps_iter_samples > 1) {
1087 key->part.ps.prolog.force_persp_sample_interp =
1088 sel->info.uses_persp_center ||
1089 sel->info.uses_persp_centroid;
1090
1091 key->part.ps.prolog.force_linear_sample_interp =
1092 sel->info.uses_linear_center ||
1093 sel->info.uses_linear_centroid;
1094 } else if (rs->multisample_enable &&
1095 sctx->framebuffer.nr_samples > 1) {
1096 key->part.ps.prolog.bc_optimize_for_persp =
1097 sel->info.uses_persp_center &&
1098 sel->info.uses_persp_centroid;
1099 key->part.ps.prolog.bc_optimize_for_linear =
1100 sel->info.uses_linear_center &&
1101 sel->info.uses_linear_centroid;
1102 } else {
1103 /* Make sure SPI doesn't compute more than 1 pair
1104 * of (i,j), which is the optimization here. */
1105 key->part.ps.prolog.force_persp_center_interp =
1106 sel->info.uses_persp_center +
1107 sel->info.uses_persp_centroid +
1108 sel->info.uses_persp_sample > 1;
1109
1110 key->part.ps.prolog.force_linear_center_interp =
1111 sel->info.uses_linear_center +
1112 sel->info.uses_linear_centroid +
1113 sel->info.uses_linear_sample > 1;
1114 }
1115 }
1116
1117 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1118 break;
1119 }
1120 default:
1121 assert(0);
1122 }
1123 }
1124
1125 static void si_build_shader_variant(void *job, int thread_index)
1126 {
1127 struct si_shader *shader = (struct si_shader *)job;
1128 struct si_shader_selector *sel = shader->selector;
1129 struct si_screen *sscreen = sel->screen;
1130 LLVMTargetMachineRef tm;
1131 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1132 int r;
1133
1134 if (thread_index >= 0) {
1135 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1136 tm = sscreen->tm[thread_index];
1137 if (!debug->async)
1138 debug = NULL;
1139 } else {
1140 tm = shader->compiler_ctx_state.tm;
1141 }
1142
1143 r = si_shader_create(sscreen, tm, shader, debug);
1144 if (unlikely(r)) {
1145 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1146 sel->type, r);
1147 shader->compilation_failed = true;
1148 return;
1149 }
1150
1151 if (shader->compiler_ctx_state.is_debug_context) {
1152 FILE *f = open_memstream(&shader->shader_log,
1153 &shader->shader_log_size);
1154 if (f) {
1155 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1156 fclose(f);
1157 }
1158 }
1159
1160 si_shader_init_pm4_state(sscreen, shader);
1161 }
1162
1163 /* Select the hw shader variant depending on the current state. */
1164 static int si_shader_select_with_key(struct si_screen *sscreen,
1165 struct si_shader_ctx_state *state,
1166 struct si_compiler_ctx_state *compiler_state,
1167 struct si_shader_key *key,
1168 int thread_index)
1169 {
1170 static const struct si_shader_key zeroed;
1171 struct si_shader_selector *sel = state->cso;
1172 struct si_shader *current = state->current;
1173 struct si_shader *iter, *shader = NULL;
1174
1175 if (unlikely(sscreen->b.debug_flags & DBG_NO_OPT_VARIANT)) {
1176 memset(&key->opt, 0, sizeof(key->opt));
1177 }
1178
1179 again:
1180 /* Check if we don't need to change anything.
1181 * This path is also used for most shaders that don't need multiple
1182 * variants, it will cost just a computation of the key and this
1183 * test. */
1184 if (likely(current &&
1185 memcmp(&current->key, key, sizeof(*key)) == 0 &&
1186 (!current->is_optimized ||
1187 util_queue_fence_is_signalled(&current->optimized_ready))))
1188 return 0;
1189
1190 /* This must be done before the mutex is locked, because async GS
1191 * compilation calls this function too, and therefore must enter
1192 * the mutex first.
1193 *
1194 * Only wait if we are in a draw call. Don't wait if we are
1195 * in a compiler thread.
1196 */
1197 if (thread_index < 0)
1198 util_queue_job_wait(&sel->ready);
1199
1200 pipe_mutex_lock(sel->mutex);
1201
1202 /* Find the shader variant. */
1203 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1204 /* Don't check the "current" shader. We checked it above. */
1205 if (current != iter &&
1206 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1207 /* If it's an optimized shader and its compilation has
1208 * been started but isn't done, use the unoptimized
1209 * shader so as not to cause a stall due to compilation.
1210 */
1211 if (iter->is_optimized &&
1212 !util_queue_fence_is_signalled(&iter->optimized_ready)) {
1213 memset(&key->opt, 0, sizeof(key->opt));
1214 pipe_mutex_unlock(sel->mutex);
1215 goto again;
1216 }
1217
1218 if (iter->compilation_failed) {
1219 pipe_mutex_unlock(sel->mutex);
1220 return -1; /* skip the draw call */
1221 }
1222
1223 state->current = iter;
1224 pipe_mutex_unlock(sel->mutex);
1225 return 0;
1226 }
1227 }
1228
1229 /* Build a new shader. */
1230 shader = CALLOC_STRUCT(si_shader);
1231 if (!shader) {
1232 pipe_mutex_unlock(sel->mutex);
1233 return -ENOMEM;
1234 }
1235 shader->selector = sel;
1236 shader->key = *key;
1237 shader->compiler_ctx_state = *compiler_state;
1238
1239 bool is_pure_monolithic =
1240 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1241
1242 /* Monolithic-only shaders don't make a distinction between optimized
1243 * and unoptimized. */
1244 shader->is_monolithic =
1245 !sel->main_shader_part ||
1246 sel->main_shader_part->key.as_ls != key->as_ls ||
1247 sel->main_shader_part->key.as_es != key->as_es ||
1248 is_pure_monolithic ||
1249 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1250
1251 shader->is_optimized =
1252 !sscreen->use_monolithic_shaders &&
1253 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1254 if (shader->is_optimized)
1255 util_queue_fence_init(&shader->optimized_ready);
1256
1257 if (!sel->last_variant) {
1258 sel->first_variant = shader;
1259 sel->last_variant = shader;
1260 } else {
1261 sel->last_variant->next_variant = shader;
1262 sel->last_variant = shader;
1263 }
1264
1265 /* If it's an optimized shader, compile it asynchronously. */
1266 if (shader->is_optimized &&
1267 !is_pure_monolithic &&
1268 thread_index < 0) {
1269 /* Compile it asynchronously. */
1270 util_queue_add_job(&sscreen->shader_compiler_queue,
1271 shader, &shader->optimized_ready,
1272 si_build_shader_variant, NULL);
1273
1274 /* Use the default (unoptimized) shader for now. */
1275 memset(&key->opt, 0, sizeof(key->opt));
1276 pipe_mutex_unlock(sel->mutex);
1277 goto again;
1278 }
1279
1280 assert(!shader->is_optimized);
1281 si_build_shader_variant(shader, thread_index);
1282
1283 if (!shader->compilation_failed)
1284 state->current = shader;
1285
1286 pipe_mutex_unlock(sel->mutex);
1287 return shader->compilation_failed ? -1 : 0;
1288 }
1289
1290 static int si_shader_select(struct pipe_context *ctx,
1291 struct si_shader_ctx_state *state,
1292 struct si_compiler_ctx_state *compiler_state)
1293 {
1294 struct si_context *sctx = (struct si_context *)ctx;
1295 struct si_shader_key key;
1296
1297 si_shader_selector_key(ctx, state->cso, &key);
1298 return si_shader_select_with_key(sctx->screen, state, compiler_state,
1299 &key, -1);
1300 }
1301
1302 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1303 struct si_shader_key *key)
1304 {
1305 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1306
1307 switch (info->processor) {
1308 case PIPE_SHADER_VERTEX:
1309 switch (next_shader) {
1310 case PIPE_SHADER_GEOMETRY:
1311 key->as_es = 1;
1312 break;
1313 case PIPE_SHADER_TESS_CTRL:
1314 case PIPE_SHADER_TESS_EVAL:
1315 key->as_ls = 1;
1316 break;
1317 default:
1318 /* If POSITION isn't written, it can't be a HW VS.
1319 * Assume that it's a HW LS. (the next shader is TCS)
1320 * This heuristic is needed for separate shader objects.
1321 */
1322 if (!info->writes_position)
1323 key->as_ls = 1;
1324 }
1325 break;
1326
1327 case PIPE_SHADER_TESS_EVAL:
1328 if (next_shader == PIPE_SHADER_GEOMETRY ||
1329 !info->writes_position)
1330 key->as_es = 1;
1331 break;
1332 }
1333 }
1334
1335 /**
1336 * Compile the main shader part or the monolithic shader as part of
1337 * si_shader_selector initialization. Since it can be done asynchronously,
1338 * there is no way to report compile failures to applications.
1339 */
1340 void si_init_shader_selector_async(void *job, int thread_index)
1341 {
1342 struct si_shader_selector *sel = (struct si_shader_selector *)job;
1343 struct si_screen *sscreen = sel->screen;
1344 LLVMTargetMachineRef tm;
1345 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
1346 unsigned i;
1347
1348 if (thread_index >= 0) {
1349 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1350 tm = sscreen->tm[thread_index];
1351 if (!debug->async)
1352 debug = NULL;
1353 } else {
1354 tm = sel->compiler_ctx_state.tm;
1355 }
1356
1357 /* Compile the main shader part for use with a prolog and/or epilog.
1358 * If this fails, the driver will try to compile a monolithic shader
1359 * on demand.
1360 */
1361 if (!sscreen->use_monolithic_shaders) {
1362 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1363 void *tgsi_binary;
1364
1365 if (!shader) {
1366 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
1367 return;
1368 }
1369
1370 shader->selector = sel;
1371 si_parse_next_shader_property(&sel->info, &shader->key);
1372
1373 tgsi_binary = si_get_tgsi_binary(sel);
1374
1375 /* Try to load the shader from the shader cache. */
1376 pipe_mutex_lock(sscreen->shader_cache_mutex);
1377
1378 if (tgsi_binary &&
1379 si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
1380 FREE(tgsi_binary);
1381 pipe_mutex_unlock(sscreen->shader_cache_mutex);
1382 } else {
1383 pipe_mutex_unlock(sscreen->shader_cache_mutex);
1384
1385 /* Compile the shader if it hasn't been loaded from the cache. */
1386 if (si_compile_tgsi_shader(sscreen, tm, shader, false,
1387 debug) != 0) {
1388 FREE(shader);
1389 FREE(tgsi_binary);
1390 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
1391 return;
1392 }
1393
1394 if (tgsi_binary) {
1395 pipe_mutex_lock(sscreen->shader_cache_mutex);
1396 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary, shader))
1397 FREE(tgsi_binary);
1398 pipe_mutex_unlock(sscreen->shader_cache_mutex);
1399 }
1400 }
1401
1402 sel->main_shader_part = shader;
1403
1404 /* Unset "outputs_written" flags for outputs converted to
1405 * DEFAULT_VAL, so that later inter-shader optimizations don't
1406 * try to eliminate outputs that don't exist in the final
1407 * shader.
1408 *
1409 * This is only done if non-monolithic shaders are enabled.
1410 */
1411 if ((sel->type == PIPE_SHADER_VERTEX ||
1412 sel->type == PIPE_SHADER_TESS_EVAL) &&
1413 !shader->key.as_ls &&
1414 !shader->key.as_es) {
1415 unsigned i;
1416
1417 for (i = 0; i < sel->info.num_outputs; i++) {
1418 unsigned offset = shader->info.vs_output_param_offset[i];
1419
1420 if (offset <= EXP_PARAM_OFFSET_31)
1421 continue;
1422
1423 unsigned name = sel->info.output_semantic_name[i];
1424 unsigned index = sel->info.output_semantic_index[i];
1425 unsigned id;
1426
1427 switch (name) {
1428 case TGSI_SEMANTIC_GENERIC:
1429 /* don't process indices the function can't handle */
1430 if (index >= 60)
1431 break;
1432 /* fall through */
1433 case TGSI_SEMANTIC_CLIPDIST:
1434 id = si_shader_io_get_unique_index(name, index);
1435 sel->outputs_written &= ~(1ull << id);
1436 break;
1437 case TGSI_SEMANTIC_POSITION: /* ignore these */
1438 case TGSI_SEMANTIC_PSIZE:
1439 case TGSI_SEMANTIC_CLIPVERTEX:
1440 case TGSI_SEMANTIC_EDGEFLAG:
1441 break;
1442 default:
1443 id = si_shader_io_get_unique_index2(name, index);
1444 sel->outputs_written2 &= ~(1u << id);
1445 }
1446 }
1447 }
1448 }
1449
1450 /* Pre-compilation. */
1451 if (sscreen->b.debug_flags & DBG_PRECOMPILE) {
1452 struct si_shader_ctx_state state = {sel};
1453 struct si_shader_key key;
1454
1455 memset(&key, 0, sizeof(key));
1456 si_parse_next_shader_property(&sel->info, &key);
1457
1458 /* Set reasonable defaults, so that the shader key doesn't
1459 * cause any code to be eliminated.
1460 */
1461 switch (sel->type) {
1462 case PIPE_SHADER_TESS_CTRL:
1463 key.part.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
1464 break;
1465 case PIPE_SHADER_FRAGMENT:
1466 key.part.ps.prolog.bc_optimize_for_persp =
1467 sel->info.uses_persp_center &&
1468 sel->info.uses_persp_centroid;
1469 key.part.ps.prolog.bc_optimize_for_linear =
1470 sel->info.uses_linear_center &&
1471 sel->info.uses_linear_centroid;
1472 key.part.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
1473 for (i = 0; i < 8; i++)
1474 if (sel->info.colors_written & (1 << i))
1475 key.part.ps.epilog.spi_shader_col_format |=
1476 V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
1477 break;
1478 }
1479
1480 if (si_shader_select_with_key(sscreen, &state,
1481 &sel->compiler_ctx_state, &key,
1482 thread_index))
1483 fprintf(stderr, "radeonsi: can't create a monolithic shader\n");
1484 }
1485
1486 /* The GS copy shader is always pre-compiled. */
1487 if (sel->type == PIPE_SHADER_GEOMETRY) {
1488 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, tm, sel, debug);
1489 if (!sel->gs_copy_shader) {
1490 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
1491 return;
1492 }
1493
1494 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
1495 }
1496 }
1497
1498 static void *si_create_shader_selector(struct pipe_context *ctx,
1499 const struct pipe_shader_state *state)
1500 {
1501 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
1502 struct si_context *sctx = (struct si_context*)ctx;
1503 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
1504 int i;
1505
1506 if (!sel)
1507 return NULL;
1508
1509 sel->screen = sscreen;
1510 sel->compiler_ctx_state.tm = sctx->tm;
1511 sel->compiler_ctx_state.debug = sctx->b.debug;
1512 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
1513 sel->tokens = tgsi_dup_tokens(state->tokens);
1514 if (!sel->tokens) {
1515 FREE(sel);
1516 return NULL;
1517 }
1518
1519 sel->so = state->stream_output;
1520 tgsi_scan_shader(state->tokens, &sel->info);
1521 sel->type = sel->info.processor;
1522 p_atomic_inc(&sscreen->b.num_shaders_created);
1523
1524 /* Set which opcode uses which (i,j) pair. */
1525 if (sel->info.uses_persp_opcode_interp_centroid)
1526 sel->info.uses_persp_centroid = true;
1527
1528 if (sel->info.uses_linear_opcode_interp_centroid)
1529 sel->info.uses_linear_centroid = true;
1530
1531 if (sel->info.uses_persp_opcode_interp_offset ||
1532 sel->info.uses_persp_opcode_interp_sample)
1533 sel->info.uses_persp_center = true;
1534
1535 if (sel->info.uses_linear_opcode_interp_offset ||
1536 sel->info.uses_linear_opcode_interp_sample)
1537 sel->info.uses_linear_center = true;
1538
1539 switch (sel->type) {
1540 case PIPE_SHADER_GEOMETRY:
1541 sel->gs_output_prim =
1542 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
1543 sel->gs_max_out_vertices =
1544 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
1545 sel->gs_num_invocations =
1546 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
1547 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
1548 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
1549 sel->gs_max_out_vertices;
1550
1551 sel->max_gs_stream = 0;
1552 for (i = 0; i < sel->so.num_outputs; i++)
1553 sel->max_gs_stream = MAX2(sel->max_gs_stream,
1554 sel->so.output[i].stream);
1555
1556 sel->gs_input_verts_per_prim =
1557 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
1558 break;
1559
1560 case PIPE_SHADER_TESS_CTRL:
1561 /* Always reserve space for these. */
1562 sel->patch_outputs_written |=
1563 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0)) |
1564 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0));
1565 /* fall through */
1566 case PIPE_SHADER_VERTEX:
1567 case PIPE_SHADER_TESS_EVAL:
1568 for (i = 0; i < sel->info.num_outputs; i++) {
1569 unsigned name = sel->info.output_semantic_name[i];
1570 unsigned index = sel->info.output_semantic_index[i];
1571
1572 switch (name) {
1573 case TGSI_SEMANTIC_TESSINNER:
1574 case TGSI_SEMANTIC_TESSOUTER:
1575 case TGSI_SEMANTIC_PATCH:
1576 sel->patch_outputs_written |=
1577 1llu << si_shader_io_get_unique_index(name, index);
1578 break;
1579
1580 case TGSI_SEMANTIC_GENERIC:
1581 /* don't process indices the function can't handle */
1582 if (index >= 60)
1583 break;
1584 /* fall through */
1585 case TGSI_SEMANTIC_POSITION:
1586 case TGSI_SEMANTIC_PSIZE:
1587 case TGSI_SEMANTIC_CLIPDIST:
1588 sel->outputs_written |=
1589 1llu << si_shader_io_get_unique_index(name, index);
1590 break;
1591 case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */
1592 case TGSI_SEMANTIC_EDGEFLAG:
1593 break;
1594 default:
1595 sel->outputs_written2 |=
1596 1u << si_shader_io_get_unique_index2(name, index);
1597 }
1598 }
1599 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
1600 break;
1601
1602 case PIPE_SHADER_FRAGMENT:
1603 for (i = 0; i < sel->info.num_inputs; i++) {
1604 unsigned name = sel->info.input_semantic_name[i];
1605 unsigned index = sel->info.input_semantic_index[i];
1606
1607 switch (name) {
1608 case TGSI_SEMANTIC_CLIPDIST:
1609 case TGSI_SEMANTIC_GENERIC:
1610 sel->inputs_read |=
1611 1llu << si_shader_io_get_unique_index(name, index);
1612 break;
1613 case TGSI_SEMANTIC_PCOORD: /* ignore this */
1614 break;
1615 default:
1616 sel->inputs_read2 |=
1617 1u << si_shader_io_get_unique_index2(name, index);
1618 }
1619 }
1620
1621 for (i = 0; i < 8; i++)
1622 if (sel->info.colors_written & (1 << i))
1623 sel->colors_written_4bit |= 0xf << (4 * i);
1624
1625 for (i = 0; i < sel->info.num_inputs; i++) {
1626 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
1627 int index = sel->info.input_semantic_index[i];
1628 sel->color_attr_index[index] = i;
1629 }
1630 }
1631 break;
1632 }
1633
1634 /* DB_SHADER_CONTROL */
1635 sel->db_shader_control =
1636 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
1637 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
1638 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
1639 S_02880C_KILL_ENABLE(sel->info.uses_kill);
1640
1641 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
1642 case TGSI_FS_DEPTH_LAYOUT_GREATER:
1643 sel->db_shader_control |=
1644 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
1645 break;
1646 case TGSI_FS_DEPTH_LAYOUT_LESS:
1647 sel->db_shader_control |=
1648 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
1649 break;
1650 }
1651
1652 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
1653 *
1654 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
1655 * --|-----------|------------|------------|--------------------|-------------------|-------------
1656 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
1657 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
1658 * 2 | false | true | n/a | LateZ | 1 | 0
1659 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
1660 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
1661 *
1662 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
1663 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
1664 *
1665 * Don't use ReZ without profiling !!!
1666 *
1667 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
1668 * shaders.
1669 */
1670 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
1671 /* Cases 3, 4. */
1672 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
1673 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
1674 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
1675 } else if (sel->info.writes_memory) {
1676 /* Case 2. */
1677 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
1678 S_02880C_EXEC_ON_HIER_FAIL(1);
1679 } else {
1680 /* Case 1. */
1681 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
1682 }
1683
1684 pipe_mutex_init(sel->mutex);
1685 util_queue_fence_init(&sel->ready);
1686
1687 if ((sctx->b.debug.debug_message && !sctx->b.debug.async) ||
1688 sctx->is_debug ||
1689 r600_can_dump_shader(&sscreen->b, sel->info.processor) ||
1690 !util_queue_is_initialized(&sscreen->shader_compiler_queue))
1691 si_init_shader_selector_async(sel, -1);
1692 else
1693 util_queue_add_job(&sscreen->shader_compiler_queue, sel,
1694 &sel->ready, si_init_shader_selector_async,
1695 NULL);
1696
1697 return sel;
1698 }
1699
1700 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
1701 {
1702 struct si_context *sctx = (struct si_context *)ctx;
1703 struct si_shader_selector *sel = state;
1704
1705 if (sctx->vs_shader.cso == sel)
1706 return;
1707
1708 sctx->vs_shader.cso = sel;
1709 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
1710 sctx->do_update_shaders = true;
1711 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1712 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1713 }
1714
1715 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
1716 {
1717 struct si_context *sctx = (struct si_context *)ctx;
1718 struct si_shader_selector *sel = state;
1719 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
1720
1721 if (sctx->gs_shader.cso == sel)
1722 return;
1723
1724 sctx->gs_shader.cso = sel;
1725 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
1726 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
1727 sctx->do_update_shaders = true;
1728 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1729 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1730
1731 if (enable_changed)
1732 si_shader_change_notify(sctx);
1733 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1734 }
1735
1736 static void si_update_tcs_tes_uses_prim_id(struct si_context *sctx)
1737 {
1738 sctx->ia_multi_vgt_param_key.u.tcs_tes_uses_prim_id =
1739 (sctx->tes_shader.cso &&
1740 sctx->tes_shader.cso->info.uses_primid) ||
1741 (sctx->tcs_shader.cso &&
1742 sctx->tcs_shader.cso->info.uses_primid);
1743 }
1744
1745 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
1746 {
1747 struct si_context *sctx = (struct si_context *)ctx;
1748 struct si_shader_selector *sel = state;
1749 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
1750
1751 if (sctx->tcs_shader.cso == sel)
1752 return;
1753
1754 sctx->tcs_shader.cso = sel;
1755 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
1756 si_update_tcs_tes_uses_prim_id(sctx);
1757 sctx->do_update_shaders = true;
1758
1759 if (enable_changed)
1760 sctx->last_tcs = NULL; /* invalidate derived tess state */
1761 }
1762
1763 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
1764 {
1765 struct si_context *sctx = (struct si_context *)ctx;
1766 struct si_shader_selector *sel = state;
1767 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
1768
1769 if (sctx->tes_shader.cso == sel)
1770 return;
1771
1772 sctx->tes_shader.cso = sel;
1773 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
1774 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
1775 si_update_tcs_tes_uses_prim_id(sctx);
1776 sctx->do_update_shaders = true;
1777 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1778 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1779
1780 if (enable_changed) {
1781 si_shader_change_notify(sctx);
1782 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
1783 }
1784 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1785 }
1786
1787 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
1788 {
1789 struct si_context *sctx = (struct si_context *)ctx;
1790 struct si_shader_selector *sel = state;
1791
1792 /* skip if supplied shader is one already in use */
1793 if (sctx->ps_shader.cso == sel)
1794 return;
1795
1796 sctx->ps_shader.cso = sel;
1797 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
1798 sctx->do_update_shaders = true;
1799 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
1800 }
1801
1802 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
1803 {
1804 if (shader->is_optimized) {
1805 util_queue_job_wait(&shader->optimized_ready);
1806 util_queue_fence_destroy(&shader->optimized_ready);
1807 }
1808
1809 if (shader->pm4) {
1810 switch (shader->selector->type) {
1811 case PIPE_SHADER_VERTEX:
1812 if (shader->key.as_ls)
1813 si_pm4_delete_state(sctx, ls, shader->pm4);
1814 else if (shader->key.as_es)
1815 si_pm4_delete_state(sctx, es, shader->pm4);
1816 else
1817 si_pm4_delete_state(sctx, vs, shader->pm4);
1818 break;
1819 case PIPE_SHADER_TESS_CTRL:
1820 si_pm4_delete_state(sctx, hs, shader->pm4);
1821 break;
1822 case PIPE_SHADER_TESS_EVAL:
1823 if (shader->key.as_es)
1824 si_pm4_delete_state(sctx, es, shader->pm4);
1825 else
1826 si_pm4_delete_state(sctx, vs, shader->pm4);
1827 break;
1828 case PIPE_SHADER_GEOMETRY:
1829 if (shader->is_gs_copy_shader)
1830 si_pm4_delete_state(sctx, vs, shader->pm4);
1831 else
1832 si_pm4_delete_state(sctx, gs, shader->pm4);
1833 break;
1834 case PIPE_SHADER_FRAGMENT:
1835 si_pm4_delete_state(sctx, ps, shader->pm4);
1836 break;
1837 }
1838 }
1839
1840 si_shader_destroy(shader);
1841 free(shader);
1842 }
1843
1844 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
1845 {
1846 struct si_context *sctx = (struct si_context *)ctx;
1847 struct si_shader_selector *sel = (struct si_shader_selector *)state;
1848 struct si_shader *p = sel->first_variant, *c;
1849 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
1850 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
1851 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
1852 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
1853 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
1854 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
1855 };
1856
1857 util_queue_job_wait(&sel->ready);
1858
1859 if (current_shader[sel->type]->cso == sel) {
1860 current_shader[sel->type]->cso = NULL;
1861 current_shader[sel->type]->current = NULL;
1862 }
1863
1864 while (p) {
1865 c = p->next_variant;
1866 si_delete_shader(sctx, p);
1867 p = c;
1868 }
1869
1870 if (sel->main_shader_part)
1871 si_delete_shader(sctx, sel->main_shader_part);
1872 if (sel->gs_copy_shader)
1873 si_delete_shader(sctx, sel->gs_copy_shader);
1874
1875 util_queue_fence_destroy(&sel->ready);
1876 pipe_mutex_destroy(sel->mutex);
1877 free(sel->tokens);
1878 free(sel);
1879 }
1880
1881 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
1882 struct si_shader *vs, unsigned name,
1883 unsigned index, unsigned interpolate)
1884 {
1885 struct tgsi_shader_info *vsinfo = &vs->selector->info;
1886 unsigned j, offset, ps_input_cntl = 0;
1887
1888 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
1889 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
1890 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1891
1892 if (name == TGSI_SEMANTIC_PCOORD ||
1893 (name == TGSI_SEMANTIC_TEXCOORD &&
1894 sctx->sprite_coord_enable & (1 << index))) {
1895 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
1896 }
1897
1898 for (j = 0; j < vsinfo->num_outputs; j++) {
1899 if (name == vsinfo->output_semantic_name[j] &&
1900 index == vsinfo->output_semantic_index[j]) {
1901 offset = vs->info.vs_output_param_offset[j];
1902
1903 if (offset <= EXP_PARAM_OFFSET_31) {
1904 /* The input is loaded from parameter memory. */
1905 ps_input_cntl |= S_028644_OFFSET(offset);
1906 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
1907 if (offset == EXP_PARAM_UNDEFINED) {
1908 /* This can happen with depth-only rendering. */
1909 offset = 0;
1910 } else {
1911 /* The input is a DEFAULT_VAL constant. */
1912 assert(offset >= EXP_PARAM_DEFAULT_VAL_0000 &&
1913 offset <= EXP_PARAM_DEFAULT_VAL_1111);
1914 offset -= EXP_PARAM_DEFAULT_VAL_0000;
1915 }
1916
1917 ps_input_cntl = S_028644_OFFSET(0x20) |
1918 S_028644_DEFAULT_VAL(offset);
1919 }
1920 break;
1921 }
1922 }
1923
1924 if (name == TGSI_SEMANTIC_PRIMID)
1925 /* PrimID is written after the last output. */
1926 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
1927 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
1928 /* No corresponding output found, load defaults into input.
1929 * Don't set any other bits.
1930 * (FLAT_SHADE=1 completely changes behavior) */
1931 ps_input_cntl = S_028644_OFFSET(0x20);
1932 /* D3D 9 behaviour. GL is undefined */
1933 if (name == TGSI_SEMANTIC_COLOR && index == 0)
1934 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
1935 }
1936 return ps_input_cntl;
1937 }
1938
1939 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
1940 {
1941 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1942 struct si_shader *ps = sctx->ps_shader.current;
1943 struct si_shader *vs = si_get_vs_state(sctx);
1944 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
1945 unsigned i, num_interp, num_written = 0, bcol_interp[2];
1946
1947 if (!ps || !ps->selector->info.num_inputs)
1948 return;
1949
1950 num_interp = si_get_ps_num_interp(ps);
1951 assert(num_interp > 0);
1952 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
1953
1954 for (i = 0; i < psinfo->num_inputs; i++) {
1955 unsigned name = psinfo->input_semantic_name[i];
1956 unsigned index = psinfo->input_semantic_index[i];
1957 unsigned interpolate = psinfo->input_interpolate[i];
1958
1959 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
1960 interpolate));
1961 num_written++;
1962
1963 if (name == TGSI_SEMANTIC_COLOR) {
1964 assert(index < ARRAY_SIZE(bcol_interp));
1965 bcol_interp[index] = interpolate;
1966 }
1967 }
1968
1969 if (ps->key.part.ps.prolog.color_two_side) {
1970 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
1971
1972 for (i = 0; i < 2; i++) {
1973 if (!(psinfo->colors_read & (0xf << (i * 4))))
1974 continue;
1975
1976 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
1977 i, bcol_interp[i]));
1978 num_written++;
1979 }
1980 }
1981 assert(num_interp == num_written);
1982 }
1983
1984 /**
1985 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
1986 */
1987 static void si_init_config_add_vgt_flush(struct si_context *sctx)
1988 {
1989 if (sctx->init_config_has_vgt_flush)
1990 return;
1991
1992 /* Done by Vulkan before VGT_FLUSH. */
1993 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
1994 si_pm4_cmd_add(sctx->init_config,
1995 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1996 si_pm4_cmd_end(sctx->init_config, false);
1997
1998 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
1999 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2000 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2001 si_pm4_cmd_end(sctx->init_config, false);
2002 sctx->init_config_has_vgt_flush = true;
2003 }
2004
2005 /* Initialize state related to ESGS / GSVS ring buffers */
2006 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2007 {
2008 struct si_shader_selector *es =
2009 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2010 struct si_shader_selector *gs = sctx->gs_shader.cso;
2011 struct si_pm4_state *pm4;
2012
2013 /* Chip constants. */
2014 unsigned num_se = sctx->screen->b.info.max_se;
2015 unsigned wave_size = 64;
2016 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2017 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
2018 unsigned alignment = 256 * num_se;
2019 /* The maximum size is 63.999 MB per SE. */
2020 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2021
2022 /* Calculate the minimum size. */
2023 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
2024 wave_size, alignment);
2025
2026 /* These are recommended sizes, not minimum sizes. */
2027 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2028 es->esgs_itemsize * gs->gs_input_verts_per_prim;
2029 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2030 gs->max_gsvs_emit_size;
2031
2032 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2033 esgs_ring_size = align(esgs_ring_size, alignment);
2034 gsvs_ring_size = align(gsvs_ring_size, alignment);
2035
2036 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2037 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2038
2039 /* Some rings don't have to be allocated if shaders don't use them.
2040 * (e.g. no varyings between ES and GS or GS and VS)
2041 */
2042 bool update_esgs = esgs_ring_size &&
2043 (!sctx->esgs_ring ||
2044 sctx->esgs_ring->width0 < esgs_ring_size);
2045 bool update_gsvs = gsvs_ring_size &&
2046 (!sctx->gsvs_ring ||
2047 sctx->gsvs_ring->width0 < gsvs_ring_size);
2048
2049 if (!update_esgs && !update_gsvs)
2050 return true;
2051
2052 if (update_esgs) {
2053 pipe_resource_reference(&sctx->esgs_ring, NULL);
2054 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, 0,
2055 PIPE_USAGE_DEFAULT,
2056 esgs_ring_size);
2057 if (!sctx->esgs_ring)
2058 return false;
2059 }
2060
2061 if (update_gsvs) {
2062 pipe_resource_reference(&sctx->gsvs_ring, NULL);
2063 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, 0,
2064 PIPE_USAGE_DEFAULT,
2065 gsvs_ring_size);
2066 if (!sctx->gsvs_ring)
2067 return false;
2068 }
2069
2070 /* Create the "init_config_gs_rings" state. */
2071 pm4 = CALLOC_STRUCT(si_pm4_state);
2072 if (!pm4)
2073 return false;
2074
2075 if (sctx->b.chip_class >= CIK) {
2076 if (sctx->esgs_ring)
2077 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2078 sctx->esgs_ring->width0 / 256);
2079 if (sctx->gsvs_ring)
2080 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2081 sctx->gsvs_ring->width0 / 256);
2082 } else {
2083 if (sctx->esgs_ring)
2084 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2085 sctx->esgs_ring->width0 / 256);
2086 if (sctx->gsvs_ring)
2087 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2088 sctx->gsvs_ring->width0 / 256);
2089 }
2090
2091 /* Set the state. */
2092 if (sctx->init_config_gs_rings)
2093 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
2094 sctx->init_config_gs_rings = pm4;
2095
2096 if (!sctx->init_config_has_vgt_flush) {
2097 si_init_config_add_vgt_flush(sctx);
2098 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2099 }
2100
2101 /* Flush the context to re-emit both init_config states. */
2102 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2103 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2104
2105 /* Set ring bindings. */
2106 if (sctx->esgs_ring) {
2107 si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
2108 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2109 true, true, 4, 64, 0);
2110 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
2111 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2112 false, false, 0, 0, 0);
2113 }
2114 if (sctx->gsvs_ring) {
2115 si_set_ring_buffer(&sctx->b.b, SI_RING_GSVS,
2116 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
2117 false, false, 0, 0, 0);
2118 }
2119
2120 return true;
2121 }
2122
2123 /**
2124 * @returns 1 if \p sel has been updated to use a new scratch buffer
2125 * 0 if not
2126 * < 0 if there was a failure
2127 */
2128 static int si_update_scratch_buffer(struct si_context *sctx,
2129 struct si_shader *shader)
2130 {
2131 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
2132 int r;
2133
2134 if (!shader)
2135 return 0;
2136
2137 /* This shader doesn't need a scratch buffer */
2138 if (shader->config.scratch_bytes_per_wave == 0)
2139 return 0;
2140
2141 /* This shader is already configured to use the current
2142 * scratch buffer. */
2143 if (shader->scratch_bo == sctx->scratch_buffer)
2144 return 0;
2145
2146 assert(sctx->scratch_buffer);
2147
2148 si_shader_apply_scratch_relocs(sctx, shader, &shader->config, scratch_va);
2149
2150 /* Replace the shader bo with a new bo that has the relocs applied. */
2151 r = si_shader_binary_upload(sctx->screen, shader);
2152 if (r)
2153 return r;
2154
2155 /* Update the shader state to use the new shader bo. */
2156 si_shader_init_pm4_state(sctx->screen, shader);
2157
2158 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
2159
2160 return 1;
2161 }
2162
2163 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
2164 {
2165 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
2166 }
2167
2168 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
2169 {
2170 return shader ? shader->config.scratch_bytes_per_wave : 0;
2171 }
2172
2173 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
2174 {
2175 unsigned bytes = 0;
2176
2177 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
2178 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
2179 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
2180 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tcs_shader.current));
2181 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
2182 return bytes;
2183 }
2184
2185 static bool si_update_spi_tmpring_size(struct si_context *sctx)
2186 {
2187 unsigned current_scratch_buffer_size =
2188 si_get_current_scratch_buffer_size(sctx);
2189 unsigned scratch_bytes_per_wave =
2190 si_get_max_scratch_bytes_per_wave(sctx);
2191 unsigned scratch_needed_size = scratch_bytes_per_wave *
2192 sctx->scratch_waves;
2193 unsigned spi_tmpring_size;
2194 int r;
2195
2196 if (scratch_needed_size > 0) {
2197 if (scratch_needed_size > current_scratch_buffer_size) {
2198 /* Create a bigger scratch buffer */
2199 r600_resource_reference(&sctx->scratch_buffer, NULL);
2200
2201 sctx->scratch_buffer = (struct r600_resource*)
2202 pipe_buffer_create(&sctx->screen->b.b, 0,
2203 PIPE_USAGE_DEFAULT, scratch_needed_size);
2204 if (!sctx->scratch_buffer)
2205 return false;
2206
2207 si_mark_atom_dirty(sctx, &sctx->scratch_state);
2208 r600_context_add_resource_size(&sctx->b.b,
2209 &sctx->scratch_buffer->b.b);
2210 }
2211
2212 /* Update the shaders, so they are using the latest scratch. The
2213 * scratch buffer may have been changed since these shaders were
2214 * last used, so we still need to try to update them, even if
2215 * they require scratch buffers smaller than the current size.
2216 */
2217 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
2218 if (r < 0)
2219 return false;
2220 if (r == 1)
2221 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2222
2223 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
2224 if (r < 0)
2225 return false;
2226 if (r == 1)
2227 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2228
2229 r = si_update_scratch_buffer(sctx, sctx->tcs_shader.current);
2230 if (r < 0)
2231 return false;
2232 if (r == 1)
2233 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
2234
2235 /* VS can be bound as LS, ES, or VS. */
2236 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
2237 if (r < 0)
2238 return false;
2239 if (r == 1) {
2240 if (sctx->tes_shader.current)
2241 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2242 else if (sctx->gs_shader.current)
2243 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2244 else
2245 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2246 }
2247
2248 /* TES can be bound as ES or VS. */
2249 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
2250 if (r < 0)
2251 return false;
2252 if (r == 1) {
2253 if (sctx->gs_shader.current)
2254 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2255 else
2256 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2257 }
2258 }
2259
2260 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
2261 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
2262 "scratch size should already be aligned correctly.");
2263
2264 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
2265 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
2266 if (spi_tmpring_size != sctx->spi_tmpring_size) {
2267 sctx->spi_tmpring_size = spi_tmpring_size;
2268 si_mark_atom_dirty(sctx, &sctx->scratch_state);
2269 }
2270 return true;
2271 }
2272
2273 static void si_init_tess_factor_ring(struct si_context *sctx)
2274 {
2275 bool double_offchip_buffers = sctx->b.chip_class >= CIK;
2276 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2277 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
2278 sctx->screen->b.info.max_se;
2279 unsigned offchip_granularity;
2280
2281 switch (sctx->screen->tess_offchip_block_dw_size) {
2282 default:
2283 assert(0);
2284 /* fall through */
2285 case 8192:
2286 offchip_granularity = V_03093C_X_8K_DWORDS;
2287 break;
2288 case 4096:
2289 offchip_granularity = V_03093C_X_4K_DWORDS;
2290 break;
2291 }
2292
2293 switch (sctx->b.chip_class) {
2294 case SI:
2295 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2296 break;
2297 case CIK:
2298 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2299 break;
2300 case VI:
2301 default:
2302 max_offchip_buffers = MIN2(max_offchip_buffers, 512);
2303 break;
2304 }
2305
2306 assert(!sctx->tf_ring);
2307 sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, 0,
2308 PIPE_USAGE_DEFAULT,
2309 32768 * sctx->screen->b.info.max_se);
2310 if (!sctx->tf_ring)
2311 return;
2312
2313 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
2314
2315 sctx->tess_offchip_ring = pipe_buffer_create(sctx->b.b.screen, 0,
2316 PIPE_USAGE_DEFAULT,
2317 max_offchip_buffers *
2318 sctx->screen->tess_offchip_block_dw_size * 4);
2319 if (!sctx->tess_offchip_ring)
2320 return;
2321
2322 si_init_config_add_vgt_flush(sctx);
2323
2324 /* Append these registers to the init config state. */
2325 if (sctx->b.chip_class >= CIK) {
2326 if (sctx->b.chip_class >= VI)
2327 --max_offchip_buffers;
2328
2329 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
2330 S_030938_SIZE(sctx->tf_ring->width0 / 4));
2331 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
2332 r600_resource(sctx->tf_ring)->gpu_address >> 8);
2333 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
2334 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2335 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity));
2336 } else {
2337 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
2338 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
2339 S_008988_SIZE(sctx->tf_ring->width0 / 4));
2340 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
2341 r600_resource(sctx->tf_ring)->gpu_address >> 8);
2342 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2343 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers));
2344 }
2345
2346 /* Flush the context to re-emit the init_config state.
2347 * This is done only once in a lifetime of a context.
2348 */
2349 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2350 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2351 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2352
2353 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_FACTOR, sctx->tf_ring,
2354 0, sctx->tf_ring->width0, false, false, 0, 0, 0);
2355
2356 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_OFFCHIP,
2357 sctx->tess_offchip_ring, 0,
2358 sctx->tess_offchip_ring->width0, false, false, 0, 0, 0);
2359 }
2360
2361 /**
2362 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
2363 * VS passes its outputs to TES directly, so the fixed-function shader only
2364 * has to write TESSOUTER and TESSINNER.
2365 */
2366 static void si_generate_fixed_func_tcs(struct si_context *sctx)
2367 {
2368 struct ureg_src outer, inner;
2369 struct ureg_dst tessouter, tessinner;
2370 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
2371
2372 if (!ureg)
2373 return; /* if we get here, we're screwed */
2374
2375 assert(!sctx->fixed_func_tcs_shader.cso);
2376
2377 outer = ureg_DECL_system_value(ureg,
2378 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
2379 inner = ureg_DECL_system_value(ureg,
2380 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
2381
2382 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
2383 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
2384
2385 ureg_MOV(ureg, tessouter, outer);
2386 ureg_MOV(ureg, tessinner, inner);
2387 ureg_END(ureg);
2388
2389 sctx->fixed_func_tcs_shader.cso =
2390 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
2391 }
2392
2393 static void si_update_vgt_shader_config(struct si_context *sctx)
2394 {
2395 /* Calculate the index of the config.
2396 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
2397 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
2398 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
2399
2400 if (!*pm4) {
2401 uint32_t stages = 0;
2402
2403 *pm4 = CALLOC_STRUCT(si_pm4_state);
2404
2405 if (sctx->tes_shader.cso) {
2406 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2407 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2408
2409 if (sctx->gs_shader.cso)
2410 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2411 S_028B54_GS_EN(1) |
2412 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2413 else
2414 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2415 } else if (sctx->gs_shader.cso) {
2416 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2417 S_028B54_GS_EN(1) |
2418 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2419 }
2420
2421 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
2422 }
2423 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
2424 }
2425
2426 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
2427 {
2428 struct pipe_stream_output_info *so = &shader->so;
2429 uint32_t enabled_stream_buffers_mask = 0;
2430 int i;
2431
2432 for (i = 0; i < so->num_outputs; i++)
2433 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
2434 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
2435 sctx->b.streamout.stride_in_dw = shader->so.stride;
2436 }
2437
2438 bool si_update_shaders(struct si_context *sctx)
2439 {
2440 struct pipe_context *ctx = (struct pipe_context*)sctx;
2441 struct si_compiler_ctx_state compiler_state;
2442 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2443 struct si_shader *old_vs = si_get_vs_state(sctx);
2444 bool old_clip_disable = old_vs ? old_vs->key.opt.hw_vs.clip_disable : false;
2445 int r;
2446
2447 compiler_state.tm = sctx->tm;
2448 compiler_state.debug = sctx->b.debug;
2449 compiler_state.is_debug_context = sctx->is_debug;
2450
2451 /* Update stages before GS. */
2452 if (sctx->tes_shader.cso) {
2453 if (!sctx->tf_ring) {
2454 si_init_tess_factor_ring(sctx);
2455 if (!sctx->tf_ring)
2456 return false;
2457 }
2458
2459 /* VS as LS */
2460 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
2461 if (r)
2462 return false;
2463 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2464
2465 if (sctx->tcs_shader.cso) {
2466 r = si_shader_select(ctx, &sctx->tcs_shader,
2467 &compiler_state);
2468 if (r)
2469 return false;
2470 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
2471 } else {
2472 if (!sctx->fixed_func_tcs_shader.cso) {
2473 si_generate_fixed_func_tcs(sctx);
2474 if (!sctx->fixed_func_tcs_shader.cso)
2475 return false;
2476 }
2477
2478 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
2479 &compiler_state);
2480 if (r)
2481 return false;
2482 si_pm4_bind_state(sctx, hs,
2483 sctx->fixed_func_tcs_shader.current->pm4);
2484 }
2485
2486 r = si_shader_select(ctx, &sctx->tes_shader, &compiler_state);
2487 if (r)
2488 return false;
2489
2490 if (sctx->gs_shader.cso) {
2491 /* TES as ES */
2492 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2493 } else {
2494 /* TES as VS */
2495 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2496 si_update_so(sctx, sctx->tes_shader.cso);
2497 }
2498 } else if (sctx->gs_shader.cso) {
2499 /* VS as ES */
2500 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
2501 if (r)
2502 return false;
2503 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2504
2505 si_pm4_bind_state(sctx, ls, NULL);
2506 si_pm4_bind_state(sctx, hs, NULL);
2507 } else {
2508 /* VS as VS */
2509 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
2510 if (r)
2511 return false;
2512 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2513 si_update_so(sctx, sctx->vs_shader.cso);
2514
2515 si_pm4_bind_state(sctx, ls, NULL);
2516 si_pm4_bind_state(sctx, hs, NULL);
2517 }
2518
2519 /* Update GS. */
2520 if (sctx->gs_shader.cso) {
2521 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
2522 if (r)
2523 return false;
2524 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2525 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
2526 si_update_so(sctx, sctx->gs_shader.cso);
2527
2528 if (!si_update_gs_ring_buffers(sctx))
2529 return false;
2530 } else {
2531 si_pm4_bind_state(sctx, gs, NULL);
2532 si_pm4_bind_state(sctx, es, NULL);
2533 }
2534
2535 si_update_vgt_shader_config(sctx);
2536
2537 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.hw_vs.clip_disable)
2538 si_mark_atom_dirty(sctx, &sctx->clip_regs);
2539
2540 if (sctx->ps_shader.cso) {
2541 unsigned db_shader_control;
2542
2543 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
2544 if (r)
2545 return false;
2546 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2547
2548 db_shader_control =
2549 sctx->ps_shader.cso->db_shader_control |
2550 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
2551
2552 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
2553 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
2554 sctx->flatshade != rs->flatshade) {
2555 sctx->sprite_coord_enable = rs->sprite_coord_enable;
2556 sctx->flatshade = rs->flatshade;
2557 si_mark_atom_dirty(sctx, &sctx->spi_map);
2558 }
2559
2560 if (sctx->b.family == CHIP_STONEY && si_pm4_state_changed(sctx, ps))
2561 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2562
2563 if (sctx->ps_db_shader_control != db_shader_control) {
2564 sctx->ps_db_shader_control = db_shader_control;
2565 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2566 }
2567
2568 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
2569 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
2570 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2571
2572 if (sctx->b.chip_class == SI)
2573 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2574
2575 if (sctx->framebuffer.nr_samples <= 1)
2576 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2577 }
2578 }
2579
2580 if (si_pm4_state_changed(sctx, ls) ||
2581 si_pm4_state_changed(sctx, hs) ||
2582 si_pm4_state_changed(sctx, es) ||
2583 si_pm4_state_changed(sctx, gs) ||
2584 si_pm4_state_changed(sctx, vs) ||
2585 si_pm4_state_changed(sctx, ps)) {
2586 if (!si_update_spi_tmpring_size(sctx))
2587 return false;
2588 }
2589
2590 if (sctx->b.chip_class >= CIK)
2591 si_mark_atom_dirty(sctx, &sctx->prefetch_L2);
2592
2593 sctx->do_update_shaders = false;
2594 return true;
2595 }
2596
2597 static void si_emit_scratch_state(struct si_context *sctx,
2598 struct r600_atom *atom)
2599 {
2600 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2601
2602 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
2603 sctx->spi_tmpring_size);
2604
2605 if (sctx->scratch_buffer) {
2606 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2607 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
2608 RADEON_PRIO_SCRATCH_BUFFER);
2609 }
2610 }
2611
2612 void si_init_shader_functions(struct si_context *sctx)
2613 {
2614 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
2615 si_init_atom(sctx, &sctx->scratch_state, &sctx->atoms.s.scratch_state,
2616 si_emit_scratch_state);
2617
2618 sctx->b.b.create_vs_state = si_create_shader_selector;
2619 sctx->b.b.create_tcs_state = si_create_shader_selector;
2620 sctx->b.b.create_tes_state = si_create_shader_selector;
2621 sctx->b.b.create_gs_state = si_create_shader_selector;
2622 sctx->b.b.create_fs_state = si_create_shader_selector;
2623
2624 sctx->b.b.bind_vs_state = si_bind_vs_shader;
2625 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
2626 sctx->b.b.bind_tes_state = si_bind_tes_shader;
2627 sctx->b.b.bind_gs_state = si_bind_gs_shader;
2628 sctx->b.b.bind_fs_state = si_bind_ps_shader;
2629
2630 sctx->b.b.delete_vs_state = si_delete_shader_selector;
2631 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
2632 sctx->b.b.delete_tes_state = si_delete_shader_selector;
2633 sctx->b.b.delete_gs_state = si_delete_shader_selector;
2634 sctx->b.b.delete_fs_state = si_delete_shader_selector;
2635 }