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382738a21212e0f6a38ecfe23e6141ccb909f108
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "si_shader.h"
30 #include "sid.h"
31
32 #include "tgsi/tgsi_parse.h"
33 #include "util/u_memory.h"
34 #include "util/u_simple_shaders.h"
35
36 static void si_shader_es(struct si_shader *shader)
37 {
38 struct si_pm4_state *pm4;
39 unsigned num_sgprs, num_user_sgprs;
40 unsigned vgpr_comp_cnt;
41 uint64_t va;
42
43 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
44
45 if (pm4 == NULL)
46 return;
47
48 va = shader->bo->gpu_address;
49 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
50
51 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
52
53 num_user_sgprs = SI_VS_NUM_USER_SGPR;
54 num_sgprs = shader->num_sgprs;
55 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
56 if ((num_user_sgprs + 1) > num_sgprs) {
57 /* Last 2 reserved SGPRs are used for VCC */
58 num_sgprs = num_user_sgprs + 1 + 2;
59 }
60 assert(num_sgprs <= 104);
61
62 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
63 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
64 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
65 S_00B328_VGPRS((shader->num_vgprs - 1) / 4) |
66 S_00B328_SGPRS((num_sgprs - 1) / 8) |
67 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
68 S_00B328_DX10_CLAMP(shader->dx10_clamp_mode));
69 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
70 S_00B32C_USER_SGPR(num_user_sgprs) |
71 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
72 }
73
74 static void si_shader_gs(struct si_shader *shader)
75 {
76 unsigned gs_vert_itemsize = shader->selector->info.num_outputs * (16 >> 2);
77 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
78 unsigned gsvs_itemsize = gs_vert_itemsize * gs_max_vert_out;
79 unsigned cut_mode;
80 struct si_pm4_state *pm4;
81 unsigned num_sgprs, num_user_sgprs;
82 uint64_t va;
83
84 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
85 assert(gsvs_itemsize < (1 << 15));
86
87 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
88
89 if (pm4 == NULL)
90 return;
91
92 if (gs_max_vert_out <= 128) {
93 cut_mode = V_028A40_GS_CUT_128;
94 } else if (gs_max_vert_out <= 256) {
95 cut_mode = V_028A40_GS_CUT_256;
96 } else if (gs_max_vert_out <= 512) {
97 cut_mode = V_028A40_GS_CUT_512;
98 } else {
99 assert(gs_max_vert_out <= 1024);
100 cut_mode = V_028A40_GS_CUT_1024;
101 }
102
103 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
104 S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
105 S_028A40_CUT_MODE(cut_mode)|
106 S_028A40_ES_WRITE_OPTIMIZE(1) |
107 S_028A40_GS_WRITE_OPTIMIZE(1));
108
109 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
110 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize);
111 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize);
112
113 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
114 util_bitcount64(shader->selector->gs_used_inputs) * (16 >> 2));
115 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
116
117 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, gs_max_vert_out);
118
119 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize);
120
121 va = shader->bo->gpu_address;
122 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
123 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
124 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
125
126 num_user_sgprs = SI_GS_NUM_USER_SGPR;
127 num_sgprs = shader->num_sgprs;
128 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
129 if ((num_user_sgprs + 2) > num_sgprs) {
130 /* Last 2 reserved SGPRs are used for VCC */
131 num_sgprs = num_user_sgprs + 2 + 2;
132 }
133 assert(num_sgprs <= 104);
134
135 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
136 S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
137 S_00B228_SGPRS((num_sgprs - 1) / 8) |
138 S_00B228_DX10_CLAMP(shader->dx10_clamp_mode));
139 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
140 S_00B22C_USER_SGPR(num_user_sgprs) |
141 S_00B22C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
142 }
143
144 static void si_shader_vs(struct si_shader *shader)
145 {
146 struct tgsi_shader_info *info = &shader->selector->info;
147 struct si_pm4_state *pm4;
148 unsigned num_sgprs, num_user_sgprs;
149 unsigned nparams, i, vgpr_comp_cnt;
150 uint64_t va;
151 unsigned window_space =
152 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
153
154 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
155
156 if (pm4 == NULL)
157 return;
158
159 va = shader->bo->gpu_address;
160 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
161
162 if (shader->is_gs_copy_shader) {
163 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
164 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
165 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
166 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
167 num_user_sgprs = SI_VS_NUM_USER_SGPR;
168 } else
169 assert(0);
170
171 num_sgprs = shader->num_sgprs;
172 if (num_user_sgprs > num_sgprs) {
173 /* Last 2 reserved SGPRs are used for VCC */
174 num_sgprs = num_user_sgprs + 2;
175 }
176 assert(num_sgprs <= 104);
177
178 /* Certain attributes (position, psize, etc.) don't count as params.
179 * VS is required to export at least one param and r600_shader_from_tgsi()
180 * takes care of adding a dummy export.
181 */
182 for (nparams = 0, i = 0 ; i < info->num_outputs; i++) {
183 switch (info->output_semantic_name[i]) {
184 case TGSI_SEMANTIC_CLIPVERTEX:
185 case TGSI_SEMANTIC_POSITION:
186 case TGSI_SEMANTIC_PSIZE:
187 break;
188 default:
189 nparams++;
190 }
191 }
192 if (nparams < 1)
193 nparams = 1;
194
195 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
196 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
197
198 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
199 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
200 S_02870C_POS1_EXPORT_FORMAT(shader->nr_pos_exports > 1 ?
201 V_02870C_SPI_SHADER_4COMP :
202 V_02870C_SPI_SHADER_NONE) |
203 S_02870C_POS2_EXPORT_FORMAT(shader->nr_pos_exports > 2 ?
204 V_02870C_SPI_SHADER_4COMP :
205 V_02870C_SPI_SHADER_NONE) |
206 S_02870C_POS3_EXPORT_FORMAT(shader->nr_pos_exports > 3 ?
207 V_02870C_SPI_SHADER_4COMP :
208 V_02870C_SPI_SHADER_NONE));
209
210 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
211 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
212 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
213 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
214 S_00B128_SGPRS((num_sgprs - 1) / 8) |
215 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
216 S_00B128_DX10_CLAMP(shader->dx10_clamp_mode));
217 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
218 S_00B12C_USER_SGPR(num_user_sgprs) |
219 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
220 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
221 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
222 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
223 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
224 S_00B12C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
225 if (window_space)
226 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
227 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
228 else
229 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
230 S_028818_VTX_W0_FMT(1) |
231 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
232 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
233 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
234 }
235
236 static void si_shader_ps(struct si_shader *shader)
237 {
238 struct tgsi_shader_info *info = &shader->selector->info;
239 struct si_pm4_state *pm4;
240 unsigned i, spi_ps_in_control;
241 unsigned num_sgprs, num_user_sgprs;
242 unsigned spi_baryc_cntl = 0, spi_ps_input_ena;
243 uint64_t va;
244
245 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
246
247 if (pm4 == NULL)
248 return;
249
250 for (i = 0; i < info->num_inputs; i++) {
251 switch (info->input_semantic_name[i]) {
252 case TGSI_SEMANTIC_POSITION:
253 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
254 * Possible vaules:
255 * 0 -> Position = pixel center (default)
256 * 1 -> Position = pixel centroid
257 * 2 -> Position = at sample position
258 */
259 switch (info->input_interpolate_loc[i]) {
260 case TGSI_INTERPOLATE_LOC_CENTROID:
261 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
262 break;
263 case TGSI_INTERPOLATE_LOC_SAMPLE:
264 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
265 break;
266 }
267
268 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
269 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
270 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
271 break;
272 }
273 }
274
275 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->nparam) |
276 S_0286D8_BC_OPTIMIZE_DISABLE(1);
277
278 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
279 spi_ps_input_ena = shader->spi_ps_input_ena;
280 /* we need to enable at least one of them, otherwise we hang the GPU */
281 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
282 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
283 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
284 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
285 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
286 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
287 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
288 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
289
290 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
291 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
292 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
293
294 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
295 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
296 shader->spi_shader_col_format);
297 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
298
299 va = shader->bo->gpu_address;
300 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
301 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
302 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
303
304 num_user_sgprs = SI_PS_NUM_USER_SGPR;
305 num_sgprs = shader->num_sgprs;
306 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
307 if ((num_user_sgprs + 1) > num_sgprs) {
308 /* Last 2 reserved SGPRs are used for VCC */
309 num_sgprs = num_user_sgprs + 1 + 2;
310 }
311 assert(num_sgprs <= 104);
312
313 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
314 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
315 S_00B028_SGPRS((num_sgprs - 1) / 8) |
316 S_00B028_DX10_CLAMP(shader->dx10_clamp_mode));
317 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
318 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
319 S_00B02C_USER_SGPR(num_user_sgprs) |
320 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
321 }
322
323 static void si_shader_init_pm4_state(struct si_shader *shader)
324 {
325
326 if (shader->pm4)
327 si_pm4_free_state_simple(shader->pm4);
328
329 switch (shader->selector->type) {
330 case PIPE_SHADER_VERTEX:
331 if (shader->key.vs.as_es)
332 si_shader_es(shader);
333 else
334 si_shader_vs(shader);
335 break;
336 case PIPE_SHADER_GEOMETRY:
337 si_shader_gs(shader);
338 si_shader_vs(shader->gs_copy_shader);
339 break;
340 case PIPE_SHADER_FRAGMENT:
341 si_shader_ps(shader);
342 break;
343 default:
344 assert(0);
345 }
346 }
347
348 /* Compute the key for the hw shader variant */
349 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
350 struct si_shader_selector *sel,
351 union si_shader_key *key)
352 {
353 struct si_context *sctx = (struct si_context *)ctx;
354 memset(key, 0, sizeof(*key));
355
356 if (sel->type == PIPE_SHADER_VERTEX) {
357 unsigned i;
358 if (!sctx->vertex_elements)
359 return;
360
361 for (i = 0; i < sctx->vertex_elements->count; ++i)
362 key->vs.instance_divisors[i] = sctx->vertex_elements->elements[i].instance_divisor;
363
364 if (sctx->gs_shader) {
365 key->vs.as_es = 1;
366 key->vs.gs_used_inputs = sctx->gs_shader->gs_used_inputs;
367 }
368 } else if (sel->type == PIPE_SHADER_FRAGMENT) {
369 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
370
371 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
372 key->ps.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
373 key->ps.export_16bpc = sctx->framebuffer.export_16bpc;
374
375 if (rs) {
376 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
377 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
378 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
379 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
380
381 key->ps.color_two_side = rs->two_side;
382
383 if (sctx->queued.named.blend) {
384 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
385 rs->multisample_enable &&
386 !sctx->framebuffer.cb0_is_integer;
387 }
388
389 key->ps.poly_stipple = rs->poly_stipple_enable && is_poly;
390 key->ps.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
391 (is_line && rs->line_smooth)) &&
392 sctx->framebuffer.nr_samples <= 1;
393 }
394
395 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
396
397 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
398 if (sctx->queued.named.dsa &&
399 !sctx->framebuffer.cb0_is_integer)
400 key->ps.alpha_func = sctx->queued.named.dsa->alpha_func;
401 }
402 }
403
404 /* Select the hw shader variant depending on the current state. */
405 static int si_shader_select(struct pipe_context *ctx,
406 struct si_shader_selector *sel)
407 {
408 union si_shader_key key;
409 struct si_shader * shader = NULL;
410 int r;
411
412 si_shader_selector_key(ctx, sel, &key);
413
414 /* Check if we don't need to change anything.
415 * This path is also used for most shaders that don't need multiple
416 * variants, it will cost just a computation of the key and this
417 * test. */
418 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
419 return 0;
420 }
421
422 /* lookup if we have other variants in the list */
423 if (sel->num_shaders > 1) {
424 struct si_shader *p = sel->current, *c = p->next_variant;
425
426 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
427 p = c;
428 c = c->next_variant;
429 }
430
431 if (c) {
432 p->next_variant = c->next_variant;
433 shader = c;
434 }
435 }
436
437 if (shader) {
438 shader->next_variant = sel->current;
439 sel->current = shader;
440 } else {
441 shader = CALLOC(1, sizeof(struct si_shader));
442 shader->selector = sel;
443 shader->key = key;
444
445 shader->next_variant = sel->current;
446 sel->current = shader;
447 r = si_shader_create((struct si_screen*)ctx->screen, shader);
448 if (unlikely(r)) {
449 R600_ERR("Failed to build shader variant (type=%u) %d\n",
450 sel->type, r);
451 sel->current = NULL;
452 FREE(shader);
453 return r;
454 }
455 si_shader_init_pm4_state(shader);
456 sel->num_shaders++;
457 }
458
459 return 0;
460 }
461
462 static void *si_create_shader_state(struct pipe_context *ctx,
463 const struct pipe_shader_state *state,
464 unsigned pipe_shader_type)
465 {
466 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
467 int i;
468
469 sel->type = pipe_shader_type;
470 sel->tokens = tgsi_dup_tokens(state->tokens);
471 sel->so = state->stream_output;
472 tgsi_scan_shader(state->tokens, &sel->info);
473
474 switch (pipe_shader_type) {
475 case PIPE_SHADER_GEOMETRY:
476 sel->gs_output_prim =
477 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
478 sel->gs_max_out_vertices =
479 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
480
481 for (i = 0; i < sel->info.num_inputs; i++) {
482 unsigned name = sel->info.input_semantic_name[i];
483 unsigned index = sel->info.input_semantic_index[i];
484
485 switch (name) {
486 case TGSI_SEMANTIC_PRIMID:
487 break;
488 default:
489 sel->gs_used_inputs |=
490 1llu << si_shader_io_get_unique_index(name, index);
491 }
492 }
493 }
494
495 return sel;
496 }
497
498 static void *si_create_fs_state(struct pipe_context *ctx,
499 const struct pipe_shader_state *state)
500 {
501 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
502 }
503
504 static void *si_create_gs_state(struct pipe_context *ctx,
505 const struct pipe_shader_state *state)
506 {
507 return si_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
508 }
509
510 static void *si_create_vs_state(struct pipe_context *ctx,
511 const struct pipe_shader_state *state)
512 {
513 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
514 }
515
516 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
517 {
518 struct si_context *sctx = (struct si_context *)ctx;
519 struct si_shader_selector *sel = state;
520
521 if (sctx->vs_shader == sel || !sel)
522 return;
523
524 sctx->vs_shader = sel;
525 sctx->clip_regs.dirty = true;
526 }
527
528 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
529 {
530 struct si_context *sctx = (struct si_context *)ctx;
531 struct si_shader_selector *sel = state;
532
533 if (sctx->gs_shader == sel)
534 return;
535
536 sctx->gs_shader = sel;
537 sctx->clip_regs.dirty = true;
538 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
539 }
540
541 static void si_make_dummy_ps(struct si_context *sctx)
542 {
543 if (!sctx->dummy_pixel_shader) {
544 sctx->dummy_pixel_shader =
545 util_make_fragment_cloneinput_shader(&sctx->b.b, 0,
546 TGSI_SEMANTIC_GENERIC,
547 TGSI_INTERPOLATE_CONSTANT);
548 }
549 }
550
551 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
552 {
553 struct si_context *sctx = (struct si_context *)ctx;
554 struct si_shader_selector *sel = state;
555
556 /* skip if supplied shader is one already in use */
557 if (sctx->ps_shader == sel)
558 return;
559
560 /* use a dummy shader if binding a NULL shader */
561 if (!sel) {
562 si_make_dummy_ps(sctx);
563 sel = sctx->dummy_pixel_shader;
564 }
565
566 sctx->ps_shader = sel;
567 }
568
569 static void si_delete_shader_selector(struct pipe_context *ctx,
570 struct si_shader_selector *sel)
571 {
572 struct si_context *sctx = (struct si_context *)ctx;
573 struct si_shader *p = sel->current, *c;
574
575 while (p) {
576 c = p->next_variant;
577 if (sel->type == PIPE_SHADER_GEOMETRY) {
578 si_pm4_delete_state(sctx, gs, p->pm4);
579 si_pm4_delete_state(sctx, vs, p->gs_copy_shader->pm4);
580 } else if (sel->type == PIPE_SHADER_FRAGMENT)
581 si_pm4_delete_state(sctx, ps, p->pm4);
582 else if (p->key.vs.as_es)
583 si_pm4_delete_state(sctx, es, p->pm4);
584 else
585 si_pm4_delete_state(sctx, vs, p->pm4);
586 si_shader_destroy(ctx, p);
587 free(p);
588 p = c;
589 }
590
591 free(sel->tokens);
592 free(sel);
593 }
594
595 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
596 {
597 struct si_context *sctx = (struct si_context *)ctx;
598 struct si_shader_selector *sel = (struct si_shader_selector *)state;
599
600 if (sctx->vs_shader == sel) {
601 sctx->vs_shader = NULL;
602 }
603
604 si_delete_shader_selector(ctx, sel);
605 }
606
607 static void si_delete_gs_shader(struct pipe_context *ctx, void *state)
608 {
609 struct si_context *sctx = (struct si_context *)ctx;
610 struct si_shader_selector *sel = (struct si_shader_selector *)state;
611
612 if (sctx->gs_shader == sel) {
613 sctx->gs_shader = NULL;
614 }
615
616 si_delete_shader_selector(ctx, sel);
617 }
618
619 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
620 {
621 struct si_context *sctx = (struct si_context *)ctx;
622 struct si_shader_selector *sel = (struct si_shader_selector *)state;
623
624 if (sctx->ps_shader == sel) {
625 sctx->ps_shader = NULL;
626 }
627
628 si_delete_shader_selector(ctx, sel);
629 }
630
631 static void si_update_spi_map(struct si_context *sctx)
632 {
633 struct si_shader *ps = sctx->ps_shader->current;
634 struct si_shader *vs = si_get_vs_state(sctx);
635 struct tgsi_shader_info *psinfo = &ps->selector->info;
636 struct tgsi_shader_info *vsinfo = &vs->selector->info;
637 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
638 unsigned i, j, tmp;
639
640 for (i = 0; i < psinfo->num_inputs; i++) {
641 unsigned name = psinfo->input_semantic_name[i];
642 unsigned index = psinfo->input_semantic_index[i];
643 unsigned interpolate = psinfo->input_interpolate[i];
644 unsigned param_offset = ps->ps_input_param_offset[i];
645
646 if (name == TGSI_SEMANTIC_POSITION ||
647 name == TGSI_SEMANTIC_FACE)
648 /* Read from preloaded VGPRs, not parameters */
649 continue;
650
651 bcolor:
652 tmp = 0;
653
654 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
655 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
656 tmp |= S_028644_FLAT_SHADE(1);
657
658 if (name == TGSI_SEMANTIC_GENERIC &&
659 sctx->sprite_coord_enable & (1 << index)) {
660 tmp |= S_028644_PT_SPRITE_TEX(1);
661 }
662
663 for (j = 0; j < vsinfo->num_outputs; j++) {
664 if (name == vsinfo->output_semantic_name[j] &&
665 index == vsinfo->output_semantic_index[j]) {
666 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[j]);
667 break;
668 }
669 }
670
671 if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(tmp)) {
672 /* No corresponding output found, load defaults into input.
673 * Don't set any other bits.
674 * (FLAT_SHADE=1 completely changes behavior) */
675 tmp = S_028644_OFFSET(0x20);
676 }
677
678 si_pm4_set_reg(pm4,
679 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
680 tmp);
681
682 if (name == TGSI_SEMANTIC_COLOR &&
683 ps->key.ps.color_two_side) {
684 name = TGSI_SEMANTIC_BCOLOR;
685 param_offset++;
686 goto bcolor;
687 }
688 }
689
690 si_pm4_set_state(sctx, spi, pm4);
691 }
692
693 /* Initialize state related to ESGS / GSVS ring buffers */
694 static void si_init_gs_rings(struct si_context *sctx)
695 {
696 unsigned esgs_ring_size = 128 * 1024;
697 unsigned gsvs_ring_size = 64 * 1024 * 1024;
698
699 assert(!sctx->gs_rings);
700 sctx->gs_rings = CALLOC_STRUCT(si_pm4_state);
701
702 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
703 PIPE_USAGE_DEFAULT, esgs_ring_size);
704
705 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
706 PIPE_USAGE_DEFAULT, gsvs_ring_size);
707
708 if (sctx->b.chip_class >= CIK) {
709 si_pm4_set_reg(sctx->gs_rings, R_030900_VGT_ESGS_RING_SIZE,
710 esgs_ring_size / 256);
711 si_pm4_set_reg(sctx->gs_rings, R_030904_VGT_GSVS_RING_SIZE,
712 gsvs_ring_size / 256);
713 } else {
714 si_pm4_set_reg(sctx->gs_rings, R_0088C8_VGT_ESGS_RING_SIZE,
715 esgs_ring_size / 256);
716 si_pm4_set_reg(sctx->gs_rings, R_0088CC_VGT_GSVS_RING_SIZE,
717 gsvs_ring_size / 256);
718 }
719
720 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
721 sctx->esgs_ring, 0, esgs_ring_size,
722 true, true, 4, 64);
723 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
724 sctx->esgs_ring, 0, esgs_ring_size,
725 false, false, 0, 0);
726 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
727 sctx->gsvs_ring, 0, gsvs_ring_size,
728 false, false, 0, 0);
729 }
730
731 /**
732 * @returns 1 if \p sel has been updated to use a new scratch buffer and 0
733 * otherwise.
734 */
735 static unsigned si_update_scratch_buffer(struct si_context *sctx,
736 struct si_shader_selector *sel)
737 {
738 struct si_shader *shader;
739 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
740 unsigned char *ptr;
741
742 if (!sel)
743 return 0;
744
745 shader = sel->current;
746
747 /* This shader doesn't need a scratch buffer */
748 if (shader->scratch_bytes_per_wave == 0)
749 return 0;
750
751 /* This shader is already configured to use the current
752 * scratch buffer. */
753 if (shader->scratch_bo == sctx->scratch_buffer)
754 return 0;
755
756 assert(sctx->scratch_buffer);
757
758 si_shader_apply_scratch_relocs(sctx, shader, scratch_va);
759
760 /* Replace the shader bo with a new bo that has the relocs applied. */
761 r600_resource_reference(&shader->bo, NULL);
762 shader->bo = si_resource_create_custom(&sctx->screen->b.b, PIPE_USAGE_IMMUTABLE,
763 shader->binary.code_size);
764 ptr = sctx->screen->b.ws->buffer_map(shader->bo->cs_buf, NULL, PIPE_TRANSFER_WRITE);
765 util_memcpy_cpu_to_le32(ptr, shader->binary.code, shader->binary.code_size);
766 sctx->screen->b.ws->buffer_unmap(shader->bo->cs_buf);
767
768 /* Update the shader state to use the new shader bo. */
769 si_shader_init_pm4_state(shader);
770
771 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
772
773 return 1;
774 }
775
776 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
777 {
778 if (!sctx->scratch_buffer)
779 return 0;
780
781 return sctx->scratch_buffer->b.b.width0;
782 }
783
784 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_context *sctx,
785 struct si_shader_selector *sel)
786 {
787 if (!sel)
788 return 0;
789
790 return sel->current->scratch_bytes_per_wave;
791 }
792
793 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
794 {
795
796 return MAX3(si_get_scratch_buffer_bytes_per_wave(sctx, sctx->ps_shader),
797 si_get_scratch_buffer_bytes_per_wave(sctx, sctx->gs_shader),
798 si_get_scratch_buffer_bytes_per_wave(sctx, sctx->vs_shader));
799 }
800
801 static void si_update_spi_tmpring_size(struct si_context *sctx)
802 {
803 unsigned current_scratch_buffer_size =
804 si_get_current_scratch_buffer_size(sctx);
805 unsigned scratch_bytes_per_wave =
806 si_get_max_scratch_bytes_per_wave(sctx);
807 unsigned scratch_needed_size = scratch_bytes_per_wave *
808 sctx->scratch_waves;
809
810 if (scratch_needed_size > 0) {
811
812 if (scratch_needed_size > current_scratch_buffer_size) {
813 /* Create a bigger scratch buffer */
814 pipe_resource_reference(
815 (struct pipe_resource**)&sctx->scratch_buffer,
816 NULL);
817
818 sctx->scratch_buffer =
819 si_resource_create_custom(&sctx->screen->b.b,
820 PIPE_USAGE_DEFAULT, scratch_needed_size);
821 }
822
823 /* Update the shaders, so they are using the latest scratch. The
824 * scratch buffer may have been changed since these shaders were
825 * last used, so we still need to try to update them, even if
826 * they require scratch buffers smaller than the current size.
827 */
828 if (si_update_scratch_buffer(sctx, sctx->ps_shader))
829 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
830 if (si_update_scratch_buffer(sctx, sctx->gs_shader))
831 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
832 if (si_update_scratch_buffer(sctx, sctx->vs_shader))
833 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
834 }
835
836 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
837 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
838 "scratch size should already be aligned correctly.");
839
840 sctx->spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
841 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
842 }
843
844 void si_update_shaders(struct si_context *sctx)
845 {
846 struct pipe_context *ctx = (struct pipe_context*)sctx;
847 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
848
849 if (sctx->gs_shader) {
850 si_shader_select(ctx, sctx->gs_shader);
851 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
852 si_pm4_bind_state(sctx, vs, sctx->gs_shader->current->gs_copy_shader->pm4);
853
854 sctx->b.streamout.stride_in_dw = sctx->gs_shader->so.stride;
855
856 si_shader_select(ctx, sctx->vs_shader);
857 si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
858
859 if (!sctx->gs_rings)
860 si_init_gs_rings(sctx);
861 if (sctx->emitted.named.gs_rings != sctx->gs_rings)
862 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
863 si_pm4_bind_state(sctx, gs_rings, sctx->gs_rings);
864
865 si_set_ring_buffer(ctx, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
866 sctx->gsvs_ring,
867 sctx->gs_shader->gs_max_out_vertices *
868 sctx->gs_shader->info.num_outputs * 16,
869 64, true, true, 4, 16);
870
871 if (!sctx->gs_on) {
872 sctx->gs_on = CALLOC_STRUCT(si_pm4_state);
873
874 si_pm4_set_reg(sctx->gs_on, R_028B54_VGT_SHADER_STAGES_EN,
875 S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
876 S_028B54_GS_EN(1) |
877 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER));
878 }
879 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_on);
880 } else {
881 si_shader_select(ctx, sctx->vs_shader);
882 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
883
884 sctx->b.streamout.stride_in_dw = sctx->vs_shader->so.stride;
885
886 if (!sctx->gs_off) {
887 sctx->gs_off = CALLOC_STRUCT(si_pm4_state);
888
889 si_pm4_set_reg(sctx->gs_off, R_028A40_VGT_GS_MODE, 0);
890 si_pm4_set_reg(sctx->gs_off, R_028B54_VGT_SHADER_STAGES_EN, 0);
891 }
892 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_off);
893 si_pm4_bind_state(sctx, gs_rings, NULL);
894 si_pm4_bind_state(sctx, gs, NULL);
895 si_pm4_bind_state(sctx, es, NULL);
896 }
897
898 si_shader_select(ctx, sctx->ps_shader);
899
900 if (!sctx->ps_shader->current) {
901 struct si_shader_selector *sel;
902
903 /* use a dummy shader if compiling the shader (variant) failed */
904 si_make_dummy_ps(sctx);
905 sel = sctx->dummy_pixel_shader;
906 si_shader_select(ctx, sel);
907 sctx->ps_shader->current = sel->current;
908 }
909
910 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
911
912 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
913 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
914 sctx->flatshade != rs->flatshade) {
915 sctx->sprite_coord_enable = rs->sprite_coord_enable;
916 sctx->flatshade = rs->flatshade;
917 si_update_spi_map(sctx);
918 }
919
920 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
921 si_pm4_state_changed(sctx, gs)) {
922 si_update_spi_tmpring_size(sctx);
923 }
924
925 if (sctx->ps_db_shader_control != sctx->ps_shader->current->db_shader_control) {
926 sctx->ps_db_shader_control = sctx->ps_shader->current->db_shader_control;
927 sctx->db_render_state.dirty = true;
928 }
929
930 if (sctx->smoothing_enabled != sctx->ps_shader->current->key.ps.poly_line_smoothing) {
931 sctx->smoothing_enabled = sctx->ps_shader->current->key.ps.poly_line_smoothing;
932 sctx->msaa_config.dirty = true;
933
934 if (sctx->b.chip_class == SI)
935 sctx->db_render_state.dirty = true;
936 }
937 }
938
939 void si_init_shader_functions(struct si_context *sctx)
940 {
941 sctx->b.b.create_vs_state = si_create_vs_state;
942 sctx->b.b.create_gs_state = si_create_gs_state;
943 sctx->b.b.create_fs_state = si_create_fs_state;
944
945 sctx->b.b.bind_vs_state = si_bind_vs_shader;
946 sctx->b.b.bind_gs_state = si_bind_gs_shader;
947 sctx->b.b.bind_fs_state = si_bind_ps_shader;
948
949 sctx->b.b.delete_vs_state = si_delete_vs_shader;
950 sctx->b.b.delete_gs_state = si_delete_gs_shader;
951 sctx->b.b.delete_fs_state = si_delete_ps_shader;
952 }