2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
29 #include "si_shader.h"
31 #include "radeon/r600_cs.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/hash_table.h"
36 #include "util/u_hash.h"
37 #include "util/u_memory.h"
38 #include "util/u_prim.h"
39 #include "util/u_simple_shaders.h"
44 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
47 static void *si_get_tgsi_binary(struct si_shader_selector
*sel
)
49 unsigned tgsi_size
= tgsi_num_tokens(sel
->tokens
) *
50 sizeof(struct tgsi_token
);
51 unsigned size
= 4 + tgsi_size
+ sizeof(sel
->so
);
52 char *result
= (char*)MALLOC(size
);
57 *((uint32_t*)result
) = size
;
58 memcpy(result
+ 4, sel
->tokens
, tgsi_size
);
59 memcpy(result
+ 4 + tgsi_size
, &sel
->so
, sizeof(sel
->so
));
63 /** Copy "data" to "ptr" and return the next dword following copied data. */
64 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
66 /* data may be NULL if size == 0 */
68 memcpy(ptr
, data
, size
);
69 ptr
+= DIV_ROUND_UP(size
, 4);
73 /** Read data from "ptr". Return the next dword following the data. */
74 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
76 memcpy(data
, ptr
, size
);
77 ptr
+= DIV_ROUND_UP(size
, 4);
82 * Write the size as uint followed by the data. Return the next dword
83 * following the copied data.
85 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
88 return write_data(ptr
, data
, size
);
92 * Read the size as uint followed by the data. Return both via parameters.
93 * Return the next dword following the data.
95 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
98 assert(*data
== NULL
);
101 *data
= malloc(*size
);
102 return read_data(ptr
, *data
, *size
);
106 * Return the shader binary in a buffer. The first 4 bytes contain its size
109 static void *si_get_shader_binary(struct si_shader
*shader
)
111 /* There is always a size of data followed by the data itself. */
112 unsigned relocs_size
= shader
->binary
.reloc_count
*
113 sizeof(shader
->binary
.relocs
[0]);
114 unsigned disasm_size
= strlen(shader
->binary
.disasm_string
) + 1;
115 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
116 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
119 4 + /* CRC32 of the data below */
120 align(sizeof(shader
->config
), 4) +
121 align(sizeof(shader
->info
), 4) +
122 4 + align(shader
->binary
.code_size
, 4) +
123 4 + align(shader
->binary
.rodata_size
, 4) +
124 4 + align(relocs_size
, 4) +
125 4 + align(disasm_size
, 4) +
126 4 + align(llvm_ir_size
, 4);
127 void *buffer
= CALLOC(1, size
);
128 uint32_t *ptr
= (uint32_t*)buffer
;
134 ptr
++; /* CRC32 is calculated at the end. */
136 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
137 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
138 ptr
= write_chunk(ptr
, shader
->binary
.code
, shader
->binary
.code_size
);
139 ptr
= write_chunk(ptr
, shader
->binary
.rodata
, shader
->binary
.rodata_size
);
140 ptr
= write_chunk(ptr
, shader
->binary
.relocs
, relocs_size
);
141 ptr
= write_chunk(ptr
, shader
->binary
.disasm_string
, disasm_size
);
142 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
143 assert((char *)ptr
- (char *)buffer
== size
);
146 ptr
= (uint32_t*)buffer
;
148 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
153 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
155 uint32_t *ptr
= (uint32_t*)binary
;
156 uint32_t size
= *ptr
++;
157 uint32_t crc32
= *ptr
++;
160 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
161 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
165 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
166 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
167 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.code
,
168 &shader
->binary
.code_size
);
169 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.rodata
,
170 &shader
->binary
.rodata_size
);
171 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.relocs
, &chunk_size
);
172 shader
->binary
.reloc_count
= chunk_size
/ sizeof(shader
->binary
.relocs
[0]);
173 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.disasm_string
, &chunk_size
);
174 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
180 * Insert a shader into the cache. It's assumed the shader is not in the cache.
181 * Use si_shader_cache_load_shader before calling this.
183 * Returns false on failure, in which case the tgsi_binary should be freed.
185 static bool si_shader_cache_insert_shader(struct si_screen
*sscreen
,
187 struct si_shader
*shader
)
190 struct hash_entry
*entry
;
192 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, tgsi_binary
);
194 return false; /* already added */
196 hw_binary
= si_get_shader_binary(shader
);
200 if (_mesa_hash_table_insert(sscreen
->shader_cache
, tgsi_binary
,
201 hw_binary
) == NULL
) {
209 static bool si_shader_cache_load_shader(struct si_screen
*sscreen
,
211 struct si_shader
*shader
)
213 struct hash_entry
*entry
=
214 _mesa_hash_table_search(sscreen
->shader_cache
, tgsi_binary
);
218 return si_load_shader_binary(shader
, entry
->data
);
221 static uint32_t si_shader_cache_key_hash(const void *key
)
223 /* The first dword is the key size. */
224 return util_hash_crc32(key
, *(uint32_t*)key
);
227 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
229 uint32_t *keya
= (uint32_t*)a
;
230 uint32_t *keyb
= (uint32_t*)b
;
232 /* The first dword is the key size. */
236 return memcmp(keya
, keyb
, *keya
) == 0;
239 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
241 FREE((void*)entry
->key
);
245 bool si_init_shader_cache(struct si_screen
*sscreen
)
247 pipe_mutex_init(sscreen
->shader_cache_mutex
);
248 sscreen
->shader_cache
=
249 _mesa_hash_table_create(NULL
,
250 si_shader_cache_key_hash
,
251 si_shader_cache_key_equals
);
252 return sscreen
->shader_cache
!= NULL
;
255 void si_destroy_shader_cache(struct si_screen
*sscreen
)
257 if (sscreen
->shader_cache
)
258 _mesa_hash_table_destroy(sscreen
->shader_cache
,
259 si_destroy_shader_cache_entry
);
260 pipe_mutex_destroy(sscreen
->shader_cache_mutex
);
265 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
266 struct si_shader
*shader
,
267 struct si_pm4_state
*pm4
)
269 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
270 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
271 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
272 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
273 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
274 unsigned type
, partitioning
, topology
, distribution_mode
;
276 switch (tes_prim_mode
) {
277 case PIPE_PRIM_LINES
:
278 type
= V_028B6C_TESS_ISOLINE
;
280 case PIPE_PRIM_TRIANGLES
:
281 type
= V_028B6C_TESS_TRIANGLE
;
283 case PIPE_PRIM_QUADS
:
284 type
= V_028B6C_TESS_QUAD
;
291 switch (tes_spacing
) {
292 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
293 partitioning
= V_028B6C_PART_FRAC_ODD
;
295 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
296 partitioning
= V_028B6C_PART_FRAC_EVEN
;
298 case PIPE_TESS_SPACING_EQUAL
:
299 partitioning
= V_028B6C_PART_INTEGER
;
307 topology
= V_028B6C_OUTPUT_POINT
;
308 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
309 topology
= V_028B6C_OUTPUT_LINE
;
310 else if (tes_vertex_order_cw
)
311 /* for some reason, this must be the other way around */
312 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
314 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
316 if (sscreen
->has_distributed_tess
) {
317 if (sscreen
->b
.family
== CHIP_FIJI
||
318 sscreen
->b
.family
>= CHIP_POLARIS10
)
319 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
321 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
323 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
325 si_pm4_set_reg(pm4
, R_028B6C_VGT_TF_PARAM
,
326 S_028B6C_TYPE(type
) |
327 S_028B6C_PARTITIONING(partitioning
) |
328 S_028B6C_TOPOLOGY(topology
) |
329 S_028B6C_DISTRIBUTION_MODE(distribution_mode
));
332 static void si_shader_ls(struct si_shader
*shader
)
334 struct si_pm4_state
*pm4
;
335 unsigned vgpr_comp_cnt
;
338 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
342 va
= shader
->bo
->gpu_address
;
343 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
345 /* We need at least 2 components for LS.
346 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
347 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 3 : 1;
349 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
350 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, va
>> 40);
352 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
353 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
354 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt
) |
355 S_00B528_DX10_CLAMP(1) |
356 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
357 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(SI_LS_NUM_USER_SGPR
) |
358 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
361 static void si_shader_hs(struct si_shader
*shader
)
363 struct si_pm4_state
*pm4
;
366 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
370 va
= shader
->bo
->gpu_address
;
371 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
373 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
374 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, va
>> 40);
375 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
376 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
377 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
378 S_00B428_DX10_CLAMP(1) |
379 S_00B428_FLOAT_MODE(shader
->config
.float_mode
));
380 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
381 S_00B42C_USER_SGPR(SI_TCS_NUM_USER_SGPR
) |
382 S_00B42C_OC_LDS_EN(1) |
383 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
386 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
388 struct si_pm4_state
*pm4
;
389 unsigned num_user_sgprs
;
390 unsigned vgpr_comp_cnt
;
394 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
399 va
= shader
->bo
->gpu_address
;
400 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
402 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
403 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 3 : 0;
404 num_user_sgprs
= SI_ES_NUM_USER_SGPR
;
405 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
406 vgpr_comp_cnt
= 3; /* all components are needed for TES */
407 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
409 unreachable("invalid shader selector type");
411 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
413 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
414 shader
->selector
->esgs_itemsize
/ 4);
415 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
416 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
417 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
418 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
419 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
420 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
421 S_00B328_DX10_CLAMP(1) |
422 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
423 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
424 S_00B32C_USER_SGPR(num_user_sgprs
) |
425 S_00B32C_OC_LDS_EN(oc_lds_en
) |
426 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
428 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
429 si_set_tesseval_regs(sscreen
, shader
, pm4
);
433 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
436 static uint32_t si_vgt_gs_mode(struct si_shader
*shader
)
438 unsigned gs_max_vert_out
= shader
->selector
->gs_max_out_vertices
;
441 if (gs_max_vert_out
<= 128) {
442 cut_mode
= V_028A40_GS_CUT_128
;
443 } else if (gs_max_vert_out
<= 256) {
444 cut_mode
= V_028A40_GS_CUT_256
;
445 } else if (gs_max_vert_out
<= 512) {
446 cut_mode
= V_028A40_GS_CUT_512
;
448 assert(gs_max_vert_out
<= 1024);
449 cut_mode
= V_028A40_GS_CUT_1024
;
452 return S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
453 S_028A40_CUT_MODE(cut_mode
)|
454 S_028A40_ES_WRITE_OPTIMIZE(1) |
455 S_028A40_GS_WRITE_OPTIMIZE(1);
458 static void si_shader_gs(struct si_shader
*shader
)
460 unsigned gs_vert_itemsize
= shader
->selector
->gsvs_vertex_size
;
461 unsigned gsvs_itemsize
= shader
->selector
->max_gsvs_emit_size
>> 2;
462 unsigned gs_num_invocations
= shader
->selector
->gs_num_invocations
;
463 struct si_pm4_state
*pm4
;
465 unsigned max_stream
= shader
->selector
->max_gs_stream
;
467 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
468 assert(gsvs_itemsize
< (1 << 15));
470 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
475 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, si_vgt_gs_mode(shader
));
477 si_pm4_set_reg(pm4
, R_028A60_VGT_GSVS_RING_OFFSET_1
, gsvs_itemsize
);
478 si_pm4_set_reg(pm4
, R_028A64_VGT_GSVS_RING_OFFSET_2
, gsvs_itemsize
* ((max_stream
>= 2) ? 2 : 1));
479 si_pm4_set_reg(pm4
, R_028A68_VGT_GSVS_RING_OFFSET_3
, gsvs_itemsize
* ((max_stream
>= 3) ? 3 : 1));
481 si_pm4_set_reg(pm4
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, gsvs_itemsize
* (max_stream
+ 1));
483 si_pm4_set_reg(pm4
, R_028B38_VGT_GS_MAX_VERT_OUT
, shader
->selector
->gs_max_out_vertices
);
485 si_pm4_set_reg(pm4
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, gs_vert_itemsize
>> 2);
486 si_pm4_set_reg(pm4
, R_028B60_VGT_GS_VERT_ITEMSIZE_1
, (max_stream
>= 1) ? gs_vert_itemsize
>> 2 : 0);
487 si_pm4_set_reg(pm4
, R_028B64_VGT_GS_VERT_ITEMSIZE_2
, (max_stream
>= 2) ? gs_vert_itemsize
>> 2 : 0);
488 si_pm4_set_reg(pm4
, R_028B68_VGT_GS_VERT_ITEMSIZE_3
, (max_stream
>= 3) ? gs_vert_itemsize
>> 2 : 0);
490 si_pm4_set_reg(pm4
, R_028B90_VGT_GS_INSTANCE_CNT
,
491 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
492 S_028B90_ENABLE(gs_num_invocations
> 0));
494 va
= shader
->bo
->gpu_address
;
495 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
496 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
497 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, va
>> 40);
499 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
500 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
501 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
502 S_00B228_DX10_CLAMP(1) |
503 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
504 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
505 S_00B22C_USER_SGPR(SI_GS_NUM_USER_SGPR
) |
506 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
510 * Compute the state for \p shader, which will run as a vertex shader on the
513 * If \p gs is non-NULL, it points to the geometry shader for which this shader
514 * is the copy shader.
516 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
517 struct si_shader
*gs
)
519 struct si_pm4_state
*pm4
;
520 unsigned num_user_sgprs
;
521 unsigned nparams
, vgpr_comp_cnt
;
524 unsigned window_space
=
525 shader
->selector
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
526 bool enable_prim_id
= si_vs_exports_prim_id(shader
);
528 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
533 /* We always write VGT_GS_MODE in the VS state, because every switch
534 * between different shader pipelines involving a different GS or no
535 * GS at all involves a switch of the VS (different GS use different
536 * copy shaders). On the other hand, when the API switches from a GS to
537 * no GS and then back to the same GS used originally, the GS state is
541 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
,
542 S_028A40_MODE(enable_prim_id
? V_028A40_GS_SCENARIO_A
: 0));
543 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, enable_prim_id
);
545 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, si_vgt_gs_mode(gs
));
546 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
549 va
= shader
->bo
->gpu_address
;
550 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
553 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
554 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
555 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
556 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 3 : (enable_prim_id
? 2 : 0);
557 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
558 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
559 vgpr_comp_cnt
= 3; /* all components are needed for TES */
560 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
562 unreachable("invalid shader selector type");
564 /* VS is required to export at least one param. */
565 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
566 si_pm4_set_reg(pm4
, R_0286C4_SPI_VS_OUT_CONFIG
,
567 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
569 si_pm4_set_reg(pm4
, R_02870C_SPI_SHADER_POS_FORMAT
,
570 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
571 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
572 V_02870C_SPI_SHADER_4COMP
:
573 V_02870C_SPI_SHADER_NONE
) |
574 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
575 V_02870C_SPI_SHADER_4COMP
:
576 V_02870C_SPI_SHADER_NONE
) |
577 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
578 V_02870C_SPI_SHADER_4COMP
:
579 V_02870C_SPI_SHADER_NONE
));
581 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
583 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
584 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, va
>> 40);
585 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
586 S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
587 S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
588 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
589 S_00B128_DX10_CLAMP(1) |
590 S_00B128_FLOAT_MODE(shader
->config
.float_mode
));
591 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
592 S_00B12C_USER_SGPR(num_user_sgprs
) |
593 S_00B12C_OC_LDS_EN(oc_lds_en
) |
594 S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
595 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
596 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
597 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
598 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
) |
599 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
601 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
602 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
604 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
605 S_028818_VTX_W0_FMT(1) |
606 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
607 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
608 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
610 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
611 si_set_tesseval_regs(sscreen
, shader
, pm4
);
614 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
616 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
617 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
618 !!(info
->colors_read
& 0xf0);
619 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
620 (ps
->key
.ps
.prolog
.color_two_side
? num_colors
: 0);
622 assert(num_interp
<= 32);
623 return MIN2(num_interp
, 32);
626 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
628 unsigned value
= shader
->key
.ps
.epilog
.spi_shader_col_format
;
629 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
631 /* If the i-th target format is set, all previous target formats must
632 * be non-zero to avoid hangs.
634 for (i
= 0; i
< num_targets
; i
++)
635 if (!(value
& (0xf << (i
* 4))))
636 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
641 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format
)
643 unsigned i
, cb_shader_mask
= 0;
645 for (i
= 0; i
< 8; i
++) {
646 switch ((spi_shader_col_format
>> (i
* 4)) & 0xf) {
647 case V_028714_SPI_SHADER_ZERO
:
649 case V_028714_SPI_SHADER_32_R
:
650 cb_shader_mask
|= 0x1 << (i
* 4);
652 case V_028714_SPI_SHADER_32_GR
:
653 cb_shader_mask
|= 0x3 << (i
* 4);
655 case V_028714_SPI_SHADER_32_AR
:
656 cb_shader_mask
|= 0x9 << (i
* 4);
658 case V_028714_SPI_SHADER_FP16_ABGR
:
659 case V_028714_SPI_SHADER_UNORM16_ABGR
:
660 case V_028714_SPI_SHADER_SNORM16_ABGR
:
661 case V_028714_SPI_SHADER_UINT16_ABGR
:
662 case V_028714_SPI_SHADER_SINT16_ABGR
:
663 case V_028714_SPI_SHADER_32_ABGR
:
664 cb_shader_mask
|= 0xf << (i
* 4);
670 return cb_shader_mask
;
673 static void si_shader_ps(struct si_shader
*shader
)
675 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
676 struct si_pm4_state
*pm4
;
677 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
678 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
680 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
682 /* we need to enable at least one of them, otherwise we hang the GPU */
683 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
684 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
685 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
686 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
687 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
688 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
689 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
690 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
692 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
697 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
699 * 0 -> Position = pixel center
700 * 1 -> Position = pixel centroid
701 * 2 -> Position = at sample position
703 * From GLSL 4.5 specification, section 7.1:
704 * "The variable gl_FragCoord is available as an input variable from
705 * within fragment shaders and it holds the window relative coordinates
706 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
707 * value can be for any location within the pixel, or one of the
708 * fragment samples. The use of centroid does not further restrict
709 * this value to be inside the current primitive."
711 * Meaning that centroid has no effect and we can return anything within
712 * the pixel. Thus, return the value at sample position, because that's
713 * the most accurate one shaders can get.
715 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
717 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
718 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
719 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
721 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
722 cb_shader_mask
= si_get_cb_shader_mask(spi_shader_col_format
);
724 /* Ensure that some export memory is always allocated, for two reasons:
726 * 1) Correctness: The hardware ignores the EXEC mask if no export
727 * memory is allocated, so KILL and alpha test do not work correctly
729 * 2) Performance: Every shader needs at least a NULL export, even when
730 * it writes no color/depth output. The NULL export instruction
731 * stalls without this setting.
733 * Don't add this to CB_SHADER_MASK.
735 if (!spi_shader_col_format
&&
736 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
737 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
739 si_pm4_set_reg(pm4
, R_0286CC_SPI_PS_INPUT_ENA
, input_ena
);
740 si_pm4_set_reg(pm4
, R_0286D0_SPI_PS_INPUT_ADDR
,
741 shader
->config
.spi_ps_input_addr
);
743 /* Set interpolation controls. */
744 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
));
747 si_pm4_set_reg(pm4
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
748 si_pm4_set_reg(pm4
, R_0286D8_SPI_PS_IN_CONTROL
, spi_ps_in_control
);
750 si_pm4_set_reg(pm4
, R_028710_SPI_SHADER_Z_FORMAT
,
751 info
->writes_samplemask
? V_028710_SPI_SHADER_32_ABGR
:
752 info
->writes_stencil
? V_028710_SPI_SHADER_32_GR
:
753 info
->writes_z
? V_028710_SPI_SHADER_32_R
:
754 V_028710_SPI_SHADER_ZERO
);
756 si_pm4_set_reg(pm4
, R_028714_SPI_SHADER_COL_FORMAT
, spi_shader_col_format
);
757 si_pm4_set_reg(pm4
, R_02823C_CB_SHADER_MASK
, cb_shader_mask
);
759 va
= shader
->bo
->gpu_address
;
760 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
761 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
762 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, va
>> 40);
764 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
,
765 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
766 S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
767 S_00B028_DX10_CLAMP(1) |
768 S_00B028_FLOAT_MODE(shader
->config
.float_mode
));
769 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
770 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
771 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
772 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
774 /* Prefer RE_Z if the shader is complex enough. The requirement is either:
775 * - the shader uses at least 2 VMEM instructions, or
776 * - the code size is at least 50 2-dword instructions or 100 1-dword
779 * Shaders with side effects that must execute independently of the
780 * depth test require LATE_Z.
782 if (info
->writes_memory
&&
783 !info
->properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
])
784 shader
->z_order
= V_02880C_LATE_Z
;
785 else if (info
->num_memory_instructions
>= 2 ||
786 shader
->binary
.code_size
> 100*4)
787 shader
->z_order
= V_02880C_EARLY_Z_THEN_RE_Z
;
789 shader
->z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
792 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
793 struct si_shader
*shader
)
797 si_pm4_free_state_simple(shader
->pm4
);
799 switch (shader
->selector
->type
) {
800 case PIPE_SHADER_VERTEX
:
801 if (shader
->key
.vs
.as_ls
)
802 si_shader_ls(shader
);
803 else if (shader
->key
.vs
.as_es
)
804 si_shader_es(sscreen
, shader
);
806 si_shader_vs(sscreen
, shader
, NULL
);
808 case PIPE_SHADER_TESS_CTRL
:
809 si_shader_hs(shader
);
811 case PIPE_SHADER_TESS_EVAL
:
812 if (shader
->key
.tes
.as_es
)
813 si_shader_es(sscreen
, shader
);
815 si_shader_vs(sscreen
, shader
, NULL
);
817 case PIPE_SHADER_GEOMETRY
:
818 si_shader_gs(shader
);
819 si_shader_vs(sscreen
, shader
->gs_copy_shader
, shader
);
821 case PIPE_SHADER_FRAGMENT
:
822 si_shader_ps(shader
);
829 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
831 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
832 if (sctx
->queued
.named
.dsa
&&
833 !sctx
->framebuffer
.cb0_is_integer
)
834 return sctx
->queued
.named
.dsa
->alpha_func
;
836 return PIPE_FUNC_ALWAYS
;
839 /* Compute the key for the hw shader variant */
840 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
841 struct si_shader_selector
*sel
,
842 union si_shader_key
*key
)
844 struct si_context
*sctx
= (struct si_context
*)ctx
;
847 memset(key
, 0, sizeof(*key
));
850 case PIPE_SHADER_VERTEX
:
851 if (sctx
->vertex_elements
) {
852 unsigned count
= MIN2(sel
->info
.num_inputs
,
853 sctx
->vertex_elements
->count
);
854 for (i
= 0; i
< count
; ++i
)
855 key
->vs
.prolog
.instance_divisors
[i
] =
856 sctx
->vertex_elements
->elements
[i
].instance_divisor
;
858 if (sctx
->tes_shader
.cso
)
860 else if (sctx
->gs_shader
.cso
)
863 if (!sctx
->gs_shader
.cso
&& sctx
->ps_shader
.cso
&&
864 sctx
->ps_shader
.cso
->info
.uses_primid
)
865 key
->vs
.epilog
.export_prim_id
= 1;
867 case PIPE_SHADER_TESS_CTRL
:
868 key
->tcs
.epilog
.prim_mode
=
869 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
871 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
872 key
->tcs
.epilog
.inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
874 case PIPE_SHADER_TESS_EVAL
:
875 if (sctx
->gs_shader
.cso
)
877 else if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
878 key
->tes
.epilog
.export_prim_id
= 1;
880 case PIPE_SHADER_GEOMETRY
:
882 case PIPE_SHADER_FRAGMENT
: {
883 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
884 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
886 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
887 sel
->info
.colors_written
== 0x1)
888 key
->ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
891 /* Select the shader color format based on whether
892 * blending or alpha are needed.
894 key
->ps
.epilog
.spi_shader_col_format
=
895 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
896 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
897 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
898 sctx
->framebuffer
.spi_shader_col_format_blend
) |
899 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
900 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
901 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
902 sctx
->framebuffer
.spi_shader_col_format
);
904 /* The output for dual source blending should have
905 * the same format as the first output.
907 if (blend
->dual_src_blend
)
908 key
->ps
.epilog
.spi_shader_col_format
|=
909 (key
->ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
911 key
->ps
.epilog
.spi_shader_col_format
= sctx
->framebuffer
.spi_shader_col_format
;
913 /* If alpha-to-coverage is enabled, we have to export alpha
914 * even if there is no color buffer.
916 if (!(key
->ps
.epilog
.spi_shader_col_format
& 0xf) &&
917 blend
&& blend
->alpha_to_coverage
)
918 key
->ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
920 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
921 * to the range supported by the type if a channel has less
922 * than 16 bits and the export format is 16_ABGR.
924 if (sctx
->b
.chip_class
<= CIK
&& sctx
->b
.family
!= CHIP_HAWAII
)
925 key
->ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
927 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
928 if (!key
->ps
.epilog
.last_cbuf
) {
929 key
->ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
930 key
->ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
934 bool is_poly
= (sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES
&&
935 sctx
->current_rast_prim
<= PIPE_PRIM_POLYGON
) ||
936 sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES_ADJACENCY
;
937 bool is_line
= !is_poly
&& sctx
->current_rast_prim
!= PIPE_PRIM_POINTS
;
939 key
->ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
940 key
->ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
942 if (sctx
->queued
.named
.blend
) {
943 key
->ps
.epilog
.alpha_to_one
= sctx
->queued
.named
.blend
->alpha_to_one
&&
944 rs
->multisample_enable
&&
945 !sctx
->framebuffer
.cb0_is_integer
;
948 key
->ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
949 key
->ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
950 (is_line
&& rs
->line_smooth
)) &&
951 sctx
->framebuffer
.nr_samples
<= 1;
952 key
->ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
954 if (rs
->force_persample_interp
&&
955 rs
->multisample_enable
&&
956 sctx
->framebuffer
.nr_samples
> 1 &&
957 sctx
->ps_iter_samples
> 1) {
958 key
->ps
.prolog
.force_persp_sample_interp
=
959 sel
->info
.uses_persp_center
||
960 sel
->info
.uses_persp_centroid
;
962 key
->ps
.prolog
.force_linear_sample_interp
=
963 sel
->info
.uses_linear_center
||
964 sel
->info
.uses_linear_centroid
;
965 } else if (rs
->multisample_enable
&&
966 sctx
->framebuffer
.nr_samples
> 1) {
967 key
->ps
.prolog
.bc_optimize_for_persp
=
968 sel
->info
.uses_persp_center
&&
969 sel
->info
.uses_persp_centroid
;
970 key
->ps
.prolog
.bc_optimize_for_linear
=
971 sel
->info
.uses_linear_center
&&
972 sel
->info
.uses_linear_centroid
;
974 /* Make sure SPI doesn't compute more than 1 pair
975 * of (i,j), which is the optimization here. */
976 key
->ps
.prolog
.force_persp_center_interp
=
977 sel
->info
.uses_persp_center
+
978 sel
->info
.uses_persp_centroid
+
979 sel
->info
.uses_persp_sample
> 1;
981 key
->ps
.prolog
.force_linear_center_interp
=
982 sel
->info
.uses_linear_center
+
983 sel
->info
.uses_linear_centroid
+
984 sel
->info
.uses_linear_sample
> 1;
988 key
->ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
996 /* Select the hw shader variant depending on the current state. */
997 static int si_shader_select_with_key(struct si_screen
*sscreen
,
998 struct si_shader_ctx_state
*state
,
999 union si_shader_key
*key
,
1000 LLVMTargetMachineRef tm
,
1001 struct pipe_debug_callback
*debug
,
1003 bool is_debug_context
)
1005 struct si_shader_selector
*sel
= state
->cso
;
1006 struct si_shader
*current
= state
->current
;
1007 struct si_shader
*iter
, *shader
= NULL
;
1010 /* Check if we don't need to change anything.
1011 * This path is also used for most shaders that don't need multiple
1012 * variants, it will cost just a computation of the key and this
1014 if (likely(current
&& memcmp(¤t
->key
, key
, sizeof(*key
)) == 0))
1017 /* This must be done before the mutex is locked, because async GS
1018 * compilation calls this function too, and therefore must enter
1022 util_queue_job_wait(&sel
->ready
);
1024 pipe_mutex_lock(sel
->mutex
);
1026 /* Find the shader variant. */
1027 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
1028 /* Don't check the "current" shader. We checked it above. */
1029 if (current
!= iter
&&
1030 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
1031 state
->current
= iter
;
1032 pipe_mutex_unlock(sel
->mutex
);
1037 /* Build a new shader. */
1038 shader
= CALLOC_STRUCT(si_shader
);
1040 pipe_mutex_unlock(sel
->mutex
);
1043 shader
->selector
= sel
;
1046 r
= si_shader_create(sscreen
, tm
, shader
, debug
);
1048 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1051 pipe_mutex_unlock(sel
->mutex
);
1055 if (is_debug_context
) {
1056 FILE *f
= open_memstream(&shader
->shader_log
,
1057 &shader
->shader_log_size
);
1059 si_shader_dump(sscreen
, shader
, NULL
, sel
->type
, f
);
1064 si_shader_init_pm4_state(sscreen
, shader
);
1066 if (!sel
->last_variant
) {
1067 sel
->first_variant
= shader
;
1068 sel
->last_variant
= shader
;
1070 sel
->last_variant
->next_variant
= shader
;
1071 sel
->last_variant
= shader
;
1073 state
->current
= shader
;
1074 pipe_mutex_unlock(sel
->mutex
);
1078 static int si_shader_select(struct pipe_context
*ctx
,
1079 struct si_shader_ctx_state
*state
)
1081 struct si_context
*sctx
= (struct si_context
*)ctx
;
1082 union si_shader_key key
;
1084 si_shader_selector_key(ctx
, state
->cso
, &key
);
1085 return si_shader_select_with_key(sctx
->screen
, state
, &key
,
1086 sctx
->tm
, &sctx
->b
.debug
, true,
1090 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
1091 union si_shader_key
*key
)
1093 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
1095 switch (info
->processor
) {
1096 case PIPE_SHADER_VERTEX
:
1097 switch (next_shader
) {
1098 case PIPE_SHADER_GEOMETRY
:
1101 case PIPE_SHADER_TESS_CTRL
:
1102 case PIPE_SHADER_TESS_EVAL
:
1108 case PIPE_SHADER_TESS_EVAL
:
1109 if (next_shader
== PIPE_SHADER_GEOMETRY
)
1116 * Compile the main shader part or the monolithic shader as part of
1117 * si_shader_selector initialization. Since it can be done asynchronously,
1118 * there is no way to report compile failures to applications.
1120 void si_init_shader_selector_async(void *job
, int thread_index
)
1122 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
1123 struct si_screen
*sscreen
= sel
->screen
;
1124 LLVMTargetMachineRef tm
;
1125 struct pipe_debug_callback
*debug
= &sel
->debug
;
1128 if (thread_index
>= 0) {
1129 assert(thread_index
< ARRAY_SIZE(sscreen
->tm
));
1130 tm
= sscreen
->tm
[thread_index
];
1137 /* Compile the main shader part for use with a prolog and/or epilog.
1138 * If this fails, the driver will try to compile a monolithic shader
1141 if (sel
->type
!= PIPE_SHADER_GEOMETRY
&&
1142 !sscreen
->use_monolithic_shaders
) {
1143 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
1147 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
1151 shader
->selector
= sel
;
1152 si_parse_next_shader_property(&sel
->info
, &shader
->key
);
1154 tgsi_binary
= si_get_tgsi_binary(sel
);
1156 /* Try to load the shader from the shader cache. */
1157 pipe_mutex_lock(sscreen
->shader_cache_mutex
);
1160 si_shader_cache_load_shader(sscreen
, tgsi_binary
, shader
)) {
1162 pipe_mutex_unlock(sscreen
->shader_cache_mutex
);
1164 pipe_mutex_unlock(sscreen
->shader_cache_mutex
);
1166 /* Compile the shader if it hasn't been loaded from the cache. */
1167 if (si_compile_tgsi_shader(sscreen
, tm
, shader
, false,
1171 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
1176 pipe_mutex_lock(sscreen
->shader_cache_mutex
);
1177 if (!si_shader_cache_insert_shader(sscreen
, tgsi_binary
, shader
))
1179 pipe_mutex_unlock(sscreen
->shader_cache_mutex
);
1183 sel
->main_shader_part
= shader
;
1186 /* Pre-compilation. */
1187 if (sel
->type
== PIPE_SHADER_GEOMETRY
||
1188 sscreen
->b
.debug_flags
& DBG_PRECOMPILE
) {
1189 struct si_shader_ctx_state state
= {sel
};
1190 union si_shader_key key
;
1192 memset(&key
, 0, sizeof(key
));
1193 si_parse_next_shader_property(&sel
->info
, &key
);
1195 /* Set reasonable defaults, so that the shader key doesn't
1196 * cause any code to be eliminated.
1198 switch (sel
->type
) {
1199 case PIPE_SHADER_TESS_CTRL
:
1200 key
.tcs
.epilog
.prim_mode
= PIPE_PRIM_TRIANGLES
;
1202 case PIPE_SHADER_FRAGMENT
:
1203 key
.ps
.epilog
.alpha_func
= PIPE_FUNC_ALWAYS
;
1204 for (i
= 0; i
< 8; i
++)
1205 if (sel
->info
.colors_written
& (1 << i
))
1206 key
.ps
.epilog
.spi_shader_col_format
|=
1207 V_028710_SPI_SHADER_FP16_ABGR
<< (i
* 4);
1211 if (si_shader_select_with_key(sscreen
, &state
, &key
, tm
, debug
,
1212 false, sel
->is_debug_context
))
1213 fprintf(stderr
, "radeonsi: can't create a monolithic shader\n");
1217 static void *si_create_shader_selector(struct pipe_context
*ctx
,
1218 const struct pipe_shader_state
*state
)
1220 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
1221 struct si_context
*sctx
= (struct si_context
*)ctx
;
1222 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
1228 sel
->screen
= sscreen
;
1230 sel
->debug
= sctx
->b
.debug
;
1231 sel
->is_debug_context
= sctx
->is_debug
;
1232 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
1238 sel
->so
= state
->stream_output
;
1239 tgsi_scan_shader(state
->tokens
, &sel
->info
);
1240 sel
->type
= sel
->info
.processor
;
1241 p_atomic_inc(&sscreen
->b
.num_shaders_created
);
1243 /* Set which opcode uses which (i,j) pair. */
1244 if (sel
->info
.uses_persp_opcode_interp_centroid
)
1245 sel
->info
.uses_persp_centroid
= true;
1247 if (sel
->info
.uses_linear_opcode_interp_centroid
)
1248 sel
->info
.uses_linear_centroid
= true;
1250 if (sel
->info
.uses_persp_opcode_interp_offset
||
1251 sel
->info
.uses_persp_opcode_interp_sample
)
1252 sel
->info
.uses_persp_center
= true;
1254 if (sel
->info
.uses_linear_opcode_interp_offset
||
1255 sel
->info
.uses_linear_opcode_interp_sample
)
1256 sel
->info
.uses_linear_center
= true;
1258 switch (sel
->type
) {
1259 case PIPE_SHADER_GEOMETRY
:
1260 sel
->gs_output_prim
=
1261 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
1262 sel
->gs_max_out_vertices
=
1263 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
1264 sel
->gs_num_invocations
=
1265 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
1266 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
1267 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
1268 sel
->gs_max_out_vertices
;
1270 sel
->max_gs_stream
= 0;
1271 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
1272 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
1273 sel
->so
.output
[i
].stream
);
1275 sel
->gs_input_verts_per_prim
=
1276 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
1279 case PIPE_SHADER_TESS_CTRL
:
1280 /* Always reserve space for these. */
1281 sel
->patch_outputs_written
|=
1282 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER
, 0)) |
1283 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER
, 0));
1285 case PIPE_SHADER_VERTEX
:
1286 case PIPE_SHADER_TESS_EVAL
:
1287 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
1288 unsigned name
= sel
->info
.output_semantic_name
[i
];
1289 unsigned index
= sel
->info
.output_semantic_index
[i
];
1292 case TGSI_SEMANTIC_TESSINNER
:
1293 case TGSI_SEMANTIC_TESSOUTER
:
1294 case TGSI_SEMANTIC_PATCH
:
1295 sel
->patch_outputs_written
|=
1296 1llu << si_shader_io_get_unique_index(name
, index
);
1299 sel
->outputs_written
|=
1300 1llu << si_shader_io_get_unique_index(name
, index
);
1303 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
1306 case PIPE_SHADER_FRAGMENT
:
1307 for (i
= 0; i
< 8; i
++)
1308 if (sel
->info
.colors_written
& (1 << i
))
1309 sel
->colors_written_4bit
|= 0xf << (4 * i
);
1311 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
1312 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
1313 int index
= sel
->info
.input_semantic_index
[i
];
1314 sel
->color_attr_index
[index
] = i
;
1320 /* DB_SHADER_CONTROL */
1321 sel
->db_shader_control
=
1322 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
1323 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
1324 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
1325 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
1327 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
1328 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
1329 sel
->db_shader_control
|=
1330 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
1332 case TGSI_FS_DEPTH_LAYOUT_LESS
:
1333 sel
->db_shader_control
|=
1334 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
1338 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
])
1339 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1);
1341 if (sel
->info
.writes_memory
)
1342 sel
->db_shader_control
|= S_02880C_EXEC_ON_HIER_FAIL(1) |
1343 S_02880C_EXEC_ON_NOOP(1);
1344 pipe_mutex_init(sel
->mutex
);
1345 util_queue_fence_init(&sel
->ready
);
1347 if ((sctx
->b
.debug
.debug_message
&& !sctx
->b
.debug
.async
) ||
1349 r600_can_dump_shader(&sscreen
->b
, sel
->info
.processor
) ||
1350 !util_queue_is_initialized(&sscreen
->shader_compiler_queue
))
1351 si_init_shader_selector_async(sel
, -1);
1353 util_queue_add_job(&sscreen
->shader_compiler_queue
, sel
,
1354 &sel
->ready
, si_init_shader_selector_async
,
1360 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
1362 struct si_context
*sctx
= (struct si_context
*)ctx
;
1363 struct si_shader_selector
*sel
= state
;
1365 if (sctx
->vs_shader
.cso
== sel
)
1368 sctx
->vs_shader
.cso
= sel
;
1369 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
1370 sctx
->do_update_shaders
= true;
1371 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
1372 r600_update_vs_writes_viewport_index(&sctx
->b
, si_get_vs_info(sctx
));
1375 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
1377 struct si_context
*sctx
= (struct si_context
*)ctx
;
1378 struct si_shader_selector
*sel
= state
;
1379 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
1381 if (sctx
->gs_shader
.cso
== sel
)
1384 sctx
->gs_shader
.cso
= sel
;
1385 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
1386 sctx
->do_update_shaders
= true;
1387 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
1388 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
1391 si_shader_change_notify(sctx
);
1392 r600_update_vs_writes_viewport_index(&sctx
->b
, si_get_vs_info(sctx
));
1395 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
1397 struct si_context
*sctx
= (struct si_context
*)ctx
;
1398 struct si_shader_selector
*sel
= state
;
1399 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
1401 if (sctx
->tcs_shader
.cso
== sel
)
1404 sctx
->tcs_shader
.cso
= sel
;
1405 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
1406 sctx
->do_update_shaders
= true;
1409 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
1412 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
1414 struct si_context
*sctx
= (struct si_context
*)ctx
;
1415 struct si_shader_selector
*sel
= state
;
1416 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
1418 if (sctx
->tes_shader
.cso
== sel
)
1421 sctx
->tes_shader
.cso
= sel
;
1422 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
1423 sctx
->do_update_shaders
= true;
1424 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
1425 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
1427 if (enable_changed
) {
1428 si_shader_change_notify(sctx
);
1429 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
1431 r600_update_vs_writes_viewport_index(&sctx
->b
, si_get_vs_info(sctx
));
1434 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
1436 struct si_context
*sctx
= (struct si_context
*)ctx
;
1437 struct si_shader_selector
*sel
= state
;
1439 /* skip if supplied shader is one already in use */
1440 if (sctx
->ps_shader
.cso
== sel
)
1443 sctx
->ps_shader
.cso
= sel
;
1444 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
1445 sctx
->do_update_shaders
= true;
1446 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
1449 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
1452 switch (shader
->selector
->type
) {
1453 case PIPE_SHADER_VERTEX
:
1454 if (shader
->key
.vs
.as_ls
)
1455 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
1456 else if (shader
->key
.vs
.as_es
)
1457 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
1459 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
1461 case PIPE_SHADER_TESS_CTRL
:
1462 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
1464 case PIPE_SHADER_TESS_EVAL
:
1465 if (shader
->key
.tes
.as_es
)
1466 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
1468 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
1470 case PIPE_SHADER_GEOMETRY
:
1471 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
1472 si_pm4_delete_state(sctx
, vs
, shader
->gs_copy_shader
->pm4
);
1474 case PIPE_SHADER_FRAGMENT
:
1475 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
1480 si_shader_destroy(shader
);
1484 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
1486 struct si_context
*sctx
= (struct si_context
*)ctx
;
1487 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
1488 struct si_shader
*p
= sel
->first_variant
, *c
;
1489 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
1490 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
1491 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
1492 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
1493 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
1494 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
1497 util_queue_job_wait(&sel
->ready
);
1499 if (current_shader
[sel
->type
]->cso
== sel
) {
1500 current_shader
[sel
->type
]->cso
= NULL
;
1501 current_shader
[sel
->type
]->current
= NULL
;
1505 c
= p
->next_variant
;
1506 si_delete_shader(sctx
, p
);
1510 if (sel
->main_shader_part
)
1511 si_delete_shader(sctx
, sel
->main_shader_part
);
1513 util_queue_fence_destroy(&sel
->ready
);
1514 pipe_mutex_destroy(sel
->mutex
);
1519 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
1520 struct si_shader
*vs
, unsigned name
,
1521 unsigned index
, unsigned interpolate
)
1523 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
1524 unsigned j
, ps_input_cntl
= 0;
1526 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
1527 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
))
1528 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
1530 if (name
== TGSI_SEMANTIC_PCOORD
||
1531 (name
== TGSI_SEMANTIC_TEXCOORD
&&
1532 sctx
->sprite_coord_enable
& (1 << index
))) {
1533 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
1536 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
1537 if (name
== vsinfo
->output_semantic_name
[j
] &&
1538 index
== vsinfo
->output_semantic_index
[j
]) {
1539 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[j
]);
1544 if (name
== TGSI_SEMANTIC_PRIMID
)
1545 /* PrimID is written after the last output. */
1546 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
1547 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
1548 /* No corresponding output found, load defaults into input.
1549 * Don't set any other bits.
1550 * (FLAT_SHADE=1 completely changes behavior) */
1551 ps_input_cntl
= S_028644_OFFSET(0x20);
1552 /* D3D 9 behaviour. GL is undefined */
1553 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
1554 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
1556 return ps_input_cntl
;
1559 static void si_emit_spi_map(struct si_context
*sctx
, struct r600_atom
*atom
)
1561 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1562 struct si_shader
*ps
= sctx
->ps_shader
.current
;
1563 struct si_shader
*vs
= si_get_vs_state(sctx
);
1564 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
1565 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
1567 if (!ps
|| !ps
->selector
->info
.num_inputs
)
1570 num_interp
= si_get_ps_num_interp(ps
);
1571 assert(num_interp
> 0);
1572 radeon_set_context_reg_seq(cs
, R_028644_SPI_PS_INPUT_CNTL_0
, num_interp
);
1574 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
1575 unsigned name
= psinfo
->input_semantic_name
[i
];
1576 unsigned index
= psinfo
->input_semantic_index
[i
];
1577 unsigned interpolate
= psinfo
->input_interpolate
[i
];
1579 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, name
, index
,
1583 if (name
== TGSI_SEMANTIC_COLOR
) {
1584 assert(index
< ARRAY_SIZE(bcol_interp
));
1585 bcol_interp
[index
] = interpolate
;
1589 if (ps
->key
.ps
.prolog
.color_two_side
) {
1590 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
1592 for (i
= 0; i
< 2; i
++) {
1593 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
1596 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, bcol
,
1597 i
, bcol_interp
[i
]));
1601 assert(num_interp
== num_written
);
1605 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
1607 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
1609 if (sctx
->init_config_has_vgt_flush
)
1612 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
1613 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
1614 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
1615 si_pm4_cmd_end(sctx
->init_config
, false);
1616 sctx
->init_config_has_vgt_flush
= true;
1619 /* Initialize state related to ESGS / GSVS ring buffers */
1620 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
1622 struct si_shader_selector
*es
=
1623 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
1624 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
1625 struct si_pm4_state
*pm4
;
1627 /* Chip constants. */
1628 unsigned num_se
= sctx
->screen
->b
.info
.max_se
;
1629 unsigned wave_size
= 64;
1630 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1631 unsigned gs_vertex_reuse
= 16 * num_se
; /* GS_VERTEX_REUSE register (per SE) */
1632 unsigned alignment
= 256 * num_se
;
1633 /* The maximum size is 63.999 MB per SE. */
1634 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1636 /* Calculate the minimum size. */
1637 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
1638 wave_size
, alignment
);
1640 /* These are recommended sizes, not minimum sizes. */
1641 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1642 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
1643 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1644 gs
->max_gsvs_emit_size
* (gs
->max_gs_stream
+ 1);
1646 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1647 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1648 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1650 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1651 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1653 /* Some rings don't have to be allocated if shaders don't use them.
1654 * (e.g. no varyings between ES and GS or GS and VS)
1656 bool update_esgs
= esgs_ring_size
&&
1657 (!sctx
->esgs_ring
||
1658 sctx
->esgs_ring
->width0
< esgs_ring_size
);
1659 bool update_gsvs
= gsvs_ring_size
&&
1660 (!sctx
->gsvs_ring
||
1661 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
1663 if (!update_esgs
&& !update_gsvs
)
1667 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
1668 sctx
->esgs_ring
= pipe_buffer_create(sctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1671 if (!sctx
->esgs_ring
)
1676 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
1677 sctx
->gsvs_ring
= pipe_buffer_create(sctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1680 if (!sctx
->gsvs_ring
)
1684 /* Create the "init_config_gs_rings" state. */
1685 pm4
= CALLOC_STRUCT(si_pm4_state
);
1689 if (sctx
->b
.chip_class
>= CIK
) {
1690 if (sctx
->esgs_ring
)
1691 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
1692 sctx
->esgs_ring
->width0
/ 256);
1693 if (sctx
->gsvs_ring
)
1694 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
1695 sctx
->gsvs_ring
->width0
/ 256);
1697 if (sctx
->esgs_ring
)
1698 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
1699 sctx
->esgs_ring
->width0
/ 256);
1700 if (sctx
->gsvs_ring
)
1701 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
1702 sctx
->gsvs_ring
->width0
/ 256);
1705 /* Set the state. */
1706 if (sctx
->init_config_gs_rings
)
1707 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
1708 sctx
->init_config_gs_rings
= pm4
;
1710 if (!sctx
->init_config_has_vgt_flush
) {
1711 si_init_config_add_vgt_flush(sctx
);
1712 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
1715 /* Flush the context to re-emit both init_config states. */
1716 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
1717 si_context_gfx_flush(sctx
, RADEON_FLUSH_ASYNC
, NULL
);
1719 /* Set ring bindings. */
1720 if (sctx
->esgs_ring
) {
1721 si_set_ring_buffer(&sctx
->b
.b
, SI_ES_RING_ESGS
,
1722 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
1723 true, true, 4, 64, 0);
1724 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_ESGS
,
1725 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
1726 false, false, 0, 0, 0);
1728 if (sctx
->gsvs_ring
)
1729 si_set_ring_buffer(&sctx
->b
.b
, SI_VS_RING_GSVS
,
1730 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
1731 false, false, 0, 0, 0);
1735 static void si_update_gsvs_ring_bindings(struct si_context
*sctx
)
1737 unsigned gsvs_itemsize
= sctx
->gs_shader
.cso
->max_gsvs_emit_size
;
1740 if (!sctx
->gsvs_ring
|| gsvs_itemsize
== sctx
->last_gsvs_itemsize
)
1743 sctx
->last_gsvs_itemsize
= gsvs_itemsize
;
1745 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_GSVS0
,
1746 sctx
->gsvs_ring
, gsvs_itemsize
,
1747 64, true, true, 4, 16, 0);
1749 offset
= gsvs_itemsize
* 64;
1750 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_GSVS1
,
1751 sctx
->gsvs_ring
, gsvs_itemsize
,
1752 64, true, true, 4, 16, offset
);
1754 offset
= (gsvs_itemsize
* 2) * 64;
1755 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_GSVS2
,
1756 sctx
->gsvs_ring
, gsvs_itemsize
,
1757 64, true, true, 4, 16, offset
);
1759 offset
= (gsvs_itemsize
* 3) * 64;
1760 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_GSVS3
,
1761 sctx
->gsvs_ring
, gsvs_itemsize
,
1762 64, true, true, 4, 16, offset
);
1766 * @returns 1 if \p sel has been updated to use a new scratch buffer
1768 * < 0 if there was a failure
1770 static int si_update_scratch_buffer(struct si_context
*sctx
,
1771 struct si_shader
*shader
)
1773 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
1779 /* This shader doesn't need a scratch buffer */
1780 if (shader
->config
.scratch_bytes_per_wave
== 0)
1783 /* This shader is already configured to use the current
1784 * scratch buffer. */
1785 if (shader
->scratch_bo
== sctx
->scratch_buffer
)
1788 assert(sctx
->scratch_buffer
);
1790 si_shader_apply_scratch_relocs(sctx
, shader
, &shader
->config
, scratch_va
);
1792 /* Replace the shader bo with a new bo that has the relocs applied. */
1793 r
= si_shader_binary_upload(sctx
->screen
, shader
);
1797 /* Update the shader state to use the new shader bo. */
1798 si_shader_init_pm4_state(sctx
->screen
, shader
);
1800 r600_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
1805 static unsigned si_get_current_scratch_buffer_size(struct si_context
*sctx
)
1807 return sctx
->scratch_buffer
? sctx
->scratch_buffer
->b
.b
.width0
: 0;
1810 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
1812 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
1815 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context
*sctx
)
1819 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
1820 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
1821 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
1822 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tcs_shader
.current
));
1823 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
1827 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
1829 unsigned current_scratch_buffer_size
=
1830 si_get_current_scratch_buffer_size(sctx
);
1831 unsigned scratch_bytes_per_wave
=
1832 si_get_max_scratch_bytes_per_wave(sctx
);
1833 unsigned scratch_needed_size
= scratch_bytes_per_wave
*
1834 sctx
->scratch_waves
;
1835 unsigned spi_tmpring_size
;
1838 if (scratch_needed_size
> 0) {
1839 if (scratch_needed_size
> current_scratch_buffer_size
) {
1840 /* Create a bigger scratch buffer */
1841 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
1843 sctx
->scratch_buffer
=
1844 si_resource_create_custom(&sctx
->screen
->b
.b
,
1845 PIPE_USAGE_DEFAULT
, scratch_needed_size
);
1846 if (!sctx
->scratch_buffer
)
1848 sctx
->emit_scratch_reloc
= true;
1851 /* Update the shaders, so they are using the latest scratch. The
1852 * scratch buffer may have been changed since these shaders were
1853 * last used, so we still need to try to update them, even if
1854 * they require scratch buffers smaller than the current size.
1856 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
1860 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
1862 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
1866 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
1868 r
= si_update_scratch_buffer(sctx
, sctx
->tcs_shader
.current
);
1872 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
1874 /* VS can be bound as LS, ES, or VS. */
1875 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
1879 if (sctx
->tes_shader
.current
)
1880 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
1881 else if (sctx
->gs_shader
.current
)
1882 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
1884 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
1887 /* TES can be bound as ES or VS. */
1888 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
1892 if (sctx
->gs_shader
.current
)
1893 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
1895 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
1899 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
1900 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
1901 "scratch size should already be aligned correctly.");
1903 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
1904 S_0286E8_WAVESIZE(scratch_bytes_per_wave
>> 10);
1905 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
1906 sctx
->spi_tmpring_size
= spi_tmpring_size
;
1907 sctx
->emit_scratch_reloc
= true;
1912 static void si_init_tess_factor_ring(struct si_context
*sctx
)
1914 bool double_offchip_buffers
= sctx
->b
.chip_class
>= CIK
;
1915 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
1916 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
1917 sctx
->screen
->b
.info
.max_se
;
1918 unsigned offchip_granularity
;
1920 switch (sctx
->screen
->tess_offchip_block_dw_size
) {
1925 offchip_granularity
= V_03093C_X_8K_DWORDS
;
1928 offchip_granularity
= V_03093C_X_4K_DWORDS
;
1932 switch (sctx
->b
.chip_class
) {
1934 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
1937 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
1941 max_offchip_buffers
= MIN2(max_offchip_buffers
, 512);
1945 assert(!sctx
->tf_ring
);
1946 sctx
->tf_ring
= pipe_buffer_create(sctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1948 32768 * sctx
->screen
->b
.info
.max_se
);
1952 assert(((sctx
->tf_ring
->width0
/ 4) & C_030938_SIZE
) == 0);
1954 sctx
->tess_offchip_ring
= pipe_buffer_create(sctx
->b
.b
.screen
,
1957 max_offchip_buffers
*
1958 sctx
->screen
->tess_offchip_block_dw_size
* 4);
1959 if (!sctx
->tess_offchip_ring
)
1962 si_init_config_add_vgt_flush(sctx
);
1964 /* Append these registers to the init config state. */
1965 if (sctx
->b
.chip_class
>= CIK
) {
1966 if (sctx
->b
.chip_class
>= VI
)
1967 --max_offchip_buffers
;
1969 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
1970 S_030938_SIZE(sctx
->tf_ring
->width0
/ 4));
1971 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
1972 r600_resource(sctx
->tf_ring
)->gpu_address
>> 8);
1973 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
1974 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
1975 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
));
1977 assert(offchip_granularity
== V_03093C_X_8K_DWORDS
);
1978 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
1979 S_008988_SIZE(sctx
->tf_ring
->width0
/ 4));
1980 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
1981 r600_resource(sctx
->tf_ring
)->gpu_address
>> 8);
1982 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
1983 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
));
1986 /* Flush the context to re-emit the init_config state.
1987 * This is done only once in a lifetime of a context.
1989 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
1990 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
1991 si_context_gfx_flush(sctx
, RADEON_FLUSH_ASYNC
, NULL
);
1993 si_set_ring_buffer(&sctx
->b
.b
, SI_HS_RING_TESS_FACTOR
, sctx
->tf_ring
,
1994 0, sctx
->tf_ring
->width0
, false, false, 0, 0, 0);
1996 si_set_ring_buffer(&sctx
->b
.b
, SI_HS_RING_TESS_OFFCHIP
,
1997 sctx
->tess_offchip_ring
, 0,
1998 sctx
->tess_offchip_ring
->width0
, false, false, 0, 0, 0);
2002 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
2003 * VS passes its outputs to TES directly, so the fixed-function shader only
2004 * has to write TESSOUTER and TESSINNER.
2006 static void si_generate_fixed_func_tcs(struct si_context
*sctx
)
2008 struct ureg_src outer
, inner
;
2009 struct ureg_dst tessouter
, tessinner
;
2010 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_TESS_CTRL
);
2013 return; /* if we get here, we're screwed */
2015 assert(!sctx
->fixed_func_tcs_shader
.cso
);
2017 outer
= ureg_DECL_system_value(ureg
,
2018 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
, 0);
2019 inner
= ureg_DECL_system_value(ureg
,
2020 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
, 0);
2022 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
2023 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
2025 ureg_MOV(ureg
, tessouter
, outer
);
2026 ureg_MOV(ureg
, tessinner
, inner
);
2029 sctx
->fixed_func_tcs_shader
.cso
=
2030 ureg_create_shader_and_destroy(ureg
, &sctx
->b
.b
);
2033 static void si_update_vgt_shader_config(struct si_context
*sctx
)
2035 /* Calculate the index of the config.
2036 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
2037 unsigned index
= 2*!!sctx
->tes_shader
.cso
+ !!sctx
->gs_shader
.cso
;
2038 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[index
];
2041 uint32_t stages
= 0;
2043 *pm4
= CALLOC_STRUCT(si_pm4_state
);
2045 if (sctx
->tes_shader
.cso
) {
2046 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
2047 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2049 if (sctx
->gs_shader
.cso
)
2050 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
2052 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
2054 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
2055 } else if (sctx
->gs_shader
.cso
) {
2056 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
2058 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
2061 si_pm4_set_reg(*pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
2063 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
2066 static void si_update_so(struct si_context
*sctx
, struct si_shader_selector
*shader
)
2068 struct pipe_stream_output_info
*so
= &shader
->so
;
2069 uint32_t enabled_stream_buffers_mask
= 0;
2072 for (i
= 0; i
< so
->num_outputs
; i
++)
2073 enabled_stream_buffers_mask
|= (1 << so
->output
[i
].output_buffer
) << (so
->output
[i
].stream
* 4);
2074 sctx
->b
.streamout
.enabled_stream_buffers_mask
= enabled_stream_buffers_mask
;
2075 sctx
->b
.streamout
.stride_in_dw
= shader
->so
.stride
;
2078 bool si_update_shaders(struct si_context
*sctx
)
2080 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
2081 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
2084 /* Update stages before GS. */
2085 if (sctx
->tes_shader
.cso
) {
2086 if (!sctx
->tf_ring
) {
2087 si_init_tess_factor_ring(sctx
);
2093 r
= si_shader_select(ctx
, &sctx
->vs_shader
);
2096 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
2098 if (sctx
->tcs_shader
.cso
) {
2099 r
= si_shader_select(ctx
, &sctx
->tcs_shader
);
2102 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
2104 if (!sctx
->fixed_func_tcs_shader
.cso
) {
2105 si_generate_fixed_func_tcs(sctx
);
2106 if (!sctx
->fixed_func_tcs_shader
.cso
)
2110 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
);
2113 si_pm4_bind_state(sctx
, hs
,
2114 sctx
->fixed_func_tcs_shader
.current
->pm4
);
2117 r
= si_shader_select(ctx
, &sctx
->tes_shader
);
2121 if (sctx
->gs_shader
.cso
) {
2123 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
2126 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
2127 si_update_so(sctx
, sctx
->tes_shader
.cso
);
2129 } else if (sctx
->gs_shader
.cso
) {
2131 r
= si_shader_select(ctx
, &sctx
->vs_shader
);
2134 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
2137 r
= si_shader_select(ctx
, &sctx
->vs_shader
);
2140 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
2141 si_update_so(sctx
, sctx
->vs_shader
.cso
);
2145 if (sctx
->gs_shader
.cso
) {
2146 r
= si_shader_select(ctx
, &sctx
->gs_shader
);
2149 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
2150 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.current
->gs_copy_shader
->pm4
);
2151 si_update_so(sctx
, sctx
->gs_shader
.cso
);
2153 if (!si_update_gs_ring_buffers(sctx
))
2156 si_update_gsvs_ring_bindings(sctx
);
2158 si_pm4_bind_state(sctx
, gs
, NULL
);
2159 si_pm4_bind_state(sctx
, es
, NULL
);
2162 si_update_vgt_shader_config(sctx
);
2164 if (sctx
->ps_shader
.cso
) {
2165 unsigned db_shader_control
;
2167 r
= si_shader_select(ctx
, &sctx
->ps_shader
);
2170 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
2173 sctx
->ps_shader
.cso
->db_shader_control
|
2174 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
) |
2175 S_02880C_Z_ORDER(sctx
->ps_shader
.current
->z_order
);
2177 if (si_pm4_state_changed(sctx
, ps
) || si_pm4_state_changed(sctx
, vs
) ||
2178 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
2179 sctx
->flatshade
!= rs
->flatshade
) {
2180 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
2181 sctx
->flatshade
= rs
->flatshade
;
2182 si_mark_atom_dirty(sctx
, &sctx
->spi_map
);
2185 if (sctx
->b
.family
== CHIP_STONEY
&& si_pm4_state_changed(sctx
, ps
))
2186 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
2188 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
2189 sctx
->ps_db_shader_control
= db_shader_control
;
2190 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
2193 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.ps
.epilog
.poly_line_smoothing
) {
2194 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.ps
.epilog
.poly_line_smoothing
;
2195 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2197 if (sctx
->b
.chip_class
== SI
)
2198 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
2200 if (sctx
->framebuffer
.nr_samples
<= 1)
2201 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
2205 if (si_pm4_state_changed(sctx
, ls
) ||
2206 si_pm4_state_changed(sctx
, hs
) ||
2207 si_pm4_state_changed(sctx
, es
) ||
2208 si_pm4_state_changed(sctx
, gs
) ||
2209 si_pm4_state_changed(sctx
, vs
) ||
2210 si_pm4_state_changed(sctx
, ps
)) {
2211 if (!si_update_spi_tmpring_size(sctx
))
2215 sctx
->do_update_shaders
= false;
2219 void si_init_shader_functions(struct si_context
*sctx
)
2221 si_init_atom(sctx
, &sctx
->spi_map
, &sctx
->atoms
.s
.spi_map
, si_emit_spi_map
);
2223 sctx
->b
.b
.create_vs_state
= si_create_shader_selector
;
2224 sctx
->b
.b
.create_tcs_state
= si_create_shader_selector
;
2225 sctx
->b
.b
.create_tes_state
= si_create_shader_selector
;
2226 sctx
->b
.b
.create_gs_state
= si_create_shader_selector
;
2227 sctx
->b
.b
.create_fs_state
= si_create_shader_selector
;
2229 sctx
->b
.b
.bind_vs_state
= si_bind_vs_shader
;
2230 sctx
->b
.b
.bind_tcs_state
= si_bind_tcs_shader
;
2231 sctx
->b
.b
.bind_tes_state
= si_bind_tes_shader
;
2232 sctx
->b
.b
.bind_gs_state
= si_bind_gs_shader
;
2233 sctx
->b
.b
.bind_fs_state
= si_bind_ps_shader
;
2235 sctx
->b
.b
.delete_vs_state
= si_delete_shader_selector
;
2236 sctx
->b
.b
.delete_tcs_state
= si_delete_shader_selector
;
2237 sctx
->b
.b
.delete_tes_state
= si_delete_shader_selector
;
2238 sctx
->b
.b
.delete_gs_state
= si_delete_shader_selector
;
2239 sctx
->b
.b
.delete_fs_state
= si_delete_shader_selector
;