2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
31 #include "radeon/r600_cs.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/hash_table.h"
36 #include "util/crc32.h"
37 #include "util/u_memory.h"
38 #include "util/u_prim.h"
40 #include "util/disk_cache.h"
41 #include "util/mesa-sha1.h"
42 #include "ac_exp_param.h"
47 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
50 static void *si_get_tgsi_binary(struct si_shader_selector
*sel
)
52 unsigned tgsi_size
= tgsi_num_tokens(sel
->tokens
) *
53 sizeof(struct tgsi_token
);
54 unsigned size
= 4 + tgsi_size
+ sizeof(sel
->so
);
55 char *result
= (char*)MALLOC(size
);
60 *((uint32_t*)result
) = size
;
61 memcpy(result
+ 4, sel
->tokens
, tgsi_size
);
62 memcpy(result
+ 4 + tgsi_size
, &sel
->so
, sizeof(sel
->so
));
66 /** Copy "data" to "ptr" and return the next dword following copied data. */
67 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
69 /* data may be NULL if size == 0 */
71 memcpy(ptr
, data
, size
);
72 ptr
+= DIV_ROUND_UP(size
, 4);
76 /** Read data from "ptr". Return the next dword following the data. */
77 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
79 memcpy(data
, ptr
, size
);
80 ptr
+= DIV_ROUND_UP(size
, 4);
85 * Write the size as uint followed by the data. Return the next dword
86 * following the copied data.
88 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
91 return write_data(ptr
, data
, size
);
95 * Read the size as uint followed by the data. Return both via parameters.
96 * Return the next dword following the data.
98 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
101 assert(*data
== NULL
);
104 *data
= malloc(*size
);
105 return read_data(ptr
, *data
, *size
);
109 * Return the shader binary in a buffer. The first 4 bytes contain its size
112 static void *si_get_shader_binary(struct si_shader
*shader
)
114 /* There is always a size of data followed by the data itself. */
115 unsigned relocs_size
= shader
->binary
.reloc_count
*
116 sizeof(shader
->binary
.relocs
[0]);
117 unsigned disasm_size
= shader
->binary
.disasm_string
?
118 strlen(shader
->binary
.disasm_string
) + 1 : 0;
119 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
120 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
123 4 + /* CRC32 of the data below */
124 align(sizeof(shader
->config
), 4) +
125 align(sizeof(shader
->info
), 4) +
126 4 + align(shader
->binary
.code_size
, 4) +
127 4 + align(shader
->binary
.rodata_size
, 4) +
128 4 + align(relocs_size
, 4) +
129 4 + align(disasm_size
, 4) +
130 4 + align(llvm_ir_size
, 4);
131 void *buffer
= CALLOC(1, size
);
132 uint32_t *ptr
= (uint32_t*)buffer
;
138 ptr
++; /* CRC32 is calculated at the end. */
140 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
141 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
142 ptr
= write_chunk(ptr
, shader
->binary
.code
, shader
->binary
.code_size
);
143 ptr
= write_chunk(ptr
, shader
->binary
.rodata
, shader
->binary
.rodata_size
);
144 ptr
= write_chunk(ptr
, shader
->binary
.relocs
, relocs_size
);
145 ptr
= write_chunk(ptr
, shader
->binary
.disasm_string
, disasm_size
);
146 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
147 assert((char *)ptr
- (char *)buffer
== size
);
150 ptr
= (uint32_t*)buffer
;
152 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
157 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
159 uint32_t *ptr
= (uint32_t*)binary
;
160 uint32_t size
= *ptr
++;
161 uint32_t crc32
= *ptr
++;
164 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
165 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
169 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
170 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
171 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.code
,
172 &shader
->binary
.code_size
);
173 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.rodata
,
174 &shader
->binary
.rodata_size
);
175 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.relocs
, &chunk_size
);
176 shader
->binary
.reloc_count
= chunk_size
/ sizeof(shader
->binary
.relocs
[0]);
177 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.disasm_string
, &chunk_size
);
178 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
184 * Insert a shader into the cache. It's assumed the shader is not in the cache.
185 * Use si_shader_cache_load_shader before calling this.
187 * Returns false on failure, in which case the tgsi_binary should be freed.
189 static bool si_shader_cache_insert_shader(struct si_screen
*sscreen
,
191 struct si_shader
*shader
,
192 bool insert_into_disk_cache
)
195 struct hash_entry
*entry
;
196 uint8_t key
[CACHE_KEY_SIZE
];
198 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, tgsi_binary
);
200 return false; /* already added */
202 hw_binary
= si_get_shader_binary(shader
);
206 if (_mesa_hash_table_insert(sscreen
->shader_cache
, tgsi_binary
,
207 hw_binary
) == NULL
) {
212 if (sscreen
->b
.disk_shader_cache
&& insert_into_disk_cache
) {
213 disk_cache_compute_key(sscreen
->b
.disk_shader_cache
, tgsi_binary
,
214 *((uint32_t *)tgsi_binary
), key
);
215 disk_cache_put(sscreen
->b
.disk_shader_cache
, key
, hw_binary
,
216 *((uint32_t *) hw_binary
), NULL
);
222 static bool si_shader_cache_load_shader(struct si_screen
*sscreen
,
224 struct si_shader
*shader
)
226 struct hash_entry
*entry
=
227 _mesa_hash_table_search(sscreen
->shader_cache
, tgsi_binary
);
229 if (sscreen
->b
.disk_shader_cache
) {
230 unsigned char sha1
[CACHE_KEY_SIZE
];
231 size_t tg_size
= *((uint32_t *) tgsi_binary
);
233 disk_cache_compute_key(sscreen
->b
.disk_shader_cache
,
234 tgsi_binary
, tg_size
, sha1
);
238 disk_cache_get(sscreen
->b
.disk_shader_cache
,
243 if (binary_size
< sizeof(uint32_t) ||
244 *((uint32_t*)buffer
) != binary_size
) {
245 /* Something has gone wrong discard the item
246 * from the cache and rebuild/link from
249 assert(!"Invalid radeonsi shader disk cache "
252 disk_cache_remove(sscreen
->b
.disk_shader_cache
,
259 if (!si_load_shader_binary(shader
, buffer
)) {
265 if (!si_shader_cache_insert_shader(sscreen
, tgsi_binary
,
272 if (si_load_shader_binary(shader
, entry
->data
))
277 p_atomic_inc(&sscreen
->b
.num_shader_cache_hits
);
281 static uint32_t si_shader_cache_key_hash(const void *key
)
283 /* The first dword is the key size. */
284 return util_hash_crc32(key
, *(uint32_t*)key
);
287 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
289 uint32_t *keya
= (uint32_t*)a
;
290 uint32_t *keyb
= (uint32_t*)b
;
292 /* The first dword is the key size. */
296 return memcmp(keya
, keyb
, *keya
) == 0;
299 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
301 FREE((void*)entry
->key
);
305 bool si_init_shader_cache(struct si_screen
*sscreen
)
307 (void) mtx_init(&sscreen
->shader_cache_mutex
, mtx_plain
);
308 sscreen
->shader_cache
=
309 _mesa_hash_table_create(NULL
,
310 si_shader_cache_key_hash
,
311 si_shader_cache_key_equals
);
313 return sscreen
->shader_cache
!= NULL
;
316 void si_destroy_shader_cache(struct si_screen
*sscreen
)
318 if (sscreen
->shader_cache
)
319 _mesa_hash_table_destroy(sscreen
->shader_cache
,
320 si_destroy_shader_cache_entry
);
321 mtx_destroy(&sscreen
->shader_cache_mutex
);
326 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
327 struct si_shader_selector
*tes
,
328 struct si_pm4_state
*pm4
)
330 struct tgsi_shader_info
*info
= &tes
->info
;
331 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
332 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
333 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
334 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
335 unsigned type
, partitioning
, topology
, distribution_mode
;
337 switch (tes_prim_mode
) {
338 case PIPE_PRIM_LINES
:
339 type
= V_028B6C_TESS_ISOLINE
;
341 case PIPE_PRIM_TRIANGLES
:
342 type
= V_028B6C_TESS_TRIANGLE
;
344 case PIPE_PRIM_QUADS
:
345 type
= V_028B6C_TESS_QUAD
;
352 switch (tes_spacing
) {
353 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
354 partitioning
= V_028B6C_PART_FRAC_ODD
;
356 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
357 partitioning
= V_028B6C_PART_FRAC_EVEN
;
359 case PIPE_TESS_SPACING_EQUAL
:
360 partitioning
= V_028B6C_PART_INTEGER
;
368 topology
= V_028B6C_OUTPUT_POINT
;
369 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
370 topology
= V_028B6C_OUTPUT_LINE
;
371 else if (tes_vertex_order_cw
)
372 /* for some reason, this must be the other way around */
373 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
375 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
377 if (sscreen
->has_distributed_tess
) {
378 if (sscreen
->b
.family
== CHIP_FIJI
||
379 sscreen
->b
.family
>= CHIP_POLARIS10
)
380 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
382 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
384 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
386 si_pm4_set_reg(pm4
, R_028B6C_VGT_TF_PARAM
,
387 S_028B6C_TYPE(type
) |
388 S_028B6C_PARTITIONING(partitioning
) |
389 S_028B6C_TOPOLOGY(topology
) |
390 S_028B6C_DISTRIBUTION_MODE(distribution_mode
));
393 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
394 * whether the "fractional odd" tessellation spacing is used.
396 * Possible VGT configurations and which state should set the register:
398 * Reg set in | VGT shader configuration | Value
399 * ------------------------------------------------------
401 * VS as ES | ES -> GS -> VS | 30
402 * TES as VS | LS -> HS -> VS | 14 or 30
403 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
405 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
407 static void polaris_set_vgt_vertex_reuse(struct si_screen
*sscreen
,
408 struct si_shader_selector
*sel
,
409 struct si_shader
*shader
,
410 struct si_pm4_state
*pm4
)
412 unsigned type
= sel
->type
;
414 if (sscreen
->b
.family
< CHIP_POLARIS10
)
417 /* VS as VS, or VS as ES: */
418 if ((type
== PIPE_SHADER_VERTEX
&&
420 (!shader
->key
.as_ls
&& !shader
->is_gs_copy_shader
))) ||
421 /* TES as VS, or TES as ES: */
422 type
== PIPE_SHADER_TESS_EVAL
) {
423 unsigned vtx_reuse_depth
= 30;
425 if (type
== PIPE_SHADER_TESS_EVAL
&&
426 sel
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] ==
427 PIPE_TESS_SPACING_FRACTIONAL_ODD
)
428 vtx_reuse_depth
= 14;
430 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
435 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
438 si_pm4_clear_state(shader
->pm4
);
440 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
445 static void si_shader_ls(struct si_screen
*sscreen
, struct si_shader
*shader
)
447 struct si_pm4_state
*pm4
;
448 unsigned vgpr_comp_cnt
;
451 assert(sscreen
->b
.chip_class
<= VI
);
453 pm4
= si_get_shader_pm4_state(shader
);
457 va
= shader
->bo
->gpu_address
;
458 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
460 /* We need at least 2 components for LS.
461 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
462 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
464 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
466 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
467 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, va
>> 40);
469 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
470 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
471 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt
) |
472 S_00B528_DX10_CLAMP(1) |
473 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
474 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(SI_VS_NUM_USER_SGPR
) |
475 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
478 static void si_shader_hs(struct si_screen
*sscreen
, struct si_shader
*shader
)
480 struct si_pm4_state
*pm4
;
482 unsigned ls_vgpr_comp_cnt
= 0;
484 pm4
= si_get_shader_pm4_state(shader
);
488 va
= shader
->bo
->gpu_address
;
489 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
491 if (sscreen
->b
.chip_class
>= GFX9
) {
492 si_pm4_set_reg(pm4
, R_00B410_SPI_SHADER_PGM_LO_LS
, va
>> 8);
493 si_pm4_set_reg(pm4
, R_00B414_SPI_SHADER_PGM_HI_LS
, va
>> 40);
495 /* We need at least 2 components for LS.
496 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
497 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
499 ls_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
501 shader
->config
.rsrc2
=
502 S_00B42C_USER_SGPR(GFX9_TCS_NUM_USER_SGPR
) |
503 S_00B42C_USER_SGPR_MSB(GFX9_TCS_NUM_USER_SGPR
>> 5) |
504 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
506 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
507 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, va
>> 40);
509 shader
->config
.rsrc2
=
510 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR
) |
511 S_00B42C_OC_LDS_EN(1) |
512 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
515 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
516 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
517 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
518 S_00B428_DX10_CLAMP(1) |
519 S_00B428_FLOAT_MODE(shader
->config
.float_mode
) |
520 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt
));
522 if (sscreen
->b
.chip_class
<= VI
) {
523 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
524 shader
->config
.rsrc2
);
528 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
530 struct si_pm4_state
*pm4
;
531 unsigned num_user_sgprs
;
532 unsigned vgpr_comp_cnt
;
536 assert(sscreen
->b
.chip_class
<= VI
);
538 pm4
= si_get_shader_pm4_state(shader
);
542 va
= shader
->bo
->gpu_address
;
543 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
545 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
546 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
547 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
548 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
549 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
550 vgpr_comp_cnt
= shader
->selector
->info
.uses_primid
? 3 : 2;
551 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
553 unreachable("invalid shader selector type");
555 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
557 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
558 shader
->selector
->esgs_itemsize
/ 4);
559 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
560 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
561 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
562 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
563 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
564 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
565 S_00B328_DX10_CLAMP(1) |
566 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
567 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
568 S_00B32C_USER_SGPR(num_user_sgprs
) |
569 S_00B32C_OC_LDS_EN(oc_lds_en
) |
570 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
572 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
573 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
575 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
579 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
582 static uint32_t si_vgt_gs_mode(struct si_shader_selector
*sel
)
584 enum chip_class chip_class
= sel
->screen
->b
.chip_class
;
585 unsigned gs_max_vert_out
= sel
->gs_max_out_vertices
;
588 if (gs_max_vert_out
<= 128) {
589 cut_mode
= V_028A40_GS_CUT_128
;
590 } else if (gs_max_vert_out
<= 256) {
591 cut_mode
= V_028A40_GS_CUT_256
;
592 } else if (gs_max_vert_out
<= 512) {
593 cut_mode
= V_028A40_GS_CUT_512
;
595 assert(gs_max_vert_out
<= 1024);
596 cut_mode
= V_028A40_GS_CUT_1024
;
599 return S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
600 S_028A40_CUT_MODE(cut_mode
)|
601 S_028A40_ES_WRITE_OPTIMIZE(chip_class
<= VI
) |
602 S_028A40_GS_WRITE_OPTIMIZE(1) |
603 S_028A40_ONCHIP(chip_class
>= GFX9
? 1 : 0);
606 struct gfx9_gs_info
{
607 unsigned es_verts_per_subgroup
;
608 unsigned gs_prims_per_subgroup
;
609 unsigned gs_inst_prims_in_subgroup
;
610 unsigned max_prims_per_subgroup
;
614 static void gfx9_get_gs_info(struct si_shader_selector
*es
,
615 struct si_shader_selector
*gs
,
616 struct gfx9_gs_info
*out
)
618 unsigned gs_num_invocations
= MAX2(gs
->gs_num_invocations
, 1);
619 unsigned input_prim
= gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
620 bool uses_adjacency
= input_prim
>= PIPE_PRIM_LINES_ADJACENCY
&&
621 input_prim
<= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
;
623 /* All these are in dwords: */
624 /* We can't allow using the whole LDS, because GS waves compete with
625 * other shader stages for LDS space. */
626 const unsigned max_lds_size
= 8 * 1024;
627 const unsigned esgs_itemsize
= es
->esgs_itemsize
/ 4;
628 unsigned esgs_lds_size
;
630 /* All these are per subgroup: */
631 const unsigned max_out_prims
= 32 * 1024;
632 const unsigned max_es_verts
= 255;
633 const unsigned ideal_gs_prims
= 64;
634 unsigned max_gs_prims
, gs_prims
;
635 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
637 assert(gs_num_invocations
<= 32); /* GL maximum */
639 if (uses_adjacency
|| gs_num_invocations
> 1)
640 max_gs_prims
= 127 / gs_num_invocations
;
644 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
645 * Make sure we don't go over the maximum value.
647 if (gs
->gs_max_out_vertices
> 0) {
648 max_gs_prims
= MIN2(max_gs_prims
,
650 (gs
->gs_max_out_vertices
* gs_num_invocations
));
652 assert(max_gs_prims
> 0);
654 /* If the primitive has adjacency, halve the number of vertices
655 * that will be reused in multiple primitives.
657 min_es_verts
= gs
->gs_input_verts_per_prim
/ (uses_adjacency
? 2 : 1);
659 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
660 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
662 /* Compute ESGS LDS size based on the worst case number of ES vertices
663 * needed to create the target number of GS prims per subgroup.
665 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
667 /* If total LDS usage is too big, refactor partitions based on ratio
668 * of ESGS item sizes.
670 if (esgs_lds_size
> max_lds_size
) {
671 /* Our target GS Prims Per Subgroup was too large. Calculate
672 * the maximum number of GS Prims Per Subgroup that will fit
673 * into LDS, capped by the maximum that the hardware can support.
675 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
677 assert(gs_prims
> 0);
678 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
681 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
682 assert(esgs_lds_size
<= max_lds_size
);
685 /* Now calculate remaining ESGS information. */
687 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
689 es_verts
= max_es_verts
;
691 /* Vertices for adjacency primitives are not always reused, so restore
692 * it for ES_VERTS_PER_SUBGRP.
694 min_es_verts
= gs
->gs_input_verts_per_prim
;
696 /* For normal primitives, the VGT only checks if they are past the ES
697 * verts per subgroup after allocating a full GS primitive and if they
698 * are, kick off a new subgroup. But if those additional ES verts are
699 * unique (e.g. not reused) we need to make sure there is enough LDS
700 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
702 es_verts
-= min_es_verts
- 1;
704 out
->es_verts_per_subgroup
= es_verts
;
705 out
->gs_prims_per_subgroup
= gs_prims
;
706 out
->gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
707 out
->max_prims_per_subgroup
= out
->gs_inst_prims_in_subgroup
*
708 gs
->gs_max_out_vertices
;
709 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
711 assert(out
->max_prims_per_subgroup
<= max_out_prims
);
714 static void si_shader_gs(struct si_screen
*sscreen
, struct si_shader
*shader
)
716 struct si_shader_selector
*sel
= shader
->selector
;
717 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
718 unsigned gs_num_invocations
= sel
->gs_num_invocations
;
719 struct si_pm4_state
*pm4
;
721 unsigned max_stream
= sel
->max_gs_stream
;
724 pm4
= si_get_shader_pm4_state(shader
);
728 offset
= num_components
[0] * sel
->gs_max_out_vertices
;
729 si_pm4_set_reg(pm4
, R_028A60_VGT_GSVS_RING_OFFSET_1
, offset
);
731 offset
+= num_components
[1] * sel
->gs_max_out_vertices
;
732 si_pm4_set_reg(pm4
, R_028A64_VGT_GSVS_RING_OFFSET_2
, offset
);
734 offset
+= num_components
[2] * sel
->gs_max_out_vertices
;
735 si_pm4_set_reg(pm4
, R_028A68_VGT_GSVS_RING_OFFSET_3
, offset
);
737 offset
+= num_components
[3] * sel
->gs_max_out_vertices
;
738 si_pm4_set_reg(pm4
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
740 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
741 assert(offset
< (1 << 15));
743 si_pm4_set_reg(pm4
, R_028B38_VGT_GS_MAX_VERT_OUT
, sel
->gs_max_out_vertices
);
745 si_pm4_set_reg(pm4
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, num_components
[0]);
746 si_pm4_set_reg(pm4
, R_028B60_VGT_GS_VERT_ITEMSIZE_1
, (max_stream
>= 1) ? num_components
[1] : 0);
747 si_pm4_set_reg(pm4
, R_028B64_VGT_GS_VERT_ITEMSIZE_2
, (max_stream
>= 2) ? num_components
[2] : 0);
748 si_pm4_set_reg(pm4
, R_028B68_VGT_GS_VERT_ITEMSIZE_3
, (max_stream
>= 3) ? num_components
[3] : 0);
750 si_pm4_set_reg(pm4
, R_028B90_VGT_GS_INSTANCE_CNT
,
751 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
752 S_028B90_ENABLE(gs_num_invocations
> 0));
754 va
= shader
->bo
->gpu_address
;
755 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
757 if (sscreen
->b
.chip_class
>= GFX9
) {
758 unsigned input_prim
= sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
759 unsigned es_type
= shader
->key
.part
.gs
.es
->type
;
760 unsigned es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
761 struct gfx9_gs_info gs_info
;
763 if (es_type
== PIPE_SHADER_VERTEX
)
764 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
765 es_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
766 else if (es_type
== PIPE_SHADER_TESS_EVAL
)
767 es_vgpr_comp_cnt
= shader
->key
.part
.gs
.es
->info
.uses_primid
? 3 : 2;
769 unreachable("invalid shader selector type");
771 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
772 * VGPR[0:4] are always loaded.
774 if (sel
->info
.uses_invocationid
)
775 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
776 else if (sel
->info
.uses_primid
)
777 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
778 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
779 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
781 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
783 gfx9_get_gs_info(shader
->key
.part
.gs
.es
, sel
, &gs_info
);
785 si_pm4_set_reg(pm4
, R_00B210_SPI_SHADER_PGM_LO_ES
, va
>> 8);
786 si_pm4_set_reg(pm4
, R_00B214_SPI_SHADER_PGM_HI_ES
, va
>> 40);
788 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
789 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
790 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
791 S_00B228_DX10_CLAMP(1) |
792 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
793 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
));
794 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
795 S_00B22C_USER_SGPR(GFX9_GS_NUM_USER_SGPR
) |
796 S_00B22C_USER_SGPR_MSB(GFX9_GS_NUM_USER_SGPR
>> 5) |
797 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
798 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
799 S_00B22C_LDS_SIZE(gs_info
.lds_size
) |
800 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
802 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
803 S_028A44_ES_VERTS_PER_SUBGRP(gs_info
.es_verts_per_subgroup
) |
804 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info
.gs_prims_per_subgroup
) |
805 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info
.gs_inst_prims_in_subgroup
));
806 si_pm4_set_reg(pm4
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
807 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info
.max_prims_per_subgroup
));
808 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
809 shader
->key
.part
.gs
.es
->esgs_itemsize
/ 4);
811 if (es_type
== PIPE_SHADER_TESS_EVAL
)
812 si_set_tesseval_regs(sscreen
, shader
->key
.part
.gs
.es
, pm4
);
814 polaris_set_vgt_vertex_reuse(sscreen
, shader
->key
.part
.gs
.es
,
817 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
818 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, va
>> 40);
820 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
821 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
822 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
823 S_00B228_DX10_CLAMP(1) |
824 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
825 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
826 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR
) |
827 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
832 * Compute the state for \p shader, which will run as a vertex shader on the
835 * If \p gs is non-NULL, it points to the geometry shader for which this shader
836 * is the copy shader.
838 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
839 struct si_shader_selector
*gs
)
841 const struct tgsi_shader_info
*info
= &shader
->selector
->info
;
842 struct si_pm4_state
*pm4
;
843 unsigned num_user_sgprs
;
844 unsigned nparams
, vgpr_comp_cnt
;
847 unsigned window_space
=
848 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
849 bool enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| info
->uses_primid
;
851 pm4
= si_get_shader_pm4_state(shader
);
855 /* We always write VGT_GS_MODE in the VS state, because every switch
856 * between different shader pipelines involving a different GS or no
857 * GS at all involves a switch of the VS (different GS use different
858 * copy shaders). On the other hand, when the API switches from a GS to
859 * no GS and then back to the same GS used originally, the GS state is
863 unsigned mode
= V_028A40_GS_OFF
;
865 /* PrimID needs GS scenario A. */
867 mode
= V_028A40_GS_SCENARIO_A
;
869 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, S_028A40_MODE(mode
));
870 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, enable_prim_id
);
872 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, si_vgt_gs_mode(gs
));
873 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
876 if (sscreen
->b
.chip_class
<= VI
) {
877 /* Reuse needs to be set off if we write oViewport. */
878 si_pm4_set_reg(pm4
, R_028AB4_VGT_REUSE_OFF
,
879 S_028AB4_REUSE_OFF(info
->writes_viewport_index
));
882 va
= shader
->bo
->gpu_address
;
883 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
886 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
887 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
888 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
889 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
890 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
891 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
893 vgpr_comp_cnt
= enable_prim_id
? 2 : (shader
->info
.uses_instanceid
? 1 : 0);
894 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
895 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
896 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
897 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
899 unreachable("invalid shader selector type");
901 /* VS is required to export at least one param. */
902 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
903 si_pm4_set_reg(pm4
, R_0286C4_SPI_VS_OUT_CONFIG
,
904 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
906 si_pm4_set_reg(pm4
, R_02870C_SPI_SHADER_POS_FORMAT
,
907 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
908 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
909 V_02870C_SPI_SHADER_4COMP
:
910 V_02870C_SPI_SHADER_NONE
) |
911 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
912 V_02870C_SPI_SHADER_4COMP
:
913 V_02870C_SPI_SHADER_NONE
) |
914 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
915 V_02870C_SPI_SHADER_4COMP
:
916 V_02870C_SPI_SHADER_NONE
));
918 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
920 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
921 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, va
>> 40);
922 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
923 S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
924 S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
925 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
926 S_00B128_DX10_CLAMP(1) |
927 S_00B128_FLOAT_MODE(shader
->config
.float_mode
));
928 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
929 S_00B12C_USER_SGPR(num_user_sgprs
) |
930 S_00B12C_OC_LDS_EN(oc_lds_en
) |
931 S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
932 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
933 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
934 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
935 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
) |
936 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
938 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
939 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
941 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
942 S_028818_VTX_W0_FMT(1) |
943 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
944 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
945 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
947 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
948 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
950 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
953 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
955 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
956 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
957 !!(info
->colors_read
& 0xf0);
958 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
959 (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
961 assert(num_interp
<= 32);
962 return MIN2(num_interp
, 32);
965 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
967 unsigned value
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
968 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
970 /* If the i-th target format is set, all previous target formats must
971 * be non-zero to avoid hangs.
973 for (i
= 0; i
< num_targets
; i
++)
974 if (!(value
& (0xf << (i
* 4))))
975 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
980 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format
)
982 unsigned i
, cb_shader_mask
= 0;
984 for (i
= 0; i
< 8; i
++) {
985 switch ((spi_shader_col_format
>> (i
* 4)) & 0xf) {
986 case V_028714_SPI_SHADER_ZERO
:
988 case V_028714_SPI_SHADER_32_R
:
989 cb_shader_mask
|= 0x1 << (i
* 4);
991 case V_028714_SPI_SHADER_32_GR
:
992 cb_shader_mask
|= 0x3 << (i
* 4);
994 case V_028714_SPI_SHADER_32_AR
:
995 cb_shader_mask
|= 0x9 << (i
* 4);
997 case V_028714_SPI_SHADER_FP16_ABGR
:
998 case V_028714_SPI_SHADER_UNORM16_ABGR
:
999 case V_028714_SPI_SHADER_SNORM16_ABGR
:
1000 case V_028714_SPI_SHADER_UINT16_ABGR
:
1001 case V_028714_SPI_SHADER_SINT16_ABGR
:
1002 case V_028714_SPI_SHADER_32_ABGR
:
1003 cb_shader_mask
|= 0xf << (i
* 4);
1009 return cb_shader_mask
;
1012 static void si_shader_ps(struct si_shader
*shader
)
1014 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1015 struct si_pm4_state
*pm4
;
1016 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
1017 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
1019 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
1021 /* we need to enable at least one of them, otherwise we hang the GPU */
1022 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1023 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1024 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1025 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
1026 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
1027 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1028 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
1029 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
1030 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1031 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
1032 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1033 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1034 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1035 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
1037 /* Validate interpolation optimization flags (read as implications). */
1038 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1039 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1040 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1041 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1042 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1043 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1044 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
1045 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
1046 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1047 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
1048 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
1049 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1050 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
1051 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1052 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1053 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
1054 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1055 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1057 /* Validate cases when the optimizations are off (read as implications). */
1058 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1059 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1060 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
1061 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1062 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1063 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
1065 pm4
= si_get_shader_pm4_state(shader
);
1069 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1071 * 0 -> Position = pixel center
1072 * 1 -> Position = pixel centroid
1073 * 2 -> Position = at sample position
1075 * From GLSL 4.5 specification, section 7.1:
1076 * "The variable gl_FragCoord is available as an input variable from
1077 * within fragment shaders and it holds the window relative coordinates
1078 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1079 * value can be for any location within the pixel, or one of the
1080 * fragment samples. The use of centroid does not further restrict
1081 * this value to be inside the current primitive."
1083 * Meaning that centroid has no effect and we can return anything within
1084 * the pixel. Thus, return the value at sample position, because that's
1085 * the most accurate one shaders can get.
1087 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1089 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
1090 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
1091 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
1093 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
1094 cb_shader_mask
= si_get_cb_shader_mask(spi_shader_col_format
);
1096 /* Ensure that some export memory is always allocated, for two reasons:
1098 * 1) Correctness: The hardware ignores the EXEC mask if no export
1099 * memory is allocated, so KILL and alpha test do not work correctly
1101 * 2) Performance: Every shader needs at least a NULL export, even when
1102 * it writes no color/depth output. The NULL export instruction
1103 * stalls without this setting.
1105 * Don't add this to CB_SHADER_MASK.
1107 if (!spi_shader_col_format
&&
1108 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
1109 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
1111 si_pm4_set_reg(pm4
, R_0286CC_SPI_PS_INPUT_ENA
, input_ena
);
1112 si_pm4_set_reg(pm4
, R_0286D0_SPI_PS_INPUT_ADDR
,
1113 shader
->config
.spi_ps_input_addr
);
1115 /* Set interpolation controls. */
1116 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
));
1118 /* Set registers. */
1119 si_pm4_set_reg(pm4
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
1120 si_pm4_set_reg(pm4
, R_0286D8_SPI_PS_IN_CONTROL
, spi_ps_in_control
);
1122 si_pm4_set_reg(pm4
, R_028710_SPI_SHADER_Z_FORMAT
,
1123 si_get_spi_shader_z_format(info
->writes_z
,
1124 info
->writes_stencil
,
1125 info
->writes_samplemask
));
1127 si_pm4_set_reg(pm4
, R_028714_SPI_SHADER_COL_FORMAT
, spi_shader_col_format
);
1128 si_pm4_set_reg(pm4
, R_02823C_CB_SHADER_MASK
, cb_shader_mask
);
1130 va
= shader
->bo
->gpu_address
;
1131 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1132 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
1133 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, va
>> 40);
1135 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
,
1136 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1137 S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
1138 S_00B028_DX10_CLAMP(1) |
1139 S_00B028_FLOAT_MODE(shader
->config
.float_mode
));
1140 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
1141 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
1142 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
1143 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1146 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
1147 struct si_shader
*shader
)
1149 switch (shader
->selector
->type
) {
1150 case PIPE_SHADER_VERTEX
:
1151 if (shader
->key
.as_ls
)
1152 si_shader_ls(sscreen
, shader
);
1153 else if (shader
->key
.as_es
)
1154 si_shader_es(sscreen
, shader
);
1156 si_shader_vs(sscreen
, shader
, NULL
);
1158 case PIPE_SHADER_TESS_CTRL
:
1159 si_shader_hs(sscreen
, shader
);
1161 case PIPE_SHADER_TESS_EVAL
:
1162 if (shader
->key
.as_es
)
1163 si_shader_es(sscreen
, shader
);
1165 si_shader_vs(sscreen
, shader
, NULL
);
1167 case PIPE_SHADER_GEOMETRY
:
1168 si_shader_gs(sscreen
, shader
);
1170 case PIPE_SHADER_FRAGMENT
:
1171 si_shader_ps(shader
);
1178 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
1180 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1181 if (sctx
->queued
.named
.dsa
)
1182 return sctx
->queued
.named
.dsa
->alpha_func
;
1184 return PIPE_FUNC_ALWAYS
;
1187 static void si_shader_selector_key_vs(struct si_context
*sctx
,
1188 struct si_shader_selector
*vs
,
1189 struct si_shader_key
*key
,
1190 struct si_vs_prolog_bits
*prolog_key
)
1192 if (!sctx
->vertex_elements
)
1195 prolog_key
->instance_divisor_is_one
=
1196 sctx
->vertex_elements
->instance_divisor_is_one
;
1197 prolog_key
->instance_divisor_is_fetched
=
1198 sctx
->vertex_elements
->instance_divisor_is_fetched
;
1200 /* Prefer a monolithic shader to allow scheduling divisions around
1202 if (prolog_key
->instance_divisor_is_fetched
)
1203 key
->opt
.prefer_mono
= 1;
1205 unsigned count
= MIN2(vs
->info
.num_inputs
,
1206 sctx
->vertex_elements
->count
);
1207 memcpy(key
->mono
.vs_fix_fetch
, sctx
->vertex_elements
->fix_fetch
, count
);
1210 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
,
1211 struct si_shader_selector
*vs
,
1212 struct si_shader_key
*key
)
1214 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1216 key
->opt
.clip_disable
=
1217 sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
1218 (vs
->info
.clipdist_writemask
||
1219 vs
->info
.writes_clipvertex
) &&
1220 !vs
->info
.culldist_writemask
;
1222 /* Find out if PS is disabled. */
1223 bool ps_disabled
= true;
1225 bool ps_modifies_zs
= ps
->info
.uses_kill
||
1226 ps
->info
.writes_z
||
1227 ps
->info
.writes_stencil
||
1228 ps
->info
.writes_samplemask
||
1229 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
1231 unsigned ps_colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
&
1232 sctx
->queued
.named
.blend
->cb_target_mask
;
1233 if (!ps
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
])
1234 ps_colormask
&= ps
->colors_written_4bit
;
1236 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
1239 !ps
->info
.writes_memory
);
1242 /* Find out which VS outputs aren't used by the PS. */
1243 uint64_t outputs_written
= vs
->outputs_written
;
1244 uint64_t inputs_read
= 0;
1246 /* ignore POSITION, PSIZE */
1247 outputs_written
&= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION
, 0) |
1248 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE
, 0))));
1251 inputs_read
= ps
->inputs_read
;
1254 uint64_t linked
= outputs_written
& inputs_read
;
1256 key
->opt
.kill_outputs
= ~linked
& outputs_written
;
1259 /* Compute the key for the hw shader variant */
1260 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
1261 struct si_shader_selector
*sel
,
1262 struct si_shader_key
*key
)
1264 struct si_context
*sctx
= (struct si_context
*)ctx
;
1266 memset(key
, 0, sizeof(*key
));
1268 switch (sel
->type
) {
1269 case PIPE_SHADER_VERTEX
:
1270 si_shader_selector_key_vs(sctx
, sel
, key
, &key
->part
.vs
.prolog
);
1272 if (sctx
->tes_shader
.cso
)
1274 else if (sctx
->gs_shader
.cso
)
1277 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1279 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1280 key
->mono
.u
.vs_export_prim_id
= 1;
1283 case PIPE_SHADER_TESS_CTRL
:
1284 if (sctx
->b
.chip_class
>= GFX9
) {
1285 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1286 key
, &key
->part
.tcs
.ls_prolog
);
1287 key
->part
.tcs
.ls
= sctx
->vs_shader
.cso
;
1289 /* When the LS VGPR fix is needed, monolithic shaders
1291 * - avoid initializing EXEC in both the LS prolog
1292 * and the LS main part when !vs_needs_prolog
1293 * - remove the fixup for unused input VGPRs
1295 key
->part
.tcs
.ls_prolog
.ls_vgpr_fix
= sctx
->ls_vgpr_fix
;
1297 /* The LS output / HS input layout can be communicated
1298 * directly instead of via user SGPRs for merged LS-HS.
1299 * The LS VGPR fix prefers this too.
1301 key
->opt
.prefer_mono
= 1;
1304 key
->part
.tcs
.epilog
.prim_mode
=
1305 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1306 key
->part
.tcs
.epilog
.invoc0_tess_factors_are_def
=
1307 sel
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1308 key
->part
.tcs
.epilog
.tes_reads_tess_factors
=
1309 sctx
->tes_shader
.cso
->info
.reads_tess_factors
;
1311 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
1312 key
->mono
.u
.ff_tcs_inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
1314 case PIPE_SHADER_TESS_EVAL
:
1315 if (sctx
->gs_shader
.cso
)
1318 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1320 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1321 key
->mono
.u
.vs_export_prim_id
= 1;
1324 case PIPE_SHADER_GEOMETRY
:
1325 if (sctx
->b
.chip_class
>= GFX9
) {
1326 if (sctx
->tes_shader
.cso
) {
1327 key
->part
.gs
.es
= sctx
->tes_shader
.cso
;
1329 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1330 key
, &key
->part
.gs
.vs_prolog
);
1331 key
->part
.gs
.es
= sctx
->vs_shader
.cso
;
1334 /* Merged ES-GS can have unbalanced wave usage.
1336 * ES threads are per-vertex, while GS threads are
1337 * per-primitive. So without any amplification, there
1338 * are fewer GS threads than ES threads, which can result
1339 * in empty (no-op) GS waves. With too much amplification,
1340 * there are more GS threads than ES threads, which
1341 * can result in empty (no-op) ES waves.
1343 * Non-monolithic shaders are implemented by setting EXEC
1344 * at the beginning of shader parts, and don't jump to
1345 * the end if EXEC is 0.
1347 * Monolithic shaders use conditional blocks, so they can
1348 * jump and skip empty waves of ES or GS. So set this to
1349 * always use optimized variants, which are monolithic.
1351 key
->opt
.prefer_mono
= 1;
1353 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
1355 case PIPE_SHADER_FRAGMENT
: {
1356 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1357 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1359 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
1360 sel
->info
.colors_written
== 0x1)
1361 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
1364 /* Select the shader color format based on whether
1365 * blending or alpha are needed.
1367 key
->part
.ps
.epilog
.spi_shader_col_format
=
1368 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1369 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
1370 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1371 sctx
->framebuffer
.spi_shader_col_format_blend
) |
1372 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1373 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
1374 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1375 sctx
->framebuffer
.spi_shader_col_format
);
1376 key
->part
.ps
.epilog
.spi_shader_col_format
&= blend
->cb_target_enabled_4bit
;
1378 /* The output for dual source blending should have
1379 * the same format as the first output.
1381 if (blend
->dual_src_blend
)
1382 key
->part
.ps
.epilog
.spi_shader_col_format
|=
1383 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
1385 key
->part
.ps
.epilog
.spi_shader_col_format
= sctx
->framebuffer
.spi_shader_col_format
;
1387 /* If alpha-to-coverage is enabled, we have to export alpha
1388 * even if there is no color buffer.
1390 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) &&
1391 blend
&& blend
->alpha_to_coverage
)
1392 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
1394 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1395 * to the range supported by the type if a channel has less
1396 * than 16 bits and the export format is 16_ABGR.
1398 if (sctx
->b
.chip_class
<= CIK
&& sctx
->b
.family
!= CHIP_HAWAII
) {
1399 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
1400 key
->part
.ps
.epilog
.color_is_int10
= sctx
->framebuffer
.color_is_int10
;
1403 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1404 if (!key
->part
.ps
.epilog
.last_cbuf
) {
1405 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
1406 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
1407 key
->part
.ps
.epilog
.color_is_int10
&= sel
->info
.colors_written
;
1411 bool is_poly
= (sctx
->b
.current_rast_prim
>= PIPE_PRIM_TRIANGLES
&&
1412 sctx
->b
.current_rast_prim
<= PIPE_PRIM_POLYGON
) ||
1413 sctx
->b
.current_rast_prim
>= PIPE_PRIM_TRIANGLES_ADJACENCY
;
1414 bool is_line
= !is_poly
&& sctx
->b
.current_rast_prim
!= PIPE_PRIM_POINTS
;
1416 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
1417 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
1419 if (sctx
->queued
.named
.blend
) {
1420 key
->part
.ps
.epilog
.alpha_to_one
= sctx
->queued
.named
.blend
->alpha_to_one
&&
1421 rs
->multisample_enable
;
1424 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
1425 key
->part
.ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
1426 (is_line
&& rs
->line_smooth
)) &&
1427 sctx
->framebuffer
.nr_samples
<= 1;
1428 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
1430 if (sctx
->ps_iter_samples
> 1 &&
1431 sel
->info
.reads_samplemask
) {
1432 key
->part
.ps
.prolog
.samplemask_log_ps_iter
=
1433 util_logbase2(util_next_power_of_two(sctx
->ps_iter_samples
));
1436 if (rs
->force_persample_interp
&&
1437 rs
->multisample_enable
&&
1438 sctx
->framebuffer
.nr_samples
> 1 &&
1439 sctx
->ps_iter_samples
> 1) {
1440 key
->part
.ps
.prolog
.force_persp_sample_interp
=
1441 sel
->info
.uses_persp_center
||
1442 sel
->info
.uses_persp_centroid
;
1444 key
->part
.ps
.prolog
.force_linear_sample_interp
=
1445 sel
->info
.uses_linear_center
||
1446 sel
->info
.uses_linear_centroid
;
1447 } else if (rs
->multisample_enable
&&
1448 sctx
->framebuffer
.nr_samples
> 1) {
1449 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
1450 sel
->info
.uses_persp_center
&&
1451 sel
->info
.uses_persp_centroid
;
1452 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
1453 sel
->info
.uses_linear_center
&&
1454 sel
->info
.uses_linear_centroid
;
1456 /* Make sure SPI doesn't compute more than 1 pair
1457 * of (i,j), which is the optimization here. */
1458 key
->part
.ps
.prolog
.force_persp_center_interp
=
1459 sel
->info
.uses_persp_center
+
1460 sel
->info
.uses_persp_centroid
+
1461 sel
->info
.uses_persp_sample
> 1;
1463 key
->part
.ps
.prolog
.force_linear_center_interp
=
1464 sel
->info
.uses_linear_center
+
1465 sel
->info
.uses_linear_centroid
+
1466 sel
->info
.uses_linear_sample
> 1;
1468 if (sel
->info
.opcode_count
[TGSI_OPCODE_INTERP_SAMPLE
])
1469 key
->mono
.u
.ps
.interpolate_at_sample_force_center
= 1;
1473 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
1480 if (unlikely(sctx
->screen
->b
.debug_flags
& DBG_NO_OPT_VARIANT
))
1481 memset(&key
->opt
, 0, sizeof(key
->opt
));
1484 static void si_build_shader_variant(struct si_shader
*shader
,
1488 struct si_shader_selector
*sel
= shader
->selector
;
1489 struct si_screen
*sscreen
= sel
->screen
;
1490 LLVMTargetMachineRef tm
;
1491 struct pipe_debug_callback
*debug
= &shader
->compiler_ctx_state
.debug
;
1494 if (thread_index
>= 0) {
1496 assert(thread_index
< ARRAY_SIZE(sscreen
->tm_low_priority
));
1497 tm
= sscreen
->tm_low_priority
[thread_index
];
1499 assert(thread_index
< ARRAY_SIZE(sscreen
->tm
));
1500 tm
= sscreen
->tm
[thread_index
];
1505 assert(!low_priority
);
1506 tm
= shader
->compiler_ctx_state
.tm
;
1509 r
= si_shader_create(sscreen
, tm
, shader
, debug
);
1511 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1513 shader
->compilation_failed
= true;
1517 if (shader
->compiler_ctx_state
.is_debug_context
) {
1518 FILE *f
= open_memstream(&shader
->shader_log
,
1519 &shader
->shader_log_size
);
1521 si_shader_dump(sscreen
, shader
, NULL
, sel
->type
, f
, false);
1526 si_shader_init_pm4_state(sscreen
, shader
);
1529 static void si_build_shader_variant_low_priority(void *job
, int thread_index
)
1531 struct si_shader
*shader
= (struct si_shader
*)job
;
1533 assert(thread_index
>= 0);
1535 si_build_shader_variant(shader
, thread_index
, true);
1538 static const struct si_shader_key zeroed
;
1540 static bool si_check_missing_main_part(struct si_screen
*sscreen
,
1541 struct si_shader_selector
*sel
,
1542 struct si_compiler_ctx_state
*compiler_state
,
1543 struct si_shader_key
*key
)
1545 struct si_shader
**mainp
= si_get_main_shader_part(sel
, key
);
1548 struct si_shader
*main_part
= CALLOC_STRUCT(si_shader
);
1553 main_part
->selector
= sel
;
1554 main_part
->key
.as_es
= key
->as_es
;
1555 main_part
->key
.as_ls
= key
->as_ls
;
1557 if (si_compile_tgsi_shader(sscreen
, compiler_state
->tm
,
1559 &compiler_state
->debug
) != 0) {
1568 /* Select the hw shader variant depending on the current state. */
1569 static int si_shader_select_with_key(struct si_screen
*sscreen
,
1570 struct si_shader_ctx_state
*state
,
1571 struct si_compiler_ctx_state
*compiler_state
,
1572 struct si_shader_key
*key
,
1575 struct si_shader_selector
*sel
= state
->cso
;
1576 struct si_shader_selector
*previous_stage_sel
= NULL
;
1577 struct si_shader
*current
= state
->current
;
1578 struct si_shader
*iter
, *shader
= NULL
;
1581 /* Check if we don't need to change anything.
1582 * This path is also used for most shaders that don't need multiple
1583 * variants, it will cost just a computation of the key and this
1585 if (likely(current
&&
1586 memcmp(¤t
->key
, key
, sizeof(*key
)) == 0 &&
1587 (!current
->is_optimized
||
1588 util_queue_fence_is_signalled(¤t
->optimized_ready
))))
1589 return current
->compilation_failed
? -1 : 0;
1591 /* This must be done before the mutex is locked, because async GS
1592 * compilation calls this function too, and therefore must enter
1595 * Only wait if we are in a draw call. Don't wait if we are
1596 * in a compiler thread.
1598 if (thread_index
< 0)
1599 util_queue_fence_wait(&sel
->ready
);
1601 mtx_lock(&sel
->mutex
);
1603 /* Find the shader variant. */
1604 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
1605 /* Don't check the "current" shader. We checked it above. */
1606 if (current
!= iter
&&
1607 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
1608 /* If it's an optimized shader and its compilation has
1609 * been started but isn't done, use the unoptimized
1610 * shader so as not to cause a stall due to compilation.
1612 if (iter
->is_optimized
&&
1613 !util_queue_fence_is_signalled(&iter
->optimized_ready
)) {
1614 memset(&key
->opt
, 0, sizeof(key
->opt
));
1615 mtx_unlock(&sel
->mutex
);
1619 if (iter
->compilation_failed
) {
1620 mtx_unlock(&sel
->mutex
);
1621 return -1; /* skip the draw call */
1624 state
->current
= iter
;
1625 mtx_unlock(&sel
->mutex
);
1630 /* Build a new shader. */
1631 shader
= CALLOC_STRUCT(si_shader
);
1633 mtx_unlock(&sel
->mutex
);
1636 shader
->selector
= sel
;
1638 shader
->compiler_ctx_state
= *compiler_state
;
1640 /* If this is a merged shader, get the first shader's selector. */
1641 if (sscreen
->b
.chip_class
>= GFX9
) {
1642 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
1643 previous_stage_sel
= key
->part
.tcs
.ls
;
1644 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
1645 previous_stage_sel
= key
->part
.gs
.es
;
1647 /* We need to wait for the previous shader. */
1648 if (previous_stage_sel
&& thread_index
< 0)
1649 util_queue_fence_wait(&previous_stage_sel
->ready
);
1652 /* Compile the main shader part if it doesn't exist. This can happen
1653 * if the initial guess was wrong. */
1654 bool is_pure_monolithic
=
1655 sscreen
->use_monolithic_shaders
||
1656 memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
1658 if (!is_pure_monolithic
) {
1661 /* Make sure the main shader part is present. This is needed
1662 * for shaders that can be compiled as VS, LS, or ES, and only
1663 * one of them is compiled at creation.
1665 * For merged shaders, check that the starting shader's main
1668 if (previous_stage_sel
) {
1669 struct si_shader_key shader1_key
= zeroed
;
1671 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
1672 shader1_key
.as_ls
= 1;
1673 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
1674 shader1_key
.as_es
= 1;
1678 mtx_lock(&previous_stage_sel
->mutex
);
1679 ok
= si_check_missing_main_part(sscreen
,
1681 compiler_state
, &shader1_key
);
1682 mtx_unlock(&previous_stage_sel
->mutex
);
1684 ok
= si_check_missing_main_part(sscreen
, sel
,
1685 compiler_state
, key
);
1689 mtx_unlock(&sel
->mutex
);
1690 return -ENOMEM
; /* skip the draw call */
1694 /* Keep the reference to the 1st shader of merged shaders, so that
1695 * Gallium can't destroy it before we destroy the 2nd shader.
1697 * Set sctx = NULL, because it's unused if we're not releasing
1698 * the shader, and we don't have any sctx here.
1700 si_shader_selector_reference(NULL
, &shader
->previous_stage_sel
,
1701 previous_stage_sel
);
1703 /* Monolithic-only shaders don't make a distinction between optimized
1704 * and unoptimized. */
1705 shader
->is_monolithic
=
1706 is_pure_monolithic
||
1707 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1709 shader
->is_optimized
=
1710 !is_pure_monolithic
&&
1711 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1712 if (shader
->is_optimized
)
1713 util_queue_fence_init(&shader
->optimized_ready
);
1715 if (!sel
->last_variant
) {
1716 sel
->first_variant
= shader
;
1717 sel
->last_variant
= shader
;
1719 sel
->last_variant
->next_variant
= shader
;
1720 sel
->last_variant
= shader
;
1723 /* If it's an optimized shader, compile it asynchronously. */
1724 if (shader
->is_optimized
&&
1725 !is_pure_monolithic
&&
1727 /* Compile it asynchronously. */
1728 util_queue_add_job(&sscreen
->shader_compiler_queue_low_priority
,
1729 shader
, &shader
->optimized_ready
,
1730 si_build_shader_variant_low_priority
, NULL
);
1732 /* Use the default (unoptimized) shader for now. */
1733 memset(&key
->opt
, 0, sizeof(key
->opt
));
1734 mtx_unlock(&sel
->mutex
);
1738 assert(!shader
->is_optimized
);
1739 si_build_shader_variant(shader
, thread_index
, false);
1741 if (!shader
->compilation_failed
)
1742 state
->current
= shader
;
1744 mtx_unlock(&sel
->mutex
);
1745 return shader
->compilation_failed
? -1 : 0;
1748 static int si_shader_select(struct pipe_context
*ctx
,
1749 struct si_shader_ctx_state
*state
,
1750 struct si_compiler_ctx_state
*compiler_state
)
1752 struct si_context
*sctx
= (struct si_context
*)ctx
;
1753 struct si_shader_key key
;
1755 si_shader_selector_key(ctx
, state
->cso
, &key
);
1756 return si_shader_select_with_key(sctx
->screen
, state
, compiler_state
,
1760 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
1762 struct si_shader_key
*key
)
1764 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
1766 switch (info
->processor
) {
1767 case PIPE_SHADER_VERTEX
:
1768 switch (next_shader
) {
1769 case PIPE_SHADER_GEOMETRY
:
1772 case PIPE_SHADER_TESS_CTRL
:
1773 case PIPE_SHADER_TESS_EVAL
:
1777 /* If POSITION isn't written, it can only be a HW VS
1778 * if streamout is used. If streamout isn't used,
1779 * assume that it's a HW LS. (the next shader is TCS)
1780 * This heuristic is needed for separate shader objects.
1782 if (!info
->writes_position
&& !streamout
)
1787 case PIPE_SHADER_TESS_EVAL
:
1788 if (next_shader
== PIPE_SHADER_GEOMETRY
||
1789 !info
->writes_position
)
1796 * Compile the main shader part or the monolithic shader as part of
1797 * si_shader_selector initialization. Since it can be done asynchronously,
1798 * there is no way to report compile failures to applications.
1800 static void si_init_shader_selector_async(void *job
, int thread_index
)
1802 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
1803 struct si_screen
*sscreen
= sel
->screen
;
1804 LLVMTargetMachineRef tm
;
1805 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
1808 if (thread_index
>= 0) {
1809 assert(thread_index
< ARRAY_SIZE(sscreen
->tm
));
1810 tm
= sscreen
->tm
[thread_index
];
1814 tm
= sel
->compiler_ctx_state
.tm
;
1817 /* Compile the main shader part for use with a prolog and/or epilog.
1818 * If this fails, the driver will try to compile a monolithic shader
1821 if (!sscreen
->use_monolithic_shaders
) {
1822 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
1823 void *tgsi_binary
= NULL
;
1826 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
1830 shader
->selector
= sel
;
1831 si_parse_next_shader_property(&sel
->info
,
1832 sel
->so
.num_outputs
!= 0,
1836 tgsi_binary
= si_get_tgsi_binary(sel
);
1838 /* Try to load the shader from the shader cache. */
1839 mtx_lock(&sscreen
->shader_cache_mutex
);
1842 si_shader_cache_load_shader(sscreen
, tgsi_binary
, shader
)) {
1843 mtx_unlock(&sscreen
->shader_cache_mutex
);
1845 mtx_unlock(&sscreen
->shader_cache_mutex
);
1847 /* Compile the shader if it hasn't been loaded from the cache. */
1848 if (si_compile_tgsi_shader(sscreen
, tm
, shader
, false,
1852 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
1857 mtx_lock(&sscreen
->shader_cache_mutex
);
1858 if (!si_shader_cache_insert_shader(sscreen
, tgsi_binary
, shader
, true))
1860 mtx_unlock(&sscreen
->shader_cache_mutex
);
1864 *si_get_main_shader_part(sel
, &shader
->key
) = shader
;
1866 /* Unset "outputs_written" flags for outputs converted to
1867 * DEFAULT_VAL, so that later inter-shader optimizations don't
1868 * try to eliminate outputs that don't exist in the final
1871 * This is only done if non-monolithic shaders are enabled.
1873 if ((sel
->type
== PIPE_SHADER_VERTEX
||
1874 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
1875 !shader
->key
.as_ls
&&
1876 !shader
->key
.as_es
) {
1879 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
1880 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
1882 if (offset
<= AC_EXP_PARAM_OFFSET_31
)
1885 unsigned name
= sel
->info
.output_semantic_name
[i
];
1886 unsigned index
= sel
->info
.output_semantic_index
[i
];
1890 case TGSI_SEMANTIC_GENERIC
:
1891 /* don't process indices the function can't handle */
1892 if (index
>= SI_MAX_IO_GENERIC
)
1896 id
= si_shader_io_get_unique_index(name
, index
);
1897 sel
->outputs_written
&= ~(1ull << id
);
1899 case TGSI_SEMANTIC_POSITION
: /* ignore these */
1900 case TGSI_SEMANTIC_PSIZE
:
1901 case TGSI_SEMANTIC_CLIPVERTEX
:
1902 case TGSI_SEMANTIC_EDGEFLAG
:
1909 /* Pre-compilation. */
1910 if (sscreen
->b
.debug_flags
& DBG_PRECOMPILE
&&
1911 /* GFX9 needs LS or ES for compilation, which we don't have here. */
1912 (sscreen
->b
.chip_class
<= VI
||
1913 (sel
->type
!= PIPE_SHADER_TESS_CTRL
&&
1914 sel
->type
!= PIPE_SHADER_GEOMETRY
))) {
1915 struct si_shader_ctx_state state
= {sel
};
1916 struct si_shader_key key
;
1918 memset(&key
, 0, sizeof(key
));
1919 si_parse_next_shader_property(&sel
->info
,
1920 sel
->so
.num_outputs
!= 0,
1923 /* GFX9 doesn't have LS and ES. */
1924 if (sscreen
->b
.chip_class
>= GFX9
) {
1929 /* Set reasonable defaults, so that the shader key doesn't
1930 * cause any code to be eliminated.
1932 switch (sel
->type
) {
1933 case PIPE_SHADER_TESS_CTRL
:
1934 key
.part
.tcs
.epilog
.prim_mode
= PIPE_PRIM_TRIANGLES
;
1936 case PIPE_SHADER_FRAGMENT
:
1937 key
.part
.ps
.prolog
.bc_optimize_for_persp
=
1938 sel
->info
.uses_persp_center
&&
1939 sel
->info
.uses_persp_centroid
;
1940 key
.part
.ps
.prolog
.bc_optimize_for_linear
=
1941 sel
->info
.uses_linear_center
&&
1942 sel
->info
.uses_linear_centroid
;
1943 key
.part
.ps
.epilog
.alpha_func
= PIPE_FUNC_ALWAYS
;
1944 for (i
= 0; i
< 8; i
++)
1945 if (sel
->info
.colors_written
& (1 << i
))
1946 key
.part
.ps
.epilog
.spi_shader_col_format
|=
1947 V_028710_SPI_SHADER_FP16_ABGR
<< (i
* 4);
1951 if (si_shader_select_with_key(sscreen
, &state
,
1952 &sel
->compiler_ctx_state
, &key
,
1954 fprintf(stderr
, "radeonsi: can't create a monolithic shader\n");
1957 /* The GS copy shader is always pre-compiled. */
1958 if (sel
->type
== PIPE_SHADER_GEOMETRY
) {
1959 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, tm
, sel
, debug
);
1960 if (!sel
->gs_copy_shader
) {
1961 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
1965 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
1969 /* Return descriptor slot usage masks from the given shader info. */
1970 void si_get_active_slot_masks(const struct tgsi_shader_info
*info
,
1971 uint32_t *const_and_shader_buffers
,
1972 uint64_t *samplers_and_images
)
1974 unsigned start
, num_shaderbufs
, num_constbufs
, num_images
, num_samplers
;
1976 num_shaderbufs
= util_last_bit(info
->shader_buffers_declared
);
1977 num_constbufs
= util_last_bit(info
->const_buffers_declared
);
1978 /* two 8-byte images share one 16-byte slot */
1979 num_images
= align(util_last_bit(info
->images_declared
), 2);
1980 num_samplers
= util_last_bit(info
->samplers_declared
);
1982 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
1983 start
= si_get_shaderbuf_slot(num_shaderbufs
- 1);
1984 *const_and_shader_buffers
=
1985 u_bit_consecutive(start
, num_shaderbufs
+ num_constbufs
);
1987 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
1988 start
= si_get_image_slot(num_images
- 1) / 2;
1989 *samplers_and_images
=
1990 u_bit_consecutive64(start
, num_images
/ 2 + num_samplers
);
1993 static void *si_create_shader_selector(struct pipe_context
*ctx
,
1994 const struct pipe_shader_state
*state
)
1996 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
1997 struct si_context
*sctx
= (struct si_context
*)ctx
;
1998 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
2004 pipe_reference_init(&sel
->reference
, 1);
2005 sel
->screen
= sscreen
;
2006 sel
->compiler_ctx_state
.tm
= sctx
->tm
;
2007 sel
->compiler_ctx_state
.debug
= sctx
->b
.debug
;
2008 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
2010 sel
->so
= state
->stream_output
;
2012 if (state
->type
== PIPE_SHADER_IR_TGSI
) {
2013 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
2019 tgsi_scan_shader(state
->tokens
, &sel
->info
);
2020 tgsi_scan_tess_ctrl(state
->tokens
, &sel
->info
, &sel
->tcs_info
);
2022 assert(state
->type
== PIPE_SHADER_IR_NIR
);
2024 sel
->nir
= state
->ir
.nir
;
2026 si_nir_scan_shader(sel
->nir
, &sel
->info
);
2031 sel
->type
= sel
->info
.processor
;
2032 p_atomic_inc(&sscreen
->b
.num_shaders_created
);
2033 si_get_active_slot_masks(&sel
->info
,
2034 &sel
->active_const_and_shader_buffers
,
2035 &sel
->active_samplers_and_images
);
2037 /* Record which streamout buffers are enabled. */
2038 for (i
= 0; i
< sel
->so
.num_outputs
; i
++) {
2039 sel
->enabled_streamout_buffer_mask
|=
2040 (1 << sel
->so
.output
[i
].output_buffer
) <<
2041 (sel
->so
.output
[i
].stream
* 4);
2044 /* The prolog is a no-op if there are no inputs. */
2045 sel
->vs_needs_prolog
= sel
->type
== PIPE_SHADER_VERTEX
&&
2046 sel
->info
.num_inputs
;
2048 /* Set which opcode uses which (i,j) pair. */
2049 if (sel
->info
.uses_persp_opcode_interp_centroid
)
2050 sel
->info
.uses_persp_centroid
= true;
2052 if (sel
->info
.uses_linear_opcode_interp_centroid
)
2053 sel
->info
.uses_linear_centroid
= true;
2055 if (sel
->info
.uses_persp_opcode_interp_offset
||
2056 sel
->info
.uses_persp_opcode_interp_sample
)
2057 sel
->info
.uses_persp_center
= true;
2059 if (sel
->info
.uses_linear_opcode_interp_offset
||
2060 sel
->info
.uses_linear_opcode_interp_sample
)
2061 sel
->info
.uses_linear_center
= true;
2063 switch (sel
->type
) {
2064 case PIPE_SHADER_GEOMETRY
:
2065 sel
->gs_output_prim
=
2066 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
2067 sel
->gs_max_out_vertices
=
2068 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
2069 sel
->gs_num_invocations
=
2070 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
2071 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
2072 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
2073 sel
->gs_max_out_vertices
;
2075 sel
->max_gs_stream
= 0;
2076 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
2077 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
2078 sel
->so
.output
[i
].stream
);
2080 sel
->gs_input_verts_per_prim
=
2081 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
2084 case PIPE_SHADER_TESS_CTRL
:
2085 /* Always reserve space for these. */
2086 sel
->patch_outputs_written
|=
2087 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0)) |
2088 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0));
2090 case PIPE_SHADER_VERTEX
:
2091 case PIPE_SHADER_TESS_EVAL
:
2092 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2093 unsigned name
= sel
->info
.output_semantic_name
[i
];
2094 unsigned index
= sel
->info
.output_semantic_index
[i
];
2097 case TGSI_SEMANTIC_TESSINNER
:
2098 case TGSI_SEMANTIC_TESSOUTER
:
2099 case TGSI_SEMANTIC_PATCH
:
2100 sel
->patch_outputs_written
|=
2101 1ull << si_shader_io_get_unique_index_patch(name
, index
);
2104 case TGSI_SEMANTIC_GENERIC
:
2105 /* don't process indices the function can't handle */
2106 if (index
>= SI_MAX_IO_GENERIC
)
2110 sel
->outputs_written
|=
2111 1ull << si_shader_io_get_unique_index(name
, index
);
2113 case TGSI_SEMANTIC_CLIPVERTEX
: /* ignore these */
2114 case TGSI_SEMANTIC_EDGEFLAG
:
2118 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
2120 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2121 * conflicts, i.e. each vertex will start at a different bank.
2123 if (sctx
->b
.chip_class
>= GFX9
)
2124 sel
->esgs_itemsize
+= 4;
2127 case PIPE_SHADER_FRAGMENT
:
2128 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2129 unsigned name
= sel
->info
.input_semantic_name
[i
];
2130 unsigned index
= sel
->info
.input_semantic_index
[i
];
2133 case TGSI_SEMANTIC_GENERIC
:
2134 /* don't process indices the function can't handle */
2135 if (index
>= SI_MAX_IO_GENERIC
)
2140 1ull << si_shader_io_get_unique_index(name
, index
);
2142 case TGSI_SEMANTIC_PCOORD
: /* ignore this */
2147 for (i
= 0; i
< 8; i
++)
2148 if (sel
->info
.colors_written
& (1 << i
))
2149 sel
->colors_written_4bit
|= 0xf << (4 * i
);
2151 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2152 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
2153 int index
= sel
->info
.input_semantic_index
[i
];
2154 sel
->color_attr_index
[index
] = i
;
2160 /* PA_CL_VS_OUT_CNTL */
2162 sel
->info
.writes_psize
|| sel
->info
.writes_edgeflag
||
2163 sel
->info
.writes_layer
|| sel
->info
.writes_viewport_index
;
2164 sel
->pa_cl_vs_out_cntl
=
2165 S_02881C_USE_VTX_POINT_SIZE(sel
->info
.writes_psize
) |
2166 S_02881C_USE_VTX_EDGE_FLAG(sel
->info
.writes_edgeflag
) |
2167 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel
->info
.writes_layer
) |
2168 S_02881C_USE_VTX_VIEWPORT_INDX(sel
->info
.writes_viewport_index
) |
2169 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
2170 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
);
2171 sel
->clipdist_mask
= sel
->info
.writes_clipvertex
?
2172 SIX_BITS
: sel
->info
.clipdist_writemask
;
2173 sel
->culldist_mask
= sel
->info
.culldist_writemask
<<
2174 sel
->info
.num_written_clipdistance
;
2176 /* DB_SHADER_CONTROL */
2177 sel
->db_shader_control
=
2178 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
2179 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
2180 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
2181 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
2183 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
2184 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2185 sel
->db_shader_control
|=
2186 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2188 case TGSI_FS_DEPTH_LAYOUT_LESS
:
2189 sel
->db_shader_control
|=
2190 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2194 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2196 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2197 * --|-----------|------------|------------|--------------------|-------------------|-------------
2198 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2199 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2200 * 2 | false | true | n/a | LateZ | 1 | 0
2201 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2202 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2204 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2205 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2207 * Don't use ReZ without profiling !!!
2209 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2212 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
2214 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
2215 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
2216 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
2217 } else if (sel
->info
.writes_memory
) {
2219 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) |
2220 S_02880C_EXEC_ON_HIER_FAIL(1);
2223 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2226 (void) mtx_init(&sel
->mutex
, mtx_plain
);
2227 util_queue_fence_init(&sel
->ready
);
2229 if ((sctx
->b
.debug
.debug_message
&& !sctx
->b
.debug
.async
) ||
2231 si_can_dump_shader(&sscreen
->b
, sel
->info
.processor
))
2232 si_init_shader_selector_async(sel
, -1);
2234 util_queue_add_job(&sscreen
->shader_compiler_queue
, sel
,
2235 &sel
->ready
, si_init_shader_selector_async
,
2241 static void si_update_streamout_state(struct si_context
*sctx
)
2243 struct si_shader_selector
*shader_with_so
= si_get_vs(sctx
)->cso
;
2245 if (!shader_with_so
)
2248 sctx
->b
.streamout
.enabled_stream_buffers_mask
=
2249 shader_with_so
->enabled_streamout_buffer_mask
;
2250 sctx
->b
.streamout
.stride_in_dw
= shader_with_so
->so
.stride
;
2253 static void si_update_clip_regs(struct si_context
*sctx
,
2254 struct si_shader_selector
*old_hw_vs
,
2255 struct si_shader
*old_hw_vs_variant
,
2256 struct si_shader_selector
*next_hw_vs
,
2257 struct si_shader
*next_hw_vs_variant
)
2261 old_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] !=
2262 next_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] ||
2263 old_hw_vs
->pa_cl_vs_out_cntl
!= next_hw_vs
->pa_cl_vs_out_cntl
||
2264 old_hw_vs
->clipdist_mask
!= next_hw_vs
->clipdist_mask
||
2265 old_hw_vs
->culldist_mask
!= next_hw_vs
->culldist_mask
||
2266 !old_hw_vs_variant
||
2267 !next_hw_vs_variant
||
2268 old_hw_vs_variant
->key
.opt
.clip_disable
!=
2269 next_hw_vs_variant
->key
.opt
.clip_disable
))
2270 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
2273 static void si_update_common_shader_state(struct si_context
*sctx
)
2275 sctx
->uses_bindless_samplers
=
2276 si_shader_uses_bindless_samplers(sctx
->vs_shader
.cso
) ||
2277 si_shader_uses_bindless_samplers(sctx
->gs_shader
.cso
) ||
2278 si_shader_uses_bindless_samplers(sctx
->ps_shader
.cso
) ||
2279 si_shader_uses_bindless_samplers(sctx
->tcs_shader
.cso
) ||
2280 si_shader_uses_bindless_samplers(sctx
->tes_shader
.cso
);
2281 sctx
->uses_bindless_images
=
2282 si_shader_uses_bindless_images(sctx
->vs_shader
.cso
) ||
2283 si_shader_uses_bindless_images(sctx
->gs_shader
.cso
) ||
2284 si_shader_uses_bindless_images(sctx
->ps_shader
.cso
) ||
2285 si_shader_uses_bindless_images(sctx
->tcs_shader
.cso
) ||
2286 si_shader_uses_bindless_images(sctx
->tes_shader
.cso
);
2287 sctx
->do_update_shaders
= true;
2290 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
2292 struct si_context
*sctx
= (struct si_context
*)ctx
;
2293 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2294 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2295 struct si_shader_selector
*sel
= state
;
2297 if (sctx
->vs_shader
.cso
== sel
)
2300 sctx
->vs_shader
.cso
= sel
;
2301 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2303 si_update_common_shader_state(sctx
);
2304 si_update_vs_writes_viewport_index(sctx
, si_get_vs_info(sctx
));
2305 si_set_active_descriptors_for_shader(sctx
, sel
);
2306 si_update_streamout_state(sctx
);
2307 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2308 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2311 static void si_update_tess_uses_prim_id(struct si_context
*sctx
)
2313 sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
=
2314 (sctx
->tes_shader
.cso
&&
2315 sctx
->tes_shader
.cso
->info
.uses_primid
) ||
2316 (sctx
->tcs_shader
.cso
&&
2317 sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
2318 (sctx
->gs_shader
.cso
&&
2319 sctx
->gs_shader
.cso
->info
.uses_primid
) ||
2320 (sctx
->ps_shader
.cso
&& !sctx
->gs_shader
.cso
&&
2321 sctx
->ps_shader
.cso
->info
.uses_primid
);
2324 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
2326 struct si_context
*sctx
= (struct si_context
*)ctx
;
2327 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2328 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2329 struct si_shader_selector
*sel
= state
;
2330 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
2332 if (sctx
->gs_shader
.cso
== sel
)
2335 sctx
->gs_shader
.cso
= sel
;
2336 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2337 sctx
->ia_multi_vgt_param_key
.u
.uses_gs
= sel
!= NULL
;
2339 si_update_common_shader_state(sctx
);
2340 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2342 if (enable_changed
) {
2343 si_shader_change_notify(sctx
);
2344 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2345 si_update_tess_uses_prim_id(sctx
);
2347 si_update_vs_writes_viewport_index(sctx
, si_get_vs_info(sctx
));
2348 si_set_active_descriptors_for_shader(sctx
, sel
);
2349 si_update_streamout_state(sctx
);
2350 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2351 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2354 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
2356 struct si_context
*sctx
= (struct si_context
*)ctx
;
2357 struct si_shader_selector
*sel
= state
;
2358 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
2360 if (sctx
->tcs_shader
.cso
== sel
)
2363 sctx
->tcs_shader
.cso
= sel
;
2364 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2365 si_update_tess_uses_prim_id(sctx
);
2367 si_update_common_shader_state(sctx
);
2370 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
2372 si_set_active_descriptors_for_shader(sctx
, sel
);
2375 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
2377 struct si_context
*sctx
= (struct si_context
*)ctx
;
2378 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2379 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2380 struct si_shader_selector
*sel
= state
;
2381 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
2383 if (sctx
->tes_shader
.cso
== sel
)
2386 sctx
->tes_shader
.cso
= sel
;
2387 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
2388 sctx
->ia_multi_vgt_param_key
.u
.uses_tess
= sel
!= NULL
;
2389 si_update_tess_uses_prim_id(sctx
);
2391 si_update_common_shader_state(sctx
);
2392 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2394 if (enable_changed
) {
2395 si_shader_change_notify(sctx
);
2396 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
2398 si_update_vs_writes_viewport_index(sctx
, si_get_vs_info(sctx
));
2399 si_set_active_descriptors_for_shader(sctx
, sel
);
2400 si_update_streamout_state(sctx
);
2401 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2402 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2405 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
2407 struct si_context
*sctx
= (struct si_context
*)ctx
;
2408 struct si_shader_selector
*old_sel
= sctx
->ps_shader
.cso
;
2409 struct si_shader_selector
*sel
= state
;
2411 /* skip if supplied shader is one already in use */
2415 sctx
->ps_shader
.cso
= sel
;
2416 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
2418 si_update_common_shader_state(sctx
);
2420 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2421 si_update_tess_uses_prim_id(sctx
);
2424 old_sel
->info
.colors_written
!= sel
->info
.colors_written
)
2425 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
2427 if (sctx
->screen
->has_out_of_order_rast
&&
2429 old_sel
->info
.writes_memory
!= sel
->info
.writes_memory
||
2430 old_sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] !=
2431 sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]))
2432 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2434 si_set_active_descriptors_for_shader(sctx
, sel
);
2437 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
2439 if (shader
->is_optimized
) {
2440 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue_low_priority
,
2441 &shader
->optimized_ready
);
2442 util_queue_fence_destroy(&shader
->optimized_ready
);
2446 switch (shader
->selector
->type
) {
2447 case PIPE_SHADER_VERTEX
:
2448 if (shader
->key
.as_ls
) {
2449 assert(sctx
->b
.chip_class
<= VI
);
2450 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
2451 } else if (shader
->key
.as_es
) {
2452 assert(sctx
->b
.chip_class
<= VI
);
2453 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2455 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2458 case PIPE_SHADER_TESS_CTRL
:
2459 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
2461 case PIPE_SHADER_TESS_EVAL
:
2462 if (shader
->key
.as_es
) {
2463 assert(sctx
->b
.chip_class
<= VI
);
2464 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2466 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2469 case PIPE_SHADER_GEOMETRY
:
2470 if (shader
->is_gs_copy_shader
)
2471 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2473 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
2475 case PIPE_SHADER_FRAGMENT
:
2476 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
2481 si_shader_selector_reference(sctx
, &shader
->previous_stage_sel
, NULL
);
2482 si_shader_destroy(shader
);
2486 void si_destroy_shader_selector(struct si_context
*sctx
,
2487 struct si_shader_selector
*sel
)
2489 struct si_shader
*p
= sel
->first_variant
, *c
;
2490 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
2491 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
2492 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
2493 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
2494 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
2495 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
2498 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue
, &sel
->ready
);
2500 if (current_shader
[sel
->type
]->cso
== sel
) {
2501 current_shader
[sel
->type
]->cso
= NULL
;
2502 current_shader
[sel
->type
]->current
= NULL
;
2506 c
= p
->next_variant
;
2507 si_delete_shader(sctx
, p
);
2511 if (sel
->main_shader_part
)
2512 si_delete_shader(sctx
, sel
->main_shader_part
);
2513 if (sel
->main_shader_part_ls
)
2514 si_delete_shader(sctx
, sel
->main_shader_part_ls
);
2515 if (sel
->main_shader_part_es
)
2516 si_delete_shader(sctx
, sel
->main_shader_part_es
);
2517 if (sel
->gs_copy_shader
)
2518 si_delete_shader(sctx
, sel
->gs_copy_shader
);
2520 util_queue_fence_destroy(&sel
->ready
);
2521 mtx_destroy(&sel
->mutex
);
2523 ralloc_free(sel
->nir
);
2527 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
2529 struct si_context
*sctx
= (struct si_context
*)ctx
;
2530 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
2532 si_shader_selector_reference(sctx
, &sel
, NULL
);
2535 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
2536 struct si_shader
*vs
, unsigned name
,
2537 unsigned index
, unsigned interpolate
)
2539 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
2540 unsigned j
, offset
, ps_input_cntl
= 0;
2542 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2543 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
))
2544 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
2546 if (name
== TGSI_SEMANTIC_PCOORD
||
2547 (name
== TGSI_SEMANTIC_TEXCOORD
&&
2548 sctx
->sprite_coord_enable
& (1 << index
))) {
2549 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
2552 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
2553 if (name
== vsinfo
->output_semantic_name
[j
] &&
2554 index
== vsinfo
->output_semantic_index
[j
]) {
2555 offset
= vs
->info
.vs_output_param_offset
[j
];
2557 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
2558 /* The input is loaded from parameter memory. */
2559 ps_input_cntl
|= S_028644_OFFSET(offset
);
2560 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2561 if (offset
== AC_EXP_PARAM_UNDEFINED
) {
2562 /* This can happen with depth-only rendering. */
2565 /* The input is a DEFAULT_VAL constant. */
2566 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
2567 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
2568 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
2571 ps_input_cntl
= S_028644_OFFSET(0x20) |
2572 S_028644_DEFAULT_VAL(offset
);
2578 if (name
== TGSI_SEMANTIC_PRIMID
)
2579 /* PrimID is written after the last output. */
2580 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
2581 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2582 /* No corresponding output found, load defaults into input.
2583 * Don't set any other bits.
2584 * (FLAT_SHADE=1 completely changes behavior) */
2585 ps_input_cntl
= S_028644_OFFSET(0x20);
2586 /* D3D 9 behaviour. GL is undefined */
2587 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
2588 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
2590 return ps_input_cntl
;
2593 static void si_emit_spi_map(struct si_context
*sctx
, struct r600_atom
*atom
)
2595 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2596 struct si_shader
*ps
= sctx
->ps_shader
.current
;
2597 struct si_shader
*vs
= si_get_vs_state(sctx
);
2598 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
2599 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
2601 if (!ps
|| !ps
->selector
->info
.num_inputs
)
2604 num_interp
= si_get_ps_num_interp(ps
);
2605 assert(num_interp
> 0);
2606 radeon_set_context_reg_seq(cs
, R_028644_SPI_PS_INPUT_CNTL_0
, num_interp
);
2608 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
2609 unsigned name
= psinfo
->input_semantic_name
[i
];
2610 unsigned index
= psinfo
->input_semantic_index
[i
];
2611 unsigned interpolate
= psinfo
->input_interpolate
[i
];
2613 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, name
, index
,
2617 if (name
== TGSI_SEMANTIC_COLOR
) {
2618 assert(index
< ARRAY_SIZE(bcol_interp
));
2619 bcol_interp
[index
] = interpolate
;
2623 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
2624 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
2626 for (i
= 0; i
< 2; i
++) {
2627 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
2630 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, bcol
,
2631 i
, bcol_interp
[i
]));
2635 assert(num_interp
== num_written
);
2639 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2641 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
2643 if (sctx
->init_config_has_vgt_flush
)
2646 /* Done by Vulkan before VGT_FLUSH. */
2647 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2648 si_pm4_cmd_add(sctx
->init_config
,
2649 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2650 si_pm4_cmd_end(sctx
->init_config
, false);
2652 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2653 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2654 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
2655 si_pm4_cmd_end(sctx
->init_config
, false);
2656 sctx
->init_config_has_vgt_flush
= true;
2659 /* Initialize state related to ESGS / GSVS ring buffers */
2660 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
2662 struct si_shader_selector
*es
=
2663 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
2664 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
2665 struct si_pm4_state
*pm4
;
2667 /* Chip constants. */
2668 unsigned num_se
= sctx
->screen
->b
.info
.max_se
;
2669 unsigned wave_size
= 64;
2670 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
2671 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2672 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2674 unsigned gs_vertex_reuse
= (sctx
->b
.chip_class
>= VI
? 32 : 16) * num_se
;
2675 unsigned alignment
= 256 * num_se
;
2676 /* The maximum size is 63.999 MB per SE. */
2677 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
2679 /* Calculate the minimum size. */
2680 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
2681 wave_size
, alignment
);
2683 /* These are recommended sizes, not minimum sizes. */
2684 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
2685 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
2686 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
2687 gs
->max_gsvs_emit_size
;
2689 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
2690 esgs_ring_size
= align(esgs_ring_size
, alignment
);
2691 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
2693 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
2694 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
2696 /* Some rings don't have to be allocated if shaders don't use them.
2697 * (e.g. no varyings between ES and GS or GS and VS)
2699 * GFX9 doesn't have the ESGS ring.
2701 bool update_esgs
= sctx
->b
.chip_class
<= VI
&&
2703 (!sctx
->esgs_ring
||
2704 sctx
->esgs_ring
->width0
< esgs_ring_size
);
2705 bool update_gsvs
= gsvs_ring_size
&&
2706 (!sctx
->gsvs_ring
||
2707 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
2709 if (!update_esgs
&& !update_gsvs
)
2713 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
2715 si_aligned_buffer_create(sctx
->b
.b
.screen
,
2716 R600_RESOURCE_FLAG_UNMAPPABLE
,
2718 esgs_ring_size
, alignment
);
2719 if (!sctx
->esgs_ring
)
2724 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
2726 si_aligned_buffer_create(sctx
->b
.b
.screen
,
2727 R600_RESOURCE_FLAG_UNMAPPABLE
,
2729 gsvs_ring_size
, alignment
);
2730 if (!sctx
->gsvs_ring
)
2734 /* Create the "init_config_gs_rings" state. */
2735 pm4
= CALLOC_STRUCT(si_pm4_state
);
2739 if (sctx
->b
.chip_class
>= CIK
) {
2740 if (sctx
->esgs_ring
) {
2741 assert(sctx
->b
.chip_class
<= VI
);
2742 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
2743 sctx
->esgs_ring
->width0
/ 256);
2745 if (sctx
->gsvs_ring
)
2746 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
2747 sctx
->gsvs_ring
->width0
/ 256);
2749 if (sctx
->esgs_ring
)
2750 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
2751 sctx
->esgs_ring
->width0
/ 256);
2752 if (sctx
->gsvs_ring
)
2753 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
2754 sctx
->gsvs_ring
->width0
/ 256);
2757 /* Set the state. */
2758 if (sctx
->init_config_gs_rings
)
2759 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
2760 sctx
->init_config_gs_rings
= pm4
;
2762 if (!sctx
->init_config_has_vgt_flush
) {
2763 si_init_config_add_vgt_flush(sctx
);
2764 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
2767 /* Flush the context to re-emit both init_config states. */
2768 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
2769 si_context_gfx_flush(sctx
, RADEON_FLUSH_ASYNC
, NULL
);
2771 /* Set ring bindings. */
2772 if (sctx
->esgs_ring
) {
2773 assert(sctx
->b
.chip_class
<= VI
);
2774 si_set_ring_buffer(&sctx
->b
.b
, SI_ES_RING_ESGS
,
2775 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
2776 true, true, 4, 64, 0);
2777 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_ESGS
,
2778 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
2779 false, false, 0, 0, 0);
2781 if (sctx
->gsvs_ring
) {
2782 si_set_ring_buffer(&sctx
->b
.b
, SI_RING_GSVS
,
2783 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
2784 false, false, 0, 0, 0);
2790 static void si_shader_lock(struct si_shader
*shader
)
2792 mtx_lock(&shader
->selector
->mutex
);
2793 if (shader
->previous_stage_sel
) {
2794 assert(shader
->previous_stage_sel
!= shader
->selector
);
2795 mtx_lock(&shader
->previous_stage_sel
->mutex
);
2799 static void si_shader_unlock(struct si_shader
*shader
)
2801 if (shader
->previous_stage_sel
)
2802 mtx_unlock(&shader
->previous_stage_sel
->mutex
);
2803 mtx_unlock(&shader
->selector
->mutex
);
2807 * @returns 1 if \p sel has been updated to use a new scratch buffer
2809 * < 0 if there was a failure
2811 static int si_update_scratch_buffer(struct si_context
*sctx
,
2812 struct si_shader
*shader
)
2814 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
2820 /* This shader doesn't need a scratch buffer */
2821 if (shader
->config
.scratch_bytes_per_wave
== 0)
2824 /* Prevent race conditions when updating:
2825 * - si_shader::scratch_bo
2826 * - si_shader::binary::code
2827 * - si_shader::previous_stage::binary::code.
2829 si_shader_lock(shader
);
2831 /* This shader is already configured to use the current
2832 * scratch buffer. */
2833 if (shader
->scratch_bo
== sctx
->scratch_buffer
) {
2834 si_shader_unlock(shader
);
2838 assert(sctx
->scratch_buffer
);
2840 if (shader
->previous_stage
)
2841 si_shader_apply_scratch_relocs(shader
->previous_stage
, scratch_va
);
2843 si_shader_apply_scratch_relocs(shader
, scratch_va
);
2845 /* Replace the shader bo with a new bo that has the relocs applied. */
2846 r
= si_shader_binary_upload(sctx
->screen
, shader
);
2848 si_shader_unlock(shader
);
2852 /* Update the shader state to use the new shader bo. */
2853 si_shader_init_pm4_state(sctx
->screen
, shader
);
2855 r600_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
2857 si_shader_unlock(shader
);
2861 static unsigned si_get_current_scratch_buffer_size(struct si_context
*sctx
)
2863 return sctx
->scratch_buffer
? sctx
->scratch_buffer
->b
.b
.width0
: 0;
2866 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
2868 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
2871 static struct si_shader
*si_get_tcs_current(struct si_context
*sctx
)
2873 if (!sctx
->tes_shader
.cso
)
2874 return NULL
; /* tessellation disabled */
2876 return sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.current
:
2877 sctx
->fixed_func_tcs_shader
.current
;
2880 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context
*sctx
)
2884 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
2885 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
2886 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
2887 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
2889 if (sctx
->tes_shader
.cso
) {
2890 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
2892 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(tcs
));
2897 static bool si_update_scratch_relocs(struct si_context
*sctx
)
2899 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
2902 /* Update the shaders, so that they are using the latest scratch.
2903 * The scratch buffer may have been changed since these shaders were
2904 * last used, so we still need to try to update them, even if they
2905 * require scratch buffers smaller than the current size.
2907 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
2911 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
2913 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
2917 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
2919 r
= si_update_scratch_buffer(sctx
, tcs
);
2923 si_pm4_bind_state(sctx
, hs
, tcs
->pm4
);
2925 /* VS can be bound as LS, ES, or VS. */
2926 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
2930 if (sctx
->tes_shader
.current
)
2931 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
2932 else if (sctx
->gs_shader
.current
)
2933 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
2935 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
2938 /* TES can be bound as ES or VS. */
2939 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
2943 if (sctx
->gs_shader
.current
)
2944 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
2946 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
2952 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
2954 unsigned current_scratch_buffer_size
=
2955 si_get_current_scratch_buffer_size(sctx
);
2956 unsigned scratch_bytes_per_wave
=
2957 si_get_max_scratch_bytes_per_wave(sctx
);
2958 unsigned scratch_needed_size
= scratch_bytes_per_wave
*
2959 sctx
->scratch_waves
;
2960 unsigned spi_tmpring_size
;
2962 if (scratch_needed_size
> 0) {
2963 if (scratch_needed_size
> current_scratch_buffer_size
) {
2964 /* Create a bigger scratch buffer */
2965 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
2967 sctx
->scratch_buffer
= (struct r600_resource
*)
2968 si_aligned_buffer_create(&sctx
->screen
->b
.b
,
2969 R600_RESOURCE_FLAG_UNMAPPABLE
,
2971 scratch_needed_size
, 256);
2972 if (!sctx
->scratch_buffer
)
2975 si_mark_atom_dirty(sctx
, &sctx
->scratch_state
);
2976 r600_context_add_resource_size(&sctx
->b
.b
,
2977 &sctx
->scratch_buffer
->b
.b
);
2980 if (!si_update_scratch_relocs(sctx
))
2984 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
2985 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
2986 "scratch size should already be aligned correctly.");
2988 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
2989 S_0286E8_WAVESIZE(scratch_bytes_per_wave
>> 10);
2990 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
2991 sctx
->spi_tmpring_size
= spi_tmpring_size
;
2992 si_mark_atom_dirty(sctx
, &sctx
->scratch_state
);
2997 static void si_init_tess_factor_ring(struct si_context
*sctx
)
2999 bool double_offchip_buffers
= sctx
->b
.chip_class
>= CIK
&&
3000 sctx
->b
.family
!= CHIP_CARRIZO
&&
3001 sctx
->b
.family
!= CHIP_STONEY
;
3002 /* This must be one less than the maximum number due to a hw limitation.
3003 * Various hardware bugs in SI, CIK, and GFX9 need this.
3005 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 127 : 63;
3006 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
3007 sctx
->screen
->b
.info
.max_se
;
3008 unsigned offchip_granularity
;
3010 switch (sctx
->screen
->tess_offchip_block_dw_size
) {
3015 offchip_granularity
= V_03093C_X_8K_DWORDS
;
3018 offchip_granularity
= V_03093C_X_4K_DWORDS
;
3022 assert(!sctx
->tf_ring
);
3023 /* Use 64K alignment for both rings, so that we can pass the address
3024 * to shaders as one SGPR containing bits [16:47].
3026 sctx
->tf_ring
= si_aligned_buffer_create(sctx
->b
.b
.screen
,
3027 R600_RESOURCE_FLAG_UNMAPPABLE
,
3029 32768 * sctx
->screen
->b
.info
.max_se
,
3034 assert(((sctx
->tf_ring
->width0
/ 4) & C_030938_SIZE
) == 0);
3036 sctx
->tess_offchip_ring
=
3037 si_aligned_buffer_create(sctx
->b
.b
.screen
,
3038 R600_RESOURCE_FLAG_UNMAPPABLE
,
3040 max_offchip_buffers
*
3041 sctx
->screen
->tess_offchip_block_dw_size
* 4,
3043 if (!sctx
->tess_offchip_ring
)
3046 si_init_config_add_vgt_flush(sctx
);
3048 uint64_t offchip_va
= r600_resource(sctx
->tess_offchip_ring
)->gpu_address
;
3049 uint64_t factor_va
= r600_resource(sctx
->tf_ring
)->gpu_address
;
3050 assert((offchip_va
& 0xffff) == 0);
3051 assert((factor_va
& 0xffff) == 0);
3053 si_pm4_add_bo(sctx
->init_config
, r600_resource(sctx
->tess_offchip_ring
),
3054 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
3055 si_pm4_add_bo(sctx
->init_config
, r600_resource(sctx
->tf_ring
),
3056 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
3058 /* Append these registers to the init config state. */
3059 if (sctx
->b
.chip_class
>= CIK
) {
3060 if (sctx
->b
.chip_class
>= VI
)
3061 --max_offchip_buffers
;
3063 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
3064 S_030938_SIZE(sctx
->tf_ring
->width0
/ 4));
3065 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
3067 if (sctx
->b
.chip_class
>= GFX9
)
3068 si_pm4_set_reg(sctx
->init_config
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3070 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3071 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
3072 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
));
3074 assert(offchip_granularity
== V_03093C_X_8K_DWORDS
);
3075 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
3076 S_008988_SIZE(sctx
->tf_ring
->width0
/ 4));
3077 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
3079 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3080 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
));
3083 if (sctx
->b
.chip_class
>= GFX9
) {
3084 si_pm4_set_reg(sctx
->init_config
,
3085 R_00B430_SPI_SHADER_USER_DATA_LS_0
+
3086 GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K
* 4,
3088 si_pm4_set_reg(sctx
->init_config
,
3089 R_00B430_SPI_SHADER_USER_DATA_LS_0
+
3090 GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K
* 4,
3093 si_pm4_set_reg(sctx
->init_config
,
3094 R_00B430_SPI_SHADER_USER_DATA_HS_0
+
3095 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K
* 4,
3097 si_pm4_set_reg(sctx
->init_config
,
3098 R_00B430_SPI_SHADER_USER_DATA_HS_0
+
3099 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K
* 4,
3103 /* Flush the context to re-emit the init_config state.
3104 * This is done only once in a lifetime of a context.
3106 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3107 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
3108 si_context_gfx_flush(sctx
, RADEON_FLUSH_ASYNC
, NULL
);
3112 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
3113 * VS passes its outputs to TES directly, so the fixed-function shader only
3114 * has to write TESSOUTER and TESSINNER.
3116 static void si_generate_fixed_func_tcs(struct si_context
*sctx
)
3118 struct ureg_src outer
, inner
;
3119 struct ureg_dst tessouter
, tessinner
;
3120 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_TESS_CTRL
);
3123 return; /* if we get here, we're screwed */
3125 assert(!sctx
->fixed_func_tcs_shader
.cso
);
3127 outer
= ureg_DECL_system_value(ureg
,
3128 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
, 0);
3129 inner
= ureg_DECL_system_value(ureg
,
3130 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
, 0);
3132 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
3133 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
3135 ureg_MOV(ureg
, tessouter
, outer
);
3136 ureg_MOV(ureg
, tessinner
, inner
);
3139 sctx
->fixed_func_tcs_shader
.cso
=
3140 ureg_create_shader_and_destroy(ureg
, &sctx
->b
.b
);
3143 static void si_update_vgt_shader_config(struct si_context
*sctx
)
3145 /* Calculate the index of the config.
3146 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3147 unsigned index
= 2*!!sctx
->tes_shader
.cso
+ !!sctx
->gs_shader
.cso
;
3148 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[index
];
3151 uint32_t stages
= 0;
3153 *pm4
= CALLOC_STRUCT(si_pm4_state
);
3155 if (sctx
->tes_shader
.cso
) {
3156 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3157 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3159 if (sctx
->gs_shader
.cso
)
3160 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3162 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3164 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3165 } else if (sctx
->gs_shader
.cso
) {
3166 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3168 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3171 if (sctx
->b
.chip_class
>= GFX9
)
3172 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3174 si_pm4_set_reg(*pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
3176 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
3179 bool si_update_shaders(struct si_context
*sctx
)
3181 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
3182 struct si_compiler_ctx_state compiler_state
;
3183 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3184 struct si_shader
*old_vs
= si_get_vs_state(sctx
);
3185 bool old_clip_disable
= old_vs
? old_vs
->key
.opt
.clip_disable
: false;
3186 struct si_shader
*old_ps
= sctx
->ps_shader
.current
;
3187 unsigned old_spi_shader_col_format
=
3188 old_ps
? old_ps
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
3191 compiler_state
.tm
= sctx
->tm
;
3192 compiler_state
.debug
= sctx
->b
.debug
;
3193 compiler_state
.is_debug_context
= sctx
->is_debug
;
3195 /* Update stages before GS. */
3196 if (sctx
->tes_shader
.cso
) {
3197 if (!sctx
->tf_ring
) {
3198 si_init_tess_factor_ring(sctx
);
3204 if (sctx
->b
.chip_class
<= VI
) {
3205 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
3209 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3212 if (sctx
->tcs_shader
.cso
) {
3213 r
= si_shader_select(ctx
, &sctx
->tcs_shader
,
3217 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
3219 if (!sctx
->fixed_func_tcs_shader
.cso
) {
3220 si_generate_fixed_func_tcs(sctx
);
3221 if (!sctx
->fixed_func_tcs_shader
.cso
)
3225 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
,
3229 si_pm4_bind_state(sctx
, hs
,
3230 sctx
->fixed_func_tcs_shader
.current
->pm4
);
3233 if (sctx
->gs_shader
.cso
) {
3235 if (sctx
->b
.chip_class
<= VI
) {
3236 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
3240 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3244 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
3248 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3250 } else if (sctx
->gs_shader
.cso
) {
3251 if (sctx
->b
.chip_class
<= VI
) {
3253 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
3257 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3259 si_pm4_bind_state(sctx
, ls
, NULL
);
3260 si_pm4_bind_state(sctx
, hs
, NULL
);
3264 r
= si_shader_select(ctx
, &sctx
->vs_shader
, &compiler_state
);
3267 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3268 si_pm4_bind_state(sctx
, ls
, NULL
);
3269 si_pm4_bind_state(sctx
, hs
, NULL
);
3273 if (sctx
->gs_shader
.cso
) {
3274 r
= si_shader_select(ctx
, &sctx
->gs_shader
, &compiler_state
);
3277 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3278 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
3280 if (!si_update_gs_ring_buffers(sctx
))
3283 si_pm4_bind_state(sctx
, gs
, NULL
);
3284 if (sctx
->b
.chip_class
<= VI
)
3285 si_pm4_bind_state(sctx
, es
, NULL
);
3288 si_update_vgt_shader_config(sctx
);
3290 if (old_clip_disable
!= si_get_vs_state(sctx
)->key
.opt
.clip_disable
)
3291 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
3293 if (sctx
->ps_shader
.cso
) {
3294 unsigned db_shader_control
;
3296 r
= si_shader_select(ctx
, &sctx
->ps_shader
, &compiler_state
);
3299 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3302 sctx
->ps_shader
.cso
->db_shader_control
|
3303 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
3305 if (si_pm4_state_changed(sctx
, ps
) || si_pm4_state_changed(sctx
, vs
) ||
3306 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
3307 sctx
->flatshade
!= rs
->flatshade
) {
3308 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
3309 sctx
->flatshade
= rs
->flatshade
;
3310 si_mark_atom_dirty(sctx
, &sctx
->spi_map
);
3313 if (sctx
->screen
->b
.rbplus_allowed
&&
3314 si_pm4_state_changed(sctx
, ps
) &&
3316 old_spi_shader_col_format
!=
3317 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
))
3318 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
3320 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
3321 sctx
->ps_db_shader_control
= db_shader_control
;
3322 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
3323 if (sctx
->screen
->dpbb_allowed
)
3324 si_mark_atom_dirty(sctx
, &sctx
->dpbb_state
);
3327 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
3328 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
3329 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
3331 if (sctx
->b
.chip_class
== SI
)
3332 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
3334 if (sctx
->framebuffer
.nr_samples
<= 1)
3335 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
3339 if (si_pm4_state_enabled_and_changed(sctx
, ls
) ||
3340 si_pm4_state_enabled_and_changed(sctx
, hs
) ||
3341 si_pm4_state_enabled_and_changed(sctx
, es
) ||
3342 si_pm4_state_enabled_and_changed(sctx
, gs
) ||
3343 si_pm4_state_enabled_and_changed(sctx
, vs
) ||
3344 si_pm4_state_enabled_and_changed(sctx
, ps
)) {
3345 if (!si_update_spi_tmpring_size(sctx
))
3349 if (sctx
->b
.chip_class
>= CIK
) {
3350 if (si_pm4_state_enabled_and_changed(sctx
, ls
))
3351 sctx
->prefetch_L2_mask
|= SI_PREFETCH_LS
;
3352 else if (!sctx
->queued
.named
.ls
)
3353 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_LS
;
3355 if (si_pm4_state_enabled_and_changed(sctx
, hs
))
3356 sctx
->prefetch_L2_mask
|= SI_PREFETCH_HS
;
3357 else if (!sctx
->queued
.named
.hs
)
3358 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_HS
;
3360 if (si_pm4_state_enabled_and_changed(sctx
, es
))
3361 sctx
->prefetch_L2_mask
|= SI_PREFETCH_ES
;
3362 else if (!sctx
->queued
.named
.es
)
3363 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_ES
;
3365 if (si_pm4_state_enabled_and_changed(sctx
, gs
))
3366 sctx
->prefetch_L2_mask
|= SI_PREFETCH_GS
;
3367 else if (!sctx
->queued
.named
.gs
)
3368 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_GS
;
3370 if (si_pm4_state_enabled_and_changed(sctx
, vs
))
3371 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VS
;
3372 else if (!sctx
->queued
.named
.vs
)
3373 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_VS
;
3375 if (si_pm4_state_enabled_and_changed(sctx
, ps
))
3376 sctx
->prefetch_L2_mask
|= SI_PREFETCH_PS
;
3377 else if (!sctx
->queued
.named
.ps
)
3378 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_PS
;
3381 sctx
->do_update_shaders
= false;
3385 static void si_emit_scratch_state(struct si_context
*sctx
,
3386 struct r600_atom
*atom
)
3388 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
3390 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
3391 sctx
->spi_tmpring_size
);
3393 if (sctx
->scratch_buffer
) {
3394 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
3395 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
3396 RADEON_PRIO_SCRATCH_BUFFER
);
3400 void si_init_shader_functions(struct si_context
*sctx
)
3402 si_init_atom(sctx
, &sctx
->spi_map
, &sctx
->atoms
.s
.spi_map
, si_emit_spi_map
);
3403 si_init_atom(sctx
, &sctx
->scratch_state
, &sctx
->atoms
.s
.scratch_state
,
3404 si_emit_scratch_state
);
3406 sctx
->b
.b
.create_vs_state
= si_create_shader_selector
;
3407 sctx
->b
.b
.create_tcs_state
= si_create_shader_selector
;
3408 sctx
->b
.b
.create_tes_state
= si_create_shader_selector
;
3409 sctx
->b
.b
.create_gs_state
= si_create_shader_selector
;
3410 sctx
->b
.b
.create_fs_state
= si_create_shader_selector
;
3412 sctx
->b
.b
.bind_vs_state
= si_bind_vs_shader
;
3413 sctx
->b
.b
.bind_tcs_state
= si_bind_tcs_shader
;
3414 sctx
->b
.b
.bind_tes_state
= si_bind_tes_shader
;
3415 sctx
->b
.b
.bind_gs_state
= si_bind_gs_shader
;
3416 sctx
->b
.b
.bind_fs_state
= si_bind_ps_shader
;
3418 sctx
->b
.b
.delete_vs_state
= si_delete_shader_selector
;
3419 sctx
->b
.b
.delete_tcs_state
= si_delete_shader_selector
;
3420 sctx
->b
.b
.delete_tes_state
= si_delete_shader_selector
;
3421 sctx
->b
.b
.delete_gs_state
= si_delete_shader_selector
;
3422 sctx
->b
.b
.delete_fs_state
= si_delete_shader_selector
;