2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
30 #include "radeon/r600_cs.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_ureg.h"
34 #include "util/hash_table.h"
35 #include "util/u_hash.h"
36 #include "util/u_memory.h"
37 #include "util/u_prim.h"
42 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
45 static void *si_get_tgsi_binary(struct si_shader_selector
*sel
)
47 unsigned tgsi_size
= tgsi_num_tokens(sel
->tokens
) *
48 sizeof(struct tgsi_token
);
49 unsigned size
= 4 + tgsi_size
+ sizeof(sel
->so
);
50 char *result
= (char*)MALLOC(size
);
55 *((uint32_t*)result
) = size
;
56 memcpy(result
+ 4, sel
->tokens
, tgsi_size
);
57 memcpy(result
+ 4 + tgsi_size
, &sel
->so
, sizeof(sel
->so
));
61 /** Copy "data" to "ptr" and return the next dword following copied data. */
62 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
64 /* data may be NULL if size == 0 */
66 memcpy(ptr
, data
, size
);
67 ptr
+= DIV_ROUND_UP(size
, 4);
71 /** Read data from "ptr". Return the next dword following the data. */
72 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
74 memcpy(data
, ptr
, size
);
75 ptr
+= DIV_ROUND_UP(size
, 4);
80 * Write the size as uint followed by the data. Return the next dword
81 * following the copied data.
83 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
86 return write_data(ptr
, data
, size
);
90 * Read the size as uint followed by the data. Return both via parameters.
91 * Return the next dword following the data.
93 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
96 assert(*data
== NULL
);
99 *data
= malloc(*size
);
100 return read_data(ptr
, *data
, *size
);
104 * Return the shader binary in a buffer. The first 4 bytes contain its size
107 static void *si_get_shader_binary(struct si_shader
*shader
)
109 /* There is always a size of data followed by the data itself. */
110 unsigned relocs_size
= shader
->binary
.reloc_count
*
111 sizeof(shader
->binary
.relocs
[0]);
112 unsigned disasm_size
= strlen(shader
->binary
.disasm_string
) + 1;
113 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
114 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
117 4 + /* CRC32 of the data below */
118 align(sizeof(shader
->config
), 4) +
119 align(sizeof(shader
->info
), 4) +
120 4 + align(shader
->binary
.code_size
, 4) +
121 4 + align(shader
->binary
.rodata_size
, 4) +
122 4 + align(relocs_size
, 4) +
123 4 + align(disasm_size
, 4) +
124 4 + align(llvm_ir_size
, 4);
125 void *buffer
= CALLOC(1, size
);
126 uint32_t *ptr
= (uint32_t*)buffer
;
132 ptr
++; /* CRC32 is calculated at the end. */
134 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
135 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
136 ptr
= write_chunk(ptr
, shader
->binary
.code
, shader
->binary
.code_size
);
137 ptr
= write_chunk(ptr
, shader
->binary
.rodata
, shader
->binary
.rodata_size
);
138 ptr
= write_chunk(ptr
, shader
->binary
.relocs
, relocs_size
);
139 ptr
= write_chunk(ptr
, shader
->binary
.disasm_string
, disasm_size
);
140 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
141 assert((char *)ptr
- (char *)buffer
== size
);
144 ptr
= (uint32_t*)buffer
;
146 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
151 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
153 uint32_t *ptr
= (uint32_t*)binary
;
154 uint32_t size
= *ptr
++;
155 uint32_t crc32
= *ptr
++;
158 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
159 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
163 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
164 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
165 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.code
,
166 &shader
->binary
.code_size
);
167 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.rodata
,
168 &shader
->binary
.rodata_size
);
169 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.relocs
, &chunk_size
);
170 shader
->binary
.reloc_count
= chunk_size
/ sizeof(shader
->binary
.relocs
[0]);
171 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.disasm_string
, &chunk_size
);
172 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
178 * Insert a shader into the cache. It's assumed the shader is not in the cache.
179 * Use si_shader_cache_load_shader before calling this.
181 * Returns false on failure, in which case the tgsi_binary should be freed.
183 static bool si_shader_cache_insert_shader(struct si_screen
*sscreen
,
185 struct si_shader
*shader
)
188 struct hash_entry
*entry
;
190 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, tgsi_binary
);
192 return false; /* already added */
194 hw_binary
= si_get_shader_binary(shader
);
198 if (_mesa_hash_table_insert(sscreen
->shader_cache
, tgsi_binary
,
199 hw_binary
) == NULL
) {
207 static bool si_shader_cache_load_shader(struct si_screen
*sscreen
,
209 struct si_shader
*shader
)
211 struct hash_entry
*entry
=
212 _mesa_hash_table_search(sscreen
->shader_cache
, tgsi_binary
);
216 if (!si_load_shader_binary(shader
, entry
->data
))
219 p_atomic_inc(&sscreen
->b
.num_shader_cache_hits
);
223 static uint32_t si_shader_cache_key_hash(const void *key
)
225 /* The first dword is the key size. */
226 return util_hash_crc32(key
, *(uint32_t*)key
);
229 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
231 uint32_t *keya
= (uint32_t*)a
;
232 uint32_t *keyb
= (uint32_t*)b
;
234 /* The first dword is the key size. */
238 return memcmp(keya
, keyb
, *keya
) == 0;
241 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
243 FREE((void*)entry
->key
);
247 bool si_init_shader_cache(struct si_screen
*sscreen
)
249 pipe_mutex_init(sscreen
->shader_cache_mutex
);
250 sscreen
->shader_cache
=
251 _mesa_hash_table_create(NULL
,
252 si_shader_cache_key_hash
,
253 si_shader_cache_key_equals
);
254 return sscreen
->shader_cache
!= NULL
;
257 void si_destroy_shader_cache(struct si_screen
*sscreen
)
259 if (sscreen
->shader_cache
)
260 _mesa_hash_table_destroy(sscreen
->shader_cache
,
261 si_destroy_shader_cache_entry
);
262 pipe_mutex_destroy(sscreen
->shader_cache_mutex
);
267 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
268 struct si_shader
*shader
,
269 struct si_pm4_state
*pm4
)
271 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
272 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
273 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
274 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
275 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
276 unsigned type
, partitioning
, topology
, distribution_mode
;
278 switch (tes_prim_mode
) {
279 case PIPE_PRIM_LINES
:
280 type
= V_028B6C_TESS_ISOLINE
;
282 case PIPE_PRIM_TRIANGLES
:
283 type
= V_028B6C_TESS_TRIANGLE
;
285 case PIPE_PRIM_QUADS
:
286 type
= V_028B6C_TESS_QUAD
;
293 switch (tes_spacing
) {
294 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
295 partitioning
= V_028B6C_PART_FRAC_ODD
;
297 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
298 partitioning
= V_028B6C_PART_FRAC_EVEN
;
300 case PIPE_TESS_SPACING_EQUAL
:
301 partitioning
= V_028B6C_PART_INTEGER
;
309 topology
= V_028B6C_OUTPUT_POINT
;
310 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
311 topology
= V_028B6C_OUTPUT_LINE
;
312 else if (tes_vertex_order_cw
)
313 /* for some reason, this must be the other way around */
314 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
316 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
318 if (sscreen
->has_distributed_tess
) {
319 if (sscreen
->b
.family
== CHIP_FIJI
||
320 sscreen
->b
.family
>= CHIP_POLARIS10
)
321 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
323 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
325 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
327 si_pm4_set_reg(pm4
, R_028B6C_VGT_TF_PARAM
,
328 S_028B6C_TYPE(type
) |
329 S_028B6C_PARTITIONING(partitioning
) |
330 S_028B6C_TOPOLOGY(topology
) |
331 S_028B6C_DISTRIBUTION_MODE(distribution_mode
));
334 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
337 si_pm4_clear_state(shader
->pm4
);
339 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
344 static void si_shader_ls(struct si_shader
*shader
)
346 struct si_pm4_state
*pm4
;
347 unsigned vgpr_comp_cnt
;
350 pm4
= si_get_shader_pm4_state(shader
);
354 va
= shader
->bo
->gpu_address
;
355 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
357 /* We need at least 2 components for LS.
358 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
359 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 3 : 1;
361 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
362 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, va
>> 40);
364 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
365 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
366 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt
) |
367 S_00B528_DX10_CLAMP(1) |
368 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
369 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(SI_LS_NUM_USER_SGPR
) |
370 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
373 static void si_shader_hs(struct si_shader
*shader
)
375 struct si_pm4_state
*pm4
;
378 pm4
= si_get_shader_pm4_state(shader
);
382 va
= shader
->bo
->gpu_address
;
383 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
385 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
386 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, va
>> 40);
387 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
388 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
389 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
390 S_00B428_DX10_CLAMP(1) |
391 S_00B428_FLOAT_MODE(shader
->config
.float_mode
));
392 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
393 S_00B42C_USER_SGPR(SI_TCS_NUM_USER_SGPR
) |
394 S_00B42C_OC_LDS_EN(1) |
395 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
398 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
400 struct si_pm4_state
*pm4
;
401 unsigned num_user_sgprs
;
402 unsigned vgpr_comp_cnt
;
406 pm4
= si_get_shader_pm4_state(shader
);
410 va
= shader
->bo
->gpu_address
;
411 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
413 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
414 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 3 : 0;
415 num_user_sgprs
= SI_ES_NUM_USER_SGPR
;
416 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
417 vgpr_comp_cnt
= 3; /* all components are needed for TES */
418 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
420 unreachable("invalid shader selector type");
422 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
424 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
425 shader
->selector
->esgs_itemsize
/ 4);
426 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
427 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
428 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
429 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
430 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
431 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
432 S_00B328_DX10_CLAMP(1) |
433 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
434 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
435 S_00B32C_USER_SGPR(num_user_sgprs
) |
436 S_00B32C_OC_LDS_EN(oc_lds_en
) |
437 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
439 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
440 si_set_tesseval_regs(sscreen
, shader
, pm4
);
444 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
447 static uint32_t si_vgt_gs_mode(struct si_shader_selector
*sel
)
449 unsigned gs_max_vert_out
= sel
->gs_max_out_vertices
;
452 if (gs_max_vert_out
<= 128) {
453 cut_mode
= V_028A40_GS_CUT_128
;
454 } else if (gs_max_vert_out
<= 256) {
455 cut_mode
= V_028A40_GS_CUT_256
;
456 } else if (gs_max_vert_out
<= 512) {
457 cut_mode
= V_028A40_GS_CUT_512
;
459 assert(gs_max_vert_out
<= 1024);
460 cut_mode
= V_028A40_GS_CUT_1024
;
463 return S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
464 S_028A40_CUT_MODE(cut_mode
)|
465 S_028A40_ES_WRITE_OPTIMIZE(1) |
466 S_028A40_GS_WRITE_OPTIMIZE(1);
469 static void si_shader_gs(struct si_shader
*shader
)
471 unsigned gs_vert_itemsize
= shader
->selector
->gsvs_vertex_size
;
472 unsigned gsvs_itemsize
= shader
->selector
->max_gsvs_emit_size
>> 2;
473 unsigned gs_num_invocations
= shader
->selector
->gs_num_invocations
;
474 struct si_pm4_state
*pm4
;
476 unsigned max_stream
= shader
->selector
->max_gs_stream
;
478 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
479 assert(gsvs_itemsize
< (1 << 15));
481 pm4
= si_get_shader_pm4_state(shader
);
485 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, si_vgt_gs_mode(shader
->selector
));
487 si_pm4_set_reg(pm4
, R_028A60_VGT_GSVS_RING_OFFSET_1
, gsvs_itemsize
);
488 si_pm4_set_reg(pm4
, R_028A64_VGT_GSVS_RING_OFFSET_2
, gsvs_itemsize
* ((max_stream
>= 2) ? 2 : 1));
489 si_pm4_set_reg(pm4
, R_028A68_VGT_GSVS_RING_OFFSET_3
, gsvs_itemsize
* ((max_stream
>= 3) ? 3 : 1));
491 si_pm4_set_reg(pm4
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, gsvs_itemsize
* (max_stream
+ 1));
493 si_pm4_set_reg(pm4
, R_028B38_VGT_GS_MAX_VERT_OUT
, shader
->selector
->gs_max_out_vertices
);
495 si_pm4_set_reg(pm4
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, gs_vert_itemsize
>> 2);
496 si_pm4_set_reg(pm4
, R_028B60_VGT_GS_VERT_ITEMSIZE_1
, (max_stream
>= 1) ? gs_vert_itemsize
>> 2 : 0);
497 si_pm4_set_reg(pm4
, R_028B64_VGT_GS_VERT_ITEMSIZE_2
, (max_stream
>= 2) ? gs_vert_itemsize
>> 2 : 0);
498 si_pm4_set_reg(pm4
, R_028B68_VGT_GS_VERT_ITEMSIZE_3
, (max_stream
>= 3) ? gs_vert_itemsize
>> 2 : 0);
500 si_pm4_set_reg(pm4
, R_028B90_VGT_GS_INSTANCE_CNT
,
501 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
502 S_028B90_ENABLE(gs_num_invocations
> 0));
504 va
= shader
->bo
->gpu_address
;
505 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
506 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
507 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, va
>> 40);
509 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
510 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
511 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
512 S_00B228_DX10_CLAMP(1) |
513 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
514 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
515 S_00B22C_USER_SGPR(SI_GS_NUM_USER_SGPR
) |
516 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
520 * Compute the state for \p shader, which will run as a vertex shader on the
523 * If \p gs is non-NULL, it points to the geometry shader for which this shader
524 * is the copy shader.
526 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
527 struct si_shader_selector
*gs
)
529 struct si_pm4_state
*pm4
;
530 unsigned num_user_sgprs
;
531 unsigned nparams
, vgpr_comp_cnt
;
534 unsigned window_space
=
535 shader
->selector
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
536 bool enable_prim_id
= si_vs_exports_prim_id(shader
);
538 pm4
= si_get_shader_pm4_state(shader
);
542 /* We always write VGT_GS_MODE in the VS state, because every switch
543 * between different shader pipelines involving a different GS or no
544 * GS at all involves a switch of the VS (different GS use different
545 * copy shaders). On the other hand, when the API switches from a GS to
546 * no GS and then back to the same GS used originally, the GS state is
550 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
,
551 S_028A40_MODE(enable_prim_id
? V_028A40_GS_SCENARIO_A
: 0));
552 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, enable_prim_id
);
554 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, si_vgt_gs_mode(gs
));
555 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
558 va
= shader
->bo
->gpu_address
;
559 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
562 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
563 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
564 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
565 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 3 : (enable_prim_id
? 2 : 0);
566 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
567 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
568 vgpr_comp_cnt
= 3; /* all components are needed for TES */
569 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
571 unreachable("invalid shader selector type");
573 /* VS is required to export at least one param. */
574 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
575 si_pm4_set_reg(pm4
, R_0286C4_SPI_VS_OUT_CONFIG
,
576 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
578 si_pm4_set_reg(pm4
, R_02870C_SPI_SHADER_POS_FORMAT
,
579 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
580 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
581 V_02870C_SPI_SHADER_4COMP
:
582 V_02870C_SPI_SHADER_NONE
) |
583 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
584 V_02870C_SPI_SHADER_4COMP
:
585 V_02870C_SPI_SHADER_NONE
) |
586 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
587 V_02870C_SPI_SHADER_4COMP
:
588 V_02870C_SPI_SHADER_NONE
));
590 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
592 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
593 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, va
>> 40);
594 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
595 S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
596 S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
597 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
598 S_00B128_DX10_CLAMP(1) |
599 S_00B128_FLOAT_MODE(shader
->config
.float_mode
));
600 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
601 S_00B12C_USER_SGPR(num_user_sgprs
) |
602 S_00B12C_OC_LDS_EN(oc_lds_en
) |
603 S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
604 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
605 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
606 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
607 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
) |
608 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
610 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
611 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
613 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
614 S_028818_VTX_W0_FMT(1) |
615 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
616 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
617 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
619 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
620 si_set_tesseval_regs(sscreen
, shader
, pm4
);
623 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
625 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
626 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
627 !!(info
->colors_read
& 0xf0);
628 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
629 (ps
->key
.ps
.prolog
.color_two_side
? num_colors
: 0);
631 assert(num_interp
<= 32);
632 return MIN2(num_interp
, 32);
635 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
637 unsigned value
= shader
->key
.ps
.epilog
.spi_shader_col_format
;
638 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
640 /* If the i-th target format is set, all previous target formats must
641 * be non-zero to avoid hangs.
643 for (i
= 0; i
< num_targets
; i
++)
644 if (!(value
& (0xf << (i
* 4))))
645 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
650 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format
)
652 unsigned i
, cb_shader_mask
= 0;
654 for (i
= 0; i
< 8; i
++) {
655 switch ((spi_shader_col_format
>> (i
* 4)) & 0xf) {
656 case V_028714_SPI_SHADER_ZERO
:
658 case V_028714_SPI_SHADER_32_R
:
659 cb_shader_mask
|= 0x1 << (i
* 4);
661 case V_028714_SPI_SHADER_32_GR
:
662 cb_shader_mask
|= 0x3 << (i
* 4);
664 case V_028714_SPI_SHADER_32_AR
:
665 cb_shader_mask
|= 0x9 << (i
* 4);
667 case V_028714_SPI_SHADER_FP16_ABGR
:
668 case V_028714_SPI_SHADER_UNORM16_ABGR
:
669 case V_028714_SPI_SHADER_SNORM16_ABGR
:
670 case V_028714_SPI_SHADER_UINT16_ABGR
:
671 case V_028714_SPI_SHADER_SINT16_ABGR
:
672 case V_028714_SPI_SHADER_32_ABGR
:
673 cb_shader_mask
|= 0xf << (i
* 4);
679 return cb_shader_mask
;
682 static void si_shader_ps(struct si_shader
*shader
)
684 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
685 struct si_pm4_state
*pm4
;
686 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
687 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
689 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
691 /* we need to enable at least one of them, otherwise we hang the GPU */
692 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
693 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
694 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
695 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
696 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
697 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
698 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
699 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
700 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
701 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
702 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
703 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
704 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
705 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
707 /* Validate interpolation optimization flags (read as implications). */
708 assert(!shader
->key
.ps
.prolog
.bc_optimize_for_persp
||
709 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
710 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
711 assert(!shader
->key
.ps
.prolog
.bc_optimize_for_linear
||
712 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
713 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
714 assert(!shader
->key
.ps
.prolog
.force_persp_center_interp
||
715 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
716 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
717 assert(!shader
->key
.ps
.prolog
.force_linear_center_interp
||
718 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
719 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
720 assert(!shader
->key
.ps
.prolog
.force_persp_sample_interp
||
721 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
722 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
723 assert(!shader
->key
.ps
.prolog
.force_linear_sample_interp
||
724 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
725 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
727 /* Validate cases when the optimizations are off (read as implications). */
728 assert(shader
->key
.ps
.prolog
.bc_optimize_for_persp
||
729 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
730 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
731 assert(shader
->key
.ps
.prolog
.bc_optimize_for_linear
||
732 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
733 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
735 pm4
= si_get_shader_pm4_state(shader
);
739 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
741 * 0 -> Position = pixel center
742 * 1 -> Position = pixel centroid
743 * 2 -> Position = at sample position
745 * From GLSL 4.5 specification, section 7.1:
746 * "The variable gl_FragCoord is available as an input variable from
747 * within fragment shaders and it holds the window relative coordinates
748 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
749 * value can be for any location within the pixel, or one of the
750 * fragment samples. The use of centroid does not further restrict
751 * this value to be inside the current primitive."
753 * Meaning that centroid has no effect and we can return anything within
754 * the pixel. Thus, return the value at sample position, because that's
755 * the most accurate one shaders can get.
757 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
759 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
760 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
761 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
763 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
764 cb_shader_mask
= si_get_cb_shader_mask(spi_shader_col_format
);
766 /* Ensure that some export memory is always allocated, for two reasons:
768 * 1) Correctness: The hardware ignores the EXEC mask if no export
769 * memory is allocated, so KILL and alpha test do not work correctly
771 * 2) Performance: Every shader needs at least a NULL export, even when
772 * it writes no color/depth output. The NULL export instruction
773 * stalls without this setting.
775 * Don't add this to CB_SHADER_MASK.
777 if (!spi_shader_col_format
&&
778 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
779 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
781 si_pm4_set_reg(pm4
, R_0286CC_SPI_PS_INPUT_ENA
, input_ena
);
782 si_pm4_set_reg(pm4
, R_0286D0_SPI_PS_INPUT_ADDR
,
783 shader
->config
.spi_ps_input_addr
);
785 /* Set interpolation controls. */
786 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
));
789 si_pm4_set_reg(pm4
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
790 si_pm4_set_reg(pm4
, R_0286D8_SPI_PS_IN_CONTROL
, spi_ps_in_control
);
792 si_pm4_set_reg(pm4
, R_028710_SPI_SHADER_Z_FORMAT
,
793 si_get_spi_shader_z_format(info
->writes_z
,
794 info
->writes_stencil
,
795 info
->writes_samplemask
));
797 si_pm4_set_reg(pm4
, R_028714_SPI_SHADER_COL_FORMAT
, spi_shader_col_format
);
798 si_pm4_set_reg(pm4
, R_02823C_CB_SHADER_MASK
, cb_shader_mask
);
800 va
= shader
->bo
->gpu_address
;
801 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
802 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
803 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, va
>> 40);
805 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
,
806 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
807 S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
808 S_00B028_DX10_CLAMP(1) |
809 S_00B028_FLOAT_MODE(shader
->config
.float_mode
));
810 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
811 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
812 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
813 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
816 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
817 struct si_shader
*shader
)
819 switch (shader
->selector
->type
) {
820 case PIPE_SHADER_VERTEX
:
821 if (shader
->key
.vs
.as_ls
)
822 si_shader_ls(shader
);
823 else if (shader
->key
.vs
.as_es
)
824 si_shader_es(sscreen
, shader
);
826 si_shader_vs(sscreen
, shader
, NULL
);
828 case PIPE_SHADER_TESS_CTRL
:
829 si_shader_hs(shader
);
831 case PIPE_SHADER_TESS_EVAL
:
832 if (shader
->key
.tes
.as_es
)
833 si_shader_es(sscreen
, shader
);
835 si_shader_vs(sscreen
, shader
, NULL
);
837 case PIPE_SHADER_GEOMETRY
:
838 si_shader_gs(shader
);
840 case PIPE_SHADER_FRAGMENT
:
841 si_shader_ps(shader
);
848 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
850 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
851 if (sctx
->queued
.named
.dsa
)
852 return sctx
->queued
.named
.dsa
->alpha_func
;
854 return PIPE_FUNC_ALWAYS
;
857 /* Compute the key for the hw shader variant */
858 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
859 struct si_shader_selector
*sel
,
860 union si_shader_key
*key
)
862 struct si_context
*sctx
= (struct si_context
*)ctx
;
865 memset(key
, 0, sizeof(*key
));
868 case PIPE_SHADER_VERTEX
:
869 if (sctx
->vertex_elements
) {
870 unsigned count
= MIN2(sel
->info
.num_inputs
,
871 sctx
->vertex_elements
->count
);
872 for (i
= 0; i
< count
; ++i
)
873 key
->vs
.prolog
.instance_divisors
[i
] =
874 sctx
->vertex_elements
->elements
[i
].instance_divisor
;
876 if (sctx
->tes_shader
.cso
)
878 else if (sctx
->gs_shader
.cso
)
881 if (!sctx
->gs_shader
.cso
&& sctx
->ps_shader
.cso
&&
882 sctx
->ps_shader
.cso
->info
.uses_primid
)
883 key
->vs
.epilog
.export_prim_id
= 1;
885 case PIPE_SHADER_TESS_CTRL
:
886 key
->tcs
.epilog
.prim_mode
=
887 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
889 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
890 key
->tcs
.epilog
.inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
892 case PIPE_SHADER_TESS_EVAL
:
893 if (sctx
->gs_shader
.cso
)
895 else if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
896 key
->tes
.epilog
.export_prim_id
= 1;
898 case PIPE_SHADER_GEOMETRY
:
900 case PIPE_SHADER_FRAGMENT
: {
901 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
902 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
904 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
905 sel
->info
.colors_written
== 0x1)
906 key
->ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
909 /* Select the shader color format based on whether
910 * blending or alpha are needed.
912 key
->ps
.epilog
.spi_shader_col_format
=
913 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
914 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
915 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
916 sctx
->framebuffer
.spi_shader_col_format_blend
) |
917 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
918 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
919 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
920 sctx
->framebuffer
.spi_shader_col_format
);
922 /* The output for dual source blending should have
923 * the same format as the first output.
925 if (blend
->dual_src_blend
)
926 key
->ps
.epilog
.spi_shader_col_format
|=
927 (key
->ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
929 key
->ps
.epilog
.spi_shader_col_format
= sctx
->framebuffer
.spi_shader_col_format
;
931 /* If alpha-to-coverage is enabled, we have to export alpha
932 * even if there is no color buffer.
934 if (!(key
->ps
.epilog
.spi_shader_col_format
& 0xf) &&
935 blend
&& blend
->alpha_to_coverage
)
936 key
->ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
938 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
939 * to the range supported by the type if a channel has less
940 * than 16 bits and the export format is 16_ABGR.
942 if (sctx
->b
.chip_class
<= CIK
&& sctx
->b
.family
!= CHIP_HAWAII
)
943 key
->ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
945 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
946 if (!key
->ps
.epilog
.last_cbuf
) {
947 key
->ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
948 key
->ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
952 bool is_poly
= (sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES
&&
953 sctx
->current_rast_prim
<= PIPE_PRIM_POLYGON
) ||
954 sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES_ADJACENCY
;
955 bool is_line
= !is_poly
&& sctx
->current_rast_prim
!= PIPE_PRIM_POINTS
;
957 key
->ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
958 key
->ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
960 if (sctx
->queued
.named
.blend
) {
961 key
->ps
.epilog
.alpha_to_one
= sctx
->queued
.named
.blend
->alpha_to_one
&&
962 rs
->multisample_enable
;
965 key
->ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
966 key
->ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
967 (is_line
&& rs
->line_smooth
)) &&
968 sctx
->framebuffer
.nr_samples
<= 1;
969 key
->ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
971 if (rs
->force_persample_interp
&&
972 rs
->multisample_enable
&&
973 sctx
->framebuffer
.nr_samples
> 1 &&
974 sctx
->ps_iter_samples
> 1) {
975 key
->ps
.prolog
.force_persp_sample_interp
=
976 sel
->info
.uses_persp_center
||
977 sel
->info
.uses_persp_centroid
;
979 key
->ps
.prolog
.force_linear_sample_interp
=
980 sel
->info
.uses_linear_center
||
981 sel
->info
.uses_linear_centroid
;
982 } else if (rs
->multisample_enable
&&
983 sctx
->framebuffer
.nr_samples
> 1) {
984 key
->ps
.prolog
.bc_optimize_for_persp
=
985 sel
->info
.uses_persp_center
&&
986 sel
->info
.uses_persp_centroid
;
987 key
->ps
.prolog
.bc_optimize_for_linear
=
988 sel
->info
.uses_linear_center
&&
989 sel
->info
.uses_linear_centroid
;
991 /* Make sure SPI doesn't compute more than 1 pair
992 * of (i,j), which is the optimization here. */
993 key
->ps
.prolog
.force_persp_center_interp
=
994 sel
->info
.uses_persp_center
+
995 sel
->info
.uses_persp_centroid
+
996 sel
->info
.uses_persp_sample
> 1;
998 key
->ps
.prolog
.force_linear_center_interp
=
999 sel
->info
.uses_linear_center
+
1000 sel
->info
.uses_linear_centroid
+
1001 sel
->info
.uses_linear_sample
> 1;
1005 key
->ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
1013 /* Select the hw shader variant depending on the current state. */
1014 static int si_shader_select_with_key(struct si_screen
*sscreen
,
1015 struct si_shader_ctx_state
*state
,
1016 union si_shader_key
*key
,
1017 LLVMTargetMachineRef tm
,
1018 struct pipe_debug_callback
*debug
,
1020 bool is_debug_context
)
1022 struct si_shader_selector
*sel
= state
->cso
;
1023 struct si_shader
*current
= state
->current
;
1024 struct si_shader
*iter
, *shader
= NULL
;
1027 /* Check if we don't need to change anything.
1028 * This path is also used for most shaders that don't need multiple
1029 * variants, it will cost just a computation of the key and this
1031 if (likely(current
&& memcmp(¤t
->key
, key
, sizeof(*key
)) == 0))
1034 /* This must be done before the mutex is locked, because async GS
1035 * compilation calls this function too, and therefore must enter
1039 util_queue_job_wait(&sel
->ready
);
1041 pipe_mutex_lock(sel
->mutex
);
1043 /* Find the shader variant. */
1044 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
1045 /* Don't check the "current" shader. We checked it above. */
1046 if (current
!= iter
&&
1047 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
1048 state
->current
= iter
;
1049 pipe_mutex_unlock(sel
->mutex
);
1054 /* Build a new shader. */
1055 shader
= CALLOC_STRUCT(si_shader
);
1057 pipe_mutex_unlock(sel
->mutex
);
1060 shader
->selector
= sel
;
1063 r
= si_shader_create(sscreen
, tm
, shader
, debug
);
1065 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1068 pipe_mutex_unlock(sel
->mutex
);
1072 if (is_debug_context
) {
1073 FILE *f
= open_memstream(&shader
->shader_log
,
1074 &shader
->shader_log_size
);
1076 si_shader_dump(sscreen
, shader
, NULL
, sel
->type
, f
);
1081 si_shader_init_pm4_state(sscreen
, shader
);
1083 if (!sel
->last_variant
) {
1084 sel
->first_variant
= shader
;
1085 sel
->last_variant
= shader
;
1087 sel
->last_variant
->next_variant
= shader
;
1088 sel
->last_variant
= shader
;
1090 state
->current
= shader
;
1091 pipe_mutex_unlock(sel
->mutex
);
1095 static int si_shader_select(struct pipe_context
*ctx
,
1096 struct si_shader_ctx_state
*state
)
1098 struct si_context
*sctx
= (struct si_context
*)ctx
;
1099 union si_shader_key key
;
1101 si_shader_selector_key(ctx
, state
->cso
, &key
);
1102 return si_shader_select_with_key(sctx
->screen
, state
, &key
,
1103 sctx
->tm
, &sctx
->b
.debug
, true,
1107 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
1108 union si_shader_key
*key
)
1110 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
1112 switch (info
->processor
) {
1113 case PIPE_SHADER_VERTEX
:
1114 switch (next_shader
) {
1115 case PIPE_SHADER_GEOMETRY
:
1118 case PIPE_SHADER_TESS_CTRL
:
1119 case PIPE_SHADER_TESS_EVAL
:
1125 case PIPE_SHADER_TESS_EVAL
:
1126 if (next_shader
== PIPE_SHADER_GEOMETRY
)
1133 * Compile the main shader part or the monolithic shader as part of
1134 * si_shader_selector initialization. Since it can be done asynchronously,
1135 * there is no way to report compile failures to applications.
1137 void si_init_shader_selector_async(void *job
, int thread_index
)
1139 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
1140 struct si_screen
*sscreen
= sel
->screen
;
1141 LLVMTargetMachineRef tm
;
1142 struct pipe_debug_callback
*debug
= &sel
->debug
;
1145 if (thread_index
>= 0) {
1146 assert(thread_index
< ARRAY_SIZE(sscreen
->tm
));
1147 tm
= sscreen
->tm
[thread_index
];
1154 /* Compile the main shader part for use with a prolog and/or epilog.
1155 * If this fails, the driver will try to compile a monolithic shader
1158 if (sel
->type
!= PIPE_SHADER_GEOMETRY
&&
1159 !sscreen
->use_monolithic_shaders
) {
1160 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
1164 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
1168 shader
->selector
= sel
;
1169 si_parse_next_shader_property(&sel
->info
, &shader
->key
);
1171 tgsi_binary
= si_get_tgsi_binary(sel
);
1173 /* Try to load the shader from the shader cache. */
1174 pipe_mutex_lock(sscreen
->shader_cache_mutex
);
1177 si_shader_cache_load_shader(sscreen
, tgsi_binary
, shader
)) {
1179 pipe_mutex_unlock(sscreen
->shader_cache_mutex
);
1181 pipe_mutex_unlock(sscreen
->shader_cache_mutex
);
1183 /* Compile the shader if it hasn't been loaded from the cache. */
1184 if (si_compile_tgsi_shader(sscreen
, tm
, shader
, false,
1188 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
1193 pipe_mutex_lock(sscreen
->shader_cache_mutex
);
1194 if (!si_shader_cache_insert_shader(sscreen
, tgsi_binary
, shader
))
1196 pipe_mutex_unlock(sscreen
->shader_cache_mutex
);
1200 sel
->main_shader_part
= shader
;
1203 /* Pre-compilation. */
1204 if (sel
->type
== PIPE_SHADER_GEOMETRY
||
1205 sscreen
->b
.debug_flags
& DBG_PRECOMPILE
) {
1206 struct si_shader_ctx_state state
= {sel
};
1207 union si_shader_key key
;
1209 memset(&key
, 0, sizeof(key
));
1210 si_parse_next_shader_property(&sel
->info
, &key
);
1212 /* Set reasonable defaults, so that the shader key doesn't
1213 * cause any code to be eliminated.
1215 switch (sel
->type
) {
1216 case PIPE_SHADER_TESS_CTRL
:
1217 key
.tcs
.epilog
.prim_mode
= PIPE_PRIM_TRIANGLES
;
1219 case PIPE_SHADER_FRAGMENT
:
1220 key
.ps
.prolog
.bc_optimize_for_persp
=
1221 sel
->info
.uses_persp_center
&&
1222 sel
->info
.uses_persp_centroid
;
1223 key
.ps
.prolog
.bc_optimize_for_linear
=
1224 sel
->info
.uses_linear_center
&&
1225 sel
->info
.uses_linear_centroid
;
1226 key
.ps
.epilog
.alpha_func
= PIPE_FUNC_ALWAYS
;
1227 for (i
= 0; i
< 8; i
++)
1228 if (sel
->info
.colors_written
& (1 << i
))
1229 key
.ps
.epilog
.spi_shader_col_format
|=
1230 V_028710_SPI_SHADER_FP16_ABGR
<< (i
* 4);
1234 if (si_shader_select_with_key(sscreen
, &state
, &key
, tm
, debug
,
1235 false, sel
->is_debug_context
))
1236 fprintf(stderr
, "radeonsi: can't create a monolithic shader\n");
1239 /* The GS copy shader is always pre-compiled. */
1240 if (sel
->type
== PIPE_SHADER_GEOMETRY
) {
1241 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, tm
, sel
, debug
);
1242 if (!sel
->gs_copy_shader
) {
1243 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
1247 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
1251 static void *si_create_shader_selector(struct pipe_context
*ctx
,
1252 const struct pipe_shader_state
*state
)
1254 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
1255 struct si_context
*sctx
= (struct si_context
*)ctx
;
1256 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
1262 sel
->screen
= sscreen
;
1264 sel
->debug
= sctx
->b
.debug
;
1265 sel
->is_debug_context
= sctx
->is_debug
;
1266 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
1272 sel
->so
= state
->stream_output
;
1273 tgsi_scan_shader(state
->tokens
, &sel
->info
);
1274 sel
->type
= sel
->info
.processor
;
1275 p_atomic_inc(&sscreen
->b
.num_shaders_created
);
1277 /* Set which opcode uses which (i,j) pair. */
1278 if (sel
->info
.uses_persp_opcode_interp_centroid
)
1279 sel
->info
.uses_persp_centroid
= true;
1281 if (sel
->info
.uses_linear_opcode_interp_centroid
)
1282 sel
->info
.uses_linear_centroid
= true;
1284 if (sel
->info
.uses_persp_opcode_interp_offset
||
1285 sel
->info
.uses_persp_opcode_interp_sample
)
1286 sel
->info
.uses_persp_center
= true;
1288 if (sel
->info
.uses_linear_opcode_interp_offset
||
1289 sel
->info
.uses_linear_opcode_interp_sample
)
1290 sel
->info
.uses_linear_center
= true;
1292 switch (sel
->type
) {
1293 case PIPE_SHADER_GEOMETRY
:
1294 sel
->gs_output_prim
=
1295 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
1296 sel
->gs_max_out_vertices
=
1297 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
1298 sel
->gs_num_invocations
=
1299 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
1300 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
1301 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
1302 sel
->gs_max_out_vertices
;
1304 sel
->max_gs_stream
= 0;
1305 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
1306 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
1307 sel
->so
.output
[i
].stream
);
1309 sel
->gs_input_verts_per_prim
=
1310 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
1313 case PIPE_SHADER_TESS_CTRL
:
1314 /* Always reserve space for these. */
1315 sel
->patch_outputs_written
|=
1316 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER
, 0)) |
1317 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER
, 0));
1319 case PIPE_SHADER_VERTEX
:
1320 case PIPE_SHADER_TESS_EVAL
:
1321 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
1322 unsigned name
= sel
->info
.output_semantic_name
[i
];
1323 unsigned index
= sel
->info
.output_semantic_index
[i
];
1326 case TGSI_SEMANTIC_TESSINNER
:
1327 case TGSI_SEMANTIC_TESSOUTER
:
1328 case TGSI_SEMANTIC_PATCH
:
1329 sel
->patch_outputs_written
|=
1330 1llu << si_shader_io_get_unique_index(name
, index
);
1333 sel
->outputs_written
|=
1334 1llu << si_shader_io_get_unique_index(name
, index
);
1337 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
1340 case PIPE_SHADER_FRAGMENT
:
1341 for (i
= 0; i
< 8; i
++)
1342 if (sel
->info
.colors_written
& (1 << i
))
1343 sel
->colors_written_4bit
|= 0xf << (4 * i
);
1345 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
1346 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
1347 int index
= sel
->info
.input_semantic_index
[i
];
1348 sel
->color_attr_index
[index
] = i
;
1354 /* DB_SHADER_CONTROL */
1355 sel
->db_shader_control
=
1356 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
1357 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
1358 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
1359 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
1361 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
1362 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
1363 sel
->db_shader_control
|=
1364 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
1366 case TGSI_FS_DEPTH_LAYOUT_LESS
:
1367 sel
->db_shader_control
|=
1368 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
1372 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
1374 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
1375 * --|-----------|------------|------------|--------------------|-------------------|-------------
1376 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
1377 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
1378 * 2 | false | true | n/a | LateZ | 1 | 0
1379 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
1380 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
1382 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
1383 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
1385 * Don't use ReZ without profiling !!!
1387 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
1390 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
1392 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
1393 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
1394 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
1395 } else if (sel
->info
.writes_memory
) {
1397 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) |
1398 S_02880C_EXEC_ON_HIER_FAIL(1);
1401 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
1404 pipe_mutex_init(sel
->mutex
);
1405 util_queue_fence_init(&sel
->ready
);
1407 if ((sctx
->b
.debug
.debug_message
&& !sctx
->b
.debug
.async
) ||
1409 r600_can_dump_shader(&sscreen
->b
, sel
->info
.processor
) ||
1410 !util_queue_is_initialized(&sscreen
->shader_compiler_queue
))
1411 si_init_shader_selector_async(sel
, -1);
1413 util_queue_add_job(&sscreen
->shader_compiler_queue
, sel
,
1414 &sel
->ready
, si_init_shader_selector_async
,
1420 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
1422 struct si_context
*sctx
= (struct si_context
*)ctx
;
1423 struct si_shader_selector
*sel
= state
;
1425 if (sctx
->vs_shader
.cso
== sel
)
1428 sctx
->vs_shader
.cso
= sel
;
1429 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
1430 sctx
->do_update_shaders
= true;
1431 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
1432 r600_update_vs_writes_viewport_index(&sctx
->b
, si_get_vs_info(sctx
));
1435 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
1437 struct si_context
*sctx
= (struct si_context
*)ctx
;
1438 struct si_shader_selector
*sel
= state
;
1439 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
1441 if (sctx
->gs_shader
.cso
== sel
)
1444 sctx
->gs_shader
.cso
= sel
;
1445 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
1446 sctx
->do_update_shaders
= true;
1447 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
1448 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
1451 si_shader_change_notify(sctx
);
1452 r600_update_vs_writes_viewport_index(&sctx
->b
, si_get_vs_info(sctx
));
1455 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
1457 struct si_context
*sctx
= (struct si_context
*)ctx
;
1458 struct si_shader_selector
*sel
= state
;
1459 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
1461 if (sctx
->tcs_shader
.cso
== sel
)
1464 sctx
->tcs_shader
.cso
= sel
;
1465 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
1466 sctx
->do_update_shaders
= true;
1469 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
1472 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
1474 struct si_context
*sctx
= (struct si_context
*)ctx
;
1475 struct si_shader_selector
*sel
= state
;
1476 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
1478 if (sctx
->tes_shader
.cso
== sel
)
1481 sctx
->tes_shader
.cso
= sel
;
1482 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
1483 sctx
->do_update_shaders
= true;
1484 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
1485 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
1487 if (enable_changed
) {
1488 si_shader_change_notify(sctx
);
1489 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
1491 r600_update_vs_writes_viewport_index(&sctx
->b
, si_get_vs_info(sctx
));
1494 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
1496 struct si_context
*sctx
= (struct si_context
*)ctx
;
1497 struct si_shader_selector
*sel
= state
;
1499 /* skip if supplied shader is one already in use */
1500 if (sctx
->ps_shader
.cso
== sel
)
1503 sctx
->ps_shader
.cso
= sel
;
1504 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
1505 sctx
->do_update_shaders
= true;
1506 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
1509 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
1512 switch (shader
->selector
->type
) {
1513 case PIPE_SHADER_VERTEX
:
1514 if (shader
->key
.vs
.as_ls
)
1515 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
1516 else if (shader
->key
.vs
.as_es
)
1517 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
1519 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
1521 case PIPE_SHADER_TESS_CTRL
:
1522 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
1524 case PIPE_SHADER_TESS_EVAL
:
1525 if (shader
->key
.tes
.as_es
)
1526 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
1528 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
1530 case PIPE_SHADER_GEOMETRY
:
1531 if (shader
->is_gs_copy_shader
)
1532 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
1534 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
1536 case PIPE_SHADER_FRAGMENT
:
1537 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
1542 si_shader_destroy(shader
);
1546 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
1548 struct si_context
*sctx
= (struct si_context
*)ctx
;
1549 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
1550 struct si_shader
*p
= sel
->first_variant
, *c
;
1551 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
1552 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
1553 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
1554 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
1555 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
1556 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
1559 util_queue_job_wait(&sel
->ready
);
1561 if (current_shader
[sel
->type
]->cso
== sel
) {
1562 current_shader
[sel
->type
]->cso
= NULL
;
1563 current_shader
[sel
->type
]->current
= NULL
;
1567 c
= p
->next_variant
;
1568 si_delete_shader(sctx
, p
);
1572 if (sel
->main_shader_part
)
1573 si_delete_shader(sctx
, sel
->main_shader_part
);
1574 if (sel
->gs_copy_shader
)
1575 si_delete_shader(sctx
, sel
->gs_copy_shader
);
1577 util_queue_fence_destroy(&sel
->ready
);
1578 pipe_mutex_destroy(sel
->mutex
);
1583 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
1584 struct si_shader
*vs
, unsigned name
,
1585 unsigned index
, unsigned interpolate
)
1587 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
1588 unsigned j
, offset
, ps_input_cntl
= 0;
1590 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
1591 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
))
1592 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
1594 if (name
== TGSI_SEMANTIC_PCOORD
||
1595 (name
== TGSI_SEMANTIC_TEXCOORD
&&
1596 sctx
->sprite_coord_enable
& (1 << index
))) {
1597 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
1600 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
1601 if (name
== vsinfo
->output_semantic_name
[j
] &&
1602 index
== vsinfo
->output_semantic_index
[j
]) {
1603 offset
= vs
->info
.vs_output_param_offset
[j
];
1605 if (offset
<= EXP_PARAM_OFFSET_31
) {
1606 /* The input is loaded from parameter memory. */
1607 ps_input_cntl
|= S_028644_OFFSET(offset
);
1608 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
1609 /* The input is a DEFAULT_VAL constant. */
1610 assert(offset
>= EXP_PARAM_DEFAULT_VAL_0000
&&
1611 offset
<= EXP_PARAM_DEFAULT_VAL_1111
);
1613 offset
-= EXP_PARAM_DEFAULT_VAL_0000
;
1614 ps_input_cntl
= S_028644_OFFSET(0x20) |
1615 S_028644_DEFAULT_VAL(offset
);
1621 if (name
== TGSI_SEMANTIC_PRIMID
)
1622 /* PrimID is written after the last output. */
1623 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
1624 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
1625 /* No corresponding output found, load defaults into input.
1626 * Don't set any other bits.
1627 * (FLAT_SHADE=1 completely changes behavior) */
1628 ps_input_cntl
= S_028644_OFFSET(0x20);
1629 /* D3D 9 behaviour. GL is undefined */
1630 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
1631 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
1633 return ps_input_cntl
;
1636 static void si_emit_spi_map(struct si_context
*sctx
, struct r600_atom
*atom
)
1638 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1639 struct si_shader
*ps
= sctx
->ps_shader
.current
;
1640 struct si_shader
*vs
= si_get_vs_state(sctx
);
1641 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
1642 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
1644 if (!ps
|| !ps
->selector
->info
.num_inputs
)
1647 num_interp
= si_get_ps_num_interp(ps
);
1648 assert(num_interp
> 0);
1649 radeon_set_context_reg_seq(cs
, R_028644_SPI_PS_INPUT_CNTL_0
, num_interp
);
1651 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
1652 unsigned name
= psinfo
->input_semantic_name
[i
];
1653 unsigned index
= psinfo
->input_semantic_index
[i
];
1654 unsigned interpolate
= psinfo
->input_interpolate
[i
];
1656 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, name
, index
,
1660 if (name
== TGSI_SEMANTIC_COLOR
) {
1661 assert(index
< ARRAY_SIZE(bcol_interp
));
1662 bcol_interp
[index
] = interpolate
;
1666 if (ps
->key
.ps
.prolog
.color_two_side
) {
1667 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
1669 for (i
= 0; i
< 2; i
++) {
1670 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
1673 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, bcol
,
1674 i
, bcol_interp
[i
]));
1678 assert(num_interp
== num_written
);
1682 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
1684 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
1686 if (sctx
->init_config_has_vgt_flush
)
1689 /* Done by Vulkan before VGT_FLUSH. */
1690 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
1691 si_pm4_cmd_add(sctx
->init_config
,
1692 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1693 si_pm4_cmd_end(sctx
->init_config
, false);
1695 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
1696 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
1697 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
1698 si_pm4_cmd_end(sctx
->init_config
, false);
1699 sctx
->init_config_has_vgt_flush
= true;
1702 /* Initialize state related to ESGS / GSVS ring buffers */
1703 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
1705 struct si_shader_selector
*es
=
1706 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
1707 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
1708 struct si_pm4_state
*pm4
;
1710 /* Chip constants. */
1711 unsigned num_se
= sctx
->screen
->b
.info
.max_se
;
1712 unsigned wave_size
= 64;
1713 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1714 unsigned gs_vertex_reuse
= 16 * num_se
; /* GS_VERTEX_REUSE register (per SE) */
1715 unsigned alignment
= 256 * num_se
;
1716 /* The maximum size is 63.999 MB per SE. */
1717 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1719 /* Calculate the minimum size. */
1720 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
1721 wave_size
, alignment
);
1723 /* These are recommended sizes, not minimum sizes. */
1724 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1725 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
1726 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1727 gs
->max_gsvs_emit_size
* (gs
->max_gs_stream
+ 1);
1729 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1730 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1731 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1733 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1734 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1736 /* Some rings don't have to be allocated if shaders don't use them.
1737 * (e.g. no varyings between ES and GS or GS and VS)
1739 bool update_esgs
= esgs_ring_size
&&
1740 (!sctx
->esgs_ring
||
1741 sctx
->esgs_ring
->width0
< esgs_ring_size
);
1742 bool update_gsvs
= gsvs_ring_size
&&
1743 (!sctx
->gsvs_ring
||
1744 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
1746 if (!update_esgs
&& !update_gsvs
)
1750 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
1751 sctx
->esgs_ring
= pipe_buffer_create(sctx
->b
.b
.screen
, 0,
1754 if (!sctx
->esgs_ring
)
1759 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
1760 sctx
->gsvs_ring
= pipe_buffer_create(sctx
->b
.b
.screen
, 0,
1763 if (!sctx
->gsvs_ring
)
1767 /* Create the "init_config_gs_rings" state. */
1768 pm4
= CALLOC_STRUCT(si_pm4_state
);
1772 if (sctx
->b
.chip_class
>= CIK
) {
1773 if (sctx
->esgs_ring
)
1774 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
1775 sctx
->esgs_ring
->width0
/ 256);
1776 if (sctx
->gsvs_ring
)
1777 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
1778 sctx
->gsvs_ring
->width0
/ 256);
1780 if (sctx
->esgs_ring
)
1781 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
1782 sctx
->esgs_ring
->width0
/ 256);
1783 if (sctx
->gsvs_ring
)
1784 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
1785 sctx
->gsvs_ring
->width0
/ 256);
1788 /* Set the state. */
1789 if (sctx
->init_config_gs_rings
)
1790 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
1791 sctx
->init_config_gs_rings
= pm4
;
1793 if (!sctx
->init_config_has_vgt_flush
) {
1794 si_init_config_add_vgt_flush(sctx
);
1795 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
1798 /* Flush the context to re-emit both init_config states. */
1799 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
1800 si_context_gfx_flush(sctx
, RADEON_FLUSH_ASYNC
, NULL
);
1802 /* Set ring bindings. */
1803 if (sctx
->esgs_ring
) {
1804 si_set_ring_buffer(&sctx
->b
.b
, SI_ES_RING_ESGS
,
1805 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
1806 true, true, 4, 64, 0);
1807 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_ESGS
,
1808 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
1809 false, false, 0, 0, 0);
1811 if (sctx
->gsvs_ring
)
1812 si_set_ring_buffer(&sctx
->b
.b
, SI_VS_RING_GSVS
,
1813 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
1814 false, false, 0, 0, 0);
1818 static void si_update_gsvs_ring_bindings(struct si_context
*sctx
)
1820 unsigned gsvs_itemsize
= sctx
->gs_shader
.cso
->max_gsvs_emit_size
;
1823 if (!sctx
->gsvs_ring
|| gsvs_itemsize
== sctx
->last_gsvs_itemsize
)
1826 sctx
->last_gsvs_itemsize
= gsvs_itemsize
;
1828 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_GSVS0
,
1829 sctx
->gsvs_ring
, gsvs_itemsize
,
1830 64, true, true, 4, 16, 0);
1832 offset
= gsvs_itemsize
* 64;
1833 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_GSVS1
,
1834 sctx
->gsvs_ring
, gsvs_itemsize
,
1835 64, true, true, 4, 16, offset
);
1837 offset
= (gsvs_itemsize
* 2) * 64;
1838 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_GSVS2
,
1839 sctx
->gsvs_ring
, gsvs_itemsize
,
1840 64, true, true, 4, 16, offset
);
1842 offset
= (gsvs_itemsize
* 3) * 64;
1843 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_GSVS3
,
1844 sctx
->gsvs_ring
, gsvs_itemsize
,
1845 64, true, true, 4, 16, offset
);
1849 * @returns 1 if \p sel has been updated to use a new scratch buffer
1851 * < 0 if there was a failure
1853 static int si_update_scratch_buffer(struct si_context
*sctx
,
1854 struct si_shader
*shader
)
1856 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
1862 /* This shader doesn't need a scratch buffer */
1863 if (shader
->config
.scratch_bytes_per_wave
== 0)
1866 /* This shader is already configured to use the current
1867 * scratch buffer. */
1868 if (shader
->scratch_bo
== sctx
->scratch_buffer
)
1871 assert(sctx
->scratch_buffer
);
1873 si_shader_apply_scratch_relocs(sctx
, shader
, &shader
->config
, scratch_va
);
1875 /* Replace the shader bo with a new bo that has the relocs applied. */
1876 r
= si_shader_binary_upload(sctx
->screen
, shader
);
1880 /* Update the shader state to use the new shader bo. */
1881 si_shader_init_pm4_state(sctx
->screen
, shader
);
1883 r600_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
1888 static unsigned si_get_current_scratch_buffer_size(struct si_context
*sctx
)
1890 return sctx
->scratch_buffer
? sctx
->scratch_buffer
->b
.b
.width0
: 0;
1893 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
1895 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
1898 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context
*sctx
)
1902 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
1903 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
1904 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
1905 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tcs_shader
.current
));
1906 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
1910 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
1912 unsigned current_scratch_buffer_size
=
1913 si_get_current_scratch_buffer_size(sctx
);
1914 unsigned scratch_bytes_per_wave
=
1915 si_get_max_scratch_bytes_per_wave(sctx
);
1916 unsigned scratch_needed_size
= scratch_bytes_per_wave
*
1917 sctx
->scratch_waves
;
1918 unsigned spi_tmpring_size
;
1921 if (scratch_needed_size
> 0) {
1922 if (scratch_needed_size
> current_scratch_buffer_size
) {
1923 /* Create a bigger scratch buffer */
1924 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
1926 sctx
->scratch_buffer
= (struct r600_resource
*)
1927 pipe_buffer_create(&sctx
->screen
->b
.b
, 0,
1928 PIPE_USAGE_DEFAULT
, scratch_needed_size
);
1929 if (!sctx
->scratch_buffer
)
1931 sctx
->emit_scratch_reloc
= true;
1934 /* Update the shaders, so they are using the latest scratch. The
1935 * scratch buffer may have been changed since these shaders were
1936 * last used, so we still need to try to update them, even if
1937 * they require scratch buffers smaller than the current size.
1939 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
1943 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
1945 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
1949 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
1951 r
= si_update_scratch_buffer(sctx
, sctx
->tcs_shader
.current
);
1955 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
1957 /* VS can be bound as LS, ES, or VS. */
1958 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
1962 if (sctx
->tes_shader
.current
)
1963 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
1964 else if (sctx
->gs_shader
.current
)
1965 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
1967 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
1970 /* TES can be bound as ES or VS. */
1971 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
1975 if (sctx
->gs_shader
.current
)
1976 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
1978 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
1982 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
1983 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
1984 "scratch size should already be aligned correctly.");
1986 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
1987 S_0286E8_WAVESIZE(scratch_bytes_per_wave
>> 10);
1988 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
1989 sctx
->spi_tmpring_size
= spi_tmpring_size
;
1990 sctx
->emit_scratch_reloc
= true;
1995 static void si_init_tess_factor_ring(struct si_context
*sctx
)
1997 bool double_offchip_buffers
= sctx
->b
.chip_class
>= CIK
;
1998 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
1999 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
2000 sctx
->screen
->b
.info
.max_se
;
2001 unsigned offchip_granularity
;
2003 switch (sctx
->screen
->tess_offchip_block_dw_size
) {
2008 offchip_granularity
= V_03093C_X_8K_DWORDS
;
2011 offchip_granularity
= V_03093C_X_4K_DWORDS
;
2015 switch (sctx
->b
.chip_class
) {
2017 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
2020 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
2024 max_offchip_buffers
= MIN2(max_offchip_buffers
, 512);
2028 assert(!sctx
->tf_ring
);
2029 sctx
->tf_ring
= pipe_buffer_create(sctx
->b
.b
.screen
, 0,
2031 32768 * sctx
->screen
->b
.info
.max_se
);
2035 assert(((sctx
->tf_ring
->width0
/ 4) & C_030938_SIZE
) == 0);
2037 sctx
->tess_offchip_ring
= pipe_buffer_create(sctx
->b
.b
.screen
, 0,
2039 max_offchip_buffers
*
2040 sctx
->screen
->tess_offchip_block_dw_size
* 4);
2041 if (!sctx
->tess_offchip_ring
)
2044 si_init_config_add_vgt_flush(sctx
);
2046 /* Append these registers to the init config state. */
2047 if (sctx
->b
.chip_class
>= CIK
) {
2048 if (sctx
->b
.chip_class
>= VI
)
2049 --max_offchip_buffers
;
2051 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
2052 S_030938_SIZE(sctx
->tf_ring
->width0
/ 4));
2053 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
2054 r600_resource(sctx
->tf_ring
)->gpu_address
>> 8);
2055 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
2056 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
2057 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
));
2059 assert(offchip_granularity
== V_03093C_X_8K_DWORDS
);
2060 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
2061 S_008988_SIZE(sctx
->tf_ring
->width0
/ 4));
2062 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
2063 r600_resource(sctx
->tf_ring
)->gpu_address
>> 8);
2064 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
2065 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
));
2068 /* Flush the context to re-emit the init_config state.
2069 * This is done only once in a lifetime of a context.
2071 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
2072 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
2073 si_context_gfx_flush(sctx
, RADEON_FLUSH_ASYNC
, NULL
);
2075 si_set_ring_buffer(&sctx
->b
.b
, SI_HS_RING_TESS_FACTOR
, sctx
->tf_ring
,
2076 0, sctx
->tf_ring
->width0
, false, false, 0, 0, 0);
2078 si_set_ring_buffer(&sctx
->b
.b
, SI_HS_RING_TESS_OFFCHIP
,
2079 sctx
->tess_offchip_ring
, 0,
2080 sctx
->tess_offchip_ring
->width0
, false, false, 0, 0, 0);
2084 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
2085 * VS passes its outputs to TES directly, so the fixed-function shader only
2086 * has to write TESSOUTER and TESSINNER.
2088 static void si_generate_fixed_func_tcs(struct si_context
*sctx
)
2090 struct ureg_src outer
, inner
;
2091 struct ureg_dst tessouter
, tessinner
;
2092 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_TESS_CTRL
);
2095 return; /* if we get here, we're screwed */
2097 assert(!sctx
->fixed_func_tcs_shader
.cso
);
2099 outer
= ureg_DECL_system_value(ureg
,
2100 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
, 0);
2101 inner
= ureg_DECL_system_value(ureg
,
2102 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
, 0);
2104 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
2105 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
2107 ureg_MOV(ureg
, tessouter
, outer
);
2108 ureg_MOV(ureg
, tessinner
, inner
);
2111 sctx
->fixed_func_tcs_shader
.cso
=
2112 ureg_create_shader_and_destroy(ureg
, &sctx
->b
.b
);
2115 static void si_update_vgt_shader_config(struct si_context
*sctx
)
2117 /* Calculate the index of the config.
2118 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
2119 unsigned index
= 2*!!sctx
->tes_shader
.cso
+ !!sctx
->gs_shader
.cso
;
2120 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[index
];
2123 uint32_t stages
= 0;
2125 *pm4
= CALLOC_STRUCT(si_pm4_state
);
2127 if (sctx
->tes_shader
.cso
) {
2128 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
2129 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2131 if (sctx
->gs_shader
.cso
)
2132 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
2134 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
2136 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
2137 } else if (sctx
->gs_shader
.cso
) {
2138 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
2140 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
2143 si_pm4_set_reg(*pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
2145 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
2148 static void si_update_so(struct si_context
*sctx
, struct si_shader_selector
*shader
)
2150 struct pipe_stream_output_info
*so
= &shader
->so
;
2151 uint32_t enabled_stream_buffers_mask
= 0;
2154 for (i
= 0; i
< so
->num_outputs
; i
++)
2155 enabled_stream_buffers_mask
|= (1 << so
->output
[i
].output_buffer
) << (so
->output
[i
].stream
* 4);
2156 sctx
->b
.streamout
.enabled_stream_buffers_mask
= enabled_stream_buffers_mask
;
2157 sctx
->b
.streamout
.stride_in_dw
= shader
->so
.stride
;
2160 bool si_update_shaders(struct si_context
*sctx
)
2162 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
2163 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
2166 /* Update stages before GS. */
2167 if (sctx
->tes_shader
.cso
) {
2168 if (!sctx
->tf_ring
) {
2169 si_init_tess_factor_ring(sctx
);
2175 r
= si_shader_select(ctx
, &sctx
->vs_shader
);
2178 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
2180 if (sctx
->tcs_shader
.cso
) {
2181 r
= si_shader_select(ctx
, &sctx
->tcs_shader
);
2184 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
2186 if (!sctx
->fixed_func_tcs_shader
.cso
) {
2187 si_generate_fixed_func_tcs(sctx
);
2188 if (!sctx
->fixed_func_tcs_shader
.cso
)
2192 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
);
2195 si_pm4_bind_state(sctx
, hs
,
2196 sctx
->fixed_func_tcs_shader
.current
->pm4
);
2199 r
= si_shader_select(ctx
, &sctx
->tes_shader
);
2203 if (sctx
->gs_shader
.cso
) {
2205 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
2208 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
2209 si_update_so(sctx
, sctx
->tes_shader
.cso
);
2211 } else if (sctx
->gs_shader
.cso
) {
2213 r
= si_shader_select(ctx
, &sctx
->vs_shader
);
2216 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
2219 r
= si_shader_select(ctx
, &sctx
->vs_shader
);
2222 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
2223 si_update_so(sctx
, sctx
->vs_shader
.cso
);
2227 if (sctx
->gs_shader
.cso
) {
2228 r
= si_shader_select(ctx
, &sctx
->gs_shader
);
2231 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
2232 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
2233 si_update_so(sctx
, sctx
->gs_shader
.cso
);
2235 if (!si_update_gs_ring_buffers(sctx
))
2238 si_update_gsvs_ring_bindings(sctx
);
2240 si_pm4_bind_state(sctx
, gs
, NULL
);
2241 si_pm4_bind_state(sctx
, es
, NULL
);
2244 si_update_vgt_shader_config(sctx
);
2246 if (sctx
->ps_shader
.cso
) {
2247 unsigned db_shader_control
;
2249 r
= si_shader_select(ctx
, &sctx
->ps_shader
);
2252 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
2255 sctx
->ps_shader
.cso
->db_shader_control
|
2256 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
2258 if (si_pm4_state_changed(sctx
, ps
) || si_pm4_state_changed(sctx
, vs
) ||
2259 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
2260 sctx
->flatshade
!= rs
->flatshade
) {
2261 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
2262 sctx
->flatshade
= rs
->flatshade
;
2263 si_mark_atom_dirty(sctx
, &sctx
->spi_map
);
2266 if (sctx
->b
.family
== CHIP_STONEY
&& si_pm4_state_changed(sctx
, ps
))
2267 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
2269 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
2270 sctx
->ps_db_shader_control
= db_shader_control
;
2271 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
2274 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.ps
.epilog
.poly_line_smoothing
) {
2275 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.ps
.epilog
.poly_line_smoothing
;
2276 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2278 if (sctx
->b
.chip_class
== SI
)
2279 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
2281 if (sctx
->framebuffer
.nr_samples
<= 1)
2282 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
2286 if (si_pm4_state_changed(sctx
, ls
) ||
2287 si_pm4_state_changed(sctx
, hs
) ||
2288 si_pm4_state_changed(sctx
, es
) ||
2289 si_pm4_state_changed(sctx
, gs
) ||
2290 si_pm4_state_changed(sctx
, vs
) ||
2291 si_pm4_state_changed(sctx
, ps
)) {
2292 if (!si_update_spi_tmpring_size(sctx
))
2296 sctx
->do_update_shaders
= false;
2300 void si_init_shader_functions(struct si_context
*sctx
)
2302 si_init_atom(sctx
, &sctx
->spi_map
, &sctx
->atoms
.s
.spi_map
, si_emit_spi_map
);
2304 sctx
->b
.b
.create_vs_state
= si_create_shader_selector
;
2305 sctx
->b
.b
.create_tcs_state
= si_create_shader_selector
;
2306 sctx
->b
.b
.create_tes_state
= si_create_shader_selector
;
2307 sctx
->b
.b
.create_gs_state
= si_create_shader_selector
;
2308 sctx
->b
.b
.create_fs_state
= si_create_shader_selector
;
2310 sctx
->b
.b
.bind_vs_state
= si_bind_vs_shader
;
2311 sctx
->b
.b
.bind_tcs_state
= si_bind_tcs_shader
;
2312 sctx
->b
.b
.bind_tes_state
= si_bind_tes_shader
;
2313 sctx
->b
.b
.bind_gs_state
= si_bind_gs_shader
;
2314 sctx
->b
.b
.bind_fs_state
= si_bind_ps_shader
;
2316 sctx
->b
.b
.delete_vs_state
= si_delete_shader_selector
;
2317 sctx
->b
.b
.delete_tcs_state
= si_delete_shader_selector
;
2318 sctx
->b
.b
.delete_tes_state
= si_delete_shader_selector
;
2319 sctx
->b
.b
.delete_gs_state
= si_delete_shader_selector
;
2320 sctx
->b
.b
.delete_fs_state
= si_delete_shader_selector
;