2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "radeon/r600_cs.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_ureg.h"
31 #include "util/hash_table.h"
32 #include "util/crc32.h"
33 #include "util/u_async_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
37 #include "util/disk_cache.h"
38 #include "util/mesa-sha1.h"
39 #include "ac_exp_param.h"
44 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
47 static void *si_get_tgsi_binary(struct si_shader_selector
*sel
)
49 unsigned tgsi_size
= tgsi_num_tokens(sel
->tokens
) *
50 sizeof(struct tgsi_token
);
51 unsigned size
= 4 + tgsi_size
+ sizeof(sel
->so
);
52 char *result
= (char*)MALLOC(size
);
57 *((uint32_t*)result
) = size
;
58 memcpy(result
+ 4, sel
->tokens
, tgsi_size
);
59 memcpy(result
+ 4 + tgsi_size
, &sel
->so
, sizeof(sel
->so
));
63 /** Copy "data" to "ptr" and return the next dword following copied data. */
64 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
66 /* data may be NULL if size == 0 */
68 memcpy(ptr
, data
, size
);
69 ptr
+= DIV_ROUND_UP(size
, 4);
73 /** Read data from "ptr". Return the next dword following the data. */
74 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
76 memcpy(data
, ptr
, size
);
77 ptr
+= DIV_ROUND_UP(size
, 4);
82 * Write the size as uint followed by the data. Return the next dword
83 * following the copied data.
85 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
88 return write_data(ptr
, data
, size
);
92 * Read the size as uint followed by the data. Return both via parameters.
93 * Return the next dword following the data.
95 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
98 assert(*data
== NULL
);
101 *data
= malloc(*size
);
102 return read_data(ptr
, *data
, *size
);
106 * Return the shader binary in a buffer. The first 4 bytes contain its size
109 static void *si_get_shader_binary(struct si_shader
*shader
)
111 /* There is always a size of data followed by the data itself. */
112 unsigned relocs_size
= shader
->binary
.reloc_count
*
113 sizeof(shader
->binary
.relocs
[0]);
114 unsigned disasm_size
= shader
->binary
.disasm_string
?
115 strlen(shader
->binary
.disasm_string
) + 1 : 0;
116 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
117 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
120 4 + /* CRC32 of the data below */
121 align(sizeof(shader
->config
), 4) +
122 align(sizeof(shader
->info
), 4) +
123 4 + align(shader
->binary
.code_size
, 4) +
124 4 + align(shader
->binary
.rodata_size
, 4) +
125 4 + align(relocs_size
, 4) +
126 4 + align(disasm_size
, 4) +
127 4 + align(llvm_ir_size
, 4);
128 void *buffer
= CALLOC(1, size
);
129 uint32_t *ptr
= (uint32_t*)buffer
;
135 ptr
++; /* CRC32 is calculated at the end. */
137 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
138 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
139 ptr
= write_chunk(ptr
, shader
->binary
.code
, shader
->binary
.code_size
);
140 ptr
= write_chunk(ptr
, shader
->binary
.rodata
, shader
->binary
.rodata_size
);
141 ptr
= write_chunk(ptr
, shader
->binary
.relocs
, relocs_size
);
142 ptr
= write_chunk(ptr
, shader
->binary
.disasm_string
, disasm_size
);
143 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
144 assert((char *)ptr
- (char *)buffer
== size
);
147 ptr
= (uint32_t*)buffer
;
149 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
154 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
156 uint32_t *ptr
= (uint32_t*)binary
;
157 uint32_t size
= *ptr
++;
158 uint32_t crc32
= *ptr
++;
161 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
162 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
166 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
167 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
168 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.code
,
169 &shader
->binary
.code_size
);
170 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.rodata
,
171 &shader
->binary
.rodata_size
);
172 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.relocs
, &chunk_size
);
173 shader
->binary
.reloc_count
= chunk_size
/ sizeof(shader
->binary
.relocs
[0]);
174 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.disasm_string
, &chunk_size
);
175 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
181 * Insert a shader into the cache. It's assumed the shader is not in the cache.
182 * Use si_shader_cache_load_shader before calling this.
184 * Returns false on failure, in which case the tgsi_binary should be freed.
186 static bool si_shader_cache_insert_shader(struct si_screen
*sscreen
,
188 struct si_shader
*shader
,
189 bool insert_into_disk_cache
)
192 struct hash_entry
*entry
;
193 uint8_t key
[CACHE_KEY_SIZE
];
195 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, tgsi_binary
);
197 return false; /* already added */
199 hw_binary
= si_get_shader_binary(shader
);
203 if (_mesa_hash_table_insert(sscreen
->shader_cache
, tgsi_binary
,
204 hw_binary
) == NULL
) {
209 if (sscreen
->b
.disk_shader_cache
&& insert_into_disk_cache
) {
210 disk_cache_compute_key(sscreen
->b
.disk_shader_cache
, tgsi_binary
,
211 *((uint32_t *)tgsi_binary
), key
);
212 disk_cache_put(sscreen
->b
.disk_shader_cache
, key
, hw_binary
,
213 *((uint32_t *) hw_binary
), NULL
);
219 static bool si_shader_cache_load_shader(struct si_screen
*sscreen
,
221 struct si_shader
*shader
)
223 struct hash_entry
*entry
=
224 _mesa_hash_table_search(sscreen
->shader_cache
, tgsi_binary
);
226 if (sscreen
->b
.disk_shader_cache
) {
227 unsigned char sha1
[CACHE_KEY_SIZE
];
228 size_t tg_size
= *((uint32_t *) tgsi_binary
);
230 disk_cache_compute_key(sscreen
->b
.disk_shader_cache
,
231 tgsi_binary
, tg_size
, sha1
);
235 disk_cache_get(sscreen
->b
.disk_shader_cache
,
240 if (binary_size
< sizeof(uint32_t) ||
241 *((uint32_t*)buffer
) != binary_size
) {
242 /* Something has gone wrong discard the item
243 * from the cache and rebuild/link from
246 assert(!"Invalid radeonsi shader disk cache "
249 disk_cache_remove(sscreen
->b
.disk_shader_cache
,
256 if (!si_load_shader_binary(shader
, buffer
)) {
262 if (!si_shader_cache_insert_shader(sscreen
, tgsi_binary
,
269 if (si_load_shader_binary(shader
, entry
->data
))
274 p_atomic_inc(&sscreen
->b
.num_shader_cache_hits
);
278 static uint32_t si_shader_cache_key_hash(const void *key
)
280 /* The first dword is the key size. */
281 return util_hash_crc32(key
, *(uint32_t*)key
);
284 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
286 uint32_t *keya
= (uint32_t*)a
;
287 uint32_t *keyb
= (uint32_t*)b
;
289 /* The first dword is the key size. */
293 return memcmp(keya
, keyb
, *keya
) == 0;
296 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
298 FREE((void*)entry
->key
);
302 bool si_init_shader_cache(struct si_screen
*sscreen
)
304 (void) mtx_init(&sscreen
->shader_cache_mutex
, mtx_plain
);
305 sscreen
->shader_cache
=
306 _mesa_hash_table_create(NULL
,
307 si_shader_cache_key_hash
,
308 si_shader_cache_key_equals
);
310 return sscreen
->shader_cache
!= NULL
;
313 void si_destroy_shader_cache(struct si_screen
*sscreen
)
315 if (sscreen
->shader_cache
)
316 _mesa_hash_table_destroy(sscreen
->shader_cache
,
317 si_destroy_shader_cache_entry
);
318 mtx_destroy(&sscreen
->shader_cache_mutex
);
323 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
324 struct si_shader_selector
*tes
,
325 struct si_pm4_state
*pm4
)
327 struct tgsi_shader_info
*info
= &tes
->info
;
328 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
329 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
330 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
331 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
332 unsigned type
, partitioning
, topology
, distribution_mode
;
334 switch (tes_prim_mode
) {
335 case PIPE_PRIM_LINES
:
336 type
= V_028B6C_TESS_ISOLINE
;
338 case PIPE_PRIM_TRIANGLES
:
339 type
= V_028B6C_TESS_TRIANGLE
;
341 case PIPE_PRIM_QUADS
:
342 type
= V_028B6C_TESS_QUAD
;
349 switch (tes_spacing
) {
350 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
351 partitioning
= V_028B6C_PART_FRAC_ODD
;
353 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
354 partitioning
= V_028B6C_PART_FRAC_EVEN
;
356 case PIPE_TESS_SPACING_EQUAL
:
357 partitioning
= V_028B6C_PART_INTEGER
;
365 topology
= V_028B6C_OUTPUT_POINT
;
366 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
367 topology
= V_028B6C_OUTPUT_LINE
;
368 else if (tes_vertex_order_cw
)
369 /* for some reason, this must be the other way around */
370 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
372 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
374 if (sscreen
->has_distributed_tess
) {
375 if (sscreen
->b
.family
== CHIP_FIJI
||
376 sscreen
->b
.family
>= CHIP_POLARIS10
)
377 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
379 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
381 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
383 si_pm4_set_reg(pm4
, R_028B6C_VGT_TF_PARAM
,
384 S_028B6C_TYPE(type
) |
385 S_028B6C_PARTITIONING(partitioning
) |
386 S_028B6C_TOPOLOGY(topology
) |
387 S_028B6C_DISTRIBUTION_MODE(distribution_mode
));
390 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
391 * whether the "fractional odd" tessellation spacing is used.
393 * Possible VGT configurations and which state should set the register:
395 * Reg set in | VGT shader configuration | Value
396 * ------------------------------------------------------
398 * VS as ES | ES -> GS -> VS | 30
399 * TES as VS | LS -> HS -> VS | 14 or 30
400 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
402 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
404 static void polaris_set_vgt_vertex_reuse(struct si_screen
*sscreen
,
405 struct si_shader_selector
*sel
,
406 struct si_shader
*shader
,
407 struct si_pm4_state
*pm4
)
409 unsigned type
= sel
->type
;
411 if (sscreen
->b
.family
< CHIP_POLARIS10
)
414 /* VS as VS, or VS as ES: */
415 if ((type
== PIPE_SHADER_VERTEX
&&
417 (!shader
->key
.as_ls
&& !shader
->is_gs_copy_shader
))) ||
418 /* TES as VS, or TES as ES: */
419 type
== PIPE_SHADER_TESS_EVAL
) {
420 unsigned vtx_reuse_depth
= 30;
422 if (type
== PIPE_SHADER_TESS_EVAL
&&
423 sel
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] ==
424 PIPE_TESS_SPACING_FRACTIONAL_ODD
)
425 vtx_reuse_depth
= 14;
427 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
432 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
435 si_pm4_clear_state(shader
->pm4
);
437 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
442 static void si_shader_ls(struct si_screen
*sscreen
, struct si_shader
*shader
)
444 struct si_pm4_state
*pm4
;
445 unsigned vgpr_comp_cnt
;
448 assert(sscreen
->b
.chip_class
<= VI
);
450 pm4
= si_get_shader_pm4_state(shader
);
454 va
= shader
->bo
->gpu_address
;
455 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
457 /* We need at least 2 components for LS.
458 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
459 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
461 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
463 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
464 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, va
>> 40);
466 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
467 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
468 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt
) |
469 S_00B528_DX10_CLAMP(1) |
470 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
471 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(SI_VS_NUM_USER_SGPR
) |
472 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
475 static void si_shader_hs(struct si_screen
*sscreen
, struct si_shader
*shader
)
477 struct si_pm4_state
*pm4
;
479 unsigned ls_vgpr_comp_cnt
= 0;
481 pm4
= si_get_shader_pm4_state(shader
);
485 va
= shader
->bo
->gpu_address
;
486 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
488 if (sscreen
->b
.chip_class
>= GFX9
) {
489 si_pm4_set_reg(pm4
, R_00B410_SPI_SHADER_PGM_LO_LS
, va
>> 8);
490 si_pm4_set_reg(pm4
, R_00B414_SPI_SHADER_PGM_HI_LS
, va
>> 40);
492 /* We need at least 2 components for LS.
493 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
494 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
496 ls_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
498 shader
->config
.rsrc2
=
499 S_00B42C_USER_SGPR(GFX9_TCS_NUM_USER_SGPR
) |
500 S_00B42C_USER_SGPR_MSB(GFX9_TCS_NUM_USER_SGPR
>> 5) |
501 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
503 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
504 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, va
>> 40);
506 shader
->config
.rsrc2
=
507 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR
) |
508 S_00B42C_OC_LDS_EN(1) |
509 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
512 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
513 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
514 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
515 S_00B428_DX10_CLAMP(1) |
516 S_00B428_FLOAT_MODE(shader
->config
.float_mode
) |
517 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt
));
519 if (sscreen
->b
.chip_class
<= VI
) {
520 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
521 shader
->config
.rsrc2
);
525 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
527 struct si_pm4_state
*pm4
;
528 unsigned num_user_sgprs
;
529 unsigned vgpr_comp_cnt
;
533 assert(sscreen
->b
.chip_class
<= VI
);
535 pm4
= si_get_shader_pm4_state(shader
);
539 va
= shader
->bo
->gpu_address
;
540 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
542 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
543 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
544 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
545 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
546 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
547 vgpr_comp_cnt
= shader
->selector
->info
.uses_primid
? 3 : 2;
548 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
550 unreachable("invalid shader selector type");
552 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
554 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
555 shader
->selector
->esgs_itemsize
/ 4);
556 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
557 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
558 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
559 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
560 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
561 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
562 S_00B328_DX10_CLAMP(1) |
563 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
564 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
565 S_00B32C_USER_SGPR(num_user_sgprs
) |
566 S_00B32C_OC_LDS_EN(oc_lds_en
) |
567 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
569 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
570 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
572 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
576 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
579 static uint32_t si_vgt_gs_mode(struct si_shader_selector
*sel
)
581 enum chip_class chip_class
= sel
->screen
->b
.chip_class
;
582 unsigned gs_max_vert_out
= sel
->gs_max_out_vertices
;
585 if (gs_max_vert_out
<= 128) {
586 cut_mode
= V_028A40_GS_CUT_128
;
587 } else if (gs_max_vert_out
<= 256) {
588 cut_mode
= V_028A40_GS_CUT_256
;
589 } else if (gs_max_vert_out
<= 512) {
590 cut_mode
= V_028A40_GS_CUT_512
;
592 assert(gs_max_vert_out
<= 1024);
593 cut_mode
= V_028A40_GS_CUT_1024
;
596 return S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
597 S_028A40_CUT_MODE(cut_mode
)|
598 S_028A40_ES_WRITE_OPTIMIZE(chip_class
<= VI
) |
599 S_028A40_GS_WRITE_OPTIMIZE(1) |
600 S_028A40_ONCHIP(chip_class
>= GFX9
? 1 : 0);
603 struct gfx9_gs_info
{
604 unsigned es_verts_per_subgroup
;
605 unsigned gs_prims_per_subgroup
;
606 unsigned gs_inst_prims_in_subgroup
;
607 unsigned max_prims_per_subgroup
;
611 static void gfx9_get_gs_info(struct si_shader_selector
*es
,
612 struct si_shader_selector
*gs
,
613 struct gfx9_gs_info
*out
)
615 unsigned gs_num_invocations
= MAX2(gs
->gs_num_invocations
, 1);
616 unsigned input_prim
= gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
617 bool uses_adjacency
= input_prim
>= PIPE_PRIM_LINES_ADJACENCY
&&
618 input_prim
<= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
;
620 /* All these are in dwords: */
621 /* We can't allow using the whole LDS, because GS waves compete with
622 * other shader stages for LDS space. */
623 const unsigned max_lds_size
= 8 * 1024;
624 const unsigned esgs_itemsize
= es
->esgs_itemsize
/ 4;
625 unsigned esgs_lds_size
;
627 /* All these are per subgroup: */
628 const unsigned max_out_prims
= 32 * 1024;
629 const unsigned max_es_verts
= 255;
630 const unsigned ideal_gs_prims
= 64;
631 unsigned max_gs_prims
, gs_prims
;
632 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
634 assert(gs_num_invocations
<= 32); /* GL maximum */
636 if (uses_adjacency
|| gs_num_invocations
> 1)
637 max_gs_prims
= 127 / gs_num_invocations
;
641 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
642 * Make sure we don't go over the maximum value.
644 if (gs
->gs_max_out_vertices
> 0) {
645 max_gs_prims
= MIN2(max_gs_prims
,
647 (gs
->gs_max_out_vertices
* gs_num_invocations
));
649 assert(max_gs_prims
> 0);
651 /* If the primitive has adjacency, halve the number of vertices
652 * that will be reused in multiple primitives.
654 min_es_verts
= gs
->gs_input_verts_per_prim
/ (uses_adjacency
? 2 : 1);
656 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
657 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
659 /* Compute ESGS LDS size based on the worst case number of ES vertices
660 * needed to create the target number of GS prims per subgroup.
662 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
664 /* If total LDS usage is too big, refactor partitions based on ratio
665 * of ESGS item sizes.
667 if (esgs_lds_size
> max_lds_size
) {
668 /* Our target GS Prims Per Subgroup was too large. Calculate
669 * the maximum number of GS Prims Per Subgroup that will fit
670 * into LDS, capped by the maximum that the hardware can support.
672 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
674 assert(gs_prims
> 0);
675 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
678 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
679 assert(esgs_lds_size
<= max_lds_size
);
682 /* Now calculate remaining ESGS information. */
684 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
686 es_verts
= max_es_verts
;
688 /* Vertices for adjacency primitives are not always reused, so restore
689 * it for ES_VERTS_PER_SUBGRP.
691 min_es_verts
= gs
->gs_input_verts_per_prim
;
693 /* For normal primitives, the VGT only checks if they are past the ES
694 * verts per subgroup after allocating a full GS primitive and if they
695 * are, kick off a new subgroup. But if those additional ES verts are
696 * unique (e.g. not reused) we need to make sure there is enough LDS
697 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
699 es_verts
-= min_es_verts
- 1;
701 out
->es_verts_per_subgroup
= es_verts
;
702 out
->gs_prims_per_subgroup
= gs_prims
;
703 out
->gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
704 out
->max_prims_per_subgroup
= out
->gs_inst_prims_in_subgroup
*
705 gs
->gs_max_out_vertices
;
706 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
708 assert(out
->max_prims_per_subgroup
<= max_out_prims
);
711 static void si_shader_gs(struct si_screen
*sscreen
, struct si_shader
*shader
)
713 struct si_shader_selector
*sel
= shader
->selector
;
714 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
715 unsigned gs_num_invocations
= sel
->gs_num_invocations
;
716 struct si_pm4_state
*pm4
;
718 unsigned max_stream
= sel
->max_gs_stream
;
721 pm4
= si_get_shader_pm4_state(shader
);
725 offset
= num_components
[0] * sel
->gs_max_out_vertices
;
726 si_pm4_set_reg(pm4
, R_028A60_VGT_GSVS_RING_OFFSET_1
, offset
);
728 offset
+= num_components
[1] * sel
->gs_max_out_vertices
;
729 si_pm4_set_reg(pm4
, R_028A64_VGT_GSVS_RING_OFFSET_2
, offset
);
731 offset
+= num_components
[2] * sel
->gs_max_out_vertices
;
732 si_pm4_set_reg(pm4
, R_028A68_VGT_GSVS_RING_OFFSET_3
, offset
);
734 offset
+= num_components
[3] * sel
->gs_max_out_vertices
;
735 si_pm4_set_reg(pm4
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
737 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
738 assert(offset
< (1 << 15));
740 si_pm4_set_reg(pm4
, R_028B38_VGT_GS_MAX_VERT_OUT
, sel
->gs_max_out_vertices
);
742 si_pm4_set_reg(pm4
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, num_components
[0]);
743 si_pm4_set_reg(pm4
, R_028B60_VGT_GS_VERT_ITEMSIZE_1
, (max_stream
>= 1) ? num_components
[1] : 0);
744 si_pm4_set_reg(pm4
, R_028B64_VGT_GS_VERT_ITEMSIZE_2
, (max_stream
>= 2) ? num_components
[2] : 0);
745 si_pm4_set_reg(pm4
, R_028B68_VGT_GS_VERT_ITEMSIZE_3
, (max_stream
>= 3) ? num_components
[3] : 0);
747 si_pm4_set_reg(pm4
, R_028B90_VGT_GS_INSTANCE_CNT
,
748 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
749 S_028B90_ENABLE(gs_num_invocations
> 0));
751 va
= shader
->bo
->gpu_address
;
752 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
754 if (sscreen
->b
.chip_class
>= GFX9
) {
755 unsigned input_prim
= sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
756 unsigned es_type
= shader
->key
.part
.gs
.es
->type
;
757 unsigned es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
758 struct gfx9_gs_info gs_info
;
760 if (es_type
== PIPE_SHADER_VERTEX
)
761 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
762 es_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
763 else if (es_type
== PIPE_SHADER_TESS_EVAL
)
764 es_vgpr_comp_cnt
= shader
->key
.part
.gs
.es
->info
.uses_primid
? 3 : 2;
766 unreachable("invalid shader selector type");
768 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
769 * VGPR[0:4] are always loaded.
771 if (sel
->info
.uses_invocationid
)
772 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
773 else if (sel
->info
.uses_primid
)
774 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
775 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
776 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
778 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
780 gfx9_get_gs_info(shader
->key
.part
.gs
.es
, sel
, &gs_info
);
782 si_pm4_set_reg(pm4
, R_00B210_SPI_SHADER_PGM_LO_ES
, va
>> 8);
783 si_pm4_set_reg(pm4
, R_00B214_SPI_SHADER_PGM_HI_ES
, va
>> 40);
785 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
786 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
787 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
788 S_00B228_DX10_CLAMP(1) |
789 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
790 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
));
791 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
792 S_00B22C_USER_SGPR(GFX9_GS_NUM_USER_SGPR
) |
793 S_00B22C_USER_SGPR_MSB(GFX9_GS_NUM_USER_SGPR
>> 5) |
794 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
795 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
796 S_00B22C_LDS_SIZE(gs_info
.lds_size
) |
797 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
799 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
800 S_028A44_ES_VERTS_PER_SUBGRP(gs_info
.es_verts_per_subgroup
) |
801 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info
.gs_prims_per_subgroup
) |
802 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info
.gs_inst_prims_in_subgroup
));
803 si_pm4_set_reg(pm4
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
804 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info
.max_prims_per_subgroup
));
805 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
806 shader
->key
.part
.gs
.es
->esgs_itemsize
/ 4);
808 if (es_type
== PIPE_SHADER_TESS_EVAL
)
809 si_set_tesseval_regs(sscreen
, shader
->key
.part
.gs
.es
, pm4
);
811 polaris_set_vgt_vertex_reuse(sscreen
, shader
->key
.part
.gs
.es
,
814 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
815 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, va
>> 40);
817 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
818 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
819 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
820 S_00B228_DX10_CLAMP(1) |
821 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
822 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
823 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR
) |
824 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
829 * Compute the state for \p shader, which will run as a vertex shader on the
832 * If \p gs is non-NULL, it points to the geometry shader for which this shader
833 * is the copy shader.
835 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
836 struct si_shader_selector
*gs
)
838 const struct tgsi_shader_info
*info
= &shader
->selector
->info
;
839 struct si_pm4_state
*pm4
;
840 unsigned num_user_sgprs
;
841 unsigned nparams
, vgpr_comp_cnt
;
844 unsigned window_space
=
845 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
846 bool enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| info
->uses_primid
;
848 pm4
= si_get_shader_pm4_state(shader
);
852 /* We always write VGT_GS_MODE in the VS state, because every switch
853 * between different shader pipelines involving a different GS or no
854 * GS at all involves a switch of the VS (different GS use different
855 * copy shaders). On the other hand, when the API switches from a GS to
856 * no GS and then back to the same GS used originally, the GS state is
860 unsigned mode
= V_028A40_GS_OFF
;
862 /* PrimID needs GS scenario A. */
864 mode
= V_028A40_GS_SCENARIO_A
;
866 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, S_028A40_MODE(mode
));
867 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, enable_prim_id
);
869 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, si_vgt_gs_mode(gs
));
870 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
873 if (sscreen
->b
.chip_class
<= VI
) {
874 /* Reuse needs to be set off if we write oViewport. */
875 si_pm4_set_reg(pm4
, R_028AB4_VGT_REUSE_OFF
,
876 S_028AB4_REUSE_OFF(info
->writes_viewport_index
));
879 va
= shader
->bo
->gpu_address
;
880 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
883 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
884 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
885 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
886 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
887 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
888 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
890 vgpr_comp_cnt
= enable_prim_id
? 2 : (shader
->info
.uses_instanceid
? 1 : 0);
892 if (info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
]) {
893 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
894 info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
896 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
898 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
899 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
900 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
902 unreachable("invalid shader selector type");
904 /* VS is required to export at least one param. */
905 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
906 si_pm4_set_reg(pm4
, R_0286C4_SPI_VS_OUT_CONFIG
,
907 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
909 si_pm4_set_reg(pm4
, R_02870C_SPI_SHADER_POS_FORMAT
,
910 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
911 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
912 V_02870C_SPI_SHADER_4COMP
:
913 V_02870C_SPI_SHADER_NONE
) |
914 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
915 V_02870C_SPI_SHADER_4COMP
:
916 V_02870C_SPI_SHADER_NONE
) |
917 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
918 V_02870C_SPI_SHADER_4COMP
:
919 V_02870C_SPI_SHADER_NONE
));
921 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
923 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
924 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, va
>> 40);
925 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
926 S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
927 S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
928 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
929 S_00B128_DX10_CLAMP(1) |
930 S_00B128_FLOAT_MODE(shader
->config
.float_mode
));
931 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
932 S_00B12C_USER_SGPR(num_user_sgprs
) |
933 S_00B12C_OC_LDS_EN(oc_lds_en
) |
934 S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
935 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
936 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
937 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
938 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
) |
939 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
941 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
942 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
944 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
945 S_028818_VTX_W0_FMT(1) |
946 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
947 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
948 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
950 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
951 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
953 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
956 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
958 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
959 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
960 !!(info
->colors_read
& 0xf0);
961 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
962 (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
964 assert(num_interp
<= 32);
965 return MIN2(num_interp
, 32);
968 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
970 unsigned value
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
971 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
973 /* If the i-th target format is set, all previous target formats must
974 * be non-zero to avoid hangs.
976 for (i
= 0; i
< num_targets
; i
++)
977 if (!(value
& (0xf << (i
* 4))))
978 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
983 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format
)
985 unsigned i
, cb_shader_mask
= 0;
987 for (i
= 0; i
< 8; i
++) {
988 switch ((spi_shader_col_format
>> (i
* 4)) & 0xf) {
989 case V_028714_SPI_SHADER_ZERO
:
991 case V_028714_SPI_SHADER_32_R
:
992 cb_shader_mask
|= 0x1 << (i
* 4);
994 case V_028714_SPI_SHADER_32_GR
:
995 cb_shader_mask
|= 0x3 << (i
* 4);
997 case V_028714_SPI_SHADER_32_AR
:
998 cb_shader_mask
|= 0x9 << (i
* 4);
1000 case V_028714_SPI_SHADER_FP16_ABGR
:
1001 case V_028714_SPI_SHADER_UNORM16_ABGR
:
1002 case V_028714_SPI_SHADER_SNORM16_ABGR
:
1003 case V_028714_SPI_SHADER_UINT16_ABGR
:
1004 case V_028714_SPI_SHADER_SINT16_ABGR
:
1005 case V_028714_SPI_SHADER_32_ABGR
:
1006 cb_shader_mask
|= 0xf << (i
* 4);
1012 return cb_shader_mask
;
1015 static void si_shader_ps(struct si_shader
*shader
)
1017 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1018 struct si_pm4_state
*pm4
;
1019 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
1020 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
1022 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
1024 /* we need to enable at least one of them, otherwise we hang the GPU */
1025 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1026 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1027 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1028 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
1029 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
1030 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1031 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
1032 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
1033 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1034 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
1035 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1036 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1037 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1038 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
1040 /* Validate interpolation optimization flags (read as implications). */
1041 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1042 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1043 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1044 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1045 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1046 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1047 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
1048 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
1049 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1050 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
1051 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
1052 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1053 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
1054 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1055 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1056 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
1057 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1058 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1060 /* Validate cases when the optimizations are off (read as implications). */
1061 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1062 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1063 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
1064 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1065 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1066 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
1068 pm4
= si_get_shader_pm4_state(shader
);
1072 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1074 * 0 -> Position = pixel center
1075 * 1 -> Position = pixel centroid
1076 * 2 -> Position = at sample position
1078 * From GLSL 4.5 specification, section 7.1:
1079 * "The variable gl_FragCoord is available as an input variable from
1080 * within fragment shaders and it holds the window relative coordinates
1081 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1082 * value can be for any location within the pixel, or one of the
1083 * fragment samples. The use of centroid does not further restrict
1084 * this value to be inside the current primitive."
1086 * Meaning that centroid has no effect and we can return anything within
1087 * the pixel. Thus, return the value at sample position, because that's
1088 * the most accurate one shaders can get.
1090 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1092 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
1093 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
1094 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
1096 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
1097 cb_shader_mask
= si_get_cb_shader_mask(spi_shader_col_format
);
1099 /* Ensure that some export memory is always allocated, for two reasons:
1101 * 1) Correctness: The hardware ignores the EXEC mask if no export
1102 * memory is allocated, so KILL and alpha test do not work correctly
1104 * 2) Performance: Every shader needs at least a NULL export, even when
1105 * it writes no color/depth output. The NULL export instruction
1106 * stalls without this setting.
1108 * Don't add this to CB_SHADER_MASK.
1110 if (!spi_shader_col_format
&&
1111 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
1112 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
1114 si_pm4_set_reg(pm4
, R_0286CC_SPI_PS_INPUT_ENA
, input_ena
);
1115 si_pm4_set_reg(pm4
, R_0286D0_SPI_PS_INPUT_ADDR
,
1116 shader
->config
.spi_ps_input_addr
);
1118 /* Set interpolation controls. */
1119 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
));
1121 /* Set registers. */
1122 si_pm4_set_reg(pm4
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
1123 si_pm4_set_reg(pm4
, R_0286D8_SPI_PS_IN_CONTROL
, spi_ps_in_control
);
1125 si_pm4_set_reg(pm4
, R_028710_SPI_SHADER_Z_FORMAT
,
1126 si_get_spi_shader_z_format(info
->writes_z
,
1127 info
->writes_stencil
,
1128 info
->writes_samplemask
));
1130 si_pm4_set_reg(pm4
, R_028714_SPI_SHADER_COL_FORMAT
, spi_shader_col_format
);
1131 si_pm4_set_reg(pm4
, R_02823C_CB_SHADER_MASK
, cb_shader_mask
);
1133 va
= shader
->bo
->gpu_address
;
1134 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1135 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
1136 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, va
>> 40);
1138 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
,
1139 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1140 S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
1141 S_00B028_DX10_CLAMP(1) |
1142 S_00B028_FLOAT_MODE(shader
->config
.float_mode
));
1143 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
1144 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
1145 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
1146 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1149 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
1150 struct si_shader
*shader
)
1152 switch (shader
->selector
->type
) {
1153 case PIPE_SHADER_VERTEX
:
1154 if (shader
->key
.as_ls
)
1155 si_shader_ls(sscreen
, shader
);
1156 else if (shader
->key
.as_es
)
1157 si_shader_es(sscreen
, shader
);
1159 si_shader_vs(sscreen
, shader
, NULL
);
1161 case PIPE_SHADER_TESS_CTRL
:
1162 si_shader_hs(sscreen
, shader
);
1164 case PIPE_SHADER_TESS_EVAL
:
1165 if (shader
->key
.as_es
)
1166 si_shader_es(sscreen
, shader
);
1168 si_shader_vs(sscreen
, shader
, NULL
);
1170 case PIPE_SHADER_GEOMETRY
:
1171 si_shader_gs(sscreen
, shader
);
1173 case PIPE_SHADER_FRAGMENT
:
1174 si_shader_ps(shader
);
1181 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
1183 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1184 if (sctx
->queued
.named
.dsa
)
1185 return sctx
->queued
.named
.dsa
->alpha_func
;
1187 return PIPE_FUNC_ALWAYS
;
1190 static void si_shader_selector_key_vs(struct si_context
*sctx
,
1191 struct si_shader_selector
*vs
,
1192 struct si_shader_key
*key
,
1193 struct si_vs_prolog_bits
*prolog_key
)
1195 if (!sctx
->vertex_elements
)
1198 prolog_key
->instance_divisor_is_one
=
1199 sctx
->vertex_elements
->instance_divisor_is_one
;
1200 prolog_key
->instance_divisor_is_fetched
=
1201 sctx
->vertex_elements
->instance_divisor_is_fetched
;
1203 /* Prefer a monolithic shader to allow scheduling divisions around
1205 if (prolog_key
->instance_divisor_is_fetched
)
1206 key
->opt
.prefer_mono
= 1;
1208 unsigned count
= MIN2(vs
->info
.num_inputs
,
1209 sctx
->vertex_elements
->count
);
1210 memcpy(key
->mono
.vs_fix_fetch
, sctx
->vertex_elements
->fix_fetch
, count
);
1213 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
,
1214 struct si_shader_selector
*vs
,
1215 struct si_shader_key
*key
)
1217 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1219 key
->opt
.clip_disable
=
1220 sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
1221 (vs
->info
.clipdist_writemask
||
1222 vs
->info
.writes_clipvertex
) &&
1223 !vs
->info
.culldist_writemask
;
1225 /* Find out if PS is disabled. */
1226 bool ps_disabled
= true;
1228 bool ps_modifies_zs
= ps
->info
.uses_kill
||
1229 ps
->info
.writes_z
||
1230 ps
->info
.writes_stencil
||
1231 ps
->info
.writes_samplemask
||
1232 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
1234 unsigned ps_colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
&
1235 sctx
->queued
.named
.blend
->cb_target_mask
;
1236 if (!ps
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
])
1237 ps_colormask
&= ps
->colors_written_4bit
;
1239 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
1242 !ps
->info
.writes_memory
);
1245 /* Find out which VS outputs aren't used by the PS. */
1246 uint64_t outputs_written
= vs
->outputs_written
;
1247 uint64_t inputs_read
= 0;
1249 /* ignore POSITION, PSIZE */
1250 outputs_written
&= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION
, 0) |
1251 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE
, 0))));
1254 inputs_read
= ps
->inputs_read
;
1257 uint64_t linked
= outputs_written
& inputs_read
;
1259 key
->opt
.kill_outputs
= ~linked
& outputs_written
;
1262 /* Compute the key for the hw shader variant */
1263 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
1264 struct si_shader_selector
*sel
,
1265 struct si_shader_key
*key
)
1267 struct si_context
*sctx
= (struct si_context
*)ctx
;
1269 memset(key
, 0, sizeof(*key
));
1271 switch (sel
->type
) {
1272 case PIPE_SHADER_VERTEX
:
1273 si_shader_selector_key_vs(sctx
, sel
, key
, &key
->part
.vs
.prolog
);
1275 if (sctx
->tes_shader
.cso
)
1277 else if (sctx
->gs_shader
.cso
)
1280 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1282 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1283 key
->mono
.u
.vs_export_prim_id
= 1;
1286 case PIPE_SHADER_TESS_CTRL
:
1287 if (sctx
->b
.chip_class
>= GFX9
) {
1288 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1289 key
, &key
->part
.tcs
.ls_prolog
);
1290 key
->part
.tcs
.ls
= sctx
->vs_shader
.cso
;
1292 /* When the LS VGPR fix is needed, monolithic shaders
1294 * - avoid initializing EXEC in both the LS prolog
1295 * and the LS main part when !vs_needs_prolog
1296 * - remove the fixup for unused input VGPRs
1298 key
->part
.tcs
.ls_prolog
.ls_vgpr_fix
= sctx
->ls_vgpr_fix
;
1300 /* The LS output / HS input layout can be communicated
1301 * directly instead of via user SGPRs for merged LS-HS.
1302 * The LS VGPR fix prefers this too.
1304 key
->opt
.prefer_mono
= 1;
1307 key
->part
.tcs
.epilog
.prim_mode
=
1308 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1309 key
->part
.tcs
.epilog
.invoc0_tess_factors_are_def
=
1310 sel
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1311 key
->part
.tcs
.epilog
.tes_reads_tess_factors
=
1312 sctx
->tes_shader
.cso
->info
.reads_tess_factors
;
1314 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
1315 key
->mono
.u
.ff_tcs_inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
1317 case PIPE_SHADER_TESS_EVAL
:
1318 if (sctx
->gs_shader
.cso
)
1321 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1323 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1324 key
->mono
.u
.vs_export_prim_id
= 1;
1327 case PIPE_SHADER_GEOMETRY
:
1328 if (sctx
->b
.chip_class
>= GFX9
) {
1329 if (sctx
->tes_shader
.cso
) {
1330 key
->part
.gs
.es
= sctx
->tes_shader
.cso
;
1332 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1333 key
, &key
->part
.gs
.vs_prolog
);
1334 key
->part
.gs
.es
= sctx
->vs_shader
.cso
;
1337 /* Merged ES-GS can have unbalanced wave usage.
1339 * ES threads are per-vertex, while GS threads are
1340 * per-primitive. So without any amplification, there
1341 * are fewer GS threads than ES threads, which can result
1342 * in empty (no-op) GS waves. With too much amplification,
1343 * there are more GS threads than ES threads, which
1344 * can result in empty (no-op) ES waves.
1346 * Non-monolithic shaders are implemented by setting EXEC
1347 * at the beginning of shader parts, and don't jump to
1348 * the end if EXEC is 0.
1350 * Monolithic shaders use conditional blocks, so they can
1351 * jump and skip empty waves of ES or GS. So set this to
1352 * always use optimized variants, which are monolithic.
1354 key
->opt
.prefer_mono
= 1;
1356 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
1358 case PIPE_SHADER_FRAGMENT
: {
1359 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1360 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1362 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
1363 sel
->info
.colors_written
== 0x1)
1364 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
1367 /* Select the shader color format based on whether
1368 * blending or alpha are needed.
1370 key
->part
.ps
.epilog
.spi_shader_col_format
=
1371 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1372 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
1373 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1374 sctx
->framebuffer
.spi_shader_col_format_blend
) |
1375 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1376 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
1377 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1378 sctx
->framebuffer
.spi_shader_col_format
);
1379 key
->part
.ps
.epilog
.spi_shader_col_format
&= blend
->cb_target_enabled_4bit
;
1381 /* The output for dual source blending should have
1382 * the same format as the first output.
1384 if (blend
->dual_src_blend
)
1385 key
->part
.ps
.epilog
.spi_shader_col_format
|=
1386 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
1388 key
->part
.ps
.epilog
.spi_shader_col_format
= sctx
->framebuffer
.spi_shader_col_format
;
1390 /* If alpha-to-coverage is enabled, we have to export alpha
1391 * even if there is no color buffer.
1393 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) &&
1394 blend
&& blend
->alpha_to_coverage
)
1395 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
1397 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1398 * to the range supported by the type if a channel has less
1399 * than 16 bits and the export format is 16_ABGR.
1401 if (sctx
->b
.chip_class
<= CIK
&& sctx
->b
.family
!= CHIP_HAWAII
) {
1402 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
1403 key
->part
.ps
.epilog
.color_is_int10
= sctx
->framebuffer
.color_is_int10
;
1406 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1407 if (!key
->part
.ps
.epilog
.last_cbuf
) {
1408 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
1409 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
1410 key
->part
.ps
.epilog
.color_is_int10
&= sel
->info
.colors_written
;
1414 bool is_poly
= (sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES
&&
1415 sctx
->current_rast_prim
<= PIPE_PRIM_POLYGON
) ||
1416 sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES_ADJACENCY
;
1417 bool is_line
= !is_poly
&& sctx
->current_rast_prim
!= PIPE_PRIM_POINTS
;
1419 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
1420 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
1422 if (sctx
->queued
.named
.blend
) {
1423 key
->part
.ps
.epilog
.alpha_to_one
= sctx
->queued
.named
.blend
->alpha_to_one
&&
1424 rs
->multisample_enable
;
1427 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
1428 key
->part
.ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
1429 (is_line
&& rs
->line_smooth
)) &&
1430 sctx
->framebuffer
.nr_samples
<= 1;
1431 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
1433 if (sctx
->ps_iter_samples
> 1 &&
1434 sel
->info
.reads_samplemask
) {
1435 key
->part
.ps
.prolog
.samplemask_log_ps_iter
=
1436 util_logbase2(util_next_power_of_two(sctx
->ps_iter_samples
));
1439 if (rs
->force_persample_interp
&&
1440 rs
->multisample_enable
&&
1441 sctx
->framebuffer
.nr_samples
> 1 &&
1442 sctx
->ps_iter_samples
> 1) {
1443 key
->part
.ps
.prolog
.force_persp_sample_interp
=
1444 sel
->info
.uses_persp_center
||
1445 sel
->info
.uses_persp_centroid
;
1447 key
->part
.ps
.prolog
.force_linear_sample_interp
=
1448 sel
->info
.uses_linear_center
||
1449 sel
->info
.uses_linear_centroid
;
1450 } else if (rs
->multisample_enable
&&
1451 sctx
->framebuffer
.nr_samples
> 1) {
1452 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
1453 sel
->info
.uses_persp_center
&&
1454 sel
->info
.uses_persp_centroid
;
1455 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
1456 sel
->info
.uses_linear_center
&&
1457 sel
->info
.uses_linear_centroid
;
1459 /* Make sure SPI doesn't compute more than 1 pair
1460 * of (i,j), which is the optimization here. */
1461 key
->part
.ps
.prolog
.force_persp_center_interp
=
1462 sel
->info
.uses_persp_center
+
1463 sel
->info
.uses_persp_centroid
+
1464 sel
->info
.uses_persp_sample
> 1;
1466 key
->part
.ps
.prolog
.force_linear_center_interp
=
1467 sel
->info
.uses_linear_center
+
1468 sel
->info
.uses_linear_centroid
+
1469 sel
->info
.uses_linear_sample
> 1;
1471 if (sel
->info
.opcode_count
[TGSI_OPCODE_INTERP_SAMPLE
])
1472 key
->mono
.u
.ps
.interpolate_at_sample_force_center
= 1;
1476 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
1483 if (unlikely(sctx
->screen
->b
.debug_flags
& DBG(NO_OPT_VARIANT
)))
1484 memset(&key
->opt
, 0, sizeof(key
->opt
));
1487 static void si_build_shader_variant(struct si_shader
*shader
,
1491 struct si_shader_selector
*sel
= shader
->selector
;
1492 struct si_screen
*sscreen
= sel
->screen
;
1493 LLVMTargetMachineRef tm
;
1494 struct pipe_debug_callback
*debug
= &shader
->compiler_ctx_state
.debug
;
1497 if (thread_index
>= 0) {
1499 assert(thread_index
< ARRAY_SIZE(sscreen
->tm_low_priority
));
1500 tm
= sscreen
->tm_low_priority
[thread_index
];
1502 assert(thread_index
< ARRAY_SIZE(sscreen
->tm
));
1503 tm
= sscreen
->tm
[thread_index
];
1508 assert(!low_priority
);
1509 tm
= shader
->compiler_ctx_state
.tm
;
1512 r
= si_shader_create(sscreen
, tm
, shader
, debug
);
1514 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1516 shader
->compilation_failed
= true;
1520 if (shader
->compiler_ctx_state
.is_debug_context
) {
1521 FILE *f
= open_memstream(&shader
->shader_log
,
1522 &shader
->shader_log_size
);
1524 si_shader_dump(sscreen
, shader
, NULL
, sel
->type
, f
, false);
1529 si_shader_init_pm4_state(sscreen
, shader
);
1532 static void si_build_shader_variant_low_priority(void *job
, int thread_index
)
1534 struct si_shader
*shader
= (struct si_shader
*)job
;
1536 assert(thread_index
>= 0);
1538 si_build_shader_variant(shader
, thread_index
, true);
1541 static const struct si_shader_key zeroed
;
1543 static bool si_check_missing_main_part(struct si_screen
*sscreen
,
1544 struct si_shader_selector
*sel
,
1545 struct si_compiler_ctx_state
*compiler_state
,
1546 struct si_shader_key
*key
)
1548 struct si_shader
**mainp
= si_get_main_shader_part(sel
, key
);
1551 struct si_shader
*main_part
= CALLOC_STRUCT(si_shader
);
1556 /* We can leave the fence as permanently signaled because the
1557 * main part becomes visible globally only after it has been
1559 util_queue_fence_init(&main_part
->ready
);
1561 main_part
->selector
= sel
;
1562 main_part
->key
.as_es
= key
->as_es
;
1563 main_part
->key
.as_ls
= key
->as_ls
;
1565 if (si_compile_tgsi_shader(sscreen
, compiler_state
->tm
,
1567 &compiler_state
->debug
) != 0) {
1576 /* Select the hw shader variant depending on the current state. */
1577 static int si_shader_select_with_key(struct si_screen
*sscreen
,
1578 struct si_shader_ctx_state
*state
,
1579 struct si_compiler_ctx_state
*compiler_state
,
1580 struct si_shader_key
*key
,
1583 struct si_shader_selector
*sel
= state
->cso
;
1584 struct si_shader_selector
*previous_stage_sel
= NULL
;
1585 struct si_shader
*current
= state
->current
;
1586 struct si_shader
*iter
, *shader
= NULL
;
1589 /* Check if we don't need to change anything.
1590 * This path is also used for most shaders that don't need multiple
1591 * variants, it will cost just a computation of the key and this
1593 if (likely(current
&&
1594 memcmp(¤t
->key
, key
, sizeof(*key
)) == 0)) {
1595 if (unlikely(!util_queue_fence_is_signalled(¤t
->ready
))) {
1596 if (current
->is_optimized
) {
1597 memset(&key
->opt
, 0, sizeof(key
->opt
));
1598 goto current_not_ready
;
1601 util_queue_fence_wait(¤t
->ready
);
1604 return current
->compilation_failed
? -1 : 0;
1608 /* This must be done before the mutex is locked, because async GS
1609 * compilation calls this function too, and therefore must enter
1612 * Only wait if we are in a draw call. Don't wait if we are
1613 * in a compiler thread.
1615 if (thread_index
< 0)
1616 util_queue_fence_wait(&sel
->ready
);
1618 mtx_lock(&sel
->mutex
);
1620 /* Find the shader variant. */
1621 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
1622 /* Don't check the "current" shader. We checked it above. */
1623 if (current
!= iter
&&
1624 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
1625 mtx_unlock(&sel
->mutex
);
1627 if (unlikely(!util_queue_fence_is_signalled(&iter
->ready
))) {
1628 /* If it's an optimized shader and its compilation has
1629 * been started but isn't done, use the unoptimized
1630 * shader so as not to cause a stall due to compilation.
1632 if (iter
->is_optimized
) {
1633 memset(&key
->opt
, 0, sizeof(key
->opt
));
1637 util_queue_fence_wait(&iter
->ready
);
1640 if (iter
->compilation_failed
) {
1641 return -1; /* skip the draw call */
1644 state
->current
= iter
;
1649 /* Build a new shader. */
1650 shader
= CALLOC_STRUCT(si_shader
);
1652 mtx_unlock(&sel
->mutex
);
1656 util_queue_fence_init(&shader
->ready
);
1658 shader
->selector
= sel
;
1660 shader
->compiler_ctx_state
= *compiler_state
;
1662 /* If this is a merged shader, get the first shader's selector. */
1663 if (sscreen
->b
.chip_class
>= GFX9
) {
1664 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
1665 previous_stage_sel
= key
->part
.tcs
.ls
;
1666 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
1667 previous_stage_sel
= key
->part
.gs
.es
;
1669 /* We need to wait for the previous shader. */
1670 if (previous_stage_sel
&& thread_index
< 0)
1671 util_queue_fence_wait(&previous_stage_sel
->ready
);
1674 /* Compile the main shader part if it doesn't exist. This can happen
1675 * if the initial guess was wrong. */
1676 bool is_pure_monolithic
=
1677 sscreen
->use_monolithic_shaders
||
1678 memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
1680 if (!is_pure_monolithic
) {
1683 /* Make sure the main shader part is present. This is needed
1684 * for shaders that can be compiled as VS, LS, or ES, and only
1685 * one of them is compiled at creation.
1687 * For merged shaders, check that the starting shader's main
1690 if (previous_stage_sel
) {
1691 struct si_shader_key shader1_key
= zeroed
;
1693 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
1694 shader1_key
.as_ls
= 1;
1695 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
1696 shader1_key
.as_es
= 1;
1700 mtx_lock(&previous_stage_sel
->mutex
);
1701 ok
= si_check_missing_main_part(sscreen
,
1703 compiler_state
, &shader1_key
);
1704 mtx_unlock(&previous_stage_sel
->mutex
);
1706 ok
= si_check_missing_main_part(sscreen
, sel
,
1707 compiler_state
, key
);
1711 mtx_unlock(&sel
->mutex
);
1712 return -ENOMEM
; /* skip the draw call */
1716 /* Keep the reference to the 1st shader of merged shaders, so that
1717 * Gallium can't destroy it before we destroy the 2nd shader.
1719 * Set sctx = NULL, because it's unused if we're not releasing
1720 * the shader, and we don't have any sctx here.
1722 si_shader_selector_reference(NULL
, &shader
->previous_stage_sel
,
1723 previous_stage_sel
);
1725 /* Monolithic-only shaders don't make a distinction between optimized
1726 * and unoptimized. */
1727 shader
->is_monolithic
=
1728 is_pure_monolithic
||
1729 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1731 shader
->is_optimized
=
1732 !is_pure_monolithic
&&
1733 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1735 /* If it's an optimized shader, compile it asynchronously. */
1736 if (shader
->is_optimized
&&
1737 !is_pure_monolithic
&&
1739 /* Compile it asynchronously. */
1740 util_queue_add_job(&sscreen
->shader_compiler_queue_low_priority
,
1741 shader
, &shader
->ready
,
1742 si_build_shader_variant_low_priority
, NULL
);
1744 /* Add only after the ready fence was reset, to guard against a
1745 * race with si_bind_XX_shader. */
1746 if (!sel
->last_variant
) {
1747 sel
->first_variant
= shader
;
1748 sel
->last_variant
= shader
;
1750 sel
->last_variant
->next_variant
= shader
;
1751 sel
->last_variant
= shader
;
1754 /* Use the default (unoptimized) shader for now. */
1755 memset(&key
->opt
, 0, sizeof(key
->opt
));
1756 mtx_unlock(&sel
->mutex
);
1760 /* Reset the fence before adding to the variant list. */
1761 util_queue_fence_reset(&shader
->ready
);
1763 if (!sel
->last_variant
) {
1764 sel
->first_variant
= shader
;
1765 sel
->last_variant
= shader
;
1767 sel
->last_variant
->next_variant
= shader
;
1768 sel
->last_variant
= shader
;
1771 mtx_unlock(&sel
->mutex
);
1773 assert(!shader
->is_optimized
);
1774 si_build_shader_variant(shader
, thread_index
, false);
1776 util_queue_fence_signal(&shader
->ready
);
1778 if (!shader
->compilation_failed
)
1779 state
->current
= shader
;
1781 return shader
->compilation_failed
? -1 : 0;
1784 static int si_shader_select(struct pipe_context
*ctx
,
1785 struct si_shader_ctx_state
*state
,
1786 struct si_compiler_ctx_state
*compiler_state
)
1788 struct si_context
*sctx
= (struct si_context
*)ctx
;
1789 struct si_shader_key key
;
1791 si_shader_selector_key(ctx
, state
->cso
, &key
);
1792 return si_shader_select_with_key(sctx
->screen
, state
, compiler_state
,
1796 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
1798 struct si_shader_key
*key
)
1800 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
1802 switch (info
->processor
) {
1803 case PIPE_SHADER_VERTEX
:
1804 switch (next_shader
) {
1805 case PIPE_SHADER_GEOMETRY
:
1808 case PIPE_SHADER_TESS_CTRL
:
1809 case PIPE_SHADER_TESS_EVAL
:
1813 /* If POSITION isn't written, it can only be a HW VS
1814 * if streamout is used. If streamout isn't used,
1815 * assume that it's a HW LS. (the next shader is TCS)
1816 * This heuristic is needed for separate shader objects.
1818 if (!info
->writes_position
&& !streamout
)
1823 case PIPE_SHADER_TESS_EVAL
:
1824 if (next_shader
== PIPE_SHADER_GEOMETRY
||
1825 !info
->writes_position
)
1832 * Compile the main shader part or the monolithic shader as part of
1833 * si_shader_selector initialization. Since it can be done asynchronously,
1834 * there is no way to report compile failures to applications.
1836 static void si_init_shader_selector_async(void *job
, int thread_index
)
1838 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
1839 struct si_screen
*sscreen
= sel
->screen
;
1840 LLVMTargetMachineRef tm
;
1841 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
1844 assert(!debug
->debug_message
|| debug
->async
);
1845 assert(thread_index
>= 0);
1846 assert(thread_index
< ARRAY_SIZE(sscreen
->tm
));
1847 tm
= sscreen
->tm
[thread_index
];
1849 /* Compile the main shader part for use with a prolog and/or epilog.
1850 * If this fails, the driver will try to compile a monolithic shader
1853 if (!sscreen
->use_monolithic_shaders
) {
1854 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
1855 void *tgsi_binary
= NULL
;
1858 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
1862 /* We can leave the fence signaled because use of the default
1863 * main part is guarded by the selector's ready fence. */
1864 util_queue_fence_init(&shader
->ready
);
1866 shader
->selector
= sel
;
1867 si_parse_next_shader_property(&sel
->info
,
1868 sel
->so
.num_outputs
!= 0,
1872 tgsi_binary
= si_get_tgsi_binary(sel
);
1874 /* Try to load the shader from the shader cache. */
1875 mtx_lock(&sscreen
->shader_cache_mutex
);
1878 si_shader_cache_load_shader(sscreen
, tgsi_binary
, shader
)) {
1879 mtx_unlock(&sscreen
->shader_cache_mutex
);
1881 mtx_unlock(&sscreen
->shader_cache_mutex
);
1883 /* Compile the shader if it hasn't been loaded from the cache. */
1884 if (si_compile_tgsi_shader(sscreen
, tm
, shader
, false,
1888 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
1893 mtx_lock(&sscreen
->shader_cache_mutex
);
1894 if (!si_shader_cache_insert_shader(sscreen
, tgsi_binary
, shader
, true))
1896 mtx_unlock(&sscreen
->shader_cache_mutex
);
1900 *si_get_main_shader_part(sel
, &shader
->key
) = shader
;
1902 /* Unset "outputs_written" flags for outputs converted to
1903 * DEFAULT_VAL, so that later inter-shader optimizations don't
1904 * try to eliminate outputs that don't exist in the final
1907 * This is only done if non-monolithic shaders are enabled.
1909 if ((sel
->type
== PIPE_SHADER_VERTEX
||
1910 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
1911 !shader
->key
.as_ls
&&
1912 !shader
->key
.as_es
) {
1915 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
1916 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
1918 if (offset
<= AC_EXP_PARAM_OFFSET_31
)
1921 unsigned name
= sel
->info
.output_semantic_name
[i
];
1922 unsigned index
= sel
->info
.output_semantic_index
[i
];
1926 case TGSI_SEMANTIC_GENERIC
:
1927 /* don't process indices the function can't handle */
1928 if (index
>= SI_MAX_IO_GENERIC
)
1932 id
= si_shader_io_get_unique_index(name
, index
);
1933 sel
->outputs_written
&= ~(1ull << id
);
1935 case TGSI_SEMANTIC_POSITION
: /* ignore these */
1936 case TGSI_SEMANTIC_PSIZE
:
1937 case TGSI_SEMANTIC_CLIPVERTEX
:
1938 case TGSI_SEMANTIC_EDGEFLAG
:
1945 /* Pre-compilation. */
1946 if (sscreen
->b
.debug_flags
& DBG(PRECOMPILE
) &&
1947 /* GFX9 needs LS or ES for compilation, which we don't have here. */
1948 (sscreen
->b
.chip_class
<= VI
||
1949 (sel
->type
!= PIPE_SHADER_TESS_CTRL
&&
1950 sel
->type
!= PIPE_SHADER_GEOMETRY
))) {
1951 struct si_shader_ctx_state state
= {sel
};
1952 struct si_shader_key key
;
1954 memset(&key
, 0, sizeof(key
));
1955 si_parse_next_shader_property(&sel
->info
,
1956 sel
->so
.num_outputs
!= 0,
1959 /* GFX9 doesn't have LS and ES. */
1960 if (sscreen
->b
.chip_class
>= GFX9
) {
1965 /* Set reasonable defaults, so that the shader key doesn't
1966 * cause any code to be eliminated.
1968 switch (sel
->type
) {
1969 case PIPE_SHADER_TESS_CTRL
:
1970 key
.part
.tcs
.epilog
.prim_mode
= PIPE_PRIM_TRIANGLES
;
1972 case PIPE_SHADER_FRAGMENT
:
1973 key
.part
.ps
.prolog
.bc_optimize_for_persp
=
1974 sel
->info
.uses_persp_center
&&
1975 sel
->info
.uses_persp_centroid
;
1976 key
.part
.ps
.prolog
.bc_optimize_for_linear
=
1977 sel
->info
.uses_linear_center
&&
1978 sel
->info
.uses_linear_centroid
;
1979 key
.part
.ps
.epilog
.alpha_func
= PIPE_FUNC_ALWAYS
;
1980 for (i
= 0; i
< 8; i
++)
1981 if (sel
->info
.colors_written
& (1 << i
))
1982 key
.part
.ps
.epilog
.spi_shader_col_format
|=
1983 V_028710_SPI_SHADER_FP16_ABGR
<< (i
* 4);
1987 if (si_shader_select_with_key(sscreen
, &state
,
1988 &sel
->compiler_ctx_state
, &key
,
1990 fprintf(stderr
, "radeonsi: can't create a monolithic shader\n");
1993 /* The GS copy shader is always pre-compiled. */
1994 if (sel
->type
== PIPE_SHADER_GEOMETRY
) {
1995 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, tm
, sel
, debug
);
1996 if (!sel
->gs_copy_shader
) {
1997 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
2001 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
2005 /* Return descriptor slot usage masks from the given shader info. */
2006 void si_get_active_slot_masks(const struct tgsi_shader_info
*info
,
2007 uint32_t *const_and_shader_buffers
,
2008 uint64_t *samplers_and_images
)
2010 unsigned start
, num_shaderbufs
, num_constbufs
, num_images
, num_samplers
;
2012 num_shaderbufs
= util_last_bit(info
->shader_buffers_declared
);
2013 num_constbufs
= util_last_bit(info
->const_buffers_declared
);
2014 /* two 8-byte images share one 16-byte slot */
2015 num_images
= align(util_last_bit(info
->images_declared
), 2);
2016 num_samplers
= util_last_bit(info
->samplers_declared
);
2018 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2019 start
= si_get_shaderbuf_slot(num_shaderbufs
- 1);
2020 *const_and_shader_buffers
=
2021 u_bit_consecutive(start
, num_shaderbufs
+ num_constbufs
);
2023 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2024 start
= si_get_image_slot(num_images
- 1) / 2;
2025 *samplers_and_images
=
2026 u_bit_consecutive64(start
, num_images
/ 2 + num_samplers
);
2029 static void *si_create_shader_selector(struct pipe_context
*ctx
,
2030 const struct pipe_shader_state
*state
)
2032 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
2033 struct si_context
*sctx
= (struct si_context
*)ctx
;
2034 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
2040 pipe_reference_init(&sel
->reference
, 1);
2041 sel
->screen
= sscreen
;
2042 sel
->compiler_ctx_state
.debug
= sctx
->debug
;
2043 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
2045 sel
->so
= state
->stream_output
;
2047 if (state
->type
== PIPE_SHADER_IR_TGSI
) {
2048 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
2054 tgsi_scan_shader(state
->tokens
, &sel
->info
);
2055 tgsi_scan_tess_ctrl(state
->tokens
, &sel
->info
, &sel
->tcs_info
);
2057 assert(state
->type
== PIPE_SHADER_IR_NIR
);
2059 sel
->nir
= state
->ir
.nir
;
2061 si_nir_scan_shader(sel
->nir
, &sel
->info
);
2066 sel
->type
= sel
->info
.processor
;
2067 p_atomic_inc(&sscreen
->b
.num_shaders_created
);
2068 si_get_active_slot_masks(&sel
->info
,
2069 &sel
->active_const_and_shader_buffers
,
2070 &sel
->active_samplers_and_images
);
2072 /* Record which streamout buffers are enabled. */
2073 for (i
= 0; i
< sel
->so
.num_outputs
; i
++) {
2074 sel
->enabled_streamout_buffer_mask
|=
2075 (1 << sel
->so
.output
[i
].output_buffer
) <<
2076 (sel
->so
.output
[i
].stream
* 4);
2079 /* The prolog is a no-op if there are no inputs. */
2080 sel
->vs_needs_prolog
= sel
->type
== PIPE_SHADER_VERTEX
&&
2081 sel
->info
.num_inputs
&&
2082 !sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
2084 sel
->force_correct_derivs_after_kill
=
2085 sel
->type
== PIPE_SHADER_FRAGMENT
&&
2086 sel
->info
.uses_derivatives
&&
2087 sel
->info
.uses_kill
&&
2088 sctx
->screen
->b
.debug_flags
& DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
2090 /* Set which opcode uses which (i,j) pair. */
2091 if (sel
->info
.uses_persp_opcode_interp_centroid
)
2092 sel
->info
.uses_persp_centroid
= true;
2094 if (sel
->info
.uses_linear_opcode_interp_centroid
)
2095 sel
->info
.uses_linear_centroid
= true;
2097 if (sel
->info
.uses_persp_opcode_interp_offset
||
2098 sel
->info
.uses_persp_opcode_interp_sample
)
2099 sel
->info
.uses_persp_center
= true;
2101 if (sel
->info
.uses_linear_opcode_interp_offset
||
2102 sel
->info
.uses_linear_opcode_interp_sample
)
2103 sel
->info
.uses_linear_center
= true;
2105 switch (sel
->type
) {
2106 case PIPE_SHADER_GEOMETRY
:
2107 sel
->gs_output_prim
=
2108 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
2109 sel
->gs_max_out_vertices
=
2110 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
2111 sel
->gs_num_invocations
=
2112 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
2113 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
2114 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
2115 sel
->gs_max_out_vertices
;
2117 sel
->max_gs_stream
= 0;
2118 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
2119 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
2120 sel
->so
.output
[i
].stream
);
2122 sel
->gs_input_verts_per_prim
=
2123 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
2126 case PIPE_SHADER_TESS_CTRL
:
2127 /* Always reserve space for these. */
2128 sel
->patch_outputs_written
|=
2129 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0)) |
2130 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0));
2132 case PIPE_SHADER_VERTEX
:
2133 case PIPE_SHADER_TESS_EVAL
:
2134 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2135 unsigned name
= sel
->info
.output_semantic_name
[i
];
2136 unsigned index
= sel
->info
.output_semantic_index
[i
];
2139 case TGSI_SEMANTIC_TESSINNER
:
2140 case TGSI_SEMANTIC_TESSOUTER
:
2141 case TGSI_SEMANTIC_PATCH
:
2142 sel
->patch_outputs_written
|=
2143 1ull << si_shader_io_get_unique_index_patch(name
, index
);
2146 case TGSI_SEMANTIC_GENERIC
:
2147 /* don't process indices the function can't handle */
2148 if (index
>= SI_MAX_IO_GENERIC
)
2152 sel
->outputs_written
|=
2153 1ull << si_shader_io_get_unique_index(name
, index
);
2155 case TGSI_SEMANTIC_CLIPVERTEX
: /* ignore these */
2156 case TGSI_SEMANTIC_EDGEFLAG
:
2160 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
2162 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2163 * conflicts, i.e. each vertex will start at a different bank.
2165 if (sctx
->b
.chip_class
>= GFX9
)
2166 sel
->esgs_itemsize
+= 4;
2169 case PIPE_SHADER_FRAGMENT
:
2170 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2171 unsigned name
= sel
->info
.input_semantic_name
[i
];
2172 unsigned index
= sel
->info
.input_semantic_index
[i
];
2175 case TGSI_SEMANTIC_GENERIC
:
2176 /* don't process indices the function can't handle */
2177 if (index
>= SI_MAX_IO_GENERIC
)
2182 1ull << si_shader_io_get_unique_index(name
, index
);
2184 case TGSI_SEMANTIC_PCOORD
: /* ignore this */
2189 for (i
= 0; i
< 8; i
++)
2190 if (sel
->info
.colors_written
& (1 << i
))
2191 sel
->colors_written_4bit
|= 0xf << (4 * i
);
2193 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2194 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
2195 int index
= sel
->info
.input_semantic_index
[i
];
2196 sel
->color_attr_index
[index
] = i
;
2202 /* PA_CL_VS_OUT_CNTL */
2204 sel
->info
.writes_psize
|| sel
->info
.writes_edgeflag
||
2205 sel
->info
.writes_layer
|| sel
->info
.writes_viewport_index
;
2206 sel
->pa_cl_vs_out_cntl
=
2207 S_02881C_USE_VTX_POINT_SIZE(sel
->info
.writes_psize
) |
2208 S_02881C_USE_VTX_EDGE_FLAG(sel
->info
.writes_edgeflag
) |
2209 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel
->info
.writes_layer
) |
2210 S_02881C_USE_VTX_VIEWPORT_INDX(sel
->info
.writes_viewport_index
) |
2211 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
2212 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
);
2213 sel
->clipdist_mask
= sel
->info
.writes_clipvertex
?
2214 SIX_BITS
: sel
->info
.clipdist_writemask
;
2215 sel
->culldist_mask
= sel
->info
.culldist_writemask
<<
2216 sel
->info
.num_written_clipdistance
;
2218 /* DB_SHADER_CONTROL */
2219 sel
->db_shader_control
=
2220 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
2221 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
2222 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
2223 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
2225 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
2226 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2227 sel
->db_shader_control
|=
2228 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2230 case TGSI_FS_DEPTH_LAYOUT_LESS
:
2231 sel
->db_shader_control
|=
2232 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2236 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2238 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2239 * --|-----------|------------|------------|--------------------|-------------------|-------------
2240 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2241 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2242 * 2 | false | true | n/a | LateZ | 1 | 0
2243 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2244 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2246 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2247 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2249 * Don't use ReZ without profiling !!!
2251 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2254 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
2256 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
2257 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
2258 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
2259 } else if (sel
->info
.writes_memory
) {
2261 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) |
2262 S_02880C_EXEC_ON_HIER_FAIL(1);
2265 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2268 (void) mtx_init(&sel
->mutex
, mtx_plain
);
2269 util_queue_fence_init(&sel
->ready
);
2271 struct util_async_debug_callback async_debug
;
2273 (sctx
->debug
.debug_message
&& !sctx
->debug
.async
) ||
2275 si_can_dump_shader(sscreen
, sel
->info
.processor
);
2278 u_async_debug_init(&async_debug
);
2279 sel
->compiler_ctx_state
.debug
= async_debug
.base
;
2282 util_queue_add_job(&sscreen
->shader_compiler_queue
, sel
,
2283 &sel
->ready
, si_init_shader_selector_async
,
2287 util_queue_fence_wait(&sel
->ready
);
2288 u_async_debug_drain(&async_debug
, &sctx
->debug
);
2289 u_async_debug_cleanup(&async_debug
);
2295 static void si_update_streamout_state(struct si_context
*sctx
)
2297 struct si_shader_selector
*shader_with_so
= si_get_vs(sctx
)->cso
;
2299 if (!shader_with_so
)
2302 sctx
->streamout
.enabled_stream_buffers_mask
=
2303 shader_with_so
->enabled_streamout_buffer_mask
;
2304 sctx
->streamout
.stride_in_dw
= shader_with_so
->so
.stride
;
2307 static void si_update_clip_regs(struct si_context
*sctx
,
2308 struct si_shader_selector
*old_hw_vs
,
2309 struct si_shader
*old_hw_vs_variant
,
2310 struct si_shader_selector
*next_hw_vs
,
2311 struct si_shader
*next_hw_vs_variant
)
2315 old_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] !=
2316 next_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] ||
2317 old_hw_vs
->pa_cl_vs_out_cntl
!= next_hw_vs
->pa_cl_vs_out_cntl
||
2318 old_hw_vs
->clipdist_mask
!= next_hw_vs
->clipdist_mask
||
2319 old_hw_vs
->culldist_mask
!= next_hw_vs
->culldist_mask
||
2320 !old_hw_vs_variant
||
2321 !next_hw_vs_variant
||
2322 old_hw_vs_variant
->key
.opt
.clip_disable
!=
2323 next_hw_vs_variant
->key
.opt
.clip_disable
))
2324 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
2327 static void si_update_common_shader_state(struct si_context
*sctx
)
2329 sctx
->uses_bindless_samplers
=
2330 si_shader_uses_bindless_samplers(sctx
->vs_shader
.cso
) ||
2331 si_shader_uses_bindless_samplers(sctx
->gs_shader
.cso
) ||
2332 si_shader_uses_bindless_samplers(sctx
->ps_shader
.cso
) ||
2333 si_shader_uses_bindless_samplers(sctx
->tcs_shader
.cso
) ||
2334 si_shader_uses_bindless_samplers(sctx
->tes_shader
.cso
);
2335 sctx
->uses_bindless_images
=
2336 si_shader_uses_bindless_images(sctx
->vs_shader
.cso
) ||
2337 si_shader_uses_bindless_images(sctx
->gs_shader
.cso
) ||
2338 si_shader_uses_bindless_images(sctx
->ps_shader
.cso
) ||
2339 si_shader_uses_bindless_images(sctx
->tcs_shader
.cso
) ||
2340 si_shader_uses_bindless_images(sctx
->tes_shader
.cso
);
2341 sctx
->do_update_shaders
= true;
2344 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
2346 struct si_context
*sctx
= (struct si_context
*)ctx
;
2347 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2348 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2349 struct si_shader_selector
*sel
= state
;
2351 if (sctx
->vs_shader
.cso
== sel
)
2354 sctx
->vs_shader
.cso
= sel
;
2355 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2356 sctx
->num_vs_blit_sgprs
= sel
? sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
] : 0;
2358 si_update_common_shader_state(sctx
);
2359 si_update_vs_viewport_state(sctx
);
2360 si_set_active_descriptors_for_shader(sctx
, sel
);
2361 si_update_streamout_state(sctx
);
2362 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2363 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2366 static void si_update_tess_uses_prim_id(struct si_context
*sctx
)
2368 sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
=
2369 (sctx
->tes_shader
.cso
&&
2370 sctx
->tes_shader
.cso
->info
.uses_primid
) ||
2371 (sctx
->tcs_shader
.cso
&&
2372 sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
2373 (sctx
->gs_shader
.cso
&&
2374 sctx
->gs_shader
.cso
->info
.uses_primid
) ||
2375 (sctx
->ps_shader
.cso
&& !sctx
->gs_shader
.cso
&&
2376 sctx
->ps_shader
.cso
->info
.uses_primid
);
2379 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
2381 struct si_context
*sctx
= (struct si_context
*)ctx
;
2382 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2383 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2384 struct si_shader_selector
*sel
= state
;
2385 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
2387 if (sctx
->gs_shader
.cso
== sel
)
2390 sctx
->gs_shader
.cso
= sel
;
2391 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2392 sctx
->ia_multi_vgt_param_key
.u
.uses_gs
= sel
!= NULL
;
2394 si_update_common_shader_state(sctx
);
2395 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2397 if (enable_changed
) {
2398 si_shader_change_notify(sctx
);
2399 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2400 si_update_tess_uses_prim_id(sctx
);
2402 si_update_vs_viewport_state(sctx
);
2403 si_set_active_descriptors_for_shader(sctx
, sel
);
2404 si_update_streamout_state(sctx
);
2405 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2406 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2409 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
2411 struct si_context
*sctx
= (struct si_context
*)ctx
;
2412 struct si_shader_selector
*sel
= state
;
2413 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
2415 if (sctx
->tcs_shader
.cso
== sel
)
2418 sctx
->tcs_shader
.cso
= sel
;
2419 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2420 si_update_tess_uses_prim_id(sctx
);
2422 si_update_common_shader_state(sctx
);
2425 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
2427 si_set_active_descriptors_for_shader(sctx
, sel
);
2430 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
2432 struct si_context
*sctx
= (struct si_context
*)ctx
;
2433 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2434 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2435 struct si_shader_selector
*sel
= state
;
2436 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
2438 if (sctx
->tes_shader
.cso
== sel
)
2441 sctx
->tes_shader
.cso
= sel
;
2442 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
2443 sctx
->ia_multi_vgt_param_key
.u
.uses_tess
= sel
!= NULL
;
2444 si_update_tess_uses_prim_id(sctx
);
2446 si_update_common_shader_state(sctx
);
2447 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2449 if (enable_changed
) {
2450 si_shader_change_notify(sctx
);
2451 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
2453 si_update_vs_viewport_state(sctx
);
2454 si_set_active_descriptors_for_shader(sctx
, sel
);
2455 si_update_streamout_state(sctx
);
2456 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2457 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2460 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
2462 struct si_context
*sctx
= (struct si_context
*)ctx
;
2463 struct si_shader_selector
*old_sel
= sctx
->ps_shader
.cso
;
2464 struct si_shader_selector
*sel
= state
;
2466 /* skip if supplied shader is one already in use */
2470 sctx
->ps_shader
.cso
= sel
;
2471 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
2473 si_update_common_shader_state(sctx
);
2475 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2476 si_update_tess_uses_prim_id(sctx
);
2479 old_sel
->info
.colors_written
!= sel
->info
.colors_written
)
2480 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
2482 if (sctx
->screen
->has_out_of_order_rast
&&
2484 old_sel
->info
.writes_memory
!= sel
->info
.writes_memory
||
2485 old_sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] !=
2486 sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]))
2487 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2489 si_set_active_descriptors_for_shader(sctx
, sel
);
2492 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
2494 if (shader
->is_optimized
) {
2495 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue_low_priority
,
2499 util_queue_fence_destroy(&shader
->ready
);
2502 switch (shader
->selector
->type
) {
2503 case PIPE_SHADER_VERTEX
:
2504 if (shader
->key
.as_ls
) {
2505 assert(sctx
->b
.chip_class
<= VI
);
2506 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
2507 } else if (shader
->key
.as_es
) {
2508 assert(sctx
->b
.chip_class
<= VI
);
2509 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2511 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2514 case PIPE_SHADER_TESS_CTRL
:
2515 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
2517 case PIPE_SHADER_TESS_EVAL
:
2518 if (shader
->key
.as_es
) {
2519 assert(sctx
->b
.chip_class
<= VI
);
2520 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2522 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2525 case PIPE_SHADER_GEOMETRY
:
2526 if (shader
->is_gs_copy_shader
)
2527 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2529 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
2531 case PIPE_SHADER_FRAGMENT
:
2532 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
2537 si_shader_selector_reference(sctx
, &shader
->previous_stage_sel
, NULL
);
2538 si_shader_destroy(shader
);
2542 void si_destroy_shader_selector(struct si_context
*sctx
,
2543 struct si_shader_selector
*sel
)
2545 struct si_shader
*p
= sel
->first_variant
, *c
;
2546 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
2547 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
2548 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
2549 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
2550 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
2551 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
2554 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue
, &sel
->ready
);
2556 if (current_shader
[sel
->type
]->cso
== sel
) {
2557 current_shader
[sel
->type
]->cso
= NULL
;
2558 current_shader
[sel
->type
]->current
= NULL
;
2562 c
= p
->next_variant
;
2563 si_delete_shader(sctx
, p
);
2567 if (sel
->main_shader_part
)
2568 si_delete_shader(sctx
, sel
->main_shader_part
);
2569 if (sel
->main_shader_part_ls
)
2570 si_delete_shader(sctx
, sel
->main_shader_part_ls
);
2571 if (sel
->main_shader_part_es
)
2572 si_delete_shader(sctx
, sel
->main_shader_part_es
);
2573 if (sel
->gs_copy_shader
)
2574 si_delete_shader(sctx
, sel
->gs_copy_shader
);
2576 util_queue_fence_destroy(&sel
->ready
);
2577 mtx_destroy(&sel
->mutex
);
2579 ralloc_free(sel
->nir
);
2583 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
2585 struct si_context
*sctx
= (struct si_context
*)ctx
;
2586 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
2588 si_shader_selector_reference(sctx
, &sel
, NULL
);
2591 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
2592 struct si_shader
*vs
, unsigned name
,
2593 unsigned index
, unsigned interpolate
)
2595 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
2596 unsigned j
, offset
, ps_input_cntl
= 0;
2598 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2599 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
))
2600 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
2602 if (name
== TGSI_SEMANTIC_PCOORD
||
2603 (name
== TGSI_SEMANTIC_TEXCOORD
&&
2604 sctx
->sprite_coord_enable
& (1 << index
))) {
2605 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
2608 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
2609 if (name
== vsinfo
->output_semantic_name
[j
] &&
2610 index
== vsinfo
->output_semantic_index
[j
]) {
2611 offset
= vs
->info
.vs_output_param_offset
[j
];
2613 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
2614 /* The input is loaded from parameter memory. */
2615 ps_input_cntl
|= S_028644_OFFSET(offset
);
2616 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2617 if (offset
== AC_EXP_PARAM_UNDEFINED
) {
2618 /* This can happen with depth-only rendering. */
2621 /* The input is a DEFAULT_VAL constant. */
2622 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
2623 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
2624 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
2627 ps_input_cntl
= S_028644_OFFSET(0x20) |
2628 S_028644_DEFAULT_VAL(offset
);
2634 if (name
== TGSI_SEMANTIC_PRIMID
)
2635 /* PrimID is written after the last output. */
2636 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
2637 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2638 /* No corresponding output found, load defaults into input.
2639 * Don't set any other bits.
2640 * (FLAT_SHADE=1 completely changes behavior) */
2641 ps_input_cntl
= S_028644_OFFSET(0x20);
2642 /* D3D 9 behaviour. GL is undefined */
2643 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
2644 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
2646 return ps_input_cntl
;
2649 static void si_emit_spi_map(struct si_context
*sctx
, struct r600_atom
*atom
)
2651 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2652 struct si_shader
*ps
= sctx
->ps_shader
.current
;
2653 struct si_shader
*vs
= si_get_vs_state(sctx
);
2654 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
2655 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
2657 if (!ps
|| !ps
->selector
->info
.num_inputs
)
2660 num_interp
= si_get_ps_num_interp(ps
);
2661 assert(num_interp
> 0);
2662 radeon_set_context_reg_seq(cs
, R_028644_SPI_PS_INPUT_CNTL_0
, num_interp
);
2664 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
2665 unsigned name
= psinfo
->input_semantic_name
[i
];
2666 unsigned index
= psinfo
->input_semantic_index
[i
];
2667 unsigned interpolate
= psinfo
->input_interpolate
[i
];
2669 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, name
, index
,
2673 if (name
== TGSI_SEMANTIC_COLOR
) {
2674 assert(index
< ARRAY_SIZE(bcol_interp
));
2675 bcol_interp
[index
] = interpolate
;
2679 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
2680 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
2682 for (i
= 0; i
< 2; i
++) {
2683 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
2686 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, bcol
,
2687 i
, bcol_interp
[i
]));
2691 assert(num_interp
== num_written
);
2695 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2697 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
2699 if (sctx
->init_config_has_vgt_flush
)
2702 /* Done by Vulkan before VGT_FLUSH. */
2703 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2704 si_pm4_cmd_add(sctx
->init_config
,
2705 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2706 si_pm4_cmd_end(sctx
->init_config
, false);
2708 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2709 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2710 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
2711 si_pm4_cmd_end(sctx
->init_config
, false);
2712 sctx
->init_config_has_vgt_flush
= true;
2715 /* Initialize state related to ESGS / GSVS ring buffers */
2716 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
2718 struct si_shader_selector
*es
=
2719 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
2720 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
2721 struct si_pm4_state
*pm4
;
2723 /* Chip constants. */
2724 unsigned num_se
= sctx
->screen
->b
.info
.max_se
;
2725 unsigned wave_size
= 64;
2726 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
2727 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2728 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2730 unsigned gs_vertex_reuse
= (sctx
->b
.chip_class
>= VI
? 32 : 16) * num_se
;
2731 unsigned alignment
= 256 * num_se
;
2732 /* The maximum size is 63.999 MB per SE. */
2733 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
2735 /* Calculate the minimum size. */
2736 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
2737 wave_size
, alignment
);
2739 /* These are recommended sizes, not minimum sizes. */
2740 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
2741 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
2742 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
2743 gs
->max_gsvs_emit_size
;
2745 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
2746 esgs_ring_size
= align(esgs_ring_size
, alignment
);
2747 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
2749 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
2750 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
2752 /* Some rings don't have to be allocated if shaders don't use them.
2753 * (e.g. no varyings between ES and GS or GS and VS)
2755 * GFX9 doesn't have the ESGS ring.
2757 bool update_esgs
= sctx
->b
.chip_class
<= VI
&&
2759 (!sctx
->esgs_ring
||
2760 sctx
->esgs_ring
->width0
< esgs_ring_size
);
2761 bool update_gsvs
= gsvs_ring_size
&&
2762 (!sctx
->gsvs_ring
||
2763 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
2765 if (!update_esgs
&& !update_gsvs
)
2769 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
2771 si_aligned_buffer_create(sctx
->b
.b
.screen
,
2772 R600_RESOURCE_FLAG_UNMAPPABLE
,
2774 esgs_ring_size
, alignment
);
2775 if (!sctx
->esgs_ring
)
2780 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
2782 si_aligned_buffer_create(sctx
->b
.b
.screen
,
2783 R600_RESOURCE_FLAG_UNMAPPABLE
,
2785 gsvs_ring_size
, alignment
);
2786 if (!sctx
->gsvs_ring
)
2790 /* Create the "init_config_gs_rings" state. */
2791 pm4
= CALLOC_STRUCT(si_pm4_state
);
2795 if (sctx
->b
.chip_class
>= CIK
) {
2796 if (sctx
->esgs_ring
) {
2797 assert(sctx
->b
.chip_class
<= VI
);
2798 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
2799 sctx
->esgs_ring
->width0
/ 256);
2801 if (sctx
->gsvs_ring
)
2802 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
2803 sctx
->gsvs_ring
->width0
/ 256);
2805 if (sctx
->esgs_ring
)
2806 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
2807 sctx
->esgs_ring
->width0
/ 256);
2808 if (sctx
->gsvs_ring
)
2809 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
2810 sctx
->gsvs_ring
->width0
/ 256);
2813 /* Set the state. */
2814 if (sctx
->init_config_gs_rings
)
2815 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
2816 sctx
->init_config_gs_rings
= pm4
;
2818 if (!sctx
->init_config_has_vgt_flush
) {
2819 si_init_config_add_vgt_flush(sctx
);
2820 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
2823 /* Flush the context to re-emit both init_config states. */
2824 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
2825 si_context_gfx_flush(sctx
, RADEON_FLUSH_ASYNC
, NULL
);
2827 /* Set ring bindings. */
2828 if (sctx
->esgs_ring
) {
2829 assert(sctx
->b
.chip_class
<= VI
);
2830 si_set_ring_buffer(&sctx
->b
.b
, SI_ES_RING_ESGS
,
2831 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
2832 true, true, 4, 64, 0);
2833 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_ESGS
,
2834 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
2835 false, false, 0, 0, 0);
2837 if (sctx
->gsvs_ring
) {
2838 si_set_ring_buffer(&sctx
->b
.b
, SI_RING_GSVS
,
2839 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
2840 false, false, 0, 0, 0);
2846 static void si_shader_lock(struct si_shader
*shader
)
2848 mtx_lock(&shader
->selector
->mutex
);
2849 if (shader
->previous_stage_sel
) {
2850 assert(shader
->previous_stage_sel
!= shader
->selector
);
2851 mtx_lock(&shader
->previous_stage_sel
->mutex
);
2855 static void si_shader_unlock(struct si_shader
*shader
)
2857 if (shader
->previous_stage_sel
)
2858 mtx_unlock(&shader
->previous_stage_sel
->mutex
);
2859 mtx_unlock(&shader
->selector
->mutex
);
2863 * @returns 1 if \p sel has been updated to use a new scratch buffer
2865 * < 0 if there was a failure
2867 static int si_update_scratch_buffer(struct si_context
*sctx
,
2868 struct si_shader
*shader
)
2870 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
2876 /* This shader doesn't need a scratch buffer */
2877 if (shader
->config
.scratch_bytes_per_wave
== 0)
2880 /* Prevent race conditions when updating:
2881 * - si_shader::scratch_bo
2882 * - si_shader::binary::code
2883 * - si_shader::previous_stage::binary::code.
2885 si_shader_lock(shader
);
2887 /* This shader is already configured to use the current
2888 * scratch buffer. */
2889 if (shader
->scratch_bo
== sctx
->scratch_buffer
) {
2890 si_shader_unlock(shader
);
2894 assert(sctx
->scratch_buffer
);
2896 if (shader
->previous_stage
)
2897 si_shader_apply_scratch_relocs(shader
->previous_stage
, scratch_va
);
2899 si_shader_apply_scratch_relocs(shader
, scratch_va
);
2901 /* Replace the shader bo with a new bo that has the relocs applied. */
2902 r
= si_shader_binary_upload(sctx
->screen
, shader
);
2904 si_shader_unlock(shader
);
2908 /* Update the shader state to use the new shader bo. */
2909 si_shader_init_pm4_state(sctx
->screen
, shader
);
2911 r600_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
2913 si_shader_unlock(shader
);
2917 static unsigned si_get_current_scratch_buffer_size(struct si_context
*sctx
)
2919 return sctx
->scratch_buffer
? sctx
->scratch_buffer
->b
.b
.width0
: 0;
2922 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
2924 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
2927 static struct si_shader
*si_get_tcs_current(struct si_context
*sctx
)
2929 if (!sctx
->tes_shader
.cso
)
2930 return NULL
; /* tessellation disabled */
2932 return sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.current
:
2933 sctx
->fixed_func_tcs_shader
.current
;
2936 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context
*sctx
)
2940 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
2941 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
2942 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
2943 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
2945 if (sctx
->tes_shader
.cso
) {
2946 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
2948 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(tcs
));
2953 static bool si_update_scratch_relocs(struct si_context
*sctx
)
2955 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
2958 /* Update the shaders, so that they are using the latest scratch.
2959 * The scratch buffer may have been changed since these shaders were
2960 * last used, so we still need to try to update them, even if they
2961 * require scratch buffers smaller than the current size.
2963 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
2967 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
2969 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
2973 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
2975 r
= si_update_scratch_buffer(sctx
, tcs
);
2979 si_pm4_bind_state(sctx
, hs
, tcs
->pm4
);
2981 /* VS can be bound as LS, ES, or VS. */
2982 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
2986 if (sctx
->tes_shader
.current
)
2987 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
2988 else if (sctx
->gs_shader
.current
)
2989 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
2991 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
2994 /* TES can be bound as ES or VS. */
2995 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
2999 if (sctx
->gs_shader
.current
)
3000 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3002 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3008 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
3010 unsigned current_scratch_buffer_size
=
3011 si_get_current_scratch_buffer_size(sctx
);
3012 unsigned scratch_bytes_per_wave
=
3013 si_get_max_scratch_bytes_per_wave(sctx
);
3014 unsigned scratch_needed_size
= scratch_bytes_per_wave
*
3015 sctx
->scratch_waves
;
3016 unsigned spi_tmpring_size
;
3018 if (scratch_needed_size
> 0) {
3019 if (scratch_needed_size
> current_scratch_buffer_size
) {
3020 /* Create a bigger scratch buffer */
3021 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
3023 sctx
->scratch_buffer
= (struct r600_resource
*)
3024 si_aligned_buffer_create(&sctx
->screen
->b
.b
,
3025 R600_RESOURCE_FLAG_UNMAPPABLE
,
3027 scratch_needed_size
, 256);
3028 if (!sctx
->scratch_buffer
)
3031 si_mark_atom_dirty(sctx
, &sctx
->scratch_state
);
3032 si_context_add_resource_size(&sctx
->b
.b
,
3033 &sctx
->scratch_buffer
->b
.b
);
3036 if (!si_update_scratch_relocs(sctx
))
3040 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3041 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
3042 "scratch size should already be aligned correctly.");
3044 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
3045 S_0286E8_WAVESIZE(scratch_bytes_per_wave
>> 10);
3046 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
3047 sctx
->spi_tmpring_size
= spi_tmpring_size
;
3048 si_mark_atom_dirty(sctx
, &sctx
->scratch_state
);
3053 static void si_init_tess_factor_ring(struct si_context
*sctx
)
3055 bool double_offchip_buffers
= sctx
->b
.chip_class
>= CIK
&&
3056 sctx
->b
.family
!= CHIP_CARRIZO
&&
3057 sctx
->b
.family
!= CHIP_STONEY
;
3058 /* This must be one less than the maximum number due to a hw limitation.
3059 * Various hardware bugs in SI, CIK, and GFX9 need this.
3061 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 127 : 63;
3062 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
3063 sctx
->screen
->b
.info
.max_se
;
3064 unsigned offchip_granularity
;
3066 switch (sctx
->screen
->tess_offchip_block_dw_size
) {
3071 offchip_granularity
= V_03093C_X_8K_DWORDS
;
3074 offchip_granularity
= V_03093C_X_4K_DWORDS
;
3078 assert(!sctx
->tf_ring
);
3079 /* Use 64K alignment for both rings, so that we can pass the address
3080 * to shaders as one SGPR containing bits [16:47].
3082 sctx
->tf_ring
= si_aligned_buffer_create(sctx
->b
.b
.screen
,
3083 R600_RESOURCE_FLAG_UNMAPPABLE
,
3085 32768 * sctx
->screen
->b
.info
.max_se
,
3090 assert(((sctx
->tf_ring
->width0
/ 4) & C_030938_SIZE
) == 0);
3092 sctx
->tess_offchip_ring
=
3093 si_aligned_buffer_create(sctx
->b
.b
.screen
,
3094 R600_RESOURCE_FLAG_UNMAPPABLE
,
3096 max_offchip_buffers
*
3097 sctx
->screen
->tess_offchip_block_dw_size
* 4,
3099 if (!sctx
->tess_offchip_ring
)
3102 si_init_config_add_vgt_flush(sctx
);
3104 uint64_t offchip_va
= r600_resource(sctx
->tess_offchip_ring
)->gpu_address
;
3105 uint64_t factor_va
= r600_resource(sctx
->tf_ring
)->gpu_address
;
3106 assert((offchip_va
& 0xffff) == 0);
3107 assert((factor_va
& 0xffff) == 0);
3109 si_pm4_add_bo(sctx
->init_config
, r600_resource(sctx
->tess_offchip_ring
),
3110 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
3111 si_pm4_add_bo(sctx
->init_config
, r600_resource(sctx
->tf_ring
),
3112 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
3114 /* Append these registers to the init config state. */
3115 if (sctx
->b
.chip_class
>= CIK
) {
3116 if (sctx
->b
.chip_class
>= VI
)
3117 --max_offchip_buffers
;
3119 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
3120 S_030938_SIZE(sctx
->tf_ring
->width0
/ 4));
3121 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
3123 if (sctx
->b
.chip_class
>= GFX9
)
3124 si_pm4_set_reg(sctx
->init_config
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3126 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3127 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
3128 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
));
3130 assert(offchip_granularity
== V_03093C_X_8K_DWORDS
);
3131 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
3132 S_008988_SIZE(sctx
->tf_ring
->width0
/ 4));
3133 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
3135 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3136 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
));
3139 if (sctx
->b
.chip_class
>= GFX9
) {
3140 si_pm4_set_reg(sctx
->init_config
,
3141 R_00B430_SPI_SHADER_USER_DATA_LS_0
+
3142 GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K
* 4,
3144 si_pm4_set_reg(sctx
->init_config
,
3145 R_00B430_SPI_SHADER_USER_DATA_LS_0
+
3146 GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K
* 4,
3149 si_pm4_set_reg(sctx
->init_config
,
3150 R_00B430_SPI_SHADER_USER_DATA_HS_0
+
3151 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K
* 4,
3153 si_pm4_set_reg(sctx
->init_config
,
3154 R_00B430_SPI_SHADER_USER_DATA_HS_0
+
3155 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K
* 4,
3159 /* Flush the context to re-emit the init_config state.
3160 * This is done only once in a lifetime of a context.
3162 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3163 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
3164 si_context_gfx_flush(sctx
, RADEON_FLUSH_ASYNC
, NULL
);
3168 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
3169 * VS passes its outputs to TES directly, so the fixed-function shader only
3170 * has to write TESSOUTER and TESSINNER.
3172 static void si_generate_fixed_func_tcs(struct si_context
*sctx
)
3174 struct ureg_src outer
, inner
;
3175 struct ureg_dst tessouter
, tessinner
;
3176 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_TESS_CTRL
);
3179 return; /* if we get here, we're screwed */
3181 assert(!sctx
->fixed_func_tcs_shader
.cso
);
3183 outer
= ureg_DECL_system_value(ureg
,
3184 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
, 0);
3185 inner
= ureg_DECL_system_value(ureg
,
3186 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
, 0);
3188 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
3189 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
3191 ureg_MOV(ureg
, tessouter
, outer
);
3192 ureg_MOV(ureg
, tessinner
, inner
);
3195 sctx
->fixed_func_tcs_shader
.cso
=
3196 ureg_create_shader_and_destroy(ureg
, &sctx
->b
.b
);
3199 static void si_update_vgt_shader_config(struct si_context
*sctx
)
3201 /* Calculate the index of the config.
3202 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3203 unsigned index
= 2*!!sctx
->tes_shader
.cso
+ !!sctx
->gs_shader
.cso
;
3204 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[index
];
3207 uint32_t stages
= 0;
3209 *pm4
= CALLOC_STRUCT(si_pm4_state
);
3211 if (sctx
->tes_shader
.cso
) {
3212 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3213 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3215 if (sctx
->gs_shader
.cso
)
3216 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3218 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3220 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3221 } else if (sctx
->gs_shader
.cso
) {
3222 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3224 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3227 if (sctx
->b
.chip_class
>= GFX9
)
3228 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3230 si_pm4_set_reg(*pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
3232 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
3235 bool si_update_shaders(struct si_context
*sctx
)
3237 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
3238 struct si_compiler_ctx_state compiler_state
;
3239 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3240 struct si_shader
*old_vs
= si_get_vs_state(sctx
);
3241 bool old_clip_disable
= old_vs
? old_vs
->key
.opt
.clip_disable
: false;
3242 struct si_shader
*old_ps
= sctx
->ps_shader
.current
;
3243 unsigned old_spi_shader_col_format
=
3244 old_ps
? old_ps
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
3247 compiler_state
.tm
= sctx
->tm
;
3248 compiler_state
.debug
= sctx
->debug
;
3249 compiler_state
.is_debug_context
= sctx
->is_debug
;
3251 /* Update stages before GS. */
3252 if (sctx
->tes_shader
.cso
) {
3253 if (!sctx
->tf_ring
) {
3254 si_init_tess_factor_ring(sctx
);
3260 if (sctx
->b
.chip_class
<= VI
) {
3261 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
3265 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3268 if (sctx
->tcs_shader
.cso
) {
3269 r
= si_shader_select(ctx
, &sctx
->tcs_shader
,
3273 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
3275 if (!sctx
->fixed_func_tcs_shader
.cso
) {
3276 si_generate_fixed_func_tcs(sctx
);
3277 if (!sctx
->fixed_func_tcs_shader
.cso
)
3281 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
,
3285 si_pm4_bind_state(sctx
, hs
,
3286 sctx
->fixed_func_tcs_shader
.current
->pm4
);
3289 if (sctx
->gs_shader
.cso
) {
3291 if (sctx
->b
.chip_class
<= VI
) {
3292 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
3296 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3300 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
3304 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3306 } else if (sctx
->gs_shader
.cso
) {
3307 if (sctx
->b
.chip_class
<= VI
) {
3309 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
3313 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3315 si_pm4_bind_state(sctx
, ls
, NULL
);
3316 si_pm4_bind_state(sctx
, hs
, NULL
);
3320 r
= si_shader_select(ctx
, &sctx
->vs_shader
, &compiler_state
);
3323 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3324 si_pm4_bind_state(sctx
, ls
, NULL
);
3325 si_pm4_bind_state(sctx
, hs
, NULL
);
3329 if (sctx
->gs_shader
.cso
) {
3330 r
= si_shader_select(ctx
, &sctx
->gs_shader
, &compiler_state
);
3333 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3334 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
3336 if (!si_update_gs_ring_buffers(sctx
))
3339 si_pm4_bind_state(sctx
, gs
, NULL
);
3340 if (sctx
->b
.chip_class
<= VI
)
3341 si_pm4_bind_state(sctx
, es
, NULL
);
3344 si_update_vgt_shader_config(sctx
);
3346 if (old_clip_disable
!= si_get_vs_state(sctx
)->key
.opt
.clip_disable
)
3347 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
3349 if (sctx
->ps_shader
.cso
) {
3350 unsigned db_shader_control
;
3352 r
= si_shader_select(ctx
, &sctx
->ps_shader
, &compiler_state
);
3355 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3358 sctx
->ps_shader
.cso
->db_shader_control
|
3359 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
3361 if (si_pm4_state_changed(sctx
, ps
) || si_pm4_state_changed(sctx
, vs
) ||
3362 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
3363 sctx
->flatshade
!= rs
->flatshade
) {
3364 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
3365 sctx
->flatshade
= rs
->flatshade
;
3366 si_mark_atom_dirty(sctx
, &sctx
->spi_map
);
3369 if (sctx
->screen
->b
.rbplus_allowed
&&
3370 si_pm4_state_changed(sctx
, ps
) &&
3372 old_spi_shader_col_format
!=
3373 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
))
3374 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
3376 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
3377 sctx
->ps_db_shader_control
= db_shader_control
;
3378 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
3379 if (sctx
->screen
->dpbb_allowed
)
3380 si_mark_atom_dirty(sctx
, &sctx
->dpbb_state
);
3383 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
3384 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
3385 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
3387 if (sctx
->b
.chip_class
== SI
)
3388 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
3390 if (sctx
->framebuffer
.nr_samples
<= 1)
3391 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
3395 if (si_pm4_state_enabled_and_changed(sctx
, ls
) ||
3396 si_pm4_state_enabled_and_changed(sctx
, hs
) ||
3397 si_pm4_state_enabled_and_changed(sctx
, es
) ||
3398 si_pm4_state_enabled_and_changed(sctx
, gs
) ||
3399 si_pm4_state_enabled_and_changed(sctx
, vs
) ||
3400 si_pm4_state_enabled_and_changed(sctx
, ps
)) {
3401 if (!si_update_spi_tmpring_size(sctx
))
3405 if (sctx
->b
.chip_class
>= CIK
) {
3406 if (si_pm4_state_enabled_and_changed(sctx
, ls
))
3407 sctx
->prefetch_L2_mask
|= SI_PREFETCH_LS
;
3408 else if (!sctx
->queued
.named
.ls
)
3409 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_LS
;
3411 if (si_pm4_state_enabled_and_changed(sctx
, hs
))
3412 sctx
->prefetch_L2_mask
|= SI_PREFETCH_HS
;
3413 else if (!sctx
->queued
.named
.hs
)
3414 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_HS
;
3416 if (si_pm4_state_enabled_and_changed(sctx
, es
))
3417 sctx
->prefetch_L2_mask
|= SI_PREFETCH_ES
;
3418 else if (!sctx
->queued
.named
.es
)
3419 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_ES
;
3421 if (si_pm4_state_enabled_and_changed(sctx
, gs
))
3422 sctx
->prefetch_L2_mask
|= SI_PREFETCH_GS
;
3423 else if (!sctx
->queued
.named
.gs
)
3424 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_GS
;
3426 if (si_pm4_state_enabled_and_changed(sctx
, vs
))
3427 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VS
;
3428 else if (!sctx
->queued
.named
.vs
)
3429 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_VS
;
3431 if (si_pm4_state_enabled_and_changed(sctx
, ps
))
3432 sctx
->prefetch_L2_mask
|= SI_PREFETCH_PS
;
3433 else if (!sctx
->queued
.named
.ps
)
3434 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_PS
;
3437 sctx
->do_update_shaders
= false;
3441 static void si_emit_scratch_state(struct si_context
*sctx
,
3442 struct r600_atom
*atom
)
3444 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
3446 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
3447 sctx
->spi_tmpring_size
);
3449 if (sctx
->scratch_buffer
) {
3450 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
3451 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
3452 RADEON_PRIO_SCRATCH_BUFFER
);
3456 void *si_get_blit_vs(struct si_context
*sctx
, enum blitter_attrib_type type
,
3457 unsigned num_layers
)
3459 struct pipe_context
*pipe
= &sctx
->b
.b
;
3460 unsigned vs_blit_property
;
3464 case UTIL_BLITTER_ATTRIB_NONE
:
3465 vs
= num_layers
> 1 ? &sctx
->vs_blit_pos_layered
:
3467 vs_blit_property
= SI_VS_BLIT_SGPRS_POS
;
3469 case UTIL_BLITTER_ATTRIB_COLOR
:
3470 vs
= num_layers
> 1 ? &sctx
->vs_blit_color_layered
:
3471 &sctx
->vs_blit_color
;
3472 vs_blit_property
= SI_VS_BLIT_SGPRS_POS_COLOR
;
3474 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY
:
3475 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW
:
3476 assert(num_layers
== 1);
3477 vs
= &sctx
->vs_blit_texcoord
;
3478 vs_blit_property
= SI_VS_BLIT_SGPRS_POS_TEXCOORD
;
3487 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_VERTEX
);
3491 /* Tell the shader to load VS inputs from SGPRs: */
3492 ureg_property(ureg
, TGSI_PROPERTY_VS_BLIT_SGPRS
, vs_blit_property
);
3493 ureg_property(ureg
, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
, true);
3495 /* This is just a pass-through shader with 1-3 MOV instructions. */
3497 ureg_DECL_output(ureg
, TGSI_SEMANTIC_POSITION
, 0),
3498 ureg_DECL_vs_input(ureg
, 0));
3500 if (type
!= UTIL_BLITTER_ATTRIB_NONE
) {
3502 ureg_DECL_output(ureg
, TGSI_SEMANTIC_GENERIC
, 0),
3503 ureg_DECL_vs_input(ureg
, 1));
3506 if (num_layers
> 1) {
3507 struct ureg_src instance_id
=
3508 ureg_DECL_system_value(ureg
, TGSI_SEMANTIC_INSTANCEID
, 0);
3509 struct ureg_dst layer
=
3510 ureg_DECL_output(ureg
, TGSI_SEMANTIC_LAYER
, 0);
3512 ureg_MOV(ureg
, ureg_writemask(layer
, TGSI_WRITEMASK_X
),
3513 ureg_scalar(instance_id
, TGSI_SWIZZLE_X
));
3517 *vs
= ureg_create_shader_and_destroy(ureg
, pipe
);
3521 void si_init_shader_functions(struct si_context
*sctx
)
3523 si_init_atom(sctx
, &sctx
->spi_map
, &sctx
->atoms
.s
.spi_map
, si_emit_spi_map
);
3524 si_init_atom(sctx
, &sctx
->scratch_state
, &sctx
->atoms
.s
.scratch_state
,
3525 si_emit_scratch_state
);
3527 sctx
->b
.b
.create_vs_state
= si_create_shader_selector
;
3528 sctx
->b
.b
.create_tcs_state
= si_create_shader_selector
;
3529 sctx
->b
.b
.create_tes_state
= si_create_shader_selector
;
3530 sctx
->b
.b
.create_gs_state
= si_create_shader_selector
;
3531 sctx
->b
.b
.create_fs_state
= si_create_shader_selector
;
3533 sctx
->b
.b
.bind_vs_state
= si_bind_vs_shader
;
3534 sctx
->b
.b
.bind_tcs_state
= si_bind_tcs_shader
;
3535 sctx
->b
.b
.bind_tes_state
= si_bind_tes_shader
;
3536 sctx
->b
.b
.bind_gs_state
= si_bind_gs_shader
;
3537 sctx
->b
.b
.bind_fs_state
= si_bind_ps_shader
;
3539 sctx
->b
.b
.delete_vs_state
= si_delete_shader_selector
;
3540 sctx
->b
.b
.delete_tcs_state
= si_delete_shader_selector
;
3541 sctx
->b
.b
.delete_tes_state
= si_delete_shader_selector
;
3542 sctx
->b
.b
.delete_gs_state
= si_delete_shader_selector
;
3543 sctx
->b
.b
.delete_fs_state
= si_delete_shader_selector
;