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[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "si_shader.h"
30 #include "sid.h"
31 #include "radeon/r600_cs.h"
32
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/u_memory.h"
36 #include "util/u_prim.h"
37 #include "util/u_simple_shaders.h"
38
39 static void si_set_tesseval_regs(struct si_shader *shader,
40 struct si_pm4_state *pm4)
41 {
42 struct tgsi_shader_info *info = &shader->selector->info;
43 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
44 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
45 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
46 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
47 unsigned type, partitioning, topology;
48
49 switch (tes_prim_mode) {
50 case PIPE_PRIM_LINES:
51 type = V_028B6C_TESS_ISOLINE;
52 break;
53 case PIPE_PRIM_TRIANGLES:
54 type = V_028B6C_TESS_TRIANGLE;
55 break;
56 case PIPE_PRIM_QUADS:
57 type = V_028B6C_TESS_QUAD;
58 break;
59 default:
60 assert(0);
61 return;
62 }
63
64 switch (tes_spacing) {
65 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
66 partitioning = V_028B6C_PART_FRAC_ODD;
67 break;
68 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
69 partitioning = V_028B6C_PART_FRAC_EVEN;
70 break;
71 case PIPE_TESS_SPACING_EQUAL:
72 partitioning = V_028B6C_PART_INTEGER;
73 break;
74 default:
75 assert(0);
76 return;
77 }
78
79 if (tes_point_mode)
80 topology = V_028B6C_OUTPUT_POINT;
81 else if (tes_prim_mode == PIPE_PRIM_LINES)
82 topology = V_028B6C_OUTPUT_LINE;
83 else if (tes_vertex_order_cw)
84 /* for some reason, this must be the other way around */
85 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
86 else
87 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
88
89 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
90 S_028B6C_TYPE(type) |
91 S_028B6C_PARTITIONING(partitioning) |
92 S_028B6C_TOPOLOGY(topology));
93 }
94
95 static void si_shader_ls(struct si_shader *shader)
96 {
97 struct si_pm4_state *pm4;
98 unsigned num_sgprs, num_user_sgprs;
99 unsigned vgpr_comp_cnt;
100 uint64_t va;
101
102 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
103 if (!pm4)
104 return;
105
106 va = shader->bo->gpu_address;
107 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
108
109 /* We need at least 2 components for LS.
110 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
111 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 1;
112
113 num_user_sgprs = SI_LS_NUM_USER_SGPR;
114 num_sgprs = shader->config.num_sgprs;
115 if (num_user_sgprs > num_sgprs) {
116 /* Last 2 reserved SGPRs are used for VCC */
117 num_sgprs = num_user_sgprs + 2;
118 }
119 assert(num_sgprs <= 104);
120
121 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
122 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
123
124 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
125 S_00B528_SGPRS((num_sgprs - 1) / 8) |
126 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
127 S_00B528_DX10_CLAMP(shader->dx10_clamp_mode);
128 shader->config.rsrc2 = S_00B52C_USER_SGPR(num_user_sgprs) |
129 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
130 }
131
132 static void si_shader_hs(struct si_shader *shader)
133 {
134 struct si_pm4_state *pm4;
135 unsigned num_sgprs, num_user_sgprs;
136 uint64_t va;
137
138 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
139 if (!pm4)
140 return;
141
142 va = shader->bo->gpu_address;
143 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
144
145 num_user_sgprs = SI_TCS_NUM_USER_SGPR;
146 num_sgprs = shader->config.num_sgprs;
147 /* One SGPR after user SGPRs is pre-loaded with tessellation factor
148 * buffer offset. */
149 if ((num_user_sgprs + 1) > num_sgprs) {
150 /* Last 2 reserved SGPRs are used for VCC */
151 num_sgprs = num_user_sgprs + 1 + 2;
152 }
153 assert(num_sgprs <= 104);
154
155 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
156 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
157 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
158 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
159 S_00B428_SGPRS((num_sgprs - 1) / 8) |
160 S_00B428_DX10_CLAMP(shader->dx10_clamp_mode));
161 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
162 S_00B42C_USER_SGPR(num_user_sgprs) |
163 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
164 }
165
166 static void si_shader_es(struct si_shader *shader)
167 {
168 struct si_pm4_state *pm4;
169 unsigned num_sgprs, num_user_sgprs;
170 unsigned vgpr_comp_cnt;
171 uint64_t va;
172
173 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
174
175 if (!pm4)
176 return;
177
178 va = shader->bo->gpu_address;
179 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
180
181 if (shader->selector->type == PIPE_SHADER_VERTEX) {
182 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
183 num_user_sgprs = SI_ES_NUM_USER_SGPR;
184 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
185 vgpr_comp_cnt = 3; /* all components are needed for TES */
186 num_user_sgprs = SI_TES_NUM_USER_SGPR;
187 } else
188 unreachable("invalid shader selector type");
189
190 num_sgprs = shader->config.num_sgprs;
191 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
192 if ((num_user_sgprs + 1) > num_sgprs) {
193 /* Last 2 reserved SGPRs are used for VCC */
194 num_sgprs = num_user_sgprs + 1 + 2;
195 }
196 assert(num_sgprs <= 104);
197
198 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
199 shader->selector->esgs_itemsize / 4);
200 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
201 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
202 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
203 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
204 S_00B328_SGPRS((num_sgprs - 1) / 8) |
205 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
206 S_00B328_DX10_CLAMP(shader->dx10_clamp_mode));
207 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
208 S_00B32C_USER_SGPR(num_user_sgprs) |
209 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
210
211 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
212 si_set_tesseval_regs(shader, pm4);
213 }
214
215 /**
216 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
217 * geometry shader.
218 */
219 static uint32_t si_vgt_gs_mode(struct si_shader *shader)
220 {
221 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
222 unsigned cut_mode;
223
224 if (gs_max_vert_out <= 128) {
225 cut_mode = V_028A40_GS_CUT_128;
226 } else if (gs_max_vert_out <= 256) {
227 cut_mode = V_028A40_GS_CUT_256;
228 } else if (gs_max_vert_out <= 512) {
229 cut_mode = V_028A40_GS_CUT_512;
230 } else {
231 assert(gs_max_vert_out <= 1024);
232 cut_mode = V_028A40_GS_CUT_1024;
233 }
234
235 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
236 S_028A40_CUT_MODE(cut_mode)|
237 S_028A40_ES_WRITE_OPTIMIZE(1) |
238 S_028A40_GS_WRITE_OPTIMIZE(1);
239 }
240
241 static void si_shader_gs(struct si_shader *shader)
242 {
243 unsigned gs_vert_itemsize = shader->selector->gsvs_vertex_size;
244 unsigned gsvs_itemsize = shader->selector->max_gsvs_emit_size >> 2;
245 unsigned gs_num_invocations = shader->selector->gs_num_invocations;
246 struct si_pm4_state *pm4;
247 unsigned num_sgprs, num_user_sgprs;
248 uint64_t va;
249 unsigned max_stream = shader->selector->max_gs_stream;
250
251 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
252 assert(gsvs_itemsize < (1 << 15));
253
254 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
255
256 if (!pm4)
257 return;
258
259 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(shader));
260
261 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
262 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize * ((max_stream >= 2) ? 2 : 1));
263 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize * ((max_stream >= 3) ? 3 : 1));
264
265 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize * (max_stream + 1));
266
267 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, shader->selector->gs_max_out_vertices);
268
269 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize >> 2);
270 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? gs_vert_itemsize >> 2 : 0);
271 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? gs_vert_itemsize >> 2 : 0);
272 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? gs_vert_itemsize >> 2 : 0);
273
274 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
275 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
276 S_028B90_ENABLE(gs_num_invocations > 0));
277
278 va = shader->bo->gpu_address;
279 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
280 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
281 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
282
283 num_user_sgprs = SI_GS_NUM_USER_SGPR;
284 num_sgprs = shader->config.num_sgprs;
285 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
286 if ((num_user_sgprs + 2) > num_sgprs) {
287 /* Last 2 reserved SGPRs are used for VCC */
288 num_sgprs = num_user_sgprs + 2 + 2;
289 }
290 assert(num_sgprs <= 104);
291
292 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
293 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
294 S_00B228_SGPRS((num_sgprs - 1) / 8) |
295 S_00B228_DX10_CLAMP(shader->dx10_clamp_mode));
296 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
297 S_00B22C_USER_SGPR(num_user_sgprs) |
298 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
299 }
300
301 /**
302 * Compute the state for \p shader, which will run as a vertex shader on the
303 * hardware.
304 *
305 * If \p gs is non-NULL, it points to the geometry shader for which this shader
306 * is the copy shader.
307 */
308 static void si_shader_vs(struct si_shader *shader, struct si_shader *gs)
309 {
310 struct si_pm4_state *pm4;
311 unsigned num_sgprs, num_user_sgprs;
312 unsigned nparams, vgpr_comp_cnt;
313 uint64_t va;
314 unsigned window_space =
315 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
316 bool enable_prim_id = si_vs_exports_prim_id(shader);
317
318 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
319
320 if (!pm4)
321 return;
322
323 /* We always write VGT_GS_MODE in the VS state, because every switch
324 * between different shader pipelines involving a different GS or no
325 * GS at all involves a switch of the VS (different GS use different
326 * copy shaders). On the other hand, when the API switches from a GS to
327 * no GS and then back to the same GS used originally, the GS state is
328 * not sent again.
329 */
330 if (!gs) {
331 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
332 S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
333 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
334 } else {
335 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
336 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
337 }
338
339 va = shader->bo->gpu_address;
340 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
341
342 if (gs) {
343 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
344 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
345 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
346 vgpr_comp_cnt = shader->uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
347 num_user_sgprs = SI_VS_NUM_USER_SGPR;
348 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
349 vgpr_comp_cnt = 3; /* all components are needed for TES */
350 num_user_sgprs = SI_TES_NUM_USER_SGPR;
351 } else
352 unreachable("invalid shader selector type");
353
354 num_sgprs = shader->config.num_sgprs;
355 if (num_user_sgprs > num_sgprs) {
356 /* Last 2 reserved SGPRs are used for VCC */
357 num_sgprs = num_user_sgprs + 2;
358 }
359 assert(num_sgprs <= 104);
360
361 /* VS is required to export at least one param. */
362 nparams = MAX2(shader->nr_param_exports, 1);
363 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
364 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
365
366 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
367 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
368 S_02870C_POS1_EXPORT_FORMAT(shader->nr_pos_exports > 1 ?
369 V_02870C_SPI_SHADER_4COMP :
370 V_02870C_SPI_SHADER_NONE) |
371 S_02870C_POS2_EXPORT_FORMAT(shader->nr_pos_exports > 2 ?
372 V_02870C_SPI_SHADER_4COMP :
373 V_02870C_SPI_SHADER_NONE) |
374 S_02870C_POS3_EXPORT_FORMAT(shader->nr_pos_exports > 3 ?
375 V_02870C_SPI_SHADER_4COMP :
376 V_02870C_SPI_SHADER_NONE));
377
378 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
379 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
380 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
381 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
382 S_00B128_SGPRS((num_sgprs - 1) / 8) |
383 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
384 S_00B128_DX10_CLAMP(shader->dx10_clamp_mode));
385 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
386 S_00B12C_USER_SGPR(num_user_sgprs) |
387 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
388 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
389 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
390 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
391 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
392 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
393 if (window_space)
394 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
395 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
396 else
397 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
398 S_028818_VTX_W0_FMT(1) |
399 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
400 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
401 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
402
403 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
404 si_set_tesseval_regs(shader, pm4);
405 }
406
407 static unsigned si_get_ps_num_interp(struct si_shader *ps)
408 {
409 struct tgsi_shader_info *info = &ps->selector->info;
410 unsigned num_colors = !!(info->colors_read & 0x0f) +
411 !!(info->colors_read & 0xf0);
412 unsigned num_interp = ps->selector->info.num_inputs +
413 (ps->key.ps.color_two_side ? num_colors : 0);
414
415 assert(num_interp <= 32);
416 return MIN2(num_interp, 32);
417 }
418
419 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
420 {
421 unsigned value = shader->key.ps.spi_shader_col_format;
422 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
423
424 /* If the i-th target format is set, all previous target formats must
425 * be non-zero to avoid hangs.
426 */
427 for (i = 0; i < num_targets; i++)
428 if (!(value & (0xf << (i * 4))))
429 value |= V_028714_SPI_SHADER_32_R << (i * 4);
430
431 return value;
432 }
433
434 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
435 {
436 unsigned i, cb_shader_mask = 0;
437
438 for (i = 0; i < 8; i++) {
439 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
440 case V_028714_SPI_SHADER_ZERO:
441 break;
442 case V_028714_SPI_SHADER_32_R:
443 cb_shader_mask |= 0x1 << (i * 4);
444 break;
445 case V_028714_SPI_SHADER_32_GR:
446 cb_shader_mask |= 0x3 << (i * 4);
447 break;
448 case V_028714_SPI_SHADER_32_AR:
449 cb_shader_mask |= 0x9 << (i * 4);
450 break;
451 case V_028714_SPI_SHADER_FP16_ABGR:
452 case V_028714_SPI_SHADER_UNORM16_ABGR:
453 case V_028714_SPI_SHADER_SNORM16_ABGR:
454 case V_028714_SPI_SHADER_UINT16_ABGR:
455 case V_028714_SPI_SHADER_SINT16_ABGR:
456 case V_028714_SPI_SHADER_32_ABGR:
457 cb_shader_mask |= 0xf << (i * 4);
458 break;
459 default:
460 assert(0);
461 }
462 }
463 return cb_shader_mask;
464 }
465
466 static void si_shader_ps(struct si_shader *shader)
467 {
468 struct tgsi_shader_info *info = &shader->selector->info;
469 struct si_pm4_state *pm4;
470 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
471 unsigned num_sgprs, num_user_sgprs;
472 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
473 uint64_t va;
474 bool has_centroid;
475 unsigned input_ena = shader->config.spi_ps_input_ena;
476
477 /* we need to enable at least one of them, otherwise we hang the GPU */
478 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
479 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
480 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
481 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
482 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
483 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
484 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
485 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
486
487 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
488
489 if (!pm4)
490 return;
491
492 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
493 * Possible vaules:
494 * 0 -> Position = pixel center
495 * 1 -> Position = pixel centroid
496 * 2 -> Position = at sample position
497 *
498 * From GLSL 4.5 specification, section 7.1:
499 * "The variable gl_FragCoord is available as an input variable from
500 * within fragment shaders and it holds the window relative coordinates
501 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
502 * value can be for any location within the pixel, or one of the
503 * fragment samples. The use of centroid does not further restrict
504 * this value to be inside the current primitive."
505 *
506 * Meaning that centroid has no effect and we can return anything within
507 * the pixel. Thus, return the value at sample position, because that's
508 * the most accurate one shaders can get.
509 */
510 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
511
512 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
513 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
514 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
515
516 spi_shader_col_format = si_get_spi_shader_col_format(shader);
517 cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
518
519 /* This must be non-zero for alpha-test/kill to work.
520 * The hardware ignores the EXEC mask if no export memory is allocated.
521 * Don't add this to CB_SHADER_MASK.
522 */
523 if (!spi_shader_col_format &&
524 !info->writes_z && !info->writes_stencil && !info->writes_samplemask &&
525 (shader->selector->info.uses_kill ||
526 shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS))
527 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
528
529 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
530 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, input_ena);
531
532 /* Set interpolation controls. */
533 has_centroid = G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena) ||
534 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena);
535
536 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
537 S_0286D8_BC_OPTIMIZE_DISABLE(has_centroid);
538
539 /* Set registers. */
540 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
541 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
542
543 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
544 info->writes_samplemask ? V_028710_SPI_SHADER_32_ABGR :
545 info->writes_stencil ? V_028710_SPI_SHADER_32_GR :
546 info->writes_z ? V_028710_SPI_SHADER_32_R :
547 V_028710_SPI_SHADER_ZERO);
548
549 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
550 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
551
552 va = shader->bo->gpu_address;
553 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
554 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
555 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
556
557 num_user_sgprs = SI_PS_NUM_USER_SGPR;
558 num_sgprs = shader->config.num_sgprs;
559 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
560 if ((num_user_sgprs + 1) > num_sgprs) {
561 /* Last 2 reserved SGPRs are used for VCC */
562 num_sgprs = num_user_sgprs + 1 + 2;
563 }
564 assert(num_sgprs <= 104);
565
566 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
567 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
568 S_00B028_SGPRS((num_sgprs - 1) / 8) |
569 S_00B028_DX10_CLAMP(shader->dx10_clamp_mode));
570 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
571 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
572 S_00B02C_USER_SGPR(num_user_sgprs) |
573 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
574 }
575
576 static void si_shader_init_pm4_state(struct si_shader *shader)
577 {
578
579 if (shader->pm4)
580 si_pm4_free_state_simple(shader->pm4);
581
582 switch (shader->selector->type) {
583 case PIPE_SHADER_VERTEX:
584 if (shader->key.vs.as_ls)
585 si_shader_ls(shader);
586 else if (shader->key.vs.as_es)
587 si_shader_es(shader);
588 else
589 si_shader_vs(shader, NULL);
590 break;
591 case PIPE_SHADER_TESS_CTRL:
592 si_shader_hs(shader);
593 break;
594 case PIPE_SHADER_TESS_EVAL:
595 if (shader->key.tes.as_es)
596 si_shader_es(shader);
597 else
598 si_shader_vs(shader, NULL);
599 break;
600 case PIPE_SHADER_GEOMETRY:
601 si_shader_gs(shader);
602 si_shader_vs(shader->gs_copy_shader, shader);
603 break;
604 case PIPE_SHADER_FRAGMENT:
605 si_shader_ps(shader);
606 break;
607 default:
608 assert(0);
609 }
610 }
611
612 static unsigned si_get_alpha_test_func(struct si_context *sctx)
613 {
614 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
615 if (sctx->queued.named.dsa &&
616 !sctx->framebuffer.cb0_is_integer)
617 return sctx->queued.named.dsa->alpha_func;
618
619 return PIPE_FUNC_ALWAYS;
620 }
621
622 /* Compute the key for the hw shader variant */
623 static inline void si_shader_selector_key(struct pipe_context *ctx,
624 struct si_shader_selector *sel,
625 union si_shader_key *key)
626 {
627 struct si_context *sctx = (struct si_context *)ctx;
628 unsigned i;
629
630 memset(key, 0, sizeof(*key));
631
632 switch (sel->type) {
633 case PIPE_SHADER_VERTEX:
634 if (sctx->vertex_elements)
635 for (i = 0; i < sctx->vertex_elements->count; ++i)
636 key->vs.instance_divisors[i] =
637 sctx->vertex_elements->elements[i].instance_divisor;
638
639 if (sctx->tes_shader.cso)
640 key->vs.as_ls = 1;
641 else if (sctx->gs_shader.cso)
642 key->vs.as_es = 1;
643
644 if (!sctx->gs_shader.cso && sctx->ps_shader.cso &&
645 sctx->ps_shader.cso->info.uses_primid)
646 key->vs.export_prim_id = 1;
647 break;
648 case PIPE_SHADER_TESS_CTRL:
649 key->tcs.prim_mode =
650 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
651 break;
652 case PIPE_SHADER_TESS_EVAL:
653 if (sctx->gs_shader.cso)
654 key->tes.as_es = 1;
655 else if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
656 key->tes.export_prim_id = 1;
657 break;
658 case PIPE_SHADER_GEOMETRY:
659 break;
660 case PIPE_SHADER_FRAGMENT: {
661 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
662 struct si_state_blend *blend = sctx->queued.named.blend;
663
664 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
665 sel->info.colors_written == 0x1)
666 key->ps.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
667
668 if (blend) {
669 /* Select the shader color format based on whether
670 * blending or alpha are needed.
671 */
672 key->ps.spi_shader_col_format =
673 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
674 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
675 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
676 sctx->framebuffer.spi_shader_col_format_blend) |
677 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
678 sctx->framebuffer.spi_shader_col_format_alpha) |
679 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
680 sctx->framebuffer.spi_shader_col_format);
681 } else
682 key->ps.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
683
684 /* If alpha-to-coverage is enabled, we have to export alpha
685 * even if there is no color buffer.
686 */
687 if (!(key->ps.spi_shader_col_format & 0xf) &&
688 blend && blend->alpha_to_coverage)
689 key->ps.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
690
691 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
692 * to the range supported by the type if a channel has less
693 * than 16 bits and the export format is 16_ABGR.
694 */
695 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII)
696 key->ps.color_is_int8 = sctx->framebuffer.color_is_int8;
697
698 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
699 if (!key->ps.last_cbuf) {
700 key->ps.spi_shader_col_format &= sel->colors_written_4bit;
701 key->ps.color_is_int8 &= sel->info.colors_written;
702 }
703
704 if (rs) {
705 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
706 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
707 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
708 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
709
710 key->ps.color_two_side = rs->two_side && sel->info.colors_read;
711
712 if (sctx->queued.named.blend) {
713 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
714 rs->multisample_enable &&
715 !sctx->framebuffer.cb0_is_integer;
716 }
717
718 key->ps.poly_stipple = rs->poly_stipple_enable && is_poly;
719 key->ps.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
720 (is_line && rs->line_smooth)) &&
721 sctx->framebuffer.nr_samples <= 1;
722 key->ps.clamp_color = rs->clamp_fragment_color;
723
724 key->ps.force_persample_interp = rs->force_persample_interp &&
725 rs->multisample_enable &&
726 sctx->framebuffer.nr_samples > 1 &&
727 sctx->ps_iter_samples > 1 &&
728 (sel->info.uses_persp_center ||
729 sel->info.uses_persp_centroid ||
730 sel->info.uses_linear_center ||
731 sel->info.uses_linear_centroid);
732 }
733
734 key->ps.alpha_func = si_get_alpha_test_func(sctx);
735 break;
736 }
737 default:
738 assert(0);
739 }
740 }
741
742 /* Select the hw shader variant depending on the current state. */
743 static int si_shader_select_with_key(struct pipe_context *ctx,
744 struct si_shader_ctx_state *state,
745 union si_shader_key *key)
746 {
747 struct si_context *sctx = (struct si_context *)ctx;
748 struct si_shader_selector *sel = state->cso;
749 struct si_shader *current = state->current;
750 struct si_shader *iter, *shader = NULL;
751 int r;
752
753 /* Check if we don't need to change anything.
754 * This path is also used for most shaders that don't need multiple
755 * variants, it will cost just a computation of the key and this
756 * test. */
757 if (likely(current && memcmp(&current->key, key, sizeof(*key)) == 0))
758 return 0;
759
760 pipe_mutex_lock(sel->mutex);
761
762 /* Find the shader variant. */
763 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
764 /* Don't check the "current" shader. We checked it above. */
765 if (current != iter &&
766 memcmp(&iter->key, key, sizeof(*key)) == 0) {
767 state->current = iter;
768 pipe_mutex_unlock(sel->mutex);
769 return 0;
770 }
771 }
772
773 /* Build a new shader. */
774 shader = CALLOC_STRUCT(si_shader);
775 if (!shader) {
776 pipe_mutex_unlock(sel->mutex);
777 return -ENOMEM;
778 }
779 shader->selector = sel;
780 shader->key = *key;
781
782 r = si_shader_create(sctx->screen, sctx->tm, shader, &sctx->b.debug);
783 if (unlikely(r)) {
784 R600_ERR("Failed to build shader variant (type=%u) %d\n",
785 sel->type, r);
786 FREE(shader);
787 pipe_mutex_unlock(sel->mutex);
788 return r;
789 }
790 si_shader_init_pm4_state(shader);
791
792 if (!sel->last_variant) {
793 sel->first_variant = shader;
794 sel->last_variant = shader;
795 } else {
796 sel->last_variant->next_variant = shader;
797 sel->last_variant = shader;
798 }
799 state->current = shader;
800 pipe_mutex_unlock(sel->mutex);
801 return 0;
802 }
803
804 static int si_shader_select(struct pipe_context *ctx,
805 struct si_shader_ctx_state *state)
806 {
807 union si_shader_key key;
808
809 si_shader_selector_key(ctx, state->cso, &key);
810 return si_shader_select_with_key(ctx, state, &key);
811 }
812
813 static void *si_create_shader_selector(struct pipe_context *ctx,
814 const struct pipe_shader_state *state)
815 {
816 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
817 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
818 int i;
819
820 if (!sel)
821 return NULL;
822
823 sel->tokens = tgsi_dup_tokens(state->tokens);
824 if (!sel->tokens) {
825 FREE(sel);
826 return NULL;
827 }
828
829 sel->so = state->stream_output;
830 tgsi_scan_shader(state->tokens, &sel->info);
831 sel->type = util_pipe_shader_from_tgsi_processor(sel->info.processor);
832 p_atomic_inc(&sscreen->b.num_shaders_created);
833
834 /* Set which opcode uses which (i,j) pair. */
835 if (sel->info.uses_persp_opcode_interp_centroid)
836 sel->info.uses_persp_centroid = true;
837
838 if (sel->info.uses_linear_opcode_interp_centroid)
839 sel->info.uses_linear_centroid = true;
840
841 if (sel->info.uses_persp_opcode_interp_offset ||
842 sel->info.uses_persp_opcode_interp_sample)
843 sel->info.uses_persp_center = true;
844
845 if (sel->info.uses_linear_opcode_interp_offset ||
846 sel->info.uses_linear_opcode_interp_sample)
847 sel->info.uses_linear_center = true;
848
849 switch (sel->type) {
850 case PIPE_SHADER_GEOMETRY:
851 sel->gs_output_prim =
852 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
853 sel->gs_max_out_vertices =
854 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
855 sel->gs_num_invocations =
856 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
857 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
858 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
859 sel->gs_max_out_vertices;
860
861 sel->max_gs_stream = 0;
862 for (i = 0; i < sel->so.num_outputs; i++)
863 sel->max_gs_stream = MAX2(sel->max_gs_stream,
864 sel->so.output[i].stream);
865
866 sel->gs_input_verts_per_prim =
867 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
868 break;
869
870 case PIPE_SHADER_VERTEX:
871 case PIPE_SHADER_TESS_CTRL:
872 case PIPE_SHADER_TESS_EVAL:
873 for (i = 0; i < sel->info.num_outputs; i++) {
874 unsigned name = sel->info.output_semantic_name[i];
875 unsigned index = sel->info.output_semantic_index[i];
876
877 switch (name) {
878 case TGSI_SEMANTIC_TESSINNER:
879 case TGSI_SEMANTIC_TESSOUTER:
880 case TGSI_SEMANTIC_PATCH:
881 sel->patch_outputs_written |=
882 1llu << si_shader_io_get_unique_index(name, index);
883 break;
884 default:
885 sel->outputs_written |=
886 1llu << si_shader_io_get_unique_index(name, index);
887 }
888 }
889 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
890 break;
891
892 case PIPE_SHADER_FRAGMENT:
893 for (i = 0; i < 8; i++)
894 if (sel->info.colors_written & (1 << i))
895 sel->colors_written_4bit |= 0xf << (4 * i);
896 break;
897 }
898
899 /* DB_SHADER_CONTROL */
900 sel->db_shader_control =
901 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
902 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
903 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
904 S_02880C_KILL_ENABLE(sel->info.uses_kill);
905
906 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
907 case TGSI_FS_DEPTH_LAYOUT_GREATER:
908 sel->db_shader_control |=
909 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
910 break;
911 case TGSI_FS_DEPTH_LAYOUT_LESS:
912 sel->db_shader_control |=
913 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
914 break;
915 }
916
917 /* Pre-compilation. */
918 if (sscreen->b.debug_flags & DBG_PRECOMPILE) {
919 struct si_shader_ctx_state state = {sel};
920 union si_shader_key key;
921
922 memset(&key, 0, sizeof(key));
923
924 /* Set reasonable defaults, so that the shader key doesn't
925 * cause any code to be eliminated.
926 */
927 switch (sel->type) {
928 case PIPE_SHADER_TESS_CTRL:
929 key.tcs.prim_mode = PIPE_PRIM_TRIANGLES;
930 break;
931 case PIPE_SHADER_FRAGMENT:
932 key.ps.alpha_func = PIPE_FUNC_ALWAYS;
933 for (i = 0; i < 8; i++)
934 if (sel->info.colors_written & (1 << i))
935 key.ps.spi_shader_col_format |=
936 V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
937 break;
938 }
939
940 if (si_shader_select_with_key(ctx, &state, &key)) {
941 fprintf(stderr, "radeonsi: can't create a shader\n");
942 tgsi_free_tokens(sel->tokens);
943 FREE(sel);
944 return NULL;
945 }
946 }
947
948 pipe_mutex_init(sel->mutex);
949 return sel;
950 }
951
952 /**
953 * Normally, we only emit 1 viewport and 1 scissor if no shader is using
954 * the VIEWPORT_INDEX output, and emitting the other viewports and scissors
955 * is delayed. When a shader with VIEWPORT_INDEX appears, this should be
956 * called to emit the rest.
957 */
958 static void si_update_viewports_and_scissors(struct si_context *sctx)
959 {
960 struct tgsi_shader_info *info = si_get_vs_info(sctx);
961
962 if (!info || !info->writes_viewport_index)
963 return;
964
965 if (sctx->scissors.dirty_mask)
966 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
967 if (sctx->viewports.dirty_mask)
968 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
969 }
970
971 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
972 {
973 struct si_context *sctx = (struct si_context *)ctx;
974 struct si_shader_selector *sel = state;
975
976 if (sctx->vs_shader.cso == sel)
977 return;
978
979 sctx->vs_shader.cso = sel;
980 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
981 si_mark_atom_dirty(sctx, &sctx->clip_regs);
982 si_update_viewports_and_scissors(sctx);
983 }
984
985 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
986 {
987 struct si_context *sctx = (struct si_context *)ctx;
988 struct si_shader_selector *sel = state;
989 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
990
991 if (sctx->gs_shader.cso == sel)
992 return;
993
994 sctx->gs_shader.cso = sel;
995 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
996 si_mark_atom_dirty(sctx, &sctx->clip_regs);
997 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
998
999 if (enable_changed)
1000 si_shader_change_notify(sctx);
1001 si_update_viewports_and_scissors(sctx);
1002 }
1003
1004 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
1005 {
1006 struct si_context *sctx = (struct si_context *)ctx;
1007 struct si_shader_selector *sel = state;
1008 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
1009
1010 if (sctx->tcs_shader.cso == sel)
1011 return;
1012
1013 sctx->tcs_shader.cso = sel;
1014 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
1015
1016 if (enable_changed)
1017 sctx->last_tcs = NULL; /* invalidate derived tess state */
1018 }
1019
1020 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
1021 {
1022 struct si_context *sctx = (struct si_context *)ctx;
1023 struct si_shader_selector *sel = state;
1024 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
1025
1026 if (sctx->tes_shader.cso == sel)
1027 return;
1028
1029 sctx->tes_shader.cso = sel;
1030 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
1031 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1032 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1033
1034 if (enable_changed) {
1035 si_shader_change_notify(sctx);
1036 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
1037 }
1038 si_update_viewports_and_scissors(sctx);
1039 }
1040
1041 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
1042 {
1043 struct si_context *sctx = (struct si_context *)ctx;
1044 struct si_shader_selector *sel = state;
1045
1046 /* skip if supplied shader is one already in use */
1047 if (sctx->ps_shader.cso == sel)
1048 return;
1049
1050 sctx->ps_shader.cso = sel;
1051 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
1052 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
1053 }
1054
1055 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
1056 {
1057 struct si_context *sctx = (struct si_context *)ctx;
1058 struct si_shader_selector *sel = (struct si_shader_selector *)state;
1059 struct si_shader *p = sel->first_variant, *c;
1060 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
1061 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
1062 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
1063 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
1064 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
1065 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
1066 };
1067
1068 if (current_shader[sel->type]->cso == sel) {
1069 current_shader[sel->type]->cso = NULL;
1070 current_shader[sel->type]->current = NULL;
1071 }
1072
1073 while (p) {
1074 c = p->next_variant;
1075 switch (sel->type) {
1076 case PIPE_SHADER_VERTEX:
1077 if (p->key.vs.as_ls)
1078 si_pm4_delete_state(sctx, ls, p->pm4);
1079 else if (p->key.vs.as_es)
1080 si_pm4_delete_state(sctx, es, p->pm4);
1081 else
1082 si_pm4_delete_state(sctx, vs, p->pm4);
1083 break;
1084 case PIPE_SHADER_TESS_CTRL:
1085 si_pm4_delete_state(sctx, hs, p->pm4);
1086 break;
1087 case PIPE_SHADER_TESS_EVAL:
1088 if (p->key.tes.as_es)
1089 si_pm4_delete_state(sctx, es, p->pm4);
1090 else
1091 si_pm4_delete_state(sctx, vs, p->pm4);
1092 break;
1093 case PIPE_SHADER_GEOMETRY:
1094 si_pm4_delete_state(sctx, gs, p->pm4);
1095 si_pm4_delete_state(sctx, vs, p->gs_copy_shader->pm4);
1096 break;
1097 case PIPE_SHADER_FRAGMENT:
1098 si_pm4_delete_state(sctx, ps, p->pm4);
1099 break;
1100 }
1101
1102 si_shader_destroy(p);
1103 free(p);
1104 p = c;
1105 }
1106
1107 pipe_mutex_destroy(sel->mutex);
1108 free(sel->tokens);
1109 free(sel);
1110 }
1111
1112 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
1113 struct si_shader *vs, unsigned name,
1114 unsigned index, unsigned interpolate)
1115 {
1116 struct tgsi_shader_info *vsinfo = &vs->selector->info;
1117 unsigned j, ps_input_cntl = 0;
1118
1119 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
1120 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
1121 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1122
1123 if (name == TGSI_SEMANTIC_PCOORD ||
1124 (name == TGSI_SEMANTIC_TEXCOORD &&
1125 sctx->sprite_coord_enable & (1 << index))) {
1126 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
1127 }
1128
1129 for (j = 0; j < vsinfo->num_outputs; j++) {
1130 if (name == vsinfo->output_semantic_name[j] &&
1131 index == vsinfo->output_semantic_index[j]) {
1132 ps_input_cntl |= S_028644_OFFSET(vs->vs_output_param_offset[j]);
1133 break;
1134 }
1135 }
1136
1137 if (name == TGSI_SEMANTIC_PRIMID)
1138 /* PrimID is written after the last output. */
1139 ps_input_cntl |= S_028644_OFFSET(vs->vs_output_param_offset[vsinfo->num_outputs]);
1140 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
1141 /* No corresponding output found, load defaults into input.
1142 * Don't set any other bits.
1143 * (FLAT_SHADE=1 completely changes behavior) */
1144 ps_input_cntl = S_028644_OFFSET(0x20);
1145 }
1146 return ps_input_cntl;
1147 }
1148
1149 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
1150 {
1151 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1152 struct si_shader *ps = sctx->ps_shader.current;
1153 struct si_shader *vs = si_get_vs_state(sctx);
1154 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
1155 unsigned i, num_interp, num_written = 0, bcol_interp[2];
1156
1157 if (!ps || !ps->selector->info.num_inputs)
1158 return;
1159
1160 num_interp = si_get_ps_num_interp(ps);
1161 assert(num_interp > 0);
1162 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
1163
1164 for (i = 0; i < psinfo->num_inputs; i++) {
1165 unsigned name = psinfo->input_semantic_name[i];
1166 unsigned index = psinfo->input_semantic_index[i];
1167 unsigned interpolate = psinfo->input_interpolate[i];
1168
1169 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
1170 interpolate));
1171 num_written++;
1172
1173 if (name == TGSI_SEMANTIC_COLOR) {
1174 assert(index < ARRAY_SIZE(bcol_interp));
1175 bcol_interp[index] = interpolate;
1176 }
1177 }
1178
1179 if (ps->key.ps.color_two_side) {
1180 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
1181
1182 for (i = 0; i < 2; i++) {
1183 if (!(psinfo->colors_read & (0xf << (i * 4))))
1184 continue;
1185
1186 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
1187 i, bcol_interp[i]));
1188 num_written++;
1189 }
1190 }
1191 assert(num_interp == num_written);
1192 }
1193
1194 /**
1195 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
1196 */
1197 static void si_init_config_add_vgt_flush(struct si_context *sctx)
1198 {
1199 if (sctx->init_config_has_vgt_flush)
1200 return;
1201
1202 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
1203 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
1204 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1205 si_pm4_cmd_end(sctx->init_config, false);
1206 sctx->init_config_has_vgt_flush = true;
1207 }
1208
1209 /* Initialize state related to ESGS / GSVS ring buffers */
1210 static bool si_update_gs_ring_buffers(struct si_context *sctx)
1211 {
1212 struct si_shader_selector *es =
1213 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
1214 struct si_shader_selector *gs = sctx->gs_shader.cso;
1215 struct si_pm4_state *pm4;
1216
1217 /* Chip constants. */
1218 unsigned num_se = sctx->screen->b.info.max_se;
1219 unsigned wave_size = 64;
1220 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1221 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1222 unsigned alignment = 256 * num_se;
1223 /* The maximum size is 63.999 MB per SE. */
1224 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1225
1226 /* Calculate the minimum size. */
1227 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
1228 wave_size, alignment);
1229
1230 /* These are recommended sizes, not minimum sizes. */
1231 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1232 es->esgs_itemsize * gs->gs_input_verts_per_prim;
1233 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1234 gs->max_gsvs_emit_size * (gs->max_gs_stream + 1);
1235
1236 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1237 esgs_ring_size = align(esgs_ring_size, alignment);
1238 gsvs_ring_size = align(gsvs_ring_size, alignment);
1239
1240 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1241 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1242
1243 /* Some rings don't have to be allocated if shaders don't use them.
1244 * (e.g. no varyings between ES and GS or GS and VS)
1245 */
1246 bool update_esgs = esgs_ring_size &&
1247 (!sctx->esgs_ring ||
1248 sctx->esgs_ring->width0 < esgs_ring_size);
1249 bool update_gsvs = gsvs_ring_size &&
1250 (!sctx->gsvs_ring ||
1251 sctx->gsvs_ring->width0 < gsvs_ring_size);
1252
1253 if (!update_esgs && !update_gsvs)
1254 return true;
1255
1256 if (update_esgs) {
1257 pipe_resource_reference(&sctx->esgs_ring, NULL);
1258 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1259 PIPE_USAGE_DEFAULT,
1260 esgs_ring_size);
1261 if (!sctx->esgs_ring)
1262 return false;
1263 }
1264
1265 if (update_gsvs) {
1266 pipe_resource_reference(&sctx->gsvs_ring, NULL);
1267 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1268 PIPE_USAGE_DEFAULT,
1269 gsvs_ring_size);
1270 if (!sctx->gsvs_ring)
1271 return false;
1272 }
1273
1274 /* Create the "init_config_gs_rings" state. */
1275 pm4 = CALLOC_STRUCT(si_pm4_state);
1276 if (!pm4)
1277 return false;
1278
1279 if (sctx->b.chip_class >= CIK) {
1280 if (sctx->esgs_ring)
1281 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
1282 sctx->esgs_ring->width0 / 256);
1283 if (sctx->gsvs_ring)
1284 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
1285 sctx->gsvs_ring->width0 / 256);
1286 } else {
1287 if (sctx->esgs_ring)
1288 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
1289 sctx->esgs_ring->width0 / 256);
1290 if (sctx->gsvs_ring)
1291 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
1292 sctx->gsvs_ring->width0 / 256);
1293 }
1294
1295 /* Set the state. */
1296 if (sctx->init_config_gs_rings)
1297 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
1298 sctx->init_config_gs_rings = pm4;
1299
1300 if (!sctx->init_config_has_vgt_flush) {
1301 si_init_config_add_vgt_flush(sctx);
1302 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1303 }
1304
1305 /* Flush the context to re-emit both init_config states. */
1306 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1307 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1308
1309 /* Set ring bindings. */
1310 if (sctx->esgs_ring) {
1311 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
1312 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1313 true, true, 4, 64, 0);
1314 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
1315 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1316 false, false, 0, 0, 0);
1317 }
1318 if (sctx->gsvs_ring)
1319 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
1320 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
1321 false, false, 0, 0, 0);
1322 return true;
1323 }
1324
1325 static void si_update_gsvs_ring_bindings(struct si_context *sctx)
1326 {
1327 unsigned gsvs_itemsize = sctx->gs_shader.cso->max_gsvs_emit_size;
1328 uint64_t offset;
1329
1330 if (!sctx->gsvs_ring || gsvs_itemsize == sctx->last_gsvs_itemsize)
1331 return;
1332
1333 sctx->last_gsvs_itemsize = gsvs_itemsize;
1334
1335 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
1336 sctx->gsvs_ring, gsvs_itemsize,
1337 64, true, true, 4, 16, 0);
1338
1339 offset = gsvs_itemsize * 64;
1340 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_1,
1341 sctx->gsvs_ring, gsvs_itemsize,
1342 64, true, true, 4, 16, offset);
1343
1344 offset = (gsvs_itemsize * 2) * 64;
1345 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_2,
1346 sctx->gsvs_ring, gsvs_itemsize,
1347 64, true, true, 4, 16, offset);
1348
1349 offset = (gsvs_itemsize * 3) * 64;
1350 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_3,
1351 sctx->gsvs_ring, gsvs_itemsize,
1352 64, true, true, 4, 16, offset);
1353 }
1354
1355 /**
1356 * @returns 1 if \p sel has been updated to use a new scratch buffer
1357 * 0 if not
1358 * < 0 if there was a failure
1359 */
1360 static int si_update_scratch_buffer(struct si_context *sctx,
1361 struct si_shader *shader)
1362 {
1363 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
1364 int r;
1365
1366 if (!shader)
1367 return 0;
1368
1369 /* This shader doesn't need a scratch buffer */
1370 if (shader->config.scratch_bytes_per_wave == 0)
1371 return 0;
1372
1373 /* This shader is already configured to use the current
1374 * scratch buffer. */
1375 if (shader->scratch_bo == sctx->scratch_buffer)
1376 return 0;
1377
1378 assert(sctx->scratch_buffer);
1379
1380 si_shader_apply_scratch_relocs(sctx, shader, scratch_va);
1381
1382 /* Replace the shader bo with a new bo that has the relocs applied. */
1383 r = si_shader_binary_upload(sctx->screen, shader);
1384 if (r)
1385 return r;
1386
1387 /* Update the shader state to use the new shader bo. */
1388 si_shader_init_pm4_state(shader);
1389
1390 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
1391
1392 return 1;
1393 }
1394
1395 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
1396 {
1397 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
1398 }
1399
1400 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
1401 {
1402 return shader ? shader->config.scratch_bytes_per_wave : 0;
1403 }
1404
1405 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
1406 {
1407 unsigned bytes = 0;
1408
1409 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
1410 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
1411 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
1412 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tcs_shader.current));
1413 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
1414 return bytes;
1415 }
1416
1417 static bool si_update_spi_tmpring_size(struct si_context *sctx)
1418 {
1419 unsigned current_scratch_buffer_size =
1420 si_get_current_scratch_buffer_size(sctx);
1421 unsigned scratch_bytes_per_wave =
1422 si_get_max_scratch_bytes_per_wave(sctx);
1423 unsigned scratch_needed_size = scratch_bytes_per_wave *
1424 sctx->scratch_waves;
1425 unsigned spi_tmpring_size;
1426 int r;
1427
1428 if (scratch_needed_size > 0) {
1429 if (scratch_needed_size > current_scratch_buffer_size) {
1430 /* Create a bigger scratch buffer */
1431 pipe_resource_reference(
1432 (struct pipe_resource**)&sctx->scratch_buffer,
1433 NULL);
1434
1435 sctx->scratch_buffer =
1436 si_resource_create_custom(&sctx->screen->b.b,
1437 PIPE_USAGE_DEFAULT, scratch_needed_size);
1438 if (!sctx->scratch_buffer)
1439 return false;
1440 sctx->emit_scratch_reloc = true;
1441 }
1442
1443 /* Update the shaders, so they are using the latest scratch. The
1444 * scratch buffer may have been changed since these shaders were
1445 * last used, so we still need to try to update them, even if
1446 * they require scratch buffers smaller than the current size.
1447 */
1448 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
1449 if (r < 0)
1450 return false;
1451 if (r == 1)
1452 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
1453
1454 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
1455 if (r < 0)
1456 return false;
1457 if (r == 1)
1458 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1459
1460 r = si_update_scratch_buffer(sctx, sctx->tcs_shader.current);
1461 if (r < 0)
1462 return false;
1463 if (r == 1)
1464 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1465
1466 /* VS can be bound as LS, ES, or VS. */
1467 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
1468 if (r < 0)
1469 return false;
1470 if (r == 1) {
1471 if (sctx->tes_shader.current)
1472 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1473 else if (sctx->gs_shader.current)
1474 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1475 else
1476 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1477 }
1478
1479 /* TES can be bound as ES or VS. */
1480 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
1481 if (r < 0)
1482 return false;
1483 if (r == 1) {
1484 if (sctx->gs_shader.current)
1485 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1486 else
1487 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1488 }
1489 }
1490
1491 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
1492 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
1493 "scratch size should already be aligned correctly.");
1494
1495 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
1496 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
1497 if (spi_tmpring_size != sctx->spi_tmpring_size) {
1498 sctx->spi_tmpring_size = spi_tmpring_size;
1499 sctx->emit_scratch_reloc = true;
1500 }
1501 return true;
1502 }
1503
1504 static void si_init_tess_factor_ring(struct si_context *sctx)
1505 {
1506 assert(!sctx->tf_ring);
1507
1508 sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1509 PIPE_USAGE_DEFAULT,
1510 32768 * sctx->screen->b.info.max_se);
1511 if (!sctx->tf_ring)
1512 return;
1513
1514 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
1515
1516 si_init_config_add_vgt_flush(sctx);
1517
1518 /* Append these registers to the init config state. */
1519 if (sctx->b.chip_class >= CIK) {
1520 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
1521 S_030938_SIZE(sctx->tf_ring->width0 / 4));
1522 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
1523 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1524 } else {
1525 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
1526 S_008988_SIZE(sctx->tf_ring->width0 / 4));
1527 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
1528 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1529 }
1530
1531 /* Flush the context to re-emit the init_config state.
1532 * This is done only once in a lifetime of a context.
1533 */
1534 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1535 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1536 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1537
1538 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_TESS_CTRL,
1539 SI_RING_TESS_FACTOR, sctx->tf_ring, 0,
1540 sctx->tf_ring->width0, false, false, 0, 0, 0);
1541 }
1542
1543 /**
1544 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
1545 * VS passes its outputs to TES directly, so the fixed-function shader only
1546 * has to write TESSOUTER and TESSINNER.
1547 */
1548 static void si_generate_fixed_func_tcs(struct si_context *sctx)
1549 {
1550 struct ureg_src const0, const1;
1551 struct ureg_dst tessouter, tessinner;
1552 struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
1553
1554 if (!ureg)
1555 return; /* if we get here, we're screwed */
1556
1557 assert(!sctx->fixed_func_tcs_shader.cso);
1558
1559 ureg_DECL_constant2D(ureg, 0, 1, SI_DRIVER_STATE_CONST_BUF);
1560 const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 0),
1561 SI_DRIVER_STATE_CONST_BUF);
1562 const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 1),
1563 SI_DRIVER_STATE_CONST_BUF);
1564
1565 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1566 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1567
1568 ureg_MOV(ureg, tessouter, const0);
1569 ureg_MOV(ureg, tessinner, const1);
1570 ureg_END(ureg);
1571
1572 sctx->fixed_func_tcs_shader.cso =
1573 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
1574 }
1575
1576 static void si_update_vgt_shader_config(struct si_context *sctx)
1577 {
1578 /* Calculate the index of the config.
1579 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
1580 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
1581 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
1582
1583 if (!*pm4) {
1584 uint32_t stages = 0;
1585
1586 *pm4 = CALLOC_STRUCT(si_pm4_state);
1587
1588 if (sctx->tes_shader.cso) {
1589 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
1590 S_028B54_HS_EN(1);
1591
1592 if (sctx->gs_shader.cso)
1593 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
1594 S_028B54_GS_EN(1) |
1595 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1596 else
1597 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
1598 } else if (sctx->gs_shader.cso) {
1599 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1600 S_028B54_GS_EN(1) |
1601 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1602 }
1603
1604 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
1605 }
1606 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
1607 }
1608
1609 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
1610 {
1611 struct pipe_stream_output_info *so = &shader->so;
1612 uint32_t enabled_stream_buffers_mask = 0;
1613 int i;
1614
1615 for (i = 0; i < so->num_outputs; i++)
1616 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
1617 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
1618 sctx->b.streamout.stride_in_dw = shader->so.stride;
1619 }
1620
1621 bool si_update_shaders(struct si_context *sctx)
1622 {
1623 struct pipe_context *ctx = (struct pipe_context*)sctx;
1624 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1625 int r;
1626
1627 /* Update stages before GS. */
1628 if (sctx->tes_shader.cso) {
1629 if (!sctx->tf_ring) {
1630 si_init_tess_factor_ring(sctx);
1631 if (!sctx->tf_ring)
1632 return false;
1633 }
1634
1635 /* VS as LS */
1636 r = si_shader_select(ctx, &sctx->vs_shader);
1637 if (r)
1638 return false;
1639 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1640
1641 if (sctx->tcs_shader.cso) {
1642 r = si_shader_select(ctx, &sctx->tcs_shader);
1643 if (r)
1644 return false;
1645 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1646 } else {
1647 if (!sctx->fixed_func_tcs_shader.cso) {
1648 si_generate_fixed_func_tcs(sctx);
1649 if (!sctx->fixed_func_tcs_shader.cso)
1650 return false;
1651 }
1652
1653 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader);
1654 if (r)
1655 return false;
1656 si_pm4_bind_state(sctx, hs,
1657 sctx->fixed_func_tcs_shader.current->pm4);
1658 }
1659
1660 r = si_shader_select(ctx, &sctx->tes_shader);
1661 if (r)
1662 return false;
1663
1664 if (sctx->gs_shader.cso) {
1665 /* TES as ES */
1666 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1667 } else {
1668 /* TES as VS */
1669 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1670 si_update_so(sctx, sctx->tes_shader.cso);
1671 }
1672 } else if (sctx->gs_shader.cso) {
1673 /* VS as ES */
1674 r = si_shader_select(ctx, &sctx->vs_shader);
1675 if (r)
1676 return false;
1677 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1678 } else {
1679 /* VS as VS */
1680 r = si_shader_select(ctx, &sctx->vs_shader);
1681 if (r)
1682 return false;
1683 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1684 si_update_so(sctx, sctx->vs_shader.cso);
1685 }
1686
1687 /* Update GS. */
1688 if (sctx->gs_shader.cso) {
1689 r = si_shader_select(ctx, &sctx->gs_shader);
1690 if (r)
1691 return false;
1692 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1693 si_pm4_bind_state(sctx, vs, sctx->gs_shader.current->gs_copy_shader->pm4);
1694 si_update_so(sctx, sctx->gs_shader.cso);
1695
1696 if (!si_update_gs_ring_buffers(sctx))
1697 return false;
1698
1699 si_update_gsvs_ring_bindings(sctx);
1700 } else {
1701 si_pm4_bind_state(sctx, gs, NULL);
1702 si_pm4_bind_state(sctx, es, NULL);
1703 }
1704
1705 si_update_vgt_shader_config(sctx);
1706
1707 if (sctx->ps_shader.cso) {
1708 unsigned db_shader_control =
1709 sctx->ps_shader.cso->db_shader_control |
1710 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
1711
1712 r = si_shader_select(ctx, &sctx->ps_shader);
1713 if (r)
1714 return false;
1715 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
1716
1717 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
1718 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
1719 sctx->flatshade != rs->flatshade) {
1720 sctx->sprite_coord_enable = rs->sprite_coord_enable;
1721 sctx->flatshade = rs->flatshade;
1722 si_mark_atom_dirty(sctx, &sctx->spi_map);
1723 }
1724
1725 if (sctx->b.family == CHIP_STONEY && si_pm4_state_changed(sctx, ps))
1726 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
1727
1728 if (sctx->ps_db_shader_control != db_shader_control) {
1729 sctx->ps_db_shader_control = db_shader_control;
1730 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1731 }
1732
1733 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.ps.poly_line_smoothing) {
1734 sctx->smoothing_enabled = sctx->ps_shader.current->key.ps.poly_line_smoothing;
1735 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1736
1737 if (sctx->b.chip_class == SI)
1738 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1739 }
1740 }
1741
1742 if (si_pm4_state_changed(sctx, ls) ||
1743 si_pm4_state_changed(sctx, hs) ||
1744 si_pm4_state_changed(sctx, es) ||
1745 si_pm4_state_changed(sctx, gs) ||
1746 si_pm4_state_changed(sctx, vs) ||
1747 si_pm4_state_changed(sctx, ps)) {
1748 if (!si_update_spi_tmpring_size(sctx))
1749 return false;
1750 }
1751 return true;
1752 }
1753
1754 void si_init_shader_functions(struct si_context *sctx)
1755 {
1756 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
1757
1758 sctx->b.b.create_vs_state = si_create_shader_selector;
1759 sctx->b.b.create_tcs_state = si_create_shader_selector;
1760 sctx->b.b.create_tes_state = si_create_shader_selector;
1761 sctx->b.b.create_gs_state = si_create_shader_selector;
1762 sctx->b.b.create_fs_state = si_create_shader_selector;
1763
1764 sctx->b.b.bind_vs_state = si_bind_vs_shader;
1765 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
1766 sctx->b.b.bind_tes_state = si_bind_tes_shader;
1767 sctx->b.b.bind_gs_state = si_bind_gs_shader;
1768 sctx->b.b.bind_fs_state = si_bind_ps_shader;
1769
1770 sctx->b.b.delete_vs_state = si_delete_shader_selector;
1771 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
1772 sctx->b.b.delete_tes_state = si_delete_shader_selector;
1773 sctx->b.b.delete_gs_state = si_delete_shader_selector;
1774 sctx->b.b.delete_fs_state = si_delete_shader_selector;
1775 }