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radeonsi: add struct si_shader_config
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "si_shader.h"
30 #include "sid.h"
31 #include "radeon/r600_cs.h"
32
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/u_memory.h"
36 #include "util/u_prim.h"
37 #include "util/u_simple_shaders.h"
38
39 static void si_set_tesseval_regs(struct si_shader *shader,
40 struct si_pm4_state *pm4)
41 {
42 struct tgsi_shader_info *info = &shader->selector->info;
43 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
44 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
45 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
46 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
47 unsigned type, partitioning, topology;
48
49 switch (tes_prim_mode) {
50 case PIPE_PRIM_LINES:
51 type = V_028B6C_TESS_ISOLINE;
52 break;
53 case PIPE_PRIM_TRIANGLES:
54 type = V_028B6C_TESS_TRIANGLE;
55 break;
56 case PIPE_PRIM_QUADS:
57 type = V_028B6C_TESS_QUAD;
58 break;
59 default:
60 assert(0);
61 return;
62 }
63
64 switch (tes_spacing) {
65 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
66 partitioning = V_028B6C_PART_FRAC_ODD;
67 break;
68 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
69 partitioning = V_028B6C_PART_FRAC_EVEN;
70 break;
71 case PIPE_TESS_SPACING_EQUAL:
72 partitioning = V_028B6C_PART_INTEGER;
73 break;
74 default:
75 assert(0);
76 return;
77 }
78
79 if (tes_point_mode)
80 topology = V_028B6C_OUTPUT_POINT;
81 else if (tes_prim_mode == PIPE_PRIM_LINES)
82 topology = V_028B6C_OUTPUT_LINE;
83 else if (tes_vertex_order_cw)
84 /* for some reason, this must be the other way around */
85 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
86 else
87 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
88
89 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
90 S_028B6C_TYPE(type) |
91 S_028B6C_PARTITIONING(partitioning) |
92 S_028B6C_TOPOLOGY(topology));
93 }
94
95 static void si_shader_ls(struct si_shader *shader)
96 {
97 struct si_pm4_state *pm4;
98 unsigned num_sgprs, num_user_sgprs;
99 unsigned vgpr_comp_cnt;
100 uint64_t va;
101
102 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
103 if (!pm4)
104 return;
105
106 va = shader->bo->gpu_address;
107 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
108
109 /* We need at least 2 components for LS.
110 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
111 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 1;
112
113 num_user_sgprs = SI_LS_NUM_USER_SGPR;
114 num_sgprs = shader->config.num_sgprs;
115 if (num_user_sgprs > num_sgprs) {
116 /* Last 2 reserved SGPRs are used for VCC */
117 num_sgprs = num_user_sgprs + 2;
118 }
119 assert(num_sgprs <= 104);
120
121 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
122 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
123
124 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
125 S_00B528_SGPRS((num_sgprs - 1) / 8) |
126 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
127 S_00B528_DX10_CLAMP(shader->dx10_clamp_mode);
128 shader->config.rsrc2 = S_00B52C_USER_SGPR(num_user_sgprs) |
129 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
130 }
131
132 static void si_shader_hs(struct si_shader *shader)
133 {
134 struct si_pm4_state *pm4;
135 unsigned num_sgprs, num_user_sgprs;
136 uint64_t va;
137
138 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
139 if (!pm4)
140 return;
141
142 va = shader->bo->gpu_address;
143 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
144
145 num_user_sgprs = SI_TCS_NUM_USER_SGPR;
146 num_sgprs = shader->config.num_sgprs;
147 /* One SGPR after user SGPRs is pre-loaded with tessellation factor
148 * buffer offset. */
149 if ((num_user_sgprs + 1) > num_sgprs) {
150 /* Last 2 reserved SGPRs are used for VCC */
151 num_sgprs = num_user_sgprs + 1 + 2;
152 }
153 assert(num_sgprs <= 104);
154
155 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
156 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
157 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
158 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
159 S_00B428_SGPRS((num_sgprs - 1) / 8) |
160 S_00B428_DX10_CLAMP(shader->dx10_clamp_mode));
161 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
162 S_00B42C_USER_SGPR(num_user_sgprs) |
163 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
164 }
165
166 static void si_shader_es(struct si_shader *shader)
167 {
168 struct si_pm4_state *pm4;
169 unsigned num_sgprs, num_user_sgprs;
170 unsigned vgpr_comp_cnt;
171 uint64_t va;
172
173 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
174
175 if (!pm4)
176 return;
177
178 va = shader->bo->gpu_address;
179 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
180
181 if (shader->selector->type == PIPE_SHADER_VERTEX) {
182 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
183 num_user_sgprs = SI_ES_NUM_USER_SGPR;
184 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
185 vgpr_comp_cnt = 3; /* all components are needed for TES */
186 num_user_sgprs = SI_TES_NUM_USER_SGPR;
187 } else
188 unreachable("invalid shader selector type");
189
190 num_sgprs = shader->config.num_sgprs;
191 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
192 if ((num_user_sgprs + 1) > num_sgprs) {
193 /* Last 2 reserved SGPRs are used for VCC */
194 num_sgprs = num_user_sgprs + 1 + 2;
195 }
196 assert(num_sgprs <= 104);
197
198 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
199 shader->selector->esgs_itemsize / 4);
200 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
201 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
202 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
203 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
204 S_00B328_SGPRS((num_sgprs - 1) / 8) |
205 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
206 S_00B328_DX10_CLAMP(shader->dx10_clamp_mode));
207 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
208 S_00B32C_USER_SGPR(num_user_sgprs) |
209 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
210
211 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
212 si_set_tesseval_regs(shader, pm4);
213 }
214
215 static void si_shader_gs(struct si_shader *shader)
216 {
217 unsigned gs_vert_itemsize = shader->selector->gsvs_vertex_size;
218 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
219 unsigned gsvs_itemsize = shader->selector->max_gsvs_emit_size >> 2;
220 unsigned gs_num_invocations = shader->selector->gs_num_invocations;
221 unsigned cut_mode;
222 struct si_pm4_state *pm4;
223 unsigned num_sgprs, num_user_sgprs;
224 uint64_t va;
225 unsigned max_stream = shader->selector->max_gs_stream;
226
227 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
228 assert(gsvs_itemsize < (1 << 15));
229
230 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
231
232 if (!pm4)
233 return;
234
235 if (gs_max_vert_out <= 128) {
236 cut_mode = V_028A40_GS_CUT_128;
237 } else if (gs_max_vert_out <= 256) {
238 cut_mode = V_028A40_GS_CUT_256;
239 } else if (gs_max_vert_out <= 512) {
240 cut_mode = V_028A40_GS_CUT_512;
241 } else {
242 assert(gs_max_vert_out <= 1024);
243 cut_mode = V_028A40_GS_CUT_1024;
244 }
245
246 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
247 S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
248 S_028A40_CUT_MODE(cut_mode)|
249 S_028A40_ES_WRITE_OPTIMIZE(1) |
250 S_028A40_GS_WRITE_OPTIMIZE(1));
251
252 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
253 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize * ((max_stream >= 2) ? 2 : 1));
254 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize * ((max_stream >= 3) ? 3 : 1));
255
256 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize * (max_stream + 1));
257
258 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, gs_max_vert_out);
259
260 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize >> 2);
261 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? gs_vert_itemsize >> 2 : 0);
262 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? gs_vert_itemsize >> 2 : 0);
263 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? gs_vert_itemsize >> 2 : 0);
264
265 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
266 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
267 S_028B90_ENABLE(gs_num_invocations > 0));
268
269 va = shader->bo->gpu_address;
270 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
271 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
272 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
273
274 num_user_sgprs = SI_GS_NUM_USER_SGPR;
275 num_sgprs = shader->config.num_sgprs;
276 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
277 if ((num_user_sgprs + 2) > num_sgprs) {
278 /* Last 2 reserved SGPRs are used for VCC */
279 num_sgprs = num_user_sgprs + 2 + 2;
280 }
281 assert(num_sgprs <= 104);
282
283 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
284 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
285 S_00B228_SGPRS((num_sgprs - 1) / 8) |
286 S_00B228_DX10_CLAMP(shader->dx10_clamp_mode));
287 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
288 S_00B22C_USER_SGPR(num_user_sgprs) |
289 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
290 }
291
292 static void si_shader_vs(struct si_shader *shader)
293 {
294 struct si_pm4_state *pm4;
295 unsigned num_sgprs, num_user_sgprs;
296 unsigned nparams, vgpr_comp_cnt;
297 uint64_t va;
298 unsigned window_space =
299 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
300 bool enable_prim_id = si_vs_exports_prim_id(shader);
301
302 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
303
304 if (!pm4)
305 return;
306
307 /* If this is the GS copy shader, the GS state writes this register.
308 * Otherwise, the VS state writes it.
309 */
310 if (!shader->is_gs_copy_shader) {
311 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
312 S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
313 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
314 } else
315 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
316
317 va = shader->bo->gpu_address;
318 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
319
320 if (shader->is_gs_copy_shader) {
321 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
322 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
323 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
324 vgpr_comp_cnt = shader->uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
325 num_user_sgprs = SI_VS_NUM_USER_SGPR;
326 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
327 vgpr_comp_cnt = 3; /* all components are needed for TES */
328 num_user_sgprs = SI_TES_NUM_USER_SGPR;
329 } else
330 unreachable("invalid shader selector type");
331
332 num_sgprs = shader->config.num_sgprs;
333 if (num_user_sgprs > num_sgprs) {
334 /* Last 2 reserved SGPRs are used for VCC */
335 num_sgprs = num_user_sgprs + 2;
336 }
337 assert(num_sgprs <= 104);
338
339 /* VS is required to export at least one param. */
340 nparams = MAX2(shader->nr_param_exports, 1);
341 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
342 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
343
344 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
345 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
346 S_02870C_POS1_EXPORT_FORMAT(shader->nr_pos_exports > 1 ?
347 V_02870C_SPI_SHADER_4COMP :
348 V_02870C_SPI_SHADER_NONE) |
349 S_02870C_POS2_EXPORT_FORMAT(shader->nr_pos_exports > 2 ?
350 V_02870C_SPI_SHADER_4COMP :
351 V_02870C_SPI_SHADER_NONE) |
352 S_02870C_POS3_EXPORT_FORMAT(shader->nr_pos_exports > 3 ?
353 V_02870C_SPI_SHADER_4COMP :
354 V_02870C_SPI_SHADER_NONE));
355
356 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
357 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
358 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
359 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
360 S_00B128_SGPRS((num_sgprs - 1) / 8) |
361 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
362 S_00B128_DX10_CLAMP(shader->dx10_clamp_mode));
363 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
364 S_00B12C_USER_SGPR(num_user_sgprs) |
365 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
366 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
367 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
368 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
369 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
370 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
371 if (window_space)
372 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
373 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
374 else
375 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
376 S_028818_VTX_W0_FMT(1) |
377 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
378 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
379 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
380
381 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
382 si_set_tesseval_regs(shader, pm4);
383 }
384
385 static void si_shader_ps(struct si_shader *shader)
386 {
387 struct tgsi_shader_info *info = &shader->selector->info;
388 struct si_pm4_state *pm4;
389 unsigned i, spi_ps_in_control;
390 unsigned spi_shader_col_format = 0, cb_shader_mask = 0;
391 unsigned colors_written, export_16bpc;
392 unsigned num_sgprs, num_user_sgprs;
393 unsigned spi_baryc_cntl = 0;
394 uint64_t va;
395 bool has_centroid;
396
397 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
398
399 if (!pm4)
400 return;
401
402 for (i = 0; i < info->num_inputs; i++) {
403 switch (info->input_semantic_name[i]) {
404 case TGSI_SEMANTIC_POSITION:
405 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
406 * Possible vaules:
407 * 0 -> Position = pixel center (default)
408 * 1 -> Position = pixel centroid
409 * 2 -> Position = at sample position
410 */
411 switch (info->input_interpolate_loc[i]) {
412 case TGSI_INTERPOLATE_LOC_CENTROID:
413 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
414 break;
415 case TGSI_INTERPOLATE_LOC_SAMPLE:
416 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
417 break;
418 }
419
420 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
421 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
422 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
423 break;
424 }
425 }
426
427 /* Find out what SPI_SHADER_COL_FORMAT and CB_SHADER_MASK should be. */
428 colors_written = info->colors_written;
429 export_16bpc = shader->key.ps.export_16bpc;
430
431 if (info->colors_written == 0x1 &&
432 info->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS]) {
433 colors_written |= (1 << (shader->key.ps.last_cbuf + 1)) - 1;
434 }
435
436 while (colors_written) {
437 i = u_bit_scan(&colors_written);
438 if (export_16bpc & (1 << i))
439 spi_shader_col_format |= V_028714_SPI_SHADER_FP16_ABGR << (4 * i);
440 else
441 spi_shader_col_format |= V_028714_SPI_SHADER_32_ABGR << (4 * i);
442 cb_shader_mask |= 0xf << (4 * i);
443 }
444
445 /* Set interpolation controls. */
446 has_centroid = G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena) ||
447 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena);
448
449 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->nparam) |
450 S_0286D8_BC_OPTIMIZE_DISABLE(has_centroid);
451
452 /* Set registers. */
453 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
454 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
455
456 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
457 info->writes_samplemask ? V_028710_SPI_SHADER_32_ABGR :
458 info->writes_stencil ? V_028710_SPI_SHADER_32_GR :
459 info->writes_z ? V_028710_SPI_SHADER_32_R :
460 V_028710_SPI_SHADER_ZERO);
461
462 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
463 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
464
465 va = shader->bo->gpu_address;
466 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
467 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
468 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
469
470 num_user_sgprs = SI_PS_NUM_USER_SGPR;
471 num_sgprs = shader->config.num_sgprs;
472 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
473 if ((num_user_sgprs + 1) > num_sgprs) {
474 /* Last 2 reserved SGPRs are used for VCC */
475 num_sgprs = num_user_sgprs + 1 + 2;
476 }
477 assert(num_sgprs <= 104);
478
479 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
480 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
481 S_00B028_SGPRS((num_sgprs - 1) / 8) |
482 S_00B028_DX10_CLAMP(shader->dx10_clamp_mode));
483 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
484 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
485 S_00B02C_USER_SGPR(num_user_sgprs) |
486 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
487 }
488
489 static void si_shader_init_pm4_state(struct si_shader *shader)
490 {
491
492 if (shader->pm4)
493 si_pm4_free_state_simple(shader->pm4);
494
495 switch (shader->selector->type) {
496 case PIPE_SHADER_VERTEX:
497 if (shader->key.vs.as_ls)
498 si_shader_ls(shader);
499 else if (shader->key.vs.as_es)
500 si_shader_es(shader);
501 else
502 si_shader_vs(shader);
503 break;
504 case PIPE_SHADER_TESS_CTRL:
505 si_shader_hs(shader);
506 break;
507 case PIPE_SHADER_TESS_EVAL:
508 if (shader->key.tes.as_es)
509 si_shader_es(shader);
510 else
511 si_shader_vs(shader);
512 break;
513 case PIPE_SHADER_GEOMETRY:
514 si_shader_gs(shader);
515 si_shader_vs(shader->gs_copy_shader);
516 break;
517 case PIPE_SHADER_FRAGMENT:
518 si_shader_ps(shader);
519 break;
520 default:
521 assert(0);
522 }
523 }
524
525 static unsigned si_get_alpha_test_func(struct si_context *sctx)
526 {
527 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
528 if (sctx->queued.named.dsa &&
529 !sctx->framebuffer.cb0_is_integer)
530 return sctx->queued.named.dsa->alpha_func;
531
532 return PIPE_FUNC_ALWAYS;
533 }
534
535 /* Compute the key for the hw shader variant */
536 static inline void si_shader_selector_key(struct pipe_context *ctx,
537 struct si_shader_selector *sel,
538 union si_shader_key *key)
539 {
540 struct si_context *sctx = (struct si_context *)ctx;
541 unsigned i;
542
543 memset(key, 0, sizeof(*key));
544
545 switch (sel->type) {
546 case PIPE_SHADER_VERTEX:
547 if (sctx->vertex_elements)
548 for (i = 0; i < sctx->vertex_elements->count; ++i)
549 key->vs.instance_divisors[i] =
550 sctx->vertex_elements->elements[i].instance_divisor;
551
552 if (sctx->tes_shader.cso)
553 key->vs.as_ls = 1;
554 else if (sctx->gs_shader.cso)
555 key->vs.as_es = 1;
556
557 if (!sctx->gs_shader.cso && sctx->ps_shader.cso &&
558 sctx->ps_shader.cso->info.uses_primid)
559 key->vs.export_prim_id = 1;
560 break;
561 case PIPE_SHADER_TESS_CTRL:
562 key->tcs.prim_mode =
563 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
564 break;
565 case PIPE_SHADER_TESS_EVAL:
566 if (sctx->gs_shader.cso)
567 key->tes.as_es = 1;
568 else if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
569 key->tes.export_prim_id = 1;
570 break;
571 case PIPE_SHADER_GEOMETRY:
572 break;
573 case PIPE_SHADER_FRAGMENT: {
574 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
575
576 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
577 sel->info.colors_written == 0x1)
578 key->ps.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
579
580 key->ps.export_16bpc = sctx->framebuffer.export_16bpc;
581
582 if (rs) {
583 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
584 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
585 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
586 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
587
588 key->ps.color_two_side = rs->two_side;
589
590 if (sctx->queued.named.blend) {
591 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
592 rs->multisample_enable &&
593 !sctx->framebuffer.cb0_is_integer;
594 }
595
596 key->ps.poly_stipple = rs->poly_stipple_enable && is_poly;
597 key->ps.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
598 (is_line && rs->line_smooth)) &&
599 sctx->framebuffer.nr_samples <= 1;
600 key->ps.clamp_color = rs->clamp_fragment_color;
601 }
602
603 key->ps.alpha_func = si_get_alpha_test_func(sctx);
604 break;
605 }
606 default:
607 assert(0);
608 }
609 }
610
611 /* Select the hw shader variant depending on the current state. */
612 static int si_shader_select(struct pipe_context *ctx,
613 struct si_shader_ctx_state *state)
614 {
615 struct si_context *sctx = (struct si_context *)ctx;
616 struct si_shader_selector *sel = state->cso;
617 struct si_shader *current = state->current;
618 union si_shader_key key;
619 struct si_shader *iter, *shader = NULL;
620 int r;
621
622 si_shader_selector_key(ctx, sel, &key);
623
624 /* Check if we don't need to change anything.
625 * This path is also used for most shaders that don't need multiple
626 * variants, it will cost just a computation of the key and this
627 * test. */
628 if (likely(current && memcmp(&current->key, &key, sizeof(key)) == 0))
629 return 0;
630
631 pipe_mutex_lock(sel->mutex);
632
633 /* Find the shader variant. */
634 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
635 /* Don't check the "current" shader. We checked it above. */
636 if (current != iter &&
637 memcmp(&iter->key, &key, sizeof(key)) == 0) {
638 state->current = iter;
639 pipe_mutex_unlock(sel->mutex);
640 return 0;
641 }
642 }
643
644 /* Build a new shader. */
645 shader = CALLOC_STRUCT(si_shader);
646 if (!shader) {
647 pipe_mutex_unlock(sel->mutex);
648 return -ENOMEM;
649 }
650 shader->selector = sel;
651 shader->key = key;
652
653 r = si_shader_create(sctx->screen, sctx->tm, shader, &sctx->b.debug);
654 if (unlikely(r)) {
655 R600_ERR("Failed to build shader variant (type=%u) %d\n",
656 sel->type, r);
657 FREE(shader);
658 pipe_mutex_unlock(sel->mutex);
659 return r;
660 }
661 si_shader_init_pm4_state(shader);
662
663 if (!sel->last_variant) {
664 sel->first_variant = shader;
665 sel->last_variant = shader;
666 } else {
667 sel->last_variant->next_variant = shader;
668 sel->last_variant = shader;
669 }
670 state->current = shader;
671 pipe_mutex_unlock(sel->mutex);
672 return 0;
673 }
674
675 static void *si_create_shader_selector(struct pipe_context *ctx,
676 const struct pipe_shader_state *state)
677 {
678 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
679 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
680 int i;
681
682 if (!sel)
683 return NULL;
684
685 sel->tokens = tgsi_dup_tokens(state->tokens);
686 if (!sel->tokens) {
687 FREE(sel);
688 return NULL;
689 }
690
691 sel->so = state->stream_output;
692 tgsi_scan_shader(state->tokens, &sel->info);
693 sel->type = util_pipe_shader_from_tgsi_processor(sel->info.processor);
694 p_atomic_inc(&sscreen->b.num_shaders_created);
695
696 /* First set which opcode uses which (i,j) pair. */
697 if (sel->info.uses_persp_opcode_interp_centroid)
698 sel->info.uses_persp_centroid = true;
699
700 if (sel->info.uses_linear_opcode_interp_centroid)
701 sel->info.uses_linear_centroid = true;
702
703 if (sel->info.uses_persp_opcode_interp_offset ||
704 sel->info.uses_persp_opcode_interp_sample)
705 sel->info.uses_persp_center = true;
706
707 if (sel->info.uses_linear_opcode_interp_offset ||
708 sel->info.uses_linear_opcode_interp_sample)
709 sel->info.uses_linear_center = true;
710
711 /* Determine if the shader has to use a conditional assignment when
712 * emulating force_persample_interp.
713 */
714 sel->forces_persample_interp_for_persp =
715 sel->info.uses_persp_center +
716 sel->info.uses_persp_centroid +
717 sel->info.uses_persp_sample >= 2;
718
719 sel->forces_persample_interp_for_linear =
720 sel->info.uses_linear_center +
721 sel->info.uses_linear_centroid +
722 sel->info.uses_linear_sample >= 2;
723
724 switch (sel->type) {
725 case PIPE_SHADER_GEOMETRY:
726 sel->gs_output_prim =
727 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
728 sel->gs_max_out_vertices =
729 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
730 sel->gs_num_invocations =
731 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
732 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
733 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
734 sel->gs_max_out_vertices;
735
736 sel->max_gs_stream = 0;
737 for (i = 0; i < sel->so.num_outputs; i++)
738 sel->max_gs_stream = MAX2(sel->max_gs_stream,
739 sel->so.output[i].stream);
740
741 sel->gs_input_verts_per_prim =
742 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
743 break;
744
745 case PIPE_SHADER_VERTEX:
746 case PIPE_SHADER_TESS_CTRL:
747 case PIPE_SHADER_TESS_EVAL:
748 for (i = 0; i < sel->info.num_outputs; i++) {
749 unsigned name = sel->info.output_semantic_name[i];
750 unsigned index = sel->info.output_semantic_index[i];
751
752 switch (name) {
753 case TGSI_SEMANTIC_TESSINNER:
754 case TGSI_SEMANTIC_TESSOUTER:
755 case TGSI_SEMANTIC_PATCH:
756 sel->patch_outputs_written |=
757 1llu << si_shader_io_get_unique_index(name, index);
758 break;
759 default:
760 sel->outputs_written |=
761 1llu << si_shader_io_get_unique_index(name, index);
762 }
763 }
764 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
765 break;
766 }
767
768 /* DB_SHADER_CONTROL */
769 sel->db_shader_control =
770 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
771 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
772 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
773 S_02880C_KILL_ENABLE(sel->info.uses_kill);
774
775 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
776 case TGSI_FS_DEPTH_LAYOUT_GREATER:
777 sel->db_shader_control |=
778 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
779 break;
780 case TGSI_FS_DEPTH_LAYOUT_LESS:
781 sel->db_shader_control |=
782 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
783 break;
784 }
785
786 /* Pre-compilation. */
787 if (sscreen->b.debug_flags & DBG_PRECOMPILE) {
788 struct si_shader_ctx_state state = {sel};
789
790 if (si_shader_select(ctx, &state)) {
791 fprintf(stderr, "radeonsi: can't create a shader\n");
792 tgsi_free_tokens(sel->tokens);
793 FREE(sel);
794 return NULL;
795 }
796 }
797
798 pipe_mutex_init(sel->mutex);
799 return sel;
800 }
801
802 /**
803 * Normally, we only emit 1 viewport and 1 scissor if no shader is using
804 * the VIEWPORT_INDEX output, and emitting the other viewports and scissors
805 * is delayed. When a shader with VIEWPORT_INDEX appears, this should be
806 * called to emit the rest.
807 */
808 static void si_update_viewports_and_scissors(struct si_context *sctx)
809 {
810 struct tgsi_shader_info *info = si_get_vs_info(sctx);
811
812 if (!info || !info->writes_viewport_index)
813 return;
814
815 if (sctx->scissors.dirty_mask)
816 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
817 if (sctx->viewports.dirty_mask)
818 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
819 }
820
821 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
822 {
823 struct si_context *sctx = (struct si_context *)ctx;
824 struct si_shader_selector *sel = state;
825
826 if (sctx->vs_shader.cso == sel)
827 return;
828
829 sctx->vs_shader.cso = sel;
830 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
831 si_mark_atom_dirty(sctx, &sctx->clip_regs);
832 si_update_viewports_and_scissors(sctx);
833 }
834
835 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
836 {
837 struct si_context *sctx = (struct si_context *)ctx;
838 struct si_shader_selector *sel = state;
839 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
840
841 if (sctx->gs_shader.cso == sel)
842 return;
843
844 sctx->gs_shader.cso = sel;
845 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
846 si_mark_atom_dirty(sctx, &sctx->clip_regs);
847 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
848
849 if (enable_changed)
850 si_shader_change_notify(sctx);
851 si_update_viewports_and_scissors(sctx);
852 }
853
854 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
855 {
856 struct si_context *sctx = (struct si_context *)ctx;
857 struct si_shader_selector *sel = state;
858 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
859
860 if (sctx->tcs_shader.cso == sel)
861 return;
862
863 sctx->tcs_shader.cso = sel;
864 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
865
866 if (enable_changed)
867 sctx->last_tcs = NULL; /* invalidate derived tess state */
868 }
869
870 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
871 {
872 struct si_context *sctx = (struct si_context *)ctx;
873 struct si_shader_selector *sel = state;
874 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
875
876 if (sctx->tes_shader.cso == sel)
877 return;
878
879 sctx->tes_shader.cso = sel;
880 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
881 si_mark_atom_dirty(sctx, &sctx->clip_regs);
882 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
883
884 if (enable_changed) {
885 si_shader_change_notify(sctx);
886 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
887 }
888 si_update_viewports_and_scissors(sctx);
889 }
890
891 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
892 {
893 struct si_context *sctx = (struct si_context *)ctx;
894 struct si_shader_selector *sel = state;
895
896 /* skip if supplied shader is one already in use */
897 if (sctx->ps_shader.cso == sel)
898 return;
899
900 sctx->ps_shader.cso = sel;
901 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
902 si_mark_atom_dirty(sctx, &sctx->cb_target_mask);
903 }
904
905 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
906 {
907 struct si_context *sctx = (struct si_context *)ctx;
908 struct si_shader_selector *sel = (struct si_shader_selector *)state;
909 struct si_shader *p = sel->first_variant, *c;
910 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
911 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
912 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
913 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
914 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
915 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
916 };
917
918 if (current_shader[sel->type]->cso == sel) {
919 current_shader[sel->type]->cso = NULL;
920 current_shader[sel->type]->current = NULL;
921 }
922
923 while (p) {
924 c = p->next_variant;
925 switch (sel->type) {
926 case PIPE_SHADER_VERTEX:
927 if (p->key.vs.as_ls)
928 si_pm4_delete_state(sctx, ls, p->pm4);
929 else if (p->key.vs.as_es)
930 si_pm4_delete_state(sctx, es, p->pm4);
931 else
932 si_pm4_delete_state(sctx, vs, p->pm4);
933 break;
934 case PIPE_SHADER_TESS_CTRL:
935 si_pm4_delete_state(sctx, hs, p->pm4);
936 break;
937 case PIPE_SHADER_TESS_EVAL:
938 if (p->key.tes.as_es)
939 si_pm4_delete_state(sctx, es, p->pm4);
940 else
941 si_pm4_delete_state(sctx, vs, p->pm4);
942 break;
943 case PIPE_SHADER_GEOMETRY:
944 si_pm4_delete_state(sctx, gs, p->pm4);
945 si_pm4_delete_state(sctx, vs, p->gs_copy_shader->pm4);
946 break;
947 case PIPE_SHADER_FRAGMENT:
948 si_pm4_delete_state(sctx, ps, p->pm4);
949 break;
950 }
951
952 si_shader_destroy(p);
953 free(p);
954 p = c;
955 }
956
957 pipe_mutex_destroy(sel->mutex);
958 free(sel->tokens);
959 free(sel);
960 }
961
962 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
963 {
964 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
965 struct si_shader *ps = sctx->ps_shader.current;
966 struct si_shader *vs = si_get_vs_state(sctx);
967 struct tgsi_shader_info *psinfo;
968 struct tgsi_shader_info *vsinfo = &vs->selector->info;
969 unsigned i, j, tmp, num_written = 0;
970
971 if (!ps || !ps->nparam)
972 return;
973
974 psinfo = &ps->selector->info;
975
976 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, ps->nparam);
977
978 for (i = 0; i < psinfo->num_inputs; i++) {
979 unsigned name = psinfo->input_semantic_name[i];
980 unsigned index = psinfo->input_semantic_index[i];
981 unsigned interpolate = psinfo->input_interpolate[i];
982 unsigned param_offset = ps->ps_input_param_offset[i];
983
984 if (name == TGSI_SEMANTIC_POSITION ||
985 name == TGSI_SEMANTIC_FACE)
986 /* Read from preloaded VGPRs, not parameters */
987 continue;
988
989 bcolor:
990 tmp = 0;
991
992 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
993 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
994 tmp |= S_028644_FLAT_SHADE(1);
995
996 if (name == TGSI_SEMANTIC_PCOORD ||
997 (name == TGSI_SEMANTIC_TEXCOORD &&
998 sctx->sprite_coord_enable & (1 << index))) {
999 tmp |= S_028644_PT_SPRITE_TEX(1);
1000 }
1001
1002 for (j = 0; j < vsinfo->num_outputs; j++) {
1003 if (name == vsinfo->output_semantic_name[j] &&
1004 index == vsinfo->output_semantic_index[j]) {
1005 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[j]);
1006 break;
1007 }
1008 }
1009
1010 if (name == TGSI_SEMANTIC_PRIMID)
1011 /* PrimID is written after the last output. */
1012 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[vsinfo->num_outputs]);
1013 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(tmp)) {
1014 /* No corresponding output found, load defaults into input.
1015 * Don't set any other bits.
1016 * (FLAT_SHADE=1 completely changes behavior) */
1017 tmp = S_028644_OFFSET(0x20);
1018 }
1019
1020 assert(param_offset == num_written);
1021 radeon_emit(cs, tmp);
1022 num_written++;
1023
1024 if (name == TGSI_SEMANTIC_COLOR &&
1025 ps->key.ps.color_two_side) {
1026 name = TGSI_SEMANTIC_BCOLOR;
1027 param_offset++;
1028 goto bcolor;
1029 }
1030 }
1031 assert(ps->nparam == num_written);
1032 }
1033
1034 static void si_emit_spi_ps_input(struct si_context *sctx, struct r600_atom *atom)
1035 {
1036 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1037 struct si_shader *ps = sctx->ps_shader.current;
1038 unsigned input_ena;
1039
1040 if (!ps)
1041 return;
1042
1043 input_ena = ps->config.spi_ps_input_ena;
1044
1045 /* we need to enable at least one of them, otherwise we hang the GPU */
1046 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1047 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1048 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1049 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1050 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1051 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1052 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1053 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1054
1055 if (sctx->force_persample_interp) {
1056 unsigned num_persp = G_0286CC_PERSP_SAMPLE_ENA(input_ena) +
1057 G_0286CC_PERSP_CENTER_ENA(input_ena) +
1058 G_0286CC_PERSP_CENTROID_ENA(input_ena);
1059 unsigned num_linear = G_0286CC_LINEAR_SAMPLE_ENA(input_ena) +
1060 G_0286CC_LINEAR_CENTER_ENA(input_ena) +
1061 G_0286CC_LINEAR_CENTROID_ENA(input_ena);
1062
1063 /* If only one set of (i,j) coordinates is used, we can disable
1064 * CENTER/CENTROID, enable SAMPLE and it will load SAMPLE coordinates
1065 * where CENTER/CENTROID are expected, effectively forcing per-sample
1066 * interpolation.
1067 */
1068 if (num_persp == 1) {
1069 input_ena &= C_0286CC_PERSP_CENTER_ENA;
1070 input_ena &= C_0286CC_PERSP_CENTROID_ENA;
1071 input_ena |= G_0286CC_PERSP_SAMPLE_ENA(1);
1072 }
1073 if (num_linear == 1) {
1074 input_ena &= C_0286CC_LINEAR_CENTER_ENA;
1075 input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
1076 input_ena |= G_0286CC_LINEAR_SAMPLE_ENA(1);
1077 }
1078
1079 /* If at least 2 sets of coordinates are used, we can't use this
1080 * trick and have to select SAMPLE using a conditional assignment
1081 * in the shader with "force_persample_interp" being a shader constant.
1082 */
1083 }
1084
1085 radeon_set_context_reg_seq(cs, R_0286CC_SPI_PS_INPUT_ENA, 2);
1086 radeon_emit(cs, input_ena);
1087 radeon_emit(cs, input_ena);
1088
1089 if (ps->selector->forces_persample_interp_for_persp ||
1090 ps->selector->forces_persample_interp_for_linear)
1091 radeon_set_sh_reg(cs, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1092 SI_SGPR_PS_STATE_BITS * 4,
1093 sctx->force_persample_interp);
1094 }
1095
1096 /**
1097 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
1098 */
1099 static void si_init_config_add_vgt_flush(struct si_context *sctx)
1100 {
1101 if (sctx->init_config_has_vgt_flush)
1102 return;
1103
1104 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
1105 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
1106 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1107 si_pm4_cmd_end(sctx->init_config, false);
1108 sctx->init_config_has_vgt_flush = true;
1109 }
1110
1111 /* Initialize state related to ESGS / GSVS ring buffers */
1112 static bool si_update_gs_ring_buffers(struct si_context *sctx)
1113 {
1114 struct si_shader_selector *es =
1115 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
1116 struct si_shader_selector *gs = sctx->gs_shader.cso;
1117 struct si_pm4_state *pm4;
1118
1119 /* Chip constants. */
1120 unsigned num_se = sctx->screen->b.info.max_se;
1121 unsigned wave_size = 64;
1122 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1123 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1124 unsigned alignment = 256 * num_se;
1125 /* The maximum size is 63.999 MB per SE. */
1126 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1127
1128 /* Calculate the minimum size. */
1129 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
1130 wave_size, alignment);
1131
1132 /* These are recommended sizes, not minimum sizes. */
1133 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1134 es->esgs_itemsize * gs->gs_input_verts_per_prim;
1135 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1136 gs->max_gsvs_emit_size * (gs->max_gs_stream + 1);
1137
1138 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1139 esgs_ring_size = align(esgs_ring_size, alignment);
1140 gsvs_ring_size = align(gsvs_ring_size, alignment);
1141
1142 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1143 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1144
1145 /* Some rings don't have to be allocated if shaders don't use them.
1146 * (e.g. no varyings between ES and GS or GS and VS)
1147 */
1148 bool update_esgs = esgs_ring_size &&
1149 (!sctx->esgs_ring ||
1150 sctx->esgs_ring->width0 < esgs_ring_size);
1151 bool update_gsvs = gsvs_ring_size &&
1152 (!sctx->gsvs_ring ||
1153 sctx->gsvs_ring->width0 < gsvs_ring_size);
1154
1155 if (!update_esgs && !update_gsvs)
1156 return true;
1157
1158 if (update_esgs) {
1159 pipe_resource_reference(&sctx->esgs_ring, NULL);
1160 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1161 PIPE_USAGE_DEFAULT,
1162 esgs_ring_size);
1163 if (!sctx->esgs_ring)
1164 return false;
1165 }
1166
1167 if (update_gsvs) {
1168 pipe_resource_reference(&sctx->gsvs_ring, NULL);
1169 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1170 PIPE_USAGE_DEFAULT,
1171 gsvs_ring_size);
1172 if (!sctx->gsvs_ring)
1173 return false;
1174 }
1175
1176 /* Create the "init_config_gs_rings" state. */
1177 pm4 = CALLOC_STRUCT(si_pm4_state);
1178 if (!pm4)
1179 return false;
1180
1181 if (sctx->b.chip_class >= CIK) {
1182 if (sctx->esgs_ring)
1183 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
1184 sctx->esgs_ring->width0 / 256);
1185 if (sctx->gsvs_ring)
1186 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
1187 sctx->gsvs_ring->width0 / 256);
1188 } else {
1189 if (sctx->esgs_ring)
1190 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
1191 sctx->esgs_ring->width0 / 256);
1192 if (sctx->gsvs_ring)
1193 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
1194 sctx->gsvs_ring->width0 / 256);
1195 }
1196
1197 /* Set the state. */
1198 if (sctx->init_config_gs_rings)
1199 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
1200 sctx->init_config_gs_rings = pm4;
1201
1202 if (!sctx->init_config_has_vgt_flush) {
1203 si_init_config_add_vgt_flush(sctx);
1204 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1205 }
1206
1207 /* Flush the context to re-emit both init_config states. */
1208 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1209 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1210
1211 /* Set ring bindings. */
1212 if (sctx->esgs_ring) {
1213 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
1214 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1215 true, true, 4, 64, 0);
1216 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
1217 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1218 false, false, 0, 0, 0);
1219 }
1220 if (sctx->gsvs_ring)
1221 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
1222 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
1223 false, false, 0, 0, 0);
1224 return true;
1225 }
1226
1227 static void si_update_gsvs_ring_bindings(struct si_context *sctx)
1228 {
1229 unsigned gsvs_itemsize = sctx->gs_shader.cso->max_gsvs_emit_size;
1230 uint64_t offset;
1231
1232 if (!sctx->gsvs_ring || gsvs_itemsize == sctx->last_gsvs_itemsize)
1233 return;
1234
1235 sctx->last_gsvs_itemsize = gsvs_itemsize;
1236
1237 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
1238 sctx->gsvs_ring, gsvs_itemsize,
1239 64, true, true, 4, 16, 0);
1240
1241 offset = gsvs_itemsize * 64;
1242 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_1,
1243 sctx->gsvs_ring, gsvs_itemsize,
1244 64, true, true, 4, 16, offset);
1245
1246 offset = (gsvs_itemsize * 2) * 64;
1247 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_2,
1248 sctx->gsvs_ring, gsvs_itemsize,
1249 64, true, true, 4, 16, offset);
1250
1251 offset = (gsvs_itemsize * 3) * 64;
1252 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_3,
1253 sctx->gsvs_ring, gsvs_itemsize,
1254 64, true, true, 4, 16, offset);
1255 }
1256
1257 /**
1258 * @returns 1 if \p sel has been updated to use a new scratch buffer
1259 * 0 if not
1260 * < 0 if there was a failure
1261 */
1262 static int si_update_scratch_buffer(struct si_context *sctx,
1263 struct si_shader *shader)
1264 {
1265 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
1266 int r;
1267
1268 if (!shader)
1269 return 0;
1270
1271 /* This shader doesn't need a scratch buffer */
1272 if (shader->config.scratch_bytes_per_wave == 0)
1273 return 0;
1274
1275 /* This shader is already configured to use the current
1276 * scratch buffer. */
1277 if (shader->scratch_bo == sctx->scratch_buffer)
1278 return 0;
1279
1280 assert(sctx->scratch_buffer);
1281
1282 si_shader_apply_scratch_relocs(sctx, shader, scratch_va);
1283
1284 /* Replace the shader bo with a new bo that has the relocs applied. */
1285 r = si_shader_binary_upload(sctx->screen, shader);
1286 if (r)
1287 return r;
1288
1289 /* Update the shader state to use the new shader bo. */
1290 si_shader_init_pm4_state(shader);
1291
1292 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
1293
1294 return 1;
1295 }
1296
1297 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
1298 {
1299 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
1300 }
1301
1302 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
1303 {
1304 return shader ? shader->config.scratch_bytes_per_wave : 0;
1305 }
1306
1307 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
1308 {
1309 unsigned bytes = 0;
1310
1311 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
1312 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
1313 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
1314 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tcs_shader.current));
1315 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
1316 return bytes;
1317 }
1318
1319 static bool si_update_spi_tmpring_size(struct si_context *sctx)
1320 {
1321 unsigned current_scratch_buffer_size =
1322 si_get_current_scratch_buffer_size(sctx);
1323 unsigned scratch_bytes_per_wave =
1324 si_get_max_scratch_bytes_per_wave(sctx);
1325 unsigned scratch_needed_size = scratch_bytes_per_wave *
1326 sctx->scratch_waves;
1327 int r;
1328
1329 if (scratch_needed_size > 0) {
1330 if (scratch_needed_size > current_scratch_buffer_size) {
1331 /* Create a bigger scratch buffer */
1332 pipe_resource_reference(
1333 (struct pipe_resource**)&sctx->scratch_buffer,
1334 NULL);
1335
1336 sctx->scratch_buffer =
1337 si_resource_create_custom(&sctx->screen->b.b,
1338 PIPE_USAGE_DEFAULT, scratch_needed_size);
1339 if (!sctx->scratch_buffer)
1340 return false;
1341 sctx->emit_scratch_reloc = true;
1342 }
1343
1344 /* Update the shaders, so they are using the latest scratch. The
1345 * scratch buffer may have been changed since these shaders were
1346 * last used, so we still need to try to update them, even if
1347 * they require scratch buffers smaller than the current size.
1348 */
1349 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
1350 if (r < 0)
1351 return false;
1352 if (r == 1)
1353 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
1354
1355 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
1356 if (r < 0)
1357 return false;
1358 if (r == 1)
1359 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1360
1361 r = si_update_scratch_buffer(sctx, sctx->tcs_shader.current);
1362 if (r < 0)
1363 return false;
1364 if (r == 1)
1365 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1366
1367 /* VS can be bound as LS, ES, or VS. */
1368 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
1369 if (r < 0)
1370 return false;
1371 if (r == 1) {
1372 if (sctx->tes_shader.current)
1373 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1374 else if (sctx->gs_shader.current)
1375 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1376 else
1377 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1378 }
1379
1380 /* TES can be bound as ES or VS. */
1381 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
1382 if (r < 0)
1383 return false;
1384 if (r == 1) {
1385 if (sctx->gs_shader.current)
1386 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1387 else
1388 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1389 }
1390 }
1391
1392 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
1393 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
1394 "scratch size should already be aligned correctly.");
1395
1396 sctx->spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
1397 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
1398 return true;
1399 }
1400
1401 static void si_init_tess_factor_ring(struct si_context *sctx)
1402 {
1403 assert(!sctx->tf_ring);
1404
1405 sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1406 PIPE_USAGE_DEFAULT,
1407 32768 * sctx->screen->b.info.max_se);
1408 if (!sctx->tf_ring)
1409 return;
1410
1411 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
1412
1413 si_init_config_add_vgt_flush(sctx);
1414
1415 /* Append these registers to the init config state. */
1416 if (sctx->b.chip_class >= CIK) {
1417 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
1418 S_030938_SIZE(sctx->tf_ring->width0 / 4));
1419 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
1420 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1421 } else {
1422 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
1423 S_008988_SIZE(sctx->tf_ring->width0 / 4));
1424 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
1425 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1426 }
1427
1428 /* Flush the context to re-emit the init_config state.
1429 * This is done only once in a lifetime of a context.
1430 */
1431 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1432 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1433 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1434
1435 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_TESS_CTRL,
1436 SI_RING_TESS_FACTOR, sctx->tf_ring, 0,
1437 sctx->tf_ring->width0, false, false, 0, 0, 0);
1438 }
1439
1440 /**
1441 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
1442 * VS passes its outputs to TES directly, so the fixed-function shader only
1443 * has to write TESSOUTER and TESSINNER.
1444 */
1445 static void si_generate_fixed_func_tcs(struct si_context *sctx)
1446 {
1447 struct ureg_src const0, const1;
1448 struct ureg_dst tessouter, tessinner;
1449 struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
1450
1451 if (!ureg)
1452 return; /* if we get here, we're screwed */
1453
1454 assert(!sctx->fixed_func_tcs_shader.cso);
1455
1456 ureg_DECL_constant2D(ureg, 0, 1, SI_DRIVER_STATE_CONST_BUF);
1457 const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 0),
1458 SI_DRIVER_STATE_CONST_BUF);
1459 const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 1),
1460 SI_DRIVER_STATE_CONST_BUF);
1461
1462 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1463 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1464
1465 ureg_MOV(ureg, tessouter, const0);
1466 ureg_MOV(ureg, tessinner, const1);
1467 ureg_END(ureg);
1468
1469 sctx->fixed_func_tcs_shader.cso =
1470 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
1471 }
1472
1473 static void si_update_vgt_shader_config(struct si_context *sctx)
1474 {
1475 /* Calculate the index of the config.
1476 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
1477 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
1478 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
1479
1480 if (!*pm4) {
1481 uint32_t stages = 0;
1482
1483 *pm4 = CALLOC_STRUCT(si_pm4_state);
1484
1485 if (sctx->tes_shader.cso) {
1486 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
1487 S_028B54_HS_EN(1);
1488
1489 if (sctx->gs_shader.cso)
1490 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
1491 S_028B54_GS_EN(1) |
1492 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1493 else
1494 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
1495 } else if (sctx->gs_shader.cso) {
1496 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1497 S_028B54_GS_EN(1) |
1498 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1499 }
1500
1501 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
1502 }
1503 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
1504 }
1505
1506 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
1507 {
1508 struct pipe_stream_output_info *so = &shader->so;
1509 uint32_t enabled_stream_buffers_mask = 0;
1510 int i;
1511
1512 for (i = 0; i < so->num_outputs; i++)
1513 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
1514 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
1515 sctx->b.streamout.stride_in_dw = shader->so.stride;
1516 }
1517
1518 bool si_update_shaders(struct si_context *sctx)
1519 {
1520 struct pipe_context *ctx = (struct pipe_context*)sctx;
1521 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1522 int r;
1523
1524 /* Update stages before GS. */
1525 if (sctx->tes_shader.cso) {
1526 if (!sctx->tf_ring) {
1527 si_init_tess_factor_ring(sctx);
1528 if (!sctx->tf_ring)
1529 return false;
1530 }
1531
1532 /* VS as LS */
1533 r = si_shader_select(ctx, &sctx->vs_shader);
1534 if (r)
1535 return false;
1536 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1537
1538 if (sctx->tcs_shader.cso) {
1539 r = si_shader_select(ctx, &sctx->tcs_shader);
1540 if (r)
1541 return false;
1542 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1543 } else {
1544 if (!sctx->fixed_func_tcs_shader.cso) {
1545 si_generate_fixed_func_tcs(sctx);
1546 if (!sctx->fixed_func_tcs_shader.cso)
1547 return false;
1548 }
1549
1550 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader);
1551 if (r)
1552 return false;
1553 si_pm4_bind_state(sctx, hs,
1554 sctx->fixed_func_tcs_shader.current->pm4);
1555 }
1556
1557 r = si_shader_select(ctx, &sctx->tes_shader);
1558 if (r)
1559 return false;
1560
1561 if (sctx->gs_shader.cso) {
1562 /* TES as ES */
1563 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1564 } else {
1565 /* TES as VS */
1566 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1567 si_update_so(sctx, sctx->tes_shader.cso);
1568 }
1569 } else if (sctx->gs_shader.cso) {
1570 /* VS as ES */
1571 r = si_shader_select(ctx, &sctx->vs_shader);
1572 if (r)
1573 return false;
1574 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1575 } else {
1576 /* VS as VS */
1577 r = si_shader_select(ctx, &sctx->vs_shader);
1578 if (r)
1579 return false;
1580 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1581 si_update_so(sctx, sctx->vs_shader.cso);
1582 }
1583
1584 /* Update GS. */
1585 if (sctx->gs_shader.cso) {
1586 r = si_shader_select(ctx, &sctx->gs_shader);
1587 if (r)
1588 return false;
1589 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1590 si_pm4_bind_state(sctx, vs, sctx->gs_shader.current->gs_copy_shader->pm4);
1591 si_update_so(sctx, sctx->gs_shader.cso);
1592
1593 if (!si_update_gs_ring_buffers(sctx))
1594 return false;
1595
1596 si_update_gsvs_ring_bindings(sctx);
1597 } else {
1598 si_pm4_bind_state(sctx, gs, NULL);
1599 si_pm4_bind_state(sctx, es, NULL);
1600 }
1601
1602 si_update_vgt_shader_config(sctx);
1603
1604 if (sctx->ps_shader.cso) {
1605 unsigned db_shader_control =
1606 sctx->ps_shader.cso->db_shader_control |
1607 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
1608
1609 r = si_shader_select(ctx, &sctx->ps_shader);
1610 if (r)
1611 return false;
1612 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
1613
1614 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
1615 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
1616 sctx->flatshade != rs->flatshade) {
1617 sctx->sprite_coord_enable = rs->sprite_coord_enable;
1618 sctx->flatshade = rs->flatshade;
1619 si_mark_atom_dirty(sctx, &sctx->spi_map);
1620 }
1621
1622 if (si_pm4_state_changed(sctx, ps) ||
1623 sctx->force_persample_interp != rs->force_persample_interp) {
1624 sctx->force_persample_interp = rs->force_persample_interp;
1625 si_mark_atom_dirty(sctx, &sctx->spi_ps_input);
1626 }
1627
1628 if (sctx->ps_db_shader_control != db_shader_control) {
1629 sctx->ps_db_shader_control = db_shader_control;
1630 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1631 }
1632
1633 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.ps.poly_line_smoothing) {
1634 sctx->smoothing_enabled = sctx->ps_shader.current->key.ps.poly_line_smoothing;
1635 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1636
1637 if (sctx->b.chip_class == SI)
1638 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1639 }
1640 }
1641
1642 if (si_pm4_state_changed(sctx, ls) ||
1643 si_pm4_state_changed(sctx, hs) ||
1644 si_pm4_state_changed(sctx, es) ||
1645 si_pm4_state_changed(sctx, gs) ||
1646 si_pm4_state_changed(sctx, vs) ||
1647 si_pm4_state_changed(sctx, ps)) {
1648 if (!si_update_spi_tmpring_size(sctx))
1649 return false;
1650 }
1651 return true;
1652 }
1653
1654 void si_init_shader_functions(struct si_context *sctx)
1655 {
1656 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
1657 si_init_atom(sctx, &sctx->spi_ps_input, &sctx->atoms.s.spi_ps_input, si_emit_spi_ps_input);
1658
1659 sctx->b.b.create_vs_state = si_create_shader_selector;
1660 sctx->b.b.create_tcs_state = si_create_shader_selector;
1661 sctx->b.b.create_tes_state = si_create_shader_selector;
1662 sctx->b.b.create_gs_state = si_create_shader_selector;
1663 sctx->b.b.create_fs_state = si_create_shader_selector;
1664
1665 sctx->b.b.bind_vs_state = si_bind_vs_shader;
1666 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
1667 sctx->b.b.bind_tes_state = si_bind_tes_shader;
1668 sctx->b.b.bind_gs_state = si_bind_gs_shader;
1669 sctx->b.b.bind_fs_state = si_bind_ps_shader;
1670
1671 sctx->b.b.delete_vs_state = si_delete_shader_selector;
1672 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
1673 sctx->b.b.delete_tes_state = si_delete_shader_selector;
1674 sctx->b.b.delete_gs_state = si_delete_shader_selector;
1675 sctx->b.b.delete_fs_state = si_delete_shader_selector;
1676 }