projects / mesa.git / blob
? search:


6701e9a0cf7cef790e0f25fc50d61ea8fe3216d9
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
45 * size as integer.
46 */
47 void *si_get_ir_binary(struct si_shader_selector *sel)
48 {
49 struct blob blob;
50 unsigned ir_size;
51 void *ir_binary;
52
53 if (sel->tokens) {
54 ir_binary = sel->tokens;
55 ir_size = tgsi_num_tokens(sel->tokens) *
56 sizeof(struct tgsi_token);
57 } else {
58 assert(sel->nir);
59
60 blob_init(&blob);
61 nir_serialize(&blob, sel->nir);
62 ir_binary = blob.data;
63 ir_size = blob.size;
64 }
65
66 unsigned size = 4 + ir_size + sizeof(sel->so);
67 char *result = (char*)MALLOC(size);
68 if (!result)
69 return NULL;
70
71 *((uint32_t*)result) = size;
72 memcpy(result + 4, ir_binary, ir_size);
73 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
74
75 if (sel->nir)
76 blob_finish(&blob);
77
78 return result;
79 }
80
81 /** Copy "data" to "ptr" and return the next dword following copied data. */
82 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
83 {
84 /* data may be NULL if size == 0 */
85 if (size)
86 memcpy(ptr, data, size);
87 ptr += DIV_ROUND_UP(size, 4);
88 return ptr;
89 }
90
91 /** Read data from "ptr". Return the next dword following the data. */
92 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
93 {
94 memcpy(data, ptr, size);
95 ptr += DIV_ROUND_UP(size, 4);
96 return ptr;
97 }
98
99 /**
100 * Write the size as uint followed by the data. Return the next dword
101 * following the copied data.
102 */
103 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
104 {
105 *ptr++ = size;
106 return write_data(ptr, data, size);
107 }
108
109 /**
110 * Read the size as uint followed by the data. Return both via parameters.
111 * Return the next dword following the data.
112 */
113 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
114 {
115 *size = *ptr++;
116 assert(*data == NULL);
117 if (!*size)
118 return ptr;
119 *data = malloc(*size);
120 return read_data(ptr, *data, *size);
121 }
122
123 /**
124 * Return the shader binary in a buffer. The first 4 bytes contain its size
125 * as integer.
126 */
127 static void *si_get_shader_binary(struct si_shader *shader)
128 {
129 /* There is always a size of data followed by the data itself. */
130 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
131 strlen(shader->binary.llvm_ir_string) + 1 : 0;
132
133 /* Refuse to allocate overly large buffers and guard against integer
134 * overflow. */
135 if (shader->binary.elf_size > UINT_MAX / 4 ||
136 llvm_ir_size > UINT_MAX / 4)
137 return NULL;
138
139 unsigned size =
140 4 + /* total size */
141 4 + /* CRC32 of the data below */
142 align(sizeof(shader->config), 4) +
143 align(sizeof(shader->info), 4) +
144 4 + align(shader->binary.elf_size, 4) +
145 4 + align(llvm_ir_size, 4);
146 void *buffer = CALLOC(1, size);
147 uint32_t *ptr = (uint32_t*)buffer;
148
149 if (!buffer)
150 return NULL;
151
152 *ptr++ = size;
153 ptr++; /* CRC32 is calculated at the end. */
154
155 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
156 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
157 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
158 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
159 assert((char *)ptr - (char *)buffer == size);
160
161 /* Compute CRC32. */
162 ptr = (uint32_t*)buffer;
163 ptr++;
164 *ptr = util_hash_crc32(ptr + 1, size - 8);
165
166 return buffer;
167 }
168
169 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
170 {
171 uint32_t *ptr = (uint32_t*)binary;
172 uint32_t size = *ptr++;
173 uint32_t crc32 = *ptr++;
174 unsigned chunk_size;
175 unsigned elf_size;
176
177 if (util_hash_crc32(ptr, size - 8) != crc32) {
178 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
179 return false;
180 }
181
182 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
183 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
184 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
185 &elf_size);
186 shader->binary.elf_size = elf_size;
187 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
188
189 return true;
190 }
191
192 /**
193 * Insert a shader into the cache. It's assumed the shader is not in the cache.
194 * Use si_shader_cache_load_shader before calling this.
195 *
196 * Returns false on failure, in which case the ir_binary should be freed.
197 */
198 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
199 struct si_shader *shader,
200 bool insert_into_disk_cache)
201 {
202 void *hw_binary;
203 struct hash_entry *entry;
204 uint8_t key[CACHE_KEY_SIZE];
205
206 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
207 if (entry)
208 return false; /* already added */
209
210 hw_binary = si_get_shader_binary(shader);
211 if (!hw_binary)
212 return false;
213
214 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
215 hw_binary) == NULL) {
216 FREE(hw_binary);
217 return false;
218 }
219
220 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
221 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
222 *((uint32_t *)ir_binary), key);
223 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
224 *((uint32_t *) hw_binary), NULL);
225 }
226
227 return true;
228 }
229
230 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
231 struct si_shader *shader)
232 {
233 struct hash_entry *entry =
234 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
235 if (!entry) {
236 if (sscreen->disk_shader_cache) {
237 unsigned char sha1[CACHE_KEY_SIZE];
238 size_t tg_size = *((uint32_t *) ir_binary);
239
240 disk_cache_compute_key(sscreen->disk_shader_cache,
241 ir_binary, tg_size, sha1);
242
243 size_t binary_size;
244 uint8_t *buffer =
245 disk_cache_get(sscreen->disk_shader_cache,
246 sha1, &binary_size);
247 if (!buffer)
248 return false;
249
250 if (binary_size < sizeof(uint32_t) ||
251 *((uint32_t*)buffer) != binary_size) {
252 /* Something has gone wrong discard the item
253 * from the cache and rebuild/link from
254 * source.
255 */
256 assert(!"Invalid radeonsi shader disk cache "
257 "item!");
258
259 disk_cache_remove(sscreen->disk_shader_cache,
260 sha1);
261 free(buffer);
262
263 return false;
264 }
265
266 if (!si_load_shader_binary(shader, buffer)) {
267 free(buffer);
268 return false;
269 }
270 free(buffer);
271
272 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
273 shader, false))
274 FREE(ir_binary);
275 } else {
276 return false;
277 }
278 } else {
279 if (si_load_shader_binary(shader, entry->data))
280 FREE(ir_binary);
281 else
282 return false;
283 }
284 p_atomic_inc(&sscreen->num_shader_cache_hits);
285 return true;
286 }
287
288 static uint32_t si_shader_cache_key_hash(const void *key)
289 {
290 /* The first dword is the key size. */
291 return util_hash_crc32(key, *(uint32_t*)key);
292 }
293
294 static bool si_shader_cache_key_equals(const void *a, const void *b)
295 {
296 uint32_t *keya = (uint32_t*)a;
297 uint32_t *keyb = (uint32_t*)b;
298
299 /* The first dword is the key size. */
300 if (*keya != *keyb)
301 return false;
302
303 return memcmp(keya, keyb, *keya) == 0;
304 }
305
306 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
307 {
308 FREE((void*)entry->key);
309 FREE(entry->data);
310 }
311
312 bool si_init_shader_cache(struct si_screen *sscreen)
313 {
314 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
315 sscreen->shader_cache =
316 _mesa_hash_table_create(NULL,
317 si_shader_cache_key_hash,
318 si_shader_cache_key_equals);
319
320 return sscreen->shader_cache != NULL;
321 }
322
323 void si_destroy_shader_cache(struct si_screen *sscreen)
324 {
325 if (sscreen->shader_cache)
326 _mesa_hash_table_destroy(sscreen->shader_cache,
327 si_destroy_shader_cache_entry);
328 mtx_destroy(&sscreen->shader_cache_mutex);
329 }
330
331 /* SHADER STATES */
332
333 static void si_set_tesseval_regs(struct si_screen *sscreen,
334 const struct si_shader_selector *tes,
335 struct si_pm4_state *pm4)
336 {
337 const struct tgsi_shader_info *info = &tes->info;
338 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
339 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
340 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
341 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
342 unsigned type, partitioning, topology, distribution_mode;
343
344 switch (tes_prim_mode) {
345 case PIPE_PRIM_LINES:
346 type = V_028B6C_TESS_ISOLINE;
347 break;
348 case PIPE_PRIM_TRIANGLES:
349 type = V_028B6C_TESS_TRIANGLE;
350 break;
351 case PIPE_PRIM_QUADS:
352 type = V_028B6C_TESS_QUAD;
353 break;
354 default:
355 assert(0);
356 return;
357 }
358
359 switch (tes_spacing) {
360 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
361 partitioning = V_028B6C_PART_FRAC_ODD;
362 break;
363 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
364 partitioning = V_028B6C_PART_FRAC_EVEN;
365 break;
366 case PIPE_TESS_SPACING_EQUAL:
367 partitioning = V_028B6C_PART_INTEGER;
368 break;
369 default:
370 assert(0);
371 return;
372 }
373
374 if (tes_point_mode)
375 topology = V_028B6C_OUTPUT_POINT;
376 else if (tes_prim_mode == PIPE_PRIM_LINES)
377 topology = V_028B6C_OUTPUT_LINE;
378 else if (tes_vertex_order_cw)
379 /* for some reason, this must be the other way around */
380 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
381 else
382 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
383
384 if (sscreen->has_distributed_tess) {
385 if (sscreen->info.family == CHIP_FIJI ||
386 sscreen->info.family >= CHIP_POLARIS10)
387 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
388 else
389 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
390 } else
391 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
392
393 assert(pm4->shader);
394 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
395 S_028B6C_PARTITIONING(partitioning) |
396 S_028B6C_TOPOLOGY(topology) |
397 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
398 }
399
400 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
401 * whether the "fractional odd" tessellation spacing is used.
402 *
403 * Possible VGT configurations and which state should set the register:
404 *
405 * Reg set in | VGT shader configuration | Value
406 * ------------------------------------------------------
407 * VS as VS | VS | 30
408 * VS as ES | ES -> GS -> VS | 30
409 * TES as VS | LS -> HS -> VS | 14 or 30
410 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
411 *
412 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
413 */
414 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
415 struct si_shader_selector *sel,
416 struct si_shader *shader,
417 struct si_pm4_state *pm4)
418 {
419 unsigned type = sel->type;
420
421 if (sscreen->info.family < CHIP_POLARIS10 ||
422 sscreen->info.chip_class >= GFX10)
423 return;
424
425 /* VS as VS, or VS as ES: */
426 if ((type == PIPE_SHADER_VERTEX &&
427 (!shader ||
428 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
429 /* TES as VS, or TES as ES: */
430 type == PIPE_SHADER_TESS_EVAL) {
431 unsigned vtx_reuse_depth = 30;
432
433 if (type == PIPE_SHADER_TESS_EVAL &&
434 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
435 PIPE_TESS_SPACING_FRACTIONAL_ODD)
436 vtx_reuse_depth = 14;
437
438 assert(pm4->shader);
439 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
440 }
441 }
442
443 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
444 {
445 if (shader->pm4)
446 si_pm4_clear_state(shader->pm4);
447 else
448 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
449
450 if (shader->pm4) {
451 shader->pm4->shader = shader;
452 return shader->pm4;
453 } else {
454 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
455 return NULL;
456 }
457 }
458
459 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
460 {
461 /* Add the pointer to VBO descriptors. */
462 return num_always_on_user_sgprs + 1;
463 }
464
465 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
466 {
467 struct si_pm4_state *pm4;
468 unsigned vgpr_comp_cnt;
469 uint64_t va;
470
471 assert(sscreen->info.chip_class <= GFX8);
472
473 pm4 = si_get_shader_pm4_state(shader);
474 if (!pm4)
475 return;
476
477 va = shader->bo->gpu_address;
478 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
479
480 /* We need at least 2 components for LS.
481 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
482 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
483 */
484 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
485
486 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
487 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
488
489 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
490 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
491 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
492 S_00B528_DX10_CLAMP(1) |
493 S_00B528_FLOAT_MODE(shader->config.float_mode);
494 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
495 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
496 }
497
498 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
499 {
500 struct si_pm4_state *pm4;
501 uint64_t va;
502 unsigned ls_vgpr_comp_cnt = 0;
503
504 pm4 = si_get_shader_pm4_state(shader);
505 if (!pm4)
506 return;
507
508 va = shader->bo->gpu_address;
509 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
510
511 if (sscreen->info.chip_class >= GFX9) {
512 if (sscreen->info.chip_class >= GFX10) {
513 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
514 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
515 } else {
516 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
517 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
518 }
519
520 /* We need at least 2 components for LS.
521 * GFX9 VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
522 * GFX10 VGPR0-3: (VertexID, RelAutoindex, UserVGPR1, InstanceID).
523 * On gfx9, StepRate0 is set to 1 so that VGPR3 doesn't have to
524 * be loaded.
525 */
526 ls_vgpr_comp_cnt = 1;
527 if (shader->info.uses_instanceid) {
528 if (sscreen->info.chip_class >= GFX10)
529 ls_vgpr_comp_cnt = 3;
530 else
531 ls_vgpr_comp_cnt = 2;
532 }
533
534 unsigned num_user_sgprs =
535 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
536
537 shader->config.rsrc2 =
538 S_00B42C_USER_SGPR(num_user_sgprs) |
539 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
540
541 if (sscreen->info.chip_class >= GFX10)
542 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
543 else
544 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
545 } else {
546 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
547 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
548
549 shader->config.rsrc2 =
550 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
551 S_00B42C_OC_LDS_EN(1) |
552 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
553 }
554
555 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
556 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
557 (sscreen->info.chip_class <= GFX9 ?
558 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
559 S_00B428_DX10_CLAMP(1) |
560 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
561 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
562 S_00B428_FLOAT_MODE(shader->config.float_mode) |
563 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
564
565 if (sscreen->info.chip_class <= GFX8) {
566 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
567 shader->config.rsrc2);
568 }
569 }
570
571 static void si_emit_shader_es(struct si_context *sctx)
572 {
573 struct si_shader *shader = sctx->queued.named.es->shader;
574 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
575
576 if (!shader)
577 return;
578
579 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
580 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
581 shader->selector->esgs_itemsize / 4);
582
583 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
584 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
585 SI_TRACKED_VGT_TF_PARAM,
586 shader->vgt_tf_param);
587
588 if (shader->vgt_vertex_reuse_block_cntl)
589 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
590 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
591 shader->vgt_vertex_reuse_block_cntl);
592
593 if (initial_cdw != sctx->gfx_cs->current.cdw)
594 sctx->context_roll = true;
595 }
596
597 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
598 {
599 struct si_pm4_state *pm4;
600 unsigned num_user_sgprs;
601 unsigned vgpr_comp_cnt;
602 uint64_t va;
603 unsigned oc_lds_en;
604
605 assert(sscreen->info.chip_class <= GFX8);
606
607 pm4 = si_get_shader_pm4_state(shader);
608 if (!pm4)
609 return;
610
611 pm4->atom.emit = si_emit_shader_es;
612 va = shader->bo->gpu_address;
613 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
614
615 if (shader->selector->type == PIPE_SHADER_VERTEX) {
616 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
617 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
618 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
619 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
620 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
621 num_user_sgprs = SI_TES_NUM_USER_SGPR;
622 } else
623 unreachable("invalid shader selector type");
624
625 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
626
627 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
628 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
629 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
630 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
631 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
632 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
633 S_00B328_DX10_CLAMP(1) |
634 S_00B328_FLOAT_MODE(shader->config.float_mode));
635 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
636 S_00B32C_USER_SGPR(num_user_sgprs) |
637 S_00B32C_OC_LDS_EN(oc_lds_en) |
638 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
639
640 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
641 si_set_tesseval_regs(sscreen, shader->selector, pm4);
642
643 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
644 }
645
646 void gfx9_get_gs_info(struct si_shader_selector *es,
647 struct si_shader_selector *gs,
648 struct gfx9_gs_info *out)
649 {
650 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
651 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
652 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
653 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
654
655 /* All these are in dwords: */
656 /* We can't allow using the whole LDS, because GS waves compete with
657 * other shader stages for LDS space. */
658 const unsigned max_lds_size = 8 * 1024;
659 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
660 unsigned esgs_lds_size;
661
662 /* All these are per subgroup: */
663 const unsigned max_out_prims = 32 * 1024;
664 const unsigned max_es_verts = 255;
665 const unsigned ideal_gs_prims = 64;
666 unsigned max_gs_prims, gs_prims;
667 unsigned min_es_verts, es_verts, worst_case_es_verts;
668
669 if (uses_adjacency || gs_num_invocations > 1)
670 max_gs_prims = 127 / gs_num_invocations;
671 else
672 max_gs_prims = 255;
673
674 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
675 * Make sure we don't go over the maximum value.
676 */
677 if (gs->gs_max_out_vertices > 0) {
678 max_gs_prims = MIN2(max_gs_prims,
679 max_out_prims /
680 (gs->gs_max_out_vertices * gs_num_invocations));
681 }
682 assert(max_gs_prims > 0);
683
684 /* If the primitive has adjacency, halve the number of vertices
685 * that will be reused in multiple primitives.
686 */
687 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
688
689 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
690 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
691
692 /* Compute ESGS LDS size based on the worst case number of ES vertices
693 * needed to create the target number of GS prims per subgroup.
694 */
695 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
696
697 /* If total LDS usage is too big, refactor partitions based on ratio
698 * of ESGS item sizes.
699 */
700 if (esgs_lds_size > max_lds_size) {
701 /* Our target GS Prims Per Subgroup was too large. Calculate
702 * the maximum number of GS Prims Per Subgroup that will fit
703 * into LDS, capped by the maximum that the hardware can support.
704 */
705 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
706 max_gs_prims);
707 assert(gs_prims > 0);
708 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
709 max_es_verts);
710
711 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
712 assert(esgs_lds_size <= max_lds_size);
713 }
714
715 /* Now calculate remaining ESGS information. */
716 if (esgs_lds_size)
717 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
718 else
719 es_verts = max_es_verts;
720
721 /* Vertices for adjacency primitives are not always reused, so restore
722 * it for ES_VERTS_PER_SUBGRP.
723 */
724 min_es_verts = gs->gs_input_verts_per_prim;
725
726 /* For normal primitives, the VGT only checks if they are past the ES
727 * verts per subgroup after allocating a full GS primitive and if they
728 * are, kick off a new subgroup. But if those additional ES verts are
729 * unique (e.g. not reused) we need to make sure there is enough LDS
730 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
731 */
732 es_verts -= min_es_verts - 1;
733
734 out->es_verts_per_subgroup = es_verts;
735 out->gs_prims_per_subgroup = gs_prims;
736 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
737 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
738 gs->gs_max_out_vertices;
739 out->esgs_ring_size = 4 * esgs_lds_size;
740
741 assert(out->max_prims_per_subgroup <= max_out_prims);
742 }
743
744 static void si_emit_shader_gs(struct si_context *sctx)
745 {
746 struct si_shader *shader = sctx->queued.named.gs->shader;
747 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
748
749 if (!shader)
750 return;
751
752 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
753 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
754 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
755 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
756 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
757 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
758 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
759
760 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
761 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
762 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
763 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
764
765 /* R_028B38_VGT_GS_MAX_VERT_OUT */
766 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
767 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
768 shader->ctx_reg.gs.vgt_gs_max_vert_out);
769
770 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
771 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
772 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
773 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
774 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
775 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
776 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
777 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
778
779 /* R_028B90_VGT_GS_INSTANCE_CNT */
780 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
781 SI_TRACKED_VGT_GS_INSTANCE_CNT,
782 shader->ctx_reg.gs.vgt_gs_instance_cnt);
783
784 if (sctx->chip_class >= GFX9) {
785 /* R_028A44_VGT_GS_ONCHIP_CNTL */
786 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
787 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
788 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
789 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
790 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
791 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
792 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
793 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
794 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
795 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
796 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
797
798 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
799 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
800 SI_TRACKED_VGT_TF_PARAM,
801 shader->vgt_tf_param);
802 if (shader->vgt_vertex_reuse_block_cntl)
803 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
804 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
805 shader->vgt_vertex_reuse_block_cntl);
806 }
807
808 if (initial_cdw != sctx->gfx_cs->current.cdw)
809 sctx->context_roll = true;
810 }
811
812 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
813 {
814 struct si_shader_selector *sel = shader->selector;
815 const ubyte *num_components = sel->info.num_stream_output_components;
816 unsigned gs_num_invocations = sel->gs_num_invocations;
817 struct si_pm4_state *pm4;
818 uint64_t va;
819 unsigned max_stream = sel->max_gs_stream;
820 unsigned offset;
821
822 pm4 = si_get_shader_pm4_state(shader);
823 if (!pm4)
824 return;
825
826 pm4->atom.emit = si_emit_shader_gs;
827
828 offset = num_components[0] * sel->gs_max_out_vertices;
829 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
830
831 if (max_stream >= 1)
832 offset += num_components[1] * sel->gs_max_out_vertices;
833 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
834
835 if (max_stream >= 2)
836 offset += num_components[2] * sel->gs_max_out_vertices;
837 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
838
839 if (max_stream >= 3)
840 offset += num_components[3] * sel->gs_max_out_vertices;
841 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
842
843 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
844 assert(offset < (1 << 15));
845
846 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
847
848 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
849 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
850 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
851 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
852
853 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
854 S_028B90_ENABLE(gs_num_invocations > 0);
855
856 va = shader->bo->gpu_address;
857 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
858
859 if (sscreen->info.chip_class >= GFX9) {
860 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
861 unsigned es_type = shader->key.part.gs.es->type;
862 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
863
864 if (es_type == PIPE_SHADER_VERTEX)
865 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
866 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
867 else if (es_type == PIPE_SHADER_TESS_EVAL)
868 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
869 else
870 unreachable("invalid shader selector type");
871
872 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
873 * VGPR[0:4] are always loaded.
874 */
875 if (sel->info.uses_invocationid)
876 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
877 else if (sel->info.uses_primid)
878 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
879 else if (input_prim >= PIPE_PRIM_TRIANGLES)
880 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
881 else
882 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
883
884 unsigned num_user_sgprs;
885 if (es_type == PIPE_SHADER_VERTEX)
886 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
887 else
888 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
889
890 if (sscreen->info.chip_class >= GFX10) {
891 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
892 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
893 } else {
894 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
895 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
896 }
897
898 uint32_t rsrc1 =
899 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
900 S_00B228_DX10_CLAMP(1) |
901 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
902 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
903 S_00B228_FLOAT_MODE(shader->config.float_mode) |
904 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
905 uint32_t rsrc2 =
906 S_00B22C_USER_SGPR(num_user_sgprs) |
907 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
908 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
909 S_00B22C_LDS_SIZE(shader->config.lds_size) |
910 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
911
912 if (sscreen->info.chip_class >= GFX10) {
913 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
914 } else {
915 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
916 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
917 }
918
919 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
920 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
921
922 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
923 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
924 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
925 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
926 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
927 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
928 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
929 shader->key.part.gs.es->esgs_itemsize / 4;
930
931 if (es_type == PIPE_SHADER_TESS_EVAL)
932 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
933
934 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
935 NULL, pm4);
936 } else {
937 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
938 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
939
940 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
941 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
942 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
943 S_00B228_DX10_CLAMP(1) |
944 S_00B228_FLOAT_MODE(shader->config.float_mode));
945 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
946 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
947 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
948 }
949 }
950
951 /* Common tail code for NGG primitive shaders. */
952 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
953 struct si_shader *shader,
954 unsigned initial_cdw)
955 {
956 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
957 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
958 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
959 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
960 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
961 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
962 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
963 SI_TRACKED_VGT_PRIMITIVEID_EN,
964 shader->ctx_reg.ngg.vgt_primitiveid_en);
965 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
966 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
967 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
968 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
969 SI_TRACKED_VGT_GS_INSTANCE_CNT,
970 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
971 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
972 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
973 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
974 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
975 SI_TRACKED_VGT_REUSE_OFF,
976 shader->ctx_reg.ngg.vgt_reuse_off);
977 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
978 SI_TRACKED_SPI_VS_OUT_CONFIG,
979 shader->ctx_reg.ngg.spi_vs_out_config);
980 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
981 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
982 shader->ctx_reg.ngg.spi_shader_idx_format,
983 shader->ctx_reg.ngg.spi_shader_pos_format);
984 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
985 SI_TRACKED_PA_CL_VTE_CNTL,
986 shader->ctx_reg.ngg.pa_cl_vte_cntl);
987 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
988 SI_TRACKED_PA_CL_NGG_CNTL,
989 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
990
991 if (initial_cdw != sctx->gfx_cs->current.cdw)
992 sctx->context_roll = true;
993
994 if (shader->ge_cntl != sctx->last_multi_vgt_param) {
995 radeon_set_uconfig_reg(sctx->gfx_cs, R_03096C_GE_CNTL, shader->ge_cntl);
996 sctx->last_multi_vgt_param = shader->ge_cntl;
997 }
998 }
999
1000 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
1001 {
1002 struct si_shader *shader = sctx->queued.named.gs->shader;
1003 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1004
1005 if (!shader)
1006 return;
1007
1008 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1009 }
1010
1011 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1012 {
1013 struct si_shader *shader = sctx->queued.named.gs->shader;
1014 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1015
1016 if (!shader)
1017 return;
1018
1019 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1020 SI_TRACKED_VGT_TF_PARAM,
1021 shader->vgt_tf_param);
1022
1023 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1024 }
1025
1026 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1027 {
1028 struct si_shader *shader = sctx->queued.named.gs->shader;
1029 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1030
1031 if (!shader)
1032 return;
1033
1034 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1035 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1036 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1037
1038 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1039 }
1040
1041 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1042 {
1043 struct si_shader *shader = sctx->queued.named.gs->shader;
1044 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1045
1046 if (!shader)
1047 return;
1048
1049 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1050 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1051 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1052 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1053 SI_TRACKED_VGT_TF_PARAM,
1054 shader->vgt_tf_param);
1055
1056 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1057 }
1058
1059 static void si_set_ge_pc_alloc(struct si_screen *sscreen,
1060 struct si_pm4_state *pm4, bool culling)
1061 {
1062 si_pm4_set_reg(pm4, R_030980_GE_PC_ALLOC,
1063 S_030980_OVERSUB_EN(1) |
1064 S_030980_NUM_PC_LINES((culling ? 256 : 128) * sscreen->info.max_se - 1));
1065 }
1066
1067 unsigned si_get_input_prim(const struct si_shader_selector *gs,
1068 unsigned default_worst_case)
1069 {
1070 if (gs->type == PIPE_SHADER_GEOMETRY)
1071 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1072
1073 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1074 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1075 return PIPE_PRIM_POINTS;
1076 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1077 return PIPE_PRIM_LINES;
1078 return PIPE_PRIM_TRIANGLES;
1079 }
1080
1081 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1082 return default_worst_case;
1083 }
1084
1085 /**
1086 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1087 * in NGG mode.
1088 */
1089 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1090 {
1091 const struct si_shader_selector *gs_sel = shader->selector;
1092 const struct tgsi_shader_info *gs_info = &gs_sel->info;
1093 enum pipe_shader_type gs_type = shader->selector->type;
1094 const struct si_shader_selector *es_sel =
1095 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1096 const struct tgsi_shader_info *es_info = &es_sel->info;
1097 enum pipe_shader_type es_type = es_sel->type;
1098 unsigned num_user_sgprs;
1099 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1100 uint64_t va;
1101 unsigned window_space =
1102 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1103 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1104 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1105 /* Anything above TRIANGLES has the same effect as TRIANGLES here. */
1106 unsigned input_prim = si_get_input_prim(gs_sel, PIPE_PRIM_TRIANGLES);
1107 bool break_wave_at_eoi = false;
1108 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1109 if (!pm4)
1110 return;
1111
1112 if (es_type == PIPE_SHADER_TESS_EVAL) {
1113 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1114 : gfx10_emit_shader_ngg_tess_nogs;
1115 } else {
1116 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1117 : gfx10_emit_shader_ngg_notess_nogs;
1118 }
1119
1120 va = shader->bo->gpu_address;
1121 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1122
1123 if (es_type == PIPE_SHADER_VERTEX) {
1124 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
1125 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
1126
1127 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1128 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1129 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1130 } else {
1131 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
1132 }
1133 } else {
1134 assert(es_type == PIPE_SHADER_TESS_EVAL);
1135 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1136 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1137
1138 if (es_enable_prim_id || gs_info->uses_primid)
1139 break_wave_at_eoi = true;
1140 }
1141
1142 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1143 * VGPR[0:4] are always loaded.
1144 *
1145 * Vertex shaders always need to load VGPR3, because they need to
1146 * pass edge flags for decomposed primitives (such as quads) to the PA
1147 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1148 */
1149 if (gs_info->uses_invocationid || gs_type == PIPE_SHADER_VERTEX)
1150 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1151 else if (gs_info->uses_primid)
1152 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1153 else if (input_prim >= PIPE_PRIM_TRIANGLES)
1154 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1155 else
1156 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1157
1158 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1159 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1160 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1161 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
1162 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1163 S_00B228_DX10_CLAMP(1) |
1164 S_00B228_MEM_ORDERED(1) |
1165 S_00B228_WGP_MODE(1) |
1166 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1167 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1168 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1169 S_00B22C_USER_SGPR(num_user_sgprs) |
1170 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1171 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1172 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1173 S_00B22C_LDS_SIZE(shader->config.lds_size));
1174 si_set_ge_pc_alloc(sscreen, pm4, false);
1175
1176 nparams = MAX2(shader->info.nr_param_exports, 1);
1177 shader->ctx_reg.ngg.spi_vs_out_config =
1178 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1179 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1180
1181 shader->ctx_reg.ngg.spi_shader_idx_format =
1182 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1183 shader->ctx_reg.ngg.spi_shader_pos_format =
1184 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1185 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1186 V_02870C_SPI_SHADER_4COMP :
1187 V_02870C_SPI_SHADER_NONE) |
1188 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1189 V_02870C_SPI_SHADER_4COMP :
1190 V_02870C_SPI_SHADER_NONE) |
1191 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1192 V_02870C_SPI_SHADER_4COMP :
1193 V_02870C_SPI_SHADER_NONE);
1194
1195 shader->ctx_reg.ngg.vgt_primitiveid_en =
1196 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1197 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id);
1198
1199 if (gs_type == PIPE_SHADER_GEOMETRY) {
1200 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1201 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1202 } else {
1203 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1204 }
1205
1206 if (es_type == PIPE_SHADER_TESS_EVAL)
1207 si_set_tesseval_regs(sscreen, es_sel, pm4);
1208
1209 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1210 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1211 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1212 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1213 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1214 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1215 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1216 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1217 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1218 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1219 S_028B90_CNT(gs_num_invocations) |
1220 S_028B90_ENABLE(gs_num_invocations > 1) |
1221 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1222 shader->ngg.max_vert_out_per_gs_instance);
1223
1224 /* User edge flags are set by the pos exports. If user edge flags are
1225 * not used, we must use hw-generated edge flags and pass them via
1226 * the prim export to prevent drawing lines on internal edges of
1227 * decomposed primitives (such as quads) with polygon mode = lines.
1228 *
1229 * TODO: We should combine hw-generated edge flags with user edge
1230 * flags in the shader.
1231 */
1232 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1233 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX &&
1234 !gs_info->writes_edgeflag);
1235
1236 shader->ge_cntl =
1237 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1238 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts) |
1239 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1240
1241 if (window_space) {
1242 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1243 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1244 } else {
1245 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1246 S_028818_VTX_W0_FMT(1) |
1247 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1248 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1249 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1250 }
1251
1252 shader->ctx_reg.ngg.vgt_reuse_off =
1253 S_028AB4_REUSE_OFF(sscreen->info.family == CHIP_NAVI10 &&
1254 sscreen->info.chip_external_rev == 0x1 &&
1255 es_type == PIPE_SHADER_TESS_EVAL);
1256 }
1257
1258 static void si_emit_shader_vs(struct si_context *sctx)
1259 {
1260 struct si_shader *shader = sctx->queued.named.vs->shader;
1261 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1262
1263 if (!shader)
1264 return;
1265
1266 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1267 SI_TRACKED_VGT_GS_MODE,
1268 shader->ctx_reg.vs.vgt_gs_mode);
1269 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1270 SI_TRACKED_VGT_PRIMITIVEID_EN,
1271 shader->ctx_reg.vs.vgt_primitiveid_en);
1272
1273 if (sctx->chip_class <= GFX8) {
1274 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1275 SI_TRACKED_VGT_REUSE_OFF,
1276 shader->ctx_reg.vs.vgt_reuse_off);
1277 }
1278
1279 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1280 SI_TRACKED_SPI_VS_OUT_CONFIG,
1281 shader->ctx_reg.vs.spi_vs_out_config);
1282
1283 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1284 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1285 shader->ctx_reg.vs.spi_shader_pos_format);
1286
1287 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1288 SI_TRACKED_PA_CL_VTE_CNTL,
1289 shader->ctx_reg.vs.pa_cl_vte_cntl);
1290
1291 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1292 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1293 SI_TRACKED_VGT_TF_PARAM,
1294 shader->vgt_tf_param);
1295
1296 if (shader->vgt_vertex_reuse_block_cntl)
1297 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1298 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1299 shader->vgt_vertex_reuse_block_cntl);
1300
1301 if (initial_cdw != sctx->gfx_cs->current.cdw)
1302 sctx->context_roll = true;
1303 }
1304
1305 /**
1306 * Compute the state for \p shader, which will run as a vertex shader on the
1307 * hardware.
1308 *
1309 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1310 * is the copy shader.
1311 */
1312 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1313 struct si_shader_selector *gs)
1314 {
1315 const struct tgsi_shader_info *info = &shader->selector->info;
1316 struct si_pm4_state *pm4;
1317 unsigned num_user_sgprs, vgpr_comp_cnt;
1318 uint64_t va;
1319 unsigned nparams, oc_lds_en;
1320 unsigned window_space =
1321 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1322 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1323
1324 pm4 = si_get_shader_pm4_state(shader);
1325 if (!pm4)
1326 return;
1327
1328 pm4->atom.emit = si_emit_shader_vs;
1329
1330 /* We always write VGT_GS_MODE in the VS state, because every switch
1331 * between different shader pipelines involving a different GS or no
1332 * GS at all involves a switch of the VS (different GS use different
1333 * copy shaders). On the other hand, when the API switches from a GS to
1334 * no GS and then back to the same GS used originally, the GS state is
1335 * not sent again.
1336 */
1337 if (!gs) {
1338 unsigned mode = V_028A40_GS_OFF;
1339
1340 /* PrimID needs GS scenario A. */
1341 if (enable_prim_id)
1342 mode = V_028A40_GS_SCENARIO_A;
1343
1344 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1345 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1346 } else {
1347 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1348 sscreen->info.chip_class);
1349 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1350 }
1351
1352 if (sscreen->info.chip_class <= GFX8) {
1353 /* Reuse needs to be set off if we write oViewport. */
1354 shader->ctx_reg.vs.vgt_reuse_off =
1355 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1356 }
1357
1358 va = shader->bo->gpu_address;
1359 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1360
1361 if (gs) {
1362 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1363 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1364 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1365 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1366 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1367 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1368 */
1369 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
1370
1371 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1372 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1373 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1374 } else {
1375 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1376 }
1377 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1378 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1379 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1380 } else
1381 unreachable("invalid shader selector type");
1382
1383 /* VS is required to export at least one param. */
1384 nparams = MAX2(shader->info.nr_param_exports, 1);
1385 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1386
1387 if (sscreen->info.chip_class >= GFX10) {
1388 shader->ctx_reg.vs.spi_vs_out_config |=
1389 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1390 }
1391
1392 shader->ctx_reg.vs.spi_shader_pos_format =
1393 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1394 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1395 V_02870C_SPI_SHADER_4COMP :
1396 V_02870C_SPI_SHADER_NONE) |
1397 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1398 V_02870C_SPI_SHADER_4COMP :
1399 V_02870C_SPI_SHADER_NONE) |
1400 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1401 V_02870C_SPI_SHADER_4COMP :
1402 V_02870C_SPI_SHADER_NONE);
1403
1404 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1405
1406 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1407 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1408 if (sscreen->info.chip_class >= GFX10)
1409 si_set_ge_pc_alloc(sscreen, pm4, false);
1410
1411 uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
1412 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1413 S_00B128_DX10_CLAMP(1) |
1414 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1415 S_00B128_FLOAT_MODE(shader->config.float_mode);
1416 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
1417 S_00B12C_OC_LDS_EN(oc_lds_en) |
1418 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1419
1420 if (sscreen->info.chip_class <= GFX9) {
1421 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1422 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1423 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1424 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1425 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1426 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1427 }
1428
1429 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1430 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1431
1432 if (window_space)
1433 shader->ctx_reg.vs.pa_cl_vte_cntl =
1434 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1435 else
1436 shader->ctx_reg.vs.pa_cl_vte_cntl =
1437 S_028818_VTX_W0_FMT(1) |
1438 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1439 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1440 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1441
1442 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1443 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1444
1445 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1446 }
1447
1448 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1449 {
1450 struct tgsi_shader_info *info = &ps->selector->info;
1451 unsigned num_colors = !!(info->colors_read & 0x0f) +
1452 !!(info->colors_read & 0xf0);
1453 unsigned num_interp = ps->selector->info.num_inputs +
1454 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1455
1456 assert(num_interp <= 32);
1457 return MIN2(num_interp, 32);
1458 }
1459
1460 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1461 {
1462 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1463 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1464
1465 /* If the i-th target format is set, all previous target formats must
1466 * be non-zero to avoid hangs.
1467 */
1468 for (i = 0; i < num_targets; i++)
1469 if (!(value & (0xf << (i * 4))))
1470 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1471
1472 return value;
1473 }
1474
1475 static void si_emit_shader_ps(struct si_context *sctx)
1476 {
1477 struct si_shader *shader = sctx->queued.named.ps->shader;
1478 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1479
1480 if (!shader)
1481 return;
1482
1483 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1484 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1485 SI_TRACKED_SPI_PS_INPUT_ENA,
1486 shader->ctx_reg.ps.spi_ps_input_ena,
1487 shader->ctx_reg.ps.spi_ps_input_addr);
1488
1489 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1490 SI_TRACKED_SPI_BARYC_CNTL,
1491 shader->ctx_reg.ps.spi_baryc_cntl);
1492 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1493 SI_TRACKED_SPI_PS_IN_CONTROL,
1494 shader->ctx_reg.ps.spi_ps_in_control);
1495
1496 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1497 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1498 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1499 shader->ctx_reg.ps.spi_shader_z_format,
1500 shader->ctx_reg.ps.spi_shader_col_format);
1501
1502 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1503 SI_TRACKED_CB_SHADER_MASK,
1504 shader->ctx_reg.ps.cb_shader_mask);
1505
1506 if (initial_cdw != sctx->gfx_cs->current.cdw)
1507 sctx->context_roll = true;
1508 }
1509
1510 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1511 {
1512 struct tgsi_shader_info *info = &shader->selector->info;
1513 struct si_pm4_state *pm4;
1514 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1515 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1516 uint64_t va;
1517 unsigned input_ena = shader->config.spi_ps_input_ena;
1518
1519 /* we need to enable at least one of them, otherwise we hang the GPU */
1520 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1521 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1522 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1523 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1524 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1525 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1526 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1527 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1528 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1529 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1530 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1531 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1532 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1533 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1534
1535 /* Validate interpolation optimization flags (read as implications). */
1536 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1537 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1538 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1539 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1540 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1541 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1542 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1543 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1544 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1545 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1546 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1547 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1548 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1549 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1550 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1551 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1552 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1553 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1554
1555 /* Validate cases when the optimizations are off (read as implications). */
1556 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1557 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1558 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1559 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1560 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1561 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1562
1563 pm4 = si_get_shader_pm4_state(shader);
1564 if (!pm4)
1565 return;
1566
1567 pm4->atom.emit = si_emit_shader_ps;
1568
1569 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1570 * Possible vaules:
1571 * 0 -> Position = pixel center
1572 * 1 -> Position = pixel centroid
1573 * 2 -> Position = at sample position
1574 *
1575 * From GLSL 4.5 specification, section 7.1:
1576 * "The variable gl_FragCoord is available as an input variable from
1577 * within fragment shaders and it holds the window relative coordinates
1578 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1579 * value can be for any location within the pixel, or one of the
1580 * fragment samples. The use of centroid does not further restrict
1581 * this value to be inside the current primitive."
1582 *
1583 * Meaning that centroid has no effect and we can return anything within
1584 * the pixel. Thus, return the value at sample position, because that's
1585 * the most accurate one shaders can get.
1586 */
1587 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1588
1589 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1590 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1591 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1592
1593 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1594 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1595
1596 /* Ensure that some export memory is always allocated, for two reasons:
1597 *
1598 * 1) Correctness: The hardware ignores the EXEC mask if no export
1599 * memory is allocated, so KILL and alpha test do not work correctly
1600 * without this.
1601 * 2) Performance: Every shader needs at least a NULL export, even when
1602 * it writes no color/depth output. The NULL export instruction
1603 * stalls without this setting.
1604 *
1605 * Don't add this to CB_SHADER_MASK.
1606 *
1607 * GFX10 supports pixel shaders without exports by setting both
1608 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1609 * instructions if any are present.
1610 */
1611 if ((sscreen->info.chip_class <= GFX9 ||
1612 info->uses_kill ||
1613 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1614 !spi_shader_col_format &&
1615 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1616 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1617
1618 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1619 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1620
1621 /* Set interpolation controls. */
1622 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1623
1624 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1625 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1626 shader->ctx_reg.ps.spi_shader_z_format =
1627 ac_get_spi_shader_z_format(info->writes_z,
1628 info->writes_stencil,
1629 info->writes_samplemask);
1630 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1631 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1632
1633 va = shader->bo->gpu_address;
1634 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1635 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1636 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1637
1638 uint32_t rsrc1 =
1639 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1640 S_00B028_DX10_CLAMP(1) |
1641 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1642 S_00B028_FLOAT_MODE(shader->config.float_mode);
1643
1644 if (sscreen->info.chip_class < GFX10) {
1645 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1646 }
1647
1648 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1649 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1650 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1651 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1652 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1653 }
1654
1655 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1656 struct si_shader *shader)
1657 {
1658 switch (shader->selector->type) {
1659 case PIPE_SHADER_VERTEX:
1660 if (shader->key.as_ls)
1661 si_shader_ls(sscreen, shader);
1662 else if (shader->key.as_es)
1663 si_shader_es(sscreen, shader);
1664 else if (shader->key.as_ngg)
1665 gfx10_shader_ngg(sscreen, shader);
1666 else
1667 si_shader_vs(sscreen, shader, NULL);
1668 break;
1669 case PIPE_SHADER_TESS_CTRL:
1670 si_shader_hs(sscreen, shader);
1671 break;
1672 case PIPE_SHADER_TESS_EVAL:
1673 if (shader->key.as_es)
1674 si_shader_es(sscreen, shader);
1675 else if (shader->key.as_ngg)
1676 gfx10_shader_ngg(sscreen, shader);
1677 else
1678 si_shader_vs(sscreen, shader, NULL);
1679 break;
1680 case PIPE_SHADER_GEOMETRY:
1681 if (shader->key.as_ngg)
1682 gfx10_shader_ngg(sscreen, shader);
1683 else
1684 si_shader_gs(sscreen, shader);
1685 break;
1686 case PIPE_SHADER_FRAGMENT:
1687 si_shader_ps(sscreen, shader);
1688 break;
1689 default:
1690 assert(0);
1691 }
1692 }
1693
1694 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1695 {
1696 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1697 if (sctx->queued.named.dsa)
1698 return sctx->queued.named.dsa->alpha_func;
1699
1700 return PIPE_FUNC_ALWAYS;
1701 }
1702
1703 void si_shader_selector_key_vs(struct si_context *sctx,
1704 struct si_shader_selector *vs,
1705 struct si_shader_key *key,
1706 struct si_vs_prolog_bits *prolog_key)
1707 {
1708 if (!sctx->vertex_elements ||
1709 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS])
1710 return;
1711
1712 struct si_vertex_elements *elts = sctx->vertex_elements;
1713
1714 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1715 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1716 prolog_key->unpack_instance_id_from_vertex_id =
1717 sctx->prim_discard_cs_instancing;
1718
1719 /* Prefer a monolithic shader to allow scheduling divisions around
1720 * VBO loads. */
1721 if (prolog_key->instance_divisor_is_fetched)
1722 key->opt.prefer_mono = 1;
1723
1724 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1725 unsigned count_mask = (1 << count) - 1;
1726 unsigned fix = elts->fix_fetch_always & count_mask;
1727 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1728
1729 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1730 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1731 while (mask) {
1732 unsigned i = u_bit_scan(&mask);
1733 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1734 unsigned vbidx = elts->vertex_buffer_index[i];
1735 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1736 unsigned align_mask = (1 << log_hw_load_size) - 1;
1737 if (vb->buffer_offset & align_mask ||
1738 vb->stride & align_mask) {
1739 fix |= 1 << i;
1740 opencode |= 1 << i;
1741 }
1742 }
1743 }
1744
1745 while (fix) {
1746 unsigned i = u_bit_scan(&fix);
1747 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1748 }
1749 key->mono.vs_fetch_opencode = opencode;
1750 }
1751
1752 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1753 struct si_shader_selector *vs,
1754 struct si_shader_key *key)
1755 {
1756 struct si_shader_selector *ps = sctx->ps_shader.cso;
1757
1758 key->opt.clip_disable =
1759 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1760 (vs->info.clipdist_writemask ||
1761 vs->info.writes_clipvertex) &&
1762 !vs->info.culldist_writemask;
1763
1764 /* Find out if PS is disabled. */
1765 bool ps_disabled = true;
1766 if (ps) {
1767 const struct si_state_blend *blend = sctx->queued.named.blend;
1768 bool alpha_to_coverage = blend && blend->alpha_to_coverage;
1769 bool ps_modifies_zs = ps->info.uses_kill ||
1770 ps->info.writes_z ||
1771 ps->info.writes_stencil ||
1772 ps->info.writes_samplemask ||
1773 alpha_to_coverage ||
1774 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1775 unsigned ps_colormask = si_get_total_colormask(sctx);
1776
1777 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1778 (!ps_colormask &&
1779 !ps_modifies_zs &&
1780 !ps->info.writes_memory);
1781 }
1782
1783 /* Find out which VS outputs aren't used by the PS. */
1784 uint64_t outputs_written = vs->outputs_written_before_ps;
1785 uint64_t inputs_read = 0;
1786
1787 /* Ignore outputs that are not passed from VS to PS. */
1788 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1789 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1790 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1791
1792 if (!ps_disabled) {
1793 inputs_read = ps->inputs_read;
1794 }
1795
1796 uint64_t linked = outputs_written & inputs_read;
1797
1798 key->opt.kill_outputs = ~linked & outputs_written;
1799 }
1800
1801 /* Compute the key for the hw shader variant */
1802 static inline void si_shader_selector_key(struct pipe_context *ctx,
1803 struct si_shader_selector *sel,
1804 union si_vgt_stages_key stages_key,
1805 struct si_shader_key *key)
1806 {
1807 struct si_context *sctx = (struct si_context *)ctx;
1808
1809 memset(key, 0, sizeof(*key));
1810
1811 switch (sel->type) {
1812 case PIPE_SHADER_VERTEX:
1813 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1814
1815 if (sctx->tes_shader.cso)
1816 key->as_ls = 1;
1817 else if (sctx->gs_shader.cso)
1818 key->as_es = 1;
1819 else {
1820 key->as_ngg = stages_key.u.ngg;
1821 si_shader_selector_key_hw_vs(sctx, sel, key);
1822
1823 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1824 key->mono.u.vs_export_prim_id = 1;
1825 }
1826 break;
1827 case PIPE_SHADER_TESS_CTRL:
1828 if (sctx->chip_class >= GFX9) {
1829 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1830 key, &key->part.tcs.ls_prolog);
1831 key->part.tcs.ls = sctx->vs_shader.cso;
1832
1833 /* When the LS VGPR fix is needed, monolithic shaders
1834 * can:
1835 * - avoid initializing EXEC in both the LS prolog
1836 * and the LS main part when !vs_needs_prolog
1837 * - remove the fixup for unused input VGPRs
1838 */
1839 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1840
1841 /* The LS output / HS input layout can be communicated
1842 * directly instead of via user SGPRs for merged LS-HS.
1843 * The LS VGPR fix prefers this too.
1844 */
1845 key->opt.prefer_mono = 1;
1846 }
1847
1848 key->part.tcs.epilog.prim_mode =
1849 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1850 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1851 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1852 key->part.tcs.epilog.tes_reads_tess_factors =
1853 sctx->tes_shader.cso->info.reads_tess_factors;
1854
1855 if (sel == sctx->fixed_func_tcs_shader.cso)
1856 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1857 break;
1858 case PIPE_SHADER_TESS_EVAL:
1859 if (sctx->gs_shader.cso)
1860 key->as_es = 1;
1861 else {
1862 key->as_ngg = stages_key.u.ngg;
1863 si_shader_selector_key_hw_vs(sctx, sel, key);
1864
1865 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1866 key->mono.u.vs_export_prim_id = 1;
1867 }
1868 break;
1869 case PIPE_SHADER_GEOMETRY:
1870 if (sctx->chip_class >= GFX9) {
1871 if (sctx->tes_shader.cso) {
1872 key->part.gs.es = sctx->tes_shader.cso;
1873 } else {
1874 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1875 key, &key->part.gs.vs_prolog);
1876 key->part.gs.es = sctx->vs_shader.cso;
1877 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1878 }
1879
1880 key->as_ngg = stages_key.u.ngg;
1881
1882 /* Merged ES-GS can have unbalanced wave usage.
1883 *
1884 * ES threads are per-vertex, while GS threads are
1885 * per-primitive. So without any amplification, there
1886 * are fewer GS threads than ES threads, which can result
1887 * in empty (no-op) GS waves. With too much amplification,
1888 * there are more GS threads than ES threads, which
1889 * can result in empty (no-op) ES waves.
1890 *
1891 * Non-monolithic shaders are implemented by setting EXEC
1892 * at the beginning of shader parts, and don't jump to
1893 * the end if EXEC is 0.
1894 *
1895 * Monolithic shaders use conditional blocks, so they can
1896 * jump and skip empty waves of ES or GS. So set this to
1897 * always use optimized variants, which are monolithic.
1898 */
1899 key->opt.prefer_mono = 1;
1900 }
1901 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1902 break;
1903 case PIPE_SHADER_FRAGMENT: {
1904 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1905 struct si_state_blend *blend = sctx->queued.named.blend;
1906
1907 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1908 sel->info.colors_written == 0x1)
1909 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1910
1911 if (blend) {
1912 /* Select the shader color format based on whether
1913 * blending or alpha are needed.
1914 */
1915 key->part.ps.epilog.spi_shader_col_format =
1916 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1917 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1918 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1919 sctx->framebuffer.spi_shader_col_format_blend) |
1920 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1921 sctx->framebuffer.spi_shader_col_format_alpha) |
1922 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1923 sctx->framebuffer.spi_shader_col_format);
1924 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1925
1926 /* The output for dual source blending should have
1927 * the same format as the first output.
1928 */
1929 if (blend->dual_src_blend)
1930 key->part.ps.epilog.spi_shader_col_format |=
1931 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1932 } else
1933 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1934
1935 /* If alpha-to-coverage is enabled, we have to export alpha
1936 * even if there is no color buffer.
1937 */
1938 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1939 blend && blend->alpha_to_coverage)
1940 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1941
1942 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1943 * to the range supported by the type if a channel has less
1944 * than 16 bits and the export format is 16_ABGR.
1945 */
1946 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1947 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1948 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1949 }
1950
1951 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1952 if (!key->part.ps.epilog.last_cbuf) {
1953 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1954 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1955 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1956 }
1957
1958 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1959 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1960
1961 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1962 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1963
1964 if (sctx->queued.named.blend) {
1965 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1966 rs->multisample_enable;
1967 }
1968
1969 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1970 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1971 (is_line && rs->line_smooth)) &&
1972 sctx->framebuffer.nr_samples <= 1;
1973 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1974
1975 if (sctx->ps_iter_samples > 1 &&
1976 sel->info.reads_samplemask) {
1977 key->part.ps.prolog.samplemask_log_ps_iter =
1978 util_logbase2(sctx->ps_iter_samples);
1979 }
1980
1981 if (rs->force_persample_interp &&
1982 rs->multisample_enable &&
1983 sctx->framebuffer.nr_samples > 1 &&
1984 sctx->ps_iter_samples > 1) {
1985 key->part.ps.prolog.force_persp_sample_interp =
1986 sel->info.uses_persp_center ||
1987 sel->info.uses_persp_centroid;
1988
1989 key->part.ps.prolog.force_linear_sample_interp =
1990 sel->info.uses_linear_center ||
1991 sel->info.uses_linear_centroid;
1992 } else if (rs->multisample_enable &&
1993 sctx->framebuffer.nr_samples > 1) {
1994 key->part.ps.prolog.bc_optimize_for_persp =
1995 sel->info.uses_persp_center &&
1996 sel->info.uses_persp_centroid;
1997 key->part.ps.prolog.bc_optimize_for_linear =
1998 sel->info.uses_linear_center &&
1999 sel->info.uses_linear_centroid;
2000 } else {
2001 /* Make sure SPI doesn't compute more than 1 pair
2002 * of (i,j), which is the optimization here. */
2003 key->part.ps.prolog.force_persp_center_interp =
2004 sel->info.uses_persp_center +
2005 sel->info.uses_persp_centroid +
2006 sel->info.uses_persp_sample > 1;
2007
2008 key->part.ps.prolog.force_linear_center_interp =
2009 sel->info.uses_linear_center +
2010 sel->info.uses_linear_centroid +
2011 sel->info.uses_linear_sample > 1;
2012
2013 if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
2014 key->mono.u.ps.interpolate_at_sample_force_center = 1;
2015 }
2016
2017 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
2018
2019 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2020 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
2021 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2022 struct pipe_resource *tex = cb0->texture;
2023
2024 /* 1D textures are allocated and used as 2D on GFX9. */
2025 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2026 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
2027 (tex->target == PIPE_TEXTURE_1D ||
2028 tex->target == PIPE_TEXTURE_1D_ARRAY);
2029 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
2030 tex->target == PIPE_TEXTURE_2D_ARRAY ||
2031 tex->target == PIPE_TEXTURE_CUBE ||
2032 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2033 tex->target == PIPE_TEXTURE_3D;
2034 }
2035 break;
2036 }
2037 default:
2038 assert(0);
2039 }
2040
2041 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2042 memset(&key->opt, 0, sizeof(key->opt));
2043 }
2044
2045 static void si_build_shader_variant(struct si_shader *shader,
2046 int thread_index,
2047 bool low_priority)
2048 {
2049 struct si_shader_selector *sel = shader->selector;
2050 struct si_screen *sscreen = sel->screen;
2051 struct ac_llvm_compiler *compiler;
2052 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2053
2054 if (thread_index >= 0) {
2055 if (low_priority) {
2056 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2057 compiler = &sscreen->compiler_lowp[thread_index];
2058 } else {
2059 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2060 compiler = &sscreen->compiler[thread_index];
2061 }
2062 if (!debug->async)
2063 debug = NULL;
2064 } else {
2065 assert(!low_priority);
2066 compiler = shader->compiler_ctx_state.compiler;
2067 }
2068
2069 if (unlikely(!si_shader_create(sscreen, compiler, shader, debug))) {
2070 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2071 sel->type);
2072 shader->compilation_failed = true;
2073 return;
2074 }
2075
2076 if (shader->compiler_ctx_state.is_debug_context) {
2077 FILE *f = open_memstream(&shader->shader_log,
2078 &shader->shader_log_size);
2079 if (f) {
2080 si_shader_dump(sscreen, shader, NULL, f, false);
2081 fclose(f);
2082 }
2083 }
2084
2085 si_shader_init_pm4_state(sscreen, shader);
2086 }
2087
2088 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2089 {
2090 struct si_shader *shader = (struct si_shader *)job;
2091
2092 assert(thread_index >= 0);
2093
2094 si_build_shader_variant(shader, thread_index, true);
2095 }
2096
2097 static const struct si_shader_key zeroed;
2098
2099 static bool si_check_missing_main_part(struct si_screen *sscreen,
2100 struct si_shader_selector *sel,
2101 struct si_compiler_ctx_state *compiler_state,
2102 struct si_shader_key *key)
2103 {
2104 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2105
2106 if (!*mainp) {
2107 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2108
2109 if (!main_part)
2110 return false;
2111
2112 /* We can leave the fence as permanently signaled because the
2113 * main part becomes visible globally only after it has been
2114 * compiled. */
2115 util_queue_fence_init(&main_part->ready);
2116
2117 main_part->selector = sel;
2118 main_part->key.as_es = key->as_es;
2119 main_part->key.as_ls = key->as_ls;
2120 main_part->key.as_ngg = key->as_ngg;
2121 main_part->is_monolithic = false;
2122
2123 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
2124 main_part, &compiler_state->debug) != 0) {
2125 FREE(main_part);
2126 return false;
2127 }
2128 *mainp = main_part;
2129 }
2130 return true;
2131 }
2132
2133 /**
2134 * Select a shader variant according to the shader key.
2135 *
2136 * \param optimized_or_none If the key describes an optimized shader variant and
2137 * the compilation isn't finished, don't select any
2138 * shader and return an error.
2139 */
2140 int si_shader_select_with_key(struct si_screen *sscreen,
2141 struct si_shader_ctx_state *state,
2142 struct si_compiler_ctx_state *compiler_state,
2143 struct si_shader_key *key,
2144 int thread_index,
2145 bool optimized_or_none)
2146 {
2147 struct si_shader_selector *sel = state->cso;
2148 struct si_shader_selector *previous_stage_sel = NULL;
2149 struct si_shader *current = state->current;
2150 struct si_shader *iter, *shader = NULL;
2151
2152 again:
2153 /* Check if we don't need to change anything.
2154 * This path is also used for most shaders that don't need multiple
2155 * variants, it will cost just a computation of the key and this
2156 * test. */
2157 if (likely(current &&
2158 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2159 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2160 if (current->is_optimized) {
2161 if (optimized_or_none)
2162 return -1;
2163
2164 memset(&key->opt, 0, sizeof(key->opt));
2165 goto current_not_ready;
2166 }
2167
2168 util_queue_fence_wait(&current->ready);
2169 }
2170
2171 return current->compilation_failed ? -1 : 0;
2172 }
2173 current_not_ready:
2174
2175 /* This must be done before the mutex is locked, because async GS
2176 * compilation calls this function too, and therefore must enter
2177 * the mutex first.
2178 *
2179 * Only wait if we are in a draw call. Don't wait if we are
2180 * in a compiler thread.
2181 */
2182 if (thread_index < 0)
2183 util_queue_fence_wait(&sel->ready);
2184
2185 mtx_lock(&sel->mutex);
2186
2187 /* Find the shader variant. */
2188 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2189 /* Don't check the "current" shader. We checked it above. */
2190 if (current != iter &&
2191 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2192 mtx_unlock(&sel->mutex);
2193
2194 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2195 /* If it's an optimized shader and its compilation has
2196 * been started but isn't done, use the unoptimized
2197 * shader so as not to cause a stall due to compilation.
2198 */
2199 if (iter->is_optimized) {
2200 if (optimized_or_none)
2201 return -1;
2202 memset(&key->opt, 0, sizeof(key->opt));
2203 goto again;
2204 }
2205
2206 util_queue_fence_wait(&iter->ready);
2207 }
2208
2209 if (iter->compilation_failed) {
2210 return -1; /* skip the draw call */
2211 }
2212
2213 state->current = iter;
2214 return 0;
2215 }
2216 }
2217
2218 /* Build a new shader. */
2219 shader = CALLOC_STRUCT(si_shader);
2220 if (!shader) {
2221 mtx_unlock(&sel->mutex);
2222 return -ENOMEM;
2223 }
2224
2225 util_queue_fence_init(&shader->ready);
2226
2227 shader->selector = sel;
2228 shader->key = *key;
2229 shader->compiler_ctx_state = *compiler_state;
2230
2231 /* If this is a merged shader, get the first shader's selector. */
2232 if (sscreen->info.chip_class >= GFX9) {
2233 if (sel->type == PIPE_SHADER_TESS_CTRL)
2234 previous_stage_sel = key->part.tcs.ls;
2235 else if (sel->type == PIPE_SHADER_GEOMETRY)
2236 previous_stage_sel = key->part.gs.es;
2237
2238 /* We need to wait for the previous shader. */
2239 if (previous_stage_sel && thread_index < 0)
2240 util_queue_fence_wait(&previous_stage_sel->ready);
2241 }
2242
2243 bool is_pure_monolithic =
2244 sscreen->use_monolithic_shaders ||
2245 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2246
2247 /* Compile the main shader part if it doesn't exist. This can happen
2248 * if the initial guess was wrong.
2249 *
2250 * The prim discard CS doesn't need the main shader part.
2251 */
2252 if (!is_pure_monolithic &&
2253 !key->opt.vs_as_prim_discard_cs) {
2254 bool ok = true;
2255
2256 /* Make sure the main shader part is present. This is needed
2257 * for shaders that can be compiled as VS, LS, or ES, and only
2258 * one of them is compiled at creation.
2259 *
2260 * It is also needed for GS, which can be compiled as non-NGG
2261 * and NGG.
2262 *
2263 * For merged shaders, check that the starting shader's main
2264 * part is present.
2265 */
2266 if (previous_stage_sel) {
2267 struct si_shader_key shader1_key = zeroed;
2268
2269 if (sel->type == PIPE_SHADER_TESS_CTRL)
2270 shader1_key.as_ls = 1;
2271 else if (sel->type == PIPE_SHADER_GEOMETRY)
2272 shader1_key.as_es = 1;
2273 else
2274 assert(0);
2275
2276 mtx_lock(&previous_stage_sel->mutex);
2277 ok = si_check_missing_main_part(sscreen,
2278 previous_stage_sel,
2279 compiler_state, &shader1_key);
2280 mtx_unlock(&previous_stage_sel->mutex);
2281 }
2282
2283 if (ok) {
2284 ok = si_check_missing_main_part(sscreen, sel,
2285 compiler_state, key);
2286 }
2287
2288 if (!ok) {
2289 FREE(shader);
2290 mtx_unlock(&sel->mutex);
2291 return -ENOMEM; /* skip the draw call */
2292 }
2293 }
2294
2295 /* Keep the reference to the 1st shader of merged shaders, so that
2296 * Gallium can't destroy it before we destroy the 2nd shader.
2297 *
2298 * Set sctx = NULL, because it's unused if we're not releasing
2299 * the shader, and we don't have any sctx here.
2300 */
2301 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2302 previous_stage_sel);
2303
2304 /* Monolithic-only shaders don't make a distinction between optimized
2305 * and unoptimized. */
2306 shader->is_monolithic =
2307 is_pure_monolithic ||
2308 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2309
2310 /* The prim discard CS is always optimized. */
2311 shader->is_optimized =
2312 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2313 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2314
2315 /* If it's an optimized shader, compile it asynchronously. */
2316 if (shader->is_optimized && thread_index < 0) {
2317 /* Compile it asynchronously. */
2318 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2319 shader, &shader->ready,
2320 si_build_shader_variant_low_priority, NULL);
2321
2322 /* Add only after the ready fence was reset, to guard against a
2323 * race with si_bind_XX_shader. */
2324 if (!sel->last_variant) {
2325 sel->first_variant = shader;
2326 sel->last_variant = shader;
2327 } else {
2328 sel->last_variant->next_variant = shader;
2329 sel->last_variant = shader;
2330 }
2331
2332 /* Use the default (unoptimized) shader for now. */
2333 memset(&key->opt, 0, sizeof(key->opt));
2334 mtx_unlock(&sel->mutex);
2335
2336 if (sscreen->options.sync_compile)
2337 util_queue_fence_wait(&shader->ready);
2338
2339 if (optimized_or_none)
2340 return -1;
2341 goto again;
2342 }
2343
2344 /* Reset the fence before adding to the variant list. */
2345 util_queue_fence_reset(&shader->ready);
2346
2347 if (!sel->last_variant) {
2348 sel->first_variant = shader;
2349 sel->last_variant = shader;
2350 } else {
2351 sel->last_variant->next_variant = shader;
2352 sel->last_variant = shader;
2353 }
2354
2355 mtx_unlock(&sel->mutex);
2356
2357 assert(!shader->is_optimized);
2358 si_build_shader_variant(shader, thread_index, false);
2359
2360 util_queue_fence_signal(&shader->ready);
2361
2362 if (!shader->compilation_failed)
2363 state->current = shader;
2364
2365 return shader->compilation_failed ? -1 : 0;
2366 }
2367
2368 static int si_shader_select(struct pipe_context *ctx,
2369 struct si_shader_ctx_state *state,
2370 union si_vgt_stages_key stages_key,
2371 struct si_compiler_ctx_state *compiler_state)
2372 {
2373 struct si_context *sctx = (struct si_context *)ctx;
2374 struct si_shader_key key;
2375
2376 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2377 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2378 &key, -1, false);
2379 }
2380
2381 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
2382 bool streamout,
2383 struct si_shader_key *key)
2384 {
2385 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2386
2387 switch (info->processor) {
2388 case PIPE_SHADER_VERTEX:
2389 switch (next_shader) {
2390 case PIPE_SHADER_GEOMETRY:
2391 key->as_es = 1;
2392 break;
2393 case PIPE_SHADER_TESS_CTRL:
2394 case PIPE_SHADER_TESS_EVAL:
2395 key->as_ls = 1;
2396 break;
2397 default:
2398 /* If POSITION isn't written, it can only be a HW VS
2399 * if streamout is used. If streamout isn't used,
2400 * assume that it's a HW LS. (the next shader is TCS)
2401 * This heuristic is needed for separate shader objects.
2402 */
2403 if (!info->writes_position && !streamout)
2404 key->as_ls = 1;
2405 }
2406 break;
2407
2408 case PIPE_SHADER_TESS_EVAL:
2409 if (next_shader == PIPE_SHADER_GEOMETRY ||
2410 !info->writes_position)
2411 key->as_es = 1;
2412 break;
2413 }
2414 }
2415
2416 /**
2417 * Compile the main shader part or the monolithic shader as part of
2418 * si_shader_selector initialization. Since it can be done asynchronously,
2419 * there is no way to report compile failures to applications.
2420 */
2421 static void si_init_shader_selector_async(void *job, int thread_index)
2422 {
2423 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2424 struct si_screen *sscreen = sel->screen;
2425 struct ac_llvm_compiler *compiler;
2426 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2427
2428 assert(!debug->debug_message || debug->async);
2429 assert(thread_index >= 0);
2430 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2431 compiler = &sscreen->compiler[thread_index];
2432
2433 if (sel->nir)
2434 si_lower_nir(sel);
2435
2436 /* Compile the main shader part for use with a prolog and/or epilog.
2437 * If this fails, the driver will try to compile a monolithic shader
2438 * on demand.
2439 */
2440 if (!sscreen->use_monolithic_shaders) {
2441 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2442 void *ir_binary = NULL;
2443
2444 if (!shader) {
2445 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2446 return;
2447 }
2448
2449 /* We can leave the fence signaled because use of the default
2450 * main part is guarded by the selector's ready fence. */
2451 util_queue_fence_init(&shader->ready);
2452
2453 shader->selector = sel;
2454 shader->is_monolithic = false;
2455 si_parse_next_shader_property(&sel->info,
2456 sel->so.num_outputs != 0,
2457 &shader->key);
2458 if (sscreen->info.chip_class >= GFX10 &&
2459 !sscreen->options.disable_ngg &&
2460 (((sel->type == PIPE_SHADER_VERTEX ||
2461 sel->type == PIPE_SHADER_TESS_EVAL) &&
2462 !shader->key.as_ls && !shader->key.as_es) ||
2463 sel->type == PIPE_SHADER_GEOMETRY))
2464 shader->key.as_ngg = 1;
2465
2466 if (sel->tokens || sel->nir)
2467 ir_binary = si_get_ir_binary(sel);
2468
2469 /* Try to load the shader from the shader cache. */
2470 mtx_lock(&sscreen->shader_cache_mutex);
2471
2472 if (ir_binary &&
2473 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
2474 mtx_unlock(&sscreen->shader_cache_mutex);
2475 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2476 } else {
2477 mtx_unlock(&sscreen->shader_cache_mutex);
2478
2479 /* Compile the shader if it hasn't been loaded from the cache. */
2480 if (si_compile_tgsi_shader(sscreen, compiler, shader,
2481 debug) != 0) {
2482 FREE(shader);
2483 FREE(ir_binary);
2484 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2485 return;
2486 }
2487
2488 if (ir_binary) {
2489 mtx_lock(&sscreen->shader_cache_mutex);
2490 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
2491 FREE(ir_binary);
2492 mtx_unlock(&sscreen->shader_cache_mutex);
2493 }
2494 }
2495
2496 *si_get_main_shader_part(sel, &shader->key) = shader;
2497
2498 /* Unset "outputs_written" flags for outputs converted to
2499 * DEFAULT_VAL, so that later inter-shader optimizations don't
2500 * try to eliminate outputs that don't exist in the final
2501 * shader.
2502 *
2503 * This is only done if non-monolithic shaders are enabled.
2504 */
2505 if ((sel->type == PIPE_SHADER_VERTEX ||
2506 sel->type == PIPE_SHADER_TESS_EVAL) &&
2507 !shader->key.as_ls &&
2508 !shader->key.as_es) {
2509 unsigned i;
2510
2511 for (i = 0; i < sel->info.num_outputs; i++) {
2512 unsigned offset = shader->info.vs_output_param_offset[i];
2513
2514 if (offset <= AC_EXP_PARAM_OFFSET_31)
2515 continue;
2516
2517 unsigned name = sel->info.output_semantic_name[i];
2518 unsigned index = sel->info.output_semantic_index[i];
2519 unsigned id;
2520
2521 switch (name) {
2522 case TGSI_SEMANTIC_GENERIC:
2523 /* don't process indices the function can't handle */
2524 if (index >= SI_MAX_IO_GENERIC)
2525 break;
2526 /* fall through */
2527 default:
2528 id = si_shader_io_get_unique_index(name, index, true);
2529 sel->outputs_written_before_ps &= ~(1ull << id);
2530 break;
2531 case TGSI_SEMANTIC_POSITION: /* ignore these */
2532 case TGSI_SEMANTIC_PSIZE:
2533 case TGSI_SEMANTIC_CLIPVERTEX:
2534 case TGSI_SEMANTIC_EDGEFLAG:
2535 break;
2536 }
2537 }
2538 }
2539 }
2540
2541 /* The GS copy shader is always pre-compiled.
2542 *
2543 * TODO-GFX10: We could compile the GS copy shader on demand, since it
2544 * is only used in the (rare) non-NGG case.
2545 */
2546 if (sel->type == PIPE_SHADER_GEOMETRY) {
2547 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2548 if (!sel->gs_copy_shader) {
2549 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2550 return;
2551 }
2552
2553 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2554 }
2555 }
2556
2557 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2558 struct util_queue_fence *ready_fence,
2559 struct si_compiler_ctx_state *compiler_ctx_state,
2560 void *job, util_queue_execute_func execute)
2561 {
2562 util_queue_fence_init(ready_fence);
2563
2564 struct util_async_debug_callback async_debug;
2565 bool debug =
2566 (sctx->debug.debug_message && !sctx->debug.async) ||
2567 sctx->is_debug ||
2568 si_can_dump_shader(sctx->screen, processor);
2569
2570 if (debug) {
2571 u_async_debug_init(&async_debug);
2572 compiler_ctx_state->debug = async_debug.base;
2573 }
2574
2575 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2576 ready_fence, execute, NULL);
2577
2578 if (debug) {
2579 util_queue_fence_wait(ready_fence);
2580 u_async_debug_drain(&async_debug, &sctx->debug);
2581 u_async_debug_cleanup(&async_debug);
2582 }
2583
2584 if (sctx->screen->options.sync_compile)
2585 util_queue_fence_wait(ready_fence);
2586 }
2587
2588 /* Return descriptor slot usage masks from the given shader info. */
2589 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2590 uint32_t *const_and_shader_buffers,
2591 uint64_t *samplers_and_images)
2592 {
2593 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2594
2595 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2596 num_constbufs = util_last_bit(info->const_buffers_declared);
2597 /* two 8-byte images share one 16-byte slot */
2598 num_images = align(util_last_bit(info->images_declared), 2);
2599 num_samplers = util_last_bit(info->samplers_declared);
2600
2601 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2602 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2603 *const_and_shader_buffers =
2604 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2605
2606 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2607 start = si_get_image_slot(num_images - 1) / 2;
2608 *samplers_and_images =
2609 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2610 }
2611
2612 static void *si_create_shader_selector(struct pipe_context *ctx,
2613 const struct pipe_shader_state *state)
2614 {
2615 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2616 struct si_context *sctx = (struct si_context*)ctx;
2617 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2618 int i;
2619
2620 if (!sel)
2621 return NULL;
2622
2623 pipe_reference_init(&sel->reference, 1);
2624 sel->screen = sscreen;
2625 sel->compiler_ctx_state.debug = sctx->debug;
2626 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2627
2628 sel->so = state->stream_output;
2629
2630 if (state->type == PIPE_SHADER_IR_TGSI) {
2631 sel->tokens = tgsi_dup_tokens(state->tokens);
2632 if (!sel->tokens) {
2633 FREE(sel);
2634 return NULL;
2635 }
2636
2637 tgsi_scan_shader(state->tokens, &sel->info);
2638 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2639 } else {
2640 assert(state->type == PIPE_SHADER_IR_NIR);
2641
2642 sel->nir = state->ir.nir;
2643
2644 si_nir_opts(sel->nir);
2645 si_nir_scan_shader(sel->nir, &sel->info);
2646 si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
2647 }
2648
2649 sel->type = sel->info.processor;
2650 p_atomic_inc(&sscreen->num_shaders_created);
2651 si_get_active_slot_masks(&sel->info,
2652 &sel->active_const_and_shader_buffers,
2653 &sel->active_samplers_and_images);
2654
2655 /* Record which streamout buffers are enabled. */
2656 for (i = 0; i < sel->so.num_outputs; i++) {
2657 sel->enabled_streamout_buffer_mask |=
2658 (1 << sel->so.output[i].output_buffer) <<
2659 (sel->so.output[i].stream * 4);
2660 }
2661
2662 /* The prolog is a no-op if there are no inputs. */
2663 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2664 sel->info.num_inputs &&
2665 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2666
2667 sel->force_correct_derivs_after_kill =
2668 sel->type == PIPE_SHADER_FRAGMENT &&
2669 sel->info.uses_derivatives &&
2670 sel->info.uses_kill &&
2671 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2672
2673 sel->prim_discard_cs_allowed =
2674 sel->type == PIPE_SHADER_VERTEX &&
2675 !sel->info.uses_bindless_images &&
2676 !sel->info.uses_bindless_samplers &&
2677 !sel->info.writes_memory &&
2678 !sel->info.writes_viewport_index &&
2679 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2680 !sel->so.num_outputs;
2681
2682 /* Set which opcode uses which (i,j) pair. */
2683 if (sel->info.uses_persp_opcode_interp_centroid)
2684 sel->info.uses_persp_centroid = true;
2685
2686 if (sel->info.uses_linear_opcode_interp_centroid)
2687 sel->info.uses_linear_centroid = true;
2688
2689 if (sel->info.uses_persp_opcode_interp_offset ||
2690 sel->info.uses_persp_opcode_interp_sample)
2691 sel->info.uses_persp_center = true;
2692
2693 if (sel->info.uses_linear_opcode_interp_offset ||
2694 sel->info.uses_linear_opcode_interp_sample)
2695 sel->info.uses_linear_center = true;
2696
2697 switch (sel->type) {
2698 case PIPE_SHADER_GEOMETRY:
2699 sel->gs_output_prim =
2700 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2701
2702 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2703 sel->rast_prim = sel->gs_output_prim;
2704 if (util_rast_prim_is_triangles(sel->rast_prim))
2705 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2706
2707 sel->gs_max_out_vertices =
2708 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2709 sel->gs_num_invocations =
2710 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2711 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2712 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2713 sel->gs_max_out_vertices;
2714
2715 sel->max_gs_stream = 0;
2716 for (i = 0; i < sel->so.num_outputs; i++)
2717 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2718 sel->so.output[i].stream);
2719
2720 sel->gs_input_verts_per_prim =
2721 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2722 break;
2723
2724 case PIPE_SHADER_TESS_CTRL:
2725 /* Always reserve space for these. */
2726 sel->patch_outputs_written |=
2727 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2728 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2729 /* fall through */
2730 case PIPE_SHADER_VERTEX:
2731 case PIPE_SHADER_TESS_EVAL:
2732 for (i = 0; i < sel->info.num_outputs; i++) {
2733 unsigned name = sel->info.output_semantic_name[i];
2734 unsigned index = sel->info.output_semantic_index[i];
2735
2736 switch (name) {
2737 case TGSI_SEMANTIC_TESSINNER:
2738 case TGSI_SEMANTIC_TESSOUTER:
2739 case TGSI_SEMANTIC_PATCH:
2740 sel->patch_outputs_written |=
2741 1ull << si_shader_io_get_unique_index_patch(name, index);
2742 break;
2743
2744 case TGSI_SEMANTIC_GENERIC:
2745 /* don't process indices the function can't handle */
2746 if (index >= SI_MAX_IO_GENERIC)
2747 break;
2748 /* fall through */
2749 default:
2750 sel->outputs_written |=
2751 1ull << si_shader_io_get_unique_index(name, index, false);
2752 sel->outputs_written_before_ps |=
2753 1ull << si_shader_io_get_unique_index(name, index, true);
2754 break;
2755 case TGSI_SEMANTIC_EDGEFLAG:
2756 break;
2757 }
2758 }
2759 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2760 sel->lshs_vertex_stride = sel->esgs_itemsize;
2761
2762 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2763 * will start on a different bank. (except for the maximum 32*16).
2764 */
2765 if (sel->lshs_vertex_stride < 32*16)
2766 sel->lshs_vertex_stride += 4;
2767
2768 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2769 * conflicts, i.e. each vertex will start at a different bank.
2770 */
2771 if (sctx->chip_class >= GFX9)
2772 sel->esgs_itemsize += 4;
2773
2774 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2775
2776 /* Only for TES: */
2777 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2778 sel->rast_prim = PIPE_PRIM_POINTS;
2779 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2780 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2781 else
2782 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2783 break;
2784
2785 case PIPE_SHADER_FRAGMENT:
2786 for (i = 0; i < sel->info.num_inputs; i++) {
2787 unsigned name = sel->info.input_semantic_name[i];
2788 unsigned index = sel->info.input_semantic_index[i];
2789
2790 switch (name) {
2791 case TGSI_SEMANTIC_GENERIC:
2792 /* don't process indices the function can't handle */
2793 if (index >= SI_MAX_IO_GENERIC)
2794 break;
2795 /* fall through */
2796 default:
2797 sel->inputs_read |=
2798 1ull << si_shader_io_get_unique_index(name, index, true);
2799 break;
2800 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2801 break;
2802 }
2803 }
2804
2805 for (i = 0; i < 8; i++)
2806 if (sel->info.colors_written & (1 << i))
2807 sel->colors_written_4bit |= 0xf << (4 * i);
2808
2809 for (i = 0; i < sel->info.num_inputs; i++) {
2810 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2811 int index = sel->info.input_semantic_index[i];
2812 sel->color_attr_index[index] = i;
2813 }
2814 }
2815 break;
2816 default:;
2817 }
2818
2819 /* PA_CL_VS_OUT_CNTL */
2820 bool misc_vec_ena =
2821 sel->info.writes_psize || sel->info.writes_edgeflag ||
2822 sel->info.writes_layer || sel->info.writes_viewport_index;
2823 sel->pa_cl_vs_out_cntl =
2824 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2825 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2826 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2827 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2828 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2829 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2830 sel->clipdist_mask = sel->info.writes_clipvertex ?
2831 SIX_BITS : sel->info.clipdist_writemask;
2832 sel->culldist_mask = sel->info.culldist_writemask <<
2833 sel->info.num_written_clipdistance;
2834
2835 /* DB_SHADER_CONTROL */
2836 sel->db_shader_control =
2837 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2838 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2839 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2840 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2841
2842 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2843 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2844 sel->db_shader_control |=
2845 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2846 break;
2847 case TGSI_FS_DEPTH_LAYOUT_LESS:
2848 sel->db_shader_control |=
2849 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2850 break;
2851 }
2852
2853 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2854 *
2855 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2856 * --|-----------|------------|------------|--------------------|-------------------|-------------
2857 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2858 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2859 * 2 | false | true | n/a | LateZ | 1 | 0
2860 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2861 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2862 *
2863 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2864 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2865 *
2866 * Don't use ReZ without profiling !!!
2867 *
2868 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2869 * shaders.
2870 */
2871 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2872 /* Cases 3, 4. */
2873 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2874 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2875 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2876 } else if (sel->info.writes_memory) {
2877 /* Case 2. */
2878 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2879 S_02880C_EXEC_ON_HIER_FAIL(1);
2880 } else {
2881 /* Case 1. */
2882 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2883 }
2884
2885 if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
2886 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2887
2888 (void) mtx_init(&sel->mutex, mtx_plain);
2889
2890 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2891 &sel->compiler_ctx_state, sel,
2892 si_init_shader_selector_async);
2893 return sel;
2894 }
2895
2896 static void si_update_streamout_state(struct si_context *sctx)
2897 {
2898 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2899
2900 if (!shader_with_so)
2901 return;
2902
2903 sctx->streamout.enabled_stream_buffers_mask =
2904 shader_with_so->enabled_streamout_buffer_mask;
2905 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2906 }
2907
2908 static void si_update_clip_regs(struct si_context *sctx,
2909 struct si_shader_selector *old_hw_vs,
2910 struct si_shader *old_hw_vs_variant,
2911 struct si_shader_selector *next_hw_vs,
2912 struct si_shader *next_hw_vs_variant)
2913 {
2914 if (next_hw_vs &&
2915 (!old_hw_vs ||
2916 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2917 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2918 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2919 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2920 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2921 !old_hw_vs_variant ||
2922 !next_hw_vs_variant ||
2923 old_hw_vs_variant->key.opt.clip_disable !=
2924 next_hw_vs_variant->key.opt.clip_disable))
2925 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2926 }
2927
2928 static void si_update_common_shader_state(struct si_context *sctx)
2929 {
2930 sctx->uses_bindless_samplers =
2931 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2932 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2933 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2934 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2935 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2936 sctx->uses_bindless_images =
2937 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2938 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2939 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2940 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2941 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2942 sctx->do_update_shaders = true;
2943 }
2944
2945 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2946 {
2947 struct si_context *sctx = (struct si_context *)ctx;
2948 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2949 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2950 struct si_shader_selector *sel = state;
2951
2952 if (sctx->vs_shader.cso == sel)
2953 return;
2954
2955 sctx->vs_shader.cso = sel;
2956 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2957 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2958
2959 si_update_common_shader_state(sctx);
2960 si_update_vs_viewport_state(sctx);
2961 si_set_active_descriptors_for_shader(sctx, sel);
2962 si_update_streamout_state(sctx);
2963 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2964 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2965 }
2966
2967 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2968 {
2969 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2970 (sctx->tes_shader.cso &&
2971 sctx->tes_shader.cso->info.uses_primid) ||
2972 (sctx->tcs_shader.cso &&
2973 sctx->tcs_shader.cso->info.uses_primid) ||
2974 (sctx->gs_shader.cso &&
2975 sctx->gs_shader.cso->info.uses_primid) ||
2976 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2977 sctx->ps_shader.cso->info.uses_primid);
2978 }
2979
2980 static bool si_update_ngg(struct si_context *sctx)
2981 {
2982 if (sctx->chip_class <= GFX9 ||
2983 sctx->screen->options.disable_ngg)
2984 return false;
2985
2986 bool new_ngg = true;
2987
2988 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2989 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
2990 sctx->gs_shader.cso->gs_num_invocations * sctx->gs_shader.cso->gs_max_out_vertices > 256)
2991 new_ngg = false;
2992
2993 if (new_ngg != sctx->ngg) {
2994 sctx->ngg = new_ngg;
2995 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2996 return true;
2997 }
2998 return false;
2999 }
3000
3001 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
3002 {
3003 struct si_context *sctx = (struct si_context *)ctx;
3004 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3005 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3006 struct si_shader_selector *sel = state;
3007 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
3008 bool ngg_changed;
3009
3010 if (sctx->gs_shader.cso == sel)
3011 return;
3012
3013 sctx->gs_shader.cso = sel;
3014 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
3015 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
3016
3017 si_update_common_shader_state(sctx);
3018 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3019
3020 ngg_changed = si_update_ngg(sctx);
3021 if (ngg_changed || enable_changed)
3022 si_shader_change_notify(sctx);
3023 if (enable_changed) {
3024 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3025 si_update_tess_uses_prim_id(sctx);
3026 }
3027 si_update_vs_viewport_state(sctx);
3028 si_set_active_descriptors_for_shader(sctx, sel);
3029 si_update_streamout_state(sctx);
3030 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3031 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3032 }
3033
3034 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3035 {
3036 struct si_context *sctx = (struct si_context *)ctx;
3037 struct si_shader_selector *sel = state;
3038 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3039
3040 if (sctx->tcs_shader.cso == sel)
3041 return;
3042
3043 sctx->tcs_shader.cso = sel;
3044 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3045 si_update_tess_uses_prim_id(sctx);
3046
3047 si_update_common_shader_state(sctx);
3048
3049 if (enable_changed)
3050 sctx->last_tcs = NULL; /* invalidate derived tess state */
3051
3052 si_set_active_descriptors_for_shader(sctx, sel);
3053 }
3054
3055 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3056 {
3057 struct si_context *sctx = (struct si_context *)ctx;
3058 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3059 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3060 struct si_shader_selector *sel = state;
3061 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3062
3063 if (sctx->tes_shader.cso == sel)
3064 return;
3065
3066 sctx->tes_shader.cso = sel;
3067 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3068 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3069 si_update_tess_uses_prim_id(sctx);
3070
3071 si_update_common_shader_state(sctx);
3072 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3073
3074 if (enable_changed) {
3075 si_update_ngg(sctx);
3076 si_shader_change_notify(sctx);
3077 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3078 }
3079 si_update_vs_viewport_state(sctx);
3080 si_set_active_descriptors_for_shader(sctx, sel);
3081 si_update_streamout_state(sctx);
3082 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3083 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3084 }
3085
3086 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3087 {
3088 struct si_context *sctx = (struct si_context *)ctx;
3089 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3090 struct si_shader_selector *sel = state;
3091
3092 /* skip if supplied shader is one already in use */
3093 if (old_sel == sel)
3094 return;
3095
3096 sctx->ps_shader.cso = sel;
3097 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3098
3099 si_update_common_shader_state(sctx);
3100 if (sel) {
3101 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3102 si_update_tess_uses_prim_id(sctx);
3103
3104 if (!old_sel ||
3105 old_sel->info.colors_written != sel->info.colors_written)
3106 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3107
3108 if (sctx->screen->has_out_of_order_rast &&
3109 (!old_sel ||
3110 old_sel->info.writes_memory != sel->info.writes_memory ||
3111 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3112 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3113 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3114 }
3115 si_set_active_descriptors_for_shader(sctx, sel);
3116 si_update_ps_colorbuf0_slot(sctx);
3117 }
3118
3119 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3120 {
3121 if (shader->is_optimized) {
3122 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3123 &shader->ready);
3124 }
3125
3126 util_queue_fence_destroy(&shader->ready);
3127
3128 if (shader->pm4) {
3129 /* If destroyed shaders were not unbound, the next compiled
3130 * shader variant could get the same pointer address and so
3131 * binding it to the same shader stage would be considered
3132 * a no-op, causing random behavior.
3133 */
3134 switch (shader->selector->type) {
3135 case PIPE_SHADER_VERTEX:
3136 if (shader->key.as_ls) {
3137 assert(sctx->chip_class <= GFX8);
3138 si_pm4_delete_state(sctx, ls, shader->pm4);
3139 } else if (shader->key.as_es) {
3140 assert(sctx->chip_class <= GFX8);
3141 si_pm4_delete_state(sctx, es, shader->pm4);
3142 } else if (shader->key.as_ngg) {
3143 si_pm4_delete_state(sctx, gs, shader->pm4);
3144 } else {
3145 si_pm4_delete_state(sctx, vs, shader->pm4);
3146 }
3147 break;
3148 case PIPE_SHADER_TESS_CTRL:
3149 si_pm4_delete_state(sctx, hs, shader->pm4);
3150 break;
3151 case PIPE_SHADER_TESS_EVAL:
3152 if (shader->key.as_es) {
3153 assert(sctx->chip_class <= GFX8);
3154 si_pm4_delete_state(sctx, es, shader->pm4);
3155 } else if (shader->key.as_ngg) {
3156 si_pm4_delete_state(sctx, gs, shader->pm4);
3157 } else {
3158 si_pm4_delete_state(sctx, vs, shader->pm4);
3159 }
3160 break;
3161 case PIPE_SHADER_GEOMETRY:
3162 if (shader->is_gs_copy_shader)
3163 si_pm4_delete_state(sctx, vs, shader->pm4);
3164 else
3165 si_pm4_delete_state(sctx, gs, shader->pm4);
3166 break;
3167 case PIPE_SHADER_FRAGMENT:
3168 si_pm4_delete_state(sctx, ps, shader->pm4);
3169 break;
3170 default:;
3171 }
3172 }
3173
3174 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3175 si_shader_destroy(shader);
3176 free(shader);
3177 }
3178
3179 void si_destroy_shader_selector(struct si_context *sctx,
3180 struct si_shader_selector *sel)
3181 {
3182 struct si_shader *p = sel->first_variant, *c;
3183 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3184 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3185 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3186 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3187 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3188 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3189 };
3190
3191 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3192
3193 if (current_shader[sel->type]->cso == sel) {
3194 current_shader[sel->type]->cso = NULL;
3195 current_shader[sel->type]->current = NULL;
3196 }
3197
3198 while (p) {
3199 c = p->next_variant;
3200 si_delete_shader(sctx, p);
3201 p = c;
3202 }
3203
3204 if (sel->main_shader_part)
3205 si_delete_shader(sctx, sel->main_shader_part);
3206 if (sel->main_shader_part_ls)
3207 si_delete_shader(sctx, sel->main_shader_part_ls);
3208 if (sel->main_shader_part_es)
3209 si_delete_shader(sctx, sel->main_shader_part_es);
3210 if (sel->main_shader_part_ngg)
3211 si_delete_shader(sctx, sel->main_shader_part_ngg);
3212 if (sel->gs_copy_shader)
3213 si_delete_shader(sctx, sel->gs_copy_shader);
3214
3215 util_queue_fence_destroy(&sel->ready);
3216 mtx_destroy(&sel->mutex);
3217 free(sel->tokens);
3218 ralloc_free(sel->nir);
3219 free(sel);
3220 }
3221
3222 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3223 {
3224 struct si_context *sctx = (struct si_context *)ctx;
3225 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3226
3227 si_shader_selector_reference(sctx, &sel, NULL);
3228 }
3229
3230 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3231 struct si_shader *vs, unsigned name,
3232 unsigned index, unsigned interpolate)
3233 {
3234 struct tgsi_shader_info *vsinfo = &vs->selector->info;
3235 unsigned j, offset, ps_input_cntl = 0;
3236
3237 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3238 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3239 name == TGSI_SEMANTIC_PRIMID)
3240 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3241
3242 if (name == TGSI_SEMANTIC_PCOORD ||
3243 (name == TGSI_SEMANTIC_TEXCOORD &&
3244 sctx->sprite_coord_enable & (1 << index))) {
3245 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3246 }
3247
3248 for (j = 0; j < vsinfo->num_outputs; j++) {
3249 if (name == vsinfo->output_semantic_name[j] &&
3250 index == vsinfo->output_semantic_index[j]) {
3251 offset = vs->info.vs_output_param_offset[j];
3252
3253 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3254 /* The input is loaded from parameter memory. */
3255 ps_input_cntl |= S_028644_OFFSET(offset);
3256 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3257 if (offset == AC_EXP_PARAM_UNDEFINED) {
3258 /* This can happen with depth-only rendering. */
3259 offset = 0;
3260 } else {
3261 /* The input is a DEFAULT_VAL constant. */
3262 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3263 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3264 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3265 }
3266
3267 ps_input_cntl = S_028644_OFFSET(0x20) |
3268 S_028644_DEFAULT_VAL(offset);
3269 }
3270 break;
3271 }
3272 }
3273
3274 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3275 /* PrimID is written after the last output when HW VS is used. */
3276 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3277 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3278 /* No corresponding output found, load defaults into input.
3279 * Don't set any other bits.
3280 * (FLAT_SHADE=1 completely changes behavior) */
3281 ps_input_cntl = S_028644_OFFSET(0x20);
3282 /* D3D 9 behaviour. GL is undefined */
3283 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3284 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3285 }
3286 return ps_input_cntl;
3287 }
3288
3289 static void si_emit_spi_map(struct si_context *sctx)
3290 {
3291 struct si_shader *ps = sctx->ps_shader.current;
3292 struct si_shader *vs = si_get_vs_state(sctx);
3293 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3294 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3295 unsigned spi_ps_input_cntl[32];
3296
3297 if (!ps || !ps->selector->info.num_inputs)
3298 return;
3299
3300 num_interp = si_get_ps_num_interp(ps);
3301 assert(num_interp > 0);
3302
3303 for (i = 0; i < psinfo->num_inputs; i++) {
3304 unsigned name = psinfo->input_semantic_name[i];
3305 unsigned index = psinfo->input_semantic_index[i];
3306 unsigned interpolate = psinfo->input_interpolate[i];
3307
3308 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3309 index, interpolate);
3310
3311 if (name == TGSI_SEMANTIC_COLOR) {
3312 assert(index < ARRAY_SIZE(bcol_interp));
3313 bcol_interp[index] = interpolate;
3314 }
3315 }
3316
3317 if (ps->key.part.ps.prolog.color_two_side) {
3318 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3319
3320 for (i = 0; i < 2; i++) {
3321 if (!(psinfo->colors_read & (0xf << (i * 4))))
3322 continue;
3323
3324 spi_ps_input_cntl[num_written++] =
3325 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3326
3327 }
3328 }
3329 assert(num_interp == num_written);
3330
3331 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3332 /* Dota 2: Only ~16% of SPI map updates set different values. */
3333 /* Talos: Only ~9% of SPI map updates set different values. */
3334 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3335 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3336 spi_ps_input_cntl,
3337 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3338
3339 if (initial_cdw != sctx->gfx_cs->current.cdw)
3340 sctx->context_roll = true;
3341 }
3342
3343 /**
3344 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3345 */
3346 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3347 {
3348 if (sctx->init_config_has_vgt_flush)
3349 return;
3350
3351 /* Done by Vulkan before VGT_FLUSH. */
3352 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3353 si_pm4_cmd_add(sctx->init_config,
3354 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3355 si_pm4_cmd_end(sctx->init_config, false);
3356
3357 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3358 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3359 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3360 si_pm4_cmd_end(sctx->init_config, false);
3361 sctx->init_config_has_vgt_flush = true;
3362 }
3363
3364 /* Initialize state related to ESGS / GSVS ring buffers */
3365 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3366 {
3367 struct si_shader_selector *es =
3368 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3369 struct si_shader_selector *gs = sctx->gs_shader.cso;
3370 struct si_pm4_state *pm4;
3371
3372 /* Chip constants. */
3373 unsigned num_se = sctx->screen->info.max_se;
3374 unsigned wave_size = 64;
3375 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3376 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3377 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3378 */
3379 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3380 unsigned alignment = 256 * num_se;
3381 /* The maximum size is 63.999 MB per SE. */
3382 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3383
3384 /* Calculate the minimum size. */
3385 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3386 wave_size, alignment);
3387
3388 /* These are recommended sizes, not minimum sizes. */
3389 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3390 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3391 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3392 gs->max_gsvs_emit_size;
3393
3394 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3395 esgs_ring_size = align(esgs_ring_size, alignment);
3396 gsvs_ring_size = align(gsvs_ring_size, alignment);
3397
3398 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3399 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3400
3401 /* Some rings don't have to be allocated if shaders don't use them.
3402 * (e.g. no varyings between ES and GS or GS and VS)
3403 *
3404 * GFX9 doesn't have the ESGS ring.
3405 */
3406 bool update_esgs = sctx->chip_class <= GFX8 &&
3407 esgs_ring_size &&
3408 (!sctx->esgs_ring ||
3409 sctx->esgs_ring->width0 < esgs_ring_size);
3410 bool update_gsvs = gsvs_ring_size &&
3411 (!sctx->gsvs_ring ||
3412 sctx->gsvs_ring->width0 < gsvs_ring_size);
3413
3414 if (!update_esgs && !update_gsvs)
3415 return true;
3416
3417 if (update_esgs) {
3418 pipe_resource_reference(&sctx->esgs_ring, NULL);
3419 sctx->esgs_ring =
3420 pipe_aligned_buffer_create(sctx->b.screen,
3421 SI_RESOURCE_FLAG_UNMAPPABLE,
3422 PIPE_USAGE_DEFAULT,
3423 esgs_ring_size, alignment);
3424 if (!sctx->esgs_ring)
3425 return false;
3426 }
3427
3428 if (update_gsvs) {
3429 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3430 sctx->gsvs_ring =
3431 pipe_aligned_buffer_create(sctx->b.screen,
3432 SI_RESOURCE_FLAG_UNMAPPABLE,
3433 PIPE_USAGE_DEFAULT,
3434 gsvs_ring_size, alignment);
3435 if (!sctx->gsvs_ring)
3436 return false;
3437 }
3438
3439 /* Create the "init_config_gs_rings" state. */
3440 pm4 = CALLOC_STRUCT(si_pm4_state);
3441 if (!pm4)
3442 return false;
3443
3444 if (sctx->chip_class >= GFX7) {
3445 if (sctx->esgs_ring) {
3446 assert(sctx->chip_class <= GFX8);
3447 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3448 sctx->esgs_ring->width0 / 256);
3449 }
3450 if (sctx->gsvs_ring)
3451 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3452 sctx->gsvs_ring->width0 / 256);
3453 } else {
3454 if (sctx->esgs_ring)
3455 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3456 sctx->esgs_ring->width0 / 256);
3457 if (sctx->gsvs_ring)
3458 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3459 sctx->gsvs_ring->width0 / 256);
3460 }
3461
3462 /* Set the state. */
3463 if (sctx->init_config_gs_rings)
3464 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3465 sctx->init_config_gs_rings = pm4;
3466
3467 if (!sctx->init_config_has_vgt_flush) {
3468 si_init_config_add_vgt_flush(sctx);
3469 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3470 }
3471
3472 /* Flush the context to re-emit both init_config states. */
3473 sctx->initial_gfx_cs_size = 0; /* force flush */
3474 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3475
3476 /* Set ring bindings. */
3477 if (sctx->esgs_ring) {
3478 assert(sctx->chip_class <= GFX8);
3479 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3480 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3481 true, true, 4, 64, 0);
3482 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3483 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3484 false, false, 0, 0, 0);
3485 }
3486 if (sctx->gsvs_ring) {
3487 si_set_ring_buffer(sctx, SI_RING_GSVS,
3488 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3489 false, false, 0, 0, 0);
3490 }
3491
3492 return true;
3493 }
3494
3495 static void si_shader_lock(struct si_shader *shader)
3496 {
3497 mtx_lock(&shader->selector->mutex);
3498 if (shader->previous_stage_sel) {
3499 assert(shader->previous_stage_sel != shader->selector);
3500 mtx_lock(&shader->previous_stage_sel->mutex);
3501 }
3502 }
3503
3504 static void si_shader_unlock(struct si_shader *shader)
3505 {
3506 if (shader->previous_stage_sel)
3507 mtx_unlock(&shader->previous_stage_sel->mutex);
3508 mtx_unlock(&shader->selector->mutex);
3509 }
3510
3511 /**
3512 * @returns 1 if \p sel has been updated to use a new scratch buffer
3513 * 0 if not
3514 * < 0 if there was a failure
3515 */
3516 static int si_update_scratch_buffer(struct si_context *sctx,
3517 struct si_shader *shader)
3518 {
3519 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3520
3521 if (!shader)
3522 return 0;
3523
3524 /* This shader doesn't need a scratch buffer */
3525 if (shader->config.scratch_bytes_per_wave == 0)
3526 return 0;
3527
3528 /* Prevent race conditions when updating:
3529 * - si_shader::scratch_bo
3530 * - si_shader::binary::code
3531 * - si_shader::previous_stage::binary::code.
3532 */
3533 si_shader_lock(shader);
3534
3535 /* This shader is already configured to use the current
3536 * scratch buffer. */
3537 if (shader->scratch_bo == sctx->scratch_buffer) {
3538 si_shader_unlock(shader);
3539 return 0;
3540 }
3541
3542 assert(sctx->scratch_buffer);
3543
3544 /* Replace the shader bo with a new bo that has the relocs applied. */
3545 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3546 si_shader_unlock(shader);
3547 return -1;
3548 }
3549
3550 /* Update the shader state to use the new shader bo. */
3551 si_shader_init_pm4_state(sctx->screen, shader);
3552
3553 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3554
3555 si_shader_unlock(shader);
3556 return 1;
3557 }
3558
3559 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
3560 {
3561 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
3562 }
3563
3564 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3565 {
3566 return shader ? shader->config.scratch_bytes_per_wave : 0;
3567 }
3568
3569 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3570 {
3571 if (!sctx->tes_shader.cso)
3572 return NULL; /* tessellation disabled */
3573
3574 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3575 sctx->fixed_func_tcs_shader.current;
3576 }
3577
3578 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
3579 {
3580 unsigned bytes = 0;
3581
3582 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3583 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3584 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3585 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3586
3587 if (sctx->tes_shader.cso) {
3588 struct si_shader *tcs = si_get_tcs_current(sctx);
3589
3590 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
3591 }
3592 return bytes;
3593 }
3594
3595 static bool si_update_scratch_relocs(struct si_context *sctx)
3596 {
3597 struct si_shader *tcs = si_get_tcs_current(sctx);
3598 int r;
3599
3600 /* Update the shaders, so that they are using the latest scratch.
3601 * The scratch buffer may have been changed since these shaders were
3602 * last used, so we still need to try to update them, even if they
3603 * require scratch buffers smaller than the current size.
3604 */
3605 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3606 if (r < 0)
3607 return false;
3608 if (r == 1)
3609 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3610
3611 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3612 if (r < 0)
3613 return false;
3614 if (r == 1)
3615 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3616
3617 r = si_update_scratch_buffer(sctx, tcs);
3618 if (r < 0)
3619 return false;
3620 if (r == 1)
3621 si_pm4_bind_state(sctx, hs, tcs->pm4);
3622
3623 /* VS can be bound as LS, ES, or VS. */
3624 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3625 if (r < 0)
3626 return false;
3627 if (r == 1) {
3628 if (sctx->vs_shader.current->key.as_ls)
3629 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3630 else if (sctx->vs_shader.current->key.as_es)
3631 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3632 else if (sctx->vs_shader.current->key.as_ngg)
3633 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3634 else
3635 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3636 }
3637
3638 /* TES can be bound as ES or VS. */
3639 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3640 if (r < 0)
3641 return false;
3642 if (r == 1) {
3643 if (sctx->tes_shader.current->key.as_es)
3644 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3645 else if (sctx->tes_shader.current->key.as_ngg)
3646 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3647 else
3648 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3649 }
3650
3651 return true;
3652 }
3653
3654 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3655 {
3656 unsigned current_scratch_buffer_size =
3657 si_get_current_scratch_buffer_size(sctx);
3658 unsigned scratch_bytes_per_wave =
3659 si_get_max_scratch_bytes_per_wave(sctx);
3660 unsigned scratch_needed_size = scratch_bytes_per_wave *
3661 sctx->scratch_waves;
3662 unsigned spi_tmpring_size;
3663
3664 if (scratch_needed_size > 0) {
3665 if (scratch_needed_size > current_scratch_buffer_size) {
3666 /* Create a bigger scratch buffer */
3667 si_resource_reference(&sctx->scratch_buffer, NULL);
3668
3669 sctx->scratch_buffer =
3670 si_aligned_buffer_create(&sctx->screen->b,
3671 SI_RESOURCE_FLAG_UNMAPPABLE,
3672 PIPE_USAGE_DEFAULT,
3673 scratch_needed_size, 256);
3674 if (!sctx->scratch_buffer)
3675 return false;
3676
3677 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3678 si_context_add_resource_size(sctx,
3679 &sctx->scratch_buffer->b.b);
3680 }
3681
3682 if (!si_update_scratch_relocs(sctx))
3683 return false;
3684 }
3685
3686 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3687 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3688 "scratch size should already be aligned correctly.");
3689
3690 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3691 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3692 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3693 sctx->spi_tmpring_size = spi_tmpring_size;
3694 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3695 }
3696 return true;
3697 }
3698
3699 static void si_init_tess_factor_ring(struct si_context *sctx)
3700 {
3701 assert(!sctx->tess_rings);
3702
3703 /* The address must be aligned to 2^19, because the shader only
3704 * receives the high 13 bits.
3705 */
3706 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3707 SI_RESOURCE_FLAG_32BIT,
3708 PIPE_USAGE_DEFAULT,
3709 sctx->screen->tess_offchip_ring_size +
3710 sctx->screen->tess_factor_ring_size,
3711 1 << 19);
3712 if (!sctx->tess_rings)
3713 return;
3714
3715 si_init_config_add_vgt_flush(sctx);
3716
3717 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3718 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3719
3720 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3721 sctx->screen->tess_offchip_ring_size;
3722
3723 /* Append these registers to the init config state. */
3724 if (sctx->chip_class >= GFX7) {
3725 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3726 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3727 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3728 factor_va >> 8);
3729 if (sctx->chip_class >= GFX10)
3730 si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3731 S_030984_BASE_HI(factor_va >> 40));
3732 else if (sctx->chip_class == GFX9)
3733 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3734 S_030944_BASE_HI(factor_va >> 40));
3735 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3736 sctx->screen->vgt_hs_offchip_param);
3737 } else {
3738 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3739 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3740 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3741 factor_va >> 8);
3742 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3743 sctx->screen->vgt_hs_offchip_param);
3744 }
3745
3746 /* Flush the context to re-emit the init_config state.
3747 * This is done only once in a lifetime of a context.
3748 */
3749 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3750 sctx->initial_gfx_cs_size = 0; /* force flush */
3751 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3752 }
3753
3754 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3755 union si_vgt_stages_key key)
3756 {
3757 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3758 uint32_t stages = 0;
3759
3760 if (key.u.tess) {
3761 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3762 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3763
3764 if (key.u.gs)
3765 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3766 S_028B54_GS_EN(1);
3767 else if (key.u.ngg)
3768 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3769 else
3770 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3771 } else if (key.u.gs) {
3772 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3773 S_028B54_GS_EN(1);
3774 } else if (key.u.ngg) {
3775 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3776 }
3777
3778 if (key.u.ngg) {
3779 stages |= S_028B54_PRIMGEN_EN(1);
3780 if (key.u.streamout)
3781 stages |= S_028B54_NGG_WAVE_ID_EN(1);
3782 } else if (key.u.gs)
3783 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3784
3785 if (screen->info.chip_class >= GFX9)
3786 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3787
3788 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3789 return pm4;
3790 }
3791
3792 static void si_update_vgt_shader_config(struct si_context *sctx,
3793 union si_vgt_stages_key key)
3794 {
3795 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3796
3797 if (unlikely(!*pm4))
3798 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3799 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3800 }
3801
3802 bool si_update_shaders(struct si_context *sctx)
3803 {
3804 struct pipe_context *ctx = (struct pipe_context*)sctx;
3805 struct si_compiler_ctx_state compiler_state;
3806 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3807 struct si_shader *old_vs = si_get_vs_state(sctx);
3808 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3809 struct si_shader *old_ps = sctx->ps_shader.current;
3810 union si_vgt_stages_key key;
3811 unsigned old_spi_shader_col_format =
3812 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3813 int r;
3814
3815 compiler_state.compiler = &sctx->compiler;
3816 compiler_state.debug = sctx->debug;
3817 compiler_state.is_debug_context = sctx->is_debug;
3818
3819 key.index = 0;
3820
3821 if (sctx->tes_shader.cso)
3822 key.u.tess = 1;
3823 if (sctx->gs_shader.cso)
3824 key.u.gs = 1;
3825
3826 if (sctx->chip_class >= GFX10) {
3827 key.u.ngg = sctx->ngg;
3828
3829 if (sctx->gs_shader.cso)
3830 key.u.streamout = !!sctx->gs_shader.cso->so.num_outputs;
3831 else if (sctx->tes_shader.cso)
3832 key.u.streamout = !!sctx->tes_shader.cso->so.num_outputs;
3833 else
3834 key.u.streamout = !!sctx->vs_shader.cso->so.num_outputs;
3835 }
3836
3837 /* Update TCS and TES. */
3838 if (sctx->tes_shader.cso) {
3839 if (!sctx->tess_rings) {
3840 si_init_tess_factor_ring(sctx);
3841 if (!sctx->tess_rings)
3842 return false;
3843 }
3844
3845 if (sctx->tcs_shader.cso) {
3846 r = si_shader_select(ctx, &sctx->tcs_shader, key,
3847 &compiler_state);
3848 if (r)
3849 return false;
3850 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3851 } else {
3852 if (!sctx->fixed_func_tcs_shader.cso) {
3853 sctx->fixed_func_tcs_shader.cso =
3854 si_create_fixed_func_tcs(sctx);
3855 if (!sctx->fixed_func_tcs_shader.cso)
3856 return false;
3857 }
3858
3859 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3860 key, &compiler_state);
3861 if (r)
3862 return false;
3863 si_pm4_bind_state(sctx, hs,
3864 sctx->fixed_func_tcs_shader.current->pm4);
3865 }
3866
3867 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3868 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3869 if (r)
3870 return false;
3871
3872 if (sctx->gs_shader.cso) {
3873 /* TES as ES */
3874 assert(sctx->chip_class <= GFX8);
3875 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3876 } else if (key.u.ngg) {
3877 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3878 } else {
3879 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3880 }
3881 }
3882 } else {
3883 if (sctx->chip_class <= GFX8)
3884 si_pm4_bind_state(sctx, ls, NULL);
3885 si_pm4_bind_state(sctx, hs, NULL);
3886 }
3887
3888 /* Update GS. */
3889 if (sctx->gs_shader.cso) {
3890 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
3891 if (r)
3892 return false;
3893 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3894 if (!key.u.ngg) {
3895 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3896
3897 if (!si_update_gs_ring_buffers(sctx))
3898 return false;
3899 } else {
3900 si_pm4_bind_state(sctx, vs, NULL);
3901 }
3902 } else {
3903 if (!key.u.ngg) {
3904 si_pm4_bind_state(sctx, gs, NULL);
3905 if (sctx->chip_class <= GFX8)
3906 si_pm4_bind_state(sctx, es, NULL);
3907 }
3908 }
3909
3910 /* Update VS. */
3911 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
3912 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
3913 if (r)
3914 return false;
3915
3916 if (!key.u.tess && !key.u.gs) {
3917 if (key.u.ngg) {
3918 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3919 si_pm4_bind_state(sctx, vs, NULL);
3920 } else {
3921 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3922 }
3923 } else if (sctx->tes_shader.cso) {
3924 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3925 } else {
3926 assert(sctx->gs_shader.cso);
3927 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3928 }
3929 }
3930
3931 si_update_vgt_shader_config(sctx, key);
3932
3933 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3934 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3935
3936 if (sctx->ps_shader.cso) {
3937 unsigned db_shader_control;
3938
3939 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
3940 if (r)
3941 return false;
3942 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3943
3944 db_shader_control =
3945 sctx->ps_shader.cso->db_shader_control |
3946 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3947
3948 if (si_pm4_state_changed(sctx, ps) ||
3949 si_pm4_state_changed(sctx, vs) ||
3950 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
3951 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3952 sctx->flatshade != rs->flatshade) {
3953 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3954 sctx->flatshade = rs->flatshade;
3955 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3956 }
3957
3958 if (sctx->screen->rbplus_allowed &&
3959 si_pm4_state_changed(sctx, ps) &&
3960 (!old_ps ||
3961 old_spi_shader_col_format !=
3962 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3963 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3964
3965 if (sctx->ps_db_shader_control != db_shader_control) {
3966 sctx->ps_db_shader_control = db_shader_control;
3967 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3968 if (sctx->screen->dpbb_allowed)
3969 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3970 }
3971
3972 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3973 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3974 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3975
3976 if (sctx->chip_class == GFX6)
3977 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3978
3979 if (sctx->framebuffer.nr_samples <= 1)
3980 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3981 }
3982 }
3983
3984 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3985 si_pm4_state_enabled_and_changed(sctx, hs) ||
3986 si_pm4_state_enabled_and_changed(sctx, es) ||
3987 si_pm4_state_enabled_and_changed(sctx, gs) ||
3988 si_pm4_state_enabled_and_changed(sctx, vs) ||
3989 si_pm4_state_enabled_and_changed(sctx, ps)) {
3990 if (!si_update_spi_tmpring_size(sctx))
3991 return false;
3992 }
3993
3994 if (sctx->chip_class >= GFX7) {
3995 if (si_pm4_state_enabled_and_changed(sctx, ls))
3996 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3997 else if (!sctx->queued.named.ls)
3998 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3999
4000 if (si_pm4_state_enabled_and_changed(sctx, hs))
4001 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
4002 else if (!sctx->queued.named.hs)
4003 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
4004
4005 if (si_pm4_state_enabled_and_changed(sctx, es))
4006 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
4007 else if (!sctx->queued.named.es)
4008 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
4009
4010 if (si_pm4_state_enabled_and_changed(sctx, gs))
4011 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
4012 else if (!sctx->queued.named.gs)
4013 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
4014
4015 if (si_pm4_state_enabled_and_changed(sctx, vs))
4016 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
4017 else if (!sctx->queued.named.vs)
4018 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
4019
4020 if (si_pm4_state_enabled_and_changed(sctx, ps))
4021 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
4022 else if (!sctx->queued.named.ps)
4023 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
4024 }
4025
4026 sctx->do_update_shaders = false;
4027 return true;
4028 }
4029
4030 static void si_emit_scratch_state(struct si_context *sctx)
4031 {
4032 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4033
4034 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
4035 sctx->spi_tmpring_size);
4036
4037 if (sctx->scratch_buffer) {
4038 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
4039 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
4040 RADEON_PRIO_SCRATCH_BUFFER);
4041 }
4042 }
4043
4044 void si_init_shader_functions(struct si_context *sctx)
4045 {
4046 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
4047 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
4048
4049 sctx->b.create_vs_state = si_create_shader_selector;
4050 sctx->b.create_tcs_state = si_create_shader_selector;
4051 sctx->b.create_tes_state = si_create_shader_selector;
4052 sctx->b.create_gs_state = si_create_shader_selector;
4053 sctx->b.create_fs_state = si_create_shader_selector;
4054
4055 sctx->b.bind_vs_state = si_bind_vs_shader;
4056 sctx->b.bind_tcs_state = si_bind_tcs_shader;
4057 sctx->b.bind_tes_state = si_bind_tes_shader;
4058 sctx->b.bind_gs_state = si_bind_gs_shader;
4059 sctx->b.bind_fs_state = si_bind_ps_shader;
4060
4061 sctx->b.delete_vs_state = si_delete_shader_selector;
4062 sctx->b.delete_tcs_state = si_delete_shader_selector;
4063 sctx->b.delete_tes_state = si_delete_shader_selector;
4064 sctx->b.delete_gs_state = si_delete_shader_selector;
4065 sctx->b.delete_fs_state = si_delete_shader_selector;
4066 }