projects / mesa.git / blob
? search:


6a6fce6939ccc72b9d97c7426d55915845321937
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "sid.h"
30 #include "gfx9d.h"
31 #include "radeon/r600_cs.h"
32
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/hash_table.h"
36 #include "util/crc32.h"
37 #include "util/u_memory.h"
38 #include "util/u_prim.h"
39
40 #include "util/disk_cache.h"
41 #include "util/mesa-sha1.h"
42 #include "ac_exp_param.h"
43
44 /* SHADER_CACHE */
45
46 /**
47 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
48 * integer.
49 */
50 static void *si_get_tgsi_binary(struct si_shader_selector *sel)
51 {
52 unsigned tgsi_size = tgsi_num_tokens(sel->tokens) *
53 sizeof(struct tgsi_token);
54 unsigned size = 4 + tgsi_size + sizeof(sel->so);
55 char *result = (char*)MALLOC(size);
56
57 if (!result)
58 return NULL;
59
60 *((uint32_t*)result) = size;
61 memcpy(result + 4, sel->tokens, tgsi_size);
62 memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so));
63 return result;
64 }
65
66 /** Copy "data" to "ptr" and return the next dword following copied data. */
67 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
68 {
69 /* data may be NULL if size == 0 */
70 if (size)
71 memcpy(ptr, data, size);
72 ptr += DIV_ROUND_UP(size, 4);
73 return ptr;
74 }
75
76 /** Read data from "ptr". Return the next dword following the data. */
77 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
78 {
79 memcpy(data, ptr, size);
80 ptr += DIV_ROUND_UP(size, 4);
81 return ptr;
82 }
83
84 /**
85 * Write the size as uint followed by the data. Return the next dword
86 * following the copied data.
87 */
88 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
89 {
90 *ptr++ = size;
91 return write_data(ptr, data, size);
92 }
93
94 /**
95 * Read the size as uint followed by the data. Return both via parameters.
96 * Return the next dword following the data.
97 */
98 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
99 {
100 *size = *ptr++;
101 assert(*data == NULL);
102 if (!*size)
103 return ptr;
104 *data = malloc(*size);
105 return read_data(ptr, *data, *size);
106 }
107
108 /**
109 * Return the shader binary in a buffer. The first 4 bytes contain its size
110 * as integer.
111 */
112 static void *si_get_shader_binary(struct si_shader *shader)
113 {
114 /* There is always a size of data followed by the data itself. */
115 unsigned relocs_size = shader->binary.reloc_count *
116 sizeof(shader->binary.relocs[0]);
117 unsigned disasm_size = shader->binary.disasm_string ?
118 strlen(shader->binary.disasm_string) + 1 : 0;
119 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
120 strlen(shader->binary.llvm_ir_string) + 1 : 0;
121 unsigned size =
122 4 + /* total size */
123 4 + /* CRC32 of the data below */
124 align(sizeof(shader->config), 4) +
125 align(sizeof(shader->info), 4) +
126 4 + align(shader->binary.code_size, 4) +
127 4 + align(shader->binary.rodata_size, 4) +
128 4 + align(relocs_size, 4) +
129 4 + align(disasm_size, 4) +
130 4 + align(llvm_ir_size, 4);
131 void *buffer = CALLOC(1, size);
132 uint32_t *ptr = (uint32_t*)buffer;
133
134 if (!buffer)
135 return NULL;
136
137 *ptr++ = size;
138 ptr++; /* CRC32 is calculated at the end. */
139
140 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
141 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
142 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
143 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
144 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
145 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
146 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
147 assert((char *)ptr - (char *)buffer == size);
148
149 /* Compute CRC32. */
150 ptr = (uint32_t*)buffer;
151 ptr++;
152 *ptr = util_hash_crc32(ptr + 1, size - 8);
153
154 return buffer;
155 }
156
157 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
158 {
159 uint32_t *ptr = (uint32_t*)binary;
160 uint32_t size = *ptr++;
161 uint32_t crc32 = *ptr++;
162 unsigned chunk_size;
163
164 if (util_hash_crc32(ptr, size - 8) != crc32) {
165 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
166 return false;
167 }
168
169 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
170 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
171 ptr = read_chunk(ptr, (void**)&shader->binary.code,
172 &shader->binary.code_size);
173 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
174 &shader->binary.rodata_size);
175 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
176 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
177 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
178 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
179
180 return true;
181 }
182
183 /**
184 * Insert a shader into the cache. It's assumed the shader is not in the cache.
185 * Use si_shader_cache_load_shader before calling this.
186 *
187 * Returns false on failure, in which case the tgsi_binary should be freed.
188 */
189 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
190 void *tgsi_binary,
191 struct si_shader *shader,
192 bool insert_into_disk_cache)
193 {
194 void *hw_binary;
195 struct hash_entry *entry;
196 uint8_t key[CACHE_KEY_SIZE];
197
198 entry = _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
199 if (entry)
200 return false; /* already added */
201
202 hw_binary = si_get_shader_binary(shader);
203 if (!hw_binary)
204 return false;
205
206 if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
207 hw_binary) == NULL) {
208 FREE(hw_binary);
209 return false;
210 }
211
212 if (sscreen->b.disk_shader_cache && insert_into_disk_cache) {
213 disk_cache_compute_key(sscreen->b.disk_shader_cache, tgsi_binary,
214 *((uint32_t *)tgsi_binary), key);
215 disk_cache_put(sscreen->b.disk_shader_cache, key, hw_binary,
216 *((uint32_t *) hw_binary));
217 }
218
219 return true;
220 }
221
222 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
223 void *tgsi_binary,
224 struct si_shader *shader)
225 {
226 struct hash_entry *entry =
227 _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
228 if (!entry) {
229 if (sscreen->b.disk_shader_cache) {
230 unsigned char sha1[CACHE_KEY_SIZE];
231 size_t tg_size = *((uint32_t *) tgsi_binary);
232
233 disk_cache_compute_key(sscreen->b.disk_shader_cache,
234 tgsi_binary, tg_size, sha1);
235
236 size_t binary_size;
237 uint8_t *buffer =
238 disk_cache_get(sscreen->b.disk_shader_cache,
239 sha1, &binary_size);
240 if (!buffer)
241 return false;
242
243 if (binary_size < sizeof(uint32_t) ||
244 *((uint32_t*)buffer) != binary_size) {
245 /* Something has gone wrong discard the item
246 * from the cache and rebuild/link from
247 * source.
248 */
249 assert(!"Invalid radeonsi shader disk cache "
250 "item!");
251
252 disk_cache_remove(sscreen->b.disk_shader_cache,
253 sha1);
254 free(buffer);
255
256 return false;
257 }
258
259 if (!si_load_shader_binary(shader, buffer)) {
260 free(buffer);
261 return false;
262 }
263 free(buffer);
264
265 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary,
266 shader, false))
267 FREE(tgsi_binary);
268 } else {
269 return false;
270 }
271 } else {
272 if (si_load_shader_binary(shader, entry->data))
273 FREE(tgsi_binary);
274 else
275 return false;
276 }
277 p_atomic_inc(&sscreen->b.num_shader_cache_hits);
278 return true;
279 }
280
281 static uint32_t si_shader_cache_key_hash(const void *key)
282 {
283 /* The first dword is the key size. */
284 return util_hash_crc32(key, *(uint32_t*)key);
285 }
286
287 static bool si_shader_cache_key_equals(const void *a, const void *b)
288 {
289 uint32_t *keya = (uint32_t*)a;
290 uint32_t *keyb = (uint32_t*)b;
291
292 /* The first dword is the key size. */
293 if (*keya != *keyb)
294 return false;
295
296 return memcmp(keya, keyb, *keya) == 0;
297 }
298
299 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
300 {
301 FREE((void*)entry->key);
302 FREE(entry->data);
303 }
304
305 bool si_init_shader_cache(struct si_screen *sscreen)
306 {
307 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
308 sscreen->shader_cache =
309 _mesa_hash_table_create(NULL,
310 si_shader_cache_key_hash,
311 si_shader_cache_key_equals);
312
313 return sscreen->shader_cache != NULL;
314 }
315
316 void si_destroy_shader_cache(struct si_screen *sscreen)
317 {
318 if (sscreen->shader_cache)
319 _mesa_hash_table_destroy(sscreen->shader_cache,
320 si_destroy_shader_cache_entry);
321 mtx_destroy(&sscreen->shader_cache_mutex);
322 }
323
324 /* SHADER STATES */
325
326 static void si_set_tesseval_regs(struct si_screen *sscreen,
327 struct si_shader_selector *tes,
328 struct si_pm4_state *pm4)
329 {
330 struct tgsi_shader_info *info = &tes->info;
331 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
332 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
333 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
334 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
335 unsigned type, partitioning, topology, distribution_mode;
336
337 switch (tes_prim_mode) {
338 case PIPE_PRIM_LINES:
339 type = V_028B6C_TESS_ISOLINE;
340 break;
341 case PIPE_PRIM_TRIANGLES:
342 type = V_028B6C_TESS_TRIANGLE;
343 break;
344 case PIPE_PRIM_QUADS:
345 type = V_028B6C_TESS_QUAD;
346 break;
347 default:
348 assert(0);
349 return;
350 }
351
352 switch (tes_spacing) {
353 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
354 partitioning = V_028B6C_PART_FRAC_ODD;
355 break;
356 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
357 partitioning = V_028B6C_PART_FRAC_EVEN;
358 break;
359 case PIPE_TESS_SPACING_EQUAL:
360 partitioning = V_028B6C_PART_INTEGER;
361 break;
362 default:
363 assert(0);
364 return;
365 }
366
367 if (tes_point_mode)
368 topology = V_028B6C_OUTPUT_POINT;
369 else if (tes_prim_mode == PIPE_PRIM_LINES)
370 topology = V_028B6C_OUTPUT_LINE;
371 else if (tes_vertex_order_cw)
372 /* for some reason, this must be the other way around */
373 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
374 else
375 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
376
377 if (sscreen->has_distributed_tess) {
378 if (sscreen->b.family == CHIP_FIJI ||
379 sscreen->b.family >= CHIP_POLARIS10)
380 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
381 else
382 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
383 } else
384 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
385
386 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
387 S_028B6C_TYPE(type) |
388 S_028B6C_PARTITIONING(partitioning) |
389 S_028B6C_TOPOLOGY(topology) |
390 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
391 }
392
393 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
394 * whether the "fractional odd" tessellation spacing is used.
395 *
396 * Possible VGT configurations and which state should set the register:
397 *
398 * Reg set in | VGT shader configuration | Value
399 * ------------------------------------------------------
400 * VS as VS | VS | 30
401 * VS as ES | ES -> GS -> VS | 30
402 * TES as VS | LS -> HS -> VS | 14 or 30
403 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
404 *
405 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
406 */
407 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
408 struct si_shader_selector *sel,
409 struct si_shader *shader,
410 struct si_pm4_state *pm4)
411 {
412 unsigned type = sel->type;
413
414 if (sscreen->b.family < CHIP_POLARIS10)
415 return;
416
417 /* VS as VS, or VS as ES: */
418 if ((type == PIPE_SHADER_VERTEX &&
419 (!shader ||
420 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
421 /* TES as VS, or TES as ES: */
422 type == PIPE_SHADER_TESS_EVAL) {
423 unsigned vtx_reuse_depth = 30;
424
425 if (type == PIPE_SHADER_TESS_EVAL &&
426 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
427 PIPE_TESS_SPACING_FRACTIONAL_ODD)
428 vtx_reuse_depth = 14;
429
430 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
431 vtx_reuse_depth);
432 }
433 }
434
435 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
436 {
437 if (shader->pm4)
438 si_pm4_clear_state(shader->pm4);
439 else
440 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
441
442 return shader->pm4;
443 }
444
445 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
446 {
447 struct si_pm4_state *pm4;
448 unsigned vgpr_comp_cnt;
449 uint64_t va;
450
451 assert(sscreen->b.chip_class <= VI);
452
453 pm4 = si_get_shader_pm4_state(shader);
454 if (!pm4)
455 return;
456
457 va = shader->bo->gpu_address;
458 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
459
460 /* We need at least 2 components for LS.
461 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
462 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 1;
463
464 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
465 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
466
467 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
468 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
469 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
470 S_00B528_DX10_CLAMP(1) |
471 S_00B528_FLOAT_MODE(shader->config.float_mode);
472 shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_VS_NUM_USER_SGPR) |
473 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
474 }
475
476 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
477 {
478 struct si_pm4_state *pm4;
479 uint64_t va;
480 unsigned ls_vgpr_comp_cnt = 0;
481
482 pm4 = si_get_shader_pm4_state(shader);
483 if (!pm4)
484 return;
485
486 va = shader->bo->gpu_address;
487 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
488
489 if (sscreen->b.chip_class >= GFX9) {
490 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
491 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, va >> 40);
492
493 /* We need at least 2 components for LS.
494 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
495 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 1;
496
497 if (shader->config.scratch_bytes_per_wave) {
498 fprintf(stderr, "HS: scratch buffer unsupported");
499 abort();
500 }
501
502 shader->config.rsrc2 =
503 S_00B42C_USER_SGPR(GFX9_TCS_NUM_USER_SGPR) |
504 S_00B42C_USER_SGPR_MSB(GFX9_TCS_NUM_USER_SGPR >> 5) |
505 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
506 } else {
507 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
508 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
509
510 shader->config.rsrc2 =
511 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
512 S_00B42C_OC_LDS_EN(1) |
513 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
514 }
515
516 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
517 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
518 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
519 S_00B428_DX10_CLAMP(1) |
520 S_00B428_FLOAT_MODE(shader->config.float_mode) |
521 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
522
523 if (sscreen->b.chip_class <= VI) {
524 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
525 shader->config.rsrc2);
526 }
527 }
528
529 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
530 {
531 struct si_pm4_state *pm4;
532 unsigned num_user_sgprs;
533 unsigned vgpr_comp_cnt;
534 uint64_t va;
535 unsigned oc_lds_en;
536
537 assert(sscreen->b.chip_class <= VI);
538
539 pm4 = si_get_shader_pm4_state(shader);
540 if (!pm4)
541 return;
542
543 va = shader->bo->gpu_address;
544 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
545
546 if (shader->selector->type == PIPE_SHADER_VERTEX) {
547 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
548 num_user_sgprs = SI_VS_NUM_USER_SGPR;
549 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
550 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
551 num_user_sgprs = SI_TES_NUM_USER_SGPR;
552 } else
553 unreachable("invalid shader selector type");
554
555 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
556
557 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
558 shader->selector->esgs_itemsize / 4);
559 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
560 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
561 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
562 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
563 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
564 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
565 S_00B328_DX10_CLAMP(1) |
566 S_00B328_FLOAT_MODE(shader->config.float_mode));
567 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
568 S_00B32C_USER_SGPR(num_user_sgprs) |
569 S_00B32C_OC_LDS_EN(oc_lds_en) |
570 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
571
572 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
573 si_set_tesseval_regs(sscreen, shader->selector, pm4);
574
575 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
576 }
577
578 /**
579 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
580 * geometry shader.
581 */
582 static uint32_t si_vgt_gs_mode(struct si_shader_selector *sel)
583 {
584 enum chip_class chip_class = sel->screen->b.chip_class;
585 unsigned gs_max_vert_out = sel->gs_max_out_vertices;
586 unsigned cut_mode;
587
588 if (gs_max_vert_out <= 128) {
589 cut_mode = V_028A40_GS_CUT_128;
590 } else if (gs_max_vert_out <= 256) {
591 cut_mode = V_028A40_GS_CUT_256;
592 } else if (gs_max_vert_out <= 512) {
593 cut_mode = V_028A40_GS_CUT_512;
594 } else {
595 assert(gs_max_vert_out <= 1024);
596 cut_mode = V_028A40_GS_CUT_1024;
597 }
598
599 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
600 S_028A40_CUT_MODE(cut_mode)|
601 S_028A40_ES_WRITE_OPTIMIZE(chip_class <= VI) |
602 S_028A40_GS_WRITE_OPTIMIZE(1) |
603 S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0);
604 }
605
606 struct gfx9_gs_info {
607 unsigned es_verts_per_subgroup;
608 unsigned gs_prims_per_subgroup;
609 unsigned gs_inst_prims_in_subgroup;
610 unsigned max_prims_per_subgroup;
611 unsigned lds_size;
612 };
613
614 static void gfx9_get_gs_info(struct si_shader_selector *es,
615 struct si_shader_selector *gs,
616 struct gfx9_gs_info *out)
617 {
618 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
619 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
620 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
621 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
622
623 /* All these are in dwords: */
624 /* We can't allow using the whole LDS, because GS waves compete with
625 * other shader stages for LDS space. */
626 const unsigned max_lds_size = 8 * 1024;
627 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
628 unsigned esgs_lds_size;
629
630 /* All these are per subgroup: */
631 const unsigned max_out_prims = 32 * 1024;
632 const unsigned max_es_verts = 255;
633 const unsigned ideal_gs_prims = 64;
634 unsigned max_gs_prims, gs_prims;
635 unsigned min_es_verts, es_verts, worst_case_es_verts;
636
637 assert(gs_num_invocations <= 32); /* GL maximum */
638
639 if (uses_adjacency || gs_num_invocations > 1)
640 max_gs_prims = 127 / gs_num_invocations;
641 else
642 max_gs_prims = 255;
643
644 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
645 * Make sure we don't go over the maximum value.
646 */
647 max_gs_prims = MIN2(max_gs_prims,
648 max_out_prims /
649 (gs->gs_max_out_vertices * gs_num_invocations));
650 assert(max_gs_prims > 0);
651
652 /* If the primitive has adjacency, halve the number of vertices
653 * that will be reused in multiple primitives.
654 */
655 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
656
657 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
658 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
659
660 /* Compute ESGS LDS size based on the worst case number of ES vertices
661 * needed to create the target number of GS prims per subgroup.
662 */
663 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
664
665 /* If total LDS usage is too big, refactor partitions based on ratio
666 * of ESGS item sizes.
667 */
668 if (esgs_lds_size > max_lds_size) {
669 /* Our target GS Prims Per Subgroup was too large. Calculate
670 * the maximum number of GS Prims Per Subgroup that will fit
671 * into LDS, capped by the maximum that the hardware can support.
672 */
673 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
674 max_gs_prims);
675 assert(gs_prims > 0);
676 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
677 max_es_verts);
678
679 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
680 assert(esgs_lds_size <= max_lds_size);
681 }
682
683 /* Now calculate remaining ESGS information. */
684 if (esgs_lds_size)
685 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
686 else
687 es_verts = max_es_verts;
688
689 /* Vertices for adjacency primitives are not always reused, so restore
690 * it for ES_VERTS_PER_SUBGRP.
691 */
692 min_es_verts = gs->gs_input_verts_per_prim;
693
694 /* For normal primitives, the VGT only checks if they are past the ES
695 * verts per subgroup after allocating a full GS primitive and if they
696 * are, kick off a new subgroup. But if those additional ES verts are
697 * unique (e.g. not reused) we need to make sure there is enough LDS
698 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
699 */
700 es_verts -= min_es_verts - 1;
701
702 out->es_verts_per_subgroup = es_verts;
703 out->gs_prims_per_subgroup = gs_prims;
704 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
705 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
706 gs->gs_max_out_vertices;
707 out->lds_size = align(esgs_lds_size, 128) / 128;
708
709 assert(out->max_prims_per_subgroup <= max_out_prims);
710 }
711
712 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
713 {
714 struct si_shader_selector *sel = shader->selector;
715 const ubyte *num_components = sel->info.num_stream_output_components;
716 unsigned gs_num_invocations = sel->gs_num_invocations;
717 struct si_pm4_state *pm4;
718 uint64_t va;
719 unsigned max_stream = sel->max_gs_stream;
720 unsigned offset;
721
722 pm4 = si_get_shader_pm4_state(shader);
723 if (!pm4)
724 return;
725
726 offset = num_components[0] * sel->gs_max_out_vertices;
727 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, offset);
728 if (max_stream >= 1)
729 offset += num_components[1] * sel->gs_max_out_vertices;
730 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, offset);
731 if (max_stream >= 2)
732 offset += num_components[2] * sel->gs_max_out_vertices;
733 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, offset);
734 if (max_stream >= 3)
735 offset += num_components[3] * sel->gs_max_out_vertices;
736 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
737
738 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
739 assert(offset < (1 << 15));
740
741 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, sel->gs_max_out_vertices);
742
743 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, num_components[0]);
744 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? num_components[1] : 0);
745 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? num_components[2] : 0);
746 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? num_components[3] : 0);
747
748 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
749 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
750 S_028B90_ENABLE(gs_num_invocations > 0));
751
752 va = shader->bo->gpu_address;
753 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
754
755 if (sscreen->b.chip_class >= GFX9) {
756 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
757 unsigned es_type = shader->key.part.gs.es->type;
758 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
759 struct gfx9_gs_info gs_info;
760
761 if (es_type == PIPE_SHADER_VERTEX)
762 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
763 else if (es_type == PIPE_SHADER_TESS_EVAL)
764 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
765 else
766 unreachable("invalid shader selector type");
767
768 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
769 * VGPR[0:4] are always loaded.
770 */
771 if (sel->info.uses_invocationid)
772 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
773 else if (sel->info.uses_primid)
774 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
775 else if (input_prim >= PIPE_PRIM_TRIANGLES)
776 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
777 else
778 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
779
780 gfx9_get_gs_info(shader->key.part.gs.es, sel, &gs_info);
781
782 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
783 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, va >> 40);
784
785 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
786 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
787 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
788 S_00B228_DX10_CLAMP(1) |
789 S_00B228_FLOAT_MODE(shader->config.float_mode) |
790 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
791 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
792 S_00B22C_USER_SGPR(GFX9_GS_NUM_USER_SGPR) |
793 S_00B22C_USER_SGPR_MSB(GFX9_GS_NUM_USER_SGPR >> 5) |
794 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
795 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
796 S_00B22C_LDS_SIZE(gs_info.lds_size) |
797 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
798
799 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
800 S_028A44_ES_VERTS_PER_SUBGRP(gs_info.es_verts_per_subgroup) |
801 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info.gs_prims_per_subgroup) |
802 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info.gs_inst_prims_in_subgroup));
803 si_pm4_set_reg(pm4, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
804 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info.max_prims_per_subgroup));
805 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
806 shader->key.part.gs.es->esgs_itemsize / 4);
807
808 if (es_type == PIPE_SHADER_TESS_EVAL)
809 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
810
811 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
812 NULL, pm4);
813
814 if (shader->config.scratch_bytes_per_wave) {
815 fprintf(stderr, "GS: scratch buffer unsupported");
816 abort();
817 }
818 } else {
819 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
820 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
821
822 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
823 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
824 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
825 S_00B228_DX10_CLAMP(1) |
826 S_00B228_FLOAT_MODE(shader->config.float_mode));
827 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
828 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
829 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
830 }
831 }
832
833 /**
834 * Compute the state for \p shader, which will run as a vertex shader on the
835 * hardware.
836 *
837 * If \p gs is non-NULL, it points to the geometry shader for which this shader
838 * is the copy shader.
839 */
840 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
841 struct si_shader_selector *gs)
842 {
843 struct si_pm4_state *pm4;
844 unsigned num_user_sgprs;
845 unsigned nparams, vgpr_comp_cnt;
846 uint64_t va;
847 unsigned oc_lds_en;
848 unsigned window_space =
849 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
850 bool enable_prim_id = si_vs_exports_prim_id(shader);
851
852 pm4 = si_get_shader_pm4_state(shader);
853 if (!pm4)
854 return;
855
856 /* We always write VGT_GS_MODE in the VS state, because every switch
857 * between different shader pipelines involving a different GS or no
858 * GS at all involves a switch of the VS (different GS use different
859 * copy shaders). On the other hand, when the API switches from a GS to
860 * no GS and then back to the same GS used originally, the GS state is
861 * not sent again.
862 */
863 if (!gs) {
864 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
865 S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
866 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
867 } else {
868 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
869 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
870 }
871
872 va = shader->bo->gpu_address;
873 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
874
875 if (gs) {
876 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
877 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
878 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
879 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
880 num_user_sgprs = SI_VS_NUM_USER_SGPR;
881 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
882 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
883 num_user_sgprs = SI_TES_NUM_USER_SGPR;
884 } else
885 unreachable("invalid shader selector type");
886
887 /* VS is required to export at least one param. */
888 nparams = MAX2(shader->info.nr_param_exports, 1);
889 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
890 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
891
892 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
893 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
894 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
895 V_02870C_SPI_SHADER_4COMP :
896 V_02870C_SPI_SHADER_NONE) |
897 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
898 V_02870C_SPI_SHADER_4COMP :
899 V_02870C_SPI_SHADER_NONE) |
900 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
901 V_02870C_SPI_SHADER_4COMP :
902 V_02870C_SPI_SHADER_NONE));
903
904 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
905
906 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
907 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
908 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
909 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
910 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
911 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
912 S_00B128_DX10_CLAMP(1) |
913 S_00B128_FLOAT_MODE(shader->config.float_mode));
914 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
915 S_00B12C_USER_SGPR(num_user_sgprs) |
916 S_00B12C_OC_LDS_EN(oc_lds_en) |
917 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
918 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
919 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
920 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
921 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
922 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
923 if (window_space)
924 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
925 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
926 else
927 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
928 S_028818_VTX_W0_FMT(1) |
929 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
930 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
931 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
932
933 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
934 si_set_tesseval_regs(sscreen, shader->selector, pm4);
935
936 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
937 }
938
939 static unsigned si_get_ps_num_interp(struct si_shader *ps)
940 {
941 struct tgsi_shader_info *info = &ps->selector->info;
942 unsigned num_colors = !!(info->colors_read & 0x0f) +
943 !!(info->colors_read & 0xf0);
944 unsigned num_interp = ps->selector->info.num_inputs +
945 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
946
947 assert(num_interp <= 32);
948 return MIN2(num_interp, 32);
949 }
950
951 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
952 {
953 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
954 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
955
956 /* If the i-th target format is set, all previous target formats must
957 * be non-zero to avoid hangs.
958 */
959 for (i = 0; i < num_targets; i++)
960 if (!(value & (0xf << (i * 4))))
961 value |= V_028714_SPI_SHADER_32_R << (i * 4);
962
963 return value;
964 }
965
966 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
967 {
968 unsigned i, cb_shader_mask = 0;
969
970 for (i = 0; i < 8; i++) {
971 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
972 case V_028714_SPI_SHADER_ZERO:
973 break;
974 case V_028714_SPI_SHADER_32_R:
975 cb_shader_mask |= 0x1 << (i * 4);
976 break;
977 case V_028714_SPI_SHADER_32_GR:
978 cb_shader_mask |= 0x3 << (i * 4);
979 break;
980 case V_028714_SPI_SHADER_32_AR:
981 cb_shader_mask |= 0x9 << (i * 4);
982 break;
983 case V_028714_SPI_SHADER_FP16_ABGR:
984 case V_028714_SPI_SHADER_UNORM16_ABGR:
985 case V_028714_SPI_SHADER_SNORM16_ABGR:
986 case V_028714_SPI_SHADER_UINT16_ABGR:
987 case V_028714_SPI_SHADER_SINT16_ABGR:
988 case V_028714_SPI_SHADER_32_ABGR:
989 cb_shader_mask |= 0xf << (i * 4);
990 break;
991 default:
992 assert(0);
993 }
994 }
995 return cb_shader_mask;
996 }
997
998 static void si_shader_ps(struct si_shader *shader)
999 {
1000 struct tgsi_shader_info *info = &shader->selector->info;
1001 struct si_pm4_state *pm4;
1002 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1003 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1004 uint64_t va;
1005 unsigned input_ena = shader->config.spi_ps_input_ena;
1006
1007 /* we need to enable at least one of them, otherwise we hang the GPU */
1008 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1009 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1010 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1011 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1012 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1013 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1014 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1015 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1016 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1017 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1018 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1019 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1020 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1021 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1022
1023 /* Validate interpolation optimization flags (read as implications). */
1024 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1025 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1026 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1027 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1028 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1029 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1030 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1031 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1032 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1033 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1034 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1035 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1036 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1037 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1038 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1039 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1040 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1041 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1042
1043 /* Validate cases when the optimizations are off (read as implications). */
1044 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1045 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1046 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1047 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1048 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1049 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1050
1051 pm4 = si_get_shader_pm4_state(shader);
1052 if (!pm4)
1053 return;
1054
1055 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1056 * Possible vaules:
1057 * 0 -> Position = pixel center
1058 * 1 -> Position = pixel centroid
1059 * 2 -> Position = at sample position
1060 *
1061 * From GLSL 4.5 specification, section 7.1:
1062 * "The variable gl_FragCoord is available as an input variable from
1063 * within fragment shaders and it holds the window relative coordinates
1064 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1065 * value can be for any location within the pixel, or one of the
1066 * fragment samples. The use of centroid does not further restrict
1067 * this value to be inside the current primitive."
1068 *
1069 * Meaning that centroid has no effect and we can return anything within
1070 * the pixel. Thus, return the value at sample position, because that's
1071 * the most accurate one shaders can get.
1072 */
1073 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1074
1075 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1076 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1077 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1078
1079 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1080 cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
1081
1082 /* Ensure that some export memory is always allocated, for two reasons:
1083 *
1084 * 1) Correctness: The hardware ignores the EXEC mask if no export
1085 * memory is allocated, so KILL and alpha test do not work correctly
1086 * without this.
1087 * 2) Performance: Every shader needs at least a NULL export, even when
1088 * it writes no color/depth output. The NULL export instruction
1089 * stalls without this setting.
1090 *
1091 * Don't add this to CB_SHADER_MASK.
1092 */
1093 if (!spi_shader_col_format &&
1094 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1095 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1096
1097 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
1098 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
1099 shader->config.spi_ps_input_addr);
1100
1101 /* Set interpolation controls. */
1102 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1103
1104 /* Set registers. */
1105 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1106 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
1107
1108 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
1109 si_get_spi_shader_z_format(info->writes_z,
1110 info->writes_stencil,
1111 info->writes_samplemask));
1112
1113 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
1114 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
1115
1116 va = shader->bo->gpu_address;
1117 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1118 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1119 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
1120
1121 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
1122 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1123 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
1124 S_00B028_DX10_CLAMP(1) |
1125 S_00B028_FLOAT_MODE(shader->config.float_mode));
1126 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1127 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1128 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1129 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1130 }
1131
1132 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1133 struct si_shader *shader)
1134 {
1135 switch (shader->selector->type) {
1136 case PIPE_SHADER_VERTEX:
1137 if (shader->key.as_ls)
1138 si_shader_ls(sscreen, shader);
1139 else if (shader->key.as_es)
1140 si_shader_es(sscreen, shader);
1141 else
1142 si_shader_vs(sscreen, shader, NULL);
1143 break;
1144 case PIPE_SHADER_TESS_CTRL:
1145 si_shader_hs(sscreen, shader);
1146 break;
1147 case PIPE_SHADER_TESS_EVAL:
1148 if (shader->key.as_es)
1149 si_shader_es(sscreen, shader);
1150 else
1151 si_shader_vs(sscreen, shader, NULL);
1152 break;
1153 case PIPE_SHADER_GEOMETRY:
1154 si_shader_gs(sscreen, shader);
1155 break;
1156 case PIPE_SHADER_FRAGMENT:
1157 si_shader_ps(shader);
1158 break;
1159 default:
1160 assert(0);
1161 }
1162 }
1163
1164 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1165 {
1166 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1167 if (sctx->queued.named.dsa)
1168 return sctx->queued.named.dsa->alpha_func;
1169
1170 return PIPE_FUNC_ALWAYS;
1171 }
1172
1173 static void si_shader_selector_key_vs(struct si_context *sctx,
1174 struct si_shader_selector *vs,
1175 struct si_shader_key *key,
1176 struct si_vs_prolog_bits *prolog_key)
1177 {
1178 if (!sctx->vertex_elements)
1179 return;
1180
1181 unsigned count = MIN2(vs->info.num_inputs,
1182 sctx->vertex_elements->count);
1183 for (unsigned i = 0; i < count; ++i) {
1184 prolog_key->instance_divisors[i] =
1185 sctx->vertex_elements->elements[i].instance_divisor;
1186 }
1187
1188 memcpy(key->mono.vs_fix_fetch, sctx->vertex_elements->fix_fetch, count);
1189 }
1190
1191 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1192 struct si_shader_selector *vs,
1193 struct si_shader_key *key)
1194 {
1195 struct si_shader_selector *ps = sctx->ps_shader.cso;
1196
1197 key->opt.hw_vs.clip_disable =
1198 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1199 (vs->info.clipdist_writemask ||
1200 vs->info.writes_clipvertex) &&
1201 !vs->info.culldist_writemask;
1202
1203 /* Find out if PS is disabled. */
1204 bool ps_disabled = true;
1205 if (ps) {
1206 bool ps_modifies_zs = ps->info.uses_kill ||
1207 ps->info.writes_z ||
1208 ps->info.writes_stencil ||
1209 ps->info.writes_samplemask ||
1210 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1211
1212 unsigned ps_colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1213 sctx->queued.named.blend->cb_target_mask;
1214 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1215 ps_colormask &= ps->colors_written_4bit;
1216
1217 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1218 (!ps_colormask &&
1219 !ps_modifies_zs &&
1220 !ps->info.writes_memory);
1221 }
1222
1223 /* Find out which VS outputs aren't used by the PS. */
1224 uint64_t outputs_written = vs->outputs_written;
1225 uint32_t outputs_written2 = vs->outputs_written2;
1226 uint64_t inputs_read = 0;
1227 uint32_t inputs_read2 = 0;
1228
1229 outputs_written &= ~0x3; /* ignore POSITION, PSIZE */
1230
1231 if (!ps_disabled) {
1232 inputs_read = ps->inputs_read;
1233 inputs_read2 = ps->inputs_read2;
1234 }
1235
1236 uint64_t linked = outputs_written & inputs_read;
1237 uint32_t linked2 = outputs_written2 & inputs_read2;
1238
1239 key->opt.hw_vs.kill_outputs = ~linked & outputs_written;
1240 key->opt.hw_vs.kill_outputs2 = ~linked2 & outputs_written2;
1241 }
1242
1243 /* Compute the key for the hw shader variant */
1244 static inline void si_shader_selector_key(struct pipe_context *ctx,
1245 struct si_shader_selector *sel,
1246 struct si_shader_key *key)
1247 {
1248 struct si_context *sctx = (struct si_context *)ctx;
1249
1250 memset(key, 0, sizeof(*key));
1251
1252 switch (sel->type) {
1253 case PIPE_SHADER_VERTEX:
1254 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1255
1256 if (sctx->tes_shader.cso)
1257 key->as_ls = 1;
1258 else if (sctx->gs_shader.cso)
1259 key->as_es = 1;
1260 else {
1261 si_shader_selector_key_hw_vs(sctx, sel, key);
1262
1263 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1264 key->part.vs.epilog.export_prim_id = 1;
1265 }
1266 break;
1267 case PIPE_SHADER_TESS_CTRL:
1268 if (sctx->b.chip_class >= GFX9) {
1269 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1270 key, &key->part.tcs.ls_prolog);
1271 key->part.tcs.ls = sctx->vs_shader.cso;
1272 }
1273
1274 key->part.tcs.epilog.prim_mode =
1275 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1276 key->part.tcs.epilog.tes_reads_tess_factors =
1277 sctx->tes_shader.cso->info.reads_tess_factors;
1278
1279 if (sel == sctx->fixed_func_tcs_shader.cso)
1280 key->mono.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1281 break;
1282 case PIPE_SHADER_TESS_EVAL:
1283 if (sctx->gs_shader.cso)
1284 key->as_es = 1;
1285 else {
1286 si_shader_selector_key_hw_vs(sctx, sel, key);
1287
1288 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1289 key->part.tes.epilog.export_prim_id = 1;
1290 }
1291 break;
1292 case PIPE_SHADER_GEOMETRY:
1293 if (sctx->b.chip_class >= GFX9) {
1294 if (sctx->tes_shader.cso) {
1295 key->part.gs.es = sctx->tes_shader.cso;
1296 } else {
1297 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1298 key, &key->part.gs.vs_prolog);
1299 key->part.gs.es = sctx->vs_shader.cso;
1300 }
1301
1302 /* Merged ES-GS can have unbalanced wave usage.
1303 *
1304 * ES threads are per-vertex, while GS threads are
1305 * per-primitive. So without any amplification, there
1306 * are fewer GS threads than ES threads, which can result
1307 * in empty (no-op) GS waves. With too much amplification,
1308 * there are more GS threads than ES threads, which
1309 * can result in empty (no-op) ES waves.
1310 *
1311 * Non-monolithic shaders are implemented by setting EXEC
1312 * at the beginning of shader parts, and don't jump to
1313 * the end if EXEC is 0.
1314 *
1315 * Monolithic shaders use conditional blocks, so they can
1316 * jump and skip empty waves of ES or GS. So set this to
1317 * always use optimized variants, which are monolithic.
1318 */
1319 key->opt.prefer_mono = 1;
1320 }
1321 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1322 break;
1323 case PIPE_SHADER_FRAGMENT: {
1324 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1325 struct si_state_blend *blend = sctx->queued.named.blend;
1326
1327 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1328 sel->info.colors_written == 0x1)
1329 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1330
1331 if (blend) {
1332 /* Select the shader color format based on whether
1333 * blending or alpha are needed.
1334 */
1335 key->part.ps.epilog.spi_shader_col_format =
1336 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1337 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1338 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1339 sctx->framebuffer.spi_shader_col_format_blend) |
1340 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1341 sctx->framebuffer.spi_shader_col_format_alpha) |
1342 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1343 sctx->framebuffer.spi_shader_col_format);
1344
1345 /* The output for dual source blending should have
1346 * the same format as the first output.
1347 */
1348 if (blend->dual_src_blend)
1349 key->part.ps.epilog.spi_shader_col_format |=
1350 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1351 } else
1352 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1353
1354 /* If alpha-to-coverage is enabled, we have to export alpha
1355 * even if there is no color buffer.
1356 */
1357 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1358 blend && blend->alpha_to_coverage)
1359 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1360
1361 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1362 * to the range supported by the type if a channel has less
1363 * than 16 bits and the export format is 16_ABGR.
1364 */
1365 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII) {
1366 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1367 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1368 }
1369
1370 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1371 if (!key->part.ps.epilog.last_cbuf) {
1372 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1373 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1374 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1375 }
1376
1377 if (rs) {
1378 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
1379 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
1380 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
1381 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
1382
1383 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1384 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1385
1386 if (sctx->queued.named.blend) {
1387 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1388 rs->multisample_enable;
1389 }
1390
1391 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1392 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1393 (is_line && rs->line_smooth)) &&
1394 sctx->framebuffer.nr_samples <= 1;
1395 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1396
1397 if (rs->force_persample_interp &&
1398 rs->multisample_enable &&
1399 sctx->framebuffer.nr_samples > 1 &&
1400 sctx->ps_iter_samples > 1) {
1401 key->part.ps.prolog.force_persp_sample_interp =
1402 sel->info.uses_persp_center ||
1403 sel->info.uses_persp_centroid;
1404
1405 key->part.ps.prolog.force_linear_sample_interp =
1406 sel->info.uses_linear_center ||
1407 sel->info.uses_linear_centroid;
1408 } else if (rs->multisample_enable &&
1409 sctx->framebuffer.nr_samples > 1) {
1410 key->part.ps.prolog.bc_optimize_for_persp =
1411 sel->info.uses_persp_center &&
1412 sel->info.uses_persp_centroid;
1413 key->part.ps.prolog.bc_optimize_for_linear =
1414 sel->info.uses_linear_center &&
1415 sel->info.uses_linear_centroid;
1416 } else {
1417 /* Make sure SPI doesn't compute more than 1 pair
1418 * of (i,j), which is the optimization here. */
1419 key->part.ps.prolog.force_persp_center_interp =
1420 sel->info.uses_persp_center +
1421 sel->info.uses_persp_centroid +
1422 sel->info.uses_persp_sample > 1;
1423
1424 key->part.ps.prolog.force_linear_center_interp =
1425 sel->info.uses_linear_center +
1426 sel->info.uses_linear_centroid +
1427 sel->info.uses_linear_sample > 1;
1428 }
1429 }
1430
1431 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1432 break;
1433 }
1434 default:
1435 assert(0);
1436 }
1437 }
1438
1439 static void si_build_shader_variant(void *job, int thread_index)
1440 {
1441 struct si_shader *shader = (struct si_shader *)job;
1442 struct si_shader_selector *sel = shader->selector;
1443 struct si_screen *sscreen = sel->screen;
1444 LLVMTargetMachineRef tm;
1445 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1446 int r;
1447
1448 if (thread_index >= 0) {
1449 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1450 tm = sscreen->tm[thread_index];
1451 if (!debug->async)
1452 debug = NULL;
1453 } else {
1454 tm = shader->compiler_ctx_state.tm;
1455 }
1456
1457 r = si_shader_create(sscreen, tm, shader, debug);
1458 if (unlikely(r)) {
1459 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1460 sel->type, r);
1461 shader->compilation_failed = true;
1462 return;
1463 }
1464
1465 if (shader->compiler_ctx_state.is_debug_context) {
1466 FILE *f = open_memstream(&shader->shader_log,
1467 &shader->shader_log_size);
1468 if (f) {
1469 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1470 fclose(f);
1471 }
1472 }
1473
1474 si_shader_init_pm4_state(sscreen, shader);
1475 }
1476
1477 static const struct si_shader_key zeroed;
1478
1479 static bool si_check_missing_main_part(struct si_screen *sscreen,
1480 struct si_shader_selector *sel,
1481 struct si_compiler_ctx_state *compiler_state,
1482 struct si_shader_key *key)
1483 {
1484 struct si_shader **mainp = si_get_main_shader_part(sel, key);
1485
1486 if (!*mainp) {
1487 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1488
1489 if (!main_part)
1490 return false;
1491
1492 main_part->selector = sel;
1493 main_part->key.as_es = key->as_es;
1494 main_part->key.as_ls = key->as_ls;
1495
1496 if (si_compile_tgsi_shader(sscreen, compiler_state->tm,
1497 main_part, false,
1498 &compiler_state->debug) != 0) {
1499 FREE(main_part);
1500 return false;
1501 }
1502 *mainp = main_part;
1503 }
1504 return true;
1505 }
1506
1507 static void si_destroy_shader_selector(struct si_context *sctx,
1508 struct si_shader_selector *sel);
1509
1510 static void si_shader_selector_reference(struct si_context *sctx,
1511 struct si_shader_selector **dst,
1512 struct si_shader_selector *src)
1513 {
1514 if (pipe_reference(&(*dst)->reference, &src->reference))
1515 si_destroy_shader_selector(sctx, *dst);
1516
1517 *dst = src;
1518 }
1519
1520 /* Select the hw shader variant depending on the current state. */
1521 static int si_shader_select_with_key(struct si_screen *sscreen,
1522 struct si_shader_ctx_state *state,
1523 struct si_compiler_ctx_state *compiler_state,
1524 struct si_shader_key *key,
1525 int thread_index)
1526 {
1527 struct si_shader_selector *sel = state->cso;
1528 struct si_shader_selector *previous_stage_sel = NULL;
1529 struct si_shader *current = state->current;
1530 struct si_shader *iter, *shader = NULL;
1531
1532 if (unlikely(sscreen->b.debug_flags & DBG_NO_OPT_VARIANT)) {
1533 memset(&key->opt, 0, sizeof(key->opt));
1534 }
1535
1536 again:
1537 /* Check if we don't need to change anything.
1538 * This path is also used for most shaders that don't need multiple
1539 * variants, it will cost just a computation of the key and this
1540 * test. */
1541 if (likely(current &&
1542 memcmp(&current->key, key, sizeof(*key)) == 0 &&
1543 (!current->is_optimized ||
1544 util_queue_fence_is_signalled(&current->optimized_ready))))
1545 return current->compilation_failed ? -1 : 0;
1546
1547 /* This must be done before the mutex is locked, because async GS
1548 * compilation calls this function too, and therefore must enter
1549 * the mutex first.
1550 *
1551 * Only wait if we are in a draw call. Don't wait if we are
1552 * in a compiler thread.
1553 */
1554 if (thread_index < 0)
1555 util_queue_fence_wait(&sel->ready);
1556
1557 mtx_lock(&sel->mutex);
1558
1559 /* Find the shader variant. */
1560 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1561 /* Don't check the "current" shader. We checked it above. */
1562 if (current != iter &&
1563 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1564 /* If it's an optimized shader and its compilation has
1565 * been started but isn't done, use the unoptimized
1566 * shader so as not to cause a stall due to compilation.
1567 */
1568 if (iter->is_optimized &&
1569 !util_queue_fence_is_signalled(&iter->optimized_ready)) {
1570 memset(&key->opt, 0, sizeof(key->opt));
1571 mtx_unlock(&sel->mutex);
1572 goto again;
1573 }
1574
1575 if (iter->compilation_failed) {
1576 mtx_unlock(&sel->mutex);
1577 return -1; /* skip the draw call */
1578 }
1579
1580 state->current = iter;
1581 mtx_unlock(&sel->mutex);
1582 return 0;
1583 }
1584 }
1585
1586 /* Build a new shader. */
1587 shader = CALLOC_STRUCT(si_shader);
1588 if (!shader) {
1589 mtx_unlock(&sel->mutex);
1590 return -ENOMEM;
1591 }
1592 shader->selector = sel;
1593 shader->key = *key;
1594 shader->compiler_ctx_state = *compiler_state;
1595
1596 /* If this is a merged shader, get the first shader's selector. */
1597 if (sscreen->b.chip_class >= GFX9) {
1598 if (sel->type == PIPE_SHADER_TESS_CTRL)
1599 previous_stage_sel = key->part.tcs.ls;
1600 else if (sel->type == PIPE_SHADER_GEOMETRY)
1601 previous_stage_sel = key->part.gs.es;
1602 }
1603
1604 /* Compile the main shader part if it doesn't exist. This can happen
1605 * if the initial guess was wrong. */
1606 bool is_pure_monolithic =
1607 sscreen->use_monolithic_shaders ||
1608 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1609
1610 if (!is_pure_monolithic) {
1611 bool ok;
1612
1613 /* Make sure the main shader part is present. This is needed
1614 * for shaders that can be compiled as VS, LS, or ES, and only
1615 * one of them is compiled at creation.
1616 *
1617 * For merged shaders, check that the starting shader's main
1618 * part is present.
1619 */
1620 if (previous_stage_sel) {
1621 struct si_shader_key shader1_key = zeroed;
1622
1623 if (sel->type == PIPE_SHADER_TESS_CTRL)
1624 shader1_key.as_ls = 1;
1625 else if (sel->type == PIPE_SHADER_GEOMETRY)
1626 shader1_key.as_es = 1;
1627 else
1628 assert(0);
1629
1630 ok = si_check_missing_main_part(sscreen,
1631 previous_stage_sel,
1632 compiler_state, &shader1_key);
1633 } else {
1634 ok = si_check_missing_main_part(sscreen, sel,
1635 compiler_state, key);
1636 }
1637 if (!ok) {
1638 FREE(shader);
1639 mtx_unlock(&sel->mutex);
1640 return -ENOMEM; /* skip the draw call */
1641 }
1642 }
1643
1644 /* Keep the reference to the 1st shader of merged shaders, so that
1645 * Gallium can't destroy it before we destroy the 2nd shader.
1646 *
1647 * Set sctx = NULL, because it's unused if we're not releasing
1648 * the shader, and we don't have any sctx here.
1649 */
1650 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
1651 previous_stage_sel);
1652
1653 /* Monolithic-only shaders don't make a distinction between optimized
1654 * and unoptimized. */
1655 shader->is_monolithic =
1656 is_pure_monolithic ||
1657 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1658
1659 shader->is_optimized =
1660 !is_pure_monolithic &&
1661 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1662 if (shader->is_optimized)
1663 util_queue_fence_init(&shader->optimized_ready);
1664
1665 if (!sel->last_variant) {
1666 sel->first_variant = shader;
1667 sel->last_variant = shader;
1668 } else {
1669 sel->last_variant->next_variant = shader;
1670 sel->last_variant = shader;
1671 }
1672
1673 /* If it's an optimized shader, compile it asynchronously. */
1674 if (shader->is_optimized &&
1675 !is_pure_monolithic &&
1676 thread_index < 0) {
1677 /* Compile it asynchronously. */
1678 util_queue_add_job(&sscreen->shader_compiler_queue,
1679 shader, &shader->optimized_ready,
1680 si_build_shader_variant, NULL);
1681
1682 /* Use the default (unoptimized) shader for now. */
1683 memset(&key->opt, 0, sizeof(key->opt));
1684 mtx_unlock(&sel->mutex);
1685 goto again;
1686 }
1687
1688 assert(!shader->is_optimized);
1689 si_build_shader_variant(shader, thread_index);
1690
1691 if (!shader->compilation_failed)
1692 state->current = shader;
1693
1694 mtx_unlock(&sel->mutex);
1695 return shader->compilation_failed ? -1 : 0;
1696 }
1697
1698 static int si_shader_select(struct pipe_context *ctx,
1699 struct si_shader_ctx_state *state,
1700 struct si_compiler_ctx_state *compiler_state)
1701 {
1702 struct si_context *sctx = (struct si_context *)ctx;
1703 struct si_shader_key key;
1704
1705 si_shader_selector_key(ctx, state->cso, &key);
1706 return si_shader_select_with_key(sctx->screen, state, compiler_state,
1707 &key, -1);
1708 }
1709
1710 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1711 struct si_shader_key *key)
1712 {
1713 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1714
1715 switch (info->processor) {
1716 case PIPE_SHADER_VERTEX:
1717 switch (next_shader) {
1718 case PIPE_SHADER_GEOMETRY:
1719 key->as_es = 1;
1720 break;
1721 case PIPE_SHADER_TESS_CTRL:
1722 case PIPE_SHADER_TESS_EVAL:
1723 key->as_ls = 1;
1724 break;
1725 default:
1726 /* If POSITION isn't written, it can't be a HW VS.
1727 * Assume that it's a HW LS. (the next shader is TCS)
1728 * This heuristic is needed for separate shader objects.
1729 */
1730 if (!info->writes_position)
1731 key->as_ls = 1;
1732 }
1733 break;
1734
1735 case PIPE_SHADER_TESS_EVAL:
1736 if (next_shader == PIPE_SHADER_GEOMETRY ||
1737 !info->writes_position)
1738 key->as_es = 1;
1739 break;
1740 }
1741 }
1742
1743 /**
1744 * Compile the main shader part or the monolithic shader as part of
1745 * si_shader_selector initialization. Since it can be done asynchronously,
1746 * there is no way to report compile failures to applications.
1747 */
1748 void si_init_shader_selector_async(void *job, int thread_index)
1749 {
1750 struct si_shader_selector *sel = (struct si_shader_selector *)job;
1751 struct si_screen *sscreen = sel->screen;
1752 LLVMTargetMachineRef tm;
1753 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
1754 unsigned i;
1755
1756 if (thread_index >= 0) {
1757 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1758 tm = sscreen->tm[thread_index];
1759 if (!debug->async)
1760 debug = NULL;
1761 } else {
1762 tm = sel->compiler_ctx_state.tm;
1763 }
1764
1765 /* Compile the main shader part for use with a prolog and/or epilog.
1766 * If this fails, the driver will try to compile a monolithic shader
1767 * on demand.
1768 */
1769 if (!sscreen->use_monolithic_shaders) {
1770 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1771 void *tgsi_binary;
1772
1773 if (!shader) {
1774 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
1775 return;
1776 }
1777
1778 shader->selector = sel;
1779 si_parse_next_shader_property(&sel->info, &shader->key);
1780
1781 tgsi_binary = si_get_tgsi_binary(sel);
1782
1783 /* Try to load the shader from the shader cache. */
1784 mtx_lock(&sscreen->shader_cache_mutex);
1785
1786 if (tgsi_binary &&
1787 si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
1788 mtx_unlock(&sscreen->shader_cache_mutex);
1789 } else {
1790 mtx_unlock(&sscreen->shader_cache_mutex);
1791
1792 /* Compile the shader if it hasn't been loaded from the cache. */
1793 if (si_compile_tgsi_shader(sscreen, tm, shader, false,
1794 debug) != 0) {
1795 FREE(shader);
1796 FREE(tgsi_binary);
1797 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
1798 return;
1799 }
1800
1801 if (tgsi_binary) {
1802 mtx_lock(&sscreen->shader_cache_mutex);
1803 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary, shader, true))
1804 FREE(tgsi_binary);
1805 mtx_unlock(&sscreen->shader_cache_mutex);
1806 }
1807 }
1808
1809 *si_get_main_shader_part(sel, &shader->key) = shader;
1810
1811 /* Unset "outputs_written" flags for outputs converted to
1812 * DEFAULT_VAL, so that later inter-shader optimizations don't
1813 * try to eliminate outputs that don't exist in the final
1814 * shader.
1815 *
1816 * This is only done if non-monolithic shaders are enabled.
1817 */
1818 if ((sel->type == PIPE_SHADER_VERTEX ||
1819 sel->type == PIPE_SHADER_TESS_EVAL) &&
1820 !shader->key.as_ls &&
1821 !shader->key.as_es) {
1822 unsigned i;
1823
1824 for (i = 0; i < sel->info.num_outputs; i++) {
1825 unsigned offset = shader->info.vs_output_param_offset[i];
1826
1827 if (offset <= AC_EXP_PARAM_OFFSET_31)
1828 continue;
1829
1830 unsigned name = sel->info.output_semantic_name[i];
1831 unsigned index = sel->info.output_semantic_index[i];
1832 unsigned id;
1833
1834 switch (name) {
1835 case TGSI_SEMANTIC_GENERIC:
1836 /* don't process indices the function can't handle */
1837 if (index >= 60)
1838 break;
1839 /* fall through */
1840 case TGSI_SEMANTIC_CLIPDIST:
1841 id = si_shader_io_get_unique_index(name, index);
1842 sel->outputs_written &= ~(1ull << id);
1843 break;
1844 case TGSI_SEMANTIC_POSITION: /* ignore these */
1845 case TGSI_SEMANTIC_PSIZE:
1846 case TGSI_SEMANTIC_CLIPVERTEX:
1847 case TGSI_SEMANTIC_EDGEFLAG:
1848 break;
1849 default:
1850 id = si_shader_io_get_unique_index2(name, index);
1851 sel->outputs_written2 &= ~(1u << id);
1852 }
1853 }
1854 }
1855 }
1856
1857 /* Pre-compilation. */
1858 if (sscreen->b.debug_flags & DBG_PRECOMPILE) {
1859 struct si_shader_ctx_state state = {sel};
1860 struct si_shader_key key;
1861
1862 memset(&key, 0, sizeof(key));
1863 si_parse_next_shader_property(&sel->info, &key);
1864
1865 /* Set reasonable defaults, so that the shader key doesn't
1866 * cause any code to be eliminated.
1867 */
1868 switch (sel->type) {
1869 case PIPE_SHADER_TESS_CTRL:
1870 key.part.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
1871 break;
1872 case PIPE_SHADER_FRAGMENT:
1873 key.part.ps.prolog.bc_optimize_for_persp =
1874 sel->info.uses_persp_center &&
1875 sel->info.uses_persp_centroid;
1876 key.part.ps.prolog.bc_optimize_for_linear =
1877 sel->info.uses_linear_center &&
1878 sel->info.uses_linear_centroid;
1879 key.part.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
1880 for (i = 0; i < 8; i++)
1881 if (sel->info.colors_written & (1 << i))
1882 key.part.ps.epilog.spi_shader_col_format |=
1883 V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
1884 break;
1885 }
1886
1887 if (si_shader_select_with_key(sscreen, &state,
1888 &sel->compiler_ctx_state, &key,
1889 thread_index))
1890 fprintf(stderr, "radeonsi: can't create a monolithic shader\n");
1891 }
1892
1893 /* The GS copy shader is always pre-compiled. */
1894 if (sel->type == PIPE_SHADER_GEOMETRY) {
1895 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, tm, sel, debug);
1896 if (!sel->gs_copy_shader) {
1897 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
1898 return;
1899 }
1900
1901 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
1902 }
1903 }
1904
1905 static void *si_create_shader_selector(struct pipe_context *ctx,
1906 const struct pipe_shader_state *state)
1907 {
1908 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
1909 struct si_context *sctx = (struct si_context*)ctx;
1910 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
1911 int i;
1912
1913 if (!sel)
1914 return NULL;
1915
1916 pipe_reference_init(&sel->reference, 1);
1917 sel->screen = sscreen;
1918 sel->compiler_ctx_state.tm = sctx->tm;
1919 sel->compiler_ctx_state.debug = sctx->b.debug;
1920 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
1921 sel->tokens = tgsi_dup_tokens(state->tokens);
1922 if (!sel->tokens) {
1923 FREE(sel);
1924 return NULL;
1925 }
1926
1927 sel->so = state->stream_output;
1928 tgsi_scan_shader(state->tokens, &sel->info);
1929 sel->type = sel->info.processor;
1930 p_atomic_inc(&sscreen->b.num_shaders_created);
1931
1932 /* The prolog is a no-op if there are no inputs. */
1933 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
1934 sel->info.num_inputs;
1935
1936 /* Set which opcode uses which (i,j) pair. */
1937 if (sel->info.uses_persp_opcode_interp_centroid)
1938 sel->info.uses_persp_centroid = true;
1939
1940 if (sel->info.uses_linear_opcode_interp_centroid)
1941 sel->info.uses_linear_centroid = true;
1942
1943 if (sel->info.uses_persp_opcode_interp_offset ||
1944 sel->info.uses_persp_opcode_interp_sample)
1945 sel->info.uses_persp_center = true;
1946
1947 if (sel->info.uses_linear_opcode_interp_offset ||
1948 sel->info.uses_linear_opcode_interp_sample)
1949 sel->info.uses_linear_center = true;
1950
1951 switch (sel->type) {
1952 case PIPE_SHADER_GEOMETRY:
1953 sel->gs_output_prim =
1954 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
1955 sel->gs_max_out_vertices =
1956 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
1957 sel->gs_num_invocations =
1958 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
1959 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
1960 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
1961 sel->gs_max_out_vertices;
1962
1963 sel->max_gs_stream = 0;
1964 for (i = 0; i < sel->so.num_outputs; i++)
1965 sel->max_gs_stream = MAX2(sel->max_gs_stream,
1966 sel->so.output[i].stream);
1967
1968 sel->gs_input_verts_per_prim =
1969 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
1970 break;
1971
1972 case PIPE_SHADER_TESS_CTRL:
1973 /* Always reserve space for these. */
1974 sel->patch_outputs_written |=
1975 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0)) |
1976 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0));
1977 /* fall through */
1978 case PIPE_SHADER_VERTEX:
1979 case PIPE_SHADER_TESS_EVAL:
1980 for (i = 0; i < sel->info.num_outputs; i++) {
1981 unsigned name = sel->info.output_semantic_name[i];
1982 unsigned index = sel->info.output_semantic_index[i];
1983
1984 switch (name) {
1985 case TGSI_SEMANTIC_TESSINNER:
1986 case TGSI_SEMANTIC_TESSOUTER:
1987 case TGSI_SEMANTIC_PATCH:
1988 sel->patch_outputs_written |=
1989 1llu << si_shader_io_get_unique_index(name, index);
1990 break;
1991
1992 case TGSI_SEMANTIC_GENERIC:
1993 /* don't process indices the function can't handle */
1994 if (index >= 60)
1995 break;
1996 /* fall through */
1997 case TGSI_SEMANTIC_POSITION:
1998 case TGSI_SEMANTIC_PSIZE:
1999 case TGSI_SEMANTIC_CLIPDIST:
2000 sel->outputs_written |=
2001 1llu << si_shader_io_get_unique_index(name, index);
2002 break;
2003 case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */
2004 case TGSI_SEMANTIC_EDGEFLAG:
2005 break;
2006 default:
2007 sel->outputs_written2 |=
2008 1u << si_shader_io_get_unique_index2(name, index);
2009 }
2010 }
2011 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2012
2013 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2014 * conflicts, i.e. each vertex will start at a different bank.
2015 */
2016 if (sctx->b.chip_class >= GFX9)
2017 sel->esgs_itemsize += 4;
2018 break;
2019
2020 case PIPE_SHADER_FRAGMENT:
2021 for (i = 0; i < sel->info.num_inputs; i++) {
2022 unsigned name = sel->info.input_semantic_name[i];
2023 unsigned index = sel->info.input_semantic_index[i];
2024
2025 switch (name) {
2026 case TGSI_SEMANTIC_CLIPDIST:
2027 case TGSI_SEMANTIC_GENERIC:
2028 sel->inputs_read |=
2029 1llu << si_shader_io_get_unique_index(name, index);
2030 break;
2031 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2032 break;
2033 default:
2034 sel->inputs_read2 |=
2035 1u << si_shader_io_get_unique_index2(name, index);
2036 }
2037 }
2038
2039 for (i = 0; i < 8; i++)
2040 if (sel->info.colors_written & (1 << i))
2041 sel->colors_written_4bit |= 0xf << (4 * i);
2042
2043 for (i = 0; i < sel->info.num_inputs; i++) {
2044 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2045 int index = sel->info.input_semantic_index[i];
2046 sel->color_attr_index[index] = i;
2047 }
2048 }
2049 break;
2050 }
2051
2052 /* DB_SHADER_CONTROL */
2053 sel->db_shader_control =
2054 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2055 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2056 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2057 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2058
2059 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2060 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2061 sel->db_shader_control |=
2062 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2063 break;
2064 case TGSI_FS_DEPTH_LAYOUT_LESS:
2065 sel->db_shader_control |=
2066 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2067 break;
2068 }
2069
2070 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2071 *
2072 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2073 * --|-----------|------------|------------|--------------------|-------------------|-------------
2074 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2075 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2076 * 2 | false | true | n/a | LateZ | 1 | 0
2077 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2078 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2079 *
2080 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2081 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2082 *
2083 * Don't use ReZ without profiling !!!
2084 *
2085 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2086 * shaders.
2087 */
2088 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2089 /* Cases 3, 4. */
2090 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2091 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2092 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2093 } else if (sel->info.writes_memory) {
2094 /* Case 2. */
2095 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2096 S_02880C_EXEC_ON_HIER_FAIL(1);
2097 } else {
2098 /* Case 1. */
2099 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2100 }
2101
2102 (void) mtx_init(&sel->mutex, mtx_plain);
2103 util_queue_fence_init(&sel->ready);
2104
2105 if ((sctx->b.debug.debug_message && !sctx->b.debug.async) ||
2106 sctx->is_debug ||
2107 r600_can_dump_shader(&sscreen->b, sel->info.processor))
2108 si_init_shader_selector_async(sel, -1);
2109 else
2110 util_queue_add_job(&sscreen->shader_compiler_queue, sel,
2111 &sel->ready, si_init_shader_selector_async,
2112 NULL);
2113
2114 return sel;
2115 }
2116
2117 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2118 {
2119 struct si_context *sctx = (struct si_context *)ctx;
2120 struct si_shader_selector *sel = state;
2121
2122 if (sctx->vs_shader.cso == sel)
2123 return;
2124
2125 sctx->vs_shader.cso = sel;
2126 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2127 sctx->do_update_shaders = true;
2128 si_mark_atom_dirty(sctx, &sctx->clip_regs);
2129 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
2130 }
2131
2132 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2133 {
2134 struct si_context *sctx = (struct si_context *)ctx;
2135 struct si_shader_selector *sel = state;
2136 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2137
2138 if (sctx->gs_shader.cso == sel)
2139 return;
2140
2141 sctx->gs_shader.cso = sel;
2142 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2143 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2144 sctx->do_update_shaders = true;
2145 si_mark_atom_dirty(sctx, &sctx->clip_regs);
2146 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2147
2148 if (enable_changed)
2149 si_shader_change_notify(sctx);
2150 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
2151 }
2152
2153 static void si_update_tcs_tes_uses_prim_id(struct si_context *sctx)
2154 {
2155 sctx->ia_multi_vgt_param_key.u.tcs_tes_uses_prim_id =
2156 (sctx->tes_shader.cso &&
2157 sctx->tes_shader.cso->info.uses_primid) ||
2158 (sctx->tcs_shader.cso &&
2159 sctx->tcs_shader.cso->info.uses_primid);
2160 }
2161
2162 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2163 {
2164 struct si_context *sctx = (struct si_context *)ctx;
2165 struct si_shader_selector *sel = state;
2166 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2167
2168 if (sctx->tcs_shader.cso == sel)
2169 return;
2170
2171 sctx->tcs_shader.cso = sel;
2172 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
2173 si_update_tcs_tes_uses_prim_id(sctx);
2174 sctx->do_update_shaders = true;
2175
2176 if (enable_changed)
2177 sctx->last_tcs = NULL; /* invalidate derived tess state */
2178 }
2179
2180 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
2181 {
2182 struct si_context *sctx = (struct si_context *)ctx;
2183 struct si_shader_selector *sel = state;
2184 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
2185
2186 if (sctx->tes_shader.cso == sel)
2187 return;
2188
2189 sctx->tes_shader.cso = sel;
2190 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
2191 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
2192 si_update_tcs_tes_uses_prim_id(sctx);
2193 sctx->do_update_shaders = true;
2194 si_mark_atom_dirty(sctx, &sctx->clip_regs);
2195 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2196
2197 if (enable_changed) {
2198 si_shader_change_notify(sctx);
2199 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
2200 }
2201 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
2202 }
2203
2204 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2205 {
2206 struct si_context *sctx = (struct si_context *)ctx;
2207 struct si_shader_selector *sel = state;
2208
2209 /* skip if supplied shader is one already in use */
2210 if (sctx->ps_shader.cso == sel)
2211 return;
2212
2213 sctx->ps_shader.cso = sel;
2214 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
2215 sctx->do_update_shaders = true;
2216 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2217 }
2218
2219 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
2220 {
2221 if (shader->is_optimized) {
2222 util_queue_fence_wait(&shader->optimized_ready);
2223 util_queue_fence_destroy(&shader->optimized_ready);
2224 }
2225
2226 if (shader->pm4) {
2227 switch (shader->selector->type) {
2228 case PIPE_SHADER_VERTEX:
2229 if (shader->key.as_ls) {
2230 assert(sctx->b.chip_class <= VI);
2231 si_pm4_delete_state(sctx, ls, shader->pm4);
2232 } else if (shader->key.as_es) {
2233 assert(sctx->b.chip_class <= VI);
2234 si_pm4_delete_state(sctx, es, shader->pm4);
2235 } else {
2236 si_pm4_delete_state(sctx, vs, shader->pm4);
2237 }
2238 break;
2239 case PIPE_SHADER_TESS_CTRL:
2240 si_pm4_delete_state(sctx, hs, shader->pm4);
2241 break;
2242 case PIPE_SHADER_TESS_EVAL:
2243 if (shader->key.as_es) {
2244 assert(sctx->b.chip_class <= VI);
2245 si_pm4_delete_state(sctx, es, shader->pm4);
2246 } else {
2247 si_pm4_delete_state(sctx, vs, shader->pm4);
2248 }
2249 break;
2250 case PIPE_SHADER_GEOMETRY:
2251 if (shader->is_gs_copy_shader)
2252 si_pm4_delete_state(sctx, vs, shader->pm4);
2253 else
2254 si_pm4_delete_state(sctx, gs, shader->pm4);
2255 break;
2256 case PIPE_SHADER_FRAGMENT:
2257 si_pm4_delete_state(sctx, ps, shader->pm4);
2258 break;
2259 }
2260 }
2261
2262 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
2263 si_shader_destroy(shader);
2264 free(shader);
2265 }
2266
2267 static void si_destroy_shader_selector(struct si_context *sctx,
2268 struct si_shader_selector *sel)
2269 {
2270 struct si_shader *p = sel->first_variant, *c;
2271 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
2272 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
2273 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
2274 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
2275 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
2276 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
2277 };
2278
2279 util_queue_fence_wait(&sel->ready);
2280
2281 if (current_shader[sel->type]->cso == sel) {
2282 current_shader[sel->type]->cso = NULL;
2283 current_shader[sel->type]->current = NULL;
2284 }
2285
2286 while (p) {
2287 c = p->next_variant;
2288 si_delete_shader(sctx, p);
2289 p = c;
2290 }
2291
2292 if (sel->main_shader_part)
2293 si_delete_shader(sctx, sel->main_shader_part);
2294 if (sel->main_shader_part_ls)
2295 si_delete_shader(sctx, sel->main_shader_part_ls);
2296 if (sel->main_shader_part_es)
2297 si_delete_shader(sctx, sel->main_shader_part_es);
2298 if (sel->gs_copy_shader)
2299 si_delete_shader(sctx, sel->gs_copy_shader);
2300
2301 util_queue_fence_destroy(&sel->ready);
2302 mtx_destroy(&sel->mutex);
2303 free(sel->tokens);
2304 free(sel);
2305 }
2306
2307 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
2308 {
2309 struct si_context *sctx = (struct si_context *)ctx;
2310 struct si_shader_selector *sel = (struct si_shader_selector *)state;
2311
2312 si_shader_selector_reference(sctx, &sel, NULL);
2313 }
2314
2315 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
2316 struct si_shader *vs, unsigned name,
2317 unsigned index, unsigned interpolate)
2318 {
2319 struct tgsi_shader_info *vsinfo = &vs->selector->info;
2320 unsigned j, offset, ps_input_cntl = 0;
2321
2322 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
2323 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
2324 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2325
2326 if (name == TGSI_SEMANTIC_PCOORD ||
2327 (name == TGSI_SEMANTIC_TEXCOORD &&
2328 sctx->sprite_coord_enable & (1 << index))) {
2329 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
2330 }
2331
2332 for (j = 0; j < vsinfo->num_outputs; j++) {
2333 if (name == vsinfo->output_semantic_name[j] &&
2334 index == vsinfo->output_semantic_index[j]) {
2335 offset = vs->info.vs_output_param_offset[j];
2336
2337 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2338 /* The input is loaded from parameter memory. */
2339 ps_input_cntl |= S_028644_OFFSET(offset);
2340 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2341 if (offset == AC_EXP_PARAM_UNDEFINED) {
2342 /* This can happen with depth-only rendering. */
2343 offset = 0;
2344 } else {
2345 /* The input is a DEFAULT_VAL constant. */
2346 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2347 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2348 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2349 }
2350
2351 ps_input_cntl = S_028644_OFFSET(0x20) |
2352 S_028644_DEFAULT_VAL(offset);
2353 }
2354 break;
2355 }
2356 }
2357
2358 if (name == TGSI_SEMANTIC_PRIMID)
2359 /* PrimID is written after the last output. */
2360 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
2361 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2362 /* No corresponding output found, load defaults into input.
2363 * Don't set any other bits.
2364 * (FLAT_SHADE=1 completely changes behavior) */
2365 ps_input_cntl = S_028644_OFFSET(0x20);
2366 /* D3D 9 behaviour. GL is undefined */
2367 if (name == TGSI_SEMANTIC_COLOR && index == 0)
2368 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
2369 }
2370 return ps_input_cntl;
2371 }
2372
2373 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
2374 {
2375 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2376 struct si_shader *ps = sctx->ps_shader.current;
2377 struct si_shader *vs = si_get_vs_state(sctx);
2378 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
2379 unsigned i, num_interp, num_written = 0, bcol_interp[2];
2380
2381 if (!ps || !ps->selector->info.num_inputs)
2382 return;
2383
2384 num_interp = si_get_ps_num_interp(ps);
2385 assert(num_interp > 0);
2386 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
2387
2388 for (i = 0; i < psinfo->num_inputs; i++) {
2389 unsigned name = psinfo->input_semantic_name[i];
2390 unsigned index = psinfo->input_semantic_index[i];
2391 unsigned interpolate = psinfo->input_interpolate[i];
2392
2393 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
2394 interpolate));
2395 num_written++;
2396
2397 if (name == TGSI_SEMANTIC_COLOR) {
2398 assert(index < ARRAY_SIZE(bcol_interp));
2399 bcol_interp[index] = interpolate;
2400 }
2401 }
2402
2403 if (ps->key.part.ps.prolog.color_two_side) {
2404 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
2405
2406 for (i = 0; i < 2; i++) {
2407 if (!(psinfo->colors_read & (0xf << (i * 4))))
2408 continue;
2409
2410 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
2411 i, bcol_interp[i]));
2412 num_written++;
2413 }
2414 }
2415 assert(num_interp == num_written);
2416 }
2417
2418 /**
2419 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2420 */
2421 static void si_init_config_add_vgt_flush(struct si_context *sctx)
2422 {
2423 if (sctx->init_config_has_vgt_flush)
2424 return;
2425
2426 /* Done by Vulkan before VGT_FLUSH. */
2427 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2428 si_pm4_cmd_add(sctx->init_config,
2429 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2430 si_pm4_cmd_end(sctx->init_config, false);
2431
2432 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2433 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2434 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2435 si_pm4_cmd_end(sctx->init_config, false);
2436 sctx->init_config_has_vgt_flush = true;
2437 }
2438
2439 /* Initialize state related to ESGS / GSVS ring buffers */
2440 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2441 {
2442 struct si_shader_selector *es =
2443 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2444 struct si_shader_selector *gs = sctx->gs_shader.cso;
2445 struct si_pm4_state *pm4;
2446
2447 /* Chip constants. */
2448 unsigned num_se = sctx->screen->b.info.max_se;
2449 unsigned wave_size = 64;
2450 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2451 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2452 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2453 */
2454 unsigned gs_vertex_reuse = (sctx->b.chip_class >= VI ? 32 : 16) * num_se;
2455 unsigned alignment = 256 * num_se;
2456 /* The maximum size is 63.999 MB per SE. */
2457 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2458
2459 /* Calculate the minimum size. */
2460 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
2461 wave_size, alignment);
2462
2463 /* These are recommended sizes, not minimum sizes. */
2464 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2465 es->esgs_itemsize * gs->gs_input_verts_per_prim;
2466 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2467 gs->max_gsvs_emit_size;
2468
2469 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2470 esgs_ring_size = align(esgs_ring_size, alignment);
2471 gsvs_ring_size = align(gsvs_ring_size, alignment);
2472
2473 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2474 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2475
2476 /* Some rings don't have to be allocated if shaders don't use them.
2477 * (e.g. no varyings between ES and GS or GS and VS)
2478 *
2479 * GFX9 doesn't have the ESGS ring.
2480 */
2481 bool update_esgs = sctx->b.chip_class <= VI &&
2482 esgs_ring_size &&
2483 (!sctx->esgs_ring ||
2484 sctx->esgs_ring->width0 < esgs_ring_size);
2485 bool update_gsvs = gsvs_ring_size &&
2486 (!sctx->gsvs_ring ||
2487 sctx->gsvs_ring->width0 < gsvs_ring_size);
2488
2489 if (!update_esgs && !update_gsvs)
2490 return true;
2491
2492 if (update_esgs) {
2493 pipe_resource_reference(&sctx->esgs_ring, NULL);
2494 sctx->esgs_ring =
2495 r600_aligned_buffer_create(sctx->b.b.screen,
2496 R600_RESOURCE_FLAG_UNMAPPABLE,
2497 PIPE_USAGE_DEFAULT,
2498 esgs_ring_size, alignment);
2499 if (!sctx->esgs_ring)
2500 return false;
2501 }
2502
2503 if (update_gsvs) {
2504 pipe_resource_reference(&sctx->gsvs_ring, NULL);
2505 sctx->gsvs_ring =
2506 r600_aligned_buffer_create(sctx->b.b.screen,
2507 R600_RESOURCE_FLAG_UNMAPPABLE,
2508 PIPE_USAGE_DEFAULT,
2509 gsvs_ring_size, alignment);
2510 if (!sctx->gsvs_ring)
2511 return false;
2512 }
2513
2514 /* Create the "init_config_gs_rings" state. */
2515 pm4 = CALLOC_STRUCT(si_pm4_state);
2516 if (!pm4)
2517 return false;
2518
2519 if (sctx->b.chip_class >= CIK) {
2520 if (sctx->esgs_ring) {
2521 assert(sctx->b.chip_class <= VI);
2522 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2523 sctx->esgs_ring->width0 / 256);
2524 }
2525 if (sctx->gsvs_ring)
2526 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2527 sctx->gsvs_ring->width0 / 256);
2528 } else {
2529 if (sctx->esgs_ring)
2530 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2531 sctx->esgs_ring->width0 / 256);
2532 if (sctx->gsvs_ring)
2533 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2534 sctx->gsvs_ring->width0 / 256);
2535 }
2536
2537 /* Set the state. */
2538 if (sctx->init_config_gs_rings)
2539 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
2540 sctx->init_config_gs_rings = pm4;
2541
2542 if (!sctx->init_config_has_vgt_flush) {
2543 si_init_config_add_vgt_flush(sctx);
2544 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2545 }
2546
2547 /* Flush the context to re-emit both init_config states. */
2548 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2549 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2550
2551 /* Set ring bindings. */
2552 if (sctx->esgs_ring) {
2553 assert(sctx->b.chip_class <= VI);
2554 si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
2555 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2556 true, true, 4, 64, 0);
2557 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
2558 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2559 false, false, 0, 0, 0);
2560 }
2561 if (sctx->gsvs_ring) {
2562 si_set_ring_buffer(&sctx->b.b, SI_RING_GSVS,
2563 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
2564 false, false, 0, 0, 0);
2565 }
2566
2567 return true;
2568 }
2569
2570 /**
2571 * @returns 1 if \p sel has been updated to use a new scratch buffer
2572 * 0 if not
2573 * < 0 if there was a failure
2574 */
2575 static int si_update_scratch_buffer(struct si_context *sctx,
2576 struct si_shader *shader)
2577 {
2578 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
2579 int r;
2580
2581 if (!shader)
2582 return 0;
2583
2584 /* This shader doesn't need a scratch buffer */
2585 if (shader->config.scratch_bytes_per_wave == 0)
2586 return 0;
2587
2588 /* This shader is already configured to use the current
2589 * scratch buffer. */
2590 if (shader->scratch_bo == sctx->scratch_buffer)
2591 return 0;
2592
2593 assert(sctx->scratch_buffer);
2594
2595 si_shader_apply_scratch_relocs(sctx, shader, &shader->config, scratch_va);
2596
2597 /* Replace the shader bo with a new bo that has the relocs applied. */
2598 r = si_shader_binary_upload(sctx->screen, shader);
2599 if (r)
2600 return r;
2601
2602 /* Update the shader state to use the new shader bo. */
2603 si_shader_init_pm4_state(sctx->screen, shader);
2604
2605 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
2606
2607 return 1;
2608 }
2609
2610 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
2611 {
2612 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
2613 }
2614
2615 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
2616 {
2617 return shader ? shader->config.scratch_bytes_per_wave : 0;
2618 }
2619
2620 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
2621 {
2622 unsigned bytes = 0;
2623
2624 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
2625 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
2626 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
2627 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tcs_shader.current));
2628 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
2629 return bytes;
2630 }
2631
2632 static bool si_update_spi_tmpring_size(struct si_context *sctx)
2633 {
2634 unsigned current_scratch_buffer_size =
2635 si_get_current_scratch_buffer_size(sctx);
2636 unsigned scratch_bytes_per_wave =
2637 si_get_max_scratch_bytes_per_wave(sctx);
2638 unsigned scratch_needed_size = scratch_bytes_per_wave *
2639 sctx->scratch_waves;
2640 unsigned spi_tmpring_size;
2641 int r;
2642
2643 if (scratch_needed_size > 0) {
2644 if (scratch_needed_size > current_scratch_buffer_size) {
2645 /* Create a bigger scratch buffer */
2646 r600_resource_reference(&sctx->scratch_buffer, NULL);
2647
2648 sctx->scratch_buffer = (struct r600_resource*)
2649 r600_aligned_buffer_create(&sctx->screen->b.b,
2650 R600_RESOURCE_FLAG_UNMAPPABLE,
2651 PIPE_USAGE_DEFAULT,
2652 scratch_needed_size, 256);
2653 if (!sctx->scratch_buffer)
2654 return false;
2655
2656 si_mark_atom_dirty(sctx, &sctx->scratch_state);
2657 r600_context_add_resource_size(&sctx->b.b,
2658 &sctx->scratch_buffer->b.b);
2659 }
2660
2661 /* Update the shaders, so they are using the latest scratch. The
2662 * scratch buffer may have been changed since these shaders were
2663 * last used, so we still need to try to update them, even if
2664 * they require scratch buffers smaller than the current size.
2665 */
2666 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
2667 if (r < 0)
2668 return false;
2669 if (r == 1)
2670 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2671
2672 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
2673 if (r < 0)
2674 return false;
2675 if (r == 1)
2676 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2677
2678 r = si_update_scratch_buffer(sctx, sctx->tcs_shader.current);
2679 if (r < 0)
2680 return false;
2681 if (r == 1)
2682 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
2683
2684 /* VS can be bound as LS, ES, or VS. */
2685 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
2686 if (r < 0)
2687 return false;
2688 if (r == 1) {
2689 if (sctx->tes_shader.current)
2690 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2691 else if (sctx->gs_shader.current)
2692 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2693 else
2694 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2695 }
2696
2697 /* TES can be bound as ES or VS. */
2698 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
2699 if (r < 0)
2700 return false;
2701 if (r == 1) {
2702 if (sctx->gs_shader.current)
2703 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2704 else
2705 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2706 }
2707 }
2708
2709 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
2710 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
2711 "scratch size should already be aligned correctly.");
2712
2713 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
2714 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
2715 if (spi_tmpring_size != sctx->spi_tmpring_size) {
2716 sctx->spi_tmpring_size = spi_tmpring_size;
2717 si_mark_atom_dirty(sctx, &sctx->scratch_state);
2718 }
2719 return true;
2720 }
2721
2722 static void si_init_tess_factor_ring(struct si_context *sctx)
2723 {
2724 bool double_offchip_buffers = sctx->b.chip_class >= CIK &&
2725 sctx->b.family != CHIP_CARRIZO &&
2726 sctx->b.family != CHIP_STONEY;
2727 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2728 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
2729 sctx->screen->b.info.max_se;
2730 unsigned offchip_granularity;
2731
2732 switch (sctx->screen->tess_offchip_block_dw_size) {
2733 default:
2734 assert(0);
2735 /* fall through */
2736 case 8192:
2737 offchip_granularity = V_03093C_X_8K_DWORDS;
2738 break;
2739 case 4096:
2740 offchip_granularity = V_03093C_X_4K_DWORDS;
2741 break;
2742 }
2743
2744 switch (sctx->b.chip_class) {
2745 case SI:
2746 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2747 break;
2748 case CIK:
2749 case VI:
2750 case GFX9:
2751 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2752 break;
2753 default:
2754 assert(0);
2755 return;
2756 }
2757
2758 assert(!sctx->tf_ring);
2759 sctx->tf_ring = r600_aligned_buffer_create(sctx->b.b.screen,
2760 R600_RESOURCE_FLAG_UNMAPPABLE,
2761 PIPE_USAGE_DEFAULT,
2762 32768 * sctx->screen->b.info.max_se,
2763 256);
2764 if (!sctx->tf_ring)
2765 return;
2766
2767 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
2768
2769 sctx->tess_offchip_ring =
2770 r600_aligned_buffer_create(sctx->b.b.screen,
2771 R600_RESOURCE_FLAG_UNMAPPABLE,
2772 PIPE_USAGE_DEFAULT,
2773 max_offchip_buffers *
2774 sctx->screen->tess_offchip_block_dw_size * 4,
2775 256);
2776 if (!sctx->tess_offchip_ring)
2777 return;
2778
2779 si_init_config_add_vgt_flush(sctx);
2780
2781 /* Append these registers to the init config state. */
2782 if (sctx->b.chip_class >= CIK) {
2783 if (sctx->b.chip_class >= VI)
2784 --max_offchip_buffers;
2785
2786 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
2787 S_030938_SIZE(sctx->tf_ring->width0 / 4));
2788 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
2789 r600_resource(sctx->tf_ring)->gpu_address >> 8);
2790 if (sctx->b.chip_class >= GFX9)
2791 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
2792 r600_resource(sctx->tf_ring)->gpu_address >> 40);
2793 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
2794 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2795 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity));
2796 } else {
2797 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
2798 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
2799 S_008988_SIZE(sctx->tf_ring->width0 / 4));
2800 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
2801 r600_resource(sctx->tf_ring)->gpu_address >> 8);
2802 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2803 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers));
2804 }
2805
2806 /* Flush the context to re-emit the init_config state.
2807 * This is done only once in a lifetime of a context.
2808 */
2809 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2810 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2811 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2812
2813 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_FACTOR, sctx->tf_ring,
2814 0, sctx->tf_ring->width0, false, false, 0, 0, 0);
2815
2816 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_OFFCHIP,
2817 sctx->tess_offchip_ring, 0,
2818 sctx->tess_offchip_ring->width0, false, false, 0, 0, 0);
2819 }
2820
2821 /**
2822 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
2823 * VS passes its outputs to TES directly, so the fixed-function shader only
2824 * has to write TESSOUTER and TESSINNER.
2825 */
2826 static void si_generate_fixed_func_tcs(struct si_context *sctx)
2827 {
2828 struct ureg_src outer, inner;
2829 struct ureg_dst tessouter, tessinner;
2830 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
2831
2832 if (!ureg)
2833 return; /* if we get here, we're screwed */
2834
2835 assert(!sctx->fixed_func_tcs_shader.cso);
2836
2837 outer = ureg_DECL_system_value(ureg,
2838 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
2839 inner = ureg_DECL_system_value(ureg,
2840 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
2841
2842 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
2843 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
2844
2845 ureg_MOV(ureg, tessouter, outer);
2846 ureg_MOV(ureg, tessinner, inner);
2847 ureg_END(ureg);
2848
2849 sctx->fixed_func_tcs_shader.cso =
2850 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
2851 }
2852
2853 static void si_update_vgt_shader_config(struct si_context *sctx)
2854 {
2855 /* Calculate the index of the config.
2856 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
2857 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
2858 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
2859
2860 if (!*pm4) {
2861 uint32_t stages = 0;
2862
2863 *pm4 = CALLOC_STRUCT(si_pm4_state);
2864
2865 if (sctx->tes_shader.cso) {
2866 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2867 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2868
2869 if (sctx->gs_shader.cso)
2870 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2871 S_028B54_GS_EN(1) |
2872 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2873 else
2874 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2875 } else if (sctx->gs_shader.cso) {
2876 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2877 S_028B54_GS_EN(1) |
2878 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2879 }
2880
2881 if (sctx->b.chip_class >= GFX9)
2882 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2883
2884 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
2885 }
2886 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
2887 }
2888
2889 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
2890 {
2891 struct pipe_stream_output_info *so = &shader->so;
2892 uint32_t enabled_stream_buffers_mask = 0;
2893 int i;
2894
2895 for (i = 0; i < so->num_outputs; i++)
2896 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
2897 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
2898 sctx->b.streamout.stride_in_dw = shader->so.stride;
2899 }
2900
2901 bool si_update_shaders(struct si_context *sctx)
2902 {
2903 struct pipe_context *ctx = (struct pipe_context*)sctx;
2904 struct si_compiler_ctx_state compiler_state;
2905 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2906 struct si_shader *old_vs = si_get_vs_state(sctx);
2907 bool old_clip_disable = old_vs ? old_vs->key.opt.hw_vs.clip_disable : false;
2908 int r;
2909
2910 compiler_state.tm = sctx->tm;
2911 compiler_state.debug = sctx->b.debug;
2912 compiler_state.is_debug_context = sctx->is_debug;
2913
2914 /* Update stages before GS. */
2915 if (sctx->tes_shader.cso) {
2916 if (!sctx->tf_ring) {
2917 si_init_tess_factor_ring(sctx);
2918 if (!sctx->tf_ring)
2919 return false;
2920 }
2921
2922 /* VS as LS */
2923 if (sctx->b.chip_class <= VI) {
2924 r = si_shader_select(ctx, &sctx->vs_shader,
2925 &compiler_state);
2926 if (r)
2927 return false;
2928 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2929 }
2930
2931 if (sctx->tcs_shader.cso) {
2932 r = si_shader_select(ctx, &sctx->tcs_shader,
2933 &compiler_state);
2934 if (r)
2935 return false;
2936 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
2937 } else {
2938 if (!sctx->fixed_func_tcs_shader.cso) {
2939 si_generate_fixed_func_tcs(sctx);
2940 if (!sctx->fixed_func_tcs_shader.cso)
2941 return false;
2942 }
2943
2944 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
2945 &compiler_state);
2946 if (r)
2947 return false;
2948 si_pm4_bind_state(sctx, hs,
2949 sctx->fixed_func_tcs_shader.current->pm4);
2950 }
2951
2952 if (sctx->gs_shader.cso) {
2953 /* TES as ES */
2954 if (sctx->b.chip_class <= VI) {
2955 r = si_shader_select(ctx, &sctx->tes_shader,
2956 &compiler_state);
2957 if (r)
2958 return false;
2959 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2960 }
2961 } else {
2962 /* TES as VS */
2963 r = si_shader_select(ctx, &sctx->tes_shader,
2964 &compiler_state);
2965 if (r)
2966 return false;
2967 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2968 si_update_so(sctx, sctx->tes_shader.cso);
2969 }
2970 } else if (sctx->gs_shader.cso) {
2971 if (sctx->b.chip_class <= VI) {
2972 /* VS as ES */
2973 r = si_shader_select(ctx, &sctx->vs_shader,
2974 &compiler_state);
2975 if (r)
2976 return false;
2977 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2978
2979 si_pm4_bind_state(sctx, ls, NULL);
2980 si_pm4_bind_state(sctx, hs, NULL);
2981 }
2982 } else {
2983 /* VS as VS */
2984 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
2985 if (r)
2986 return false;
2987 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2988 si_update_so(sctx, sctx->vs_shader.cso);
2989
2990 si_pm4_bind_state(sctx, ls, NULL);
2991 si_pm4_bind_state(sctx, hs, NULL);
2992 }
2993
2994 /* Update GS. */
2995 if (sctx->gs_shader.cso) {
2996 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
2997 if (r)
2998 return false;
2999 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3000 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3001 si_update_so(sctx, sctx->gs_shader.cso);
3002
3003 if (!si_update_gs_ring_buffers(sctx))
3004 return false;
3005 } else {
3006 si_pm4_bind_state(sctx, gs, NULL);
3007 if (sctx->b.chip_class <= VI)
3008 si_pm4_bind_state(sctx, es, NULL);
3009 }
3010
3011 si_update_vgt_shader_config(sctx);
3012
3013 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.hw_vs.clip_disable)
3014 si_mark_atom_dirty(sctx, &sctx->clip_regs);
3015
3016 if (sctx->ps_shader.cso) {
3017 unsigned db_shader_control;
3018
3019 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
3020 if (r)
3021 return false;
3022 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3023
3024 db_shader_control =
3025 sctx->ps_shader.cso->db_shader_control |
3026 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3027
3028 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3029 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3030 sctx->flatshade != rs->flatshade) {
3031 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3032 sctx->flatshade = rs->flatshade;
3033 si_mark_atom_dirty(sctx, &sctx->spi_map);
3034 }
3035
3036 if (sctx->screen->b.rbplus_allowed && si_pm4_state_changed(sctx, ps))
3037 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
3038
3039 if (sctx->ps_db_shader_control != db_shader_control) {
3040 sctx->ps_db_shader_control = db_shader_control;
3041 si_mark_atom_dirty(sctx, &sctx->db_render_state);
3042 }
3043
3044 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3045 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3046 si_mark_atom_dirty(sctx, &sctx->msaa_config);
3047
3048 if (sctx->b.chip_class == SI)
3049 si_mark_atom_dirty(sctx, &sctx->db_render_state);
3050
3051 if (sctx->framebuffer.nr_samples <= 1)
3052 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
3053 }
3054 }
3055
3056 if (si_pm4_state_changed(sctx, ls) ||
3057 si_pm4_state_changed(sctx, hs) ||
3058 si_pm4_state_changed(sctx, es) ||
3059 si_pm4_state_changed(sctx, gs) ||
3060 si_pm4_state_changed(sctx, vs) ||
3061 si_pm4_state_changed(sctx, ps)) {
3062 if (!si_update_spi_tmpring_size(sctx))
3063 return false;
3064 }
3065
3066 if (sctx->b.chip_class >= CIK)
3067 si_mark_atom_dirty(sctx, &sctx->prefetch_L2);
3068
3069 sctx->do_update_shaders = false;
3070 return true;
3071 }
3072
3073 static void si_emit_scratch_state(struct si_context *sctx,
3074 struct r600_atom *atom)
3075 {
3076 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3077
3078 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3079 sctx->spi_tmpring_size);
3080
3081 if (sctx->scratch_buffer) {
3082 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
3083 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3084 RADEON_PRIO_SCRATCH_BUFFER);
3085 }
3086 }
3087
3088 void si_init_shader_functions(struct si_context *sctx)
3089 {
3090 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
3091 si_init_atom(sctx, &sctx->scratch_state, &sctx->atoms.s.scratch_state,
3092 si_emit_scratch_state);
3093
3094 sctx->b.b.create_vs_state = si_create_shader_selector;
3095 sctx->b.b.create_tcs_state = si_create_shader_selector;
3096 sctx->b.b.create_tes_state = si_create_shader_selector;
3097 sctx->b.b.create_gs_state = si_create_shader_selector;
3098 sctx->b.b.create_fs_state = si_create_shader_selector;
3099
3100 sctx->b.b.bind_vs_state = si_bind_vs_shader;
3101 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
3102 sctx->b.b.bind_tes_state = si_bind_tes_shader;
3103 sctx->b.b.bind_gs_state = si_bind_gs_shader;
3104 sctx->b.b.bind_fs_state = si_bind_ps_shader;
3105
3106 sctx->b.b.delete_vs_state = si_delete_shader_selector;
3107 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
3108 sctx->b.b.delete_tes_state = si_delete_shader_selector;
3109 sctx->b.b.delete_gs_state = si_delete_shader_selector;
3110 sctx->b.b.delete_fs_state = si_delete_shader_selector;
3111 }