2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
44 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
47 void *si_get_ir_binary(struct si_shader_selector
*sel
)
54 ir_binary
= sel
->tokens
;
55 ir_size
= tgsi_num_tokens(sel
->tokens
) *
56 sizeof(struct tgsi_token
);
61 nir_serialize(&blob
, sel
->nir
);
62 ir_binary
= blob
.data
;
66 unsigned size
= 4 + ir_size
+ sizeof(sel
->so
);
67 char *result
= (char*)MALLOC(size
);
71 *((uint32_t*)result
) = size
;
72 memcpy(result
+ 4, ir_binary
, ir_size
);
73 memcpy(result
+ 4 + ir_size
, &sel
->so
, sizeof(sel
->so
));
81 /** Copy "data" to "ptr" and return the next dword following copied data. */
82 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
84 /* data may be NULL if size == 0 */
86 memcpy(ptr
, data
, size
);
87 ptr
+= DIV_ROUND_UP(size
, 4);
91 /** Read data from "ptr". Return the next dword following the data. */
92 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
94 memcpy(data
, ptr
, size
);
95 ptr
+= DIV_ROUND_UP(size
, 4);
100 * Write the size as uint followed by the data. Return the next dword
101 * following the copied data.
103 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
106 return write_data(ptr
, data
, size
);
110 * Read the size as uint followed by the data. Return both via parameters.
111 * Return the next dword following the data.
113 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
116 assert(*data
== NULL
);
119 *data
= malloc(*size
);
120 return read_data(ptr
, *data
, *size
);
124 * Return the shader binary in a buffer. The first 4 bytes contain its size
127 static void *si_get_shader_binary(struct si_shader
*shader
)
129 /* There is always a size of data followed by the data itself. */
130 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
131 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
133 /* Refuse to allocate overly large buffers and guard against integer
135 if (shader
->binary
.elf_size
> UINT_MAX
/ 4 ||
136 llvm_ir_size
> UINT_MAX
/ 4)
141 4 + /* CRC32 of the data below */
142 align(sizeof(shader
->config
), 4) +
143 align(sizeof(shader
->info
), 4) +
144 4 + align(shader
->binary
.elf_size
, 4) +
145 4 + align(llvm_ir_size
, 4);
146 void *buffer
= CALLOC(1, size
);
147 uint32_t *ptr
= (uint32_t*)buffer
;
153 ptr
++; /* CRC32 is calculated at the end. */
155 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
156 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
157 ptr
= write_chunk(ptr
, shader
->binary
.elf_buffer
, shader
->binary
.elf_size
);
158 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
159 assert((char *)ptr
- (char *)buffer
== size
);
162 ptr
= (uint32_t*)buffer
;
164 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
169 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
171 uint32_t *ptr
= (uint32_t*)binary
;
172 uint32_t size
= *ptr
++;
173 uint32_t crc32
= *ptr
++;
177 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
178 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
182 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
183 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
184 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.elf_buffer
,
186 shader
->binary
.elf_size
= elf_size
;
187 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
193 * Insert a shader into the cache. It's assumed the shader is not in the cache.
194 * Use si_shader_cache_load_shader before calling this.
196 * Returns false on failure, in which case the ir_binary should be freed.
198 bool si_shader_cache_insert_shader(struct si_screen
*sscreen
, void *ir_binary
,
199 struct si_shader
*shader
,
200 bool insert_into_disk_cache
)
203 struct hash_entry
*entry
;
204 uint8_t key
[CACHE_KEY_SIZE
];
206 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
208 return false; /* already added */
210 hw_binary
= si_get_shader_binary(shader
);
214 if (_mesa_hash_table_insert(sscreen
->shader_cache
, ir_binary
,
215 hw_binary
) == NULL
) {
220 if (sscreen
->disk_shader_cache
&& insert_into_disk_cache
) {
221 disk_cache_compute_key(sscreen
->disk_shader_cache
, ir_binary
,
222 *((uint32_t *)ir_binary
), key
);
223 disk_cache_put(sscreen
->disk_shader_cache
, key
, hw_binary
,
224 *((uint32_t *) hw_binary
), NULL
);
230 bool si_shader_cache_load_shader(struct si_screen
*sscreen
, void *ir_binary
,
231 struct si_shader
*shader
)
233 struct hash_entry
*entry
=
234 _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
236 if (sscreen
->disk_shader_cache
) {
237 unsigned char sha1
[CACHE_KEY_SIZE
];
238 size_t tg_size
= *((uint32_t *) ir_binary
);
240 disk_cache_compute_key(sscreen
->disk_shader_cache
,
241 ir_binary
, tg_size
, sha1
);
245 disk_cache_get(sscreen
->disk_shader_cache
,
250 if (binary_size
< sizeof(uint32_t) ||
251 *((uint32_t*)buffer
) != binary_size
) {
252 /* Something has gone wrong discard the item
253 * from the cache and rebuild/link from
256 assert(!"Invalid radeonsi shader disk cache "
259 disk_cache_remove(sscreen
->disk_shader_cache
,
266 if (!si_load_shader_binary(shader
, buffer
)) {
272 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
,
279 if (si_load_shader_binary(shader
, entry
->data
))
284 p_atomic_inc(&sscreen
->num_shader_cache_hits
);
288 static uint32_t si_shader_cache_key_hash(const void *key
)
290 /* The first dword is the key size. */
291 return util_hash_crc32(key
, *(uint32_t*)key
);
294 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
296 uint32_t *keya
= (uint32_t*)a
;
297 uint32_t *keyb
= (uint32_t*)b
;
299 /* The first dword is the key size. */
303 return memcmp(keya
, keyb
, *keya
) == 0;
306 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
308 FREE((void*)entry
->key
);
312 bool si_init_shader_cache(struct si_screen
*sscreen
)
314 (void) mtx_init(&sscreen
->shader_cache_mutex
, mtx_plain
);
315 sscreen
->shader_cache
=
316 _mesa_hash_table_create(NULL
,
317 si_shader_cache_key_hash
,
318 si_shader_cache_key_equals
);
320 return sscreen
->shader_cache
!= NULL
;
323 void si_destroy_shader_cache(struct si_screen
*sscreen
)
325 if (sscreen
->shader_cache
)
326 _mesa_hash_table_destroy(sscreen
->shader_cache
,
327 si_destroy_shader_cache_entry
);
328 mtx_destroy(&sscreen
->shader_cache_mutex
);
333 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
334 const struct si_shader_selector
*tes
,
335 struct si_pm4_state
*pm4
)
337 const struct tgsi_shader_info
*info
= &tes
->info
;
338 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
339 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
340 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
341 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
342 unsigned type
, partitioning
, topology
, distribution_mode
;
344 switch (tes_prim_mode
) {
345 case PIPE_PRIM_LINES
:
346 type
= V_028B6C_TESS_ISOLINE
;
348 case PIPE_PRIM_TRIANGLES
:
349 type
= V_028B6C_TESS_TRIANGLE
;
351 case PIPE_PRIM_QUADS
:
352 type
= V_028B6C_TESS_QUAD
;
359 switch (tes_spacing
) {
360 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
361 partitioning
= V_028B6C_PART_FRAC_ODD
;
363 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
364 partitioning
= V_028B6C_PART_FRAC_EVEN
;
366 case PIPE_TESS_SPACING_EQUAL
:
367 partitioning
= V_028B6C_PART_INTEGER
;
375 topology
= V_028B6C_OUTPUT_POINT
;
376 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
377 topology
= V_028B6C_OUTPUT_LINE
;
378 else if (tes_vertex_order_cw
)
379 /* for some reason, this must be the other way around */
380 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
382 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
384 if (sscreen
->has_distributed_tess
) {
385 if (sscreen
->info
.family
== CHIP_FIJI
||
386 sscreen
->info
.family
>= CHIP_POLARIS10
)
387 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
389 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
391 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
394 pm4
->shader
->vgt_tf_param
= S_028B6C_TYPE(type
) |
395 S_028B6C_PARTITIONING(partitioning
) |
396 S_028B6C_TOPOLOGY(topology
) |
397 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
400 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
401 * whether the "fractional odd" tessellation spacing is used.
403 * Possible VGT configurations and which state should set the register:
405 * Reg set in | VGT shader configuration | Value
406 * ------------------------------------------------------
408 * VS as ES | ES -> GS -> VS | 30
409 * TES as VS | LS -> HS -> VS | 14 or 30
410 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
412 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
414 static void polaris_set_vgt_vertex_reuse(struct si_screen
*sscreen
,
415 struct si_shader_selector
*sel
,
416 struct si_shader
*shader
,
417 struct si_pm4_state
*pm4
)
419 unsigned type
= sel
->type
;
421 if (sscreen
->info
.family
< CHIP_POLARIS10
)
424 /* VS as VS, or VS as ES: */
425 if ((type
== PIPE_SHADER_VERTEX
&&
427 (!shader
->key
.as_ls
&& !shader
->is_gs_copy_shader
))) ||
428 /* TES as VS, or TES as ES: */
429 type
== PIPE_SHADER_TESS_EVAL
) {
430 unsigned vtx_reuse_depth
= 30;
432 if (type
== PIPE_SHADER_TESS_EVAL
&&
433 sel
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] ==
434 PIPE_TESS_SPACING_FRACTIONAL_ODD
)
435 vtx_reuse_depth
= 14;
438 pm4
->shader
->vgt_vertex_reuse_block_cntl
= vtx_reuse_depth
;
442 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
445 si_pm4_clear_state(shader
->pm4
);
447 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
450 shader
->pm4
->shader
= shader
;
453 fprintf(stderr
, "radeonsi: Failed to create pm4 state.\n");
458 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs
)
460 /* Add the pointer to VBO descriptors. */
461 return num_always_on_user_sgprs
+ 1;
464 static void si_shader_ls(struct si_screen
*sscreen
, struct si_shader
*shader
)
466 struct si_pm4_state
*pm4
;
467 unsigned vgpr_comp_cnt
;
470 assert(sscreen
->info
.chip_class
<= GFX8
);
472 pm4
= si_get_shader_pm4_state(shader
);
476 va
= shader
->bo
->gpu_address
;
477 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
479 /* We need at least 2 components for LS.
480 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
481 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
483 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
485 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
486 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
488 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
489 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
490 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt
) |
491 S_00B528_DX10_CLAMP(1) |
492 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
493 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
)) |
494 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
497 static void si_shader_hs(struct si_screen
*sscreen
, struct si_shader
*shader
)
499 struct si_pm4_state
*pm4
;
501 unsigned ls_vgpr_comp_cnt
= 0;
503 pm4
= si_get_shader_pm4_state(shader
);
507 va
= shader
->bo
->gpu_address
;
508 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
510 if (sscreen
->info
.chip_class
>= GFX9
) {
511 si_pm4_set_reg(pm4
, R_00B410_SPI_SHADER_PGM_LO_LS
, va
>> 8);
512 si_pm4_set_reg(pm4
, R_00B414_SPI_SHADER_PGM_HI_LS
, S_00B414_MEM_BASE(va
>> 40));
514 /* We need at least 2 components for LS.
515 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
516 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
518 ls_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
520 unsigned num_user_sgprs
=
521 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR
);
523 shader
->config
.rsrc2
=
524 S_00B42C_USER_SGPR(num_user_sgprs
) |
525 S_00B42C_USER_SGPR_MSB(num_user_sgprs
>> 5) |
526 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
528 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
529 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, S_00B424_MEM_BASE(va
>> 40));
531 shader
->config
.rsrc2
=
532 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR
) |
533 S_00B42C_OC_LDS_EN(1) |
534 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
537 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
538 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
539 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
540 S_00B428_DX10_CLAMP(1) |
541 S_00B428_FLOAT_MODE(shader
->config
.float_mode
) |
542 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt
));
544 if (sscreen
->info
.chip_class
<= GFX8
) {
545 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
546 shader
->config
.rsrc2
);
550 static void si_emit_shader_es(struct si_context
*sctx
)
552 struct si_shader
*shader
= sctx
->queued
.named
.es
->shader
;
553 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
558 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
559 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
560 shader
->selector
->esgs_itemsize
/ 4);
562 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
563 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
564 SI_TRACKED_VGT_TF_PARAM
,
565 shader
->vgt_tf_param
);
567 if (shader
->vgt_vertex_reuse_block_cntl
)
568 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
569 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
570 shader
->vgt_vertex_reuse_block_cntl
);
572 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
573 sctx
->context_roll
= true;
576 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
578 struct si_pm4_state
*pm4
;
579 unsigned num_user_sgprs
;
580 unsigned vgpr_comp_cnt
;
584 assert(sscreen
->info
.chip_class
<= GFX8
);
586 pm4
= si_get_shader_pm4_state(shader
);
590 pm4
->atom
.emit
= si_emit_shader_es
;
591 va
= shader
->bo
->gpu_address
;
592 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
594 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
595 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
596 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
597 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
598 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
599 vgpr_comp_cnt
= shader
->selector
->info
.uses_primid
? 3 : 2;
600 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
602 unreachable("invalid shader selector type");
604 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
606 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
607 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
608 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
609 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
610 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
611 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
612 S_00B328_DX10_CLAMP(1) |
613 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
614 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
615 S_00B32C_USER_SGPR(num_user_sgprs
) |
616 S_00B32C_OC_LDS_EN(oc_lds_en
) |
617 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
619 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
620 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
622 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
625 static unsigned si_conv_prim_to_gs_out(unsigned mode
)
627 static const int prim_conv
[] = {
628 [PIPE_PRIM_POINTS
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
629 [PIPE_PRIM_LINES
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
630 [PIPE_PRIM_LINE_LOOP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
631 [PIPE_PRIM_LINE_STRIP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
632 [PIPE_PRIM_TRIANGLES
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
633 [PIPE_PRIM_TRIANGLE_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
634 [PIPE_PRIM_TRIANGLE_FAN
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
635 [PIPE_PRIM_QUADS
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
636 [PIPE_PRIM_QUAD_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
637 [PIPE_PRIM_POLYGON
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
638 [PIPE_PRIM_LINES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
639 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
640 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
641 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
642 [PIPE_PRIM_PATCHES
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
644 assert(mode
< ARRAY_SIZE(prim_conv
));
646 return prim_conv
[mode
];
649 struct gfx9_gs_info
{
650 unsigned es_verts_per_subgroup
;
651 unsigned gs_prims_per_subgroup
;
652 unsigned gs_inst_prims_in_subgroup
;
653 unsigned max_prims_per_subgroup
;
657 static void gfx9_get_gs_info(struct si_shader_selector
*es
,
658 struct si_shader_selector
*gs
,
659 struct gfx9_gs_info
*out
)
661 unsigned gs_num_invocations
= MAX2(gs
->gs_num_invocations
, 1);
662 unsigned input_prim
= gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
663 bool uses_adjacency
= input_prim
>= PIPE_PRIM_LINES_ADJACENCY
&&
664 input_prim
<= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
;
666 /* All these are in dwords: */
667 /* We can't allow using the whole LDS, because GS waves compete with
668 * other shader stages for LDS space. */
669 const unsigned max_lds_size
= 8 * 1024;
670 const unsigned esgs_itemsize
= es
->esgs_itemsize
/ 4;
671 unsigned esgs_lds_size
;
673 /* All these are per subgroup: */
674 const unsigned max_out_prims
= 32 * 1024;
675 const unsigned max_es_verts
= 255;
676 const unsigned ideal_gs_prims
= 64;
677 unsigned max_gs_prims
, gs_prims
;
678 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
680 if (uses_adjacency
|| gs_num_invocations
> 1)
681 max_gs_prims
= 127 / gs_num_invocations
;
685 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
686 * Make sure we don't go over the maximum value.
688 if (gs
->gs_max_out_vertices
> 0) {
689 max_gs_prims
= MIN2(max_gs_prims
,
691 (gs
->gs_max_out_vertices
* gs_num_invocations
));
693 assert(max_gs_prims
> 0);
695 /* If the primitive has adjacency, halve the number of vertices
696 * that will be reused in multiple primitives.
698 min_es_verts
= gs
->gs_input_verts_per_prim
/ (uses_adjacency
? 2 : 1);
700 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
701 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
703 /* Compute ESGS LDS size based on the worst case number of ES vertices
704 * needed to create the target number of GS prims per subgroup.
706 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
708 /* If total LDS usage is too big, refactor partitions based on ratio
709 * of ESGS item sizes.
711 if (esgs_lds_size
> max_lds_size
) {
712 /* Our target GS Prims Per Subgroup was too large. Calculate
713 * the maximum number of GS Prims Per Subgroup that will fit
714 * into LDS, capped by the maximum that the hardware can support.
716 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
718 assert(gs_prims
> 0);
719 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
722 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
723 assert(esgs_lds_size
<= max_lds_size
);
726 /* Now calculate remaining ESGS information. */
728 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
730 es_verts
= max_es_verts
;
732 /* Vertices for adjacency primitives are not always reused, so restore
733 * it for ES_VERTS_PER_SUBGRP.
735 min_es_verts
= gs
->gs_input_verts_per_prim
;
737 /* For normal primitives, the VGT only checks if they are past the ES
738 * verts per subgroup after allocating a full GS primitive and if they
739 * are, kick off a new subgroup. But if those additional ES verts are
740 * unique (e.g. not reused) we need to make sure there is enough LDS
741 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
743 es_verts
-= min_es_verts
- 1;
745 out
->es_verts_per_subgroup
= es_verts
;
746 out
->gs_prims_per_subgroup
= gs_prims
;
747 out
->gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
748 out
->max_prims_per_subgroup
= out
->gs_inst_prims_in_subgroup
*
749 gs
->gs_max_out_vertices
;
750 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
752 assert(out
->max_prims_per_subgroup
<= max_out_prims
);
755 static void si_emit_shader_gs(struct si_context
*sctx
)
757 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
758 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
763 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
764 * R_028A68_VGT_GSVS_RING_OFFSET_3, R_028A6C_VGT_GS_OUT_PRIM_TYPE */
765 radeon_opt_set_context_reg4(sctx
, R_028A60_VGT_GSVS_RING_OFFSET_1
,
766 SI_TRACKED_VGT_GSVS_RING_OFFSET_1
,
767 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
,
768 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
,
769 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
,
770 shader
->ctx_reg
.gs
.vgt_gs_out_prim_type
);
773 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
774 radeon_opt_set_context_reg(sctx
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
,
775 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE
,
776 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
);
778 /* R_028B38_VGT_GS_MAX_VERT_OUT */
779 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
780 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
781 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
);
783 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
784 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
785 radeon_opt_set_context_reg4(sctx
, R_028B5C_VGT_GS_VERT_ITEMSIZE
,
786 SI_TRACKED_VGT_GS_VERT_ITEMSIZE
,
787 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
,
788 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
,
789 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
,
790 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
);
792 /* R_028B90_VGT_GS_INSTANCE_CNT */
793 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
,
794 SI_TRACKED_VGT_GS_INSTANCE_CNT
,
795 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
);
797 if (sctx
->chip_class
>= GFX9
) {
798 /* R_028A44_VGT_GS_ONCHIP_CNTL */
799 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
800 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
801 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
);
802 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
803 radeon_opt_set_context_reg(sctx
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
804 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
805 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
);
806 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
807 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
808 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
809 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
);
811 if (shader
->key
.part
.gs
.es
->type
== PIPE_SHADER_TESS_EVAL
)
812 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
813 SI_TRACKED_VGT_TF_PARAM
,
814 shader
->vgt_tf_param
);
815 if (shader
->vgt_vertex_reuse_block_cntl
)
816 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
817 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
818 shader
->vgt_vertex_reuse_block_cntl
);
821 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
822 sctx
->context_roll
= true;
825 static void si_shader_gs(struct si_screen
*sscreen
, struct si_shader
*shader
)
827 struct si_shader_selector
*sel
= shader
->selector
;
828 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
829 unsigned gs_num_invocations
= sel
->gs_num_invocations
;
830 struct si_pm4_state
*pm4
;
832 unsigned max_stream
= sel
->max_gs_stream
;
835 pm4
= si_get_shader_pm4_state(shader
);
839 pm4
->atom
.emit
= si_emit_shader_gs
;
841 offset
= num_components
[0] * sel
->gs_max_out_vertices
;
842 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
= offset
;
845 offset
+= num_components
[1] * sel
->gs_max_out_vertices
;
846 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
= offset
;
849 offset
+= num_components
[2] * sel
->gs_max_out_vertices
;
850 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
= offset
;
852 shader
->ctx_reg
.gs
.vgt_gs_out_prim_type
=
853 si_conv_prim_to_gs_out(sel
->gs_output_prim
);
856 offset
+= num_components
[3] * sel
->gs_max_out_vertices
;
857 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
= offset
;
859 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
860 assert(offset
< (1 << 15));
862 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
= sel
->gs_max_out_vertices
;
864 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
= num_components
[0];
865 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
= (max_stream
>= 1) ? num_components
[1] : 0;
866 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
= (max_stream
>= 2) ? num_components
[2] : 0;
867 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
= (max_stream
>= 3) ? num_components
[3] : 0;
869 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
= S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
870 S_028B90_ENABLE(gs_num_invocations
> 0);
872 va
= shader
->bo
->gpu_address
;
873 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
875 if (sscreen
->info
.chip_class
>= GFX9
) {
876 unsigned input_prim
= sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
877 unsigned es_type
= shader
->key
.part
.gs
.es
->type
;
878 unsigned es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
879 struct gfx9_gs_info gs_info
;
881 if (es_type
== PIPE_SHADER_VERTEX
)
882 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
883 es_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
884 else if (es_type
== PIPE_SHADER_TESS_EVAL
)
885 es_vgpr_comp_cnt
= shader
->key
.part
.gs
.es
->info
.uses_primid
? 3 : 2;
887 unreachable("invalid shader selector type");
889 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
890 * VGPR[0:4] are always loaded.
892 if (sel
->info
.uses_invocationid
)
893 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
894 else if (sel
->info
.uses_primid
)
895 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
896 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
897 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
899 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
901 unsigned num_user_sgprs
;
902 if (es_type
== PIPE_SHADER_VERTEX
)
903 num_user_sgprs
= si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR
);
905 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
907 gfx9_get_gs_info(shader
->key
.part
.gs
.es
, sel
, &gs_info
);
909 si_pm4_set_reg(pm4
, R_00B210_SPI_SHADER_PGM_LO_ES
, va
>> 8);
910 si_pm4_set_reg(pm4
, R_00B214_SPI_SHADER_PGM_HI_ES
, S_00B214_MEM_BASE(va
>> 40));
912 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
913 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
914 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
915 S_00B228_DX10_CLAMP(1) |
916 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
917 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
));
918 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
919 S_00B22C_USER_SGPR(num_user_sgprs
) |
920 S_00B22C_USER_SGPR_MSB(num_user_sgprs
>> 5) |
921 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
922 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
923 S_00B22C_LDS_SIZE(gs_info
.lds_size
) |
924 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
926 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
=
927 S_028A44_ES_VERTS_PER_SUBGRP(gs_info
.es_verts_per_subgroup
) |
928 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info
.gs_prims_per_subgroup
) |
929 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info
.gs_inst_prims_in_subgroup
);
930 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
=
931 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info
.max_prims_per_subgroup
);
932 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
=
933 shader
->key
.part
.gs
.es
->esgs_itemsize
/ 4;
935 if (es_type
== PIPE_SHADER_TESS_EVAL
)
936 si_set_tesseval_regs(sscreen
, shader
->key
.part
.gs
.es
, pm4
);
938 polaris_set_vgt_vertex_reuse(sscreen
, shader
->key
.part
.gs
.es
,
941 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
942 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, S_00B224_MEM_BASE(va
>> 40));
944 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
945 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
946 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
947 S_00B228_DX10_CLAMP(1) |
948 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
949 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
950 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR
) |
951 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
955 static void si_emit_shader_vs(struct si_context
*sctx
)
957 struct si_shader
*shader
= sctx
->queued
.named
.vs
->shader
;
958 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
963 radeon_opt_set_context_reg(sctx
, R_028A40_VGT_GS_MODE
,
964 SI_TRACKED_VGT_GS_MODE
,
965 shader
->ctx_reg
.vs
.vgt_gs_mode
);
966 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
,
967 SI_TRACKED_VGT_PRIMITIVEID_EN
,
968 shader
->ctx_reg
.vs
.vgt_primitiveid_en
);
970 if (sctx
->chip_class
<= GFX8
) {
971 radeon_opt_set_context_reg(sctx
, R_028AB4_VGT_REUSE_OFF
,
972 SI_TRACKED_VGT_REUSE_OFF
,
973 shader
->ctx_reg
.vs
.vgt_reuse_off
);
976 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
,
977 SI_TRACKED_SPI_VS_OUT_CONFIG
,
978 shader
->ctx_reg
.vs
.spi_vs_out_config
);
980 radeon_opt_set_context_reg(sctx
, R_02870C_SPI_SHADER_POS_FORMAT
,
981 SI_TRACKED_SPI_SHADER_POS_FORMAT
,
982 shader
->ctx_reg
.vs
.spi_shader_pos_format
);
984 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
,
985 SI_TRACKED_PA_CL_VTE_CNTL
,
986 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
);
988 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
989 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
990 SI_TRACKED_VGT_TF_PARAM
,
991 shader
->vgt_tf_param
);
993 if (shader
->vgt_vertex_reuse_block_cntl
)
994 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
995 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
996 shader
->vgt_vertex_reuse_block_cntl
);
998 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
999 sctx
->context_roll
= true;
1003 * Compute the state for \p shader, which will run as a vertex shader on the
1006 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1007 * is the copy shader.
1009 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
1010 struct si_shader_selector
*gs
)
1012 const struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1013 struct si_pm4_state
*pm4
;
1014 unsigned num_user_sgprs
, vgpr_comp_cnt
;
1016 unsigned nparams
, oc_lds_en
;
1017 unsigned window_space
=
1018 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
1019 bool enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| info
->uses_primid
;
1021 pm4
= si_get_shader_pm4_state(shader
);
1025 pm4
->atom
.emit
= si_emit_shader_vs
;
1027 /* We always write VGT_GS_MODE in the VS state, because every switch
1028 * between different shader pipelines involving a different GS or no
1029 * GS at all involves a switch of the VS (different GS use different
1030 * copy shaders). On the other hand, when the API switches from a GS to
1031 * no GS and then back to the same GS used originally, the GS state is
1035 unsigned mode
= V_028A40_GS_OFF
;
1037 /* PrimID needs GS scenario A. */
1039 mode
= V_028A40_GS_SCENARIO_A
;
1041 shader
->ctx_reg
.vs
.vgt_gs_mode
= S_028A40_MODE(mode
);
1042 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= enable_prim_id
;
1044 shader
->ctx_reg
.vs
.vgt_gs_mode
= ac_vgt_gs_mode(gs
->gs_max_out_vertices
,
1045 sscreen
->info
.chip_class
);
1046 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= 0;
1049 if (sscreen
->info
.chip_class
<= GFX8
) {
1050 /* Reuse needs to be set off if we write oViewport. */
1051 shader
->ctx_reg
.vs
.vgt_reuse_off
=
1052 S_028AB4_REUSE_OFF(info
->writes_viewport_index
);
1055 va
= shader
->bo
->gpu_address
;
1056 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1059 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
1060 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
1061 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
1062 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1063 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1064 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1066 vgpr_comp_cnt
= enable_prim_id
? 2 : (shader
->info
.uses_instanceid
? 1 : 0);
1068 if (info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
]) {
1069 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
1070 info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
1072 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
1074 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
1075 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
1076 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
1078 unreachable("invalid shader selector type");
1080 /* VS is required to export at least one param. */
1081 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1082 shader
->ctx_reg
.vs
.spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
1084 shader
->ctx_reg
.vs
.spi_shader_pos_format
=
1085 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1086 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
1087 V_02870C_SPI_SHADER_4COMP
:
1088 V_02870C_SPI_SHADER_NONE
) |
1089 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
1090 V_02870C_SPI_SHADER_4COMP
:
1091 V_02870C_SPI_SHADER_NONE
) |
1092 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
1093 V_02870C_SPI_SHADER_4COMP
:
1094 V_02870C_SPI_SHADER_NONE
);
1096 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
1098 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
1099 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, S_00B124_MEM_BASE(va
>> 40));
1100 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
1101 S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1102 S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
1103 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
1104 S_00B128_DX10_CLAMP(1) |
1105 S_00B128_FLOAT_MODE(shader
->config
.float_mode
));
1106 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
1107 S_00B12C_USER_SGPR(num_user_sgprs
) |
1108 S_00B12C_OC_LDS_EN(oc_lds_en
) |
1109 S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
1110 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
1111 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
1112 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
1113 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
) |
1114 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1117 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1118 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1120 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1121 S_028818_VTX_W0_FMT(1) |
1122 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1123 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1124 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1126 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
1127 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
1129 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
1132 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
1134 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
1135 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
1136 !!(info
->colors_read
& 0xf0);
1137 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
1138 (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
1140 assert(num_interp
<= 32);
1141 return MIN2(num_interp
, 32);
1144 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
1146 unsigned value
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
1147 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
1149 /* If the i-th target format is set, all previous target formats must
1150 * be non-zero to avoid hangs.
1152 for (i
= 0; i
< num_targets
; i
++)
1153 if (!(value
& (0xf << (i
* 4))))
1154 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
1159 static void si_emit_shader_ps(struct si_context
*sctx
)
1161 struct si_shader
*shader
= sctx
->queued
.named
.ps
->shader
;
1162 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1167 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1168 radeon_opt_set_context_reg2(sctx
, R_0286CC_SPI_PS_INPUT_ENA
,
1169 SI_TRACKED_SPI_PS_INPUT_ENA
,
1170 shader
->ctx_reg
.ps
.spi_ps_input_ena
,
1171 shader
->ctx_reg
.ps
.spi_ps_input_addr
);
1173 radeon_opt_set_context_reg(sctx
, R_0286E0_SPI_BARYC_CNTL
,
1174 SI_TRACKED_SPI_BARYC_CNTL
,
1175 shader
->ctx_reg
.ps
.spi_baryc_cntl
);
1176 radeon_opt_set_context_reg(sctx
, R_0286D8_SPI_PS_IN_CONTROL
,
1177 SI_TRACKED_SPI_PS_IN_CONTROL
,
1178 shader
->ctx_reg
.ps
.spi_ps_in_control
);
1180 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1181 radeon_opt_set_context_reg2(sctx
, R_028710_SPI_SHADER_Z_FORMAT
,
1182 SI_TRACKED_SPI_SHADER_Z_FORMAT
,
1183 shader
->ctx_reg
.ps
.spi_shader_z_format
,
1184 shader
->ctx_reg
.ps
.spi_shader_col_format
);
1186 radeon_opt_set_context_reg(sctx
, R_02823C_CB_SHADER_MASK
,
1187 SI_TRACKED_CB_SHADER_MASK
,
1188 shader
->ctx_reg
.ps
.cb_shader_mask
);
1190 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1191 sctx
->context_roll
= true;
1194 static void si_shader_ps(struct si_shader
*shader
)
1196 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1197 struct si_pm4_state
*pm4
;
1198 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
1199 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
1201 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
1203 /* we need to enable at least one of them, otherwise we hang the GPU */
1204 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1205 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1206 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1207 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
1208 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
1209 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1210 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
1211 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
1212 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1213 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
1214 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1215 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1216 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1217 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
1219 /* Validate interpolation optimization flags (read as implications). */
1220 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1221 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1222 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1223 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1224 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1225 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1226 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
1227 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
1228 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1229 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
1230 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
1231 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1232 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
1233 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1234 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1235 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
1236 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1237 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1239 /* Validate cases when the optimizations are off (read as implications). */
1240 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1241 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1242 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
1243 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1244 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1245 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
1247 pm4
= si_get_shader_pm4_state(shader
);
1251 pm4
->atom
.emit
= si_emit_shader_ps
;
1253 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1255 * 0 -> Position = pixel center
1256 * 1 -> Position = pixel centroid
1257 * 2 -> Position = at sample position
1259 * From GLSL 4.5 specification, section 7.1:
1260 * "The variable gl_FragCoord is available as an input variable from
1261 * within fragment shaders and it holds the window relative coordinates
1262 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1263 * value can be for any location within the pixel, or one of the
1264 * fragment samples. The use of centroid does not further restrict
1265 * this value to be inside the current primitive."
1267 * Meaning that centroid has no effect and we can return anything within
1268 * the pixel. Thus, return the value at sample position, because that's
1269 * the most accurate one shaders can get.
1271 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1273 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
1274 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
1275 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
1277 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
1278 cb_shader_mask
= ac_get_cb_shader_mask(spi_shader_col_format
);
1280 /* Ensure that some export memory is always allocated, for two reasons:
1282 * 1) Correctness: The hardware ignores the EXEC mask if no export
1283 * memory is allocated, so KILL and alpha test do not work correctly
1285 * 2) Performance: Every shader needs at least a NULL export, even when
1286 * it writes no color/depth output. The NULL export instruction
1287 * stalls without this setting.
1289 * Don't add this to CB_SHADER_MASK.
1291 if (!spi_shader_col_format
&&
1292 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
1293 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
1295 shader
->ctx_reg
.ps
.spi_ps_input_ena
= input_ena
;
1296 shader
->ctx_reg
.ps
.spi_ps_input_addr
= shader
->config
.spi_ps_input_addr
;
1298 /* Set interpolation controls. */
1299 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
));
1301 shader
->ctx_reg
.ps
.spi_baryc_cntl
= spi_baryc_cntl
;
1302 shader
->ctx_reg
.ps
.spi_ps_in_control
= spi_ps_in_control
;
1303 shader
->ctx_reg
.ps
.spi_shader_z_format
=
1304 ac_get_spi_shader_z_format(info
->writes_z
,
1305 info
->writes_stencil
,
1306 info
->writes_samplemask
);
1307 shader
->ctx_reg
.ps
.spi_shader_col_format
= spi_shader_col_format
;
1308 shader
->ctx_reg
.ps
.cb_shader_mask
= cb_shader_mask
;
1310 va
= shader
->bo
->gpu_address
;
1311 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1312 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
1313 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, S_00B024_MEM_BASE(va
>> 40));
1315 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
,
1316 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1317 S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
1318 S_00B028_DX10_CLAMP(1) |
1319 S_00B028_FLOAT_MODE(shader
->config
.float_mode
));
1320 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
1321 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
1322 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
1323 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1326 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
1327 struct si_shader
*shader
)
1329 switch (shader
->selector
->type
) {
1330 case PIPE_SHADER_VERTEX
:
1331 if (shader
->key
.as_ls
)
1332 si_shader_ls(sscreen
, shader
);
1333 else if (shader
->key
.as_es
)
1334 si_shader_es(sscreen
, shader
);
1336 si_shader_vs(sscreen
, shader
, NULL
);
1338 case PIPE_SHADER_TESS_CTRL
:
1339 si_shader_hs(sscreen
, shader
);
1341 case PIPE_SHADER_TESS_EVAL
:
1342 if (shader
->key
.as_es
)
1343 si_shader_es(sscreen
, shader
);
1345 si_shader_vs(sscreen
, shader
, NULL
);
1347 case PIPE_SHADER_GEOMETRY
:
1348 si_shader_gs(sscreen
, shader
);
1350 case PIPE_SHADER_FRAGMENT
:
1351 si_shader_ps(shader
);
1358 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
1360 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1361 if (sctx
->queued
.named
.dsa
)
1362 return sctx
->queued
.named
.dsa
->alpha_func
;
1364 return PIPE_FUNC_ALWAYS
;
1367 void si_shader_selector_key_vs(struct si_context
*sctx
,
1368 struct si_shader_selector
*vs
,
1369 struct si_shader_key
*key
,
1370 struct si_vs_prolog_bits
*prolog_key
)
1372 if (!sctx
->vertex_elements
||
1373 vs
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
])
1376 struct si_vertex_elements
*elts
= sctx
->vertex_elements
;
1378 prolog_key
->instance_divisor_is_one
= elts
->instance_divisor_is_one
;
1379 prolog_key
->instance_divisor_is_fetched
= elts
->instance_divisor_is_fetched
;
1380 prolog_key
->unpack_instance_id_from_vertex_id
=
1381 sctx
->prim_discard_cs_instancing
;
1383 /* Prefer a monolithic shader to allow scheduling divisions around
1385 if (prolog_key
->instance_divisor_is_fetched
)
1386 key
->opt
.prefer_mono
= 1;
1388 unsigned count
= MIN2(vs
->info
.num_inputs
, elts
->count
);
1389 unsigned count_mask
= (1 << count
) - 1;
1390 unsigned fix
= elts
->fix_fetch_always
& count_mask
;
1391 unsigned opencode
= elts
->fix_fetch_opencode
& count_mask
;
1393 if (sctx
->vertex_buffer_unaligned
& elts
->vb_alignment_check_mask
) {
1394 uint32_t mask
= elts
->fix_fetch_unaligned
& count_mask
;
1396 unsigned i
= u_bit_scan(&mask
);
1397 unsigned log_hw_load_size
= 1 + ((elts
->hw_load_is_dword
>> i
) & 1);
1398 unsigned vbidx
= elts
->vertex_buffer_index
[i
];
1399 struct pipe_vertex_buffer
*vb
= &sctx
->vertex_buffer
[vbidx
];
1400 unsigned align_mask
= (1 << log_hw_load_size
) - 1;
1401 if (vb
->buffer_offset
& align_mask
||
1402 vb
->stride
& align_mask
) {
1410 unsigned i
= u_bit_scan(&fix
);
1411 key
->mono
.vs_fix_fetch
[i
].bits
= elts
->fix_fetch
[i
];
1413 key
->mono
.vs_fetch_opencode
= opencode
;
1416 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
,
1417 struct si_shader_selector
*vs
,
1418 struct si_shader_key
*key
)
1420 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1422 key
->opt
.clip_disable
=
1423 sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
1424 (vs
->info
.clipdist_writemask
||
1425 vs
->info
.writes_clipvertex
) &&
1426 !vs
->info
.culldist_writemask
;
1428 /* Find out if PS is disabled. */
1429 bool ps_disabled
= true;
1431 const struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1432 bool alpha_to_coverage
= blend
&& blend
->alpha_to_coverage
;
1433 bool ps_modifies_zs
= ps
->info
.uses_kill
||
1434 ps
->info
.writes_z
||
1435 ps
->info
.writes_stencil
||
1436 ps
->info
.writes_samplemask
||
1437 alpha_to_coverage
||
1438 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
1439 unsigned ps_colormask
= si_get_total_colormask(sctx
);
1441 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
1444 !ps
->info
.writes_memory
);
1447 /* Find out which VS outputs aren't used by the PS. */
1448 uint64_t outputs_written
= vs
->outputs_written_before_ps
;
1449 uint64_t inputs_read
= 0;
1451 /* Ignore outputs that are not passed from VS to PS. */
1452 outputs_written
&= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION
, 0, true)) |
1453 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE
, 0, true)) |
1454 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX
, 0, true)));
1457 inputs_read
= ps
->inputs_read
;
1460 uint64_t linked
= outputs_written
& inputs_read
;
1462 key
->opt
.kill_outputs
= ~linked
& outputs_written
;
1465 /* Compute the key for the hw shader variant */
1466 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
1467 struct si_shader_selector
*sel
,
1468 struct si_shader_key
*key
)
1470 struct si_context
*sctx
= (struct si_context
*)ctx
;
1472 memset(key
, 0, sizeof(*key
));
1474 switch (sel
->type
) {
1475 case PIPE_SHADER_VERTEX
:
1476 si_shader_selector_key_vs(sctx
, sel
, key
, &key
->part
.vs
.prolog
);
1478 if (sctx
->tes_shader
.cso
)
1480 else if (sctx
->gs_shader
.cso
)
1483 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1485 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1486 key
->mono
.u
.vs_export_prim_id
= 1;
1489 case PIPE_SHADER_TESS_CTRL
:
1490 if (sctx
->chip_class
>= GFX9
) {
1491 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1492 key
, &key
->part
.tcs
.ls_prolog
);
1493 key
->part
.tcs
.ls
= sctx
->vs_shader
.cso
;
1495 /* When the LS VGPR fix is needed, monolithic shaders
1497 * - avoid initializing EXEC in both the LS prolog
1498 * and the LS main part when !vs_needs_prolog
1499 * - remove the fixup for unused input VGPRs
1501 key
->part
.tcs
.ls_prolog
.ls_vgpr_fix
= sctx
->ls_vgpr_fix
;
1503 /* The LS output / HS input layout can be communicated
1504 * directly instead of via user SGPRs for merged LS-HS.
1505 * The LS VGPR fix prefers this too.
1507 key
->opt
.prefer_mono
= 1;
1510 key
->part
.tcs
.epilog
.prim_mode
=
1511 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1512 key
->part
.tcs
.epilog
.invoc0_tess_factors_are_def
=
1513 sel
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1514 key
->part
.tcs
.epilog
.tes_reads_tess_factors
=
1515 sctx
->tes_shader
.cso
->info
.reads_tess_factors
;
1517 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
1518 key
->mono
.u
.ff_tcs_inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
1520 case PIPE_SHADER_TESS_EVAL
:
1521 if (sctx
->gs_shader
.cso
)
1524 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1526 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1527 key
->mono
.u
.vs_export_prim_id
= 1;
1530 case PIPE_SHADER_GEOMETRY
:
1531 if (sctx
->chip_class
>= GFX9
) {
1532 if (sctx
->tes_shader
.cso
) {
1533 key
->part
.gs
.es
= sctx
->tes_shader
.cso
;
1535 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1536 key
, &key
->part
.gs
.vs_prolog
);
1537 key
->part
.gs
.es
= sctx
->vs_shader
.cso
;
1538 key
->part
.gs
.prolog
.gfx9_prev_is_vs
= 1;
1541 /* Merged ES-GS can have unbalanced wave usage.
1543 * ES threads are per-vertex, while GS threads are
1544 * per-primitive. So without any amplification, there
1545 * are fewer GS threads than ES threads, which can result
1546 * in empty (no-op) GS waves. With too much amplification,
1547 * there are more GS threads than ES threads, which
1548 * can result in empty (no-op) ES waves.
1550 * Non-monolithic shaders are implemented by setting EXEC
1551 * at the beginning of shader parts, and don't jump to
1552 * the end if EXEC is 0.
1554 * Monolithic shaders use conditional blocks, so they can
1555 * jump and skip empty waves of ES or GS. So set this to
1556 * always use optimized variants, which are monolithic.
1558 key
->opt
.prefer_mono
= 1;
1560 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
1562 case PIPE_SHADER_FRAGMENT
: {
1563 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1564 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1566 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
1567 sel
->info
.colors_written
== 0x1)
1568 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
1571 /* Select the shader color format based on whether
1572 * blending or alpha are needed.
1574 key
->part
.ps
.epilog
.spi_shader_col_format
=
1575 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1576 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
1577 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1578 sctx
->framebuffer
.spi_shader_col_format_blend
) |
1579 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1580 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
1581 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1582 sctx
->framebuffer
.spi_shader_col_format
);
1583 key
->part
.ps
.epilog
.spi_shader_col_format
&= blend
->cb_target_enabled_4bit
;
1585 /* The output for dual source blending should have
1586 * the same format as the first output.
1588 if (blend
->dual_src_blend
)
1589 key
->part
.ps
.epilog
.spi_shader_col_format
|=
1590 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
1592 key
->part
.ps
.epilog
.spi_shader_col_format
= sctx
->framebuffer
.spi_shader_col_format
;
1594 /* If alpha-to-coverage is enabled, we have to export alpha
1595 * even if there is no color buffer.
1597 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) &&
1598 blend
&& blend
->alpha_to_coverage
)
1599 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
1601 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1602 * to the range supported by the type if a channel has less
1603 * than 16 bits and the export format is 16_ABGR.
1605 if (sctx
->chip_class
<= GFX7
&& sctx
->family
!= CHIP_HAWAII
) {
1606 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
1607 key
->part
.ps
.epilog
.color_is_int10
= sctx
->framebuffer
.color_is_int10
;
1610 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1611 if (!key
->part
.ps
.epilog
.last_cbuf
) {
1612 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
1613 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
1614 key
->part
.ps
.epilog
.color_is_int10
&= sel
->info
.colors_written
;
1617 bool is_poly
= !util_prim_is_points_or_lines(sctx
->current_rast_prim
);
1618 bool is_line
= util_prim_is_lines(sctx
->current_rast_prim
);
1620 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
1621 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
1623 if (sctx
->queued
.named
.blend
) {
1624 key
->part
.ps
.epilog
.alpha_to_one
= sctx
->queued
.named
.blend
->alpha_to_one
&&
1625 rs
->multisample_enable
;
1628 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
1629 key
->part
.ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
1630 (is_line
&& rs
->line_smooth
)) &&
1631 sctx
->framebuffer
.nr_samples
<= 1;
1632 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
1634 if (sctx
->ps_iter_samples
> 1 &&
1635 sel
->info
.reads_samplemask
) {
1636 key
->part
.ps
.prolog
.samplemask_log_ps_iter
=
1637 util_logbase2(sctx
->ps_iter_samples
);
1640 if (rs
->force_persample_interp
&&
1641 rs
->multisample_enable
&&
1642 sctx
->framebuffer
.nr_samples
> 1 &&
1643 sctx
->ps_iter_samples
> 1) {
1644 key
->part
.ps
.prolog
.force_persp_sample_interp
=
1645 sel
->info
.uses_persp_center
||
1646 sel
->info
.uses_persp_centroid
;
1648 key
->part
.ps
.prolog
.force_linear_sample_interp
=
1649 sel
->info
.uses_linear_center
||
1650 sel
->info
.uses_linear_centroid
;
1651 } else if (rs
->multisample_enable
&&
1652 sctx
->framebuffer
.nr_samples
> 1) {
1653 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
1654 sel
->info
.uses_persp_center
&&
1655 sel
->info
.uses_persp_centroid
;
1656 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
1657 sel
->info
.uses_linear_center
&&
1658 sel
->info
.uses_linear_centroid
;
1660 /* Make sure SPI doesn't compute more than 1 pair
1661 * of (i,j), which is the optimization here. */
1662 key
->part
.ps
.prolog
.force_persp_center_interp
=
1663 sel
->info
.uses_persp_center
+
1664 sel
->info
.uses_persp_centroid
+
1665 sel
->info
.uses_persp_sample
> 1;
1667 key
->part
.ps
.prolog
.force_linear_center_interp
=
1668 sel
->info
.uses_linear_center
+
1669 sel
->info
.uses_linear_centroid
+
1670 sel
->info
.uses_linear_sample
> 1;
1672 if (sel
->info
.opcode_count
[TGSI_OPCODE_INTERP_SAMPLE
])
1673 key
->mono
.u
.ps
.interpolate_at_sample_force_center
= 1;
1676 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
1678 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1679 if (sctx
->ps_uses_fbfetch
&& !sctx
->blitter
->running
) {
1680 struct pipe_surface
*cb0
= sctx
->framebuffer
.state
.cbufs
[0];
1681 struct pipe_resource
*tex
= cb0
->texture
;
1683 /* 1D textures are allocated and used as 2D on GFX9. */
1684 key
->mono
.u
.ps
.fbfetch_msaa
= sctx
->framebuffer
.nr_samples
> 1;
1685 key
->mono
.u
.ps
.fbfetch_is_1D
= sctx
->chip_class
!= GFX9
&&
1686 (tex
->target
== PIPE_TEXTURE_1D
||
1687 tex
->target
== PIPE_TEXTURE_1D_ARRAY
);
1688 key
->mono
.u
.ps
.fbfetch_layered
= tex
->target
== PIPE_TEXTURE_1D_ARRAY
||
1689 tex
->target
== PIPE_TEXTURE_2D_ARRAY
||
1690 tex
->target
== PIPE_TEXTURE_CUBE
||
1691 tex
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
1692 tex
->target
== PIPE_TEXTURE_3D
;
1700 if (unlikely(sctx
->screen
->debug_flags
& DBG(NO_OPT_VARIANT
)))
1701 memset(&key
->opt
, 0, sizeof(key
->opt
));
1704 static void si_build_shader_variant(struct si_shader
*shader
,
1708 struct si_shader_selector
*sel
= shader
->selector
;
1709 struct si_screen
*sscreen
= sel
->screen
;
1710 struct ac_llvm_compiler
*compiler
;
1711 struct pipe_debug_callback
*debug
= &shader
->compiler_ctx_state
.debug
;
1713 if (thread_index
>= 0) {
1715 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler_lowp
));
1716 compiler
= &sscreen
->compiler_lowp
[thread_index
];
1718 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
1719 compiler
= &sscreen
->compiler
[thread_index
];
1724 assert(!low_priority
);
1725 compiler
= shader
->compiler_ctx_state
.compiler
;
1728 if (unlikely(!si_shader_create(sscreen
, compiler
, shader
, debug
))) {
1729 PRINT_ERR("Failed to build shader variant (type=%u)\n",
1731 shader
->compilation_failed
= true;
1735 if (shader
->compiler_ctx_state
.is_debug_context
) {
1736 FILE *f
= open_memstream(&shader
->shader_log
,
1737 &shader
->shader_log_size
);
1739 si_shader_dump(sscreen
, shader
, NULL
, sel
->type
, f
, false);
1744 si_shader_init_pm4_state(sscreen
, shader
);
1747 static void si_build_shader_variant_low_priority(void *job
, int thread_index
)
1749 struct si_shader
*shader
= (struct si_shader
*)job
;
1751 assert(thread_index
>= 0);
1753 si_build_shader_variant(shader
, thread_index
, true);
1756 static const struct si_shader_key zeroed
;
1758 static bool si_check_missing_main_part(struct si_screen
*sscreen
,
1759 struct si_shader_selector
*sel
,
1760 struct si_compiler_ctx_state
*compiler_state
,
1761 struct si_shader_key
*key
)
1763 struct si_shader
**mainp
= si_get_main_shader_part(sel
, key
);
1766 struct si_shader
*main_part
= CALLOC_STRUCT(si_shader
);
1771 /* We can leave the fence as permanently signaled because the
1772 * main part becomes visible globally only after it has been
1774 util_queue_fence_init(&main_part
->ready
);
1776 main_part
->selector
= sel
;
1777 main_part
->key
.as_es
= key
->as_es
;
1778 main_part
->key
.as_ls
= key
->as_ls
;
1779 main_part
->is_monolithic
= false;
1781 if (si_compile_tgsi_shader(sscreen
, compiler_state
->compiler
,
1782 main_part
, &compiler_state
->debug
) != 0) {
1792 * Select a shader variant according to the shader key.
1794 * \param optimized_or_none If the key describes an optimized shader variant and
1795 * the compilation isn't finished, don't select any
1796 * shader and return an error.
1798 int si_shader_select_with_key(struct si_screen
*sscreen
,
1799 struct si_shader_ctx_state
*state
,
1800 struct si_compiler_ctx_state
*compiler_state
,
1801 struct si_shader_key
*key
,
1803 bool optimized_or_none
)
1805 struct si_shader_selector
*sel
= state
->cso
;
1806 struct si_shader_selector
*previous_stage_sel
= NULL
;
1807 struct si_shader
*current
= state
->current
;
1808 struct si_shader
*iter
, *shader
= NULL
;
1811 /* Check if we don't need to change anything.
1812 * This path is also used for most shaders that don't need multiple
1813 * variants, it will cost just a computation of the key and this
1815 if (likely(current
&&
1816 memcmp(¤t
->key
, key
, sizeof(*key
)) == 0)) {
1817 if (unlikely(!util_queue_fence_is_signalled(¤t
->ready
))) {
1818 if (current
->is_optimized
) {
1819 if (optimized_or_none
)
1822 memset(&key
->opt
, 0, sizeof(key
->opt
));
1823 goto current_not_ready
;
1826 util_queue_fence_wait(¤t
->ready
);
1829 return current
->compilation_failed
? -1 : 0;
1833 /* This must be done before the mutex is locked, because async GS
1834 * compilation calls this function too, and therefore must enter
1837 * Only wait if we are in a draw call. Don't wait if we are
1838 * in a compiler thread.
1840 if (thread_index
< 0)
1841 util_queue_fence_wait(&sel
->ready
);
1843 mtx_lock(&sel
->mutex
);
1845 /* Find the shader variant. */
1846 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
1847 /* Don't check the "current" shader. We checked it above. */
1848 if (current
!= iter
&&
1849 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
1850 mtx_unlock(&sel
->mutex
);
1852 if (unlikely(!util_queue_fence_is_signalled(&iter
->ready
))) {
1853 /* If it's an optimized shader and its compilation has
1854 * been started but isn't done, use the unoptimized
1855 * shader so as not to cause a stall due to compilation.
1857 if (iter
->is_optimized
) {
1858 if (optimized_or_none
)
1860 memset(&key
->opt
, 0, sizeof(key
->opt
));
1864 util_queue_fence_wait(&iter
->ready
);
1867 if (iter
->compilation_failed
) {
1868 return -1; /* skip the draw call */
1871 state
->current
= iter
;
1876 /* Build a new shader. */
1877 shader
= CALLOC_STRUCT(si_shader
);
1879 mtx_unlock(&sel
->mutex
);
1883 util_queue_fence_init(&shader
->ready
);
1885 shader
->selector
= sel
;
1887 shader
->compiler_ctx_state
= *compiler_state
;
1889 /* If this is a merged shader, get the first shader's selector. */
1890 if (sscreen
->info
.chip_class
>= GFX9
) {
1891 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
1892 previous_stage_sel
= key
->part
.tcs
.ls
;
1893 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
1894 previous_stage_sel
= key
->part
.gs
.es
;
1896 /* We need to wait for the previous shader. */
1897 if (previous_stage_sel
&& thread_index
< 0)
1898 util_queue_fence_wait(&previous_stage_sel
->ready
);
1901 bool is_pure_monolithic
=
1902 sscreen
->use_monolithic_shaders
||
1903 memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
1905 /* Compile the main shader part if it doesn't exist. This can happen
1906 * if the initial guess was wrong.
1908 * The prim discard CS doesn't need the main shader part.
1910 if (!is_pure_monolithic
&&
1911 !key
->opt
.vs_as_prim_discard_cs
) {
1914 /* Make sure the main shader part is present. This is needed
1915 * for shaders that can be compiled as VS, LS, or ES, and only
1916 * one of them is compiled at creation.
1918 * For merged shaders, check that the starting shader's main
1921 if (previous_stage_sel
) {
1922 struct si_shader_key shader1_key
= zeroed
;
1924 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
1925 shader1_key
.as_ls
= 1;
1926 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
1927 shader1_key
.as_es
= 1;
1931 mtx_lock(&previous_stage_sel
->mutex
);
1932 ok
= si_check_missing_main_part(sscreen
,
1934 compiler_state
, &shader1_key
);
1935 mtx_unlock(&previous_stage_sel
->mutex
);
1937 ok
= si_check_missing_main_part(sscreen
, sel
,
1938 compiler_state
, key
);
1942 mtx_unlock(&sel
->mutex
);
1943 return -ENOMEM
; /* skip the draw call */
1947 /* Keep the reference to the 1st shader of merged shaders, so that
1948 * Gallium can't destroy it before we destroy the 2nd shader.
1950 * Set sctx = NULL, because it's unused if we're not releasing
1951 * the shader, and we don't have any sctx here.
1953 si_shader_selector_reference(NULL
, &shader
->previous_stage_sel
,
1954 previous_stage_sel
);
1956 /* Monolithic-only shaders don't make a distinction between optimized
1957 * and unoptimized. */
1958 shader
->is_monolithic
=
1959 is_pure_monolithic
||
1960 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1962 /* The prim discard CS is always optimized. */
1963 shader
->is_optimized
=
1964 (!is_pure_monolithic
|| key
->opt
.vs_as_prim_discard_cs
) &&
1965 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1967 /* If it's an optimized shader, compile it asynchronously. */
1968 if (shader
->is_optimized
&& thread_index
< 0) {
1969 /* Compile it asynchronously. */
1970 util_queue_add_job(&sscreen
->shader_compiler_queue_low_priority
,
1971 shader
, &shader
->ready
,
1972 si_build_shader_variant_low_priority
, NULL
);
1974 /* Add only after the ready fence was reset, to guard against a
1975 * race with si_bind_XX_shader. */
1976 if (!sel
->last_variant
) {
1977 sel
->first_variant
= shader
;
1978 sel
->last_variant
= shader
;
1980 sel
->last_variant
->next_variant
= shader
;
1981 sel
->last_variant
= shader
;
1984 /* Use the default (unoptimized) shader for now. */
1985 memset(&key
->opt
, 0, sizeof(key
->opt
));
1986 mtx_unlock(&sel
->mutex
);
1988 if (sscreen
->options
.sync_compile
)
1989 util_queue_fence_wait(&shader
->ready
);
1991 if (optimized_or_none
)
1996 /* Reset the fence before adding to the variant list. */
1997 util_queue_fence_reset(&shader
->ready
);
1999 if (!sel
->last_variant
) {
2000 sel
->first_variant
= shader
;
2001 sel
->last_variant
= shader
;
2003 sel
->last_variant
->next_variant
= shader
;
2004 sel
->last_variant
= shader
;
2007 mtx_unlock(&sel
->mutex
);
2009 assert(!shader
->is_optimized
);
2010 si_build_shader_variant(shader
, thread_index
, false);
2012 util_queue_fence_signal(&shader
->ready
);
2014 if (!shader
->compilation_failed
)
2015 state
->current
= shader
;
2017 return shader
->compilation_failed
? -1 : 0;
2020 static int si_shader_select(struct pipe_context
*ctx
,
2021 struct si_shader_ctx_state
*state
,
2022 struct si_compiler_ctx_state
*compiler_state
)
2024 struct si_context
*sctx
= (struct si_context
*)ctx
;
2025 struct si_shader_key key
;
2027 si_shader_selector_key(ctx
, state
->cso
, &key
);
2028 return si_shader_select_with_key(sctx
->screen
, state
, compiler_state
,
2032 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
2034 struct si_shader_key
*key
)
2036 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
2038 switch (info
->processor
) {
2039 case PIPE_SHADER_VERTEX
:
2040 switch (next_shader
) {
2041 case PIPE_SHADER_GEOMETRY
:
2044 case PIPE_SHADER_TESS_CTRL
:
2045 case PIPE_SHADER_TESS_EVAL
:
2049 /* If POSITION isn't written, it can only be a HW VS
2050 * if streamout is used. If streamout isn't used,
2051 * assume that it's a HW LS. (the next shader is TCS)
2052 * This heuristic is needed for separate shader objects.
2054 if (!info
->writes_position
&& !streamout
)
2059 case PIPE_SHADER_TESS_EVAL
:
2060 if (next_shader
== PIPE_SHADER_GEOMETRY
||
2061 !info
->writes_position
)
2068 * Compile the main shader part or the monolithic shader as part of
2069 * si_shader_selector initialization. Since it can be done asynchronously,
2070 * there is no way to report compile failures to applications.
2072 static void si_init_shader_selector_async(void *job
, int thread_index
)
2074 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
2075 struct si_screen
*sscreen
= sel
->screen
;
2076 struct ac_llvm_compiler
*compiler
;
2077 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
2079 assert(!debug
->debug_message
|| debug
->async
);
2080 assert(thread_index
>= 0);
2081 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
2082 compiler
= &sscreen
->compiler
[thread_index
];
2087 /* Compile the main shader part for use with a prolog and/or epilog.
2088 * If this fails, the driver will try to compile a monolithic shader
2091 if (!sscreen
->use_monolithic_shaders
) {
2092 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
2093 void *ir_binary
= NULL
;
2096 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
2100 /* We can leave the fence signaled because use of the default
2101 * main part is guarded by the selector's ready fence. */
2102 util_queue_fence_init(&shader
->ready
);
2104 shader
->selector
= sel
;
2105 shader
->is_monolithic
= false;
2106 si_parse_next_shader_property(&sel
->info
,
2107 sel
->so
.num_outputs
!= 0,
2110 if (sel
->tokens
|| sel
->nir
)
2111 ir_binary
= si_get_ir_binary(sel
);
2113 /* Try to load the shader from the shader cache. */
2114 mtx_lock(&sscreen
->shader_cache_mutex
);
2117 si_shader_cache_load_shader(sscreen
, ir_binary
, shader
)) {
2118 mtx_unlock(&sscreen
->shader_cache_mutex
);
2119 si_shader_dump_stats_for_shader_db(shader
, debug
);
2121 mtx_unlock(&sscreen
->shader_cache_mutex
);
2123 /* Compile the shader if it hasn't been loaded from the cache. */
2124 if (si_compile_tgsi_shader(sscreen
, compiler
, shader
,
2128 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
2133 mtx_lock(&sscreen
->shader_cache_mutex
);
2134 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
, shader
, true))
2136 mtx_unlock(&sscreen
->shader_cache_mutex
);
2140 *si_get_main_shader_part(sel
, &shader
->key
) = shader
;
2142 /* Unset "outputs_written" flags for outputs converted to
2143 * DEFAULT_VAL, so that later inter-shader optimizations don't
2144 * try to eliminate outputs that don't exist in the final
2147 * This is only done if non-monolithic shaders are enabled.
2149 if ((sel
->type
== PIPE_SHADER_VERTEX
||
2150 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
2151 !shader
->key
.as_ls
&&
2152 !shader
->key
.as_es
) {
2155 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2156 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
2158 if (offset
<= AC_EXP_PARAM_OFFSET_31
)
2161 unsigned name
= sel
->info
.output_semantic_name
[i
];
2162 unsigned index
= sel
->info
.output_semantic_index
[i
];
2166 case TGSI_SEMANTIC_GENERIC
:
2167 /* don't process indices the function can't handle */
2168 if (index
>= SI_MAX_IO_GENERIC
)
2172 id
= si_shader_io_get_unique_index(name
, index
, true);
2173 sel
->outputs_written_before_ps
&= ~(1ull << id
);
2175 case TGSI_SEMANTIC_POSITION
: /* ignore these */
2176 case TGSI_SEMANTIC_PSIZE
:
2177 case TGSI_SEMANTIC_CLIPVERTEX
:
2178 case TGSI_SEMANTIC_EDGEFLAG
:
2185 /* The GS copy shader is always pre-compiled. */
2186 if (sel
->type
== PIPE_SHADER_GEOMETRY
) {
2187 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, compiler
, sel
, debug
);
2188 if (!sel
->gs_copy_shader
) {
2189 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
2193 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
2197 void si_schedule_initial_compile(struct si_context
*sctx
, unsigned processor
,
2198 struct util_queue_fence
*ready_fence
,
2199 struct si_compiler_ctx_state
*compiler_ctx_state
,
2200 void *job
, util_queue_execute_func execute
)
2202 util_queue_fence_init(ready_fence
);
2204 struct util_async_debug_callback async_debug
;
2206 (sctx
->debug
.debug_message
&& !sctx
->debug
.async
) ||
2208 si_can_dump_shader(sctx
->screen
, processor
);
2211 u_async_debug_init(&async_debug
);
2212 compiler_ctx_state
->debug
= async_debug
.base
;
2215 util_queue_add_job(&sctx
->screen
->shader_compiler_queue
, job
,
2216 ready_fence
, execute
, NULL
);
2219 util_queue_fence_wait(ready_fence
);
2220 u_async_debug_drain(&async_debug
, &sctx
->debug
);
2221 u_async_debug_cleanup(&async_debug
);
2224 if (sctx
->screen
->options
.sync_compile
)
2225 util_queue_fence_wait(ready_fence
);
2228 /* Return descriptor slot usage masks from the given shader info. */
2229 void si_get_active_slot_masks(const struct tgsi_shader_info
*info
,
2230 uint32_t *const_and_shader_buffers
,
2231 uint64_t *samplers_and_images
)
2233 unsigned start
, num_shaderbufs
, num_constbufs
, num_images
, num_samplers
;
2235 num_shaderbufs
= util_last_bit(info
->shader_buffers_declared
);
2236 num_constbufs
= util_last_bit(info
->const_buffers_declared
);
2237 /* two 8-byte images share one 16-byte slot */
2238 num_images
= align(util_last_bit(info
->images_declared
), 2);
2239 num_samplers
= util_last_bit(info
->samplers_declared
);
2241 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2242 start
= si_get_shaderbuf_slot(num_shaderbufs
- 1);
2243 *const_and_shader_buffers
=
2244 u_bit_consecutive(start
, num_shaderbufs
+ num_constbufs
);
2246 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2247 start
= si_get_image_slot(num_images
- 1) / 2;
2248 *samplers_and_images
=
2249 u_bit_consecutive64(start
, num_images
/ 2 + num_samplers
);
2252 static void *si_create_shader_selector(struct pipe_context
*ctx
,
2253 const struct pipe_shader_state
*state
)
2255 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
2256 struct si_context
*sctx
= (struct si_context
*)ctx
;
2257 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
2263 pipe_reference_init(&sel
->reference
, 1);
2264 sel
->screen
= sscreen
;
2265 sel
->compiler_ctx_state
.debug
= sctx
->debug
;
2266 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
2268 sel
->so
= state
->stream_output
;
2270 if (state
->type
== PIPE_SHADER_IR_TGSI
) {
2271 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
2277 tgsi_scan_shader(state
->tokens
, &sel
->info
);
2278 tgsi_scan_tess_ctrl(state
->tokens
, &sel
->info
, &sel
->tcs_info
);
2280 assert(state
->type
== PIPE_SHADER_IR_NIR
);
2282 sel
->nir
= state
->ir
.nir
;
2284 si_nir_opts(sel
->nir
);
2285 si_nir_scan_shader(sel
->nir
, &sel
->info
);
2286 si_nir_scan_tess_ctrl(sel
->nir
, &sel
->tcs_info
);
2289 sel
->type
= sel
->info
.processor
;
2290 p_atomic_inc(&sscreen
->num_shaders_created
);
2291 si_get_active_slot_masks(&sel
->info
,
2292 &sel
->active_const_and_shader_buffers
,
2293 &sel
->active_samplers_and_images
);
2295 /* Record which streamout buffers are enabled. */
2296 for (i
= 0; i
< sel
->so
.num_outputs
; i
++) {
2297 sel
->enabled_streamout_buffer_mask
|=
2298 (1 << sel
->so
.output
[i
].output_buffer
) <<
2299 (sel
->so
.output
[i
].stream
* 4);
2302 /* The prolog is a no-op if there are no inputs. */
2303 sel
->vs_needs_prolog
= sel
->type
== PIPE_SHADER_VERTEX
&&
2304 sel
->info
.num_inputs
&&
2305 !sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
2307 sel
->force_correct_derivs_after_kill
=
2308 sel
->type
== PIPE_SHADER_FRAGMENT
&&
2309 sel
->info
.uses_derivatives
&&
2310 sel
->info
.uses_kill
&&
2311 sctx
->screen
->debug_flags
& DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
2313 sel
->prim_discard_cs_allowed
=
2314 sel
->type
== PIPE_SHADER_VERTEX
&&
2315 !sel
->info
.uses_bindless_images
&&
2316 !sel
->info
.uses_bindless_samplers
&&
2317 !sel
->info
.writes_memory
&&
2318 !sel
->info
.writes_viewport_index
&&
2319 !sel
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] &&
2320 !sel
->so
.num_outputs
;
2322 /* Set which opcode uses which (i,j) pair. */
2323 if (sel
->info
.uses_persp_opcode_interp_centroid
)
2324 sel
->info
.uses_persp_centroid
= true;
2326 if (sel
->info
.uses_linear_opcode_interp_centroid
)
2327 sel
->info
.uses_linear_centroid
= true;
2329 if (sel
->info
.uses_persp_opcode_interp_offset
||
2330 sel
->info
.uses_persp_opcode_interp_sample
)
2331 sel
->info
.uses_persp_center
= true;
2333 if (sel
->info
.uses_linear_opcode_interp_offset
||
2334 sel
->info
.uses_linear_opcode_interp_sample
)
2335 sel
->info
.uses_linear_center
= true;
2337 switch (sel
->type
) {
2338 case PIPE_SHADER_GEOMETRY
:
2339 sel
->gs_output_prim
=
2340 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
2341 sel
->gs_max_out_vertices
=
2342 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
2343 sel
->gs_num_invocations
=
2344 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
2345 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
2346 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
2347 sel
->gs_max_out_vertices
;
2349 sel
->max_gs_stream
= 0;
2350 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
2351 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
2352 sel
->so
.output
[i
].stream
);
2354 sel
->gs_input_verts_per_prim
=
2355 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
2358 case PIPE_SHADER_TESS_CTRL
:
2359 /* Always reserve space for these. */
2360 sel
->patch_outputs_written
|=
2361 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0)) |
2362 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0));
2364 case PIPE_SHADER_VERTEX
:
2365 case PIPE_SHADER_TESS_EVAL
:
2366 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2367 unsigned name
= sel
->info
.output_semantic_name
[i
];
2368 unsigned index
= sel
->info
.output_semantic_index
[i
];
2371 case TGSI_SEMANTIC_TESSINNER
:
2372 case TGSI_SEMANTIC_TESSOUTER
:
2373 case TGSI_SEMANTIC_PATCH
:
2374 sel
->patch_outputs_written
|=
2375 1ull << si_shader_io_get_unique_index_patch(name
, index
);
2378 case TGSI_SEMANTIC_GENERIC
:
2379 /* don't process indices the function can't handle */
2380 if (index
>= SI_MAX_IO_GENERIC
)
2384 sel
->outputs_written
|=
2385 1ull << si_shader_io_get_unique_index(name
, index
, false);
2386 sel
->outputs_written_before_ps
|=
2387 1ull << si_shader_io_get_unique_index(name
, index
, true);
2389 case TGSI_SEMANTIC_EDGEFLAG
:
2393 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
2394 sel
->lshs_vertex_stride
= sel
->esgs_itemsize
;
2396 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2397 * will start on a different bank. (except for the maximum 32*16).
2399 if (sel
->lshs_vertex_stride
< 32*16)
2400 sel
->lshs_vertex_stride
+= 4;
2402 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2403 * conflicts, i.e. each vertex will start at a different bank.
2405 if (sctx
->chip_class
>= GFX9
)
2406 sel
->esgs_itemsize
+= 4;
2408 assert(((sel
->esgs_itemsize
/ 4) & C_028AAC_ITEMSIZE
) == 0);
2411 case PIPE_SHADER_FRAGMENT
:
2412 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2413 unsigned name
= sel
->info
.input_semantic_name
[i
];
2414 unsigned index
= sel
->info
.input_semantic_index
[i
];
2417 case TGSI_SEMANTIC_GENERIC
:
2418 /* don't process indices the function can't handle */
2419 if (index
>= SI_MAX_IO_GENERIC
)
2424 1ull << si_shader_io_get_unique_index(name
, index
, true);
2426 case TGSI_SEMANTIC_PCOORD
: /* ignore this */
2431 for (i
= 0; i
< 8; i
++)
2432 if (sel
->info
.colors_written
& (1 << i
))
2433 sel
->colors_written_4bit
|= 0xf << (4 * i
);
2435 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2436 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
2437 int index
= sel
->info
.input_semantic_index
[i
];
2438 sel
->color_attr_index
[index
] = i
;
2444 /* PA_CL_VS_OUT_CNTL */
2446 sel
->info
.writes_psize
|| sel
->info
.writes_edgeflag
||
2447 sel
->info
.writes_layer
|| sel
->info
.writes_viewport_index
;
2448 sel
->pa_cl_vs_out_cntl
=
2449 S_02881C_USE_VTX_POINT_SIZE(sel
->info
.writes_psize
) |
2450 S_02881C_USE_VTX_EDGE_FLAG(sel
->info
.writes_edgeflag
) |
2451 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel
->info
.writes_layer
) |
2452 S_02881C_USE_VTX_VIEWPORT_INDX(sel
->info
.writes_viewport_index
) |
2453 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
2454 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
);
2455 sel
->clipdist_mask
= sel
->info
.writes_clipvertex
?
2456 SIX_BITS
: sel
->info
.clipdist_writemask
;
2457 sel
->culldist_mask
= sel
->info
.culldist_writemask
<<
2458 sel
->info
.num_written_clipdistance
;
2460 /* DB_SHADER_CONTROL */
2461 sel
->db_shader_control
=
2462 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
2463 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
2464 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
2465 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
2467 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
2468 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2469 sel
->db_shader_control
|=
2470 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2472 case TGSI_FS_DEPTH_LAYOUT_LESS
:
2473 sel
->db_shader_control
|=
2474 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2478 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2480 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2481 * --|-----------|------------|------------|--------------------|-------------------|-------------
2482 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2483 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2484 * 2 | false | true | n/a | LateZ | 1 | 0
2485 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2486 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2488 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2489 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2491 * Don't use ReZ without profiling !!!
2493 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2496 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
2498 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
2499 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
2500 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
2501 } else if (sel
->info
.writes_memory
) {
2503 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) |
2504 S_02880C_EXEC_ON_HIER_FAIL(1);
2507 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2510 (void) mtx_init(&sel
->mutex
, mtx_plain
);
2512 si_schedule_initial_compile(sctx
, sel
->info
.processor
, &sel
->ready
,
2513 &sel
->compiler_ctx_state
, sel
,
2514 si_init_shader_selector_async
);
2518 static void si_update_streamout_state(struct si_context
*sctx
)
2520 struct si_shader_selector
*shader_with_so
= si_get_vs(sctx
)->cso
;
2522 if (!shader_with_so
)
2525 sctx
->streamout
.enabled_stream_buffers_mask
=
2526 shader_with_so
->enabled_streamout_buffer_mask
;
2527 sctx
->streamout
.stride_in_dw
= shader_with_so
->so
.stride
;
2530 static void si_update_clip_regs(struct si_context
*sctx
,
2531 struct si_shader_selector
*old_hw_vs
,
2532 struct si_shader
*old_hw_vs_variant
,
2533 struct si_shader_selector
*next_hw_vs
,
2534 struct si_shader
*next_hw_vs_variant
)
2538 old_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] !=
2539 next_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] ||
2540 old_hw_vs
->pa_cl_vs_out_cntl
!= next_hw_vs
->pa_cl_vs_out_cntl
||
2541 old_hw_vs
->clipdist_mask
!= next_hw_vs
->clipdist_mask
||
2542 old_hw_vs
->culldist_mask
!= next_hw_vs
->culldist_mask
||
2543 !old_hw_vs_variant
||
2544 !next_hw_vs_variant
||
2545 old_hw_vs_variant
->key
.opt
.clip_disable
!=
2546 next_hw_vs_variant
->key
.opt
.clip_disable
))
2547 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
2550 static void si_update_common_shader_state(struct si_context
*sctx
)
2552 sctx
->uses_bindless_samplers
=
2553 si_shader_uses_bindless_samplers(sctx
->vs_shader
.cso
) ||
2554 si_shader_uses_bindless_samplers(sctx
->gs_shader
.cso
) ||
2555 si_shader_uses_bindless_samplers(sctx
->ps_shader
.cso
) ||
2556 si_shader_uses_bindless_samplers(sctx
->tcs_shader
.cso
) ||
2557 si_shader_uses_bindless_samplers(sctx
->tes_shader
.cso
);
2558 sctx
->uses_bindless_images
=
2559 si_shader_uses_bindless_images(sctx
->vs_shader
.cso
) ||
2560 si_shader_uses_bindless_images(sctx
->gs_shader
.cso
) ||
2561 si_shader_uses_bindless_images(sctx
->ps_shader
.cso
) ||
2562 si_shader_uses_bindless_images(sctx
->tcs_shader
.cso
) ||
2563 si_shader_uses_bindless_images(sctx
->tes_shader
.cso
);
2564 sctx
->do_update_shaders
= true;
2567 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
2569 struct si_context
*sctx
= (struct si_context
*)ctx
;
2570 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2571 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2572 struct si_shader_selector
*sel
= state
;
2574 if (sctx
->vs_shader
.cso
== sel
)
2577 sctx
->vs_shader
.cso
= sel
;
2578 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2579 sctx
->num_vs_blit_sgprs
= sel
? sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
] : 0;
2581 si_update_common_shader_state(sctx
);
2582 si_update_vs_viewport_state(sctx
);
2583 si_set_active_descriptors_for_shader(sctx
, sel
);
2584 si_update_streamout_state(sctx
);
2585 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2586 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2589 static void si_update_tess_uses_prim_id(struct si_context
*sctx
)
2591 sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
=
2592 (sctx
->tes_shader
.cso
&&
2593 sctx
->tes_shader
.cso
->info
.uses_primid
) ||
2594 (sctx
->tcs_shader
.cso
&&
2595 sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
2596 (sctx
->gs_shader
.cso
&&
2597 sctx
->gs_shader
.cso
->info
.uses_primid
) ||
2598 (sctx
->ps_shader
.cso
&& !sctx
->gs_shader
.cso
&&
2599 sctx
->ps_shader
.cso
->info
.uses_primid
);
2602 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
2604 struct si_context
*sctx
= (struct si_context
*)ctx
;
2605 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2606 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2607 struct si_shader_selector
*sel
= state
;
2608 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
2610 if (sctx
->gs_shader
.cso
== sel
)
2613 sctx
->gs_shader
.cso
= sel
;
2614 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2615 sctx
->ia_multi_vgt_param_key
.u
.uses_gs
= sel
!= NULL
;
2617 si_update_common_shader_state(sctx
);
2618 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2620 if (enable_changed
) {
2621 si_shader_change_notify(sctx
);
2622 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2623 si_update_tess_uses_prim_id(sctx
);
2625 si_update_vs_viewport_state(sctx
);
2626 si_set_active_descriptors_for_shader(sctx
, sel
);
2627 si_update_streamout_state(sctx
);
2628 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2629 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2632 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
2634 struct si_context
*sctx
= (struct si_context
*)ctx
;
2635 struct si_shader_selector
*sel
= state
;
2636 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
2638 if (sctx
->tcs_shader
.cso
== sel
)
2641 sctx
->tcs_shader
.cso
= sel
;
2642 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2643 si_update_tess_uses_prim_id(sctx
);
2645 si_update_common_shader_state(sctx
);
2648 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
2650 si_set_active_descriptors_for_shader(sctx
, sel
);
2653 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
2655 struct si_context
*sctx
= (struct si_context
*)ctx
;
2656 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2657 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2658 struct si_shader_selector
*sel
= state
;
2659 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
2661 if (sctx
->tes_shader
.cso
== sel
)
2664 sctx
->tes_shader
.cso
= sel
;
2665 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
2666 sctx
->ia_multi_vgt_param_key
.u
.uses_tess
= sel
!= NULL
;
2667 si_update_tess_uses_prim_id(sctx
);
2669 si_update_common_shader_state(sctx
);
2670 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2672 if (enable_changed
) {
2673 si_shader_change_notify(sctx
);
2674 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
2676 si_update_vs_viewport_state(sctx
);
2677 si_set_active_descriptors_for_shader(sctx
, sel
);
2678 si_update_streamout_state(sctx
);
2679 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2680 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2683 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
2685 struct si_context
*sctx
= (struct si_context
*)ctx
;
2686 struct si_shader_selector
*old_sel
= sctx
->ps_shader
.cso
;
2687 struct si_shader_selector
*sel
= state
;
2689 /* skip if supplied shader is one already in use */
2693 sctx
->ps_shader
.cso
= sel
;
2694 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
2696 si_update_common_shader_state(sctx
);
2698 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2699 si_update_tess_uses_prim_id(sctx
);
2702 old_sel
->info
.colors_written
!= sel
->info
.colors_written
)
2703 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
2705 if (sctx
->screen
->has_out_of_order_rast
&&
2707 old_sel
->info
.writes_memory
!= sel
->info
.writes_memory
||
2708 old_sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] !=
2709 sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]))
2710 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2712 si_set_active_descriptors_for_shader(sctx
, sel
);
2713 si_update_ps_colorbuf0_slot(sctx
);
2716 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
2718 if (shader
->is_optimized
) {
2719 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue_low_priority
,
2723 util_queue_fence_destroy(&shader
->ready
);
2726 switch (shader
->selector
->type
) {
2727 case PIPE_SHADER_VERTEX
:
2728 if (shader
->key
.as_ls
) {
2729 assert(sctx
->chip_class
<= GFX8
);
2730 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
2731 } else if (shader
->key
.as_es
) {
2732 assert(sctx
->chip_class
<= GFX8
);
2733 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2735 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2738 case PIPE_SHADER_TESS_CTRL
:
2739 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
2741 case PIPE_SHADER_TESS_EVAL
:
2742 if (shader
->key
.as_es
) {
2743 assert(sctx
->chip_class
<= GFX8
);
2744 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2746 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2749 case PIPE_SHADER_GEOMETRY
:
2750 if (shader
->is_gs_copy_shader
)
2751 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2753 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
2755 case PIPE_SHADER_FRAGMENT
:
2756 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
2761 si_shader_selector_reference(sctx
, &shader
->previous_stage_sel
, NULL
);
2762 si_shader_destroy(shader
);
2766 void si_destroy_shader_selector(struct si_context
*sctx
,
2767 struct si_shader_selector
*sel
)
2769 struct si_shader
*p
= sel
->first_variant
, *c
;
2770 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
2771 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
2772 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
2773 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
2774 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
2775 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
2778 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue
, &sel
->ready
);
2780 if (current_shader
[sel
->type
]->cso
== sel
) {
2781 current_shader
[sel
->type
]->cso
= NULL
;
2782 current_shader
[sel
->type
]->current
= NULL
;
2786 c
= p
->next_variant
;
2787 si_delete_shader(sctx
, p
);
2791 if (sel
->main_shader_part
)
2792 si_delete_shader(sctx
, sel
->main_shader_part
);
2793 if (sel
->main_shader_part_ls
)
2794 si_delete_shader(sctx
, sel
->main_shader_part_ls
);
2795 if (sel
->main_shader_part_es
)
2796 si_delete_shader(sctx
, sel
->main_shader_part_es
);
2797 if (sel
->gs_copy_shader
)
2798 si_delete_shader(sctx
, sel
->gs_copy_shader
);
2800 util_queue_fence_destroy(&sel
->ready
);
2801 mtx_destroy(&sel
->mutex
);
2803 ralloc_free(sel
->nir
);
2807 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
2809 struct si_context
*sctx
= (struct si_context
*)ctx
;
2810 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
2812 si_shader_selector_reference(sctx
, &sel
, NULL
);
2815 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
2816 struct si_shader
*vs
, unsigned name
,
2817 unsigned index
, unsigned interpolate
)
2819 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
2820 unsigned j
, offset
, ps_input_cntl
= 0;
2822 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2823 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
) ||
2824 name
== TGSI_SEMANTIC_PRIMID
)
2825 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
2827 if (name
== TGSI_SEMANTIC_PCOORD
||
2828 (name
== TGSI_SEMANTIC_TEXCOORD
&&
2829 sctx
->sprite_coord_enable
& (1 << index
))) {
2830 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
2833 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
2834 if (name
== vsinfo
->output_semantic_name
[j
] &&
2835 index
== vsinfo
->output_semantic_index
[j
]) {
2836 offset
= vs
->info
.vs_output_param_offset
[j
];
2838 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
2839 /* The input is loaded from parameter memory. */
2840 ps_input_cntl
|= S_028644_OFFSET(offset
);
2841 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2842 if (offset
== AC_EXP_PARAM_UNDEFINED
) {
2843 /* This can happen with depth-only rendering. */
2846 /* The input is a DEFAULT_VAL constant. */
2847 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
2848 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
2849 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
2852 ps_input_cntl
= S_028644_OFFSET(0x20) |
2853 S_028644_DEFAULT_VAL(offset
);
2859 if (name
== TGSI_SEMANTIC_PRIMID
)
2860 /* PrimID is written after the last output. */
2861 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
2862 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2863 /* No corresponding output found, load defaults into input.
2864 * Don't set any other bits.
2865 * (FLAT_SHADE=1 completely changes behavior) */
2866 ps_input_cntl
= S_028644_OFFSET(0x20);
2867 /* D3D 9 behaviour. GL is undefined */
2868 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
2869 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
2871 return ps_input_cntl
;
2874 static void si_emit_spi_map(struct si_context
*sctx
)
2876 struct si_shader
*ps
= sctx
->ps_shader
.current
;
2877 struct si_shader
*vs
= si_get_vs_state(sctx
);
2878 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
2879 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
2880 unsigned spi_ps_input_cntl
[32];
2882 if (!ps
|| !ps
->selector
->info
.num_inputs
)
2885 num_interp
= si_get_ps_num_interp(ps
);
2886 assert(num_interp
> 0);
2888 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
2889 unsigned name
= psinfo
->input_semantic_name
[i
];
2890 unsigned index
= psinfo
->input_semantic_index
[i
];
2891 unsigned interpolate
= psinfo
->input_interpolate
[i
];
2893 spi_ps_input_cntl
[num_written
++] = si_get_ps_input_cntl(sctx
, vs
, name
,
2894 index
, interpolate
);
2896 if (name
== TGSI_SEMANTIC_COLOR
) {
2897 assert(index
< ARRAY_SIZE(bcol_interp
));
2898 bcol_interp
[index
] = interpolate
;
2902 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
2903 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
2905 for (i
= 0; i
< 2; i
++) {
2906 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
2909 spi_ps_input_cntl
[num_written
++] =
2910 si_get_ps_input_cntl(sctx
, vs
, bcol
, i
, bcol_interp
[i
]);
2914 assert(num_interp
== num_written
);
2916 /* R_028644_SPI_PS_INPUT_CNTL_0 */
2917 /* Dota 2: Only ~16% of SPI map updates set different values. */
2918 /* Talos: Only ~9% of SPI map updates set different values. */
2919 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
2920 radeon_opt_set_context_regn(sctx
, R_028644_SPI_PS_INPUT_CNTL_0
,
2922 sctx
->tracked_regs
.spi_ps_input_cntl
, num_interp
);
2924 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
2925 sctx
->context_roll
= true;
2929 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2931 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
2933 if (sctx
->init_config_has_vgt_flush
)
2936 /* Done by Vulkan before VGT_FLUSH. */
2937 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2938 si_pm4_cmd_add(sctx
->init_config
,
2939 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2940 si_pm4_cmd_end(sctx
->init_config
, false);
2942 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2943 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2944 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
2945 si_pm4_cmd_end(sctx
->init_config
, false);
2946 sctx
->init_config_has_vgt_flush
= true;
2949 /* Initialize state related to ESGS / GSVS ring buffers */
2950 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
2952 struct si_shader_selector
*es
=
2953 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
2954 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
2955 struct si_pm4_state
*pm4
;
2957 /* Chip constants. */
2958 unsigned num_se
= sctx
->screen
->info
.max_se
;
2959 unsigned wave_size
= 64;
2960 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
2961 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
2962 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2964 unsigned gs_vertex_reuse
= (sctx
->chip_class
>= GFX8
? 32 : 16) * num_se
;
2965 unsigned alignment
= 256 * num_se
;
2966 /* The maximum size is 63.999 MB per SE. */
2967 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
2969 /* Calculate the minimum size. */
2970 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
2971 wave_size
, alignment
);
2973 /* These are recommended sizes, not minimum sizes. */
2974 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
2975 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
2976 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
2977 gs
->max_gsvs_emit_size
;
2979 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
2980 esgs_ring_size
= align(esgs_ring_size
, alignment
);
2981 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
2983 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
2984 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
2986 /* Some rings don't have to be allocated if shaders don't use them.
2987 * (e.g. no varyings between ES and GS or GS and VS)
2989 * GFX9 doesn't have the ESGS ring.
2991 bool update_esgs
= sctx
->chip_class
<= GFX8
&&
2993 (!sctx
->esgs_ring
||
2994 sctx
->esgs_ring
->width0
< esgs_ring_size
);
2995 bool update_gsvs
= gsvs_ring_size
&&
2996 (!sctx
->gsvs_ring
||
2997 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
2999 if (!update_esgs
&& !update_gsvs
)
3003 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
3005 pipe_aligned_buffer_create(sctx
->b
.screen
,
3006 SI_RESOURCE_FLAG_UNMAPPABLE
,
3008 esgs_ring_size
, alignment
);
3009 if (!sctx
->esgs_ring
)
3014 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
3016 pipe_aligned_buffer_create(sctx
->b
.screen
,
3017 SI_RESOURCE_FLAG_UNMAPPABLE
,
3019 gsvs_ring_size
, alignment
);
3020 if (!sctx
->gsvs_ring
)
3024 /* Create the "init_config_gs_rings" state. */
3025 pm4
= CALLOC_STRUCT(si_pm4_state
);
3029 if (sctx
->chip_class
>= GFX7
) {
3030 if (sctx
->esgs_ring
) {
3031 assert(sctx
->chip_class
<= GFX8
);
3032 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
3033 sctx
->esgs_ring
->width0
/ 256);
3035 if (sctx
->gsvs_ring
)
3036 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
3037 sctx
->gsvs_ring
->width0
/ 256);
3039 if (sctx
->esgs_ring
)
3040 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
3041 sctx
->esgs_ring
->width0
/ 256);
3042 if (sctx
->gsvs_ring
)
3043 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
3044 sctx
->gsvs_ring
->width0
/ 256);
3047 /* Set the state. */
3048 if (sctx
->init_config_gs_rings
)
3049 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
3050 sctx
->init_config_gs_rings
= pm4
;
3052 if (!sctx
->init_config_has_vgt_flush
) {
3053 si_init_config_add_vgt_flush(sctx
);
3054 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3057 /* Flush the context to re-emit both init_config states. */
3058 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3059 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3061 /* Set ring bindings. */
3062 if (sctx
->esgs_ring
) {
3063 assert(sctx
->chip_class
<= GFX8
);
3064 si_set_ring_buffer(sctx
, SI_ES_RING_ESGS
,
3065 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
3066 true, true, 4, 64, 0);
3067 si_set_ring_buffer(sctx
, SI_GS_RING_ESGS
,
3068 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
3069 false, false, 0, 0, 0);
3071 if (sctx
->gsvs_ring
) {
3072 si_set_ring_buffer(sctx
, SI_RING_GSVS
,
3073 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
3074 false, false, 0, 0, 0);
3080 static void si_shader_lock(struct si_shader
*shader
)
3082 mtx_lock(&shader
->selector
->mutex
);
3083 if (shader
->previous_stage_sel
) {
3084 assert(shader
->previous_stage_sel
!= shader
->selector
);
3085 mtx_lock(&shader
->previous_stage_sel
->mutex
);
3089 static void si_shader_unlock(struct si_shader
*shader
)
3091 if (shader
->previous_stage_sel
)
3092 mtx_unlock(&shader
->previous_stage_sel
->mutex
);
3093 mtx_unlock(&shader
->selector
->mutex
);
3097 * @returns 1 if \p sel has been updated to use a new scratch buffer
3099 * < 0 if there was a failure
3101 static int si_update_scratch_buffer(struct si_context
*sctx
,
3102 struct si_shader
*shader
)
3104 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
3109 /* This shader doesn't need a scratch buffer */
3110 if (shader
->config
.scratch_bytes_per_wave
== 0)
3113 /* Prevent race conditions when updating:
3114 * - si_shader::scratch_bo
3115 * - si_shader::binary::code
3116 * - si_shader::previous_stage::binary::code.
3118 si_shader_lock(shader
);
3120 /* This shader is already configured to use the current
3121 * scratch buffer. */
3122 if (shader
->scratch_bo
== sctx
->scratch_buffer
) {
3123 si_shader_unlock(shader
);
3127 assert(sctx
->scratch_buffer
);
3129 /* Replace the shader bo with a new bo that has the relocs applied. */
3130 if (!si_shader_binary_upload(sctx
->screen
, shader
, scratch_va
)) {
3131 si_shader_unlock(shader
);
3135 /* Update the shader state to use the new shader bo. */
3136 si_shader_init_pm4_state(sctx
->screen
, shader
);
3138 si_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
3140 si_shader_unlock(shader
);
3144 static unsigned si_get_current_scratch_buffer_size(struct si_context
*sctx
)
3146 return sctx
->scratch_buffer
? sctx
->scratch_buffer
->b
.b
.width0
: 0;
3149 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
3151 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
3154 static struct si_shader
*si_get_tcs_current(struct si_context
*sctx
)
3156 if (!sctx
->tes_shader
.cso
)
3157 return NULL
; /* tessellation disabled */
3159 return sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.current
:
3160 sctx
->fixed_func_tcs_shader
.current
;
3163 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context
*sctx
)
3167 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
3168 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
3169 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
3170 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
3172 if (sctx
->tes_shader
.cso
) {
3173 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
3175 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(tcs
));
3180 static bool si_update_scratch_relocs(struct si_context
*sctx
)
3182 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
3185 /* Update the shaders, so that they are using the latest scratch.
3186 * The scratch buffer may have been changed since these shaders were
3187 * last used, so we still need to try to update them, even if they
3188 * require scratch buffers smaller than the current size.
3190 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
3194 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3196 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
3200 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3202 r
= si_update_scratch_buffer(sctx
, tcs
);
3206 si_pm4_bind_state(sctx
, hs
, tcs
->pm4
);
3208 /* VS can be bound as LS, ES, or VS. */
3209 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
3213 if (sctx
->tes_shader
.current
)
3214 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3215 else if (sctx
->gs_shader
.current
)
3216 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3218 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3221 /* TES can be bound as ES or VS. */
3222 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
3226 if (sctx
->gs_shader
.current
)
3227 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3229 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3235 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
3237 unsigned current_scratch_buffer_size
=
3238 si_get_current_scratch_buffer_size(sctx
);
3239 unsigned scratch_bytes_per_wave
=
3240 si_get_max_scratch_bytes_per_wave(sctx
);
3241 unsigned scratch_needed_size
= scratch_bytes_per_wave
*
3242 sctx
->scratch_waves
;
3243 unsigned spi_tmpring_size
;
3245 if (scratch_needed_size
> 0) {
3246 if (scratch_needed_size
> current_scratch_buffer_size
) {
3247 /* Create a bigger scratch buffer */
3248 si_resource_reference(&sctx
->scratch_buffer
, NULL
);
3250 sctx
->scratch_buffer
=
3251 si_aligned_buffer_create(&sctx
->screen
->b
,
3252 SI_RESOURCE_FLAG_UNMAPPABLE
,
3254 scratch_needed_size
, 256);
3255 if (!sctx
->scratch_buffer
)
3258 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3259 si_context_add_resource_size(sctx
,
3260 &sctx
->scratch_buffer
->b
.b
);
3263 if (!si_update_scratch_relocs(sctx
))
3267 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3268 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
3269 "scratch size should already be aligned correctly.");
3271 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
3272 S_0286E8_WAVESIZE(scratch_bytes_per_wave
>> 10);
3273 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
3274 sctx
->spi_tmpring_size
= spi_tmpring_size
;
3275 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3280 static void si_init_tess_factor_ring(struct si_context
*sctx
)
3282 assert(!sctx
->tess_rings
);
3284 /* The address must be aligned to 2^19, because the shader only
3285 * receives the high 13 bits.
3287 sctx
->tess_rings
= pipe_aligned_buffer_create(sctx
->b
.screen
,
3288 SI_RESOURCE_FLAG_32BIT
,
3290 sctx
->screen
->tess_offchip_ring_size
+
3291 sctx
->screen
->tess_factor_ring_size
,
3293 if (!sctx
->tess_rings
)
3296 si_init_config_add_vgt_flush(sctx
);
3298 si_pm4_add_bo(sctx
->init_config
, si_resource(sctx
->tess_rings
),
3299 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
3301 uint64_t factor_va
= si_resource(sctx
->tess_rings
)->gpu_address
+
3302 sctx
->screen
->tess_offchip_ring_size
;
3304 /* Append these registers to the init config state. */
3305 if (sctx
->chip_class
>= GFX7
) {
3306 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
3307 S_030938_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3308 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
3310 if (sctx
->chip_class
>= GFX9
)
3311 si_pm4_set_reg(sctx
->init_config
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3312 S_030944_BASE_HI(factor_va
>> 40));
3313 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3314 sctx
->screen
->vgt_hs_offchip_param
);
3316 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
3317 S_008988_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3318 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
3320 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3321 sctx
->screen
->vgt_hs_offchip_param
);
3324 /* Flush the context to re-emit the init_config state.
3325 * This is done only once in a lifetime of a context.
3327 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3328 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3329 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3332 static void si_update_vgt_shader_config(struct si_context
*sctx
)
3334 /* Calculate the index of the config.
3335 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3336 unsigned index
= 2*!!sctx
->tes_shader
.cso
+ !!sctx
->gs_shader
.cso
;
3337 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[index
];
3340 uint32_t stages
= 0;
3342 *pm4
= CALLOC_STRUCT(si_pm4_state
);
3344 if (sctx
->tes_shader
.cso
) {
3345 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3346 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3348 if (sctx
->gs_shader
.cso
)
3349 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3351 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3353 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3354 } else if (sctx
->gs_shader
.cso
) {
3355 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3357 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3360 if (sctx
->chip_class
>= GFX9
)
3361 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3363 si_pm4_set_reg(*pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
3365 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
3368 bool si_update_shaders(struct si_context
*sctx
)
3370 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
3371 struct si_compiler_ctx_state compiler_state
;
3372 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3373 struct si_shader
*old_vs
= si_get_vs_state(sctx
);
3374 bool old_clip_disable
= old_vs
? old_vs
->key
.opt
.clip_disable
: false;
3375 struct si_shader
*old_ps
= sctx
->ps_shader
.current
;
3376 unsigned old_spi_shader_col_format
=
3377 old_ps
? old_ps
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
3380 compiler_state
.compiler
= &sctx
->compiler
;
3381 compiler_state
.debug
= sctx
->debug
;
3382 compiler_state
.is_debug_context
= sctx
->is_debug
;
3384 /* Update stages before GS. */
3385 if (sctx
->tes_shader
.cso
) {
3386 if (!sctx
->tess_rings
) {
3387 si_init_tess_factor_ring(sctx
);
3388 if (!sctx
->tess_rings
)
3393 if (sctx
->chip_class
<= GFX8
) {
3394 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
3398 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3401 if (sctx
->tcs_shader
.cso
) {
3402 r
= si_shader_select(ctx
, &sctx
->tcs_shader
,
3406 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
3408 if (!sctx
->fixed_func_tcs_shader
.cso
) {
3409 sctx
->fixed_func_tcs_shader
.cso
=
3410 si_create_fixed_func_tcs(sctx
);
3411 if (!sctx
->fixed_func_tcs_shader
.cso
)
3415 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
,
3419 si_pm4_bind_state(sctx
, hs
,
3420 sctx
->fixed_func_tcs_shader
.current
->pm4
);
3423 if (sctx
->gs_shader
.cso
) {
3425 if (sctx
->chip_class
<= GFX8
) {
3426 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
3430 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3434 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
3438 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3440 } else if (sctx
->gs_shader
.cso
) {
3441 if (sctx
->chip_class
<= GFX8
) {
3443 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
3447 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3449 si_pm4_bind_state(sctx
, ls
, NULL
);
3450 si_pm4_bind_state(sctx
, hs
, NULL
);
3454 r
= si_shader_select(ctx
, &sctx
->vs_shader
, &compiler_state
);
3457 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3458 si_pm4_bind_state(sctx
, ls
, NULL
);
3459 si_pm4_bind_state(sctx
, hs
, NULL
);
3463 if (sctx
->gs_shader
.cso
) {
3464 r
= si_shader_select(ctx
, &sctx
->gs_shader
, &compiler_state
);
3467 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3468 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
3470 if (!si_update_gs_ring_buffers(sctx
))
3473 si_pm4_bind_state(sctx
, gs
, NULL
);
3474 if (sctx
->chip_class
<= GFX8
)
3475 si_pm4_bind_state(sctx
, es
, NULL
);
3478 si_update_vgt_shader_config(sctx
);
3480 if (old_clip_disable
!= si_get_vs_state(sctx
)->key
.opt
.clip_disable
)
3481 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
3483 if (sctx
->ps_shader
.cso
) {
3484 unsigned db_shader_control
;
3486 r
= si_shader_select(ctx
, &sctx
->ps_shader
, &compiler_state
);
3489 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3492 sctx
->ps_shader
.cso
->db_shader_control
|
3493 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
3495 if (si_pm4_state_changed(sctx
, ps
) || si_pm4_state_changed(sctx
, vs
) ||
3496 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
3497 sctx
->flatshade
!= rs
->flatshade
) {
3498 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
3499 sctx
->flatshade
= rs
->flatshade
;
3500 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.spi_map
);
3503 if (sctx
->screen
->rbplus_allowed
&&
3504 si_pm4_state_changed(sctx
, ps
) &&
3506 old_spi_shader_col_format
!=
3507 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
))
3508 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3510 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
3511 sctx
->ps_db_shader_control
= db_shader_control
;
3512 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3513 if (sctx
->screen
->dpbb_allowed
)
3514 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3517 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
3518 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
3519 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3521 if (sctx
->chip_class
== GFX6
)
3522 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3524 if (sctx
->framebuffer
.nr_samples
<= 1)
3525 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
3529 if (si_pm4_state_enabled_and_changed(sctx
, ls
) ||
3530 si_pm4_state_enabled_and_changed(sctx
, hs
) ||
3531 si_pm4_state_enabled_and_changed(sctx
, es
) ||
3532 si_pm4_state_enabled_and_changed(sctx
, gs
) ||
3533 si_pm4_state_enabled_and_changed(sctx
, vs
) ||
3534 si_pm4_state_enabled_and_changed(sctx
, ps
)) {
3535 if (!si_update_spi_tmpring_size(sctx
))
3539 if (sctx
->chip_class
>= GFX7
) {
3540 if (si_pm4_state_enabled_and_changed(sctx
, ls
))
3541 sctx
->prefetch_L2_mask
|= SI_PREFETCH_LS
;
3542 else if (!sctx
->queued
.named
.ls
)
3543 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_LS
;
3545 if (si_pm4_state_enabled_and_changed(sctx
, hs
))
3546 sctx
->prefetch_L2_mask
|= SI_PREFETCH_HS
;
3547 else if (!sctx
->queued
.named
.hs
)
3548 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_HS
;
3550 if (si_pm4_state_enabled_and_changed(sctx
, es
))
3551 sctx
->prefetch_L2_mask
|= SI_PREFETCH_ES
;
3552 else if (!sctx
->queued
.named
.es
)
3553 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_ES
;
3555 if (si_pm4_state_enabled_and_changed(sctx
, gs
))
3556 sctx
->prefetch_L2_mask
|= SI_PREFETCH_GS
;
3557 else if (!sctx
->queued
.named
.gs
)
3558 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_GS
;
3560 if (si_pm4_state_enabled_and_changed(sctx
, vs
))
3561 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VS
;
3562 else if (!sctx
->queued
.named
.vs
)
3563 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_VS
;
3565 if (si_pm4_state_enabled_and_changed(sctx
, ps
))
3566 sctx
->prefetch_L2_mask
|= SI_PREFETCH_PS
;
3567 else if (!sctx
->queued
.named
.ps
)
3568 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_PS
;
3571 sctx
->do_update_shaders
= false;
3575 static void si_emit_scratch_state(struct si_context
*sctx
)
3577 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3579 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
3580 sctx
->spi_tmpring_size
);
3582 if (sctx
->scratch_buffer
) {
3583 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3584 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
3585 RADEON_PRIO_SCRATCH_BUFFER
);
3589 void si_init_shader_functions(struct si_context
*sctx
)
3591 sctx
->atoms
.s
.spi_map
.emit
= si_emit_spi_map
;
3592 sctx
->atoms
.s
.scratch_state
.emit
= si_emit_scratch_state
;
3594 sctx
->b
.create_vs_state
= si_create_shader_selector
;
3595 sctx
->b
.create_tcs_state
= si_create_shader_selector
;
3596 sctx
->b
.create_tes_state
= si_create_shader_selector
;
3597 sctx
->b
.create_gs_state
= si_create_shader_selector
;
3598 sctx
->b
.create_fs_state
= si_create_shader_selector
;
3600 sctx
->b
.bind_vs_state
= si_bind_vs_shader
;
3601 sctx
->b
.bind_tcs_state
= si_bind_tcs_shader
;
3602 sctx
->b
.bind_tes_state
= si_bind_tes_shader
;
3603 sctx
->b
.bind_gs_state
= si_bind_gs_shader
;
3604 sctx
->b
.bind_fs_state
= si_bind_ps_shader
;
3606 sctx
->b
.delete_vs_state
= si_delete_shader_selector
;
3607 sctx
->b
.delete_tcs_state
= si_delete_shader_selector
;
3608 sctx
->b
.delete_tes_state
= si_delete_shader_selector
;
3609 sctx
->b
.delete_gs_state
= si_delete_shader_selector
;
3610 sctx
->b
.delete_fs_state
= si_delete_shader_selector
;