2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
44 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
47 void *si_get_ir_binary(struct si_shader_selector
*sel
)
54 ir_binary
= sel
->tokens
;
55 ir_size
= tgsi_num_tokens(sel
->tokens
) *
56 sizeof(struct tgsi_token
);
61 nir_serialize(&blob
, sel
->nir
);
62 ir_binary
= blob
.data
;
66 unsigned size
= 4 + ir_size
+ sizeof(sel
->so
);
67 char *result
= (char*)MALLOC(size
);
71 *((uint32_t*)result
) = size
;
72 memcpy(result
+ 4, ir_binary
, ir_size
);
73 memcpy(result
+ 4 + ir_size
, &sel
->so
, sizeof(sel
->so
));
81 /** Copy "data" to "ptr" and return the next dword following copied data. */
82 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
84 /* data may be NULL if size == 0 */
86 memcpy(ptr
, data
, size
);
87 ptr
+= DIV_ROUND_UP(size
, 4);
91 /** Read data from "ptr". Return the next dword following the data. */
92 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
94 memcpy(data
, ptr
, size
);
95 ptr
+= DIV_ROUND_UP(size
, 4);
100 * Write the size as uint followed by the data. Return the next dword
101 * following the copied data.
103 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
106 return write_data(ptr
, data
, size
);
110 * Read the size as uint followed by the data. Return both via parameters.
111 * Return the next dword following the data.
113 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
116 assert(*data
== NULL
);
119 *data
= malloc(*size
);
120 return read_data(ptr
, *data
, *size
);
124 * Return the shader binary in a buffer. The first 4 bytes contain its size
127 static void *si_get_shader_binary(struct si_shader
*shader
)
129 /* There is always a size of data followed by the data itself. */
130 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
131 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
133 /* Refuse to allocate overly large buffers and guard against integer
135 if (shader
->binary
.elf_size
> UINT_MAX
/ 4 ||
136 llvm_ir_size
> UINT_MAX
/ 4)
141 4 + /* CRC32 of the data below */
142 align(sizeof(shader
->config
), 4) +
143 align(sizeof(shader
->info
), 4) +
144 4 + align(shader
->binary
.elf_size
, 4) +
145 4 + align(llvm_ir_size
, 4);
146 void *buffer
= CALLOC(1, size
);
147 uint32_t *ptr
= (uint32_t*)buffer
;
153 ptr
++; /* CRC32 is calculated at the end. */
155 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
156 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
157 ptr
= write_chunk(ptr
, shader
->binary
.elf_buffer
, shader
->binary
.elf_size
);
158 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
159 assert((char *)ptr
- (char *)buffer
== size
);
162 ptr
= (uint32_t*)buffer
;
164 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
169 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
171 uint32_t *ptr
= (uint32_t*)binary
;
172 uint32_t size
= *ptr
++;
173 uint32_t crc32
= *ptr
++;
177 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
178 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
182 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
183 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
184 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.elf_buffer
,
186 shader
->binary
.elf_size
= elf_size
;
187 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
193 * Insert a shader into the cache. It's assumed the shader is not in the cache.
194 * Use si_shader_cache_load_shader before calling this.
196 * Returns false on failure, in which case the ir_binary should be freed.
198 bool si_shader_cache_insert_shader(struct si_screen
*sscreen
, void *ir_binary
,
199 struct si_shader
*shader
,
200 bool insert_into_disk_cache
)
203 struct hash_entry
*entry
;
204 uint8_t key
[CACHE_KEY_SIZE
];
206 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
208 return false; /* already added */
210 hw_binary
= si_get_shader_binary(shader
);
214 if (_mesa_hash_table_insert(sscreen
->shader_cache
, ir_binary
,
215 hw_binary
) == NULL
) {
220 if (sscreen
->disk_shader_cache
&& insert_into_disk_cache
) {
221 disk_cache_compute_key(sscreen
->disk_shader_cache
, ir_binary
,
222 *((uint32_t *)ir_binary
), key
);
223 disk_cache_put(sscreen
->disk_shader_cache
, key
, hw_binary
,
224 *((uint32_t *) hw_binary
), NULL
);
230 bool si_shader_cache_load_shader(struct si_screen
*sscreen
, void *ir_binary
,
231 struct si_shader
*shader
)
233 struct hash_entry
*entry
=
234 _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
236 if (sscreen
->disk_shader_cache
) {
237 unsigned char sha1
[CACHE_KEY_SIZE
];
238 size_t tg_size
= *((uint32_t *) ir_binary
);
240 disk_cache_compute_key(sscreen
->disk_shader_cache
,
241 ir_binary
, tg_size
, sha1
);
245 disk_cache_get(sscreen
->disk_shader_cache
,
250 if (binary_size
< sizeof(uint32_t) ||
251 *((uint32_t*)buffer
) != binary_size
) {
252 /* Something has gone wrong discard the item
253 * from the cache and rebuild/link from
256 assert(!"Invalid radeonsi shader disk cache "
259 disk_cache_remove(sscreen
->disk_shader_cache
,
266 if (!si_load_shader_binary(shader
, buffer
)) {
272 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
,
279 if (si_load_shader_binary(shader
, entry
->data
))
284 p_atomic_inc(&sscreen
->num_shader_cache_hits
);
288 static uint32_t si_shader_cache_key_hash(const void *key
)
290 /* The first dword is the key size. */
291 return util_hash_crc32(key
, *(uint32_t*)key
);
294 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
296 uint32_t *keya
= (uint32_t*)a
;
297 uint32_t *keyb
= (uint32_t*)b
;
299 /* The first dword is the key size. */
303 return memcmp(keya
, keyb
, *keya
) == 0;
306 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
308 FREE((void*)entry
->key
);
312 bool si_init_shader_cache(struct si_screen
*sscreen
)
314 (void) mtx_init(&sscreen
->shader_cache_mutex
, mtx_plain
);
315 sscreen
->shader_cache
=
316 _mesa_hash_table_create(NULL
,
317 si_shader_cache_key_hash
,
318 si_shader_cache_key_equals
);
320 return sscreen
->shader_cache
!= NULL
;
323 void si_destroy_shader_cache(struct si_screen
*sscreen
)
325 if (sscreen
->shader_cache
)
326 _mesa_hash_table_destroy(sscreen
->shader_cache
,
327 si_destroy_shader_cache_entry
);
328 mtx_destroy(&sscreen
->shader_cache_mutex
);
333 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
334 const struct si_shader_selector
*tes
,
335 struct si_pm4_state
*pm4
)
337 const struct tgsi_shader_info
*info
= &tes
->info
;
338 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
339 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
340 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
341 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
342 unsigned type
, partitioning
, topology
, distribution_mode
;
344 switch (tes_prim_mode
) {
345 case PIPE_PRIM_LINES
:
346 type
= V_028B6C_TESS_ISOLINE
;
348 case PIPE_PRIM_TRIANGLES
:
349 type
= V_028B6C_TESS_TRIANGLE
;
351 case PIPE_PRIM_QUADS
:
352 type
= V_028B6C_TESS_QUAD
;
359 switch (tes_spacing
) {
360 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
361 partitioning
= V_028B6C_PART_FRAC_ODD
;
363 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
364 partitioning
= V_028B6C_PART_FRAC_EVEN
;
366 case PIPE_TESS_SPACING_EQUAL
:
367 partitioning
= V_028B6C_PART_INTEGER
;
375 topology
= V_028B6C_OUTPUT_POINT
;
376 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
377 topology
= V_028B6C_OUTPUT_LINE
;
378 else if (tes_vertex_order_cw
)
379 /* for some reason, this must be the other way around */
380 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
382 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
384 if (sscreen
->has_distributed_tess
) {
385 if (sscreen
->info
.family
== CHIP_FIJI
||
386 sscreen
->info
.family
>= CHIP_POLARIS10
)
387 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
389 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
391 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
394 pm4
->shader
->vgt_tf_param
= S_028B6C_TYPE(type
) |
395 S_028B6C_PARTITIONING(partitioning
) |
396 S_028B6C_TOPOLOGY(topology
) |
397 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
400 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
401 * whether the "fractional odd" tessellation spacing is used.
403 * Possible VGT configurations and which state should set the register:
405 * Reg set in | VGT shader configuration | Value
406 * ------------------------------------------------------
408 * VS as ES | ES -> GS -> VS | 30
409 * TES as VS | LS -> HS -> VS | 14 or 30
410 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
412 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
414 static void polaris_set_vgt_vertex_reuse(struct si_screen
*sscreen
,
415 struct si_shader_selector
*sel
,
416 struct si_shader
*shader
,
417 struct si_pm4_state
*pm4
)
419 unsigned type
= sel
->type
;
421 if (sscreen
->info
.family
< CHIP_POLARIS10
)
424 /* VS as VS, or VS as ES: */
425 if ((type
== PIPE_SHADER_VERTEX
&&
427 (!shader
->key
.as_ls
&& !shader
->is_gs_copy_shader
))) ||
428 /* TES as VS, or TES as ES: */
429 type
== PIPE_SHADER_TESS_EVAL
) {
430 unsigned vtx_reuse_depth
= 30;
432 if (type
== PIPE_SHADER_TESS_EVAL
&&
433 sel
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] ==
434 PIPE_TESS_SPACING_FRACTIONAL_ODD
)
435 vtx_reuse_depth
= 14;
438 pm4
->shader
->vgt_vertex_reuse_block_cntl
= vtx_reuse_depth
;
442 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
445 si_pm4_clear_state(shader
->pm4
);
447 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
450 shader
->pm4
->shader
= shader
;
453 fprintf(stderr
, "radeonsi: Failed to create pm4 state.\n");
458 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs
)
460 /* Add the pointer to VBO descriptors. */
461 return num_always_on_user_sgprs
+ 1;
464 static void si_shader_ls(struct si_screen
*sscreen
, struct si_shader
*shader
)
466 struct si_pm4_state
*pm4
;
467 unsigned vgpr_comp_cnt
;
470 assert(sscreen
->info
.chip_class
<= GFX8
);
472 pm4
= si_get_shader_pm4_state(shader
);
476 va
= shader
->bo
->gpu_address
;
477 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
479 /* We need at least 2 components for LS.
480 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
481 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
483 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
485 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
486 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
488 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
489 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
490 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt
) |
491 S_00B528_DX10_CLAMP(1) |
492 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
493 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
)) |
494 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
497 static void si_shader_hs(struct si_screen
*sscreen
, struct si_shader
*shader
)
499 struct si_pm4_state
*pm4
;
501 unsigned ls_vgpr_comp_cnt
= 0;
503 pm4
= si_get_shader_pm4_state(shader
);
507 va
= shader
->bo
->gpu_address
;
508 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
510 if (sscreen
->info
.chip_class
>= GFX9
) {
511 if (sscreen
->info
.chip_class
>= GFX10
) {
512 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
513 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
515 si_pm4_set_reg(pm4
, R_00B410_SPI_SHADER_PGM_LO_LS
, va
>> 8);
516 si_pm4_set_reg(pm4
, R_00B414_SPI_SHADER_PGM_HI_LS
, S_00B414_MEM_BASE(va
>> 40));
519 /* We need at least 2 components for LS.
520 * GFX9 VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
521 * GFX10 VGPR0-3: (VertexID, RelAutoindex, UserVGPR1, InstanceID).
522 * On gfx9, StepRate0 is set to 1 so that VGPR3 doesn't have to
525 ls_vgpr_comp_cnt
= 1;
526 if (shader
->info
.uses_instanceid
) {
527 if (sscreen
->info
.chip_class
>= GFX10
)
528 ls_vgpr_comp_cnt
= 3;
530 ls_vgpr_comp_cnt
= 2;
533 unsigned num_user_sgprs
=
534 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR
);
536 shader
->config
.rsrc2
=
537 S_00B42C_USER_SGPR(num_user_sgprs
) |
538 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
540 if (sscreen
->info
.chip_class
>= GFX10
)
541 shader
->config
.rsrc2
|= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
543 shader
->config
.rsrc2
|= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
545 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
546 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, S_00B424_MEM_BASE(va
>> 40));
548 shader
->config
.rsrc2
=
549 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR
) |
550 S_00B42C_OC_LDS_EN(1) |
551 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
554 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
555 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
556 (sscreen
->info
.chip_class
<= GFX9
?
557 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) : 0) |
558 S_00B428_DX10_CLAMP(1) |
559 S_00B428_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
560 S_00B428_FLOAT_MODE(shader
->config
.float_mode
) |
561 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt
));
563 if (sscreen
->info
.chip_class
<= GFX8
) {
564 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
565 shader
->config
.rsrc2
);
569 static void si_emit_shader_es(struct si_context
*sctx
)
571 struct si_shader
*shader
= sctx
->queued
.named
.es
->shader
;
572 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
577 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
578 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
579 shader
->selector
->esgs_itemsize
/ 4);
581 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
582 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
583 SI_TRACKED_VGT_TF_PARAM
,
584 shader
->vgt_tf_param
);
586 if (shader
->vgt_vertex_reuse_block_cntl
)
587 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
588 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
589 shader
->vgt_vertex_reuse_block_cntl
);
591 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
592 sctx
->context_roll
= true;
595 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
597 struct si_pm4_state
*pm4
;
598 unsigned num_user_sgprs
;
599 unsigned vgpr_comp_cnt
;
603 assert(sscreen
->info
.chip_class
<= GFX8
);
605 pm4
= si_get_shader_pm4_state(shader
);
609 pm4
->atom
.emit
= si_emit_shader_es
;
610 va
= shader
->bo
->gpu_address
;
611 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
613 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
614 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
615 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
616 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
617 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
618 vgpr_comp_cnt
= shader
->selector
->info
.uses_primid
? 3 : 2;
619 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
621 unreachable("invalid shader selector type");
623 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
625 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
626 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
627 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
628 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
629 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
630 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
631 S_00B328_DX10_CLAMP(1) |
632 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
633 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
634 S_00B32C_USER_SGPR(num_user_sgprs
) |
635 S_00B32C_OC_LDS_EN(oc_lds_en
) |
636 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
638 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
639 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
641 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
644 void gfx9_get_gs_info(struct si_shader_selector
*es
,
645 struct si_shader_selector
*gs
,
646 struct gfx9_gs_info
*out
)
648 unsigned gs_num_invocations
= MAX2(gs
->gs_num_invocations
, 1);
649 unsigned input_prim
= gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
650 bool uses_adjacency
= input_prim
>= PIPE_PRIM_LINES_ADJACENCY
&&
651 input_prim
<= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
;
653 /* All these are in dwords: */
654 /* We can't allow using the whole LDS, because GS waves compete with
655 * other shader stages for LDS space. */
656 const unsigned max_lds_size
= 8 * 1024;
657 const unsigned esgs_itemsize
= es
->esgs_itemsize
/ 4;
658 unsigned esgs_lds_size
;
660 /* All these are per subgroup: */
661 const unsigned max_out_prims
= 32 * 1024;
662 const unsigned max_es_verts
= 255;
663 const unsigned ideal_gs_prims
= 64;
664 unsigned max_gs_prims
, gs_prims
;
665 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
667 if (uses_adjacency
|| gs_num_invocations
> 1)
668 max_gs_prims
= 127 / gs_num_invocations
;
672 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
673 * Make sure we don't go over the maximum value.
675 if (gs
->gs_max_out_vertices
> 0) {
676 max_gs_prims
= MIN2(max_gs_prims
,
678 (gs
->gs_max_out_vertices
* gs_num_invocations
));
680 assert(max_gs_prims
> 0);
682 /* If the primitive has adjacency, halve the number of vertices
683 * that will be reused in multiple primitives.
685 min_es_verts
= gs
->gs_input_verts_per_prim
/ (uses_adjacency
? 2 : 1);
687 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
688 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
690 /* Compute ESGS LDS size based on the worst case number of ES vertices
691 * needed to create the target number of GS prims per subgroup.
693 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
695 /* If total LDS usage is too big, refactor partitions based on ratio
696 * of ESGS item sizes.
698 if (esgs_lds_size
> max_lds_size
) {
699 /* Our target GS Prims Per Subgroup was too large. Calculate
700 * the maximum number of GS Prims Per Subgroup that will fit
701 * into LDS, capped by the maximum that the hardware can support.
703 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
705 assert(gs_prims
> 0);
706 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
709 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
710 assert(esgs_lds_size
<= max_lds_size
);
713 /* Now calculate remaining ESGS information. */
715 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
717 es_verts
= max_es_verts
;
719 /* Vertices for adjacency primitives are not always reused, so restore
720 * it for ES_VERTS_PER_SUBGRP.
722 min_es_verts
= gs
->gs_input_verts_per_prim
;
724 /* For normal primitives, the VGT only checks if they are past the ES
725 * verts per subgroup after allocating a full GS primitive and if they
726 * are, kick off a new subgroup. But if those additional ES verts are
727 * unique (e.g. not reused) we need to make sure there is enough LDS
728 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
730 es_verts
-= min_es_verts
- 1;
732 out
->es_verts_per_subgroup
= es_verts
;
733 out
->gs_prims_per_subgroup
= gs_prims
;
734 out
->gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
735 out
->max_prims_per_subgroup
= out
->gs_inst_prims_in_subgroup
*
736 gs
->gs_max_out_vertices
;
737 out
->esgs_ring_size
= 4 * esgs_lds_size
;
739 assert(out
->max_prims_per_subgroup
<= max_out_prims
);
742 static void si_emit_shader_gs(struct si_context
*sctx
)
744 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
745 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
750 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
751 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
752 radeon_opt_set_context_reg3(sctx
, R_028A60_VGT_GSVS_RING_OFFSET_1
,
753 SI_TRACKED_VGT_GSVS_RING_OFFSET_1
,
754 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
,
755 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
,
756 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
);
758 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
759 radeon_opt_set_context_reg(sctx
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
,
760 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE
,
761 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
);
763 /* R_028B38_VGT_GS_MAX_VERT_OUT */
764 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
765 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
766 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
);
768 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
769 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
770 radeon_opt_set_context_reg4(sctx
, R_028B5C_VGT_GS_VERT_ITEMSIZE
,
771 SI_TRACKED_VGT_GS_VERT_ITEMSIZE
,
772 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
,
773 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
,
774 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
,
775 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
);
777 /* R_028B90_VGT_GS_INSTANCE_CNT */
778 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
,
779 SI_TRACKED_VGT_GS_INSTANCE_CNT
,
780 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
);
782 if (sctx
->chip_class
>= GFX9
) {
783 /* R_028A44_VGT_GS_ONCHIP_CNTL */
784 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
785 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
786 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
);
787 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
788 radeon_opt_set_context_reg(sctx
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
789 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
790 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
);
791 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
792 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
793 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
794 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
);
796 if (shader
->key
.part
.gs
.es
->type
== PIPE_SHADER_TESS_EVAL
)
797 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
798 SI_TRACKED_VGT_TF_PARAM
,
799 shader
->vgt_tf_param
);
800 if (shader
->vgt_vertex_reuse_block_cntl
)
801 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
802 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
803 shader
->vgt_vertex_reuse_block_cntl
);
806 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
807 sctx
->context_roll
= true;
810 static void si_shader_gs(struct si_screen
*sscreen
, struct si_shader
*shader
)
812 struct si_shader_selector
*sel
= shader
->selector
;
813 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
814 unsigned gs_num_invocations
= sel
->gs_num_invocations
;
815 struct si_pm4_state
*pm4
;
817 unsigned max_stream
= sel
->max_gs_stream
;
820 pm4
= si_get_shader_pm4_state(shader
);
824 pm4
->atom
.emit
= si_emit_shader_gs
;
826 offset
= num_components
[0] * sel
->gs_max_out_vertices
;
827 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
= offset
;
830 offset
+= num_components
[1] * sel
->gs_max_out_vertices
;
831 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
= offset
;
834 offset
+= num_components
[2] * sel
->gs_max_out_vertices
;
835 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
= offset
;
838 offset
+= num_components
[3] * sel
->gs_max_out_vertices
;
839 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
= offset
;
841 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
842 assert(offset
< (1 << 15));
844 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
= sel
->gs_max_out_vertices
;
846 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
= num_components
[0];
847 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
= (max_stream
>= 1) ? num_components
[1] : 0;
848 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
= (max_stream
>= 2) ? num_components
[2] : 0;
849 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
= (max_stream
>= 3) ? num_components
[3] : 0;
851 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
= S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
852 S_028B90_ENABLE(gs_num_invocations
> 0);
854 va
= shader
->bo
->gpu_address
;
855 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
857 if (sscreen
->info
.chip_class
>= GFX9
) {
858 unsigned input_prim
= sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
859 unsigned es_type
= shader
->key
.part
.gs
.es
->type
;
860 unsigned es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
862 if (es_type
== PIPE_SHADER_VERTEX
)
863 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
864 es_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
865 else if (es_type
== PIPE_SHADER_TESS_EVAL
)
866 es_vgpr_comp_cnt
= shader
->key
.part
.gs
.es
->info
.uses_primid
? 3 : 2;
868 unreachable("invalid shader selector type");
870 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
871 * VGPR[0:4] are always loaded.
873 if (sel
->info
.uses_invocationid
)
874 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
875 else if (sel
->info
.uses_primid
)
876 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
877 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
878 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
880 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
882 unsigned num_user_sgprs
;
883 if (es_type
== PIPE_SHADER_VERTEX
)
884 num_user_sgprs
= si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR
);
886 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
888 if (sscreen
->info
.chip_class
>= GFX10
) {
889 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
890 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
892 si_pm4_set_reg(pm4
, R_00B210_SPI_SHADER_PGM_LO_ES
, va
>> 8);
893 si_pm4_set_reg(pm4
, R_00B214_SPI_SHADER_PGM_HI_ES
, S_00B214_MEM_BASE(va
>> 40));
897 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
898 S_00B228_DX10_CLAMP(1) |
899 S_00B228_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
900 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
901 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
);
903 S_00B22C_USER_SGPR(num_user_sgprs
) |
904 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
905 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
906 S_00B22C_LDS_SIZE(shader
->config
.lds_size
) |
907 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
909 if (sscreen
->info
.chip_class
>= GFX10
) {
910 rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
912 rsrc1
|= S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
913 rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
916 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, rsrc1
);
917 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
, rsrc2
);
919 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
=
920 S_028A44_ES_VERTS_PER_SUBGRP(shader
->gs_info
.es_verts_per_subgroup
) |
921 S_028A44_GS_PRIMS_PER_SUBGRP(shader
->gs_info
.gs_prims_per_subgroup
) |
922 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader
->gs_info
.gs_inst_prims_in_subgroup
);
923 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
=
924 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader
->gs_info
.max_prims_per_subgroup
);
925 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
=
926 shader
->key
.part
.gs
.es
->esgs_itemsize
/ 4;
928 if (es_type
== PIPE_SHADER_TESS_EVAL
)
929 si_set_tesseval_regs(sscreen
, shader
->key
.part
.gs
.es
, pm4
);
931 polaris_set_vgt_vertex_reuse(sscreen
, shader
->key
.part
.gs
.es
,
934 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
935 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, S_00B224_MEM_BASE(va
>> 40));
937 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
938 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
939 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
940 S_00B228_DX10_CLAMP(1) |
941 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
942 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
943 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR
) |
944 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
948 /* Common tail code for NGG primitive shaders. */
949 static void gfx10_emit_shader_ngg_tail(struct si_context
*sctx
,
950 struct si_shader
*shader
,
951 unsigned initial_cdw
)
953 radeon_opt_set_context_reg(sctx
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
954 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP
,
955 shader
->ctx_reg
.ngg
.ge_max_output_per_subgroup
);
956 radeon_opt_set_context_reg(sctx
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
957 SI_TRACKED_GE_NGG_SUBGRP_CNTL
,
958 shader
->ctx_reg
.ngg
.ge_ngg_subgrp_cntl
);
959 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
,
960 SI_TRACKED_VGT_PRIMITIVEID_EN
,
961 shader
->ctx_reg
.ngg
.vgt_primitiveid_en
);
962 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
963 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
964 shader
->ctx_reg
.ngg
.vgt_gs_onchip_cntl
);
965 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
,
966 SI_TRACKED_VGT_GS_INSTANCE_CNT
,
967 shader
->ctx_reg
.ngg
.vgt_gs_instance_cnt
);
968 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
969 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
970 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
);
971 radeon_opt_set_context_reg(sctx
, R_028AB4_VGT_REUSE_OFF
,
972 SI_TRACKED_VGT_REUSE_OFF
,
973 shader
->ctx_reg
.ngg
.vgt_reuse_off
);
974 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
,
975 SI_TRACKED_SPI_VS_OUT_CONFIG
,
976 shader
->ctx_reg
.ngg
.spi_vs_out_config
);
977 radeon_opt_set_context_reg2(sctx
, R_028708_SPI_SHADER_IDX_FORMAT
,
978 SI_TRACKED_SPI_SHADER_IDX_FORMAT
,
979 shader
->ctx_reg
.ngg
.spi_shader_idx_format
,
980 shader
->ctx_reg
.ngg
.spi_shader_pos_format
);
981 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
,
982 SI_TRACKED_PA_CL_VTE_CNTL
,
983 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
);
985 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
986 sctx
->context_roll
= true;
988 if (shader
->ge_cntl
!= sctx
->last_multi_vgt_param
) {
989 radeon_set_uconfig_reg(sctx
->gfx_cs
, R_03096C_GE_CNTL
, shader
->ge_cntl
);
990 sctx
->last_multi_vgt_param
= shader
->ge_cntl
;
994 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context
*sctx
)
996 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
997 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1002 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1005 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context
*sctx
)
1007 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1008 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1013 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1014 SI_TRACKED_VGT_TF_PARAM
,
1015 shader
->vgt_tf_param
);
1017 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1020 static void gfx10_emit_shader_ngg_notess_gs(struct si_context
*sctx
)
1022 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1023 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1028 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
1029 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
1030 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
);
1032 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1035 static void gfx10_emit_shader_ngg_tess_gs(struct si_context
*sctx
)
1037 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1038 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1043 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
1044 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
1045 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
);
1046 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1047 SI_TRACKED_VGT_TF_PARAM
,
1048 shader
->vgt_tf_param
);
1050 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1054 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1057 static void gfx10_shader_ngg(struct si_screen
*sscreen
, struct si_shader
*shader
)
1059 const struct si_shader_selector
*gs_sel
= shader
->selector
;
1060 const struct tgsi_shader_info
*gs_info
= &gs_sel
->info
;
1061 enum pipe_shader_type gs_type
= shader
->selector
->type
;
1062 const struct si_shader_selector
*es_sel
=
1063 shader
->previous_stage_sel
? shader
->previous_stage_sel
: shader
->selector
;
1064 const struct tgsi_shader_info
*es_info
= &es_sel
->info
;
1065 enum pipe_shader_type es_type
= es_sel
->type
;
1066 unsigned num_user_sgprs
;
1067 unsigned nparams
, es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
1069 unsigned window_space
=
1070 gs_info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
1071 bool es_enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| es_info
->uses_primid
;
1072 unsigned gs_num_invocations
= MAX2(gs_sel
->gs_num_invocations
, 1);
1073 unsigned input_prim
=
1074 gs_type
== PIPE_SHADER_GEOMETRY
?
1075 gs_info
->properties
[TGSI_PROPERTY_GS_INPUT_PRIM
] :
1076 PIPE_PRIM_TRIANGLES
; /* TODO: Optimize when primtype is known */
1077 bool break_wave_at_eoi
= false;
1078 struct si_pm4_state
*pm4
= si_get_shader_pm4_state(shader
);
1082 if (es_type
== PIPE_SHADER_TESS_EVAL
) {
1083 pm4
->atom
.emit
= gs_type
== PIPE_SHADER_GEOMETRY
? gfx10_emit_shader_ngg_tess_gs
1084 : gfx10_emit_shader_ngg_tess_nogs
;
1086 pm4
->atom
.emit
= gs_type
== PIPE_SHADER_GEOMETRY
? gfx10_emit_shader_ngg_notess_gs
1087 : gfx10_emit_shader_ngg_notess_nogs
;
1090 va
= shader
->bo
->gpu_address
;
1091 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1093 if (es_type
== PIPE_SHADER_VERTEX
) {
1094 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
1095 es_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 3 : 0;
1097 if (es_info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
]) {
1098 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
1099 es_info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
1101 num_user_sgprs
= si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR
);
1104 assert(es_type
== PIPE_SHADER_TESS_EVAL
);
1105 es_vgpr_comp_cnt
= es_enable_prim_id
? 3 : 2;
1106 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
1108 if (es_enable_prim_id
|| gs_info
->uses_primid
)
1109 break_wave_at_eoi
= true;
1112 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1113 * VGPR[0:4] are always loaded.
1115 if (gs_info
->uses_invocationid
)
1116 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
1117 else if (gs_info
->uses_primid
)
1118 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
1119 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
1120 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
1122 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
1124 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
1125 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
1126 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
1127 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1128 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
1129 S_00B228_DX10_CLAMP(1) |
1130 S_00B228_MEM_ORDERED(1) |
1131 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
));
1132 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
1133 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0) |
1134 S_00B22C_USER_SGPR(num_user_sgprs
) |
1135 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
1136 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5) |
1137 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
1138 S_00B22C_LDS_SIZE(shader
->config
.lds_size
));
1140 /* TODO: Use NO_PC_EXPORT when applicable. */
1141 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1142 shader
->ctx_reg
.ngg
.spi_vs_out_config
=
1143 S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
1145 shader
->ctx_reg
.ngg
.spi_shader_idx_format
=
1146 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
);
1147 shader
->ctx_reg
.ngg
.spi_shader_pos_format
=
1148 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1149 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
1150 V_02870C_SPI_SHADER_4COMP
:
1151 V_02870C_SPI_SHADER_NONE
) |
1152 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
1153 V_02870C_SPI_SHADER_4COMP
:
1154 V_02870C_SPI_SHADER_NONE
) |
1155 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
1156 V_02870C_SPI_SHADER_4COMP
:
1157 V_02870C_SPI_SHADER_NONE
);
1159 shader
->ctx_reg
.ngg
.vgt_primitiveid_en
=
1160 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
1161 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id
);
1163 if (gs_type
== PIPE_SHADER_GEOMETRY
) {
1164 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
= es_sel
->esgs_itemsize
/ 4;
1165 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
= gs_sel
->gs_max_out_vertices
;
1167 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
= 1;
1170 if (es_type
== PIPE_SHADER_TESS_EVAL
)
1171 si_set_tesseval_regs(sscreen
, es_sel
, pm4
);
1173 shader
->ctx_reg
.ngg
.vgt_gs_onchip_cntl
=
1174 S_028A44_ES_VERTS_PER_SUBGRP(shader
->ngg
.hw_max_esverts
) |
1175 S_028A44_GS_PRIMS_PER_SUBGRP(shader
->ngg
.max_gsprims
) |
1176 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader
->ngg
.max_gsprims
* gs_num_invocations
);
1177 shader
->ctx_reg
.ngg
.ge_max_output_per_subgroup
=
1178 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader
->ngg
.max_out_verts
);
1179 shader
->ctx_reg
.ngg
.ge_ngg_subgrp_cntl
=
1180 S_028B4C_PRIM_AMP_FACTOR(shader
->ngg
.prim_amp_factor
) |
1181 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1182 shader
->ctx_reg
.ngg
.vgt_gs_instance_cnt
=
1183 S_028B90_CNT(gs_num_invocations
) |
1184 S_028B90_ENABLE(gs_num_invocations
> 1) |
1185 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1186 shader
->ngg
.max_vert_out_per_gs_instance
);
1189 S_03096C_PRIM_GRP_SIZE(shader
->ngg
.max_gsprims
) |
1190 S_03096C_VERT_GRP_SIZE(shader
->ngg
.hw_max_esverts
) |
1191 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
1194 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
=
1195 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1197 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
=
1198 S_028818_VTX_W0_FMT(1) |
1199 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1200 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1201 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1204 shader
->ctx_reg
.ngg
.vgt_reuse_off
=
1205 S_028AB4_REUSE_OFF(sscreen
->info
.family
== CHIP_NAVI10
&&
1206 sscreen
->info
.chip_external_rev
== 0x1 &&
1207 es_type
== PIPE_SHADER_TESS_EVAL
);
1210 static void si_emit_shader_vs(struct si_context
*sctx
)
1212 struct si_shader
*shader
= sctx
->queued
.named
.vs
->shader
;
1213 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1218 radeon_opt_set_context_reg(sctx
, R_028A40_VGT_GS_MODE
,
1219 SI_TRACKED_VGT_GS_MODE
,
1220 shader
->ctx_reg
.vs
.vgt_gs_mode
);
1221 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
,
1222 SI_TRACKED_VGT_PRIMITIVEID_EN
,
1223 shader
->ctx_reg
.vs
.vgt_primitiveid_en
);
1225 if (sctx
->chip_class
<= GFX8
) {
1226 radeon_opt_set_context_reg(sctx
, R_028AB4_VGT_REUSE_OFF
,
1227 SI_TRACKED_VGT_REUSE_OFF
,
1228 shader
->ctx_reg
.vs
.vgt_reuse_off
);
1231 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
,
1232 SI_TRACKED_SPI_VS_OUT_CONFIG
,
1233 shader
->ctx_reg
.vs
.spi_vs_out_config
);
1235 radeon_opt_set_context_reg(sctx
, R_02870C_SPI_SHADER_POS_FORMAT
,
1236 SI_TRACKED_SPI_SHADER_POS_FORMAT
,
1237 shader
->ctx_reg
.vs
.spi_shader_pos_format
);
1239 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
,
1240 SI_TRACKED_PA_CL_VTE_CNTL
,
1241 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
);
1243 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
1244 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1245 SI_TRACKED_VGT_TF_PARAM
,
1246 shader
->vgt_tf_param
);
1248 if (shader
->vgt_vertex_reuse_block_cntl
)
1249 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1250 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1251 shader
->vgt_vertex_reuse_block_cntl
);
1253 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1254 sctx
->context_roll
= true;
1258 * Compute the state for \p shader, which will run as a vertex shader on the
1261 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1262 * is the copy shader.
1264 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
1265 struct si_shader_selector
*gs
)
1267 const struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1268 struct si_pm4_state
*pm4
;
1269 unsigned num_user_sgprs
, vgpr_comp_cnt
;
1271 unsigned nparams
, oc_lds_en
;
1272 unsigned window_space
=
1273 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
1274 bool enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| info
->uses_primid
;
1276 pm4
= si_get_shader_pm4_state(shader
);
1280 pm4
->atom
.emit
= si_emit_shader_vs
;
1282 /* We always write VGT_GS_MODE in the VS state, because every switch
1283 * between different shader pipelines involving a different GS or no
1284 * GS at all involves a switch of the VS (different GS use different
1285 * copy shaders). On the other hand, when the API switches from a GS to
1286 * no GS and then back to the same GS used originally, the GS state is
1290 unsigned mode
= V_028A40_GS_OFF
;
1292 /* PrimID needs GS scenario A. */
1294 mode
= V_028A40_GS_SCENARIO_A
;
1296 shader
->ctx_reg
.vs
.vgt_gs_mode
= S_028A40_MODE(mode
);
1297 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= enable_prim_id
;
1299 shader
->ctx_reg
.vs
.vgt_gs_mode
= ac_vgt_gs_mode(gs
->gs_max_out_vertices
,
1300 sscreen
->info
.chip_class
);
1301 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= 0;
1304 if (sscreen
->info
.chip_class
<= GFX8
) {
1305 /* Reuse needs to be set off if we write oViewport. */
1306 shader
->ctx_reg
.vs
.vgt_reuse_off
=
1307 S_028AB4_REUSE_OFF(info
->writes_viewport_index
);
1310 va
= shader
->bo
->gpu_address
;
1311 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1314 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
1315 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
1316 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
1317 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1318 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1319 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1321 vgpr_comp_cnt
= enable_prim_id
? 2 : (shader
->info
.uses_instanceid
? 1 : 0);
1323 if (info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
]) {
1324 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
1325 info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
1327 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
1329 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
1330 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
1331 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
1333 unreachable("invalid shader selector type");
1335 /* VS is required to export at least one param. */
1336 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1337 shader
->ctx_reg
.vs
.spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
1339 shader
->ctx_reg
.vs
.spi_shader_pos_format
=
1340 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1341 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
1342 V_02870C_SPI_SHADER_4COMP
:
1343 V_02870C_SPI_SHADER_NONE
) |
1344 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
1345 V_02870C_SPI_SHADER_4COMP
:
1346 V_02870C_SPI_SHADER_NONE
) |
1347 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
1348 V_02870C_SPI_SHADER_4COMP
:
1349 V_02870C_SPI_SHADER_NONE
);
1351 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
1353 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
1354 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, S_00B124_MEM_BASE(va
>> 40));
1355 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
1356 S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1357 S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
1358 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
1359 S_00B128_DX10_CLAMP(1) |
1360 S_00B128_FLOAT_MODE(shader
->config
.float_mode
));
1361 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
1362 S_00B12C_USER_SGPR(num_user_sgprs
) |
1363 S_00B12C_OC_LDS_EN(oc_lds_en
) |
1364 S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
1365 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
1366 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
1367 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
1368 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
) |
1369 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1372 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1373 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1375 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1376 S_028818_VTX_W0_FMT(1) |
1377 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1378 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1379 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1381 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
1382 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
1384 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
1387 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
1389 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
1390 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
1391 !!(info
->colors_read
& 0xf0);
1392 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
1393 (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
1395 assert(num_interp
<= 32);
1396 return MIN2(num_interp
, 32);
1399 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
1401 unsigned value
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
1402 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
1404 /* If the i-th target format is set, all previous target formats must
1405 * be non-zero to avoid hangs.
1407 for (i
= 0; i
< num_targets
; i
++)
1408 if (!(value
& (0xf << (i
* 4))))
1409 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
1414 static void si_emit_shader_ps(struct si_context
*sctx
)
1416 struct si_shader
*shader
= sctx
->queued
.named
.ps
->shader
;
1417 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1422 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1423 radeon_opt_set_context_reg2(sctx
, R_0286CC_SPI_PS_INPUT_ENA
,
1424 SI_TRACKED_SPI_PS_INPUT_ENA
,
1425 shader
->ctx_reg
.ps
.spi_ps_input_ena
,
1426 shader
->ctx_reg
.ps
.spi_ps_input_addr
);
1428 radeon_opt_set_context_reg(sctx
, R_0286E0_SPI_BARYC_CNTL
,
1429 SI_TRACKED_SPI_BARYC_CNTL
,
1430 shader
->ctx_reg
.ps
.spi_baryc_cntl
);
1431 radeon_opt_set_context_reg(sctx
, R_0286D8_SPI_PS_IN_CONTROL
,
1432 SI_TRACKED_SPI_PS_IN_CONTROL
,
1433 shader
->ctx_reg
.ps
.spi_ps_in_control
);
1435 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1436 radeon_opt_set_context_reg2(sctx
, R_028710_SPI_SHADER_Z_FORMAT
,
1437 SI_TRACKED_SPI_SHADER_Z_FORMAT
,
1438 shader
->ctx_reg
.ps
.spi_shader_z_format
,
1439 shader
->ctx_reg
.ps
.spi_shader_col_format
);
1441 radeon_opt_set_context_reg(sctx
, R_02823C_CB_SHADER_MASK
,
1442 SI_TRACKED_CB_SHADER_MASK
,
1443 shader
->ctx_reg
.ps
.cb_shader_mask
);
1445 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1446 sctx
->context_roll
= true;
1449 static void si_shader_ps(struct si_screen
*sscreen
, struct si_shader
*shader
)
1451 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1452 struct si_pm4_state
*pm4
;
1453 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
1454 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
1456 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
1458 /* we need to enable at least one of them, otherwise we hang the GPU */
1459 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1460 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1461 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1462 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
1463 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
1464 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1465 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
1466 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
1467 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1468 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
1469 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1470 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1471 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1472 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
1474 /* Validate interpolation optimization flags (read as implications). */
1475 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1476 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1477 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1478 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1479 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1480 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1481 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
1482 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
1483 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1484 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
1485 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
1486 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1487 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
1488 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1489 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1490 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
1491 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1492 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1494 /* Validate cases when the optimizations are off (read as implications). */
1495 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1496 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1497 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
1498 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1499 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1500 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
1502 pm4
= si_get_shader_pm4_state(shader
);
1506 pm4
->atom
.emit
= si_emit_shader_ps
;
1508 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1510 * 0 -> Position = pixel center
1511 * 1 -> Position = pixel centroid
1512 * 2 -> Position = at sample position
1514 * From GLSL 4.5 specification, section 7.1:
1515 * "The variable gl_FragCoord is available as an input variable from
1516 * within fragment shaders and it holds the window relative coordinates
1517 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1518 * value can be for any location within the pixel, or one of the
1519 * fragment samples. The use of centroid does not further restrict
1520 * this value to be inside the current primitive."
1522 * Meaning that centroid has no effect and we can return anything within
1523 * the pixel. Thus, return the value at sample position, because that's
1524 * the most accurate one shaders can get.
1526 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1528 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
1529 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
1530 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
1532 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
1533 cb_shader_mask
= ac_get_cb_shader_mask(spi_shader_col_format
);
1535 /* Ensure that some export memory is always allocated, for two reasons:
1537 * 1) Correctness: The hardware ignores the EXEC mask if no export
1538 * memory is allocated, so KILL and alpha test do not work correctly
1540 * 2) Performance: Every shader needs at least a NULL export, even when
1541 * it writes no color/depth output. The NULL export instruction
1542 * stalls without this setting.
1544 * Don't add this to CB_SHADER_MASK.
1546 if (!spi_shader_col_format
&&
1547 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
1548 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
1550 shader
->ctx_reg
.ps
.spi_ps_input_ena
= input_ena
;
1551 shader
->ctx_reg
.ps
.spi_ps_input_addr
= shader
->config
.spi_ps_input_addr
;
1553 /* Set interpolation controls. */
1554 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
));
1556 shader
->ctx_reg
.ps
.spi_baryc_cntl
= spi_baryc_cntl
;
1557 shader
->ctx_reg
.ps
.spi_ps_in_control
= spi_ps_in_control
;
1558 shader
->ctx_reg
.ps
.spi_shader_z_format
=
1559 ac_get_spi_shader_z_format(info
->writes_z
,
1560 info
->writes_stencil
,
1561 info
->writes_samplemask
);
1562 shader
->ctx_reg
.ps
.spi_shader_col_format
= spi_shader_col_format
;
1563 shader
->ctx_reg
.ps
.cb_shader_mask
= cb_shader_mask
;
1565 va
= shader
->bo
->gpu_address
;
1566 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1567 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
1568 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, S_00B024_MEM_BASE(va
>> 40));
1571 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1572 S_00B028_DX10_CLAMP(1) |
1573 S_00B028_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
1574 S_00B028_FLOAT_MODE(shader
->config
.float_mode
);
1576 if (sscreen
->info
.chip_class
< GFX10
) {
1577 rsrc1
|= S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
1580 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
, rsrc1
);
1581 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
1582 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
1583 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
1584 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1587 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
1588 struct si_shader
*shader
)
1590 switch (shader
->selector
->type
) {
1591 case PIPE_SHADER_VERTEX
:
1592 if (shader
->key
.as_ls
)
1593 si_shader_ls(sscreen
, shader
);
1594 else if (shader
->key
.as_es
)
1595 si_shader_es(sscreen
, shader
);
1596 else if (shader
->key
.as_ngg
)
1597 gfx10_shader_ngg(sscreen
, shader
);
1599 si_shader_vs(sscreen
, shader
, NULL
);
1601 case PIPE_SHADER_TESS_CTRL
:
1602 si_shader_hs(sscreen
, shader
);
1604 case PIPE_SHADER_TESS_EVAL
:
1605 if (shader
->key
.as_es
)
1606 si_shader_es(sscreen
, shader
);
1607 else if (shader
->key
.as_ngg
)
1608 gfx10_shader_ngg(sscreen
, shader
);
1610 si_shader_vs(sscreen
, shader
, NULL
);
1612 case PIPE_SHADER_GEOMETRY
:
1613 if (shader
->key
.as_ngg
)
1614 gfx10_shader_ngg(sscreen
, shader
);
1616 si_shader_gs(sscreen
, shader
);
1618 case PIPE_SHADER_FRAGMENT
:
1619 si_shader_ps(sscreen
, shader
);
1626 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
1628 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1629 if (sctx
->queued
.named
.dsa
)
1630 return sctx
->queued
.named
.dsa
->alpha_func
;
1632 return PIPE_FUNC_ALWAYS
;
1635 void si_shader_selector_key_vs(struct si_context
*sctx
,
1636 struct si_shader_selector
*vs
,
1637 struct si_shader_key
*key
,
1638 struct si_vs_prolog_bits
*prolog_key
)
1640 if (!sctx
->vertex_elements
||
1641 vs
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
])
1644 struct si_vertex_elements
*elts
= sctx
->vertex_elements
;
1646 prolog_key
->instance_divisor_is_one
= elts
->instance_divisor_is_one
;
1647 prolog_key
->instance_divisor_is_fetched
= elts
->instance_divisor_is_fetched
;
1648 prolog_key
->unpack_instance_id_from_vertex_id
=
1649 sctx
->prim_discard_cs_instancing
;
1651 /* Prefer a monolithic shader to allow scheduling divisions around
1653 if (prolog_key
->instance_divisor_is_fetched
)
1654 key
->opt
.prefer_mono
= 1;
1656 unsigned count
= MIN2(vs
->info
.num_inputs
, elts
->count
);
1657 unsigned count_mask
= (1 << count
) - 1;
1658 unsigned fix
= elts
->fix_fetch_always
& count_mask
;
1659 unsigned opencode
= elts
->fix_fetch_opencode
& count_mask
;
1661 if (sctx
->vertex_buffer_unaligned
& elts
->vb_alignment_check_mask
) {
1662 uint32_t mask
= elts
->fix_fetch_unaligned
& count_mask
;
1664 unsigned i
= u_bit_scan(&mask
);
1665 unsigned log_hw_load_size
= 1 + ((elts
->hw_load_is_dword
>> i
) & 1);
1666 unsigned vbidx
= elts
->vertex_buffer_index
[i
];
1667 struct pipe_vertex_buffer
*vb
= &sctx
->vertex_buffer
[vbidx
];
1668 unsigned align_mask
= (1 << log_hw_load_size
) - 1;
1669 if (vb
->buffer_offset
& align_mask
||
1670 vb
->stride
& align_mask
) {
1678 unsigned i
= u_bit_scan(&fix
);
1679 key
->mono
.vs_fix_fetch
[i
].bits
= elts
->fix_fetch
[i
];
1681 key
->mono
.vs_fetch_opencode
= opencode
;
1684 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
,
1685 struct si_shader_selector
*vs
,
1686 struct si_shader_key
*key
)
1688 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1690 key
->opt
.clip_disable
=
1691 sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
1692 (vs
->info
.clipdist_writemask
||
1693 vs
->info
.writes_clipvertex
) &&
1694 !vs
->info
.culldist_writemask
;
1696 /* Find out if PS is disabled. */
1697 bool ps_disabled
= true;
1699 const struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1700 bool alpha_to_coverage
= blend
&& blend
->alpha_to_coverage
;
1701 bool ps_modifies_zs
= ps
->info
.uses_kill
||
1702 ps
->info
.writes_z
||
1703 ps
->info
.writes_stencil
||
1704 ps
->info
.writes_samplemask
||
1705 alpha_to_coverage
||
1706 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
1707 unsigned ps_colormask
= si_get_total_colormask(sctx
);
1709 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
1712 !ps
->info
.writes_memory
);
1715 /* Find out which VS outputs aren't used by the PS. */
1716 uint64_t outputs_written
= vs
->outputs_written_before_ps
;
1717 uint64_t inputs_read
= 0;
1719 /* Ignore outputs that are not passed from VS to PS. */
1720 outputs_written
&= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION
, 0, true)) |
1721 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE
, 0, true)) |
1722 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX
, 0, true)));
1725 inputs_read
= ps
->inputs_read
;
1728 uint64_t linked
= outputs_written
& inputs_read
;
1730 key
->opt
.kill_outputs
= ~linked
& outputs_written
;
1733 /* Compute the key for the hw shader variant */
1734 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
1735 struct si_shader_selector
*sel
,
1736 union si_vgt_stages_key stages_key
,
1737 struct si_shader_key
*key
)
1739 struct si_context
*sctx
= (struct si_context
*)ctx
;
1741 memset(key
, 0, sizeof(*key
));
1743 switch (sel
->type
) {
1744 case PIPE_SHADER_VERTEX
:
1745 si_shader_selector_key_vs(sctx
, sel
, key
, &key
->part
.vs
.prolog
);
1747 if (sctx
->tes_shader
.cso
)
1749 else if (sctx
->gs_shader
.cso
)
1752 key
->as_ngg
= stages_key
.u
.ngg
;
1753 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1755 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1756 key
->mono
.u
.vs_export_prim_id
= 1;
1759 case PIPE_SHADER_TESS_CTRL
:
1760 if (sctx
->chip_class
>= GFX9
) {
1761 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1762 key
, &key
->part
.tcs
.ls_prolog
);
1763 key
->part
.tcs
.ls
= sctx
->vs_shader
.cso
;
1765 /* When the LS VGPR fix is needed, monolithic shaders
1767 * - avoid initializing EXEC in both the LS prolog
1768 * and the LS main part when !vs_needs_prolog
1769 * - remove the fixup for unused input VGPRs
1771 key
->part
.tcs
.ls_prolog
.ls_vgpr_fix
= sctx
->ls_vgpr_fix
;
1773 /* The LS output / HS input layout can be communicated
1774 * directly instead of via user SGPRs for merged LS-HS.
1775 * The LS VGPR fix prefers this too.
1777 key
->opt
.prefer_mono
= 1;
1780 key
->part
.tcs
.epilog
.prim_mode
=
1781 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1782 key
->part
.tcs
.epilog
.invoc0_tess_factors_are_def
=
1783 sel
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1784 key
->part
.tcs
.epilog
.tes_reads_tess_factors
=
1785 sctx
->tes_shader
.cso
->info
.reads_tess_factors
;
1787 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
1788 key
->mono
.u
.ff_tcs_inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
1790 case PIPE_SHADER_TESS_EVAL
:
1791 if (sctx
->gs_shader
.cso
)
1794 key
->as_ngg
= stages_key
.u
.ngg
;
1795 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1797 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1798 key
->mono
.u
.vs_export_prim_id
= 1;
1801 case PIPE_SHADER_GEOMETRY
:
1802 if (sctx
->chip_class
>= GFX9
) {
1803 if (sctx
->tes_shader
.cso
) {
1804 key
->part
.gs
.es
= sctx
->tes_shader
.cso
;
1806 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1807 key
, &key
->part
.gs
.vs_prolog
);
1808 key
->part
.gs
.es
= sctx
->vs_shader
.cso
;
1809 key
->part
.gs
.prolog
.gfx9_prev_is_vs
= 1;
1812 key
->as_ngg
= stages_key
.u
.ngg
;
1814 /* Merged ES-GS can have unbalanced wave usage.
1816 * ES threads are per-vertex, while GS threads are
1817 * per-primitive. So without any amplification, there
1818 * are fewer GS threads than ES threads, which can result
1819 * in empty (no-op) GS waves. With too much amplification,
1820 * there are more GS threads than ES threads, which
1821 * can result in empty (no-op) ES waves.
1823 * Non-monolithic shaders are implemented by setting EXEC
1824 * at the beginning of shader parts, and don't jump to
1825 * the end if EXEC is 0.
1827 * Monolithic shaders use conditional blocks, so they can
1828 * jump and skip empty waves of ES or GS. So set this to
1829 * always use optimized variants, which are monolithic.
1831 key
->opt
.prefer_mono
= 1;
1833 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
1835 case PIPE_SHADER_FRAGMENT
: {
1836 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1837 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1839 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
1840 sel
->info
.colors_written
== 0x1)
1841 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
1844 /* Select the shader color format based on whether
1845 * blending or alpha are needed.
1847 key
->part
.ps
.epilog
.spi_shader_col_format
=
1848 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1849 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
1850 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1851 sctx
->framebuffer
.spi_shader_col_format_blend
) |
1852 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1853 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
1854 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1855 sctx
->framebuffer
.spi_shader_col_format
);
1856 key
->part
.ps
.epilog
.spi_shader_col_format
&= blend
->cb_target_enabled_4bit
;
1858 /* The output for dual source blending should have
1859 * the same format as the first output.
1861 if (blend
->dual_src_blend
)
1862 key
->part
.ps
.epilog
.spi_shader_col_format
|=
1863 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
1865 key
->part
.ps
.epilog
.spi_shader_col_format
= sctx
->framebuffer
.spi_shader_col_format
;
1867 /* If alpha-to-coverage is enabled, we have to export alpha
1868 * even if there is no color buffer.
1870 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) &&
1871 blend
&& blend
->alpha_to_coverage
)
1872 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
1874 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1875 * to the range supported by the type if a channel has less
1876 * than 16 bits and the export format is 16_ABGR.
1878 if (sctx
->chip_class
<= GFX7
&& sctx
->family
!= CHIP_HAWAII
) {
1879 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
1880 key
->part
.ps
.epilog
.color_is_int10
= sctx
->framebuffer
.color_is_int10
;
1883 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1884 if (!key
->part
.ps
.epilog
.last_cbuf
) {
1885 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
1886 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
1887 key
->part
.ps
.epilog
.color_is_int10
&= sel
->info
.colors_written
;
1890 bool is_poly
= !util_prim_is_points_or_lines(sctx
->current_rast_prim
);
1891 bool is_line
= util_prim_is_lines(sctx
->current_rast_prim
);
1893 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
1894 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
1896 if (sctx
->queued
.named
.blend
) {
1897 key
->part
.ps
.epilog
.alpha_to_one
= sctx
->queued
.named
.blend
->alpha_to_one
&&
1898 rs
->multisample_enable
;
1901 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
1902 key
->part
.ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
1903 (is_line
&& rs
->line_smooth
)) &&
1904 sctx
->framebuffer
.nr_samples
<= 1;
1905 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
1907 if (sctx
->ps_iter_samples
> 1 &&
1908 sel
->info
.reads_samplemask
) {
1909 key
->part
.ps
.prolog
.samplemask_log_ps_iter
=
1910 util_logbase2(sctx
->ps_iter_samples
);
1913 if (rs
->force_persample_interp
&&
1914 rs
->multisample_enable
&&
1915 sctx
->framebuffer
.nr_samples
> 1 &&
1916 sctx
->ps_iter_samples
> 1) {
1917 key
->part
.ps
.prolog
.force_persp_sample_interp
=
1918 sel
->info
.uses_persp_center
||
1919 sel
->info
.uses_persp_centroid
;
1921 key
->part
.ps
.prolog
.force_linear_sample_interp
=
1922 sel
->info
.uses_linear_center
||
1923 sel
->info
.uses_linear_centroid
;
1924 } else if (rs
->multisample_enable
&&
1925 sctx
->framebuffer
.nr_samples
> 1) {
1926 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
1927 sel
->info
.uses_persp_center
&&
1928 sel
->info
.uses_persp_centroid
;
1929 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
1930 sel
->info
.uses_linear_center
&&
1931 sel
->info
.uses_linear_centroid
;
1933 /* Make sure SPI doesn't compute more than 1 pair
1934 * of (i,j), which is the optimization here. */
1935 key
->part
.ps
.prolog
.force_persp_center_interp
=
1936 sel
->info
.uses_persp_center
+
1937 sel
->info
.uses_persp_centroid
+
1938 sel
->info
.uses_persp_sample
> 1;
1940 key
->part
.ps
.prolog
.force_linear_center_interp
=
1941 sel
->info
.uses_linear_center
+
1942 sel
->info
.uses_linear_centroid
+
1943 sel
->info
.uses_linear_sample
> 1;
1945 if (sel
->info
.opcode_count
[TGSI_OPCODE_INTERP_SAMPLE
])
1946 key
->mono
.u
.ps
.interpolate_at_sample_force_center
= 1;
1949 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
1951 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1952 if (sctx
->ps_uses_fbfetch
&& !sctx
->blitter
->running
) {
1953 struct pipe_surface
*cb0
= sctx
->framebuffer
.state
.cbufs
[0];
1954 struct pipe_resource
*tex
= cb0
->texture
;
1956 /* 1D textures are allocated and used as 2D on GFX9. */
1957 key
->mono
.u
.ps
.fbfetch_msaa
= sctx
->framebuffer
.nr_samples
> 1;
1958 key
->mono
.u
.ps
.fbfetch_is_1D
= sctx
->chip_class
!= GFX9
&&
1959 (tex
->target
== PIPE_TEXTURE_1D
||
1960 tex
->target
== PIPE_TEXTURE_1D_ARRAY
);
1961 key
->mono
.u
.ps
.fbfetch_layered
= tex
->target
== PIPE_TEXTURE_1D_ARRAY
||
1962 tex
->target
== PIPE_TEXTURE_2D_ARRAY
||
1963 tex
->target
== PIPE_TEXTURE_CUBE
||
1964 tex
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
1965 tex
->target
== PIPE_TEXTURE_3D
;
1973 if (unlikely(sctx
->screen
->debug_flags
& DBG(NO_OPT_VARIANT
)))
1974 memset(&key
->opt
, 0, sizeof(key
->opt
));
1977 static void si_build_shader_variant(struct si_shader
*shader
,
1981 struct si_shader_selector
*sel
= shader
->selector
;
1982 struct si_screen
*sscreen
= sel
->screen
;
1983 struct ac_llvm_compiler
*compiler
;
1984 struct pipe_debug_callback
*debug
= &shader
->compiler_ctx_state
.debug
;
1986 if (thread_index
>= 0) {
1988 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler_lowp
));
1989 compiler
= &sscreen
->compiler_lowp
[thread_index
];
1991 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
1992 compiler
= &sscreen
->compiler
[thread_index
];
1997 assert(!low_priority
);
1998 compiler
= shader
->compiler_ctx_state
.compiler
;
2001 if (unlikely(!si_shader_create(sscreen
, compiler
, shader
, debug
))) {
2002 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2004 shader
->compilation_failed
= true;
2008 if (shader
->compiler_ctx_state
.is_debug_context
) {
2009 FILE *f
= open_memstream(&shader
->shader_log
,
2010 &shader
->shader_log_size
);
2012 si_shader_dump(sscreen
, shader
, NULL
, sel
->type
, f
, false);
2017 si_shader_init_pm4_state(sscreen
, shader
);
2020 static void si_build_shader_variant_low_priority(void *job
, int thread_index
)
2022 struct si_shader
*shader
= (struct si_shader
*)job
;
2024 assert(thread_index
>= 0);
2026 si_build_shader_variant(shader
, thread_index
, true);
2029 static const struct si_shader_key zeroed
;
2031 static bool si_check_missing_main_part(struct si_screen
*sscreen
,
2032 struct si_shader_selector
*sel
,
2033 struct si_compiler_ctx_state
*compiler_state
,
2034 struct si_shader_key
*key
)
2036 struct si_shader
**mainp
= si_get_main_shader_part(sel
, key
);
2039 struct si_shader
*main_part
= CALLOC_STRUCT(si_shader
);
2044 /* We can leave the fence as permanently signaled because the
2045 * main part becomes visible globally only after it has been
2047 util_queue_fence_init(&main_part
->ready
);
2049 main_part
->selector
= sel
;
2050 main_part
->key
.as_es
= key
->as_es
;
2051 main_part
->key
.as_ls
= key
->as_ls
;
2052 main_part
->key
.as_ngg
= key
->as_ngg
;
2053 main_part
->is_monolithic
= false;
2055 if (si_compile_tgsi_shader(sscreen
, compiler_state
->compiler
,
2056 main_part
, &compiler_state
->debug
) != 0) {
2066 * Select a shader variant according to the shader key.
2068 * \param optimized_or_none If the key describes an optimized shader variant and
2069 * the compilation isn't finished, don't select any
2070 * shader and return an error.
2072 int si_shader_select_with_key(struct si_screen
*sscreen
,
2073 struct si_shader_ctx_state
*state
,
2074 struct si_compiler_ctx_state
*compiler_state
,
2075 struct si_shader_key
*key
,
2077 bool optimized_or_none
)
2079 struct si_shader_selector
*sel
= state
->cso
;
2080 struct si_shader_selector
*previous_stage_sel
= NULL
;
2081 struct si_shader
*current
= state
->current
;
2082 struct si_shader
*iter
, *shader
= NULL
;
2085 /* Check if we don't need to change anything.
2086 * This path is also used for most shaders that don't need multiple
2087 * variants, it will cost just a computation of the key and this
2089 if (likely(current
&&
2090 memcmp(¤t
->key
, key
, sizeof(*key
)) == 0)) {
2091 if (unlikely(!util_queue_fence_is_signalled(¤t
->ready
))) {
2092 if (current
->is_optimized
) {
2093 if (optimized_or_none
)
2096 memset(&key
->opt
, 0, sizeof(key
->opt
));
2097 goto current_not_ready
;
2100 util_queue_fence_wait(¤t
->ready
);
2103 return current
->compilation_failed
? -1 : 0;
2107 /* This must be done before the mutex is locked, because async GS
2108 * compilation calls this function too, and therefore must enter
2111 * Only wait if we are in a draw call. Don't wait if we are
2112 * in a compiler thread.
2114 if (thread_index
< 0)
2115 util_queue_fence_wait(&sel
->ready
);
2117 mtx_lock(&sel
->mutex
);
2119 /* Find the shader variant. */
2120 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
2121 /* Don't check the "current" shader. We checked it above. */
2122 if (current
!= iter
&&
2123 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
2124 mtx_unlock(&sel
->mutex
);
2126 if (unlikely(!util_queue_fence_is_signalled(&iter
->ready
))) {
2127 /* If it's an optimized shader and its compilation has
2128 * been started but isn't done, use the unoptimized
2129 * shader so as not to cause a stall due to compilation.
2131 if (iter
->is_optimized
) {
2132 if (optimized_or_none
)
2134 memset(&key
->opt
, 0, sizeof(key
->opt
));
2138 util_queue_fence_wait(&iter
->ready
);
2141 if (iter
->compilation_failed
) {
2142 return -1; /* skip the draw call */
2145 state
->current
= iter
;
2150 /* Build a new shader. */
2151 shader
= CALLOC_STRUCT(si_shader
);
2153 mtx_unlock(&sel
->mutex
);
2157 util_queue_fence_init(&shader
->ready
);
2159 shader
->selector
= sel
;
2161 shader
->compiler_ctx_state
= *compiler_state
;
2163 /* If this is a merged shader, get the first shader's selector. */
2164 if (sscreen
->info
.chip_class
>= GFX9
) {
2165 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
2166 previous_stage_sel
= key
->part
.tcs
.ls
;
2167 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
2168 previous_stage_sel
= key
->part
.gs
.es
;
2170 /* We need to wait for the previous shader. */
2171 if (previous_stage_sel
&& thread_index
< 0)
2172 util_queue_fence_wait(&previous_stage_sel
->ready
);
2175 bool is_pure_monolithic
=
2176 sscreen
->use_monolithic_shaders
||
2177 memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
2179 /* Compile the main shader part if it doesn't exist. This can happen
2180 * if the initial guess was wrong.
2182 * The prim discard CS doesn't need the main shader part.
2184 if (!is_pure_monolithic
&&
2185 !key
->opt
.vs_as_prim_discard_cs
) {
2188 /* Make sure the main shader part is present. This is needed
2189 * for shaders that can be compiled as VS, LS, or ES, and only
2190 * one of them is compiled at creation.
2192 * It is also needed for GS, which can be compiled as non-NGG
2195 * For merged shaders, check that the starting shader's main
2198 if (previous_stage_sel
) {
2199 struct si_shader_key shader1_key
= zeroed
;
2201 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
2202 shader1_key
.as_ls
= 1;
2203 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
2204 shader1_key
.as_es
= 1;
2208 mtx_lock(&previous_stage_sel
->mutex
);
2209 ok
= si_check_missing_main_part(sscreen
,
2211 compiler_state
, &shader1_key
);
2212 mtx_unlock(&previous_stage_sel
->mutex
);
2216 ok
= si_check_missing_main_part(sscreen
, sel
,
2217 compiler_state
, key
);
2222 mtx_unlock(&sel
->mutex
);
2223 return -ENOMEM
; /* skip the draw call */
2227 /* Keep the reference to the 1st shader of merged shaders, so that
2228 * Gallium can't destroy it before we destroy the 2nd shader.
2230 * Set sctx = NULL, because it's unused if we're not releasing
2231 * the shader, and we don't have any sctx here.
2233 si_shader_selector_reference(NULL
, &shader
->previous_stage_sel
,
2234 previous_stage_sel
);
2236 /* Monolithic-only shaders don't make a distinction between optimized
2237 * and unoptimized. */
2238 shader
->is_monolithic
=
2239 is_pure_monolithic
||
2240 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
2242 /* The prim discard CS is always optimized. */
2243 shader
->is_optimized
=
2244 (!is_pure_monolithic
|| key
->opt
.vs_as_prim_discard_cs
) &&
2245 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
2247 /* If it's an optimized shader, compile it asynchronously. */
2248 if (shader
->is_optimized
&& thread_index
< 0) {
2249 /* Compile it asynchronously. */
2250 util_queue_add_job(&sscreen
->shader_compiler_queue_low_priority
,
2251 shader
, &shader
->ready
,
2252 si_build_shader_variant_low_priority
, NULL
);
2254 /* Add only after the ready fence was reset, to guard against a
2255 * race with si_bind_XX_shader. */
2256 if (!sel
->last_variant
) {
2257 sel
->first_variant
= shader
;
2258 sel
->last_variant
= shader
;
2260 sel
->last_variant
->next_variant
= shader
;
2261 sel
->last_variant
= shader
;
2264 /* Use the default (unoptimized) shader for now. */
2265 memset(&key
->opt
, 0, sizeof(key
->opt
));
2266 mtx_unlock(&sel
->mutex
);
2268 if (sscreen
->options
.sync_compile
)
2269 util_queue_fence_wait(&shader
->ready
);
2271 if (optimized_or_none
)
2276 /* Reset the fence before adding to the variant list. */
2277 util_queue_fence_reset(&shader
->ready
);
2279 if (!sel
->last_variant
) {
2280 sel
->first_variant
= shader
;
2281 sel
->last_variant
= shader
;
2283 sel
->last_variant
->next_variant
= shader
;
2284 sel
->last_variant
= shader
;
2287 mtx_unlock(&sel
->mutex
);
2289 assert(!shader
->is_optimized
);
2290 si_build_shader_variant(shader
, thread_index
, false);
2292 util_queue_fence_signal(&shader
->ready
);
2294 if (!shader
->compilation_failed
)
2295 state
->current
= shader
;
2297 return shader
->compilation_failed
? -1 : 0;
2300 static int si_shader_select(struct pipe_context
*ctx
,
2301 struct si_shader_ctx_state
*state
,
2302 union si_vgt_stages_key stages_key
,
2303 struct si_compiler_ctx_state
*compiler_state
)
2305 struct si_context
*sctx
= (struct si_context
*)ctx
;
2306 struct si_shader_key key
;
2308 si_shader_selector_key(ctx
, state
->cso
, stages_key
, &key
);
2309 return si_shader_select_with_key(sctx
->screen
, state
, compiler_state
,
2313 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
2315 struct si_shader_key
*key
)
2317 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
2319 switch (info
->processor
) {
2320 case PIPE_SHADER_VERTEX
:
2321 switch (next_shader
) {
2322 case PIPE_SHADER_GEOMETRY
:
2325 case PIPE_SHADER_TESS_CTRL
:
2326 case PIPE_SHADER_TESS_EVAL
:
2330 /* If POSITION isn't written, it can only be a HW VS
2331 * if streamout is used. If streamout isn't used,
2332 * assume that it's a HW LS. (the next shader is TCS)
2333 * This heuristic is needed for separate shader objects.
2335 if (!info
->writes_position
&& !streamout
)
2340 case PIPE_SHADER_TESS_EVAL
:
2341 if (next_shader
== PIPE_SHADER_GEOMETRY
||
2342 !info
->writes_position
)
2349 * Compile the main shader part or the monolithic shader as part of
2350 * si_shader_selector initialization. Since it can be done asynchronously,
2351 * there is no way to report compile failures to applications.
2353 static void si_init_shader_selector_async(void *job
, int thread_index
)
2355 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
2356 struct si_screen
*sscreen
= sel
->screen
;
2357 struct ac_llvm_compiler
*compiler
;
2358 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
2360 assert(!debug
->debug_message
|| debug
->async
);
2361 assert(thread_index
>= 0);
2362 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
2363 compiler
= &sscreen
->compiler
[thread_index
];
2368 /* Compile the main shader part for use with a prolog and/or epilog.
2369 * If this fails, the driver will try to compile a monolithic shader
2372 if (!sscreen
->use_monolithic_shaders
) {
2373 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
2374 void *ir_binary
= NULL
;
2377 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
2381 /* We can leave the fence signaled because use of the default
2382 * main part is guarded by the selector's ready fence. */
2383 util_queue_fence_init(&shader
->ready
);
2385 shader
->selector
= sel
;
2386 shader
->is_monolithic
= false;
2387 si_parse_next_shader_property(&sel
->info
,
2388 sel
->so
.num_outputs
!= 0,
2390 if (sscreen
->info
.chip_class
>= GFX10
&&
2391 !sscreen
->options
.disable_ngg
&&
2392 (((sel
->type
== PIPE_SHADER_VERTEX
||
2393 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
2394 !shader
->key
.as_ls
&& !shader
->key
.as_es
) ||
2395 sel
->type
== PIPE_SHADER_GEOMETRY
))
2396 shader
->key
.as_ngg
= 1;
2398 if (sel
->tokens
|| sel
->nir
)
2399 ir_binary
= si_get_ir_binary(sel
);
2401 /* Try to load the shader from the shader cache. */
2402 mtx_lock(&sscreen
->shader_cache_mutex
);
2405 si_shader_cache_load_shader(sscreen
, ir_binary
, shader
)) {
2406 mtx_unlock(&sscreen
->shader_cache_mutex
);
2407 si_shader_dump_stats_for_shader_db(sscreen
, shader
, debug
);
2409 mtx_unlock(&sscreen
->shader_cache_mutex
);
2411 /* Compile the shader if it hasn't been loaded from the cache. */
2412 if (si_compile_tgsi_shader(sscreen
, compiler
, shader
,
2416 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
2421 mtx_lock(&sscreen
->shader_cache_mutex
);
2422 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
, shader
, true))
2424 mtx_unlock(&sscreen
->shader_cache_mutex
);
2428 *si_get_main_shader_part(sel
, &shader
->key
) = shader
;
2430 /* Unset "outputs_written" flags for outputs converted to
2431 * DEFAULT_VAL, so that later inter-shader optimizations don't
2432 * try to eliminate outputs that don't exist in the final
2435 * This is only done if non-monolithic shaders are enabled.
2437 if ((sel
->type
== PIPE_SHADER_VERTEX
||
2438 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
2439 !shader
->key
.as_ls
&&
2440 !shader
->key
.as_es
) {
2443 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2444 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
2446 if (offset
<= AC_EXP_PARAM_OFFSET_31
)
2449 unsigned name
= sel
->info
.output_semantic_name
[i
];
2450 unsigned index
= sel
->info
.output_semantic_index
[i
];
2454 case TGSI_SEMANTIC_GENERIC
:
2455 /* don't process indices the function can't handle */
2456 if (index
>= SI_MAX_IO_GENERIC
)
2460 id
= si_shader_io_get_unique_index(name
, index
, true);
2461 sel
->outputs_written_before_ps
&= ~(1ull << id
);
2463 case TGSI_SEMANTIC_POSITION
: /* ignore these */
2464 case TGSI_SEMANTIC_PSIZE
:
2465 case TGSI_SEMANTIC_CLIPVERTEX
:
2466 case TGSI_SEMANTIC_EDGEFLAG
:
2473 /* The GS copy shader is always pre-compiled.
2475 * TODO-GFX10: We could compile the GS copy shader on demand, since it
2476 * is only used in the (rare) non-NGG case.
2478 if (sel
->type
== PIPE_SHADER_GEOMETRY
) {
2479 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, compiler
, sel
, debug
);
2480 if (!sel
->gs_copy_shader
) {
2481 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
2485 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
2489 void si_schedule_initial_compile(struct si_context
*sctx
, unsigned processor
,
2490 struct util_queue_fence
*ready_fence
,
2491 struct si_compiler_ctx_state
*compiler_ctx_state
,
2492 void *job
, util_queue_execute_func execute
)
2494 util_queue_fence_init(ready_fence
);
2496 struct util_async_debug_callback async_debug
;
2498 (sctx
->debug
.debug_message
&& !sctx
->debug
.async
) ||
2500 si_can_dump_shader(sctx
->screen
, processor
);
2503 u_async_debug_init(&async_debug
);
2504 compiler_ctx_state
->debug
= async_debug
.base
;
2507 util_queue_add_job(&sctx
->screen
->shader_compiler_queue
, job
,
2508 ready_fence
, execute
, NULL
);
2511 util_queue_fence_wait(ready_fence
);
2512 u_async_debug_drain(&async_debug
, &sctx
->debug
);
2513 u_async_debug_cleanup(&async_debug
);
2516 if (sctx
->screen
->options
.sync_compile
)
2517 util_queue_fence_wait(ready_fence
);
2520 /* Return descriptor slot usage masks from the given shader info. */
2521 void si_get_active_slot_masks(const struct tgsi_shader_info
*info
,
2522 uint32_t *const_and_shader_buffers
,
2523 uint64_t *samplers_and_images
)
2525 unsigned start
, num_shaderbufs
, num_constbufs
, num_images
, num_samplers
;
2527 num_shaderbufs
= util_last_bit(info
->shader_buffers_declared
);
2528 num_constbufs
= util_last_bit(info
->const_buffers_declared
);
2529 /* two 8-byte images share one 16-byte slot */
2530 num_images
= align(util_last_bit(info
->images_declared
), 2);
2531 num_samplers
= util_last_bit(info
->samplers_declared
);
2533 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2534 start
= si_get_shaderbuf_slot(num_shaderbufs
- 1);
2535 *const_and_shader_buffers
=
2536 u_bit_consecutive(start
, num_shaderbufs
+ num_constbufs
);
2538 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2539 start
= si_get_image_slot(num_images
- 1) / 2;
2540 *samplers_and_images
=
2541 u_bit_consecutive64(start
, num_images
/ 2 + num_samplers
);
2544 static void *si_create_shader_selector(struct pipe_context
*ctx
,
2545 const struct pipe_shader_state
*state
)
2547 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
2548 struct si_context
*sctx
= (struct si_context
*)ctx
;
2549 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
2555 pipe_reference_init(&sel
->reference
, 1);
2556 sel
->screen
= sscreen
;
2557 sel
->compiler_ctx_state
.debug
= sctx
->debug
;
2558 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
2560 sel
->so
= state
->stream_output
;
2562 if (state
->type
== PIPE_SHADER_IR_TGSI
) {
2563 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
2569 tgsi_scan_shader(state
->tokens
, &sel
->info
);
2570 tgsi_scan_tess_ctrl(state
->tokens
, &sel
->info
, &sel
->tcs_info
);
2572 assert(state
->type
== PIPE_SHADER_IR_NIR
);
2574 sel
->nir
= state
->ir
.nir
;
2576 si_nir_opts(sel
->nir
);
2577 si_nir_scan_shader(sel
->nir
, &sel
->info
);
2578 si_nir_scan_tess_ctrl(sel
->nir
, &sel
->tcs_info
);
2581 sel
->type
= sel
->info
.processor
;
2582 p_atomic_inc(&sscreen
->num_shaders_created
);
2583 si_get_active_slot_masks(&sel
->info
,
2584 &sel
->active_const_and_shader_buffers
,
2585 &sel
->active_samplers_and_images
);
2587 /* Record which streamout buffers are enabled. */
2588 for (i
= 0; i
< sel
->so
.num_outputs
; i
++) {
2589 sel
->enabled_streamout_buffer_mask
|=
2590 (1 << sel
->so
.output
[i
].output_buffer
) <<
2591 (sel
->so
.output
[i
].stream
* 4);
2594 /* The prolog is a no-op if there are no inputs. */
2595 sel
->vs_needs_prolog
= sel
->type
== PIPE_SHADER_VERTEX
&&
2596 sel
->info
.num_inputs
&&
2597 !sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
2599 sel
->force_correct_derivs_after_kill
=
2600 sel
->type
== PIPE_SHADER_FRAGMENT
&&
2601 sel
->info
.uses_derivatives
&&
2602 sel
->info
.uses_kill
&&
2603 sctx
->screen
->debug_flags
& DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
2605 sel
->prim_discard_cs_allowed
=
2606 sel
->type
== PIPE_SHADER_VERTEX
&&
2607 !sel
->info
.uses_bindless_images
&&
2608 !sel
->info
.uses_bindless_samplers
&&
2609 !sel
->info
.writes_memory
&&
2610 !sel
->info
.writes_viewport_index
&&
2611 !sel
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] &&
2612 !sel
->so
.num_outputs
;
2614 /* Set which opcode uses which (i,j) pair. */
2615 if (sel
->info
.uses_persp_opcode_interp_centroid
)
2616 sel
->info
.uses_persp_centroid
= true;
2618 if (sel
->info
.uses_linear_opcode_interp_centroid
)
2619 sel
->info
.uses_linear_centroid
= true;
2621 if (sel
->info
.uses_persp_opcode_interp_offset
||
2622 sel
->info
.uses_persp_opcode_interp_sample
)
2623 sel
->info
.uses_persp_center
= true;
2625 if (sel
->info
.uses_linear_opcode_interp_offset
||
2626 sel
->info
.uses_linear_opcode_interp_sample
)
2627 sel
->info
.uses_linear_center
= true;
2629 switch (sel
->type
) {
2630 case PIPE_SHADER_GEOMETRY
:
2631 sel
->gs_output_prim
=
2632 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
2633 sel
->gs_max_out_vertices
=
2634 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
2635 sel
->gs_num_invocations
=
2636 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
2637 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
2638 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
2639 sel
->gs_max_out_vertices
;
2641 sel
->max_gs_stream
= 0;
2642 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
2643 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
2644 sel
->so
.output
[i
].stream
);
2646 sel
->gs_input_verts_per_prim
=
2647 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
2650 case PIPE_SHADER_TESS_CTRL
:
2651 /* Always reserve space for these. */
2652 sel
->patch_outputs_written
|=
2653 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0)) |
2654 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0));
2656 case PIPE_SHADER_VERTEX
:
2657 case PIPE_SHADER_TESS_EVAL
:
2658 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2659 unsigned name
= sel
->info
.output_semantic_name
[i
];
2660 unsigned index
= sel
->info
.output_semantic_index
[i
];
2663 case TGSI_SEMANTIC_TESSINNER
:
2664 case TGSI_SEMANTIC_TESSOUTER
:
2665 case TGSI_SEMANTIC_PATCH
:
2666 sel
->patch_outputs_written
|=
2667 1ull << si_shader_io_get_unique_index_patch(name
, index
);
2670 case TGSI_SEMANTIC_GENERIC
:
2671 /* don't process indices the function can't handle */
2672 if (index
>= SI_MAX_IO_GENERIC
)
2676 sel
->outputs_written
|=
2677 1ull << si_shader_io_get_unique_index(name
, index
, false);
2678 sel
->outputs_written_before_ps
|=
2679 1ull << si_shader_io_get_unique_index(name
, index
, true);
2681 case TGSI_SEMANTIC_EDGEFLAG
:
2685 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
2686 sel
->lshs_vertex_stride
= sel
->esgs_itemsize
;
2688 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2689 * will start on a different bank. (except for the maximum 32*16).
2691 if (sel
->lshs_vertex_stride
< 32*16)
2692 sel
->lshs_vertex_stride
+= 4;
2694 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2695 * conflicts, i.e. each vertex will start at a different bank.
2697 if (sctx
->chip_class
>= GFX9
)
2698 sel
->esgs_itemsize
+= 4;
2700 assert(((sel
->esgs_itemsize
/ 4) & C_028AAC_ITEMSIZE
) == 0);
2703 case PIPE_SHADER_FRAGMENT
:
2704 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2705 unsigned name
= sel
->info
.input_semantic_name
[i
];
2706 unsigned index
= sel
->info
.input_semantic_index
[i
];
2709 case TGSI_SEMANTIC_GENERIC
:
2710 /* don't process indices the function can't handle */
2711 if (index
>= SI_MAX_IO_GENERIC
)
2716 1ull << si_shader_io_get_unique_index(name
, index
, true);
2718 case TGSI_SEMANTIC_PCOORD
: /* ignore this */
2723 for (i
= 0; i
< 8; i
++)
2724 if (sel
->info
.colors_written
& (1 << i
))
2725 sel
->colors_written_4bit
|= 0xf << (4 * i
);
2727 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2728 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
2729 int index
= sel
->info
.input_semantic_index
[i
];
2730 sel
->color_attr_index
[index
] = i
;
2736 /* PA_CL_VS_OUT_CNTL */
2738 sel
->info
.writes_psize
|| sel
->info
.writes_edgeflag
||
2739 sel
->info
.writes_layer
|| sel
->info
.writes_viewport_index
;
2740 sel
->pa_cl_vs_out_cntl
=
2741 S_02881C_USE_VTX_POINT_SIZE(sel
->info
.writes_psize
) |
2742 S_02881C_USE_VTX_EDGE_FLAG(sel
->info
.writes_edgeflag
) |
2743 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel
->info
.writes_layer
) |
2744 S_02881C_USE_VTX_VIEWPORT_INDX(sel
->info
.writes_viewport_index
) |
2745 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
2746 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
);
2747 sel
->clipdist_mask
= sel
->info
.writes_clipvertex
?
2748 SIX_BITS
: sel
->info
.clipdist_writemask
;
2749 sel
->culldist_mask
= sel
->info
.culldist_writemask
<<
2750 sel
->info
.num_written_clipdistance
;
2752 /* DB_SHADER_CONTROL */
2753 sel
->db_shader_control
=
2754 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
2755 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
2756 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
2757 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
2759 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
2760 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2761 sel
->db_shader_control
|=
2762 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2764 case TGSI_FS_DEPTH_LAYOUT_LESS
:
2765 sel
->db_shader_control
|=
2766 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2770 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2772 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2773 * --|-----------|------------|------------|--------------------|-------------------|-------------
2774 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2775 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2776 * 2 | false | true | n/a | LateZ | 1 | 0
2777 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2778 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2780 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2781 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2783 * Don't use ReZ without profiling !!!
2785 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2788 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
2790 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
2791 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
2792 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
2793 } else if (sel
->info
.writes_memory
) {
2795 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) |
2796 S_02880C_EXEC_ON_HIER_FAIL(1);
2799 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2802 (void) mtx_init(&sel
->mutex
, mtx_plain
);
2804 si_schedule_initial_compile(sctx
, sel
->info
.processor
, &sel
->ready
,
2805 &sel
->compiler_ctx_state
, sel
,
2806 si_init_shader_selector_async
);
2810 static void si_update_streamout_state(struct si_context
*sctx
)
2812 struct si_shader_selector
*shader_with_so
= si_get_vs(sctx
)->cso
;
2814 if (!shader_with_so
)
2817 sctx
->streamout
.enabled_stream_buffers_mask
=
2818 shader_with_so
->enabled_streamout_buffer_mask
;
2819 sctx
->streamout
.stride_in_dw
= shader_with_so
->so
.stride
;
2822 static void si_update_clip_regs(struct si_context
*sctx
,
2823 struct si_shader_selector
*old_hw_vs
,
2824 struct si_shader
*old_hw_vs_variant
,
2825 struct si_shader_selector
*next_hw_vs
,
2826 struct si_shader
*next_hw_vs_variant
)
2830 old_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] !=
2831 next_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] ||
2832 old_hw_vs
->pa_cl_vs_out_cntl
!= next_hw_vs
->pa_cl_vs_out_cntl
||
2833 old_hw_vs
->clipdist_mask
!= next_hw_vs
->clipdist_mask
||
2834 old_hw_vs
->culldist_mask
!= next_hw_vs
->culldist_mask
||
2835 !old_hw_vs_variant
||
2836 !next_hw_vs_variant
||
2837 old_hw_vs_variant
->key
.opt
.clip_disable
!=
2838 next_hw_vs_variant
->key
.opt
.clip_disable
))
2839 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
2842 static void si_update_common_shader_state(struct si_context
*sctx
)
2844 sctx
->uses_bindless_samplers
=
2845 si_shader_uses_bindless_samplers(sctx
->vs_shader
.cso
) ||
2846 si_shader_uses_bindless_samplers(sctx
->gs_shader
.cso
) ||
2847 si_shader_uses_bindless_samplers(sctx
->ps_shader
.cso
) ||
2848 si_shader_uses_bindless_samplers(sctx
->tcs_shader
.cso
) ||
2849 si_shader_uses_bindless_samplers(sctx
->tes_shader
.cso
);
2850 sctx
->uses_bindless_images
=
2851 si_shader_uses_bindless_images(sctx
->vs_shader
.cso
) ||
2852 si_shader_uses_bindless_images(sctx
->gs_shader
.cso
) ||
2853 si_shader_uses_bindless_images(sctx
->ps_shader
.cso
) ||
2854 si_shader_uses_bindless_images(sctx
->tcs_shader
.cso
) ||
2855 si_shader_uses_bindless_images(sctx
->tes_shader
.cso
);
2856 sctx
->do_update_shaders
= true;
2859 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
2861 struct si_context
*sctx
= (struct si_context
*)ctx
;
2862 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2863 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2864 struct si_shader_selector
*sel
= state
;
2866 if (sctx
->vs_shader
.cso
== sel
)
2869 sctx
->vs_shader
.cso
= sel
;
2870 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2871 sctx
->num_vs_blit_sgprs
= sel
? sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
] : 0;
2873 si_update_common_shader_state(sctx
);
2874 si_update_vs_viewport_state(sctx
);
2875 si_set_active_descriptors_for_shader(sctx
, sel
);
2876 si_update_streamout_state(sctx
);
2877 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2878 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2881 static void si_update_tess_uses_prim_id(struct si_context
*sctx
)
2883 sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
=
2884 (sctx
->tes_shader
.cso
&&
2885 sctx
->tes_shader
.cso
->info
.uses_primid
) ||
2886 (sctx
->tcs_shader
.cso
&&
2887 sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
2888 (sctx
->gs_shader
.cso
&&
2889 sctx
->gs_shader
.cso
->info
.uses_primid
) ||
2890 (sctx
->ps_shader
.cso
&& !sctx
->gs_shader
.cso
&&
2891 sctx
->ps_shader
.cso
->info
.uses_primid
);
2894 static bool si_update_ngg(struct si_context
*sctx
)
2896 if (sctx
->chip_class
<= GFX9
||
2897 sctx
->screen
->options
.disable_ngg
)
2900 bool new_ngg
= true;
2902 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2903 if (sctx
->gs_shader
.cso
&& sctx
->tes_shader
.cso
&&
2904 sctx
->gs_shader
.cso
->gs_num_invocations
* sctx
->gs_shader
.cso
->gs_max_out_vertices
> 256)
2907 if (new_ngg
!= sctx
->ngg
) {
2908 sctx
->ngg
= new_ngg
;
2909 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2915 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
2917 struct si_context
*sctx
= (struct si_context
*)ctx
;
2918 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2919 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2920 struct si_shader_selector
*sel
= state
;
2921 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
2924 if (sctx
->gs_shader
.cso
== sel
)
2927 sctx
->gs_shader
.cso
= sel
;
2928 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2929 sctx
->ia_multi_vgt_param_key
.u
.uses_gs
= sel
!= NULL
;
2931 si_update_common_shader_state(sctx
);
2932 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2934 ngg_changed
= si_update_ngg(sctx
);
2935 if (ngg_changed
|| enable_changed
)
2936 si_shader_change_notify(sctx
);
2937 if (enable_changed
) {
2938 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2939 si_update_tess_uses_prim_id(sctx
);
2941 si_update_vs_viewport_state(sctx
);
2942 si_set_active_descriptors_for_shader(sctx
, sel
);
2943 si_update_streamout_state(sctx
);
2944 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2945 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2948 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
2950 struct si_context
*sctx
= (struct si_context
*)ctx
;
2951 struct si_shader_selector
*sel
= state
;
2952 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
2954 if (sctx
->tcs_shader
.cso
== sel
)
2957 sctx
->tcs_shader
.cso
= sel
;
2958 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2959 si_update_tess_uses_prim_id(sctx
);
2961 si_update_common_shader_state(sctx
);
2964 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
2966 si_set_active_descriptors_for_shader(sctx
, sel
);
2969 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
2971 struct si_context
*sctx
= (struct si_context
*)ctx
;
2972 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2973 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2974 struct si_shader_selector
*sel
= state
;
2975 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
2977 if (sctx
->tes_shader
.cso
== sel
)
2980 sctx
->tes_shader
.cso
= sel
;
2981 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
2982 sctx
->ia_multi_vgt_param_key
.u
.uses_tess
= sel
!= NULL
;
2983 si_update_tess_uses_prim_id(sctx
);
2985 si_update_common_shader_state(sctx
);
2986 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2988 if (enable_changed
) {
2989 si_update_ngg(sctx
);
2990 si_shader_change_notify(sctx
);
2991 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
2993 si_update_vs_viewport_state(sctx
);
2994 si_set_active_descriptors_for_shader(sctx
, sel
);
2995 si_update_streamout_state(sctx
);
2996 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2997 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
3000 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
3002 struct si_context
*sctx
= (struct si_context
*)ctx
;
3003 struct si_shader_selector
*old_sel
= sctx
->ps_shader
.cso
;
3004 struct si_shader_selector
*sel
= state
;
3006 /* skip if supplied shader is one already in use */
3010 sctx
->ps_shader
.cso
= sel
;
3011 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
3013 si_update_common_shader_state(sctx
);
3015 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
3016 si_update_tess_uses_prim_id(sctx
);
3019 old_sel
->info
.colors_written
!= sel
->info
.colors_written
)
3020 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3022 if (sctx
->screen
->has_out_of_order_rast
&&
3024 old_sel
->info
.writes_memory
!= sel
->info
.writes_memory
||
3025 old_sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] !=
3026 sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]))
3027 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3029 si_set_active_descriptors_for_shader(sctx
, sel
);
3030 si_update_ps_colorbuf0_slot(sctx
);
3033 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
3035 if (shader
->is_optimized
) {
3036 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue_low_priority
,
3040 util_queue_fence_destroy(&shader
->ready
);
3043 switch (shader
->selector
->type
) {
3044 case PIPE_SHADER_VERTEX
:
3045 if (shader
->key
.as_ls
) {
3046 assert(sctx
->chip_class
<= GFX8
);
3047 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
3048 } else if (shader
->key
.as_es
) {
3049 assert(sctx
->chip_class
<= GFX8
);
3050 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
3052 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3055 case PIPE_SHADER_TESS_CTRL
:
3056 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
3058 case PIPE_SHADER_TESS_EVAL
:
3059 if (shader
->key
.as_es
) {
3060 assert(sctx
->chip_class
<= GFX8
);
3061 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
3063 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3066 case PIPE_SHADER_GEOMETRY
:
3067 if (shader
->is_gs_copy_shader
)
3068 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3070 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3072 case PIPE_SHADER_FRAGMENT
:
3073 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
3078 si_shader_selector_reference(sctx
, &shader
->previous_stage_sel
, NULL
);
3079 si_shader_destroy(shader
);
3083 void si_destroy_shader_selector(struct si_context
*sctx
,
3084 struct si_shader_selector
*sel
)
3086 struct si_shader
*p
= sel
->first_variant
, *c
;
3087 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
3088 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
3089 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
3090 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
3091 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
3092 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
3095 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue
, &sel
->ready
);
3097 if (current_shader
[sel
->type
]->cso
== sel
) {
3098 current_shader
[sel
->type
]->cso
= NULL
;
3099 current_shader
[sel
->type
]->current
= NULL
;
3103 c
= p
->next_variant
;
3104 si_delete_shader(sctx
, p
);
3108 if (sel
->main_shader_part
)
3109 si_delete_shader(sctx
, sel
->main_shader_part
);
3110 if (sel
->main_shader_part_ls
)
3111 si_delete_shader(sctx
, sel
->main_shader_part_ls
);
3112 if (sel
->main_shader_part_es
)
3113 si_delete_shader(sctx
, sel
->main_shader_part_es
);
3114 if (sel
->main_shader_part_ngg
)
3115 si_delete_shader(sctx
, sel
->main_shader_part_ngg
);
3116 if (sel
->gs_copy_shader
)
3117 si_delete_shader(sctx
, sel
->gs_copy_shader
);
3119 util_queue_fence_destroy(&sel
->ready
);
3120 mtx_destroy(&sel
->mutex
);
3122 ralloc_free(sel
->nir
);
3126 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
3128 struct si_context
*sctx
= (struct si_context
*)ctx
;
3129 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
3131 si_shader_selector_reference(sctx
, &sel
, NULL
);
3134 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
3135 struct si_shader
*vs
, unsigned name
,
3136 unsigned index
, unsigned interpolate
)
3138 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
3139 unsigned j
, offset
, ps_input_cntl
= 0;
3141 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
3142 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
) ||
3143 name
== TGSI_SEMANTIC_PRIMID
)
3144 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
3146 if (name
== TGSI_SEMANTIC_PCOORD
||
3147 (name
== TGSI_SEMANTIC_TEXCOORD
&&
3148 sctx
->sprite_coord_enable
& (1 << index
))) {
3149 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
3152 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
3153 if (name
== vsinfo
->output_semantic_name
[j
] &&
3154 index
== vsinfo
->output_semantic_index
[j
]) {
3155 offset
= vs
->info
.vs_output_param_offset
[j
];
3157 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
3158 /* The input is loaded from parameter memory. */
3159 ps_input_cntl
|= S_028644_OFFSET(offset
);
3160 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
3161 if (offset
== AC_EXP_PARAM_UNDEFINED
) {
3162 /* This can happen with depth-only rendering. */
3165 /* The input is a DEFAULT_VAL constant. */
3166 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
3167 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
3168 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
3171 ps_input_cntl
= S_028644_OFFSET(0x20) |
3172 S_028644_DEFAULT_VAL(offset
);
3178 if (j
== vsinfo
->num_outputs
&& name
== TGSI_SEMANTIC_PRIMID
)
3179 /* PrimID is written after the last output when HW VS is used. */
3180 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
3181 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
3182 /* No corresponding output found, load defaults into input.
3183 * Don't set any other bits.
3184 * (FLAT_SHADE=1 completely changes behavior) */
3185 ps_input_cntl
= S_028644_OFFSET(0x20);
3186 /* D3D 9 behaviour. GL is undefined */
3187 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
3188 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
3190 return ps_input_cntl
;
3193 static void si_emit_spi_map(struct si_context
*sctx
)
3195 struct si_shader
*ps
= sctx
->ps_shader
.current
;
3196 struct si_shader
*vs
= si_get_vs_state(sctx
);
3197 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
3198 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
3199 unsigned spi_ps_input_cntl
[32];
3201 if (!ps
|| !ps
->selector
->info
.num_inputs
)
3204 num_interp
= si_get_ps_num_interp(ps
);
3205 assert(num_interp
> 0);
3207 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
3208 unsigned name
= psinfo
->input_semantic_name
[i
];
3209 unsigned index
= psinfo
->input_semantic_index
[i
];
3210 unsigned interpolate
= psinfo
->input_interpolate
[i
];
3212 spi_ps_input_cntl
[num_written
++] = si_get_ps_input_cntl(sctx
, vs
, name
,
3213 index
, interpolate
);
3215 if (name
== TGSI_SEMANTIC_COLOR
) {
3216 assert(index
< ARRAY_SIZE(bcol_interp
));
3217 bcol_interp
[index
] = interpolate
;
3221 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
3222 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
3224 for (i
= 0; i
< 2; i
++) {
3225 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
3228 spi_ps_input_cntl
[num_written
++] =
3229 si_get_ps_input_cntl(sctx
, vs
, bcol
, i
, bcol_interp
[i
]);
3233 assert(num_interp
== num_written
);
3235 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3236 /* Dota 2: Only ~16% of SPI map updates set different values. */
3237 /* Talos: Only ~9% of SPI map updates set different values. */
3238 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
3239 radeon_opt_set_context_regn(sctx
, R_028644_SPI_PS_INPUT_CNTL_0
,
3241 sctx
->tracked_regs
.spi_ps_input_cntl
, num_interp
);
3243 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
3244 sctx
->context_roll
= true;
3248 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3250 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
3252 if (sctx
->init_config_has_vgt_flush
)
3255 /* Done by Vulkan before VGT_FLUSH. */
3256 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
3257 si_pm4_cmd_add(sctx
->init_config
,
3258 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3259 si_pm4_cmd_end(sctx
->init_config
, false);
3261 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3262 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
3263 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
3264 si_pm4_cmd_end(sctx
->init_config
, false);
3265 sctx
->init_config_has_vgt_flush
= true;
3268 /* Initialize state related to ESGS / GSVS ring buffers */
3269 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
3271 struct si_shader_selector
*es
=
3272 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
3273 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
3274 struct si_pm4_state
*pm4
;
3276 /* Chip constants. */
3277 unsigned num_se
= sctx
->screen
->info
.max_se
;
3278 unsigned wave_size
= 64;
3279 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
3280 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3281 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3283 unsigned gs_vertex_reuse
= (sctx
->chip_class
>= GFX8
? 32 : 16) * num_se
;
3284 unsigned alignment
= 256 * num_se
;
3285 /* The maximum size is 63.999 MB per SE. */
3286 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
3288 /* Calculate the minimum size. */
3289 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
3290 wave_size
, alignment
);
3292 /* These are recommended sizes, not minimum sizes. */
3293 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
3294 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
3295 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
3296 gs
->max_gsvs_emit_size
;
3298 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
3299 esgs_ring_size
= align(esgs_ring_size
, alignment
);
3300 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
3302 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
3303 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
3305 /* Some rings don't have to be allocated if shaders don't use them.
3306 * (e.g. no varyings between ES and GS or GS and VS)
3308 * GFX9 doesn't have the ESGS ring.
3310 bool update_esgs
= sctx
->chip_class
<= GFX8
&&
3312 (!sctx
->esgs_ring
||
3313 sctx
->esgs_ring
->width0
< esgs_ring_size
);
3314 bool update_gsvs
= gsvs_ring_size
&&
3315 (!sctx
->gsvs_ring
||
3316 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
3318 if (!update_esgs
&& !update_gsvs
)
3322 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
3324 pipe_aligned_buffer_create(sctx
->b
.screen
,
3325 SI_RESOURCE_FLAG_UNMAPPABLE
,
3327 esgs_ring_size
, alignment
);
3328 if (!sctx
->esgs_ring
)
3333 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
3335 pipe_aligned_buffer_create(sctx
->b
.screen
,
3336 SI_RESOURCE_FLAG_UNMAPPABLE
,
3338 gsvs_ring_size
, alignment
);
3339 if (!sctx
->gsvs_ring
)
3343 /* Create the "init_config_gs_rings" state. */
3344 pm4
= CALLOC_STRUCT(si_pm4_state
);
3348 if (sctx
->chip_class
>= GFX7
) {
3349 if (sctx
->esgs_ring
) {
3350 assert(sctx
->chip_class
<= GFX8
);
3351 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
3352 sctx
->esgs_ring
->width0
/ 256);
3354 if (sctx
->gsvs_ring
)
3355 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
3356 sctx
->gsvs_ring
->width0
/ 256);
3358 if (sctx
->esgs_ring
)
3359 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
3360 sctx
->esgs_ring
->width0
/ 256);
3361 if (sctx
->gsvs_ring
)
3362 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
3363 sctx
->gsvs_ring
->width0
/ 256);
3366 /* Set the state. */
3367 if (sctx
->init_config_gs_rings
)
3368 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
3369 sctx
->init_config_gs_rings
= pm4
;
3371 if (!sctx
->init_config_has_vgt_flush
) {
3372 si_init_config_add_vgt_flush(sctx
);
3373 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3376 /* Flush the context to re-emit both init_config states. */
3377 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3378 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3380 /* Set ring bindings. */
3381 if (sctx
->esgs_ring
) {
3382 assert(sctx
->chip_class
<= GFX8
);
3383 si_set_ring_buffer(sctx
, SI_ES_RING_ESGS
,
3384 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
3385 true, true, 4, 64, 0);
3386 si_set_ring_buffer(sctx
, SI_GS_RING_ESGS
,
3387 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
3388 false, false, 0, 0, 0);
3390 if (sctx
->gsvs_ring
) {
3391 si_set_ring_buffer(sctx
, SI_RING_GSVS
,
3392 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
3393 false, false, 0, 0, 0);
3399 static void si_shader_lock(struct si_shader
*shader
)
3401 mtx_lock(&shader
->selector
->mutex
);
3402 if (shader
->previous_stage_sel
) {
3403 assert(shader
->previous_stage_sel
!= shader
->selector
);
3404 mtx_lock(&shader
->previous_stage_sel
->mutex
);
3408 static void si_shader_unlock(struct si_shader
*shader
)
3410 if (shader
->previous_stage_sel
)
3411 mtx_unlock(&shader
->previous_stage_sel
->mutex
);
3412 mtx_unlock(&shader
->selector
->mutex
);
3416 * @returns 1 if \p sel has been updated to use a new scratch buffer
3418 * < 0 if there was a failure
3420 static int si_update_scratch_buffer(struct si_context
*sctx
,
3421 struct si_shader
*shader
)
3423 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
3428 /* This shader doesn't need a scratch buffer */
3429 if (shader
->config
.scratch_bytes_per_wave
== 0)
3432 /* Prevent race conditions when updating:
3433 * - si_shader::scratch_bo
3434 * - si_shader::binary::code
3435 * - si_shader::previous_stage::binary::code.
3437 si_shader_lock(shader
);
3439 /* This shader is already configured to use the current
3440 * scratch buffer. */
3441 if (shader
->scratch_bo
== sctx
->scratch_buffer
) {
3442 si_shader_unlock(shader
);
3446 assert(sctx
->scratch_buffer
);
3448 /* Replace the shader bo with a new bo that has the relocs applied. */
3449 if (!si_shader_binary_upload(sctx
->screen
, shader
, scratch_va
)) {
3450 si_shader_unlock(shader
);
3454 /* Update the shader state to use the new shader bo. */
3455 si_shader_init_pm4_state(sctx
->screen
, shader
);
3457 si_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
3459 si_shader_unlock(shader
);
3463 static unsigned si_get_current_scratch_buffer_size(struct si_context
*sctx
)
3465 return sctx
->scratch_buffer
? sctx
->scratch_buffer
->b
.b
.width0
: 0;
3468 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
3470 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
3473 static struct si_shader
*si_get_tcs_current(struct si_context
*sctx
)
3475 if (!sctx
->tes_shader
.cso
)
3476 return NULL
; /* tessellation disabled */
3478 return sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.current
:
3479 sctx
->fixed_func_tcs_shader
.current
;
3482 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context
*sctx
)
3486 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
3487 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
3488 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
3489 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
3491 if (sctx
->tes_shader
.cso
) {
3492 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
3494 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(tcs
));
3499 static bool si_update_scratch_relocs(struct si_context
*sctx
)
3501 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
3504 /* Update the shaders, so that they are using the latest scratch.
3505 * The scratch buffer may have been changed since these shaders were
3506 * last used, so we still need to try to update them, even if they
3507 * require scratch buffers smaller than the current size.
3509 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
3513 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3515 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
3519 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3521 r
= si_update_scratch_buffer(sctx
, tcs
);
3525 si_pm4_bind_state(sctx
, hs
, tcs
->pm4
);
3527 /* VS can be bound as LS, ES, or VS. */
3528 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
3532 if (sctx
->vs_shader
.current
->key
.as_ls
)
3533 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3534 else if (sctx
->vs_shader
.current
->key
.as_es
)
3535 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3536 else if (sctx
->vs_shader
.current
->key
.as_ngg
)
3537 si_pm4_bind_state(sctx
, gs
, sctx
->vs_shader
.current
->pm4
);
3539 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3542 /* TES can be bound as ES or VS. */
3543 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
3547 if (sctx
->tes_shader
.current
->key
.as_es
)
3548 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3549 else if (sctx
->tes_shader
.current
->key
.as_ngg
)
3550 si_pm4_bind_state(sctx
, gs
, sctx
->tes_shader
.current
->pm4
);
3552 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3558 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
3560 unsigned current_scratch_buffer_size
=
3561 si_get_current_scratch_buffer_size(sctx
);
3562 unsigned scratch_bytes_per_wave
=
3563 si_get_max_scratch_bytes_per_wave(sctx
);
3564 unsigned scratch_needed_size
= scratch_bytes_per_wave
*
3565 sctx
->scratch_waves
;
3566 unsigned spi_tmpring_size
;
3568 if (scratch_needed_size
> 0) {
3569 if (scratch_needed_size
> current_scratch_buffer_size
) {
3570 /* Create a bigger scratch buffer */
3571 si_resource_reference(&sctx
->scratch_buffer
, NULL
);
3573 sctx
->scratch_buffer
=
3574 si_aligned_buffer_create(&sctx
->screen
->b
,
3575 SI_RESOURCE_FLAG_UNMAPPABLE
,
3577 scratch_needed_size
, 256);
3578 if (!sctx
->scratch_buffer
)
3581 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3582 si_context_add_resource_size(sctx
,
3583 &sctx
->scratch_buffer
->b
.b
);
3586 if (!si_update_scratch_relocs(sctx
))
3590 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3591 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
3592 "scratch size should already be aligned correctly.");
3594 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
3595 S_0286E8_WAVESIZE(scratch_bytes_per_wave
>> 10);
3596 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
3597 sctx
->spi_tmpring_size
= spi_tmpring_size
;
3598 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3603 static void si_init_tess_factor_ring(struct si_context
*sctx
)
3605 assert(!sctx
->tess_rings
);
3607 /* The address must be aligned to 2^19, because the shader only
3608 * receives the high 13 bits.
3610 sctx
->tess_rings
= pipe_aligned_buffer_create(sctx
->b
.screen
,
3611 SI_RESOURCE_FLAG_32BIT
,
3613 sctx
->screen
->tess_offchip_ring_size
+
3614 sctx
->screen
->tess_factor_ring_size
,
3616 if (!sctx
->tess_rings
)
3619 si_init_config_add_vgt_flush(sctx
);
3621 si_pm4_add_bo(sctx
->init_config
, si_resource(sctx
->tess_rings
),
3622 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
3624 uint64_t factor_va
= si_resource(sctx
->tess_rings
)->gpu_address
+
3625 sctx
->screen
->tess_offchip_ring_size
;
3627 /* Append these registers to the init config state. */
3628 if (sctx
->chip_class
>= GFX7
) {
3629 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
3630 S_030938_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3631 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
3633 if (sctx
->chip_class
>= GFX10
)
3634 si_pm4_set_reg(sctx
->init_config
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
3635 S_030984_BASE_HI(factor_va
>> 40));
3636 else if (sctx
->chip_class
== GFX9
)
3637 si_pm4_set_reg(sctx
->init_config
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3638 S_030944_BASE_HI(factor_va
>> 40));
3639 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3640 sctx
->screen
->vgt_hs_offchip_param
);
3642 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
3643 S_008988_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3644 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
3646 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3647 sctx
->screen
->vgt_hs_offchip_param
);
3650 /* Flush the context to re-emit the init_config state.
3651 * This is done only once in a lifetime of a context.
3653 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3654 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3655 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3658 static struct si_pm4_state
*si_build_vgt_shader_config(struct si_screen
*screen
,
3659 union si_vgt_stages_key key
)
3661 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
3662 uint32_t stages
= 0;
3665 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3666 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3669 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3672 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
3674 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3675 } else if (key
.u
.gs
) {
3676 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3678 } else if (key
.u
.ngg
) {
3679 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
3683 stages
|= S_028B54_PRIMGEN_EN(1);
3684 if (key
.u
.streamout
)
3685 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
3686 } else if (key
.u
.gs
)
3687 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3689 if (screen
->info
.chip_class
>= GFX9
)
3690 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3692 si_pm4_set_reg(pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
3696 static void si_update_vgt_shader_config(struct si_context
*sctx
,
3697 union si_vgt_stages_key key
)
3699 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[key
.index
];
3701 if (unlikely(!*pm4
))
3702 *pm4
= si_build_vgt_shader_config(sctx
->screen
, key
);
3703 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
3706 bool si_update_shaders(struct si_context
*sctx
)
3708 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
3709 struct si_compiler_ctx_state compiler_state
;
3710 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3711 struct si_shader
*old_vs
= si_get_vs_state(sctx
);
3712 bool old_clip_disable
= old_vs
? old_vs
->key
.opt
.clip_disable
: false;
3713 struct si_shader
*old_ps
= sctx
->ps_shader
.current
;
3714 union si_vgt_stages_key key
;
3715 unsigned old_spi_shader_col_format
=
3716 old_ps
? old_ps
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
3719 compiler_state
.compiler
= &sctx
->compiler
;
3720 compiler_state
.debug
= sctx
->debug
;
3721 compiler_state
.is_debug_context
= sctx
->is_debug
;
3725 if (sctx
->tes_shader
.cso
)
3727 if (sctx
->gs_shader
.cso
)
3730 if (sctx
->chip_class
>= GFX10
) {
3731 key
.u
.ngg
= sctx
->ngg
;
3733 if (sctx
->gs_shader
.cso
)
3734 key
.u
.streamout
= !!sctx
->gs_shader
.cso
->so
.num_outputs
;
3735 else if (sctx
->tes_shader
.cso
)
3736 key
.u
.streamout
= !!sctx
->tes_shader
.cso
->so
.num_outputs
;
3738 key
.u
.streamout
= !!sctx
->vs_shader
.cso
->so
.num_outputs
;
3741 /* Update TCS and TES. */
3742 if (sctx
->tes_shader
.cso
) {
3743 if (!sctx
->tess_rings
) {
3744 si_init_tess_factor_ring(sctx
);
3745 if (!sctx
->tess_rings
)
3749 if (sctx
->tcs_shader
.cso
) {
3750 r
= si_shader_select(ctx
, &sctx
->tcs_shader
, key
,
3754 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
3756 if (!sctx
->fixed_func_tcs_shader
.cso
) {
3757 sctx
->fixed_func_tcs_shader
.cso
=
3758 si_create_fixed_func_tcs(sctx
);
3759 if (!sctx
->fixed_func_tcs_shader
.cso
)
3763 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
,
3764 key
, &compiler_state
);
3767 si_pm4_bind_state(sctx
, hs
,
3768 sctx
->fixed_func_tcs_shader
.current
->pm4
);
3771 if (!sctx
->gs_shader
.cso
|| sctx
->chip_class
<= GFX8
) {
3772 r
= si_shader_select(ctx
, &sctx
->tes_shader
, key
, &compiler_state
);
3776 if (sctx
->gs_shader
.cso
) {
3778 assert(sctx
->chip_class
<= GFX8
);
3779 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3780 } else if (key
.u
.ngg
) {
3781 si_pm4_bind_state(sctx
, gs
, sctx
->tes_shader
.current
->pm4
);
3783 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3787 if (sctx
->chip_class
<= GFX8
)
3788 si_pm4_bind_state(sctx
, ls
, NULL
);
3789 si_pm4_bind_state(sctx
, hs
, NULL
);
3793 if (sctx
->gs_shader
.cso
) {
3794 r
= si_shader_select(ctx
, &sctx
->gs_shader
, key
, &compiler_state
);
3797 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3799 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
3801 if (!si_update_gs_ring_buffers(sctx
))
3804 si_pm4_bind_state(sctx
, vs
, NULL
);
3808 si_pm4_bind_state(sctx
, gs
, NULL
);
3809 if (sctx
->chip_class
<= GFX8
)
3810 si_pm4_bind_state(sctx
, es
, NULL
);
3815 if ((!key
.u
.tess
&& !key
.u
.gs
) || sctx
->chip_class
<= GFX8
) {
3816 r
= si_shader_select(ctx
, &sctx
->vs_shader
, key
, &compiler_state
);
3820 if (!key
.u
.tess
&& !key
.u
.gs
) {
3822 si_pm4_bind_state(sctx
, gs
, sctx
->vs_shader
.current
->pm4
);
3823 si_pm4_bind_state(sctx
, vs
, NULL
);
3825 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3827 } else if (sctx
->tes_shader
.cso
) {
3828 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3830 assert(sctx
->gs_shader
.cso
);
3831 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3835 si_update_vgt_shader_config(sctx
, key
);
3837 if (old_clip_disable
!= si_get_vs_state(sctx
)->key
.opt
.clip_disable
)
3838 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
3840 if (sctx
->ps_shader
.cso
) {
3841 unsigned db_shader_control
;
3843 r
= si_shader_select(ctx
, &sctx
->ps_shader
, key
, &compiler_state
);
3846 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3849 sctx
->ps_shader
.cso
->db_shader_control
|
3850 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
3852 if (si_pm4_state_changed(sctx
, ps
) ||
3853 si_pm4_state_changed(sctx
, vs
) ||
3854 (key
.u
.ngg
&& si_pm4_state_changed(sctx
, gs
)) ||
3855 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
3856 sctx
->flatshade
!= rs
->flatshade
) {
3857 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
3858 sctx
->flatshade
= rs
->flatshade
;
3859 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.spi_map
);
3862 if (sctx
->screen
->rbplus_allowed
&&
3863 si_pm4_state_changed(sctx
, ps
) &&
3865 old_spi_shader_col_format
!=
3866 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
))
3867 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3869 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
3870 sctx
->ps_db_shader_control
= db_shader_control
;
3871 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3872 if (sctx
->screen
->dpbb_allowed
)
3873 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3876 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
3877 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
3878 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3880 if (sctx
->chip_class
== GFX6
)
3881 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3883 if (sctx
->framebuffer
.nr_samples
<= 1)
3884 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
3888 if (si_pm4_state_enabled_and_changed(sctx
, ls
) ||
3889 si_pm4_state_enabled_and_changed(sctx
, hs
) ||
3890 si_pm4_state_enabled_and_changed(sctx
, es
) ||
3891 si_pm4_state_enabled_and_changed(sctx
, gs
) ||
3892 si_pm4_state_enabled_and_changed(sctx
, vs
) ||
3893 si_pm4_state_enabled_and_changed(sctx
, ps
)) {
3894 if (!si_update_spi_tmpring_size(sctx
))
3898 if (sctx
->chip_class
>= GFX7
) {
3899 if (si_pm4_state_enabled_and_changed(sctx
, ls
))
3900 sctx
->prefetch_L2_mask
|= SI_PREFETCH_LS
;
3901 else if (!sctx
->queued
.named
.ls
)
3902 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_LS
;
3904 if (si_pm4_state_enabled_and_changed(sctx
, hs
))
3905 sctx
->prefetch_L2_mask
|= SI_PREFETCH_HS
;
3906 else if (!sctx
->queued
.named
.hs
)
3907 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_HS
;
3909 if (si_pm4_state_enabled_and_changed(sctx
, es
))
3910 sctx
->prefetch_L2_mask
|= SI_PREFETCH_ES
;
3911 else if (!sctx
->queued
.named
.es
)
3912 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_ES
;
3914 if (si_pm4_state_enabled_and_changed(sctx
, gs
))
3915 sctx
->prefetch_L2_mask
|= SI_PREFETCH_GS
;
3916 else if (!sctx
->queued
.named
.gs
)
3917 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_GS
;
3919 if (si_pm4_state_enabled_and_changed(sctx
, vs
))
3920 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VS
;
3921 else if (!sctx
->queued
.named
.vs
)
3922 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_VS
;
3924 if (si_pm4_state_enabled_and_changed(sctx
, ps
))
3925 sctx
->prefetch_L2_mask
|= SI_PREFETCH_PS
;
3926 else if (!sctx
->queued
.named
.ps
)
3927 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_PS
;
3930 sctx
->do_update_shaders
= false;
3934 static void si_emit_scratch_state(struct si_context
*sctx
)
3936 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3938 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
3939 sctx
->spi_tmpring_size
);
3941 if (sctx
->scratch_buffer
) {
3942 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3943 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
3944 RADEON_PRIO_SCRATCH_BUFFER
);
3948 void si_init_shader_functions(struct si_context
*sctx
)
3950 sctx
->atoms
.s
.spi_map
.emit
= si_emit_spi_map
;
3951 sctx
->atoms
.s
.scratch_state
.emit
= si_emit_scratch_state
;
3953 sctx
->b
.create_vs_state
= si_create_shader_selector
;
3954 sctx
->b
.create_tcs_state
= si_create_shader_selector
;
3955 sctx
->b
.create_tes_state
= si_create_shader_selector
;
3956 sctx
->b
.create_gs_state
= si_create_shader_selector
;
3957 sctx
->b
.create_fs_state
= si_create_shader_selector
;
3959 sctx
->b
.bind_vs_state
= si_bind_vs_shader
;
3960 sctx
->b
.bind_tcs_state
= si_bind_tcs_shader
;
3961 sctx
->b
.bind_tes_state
= si_bind_tes_shader
;
3962 sctx
->b
.bind_gs_state
= si_bind_gs_shader
;
3963 sctx
->b
.bind_fs_state
= si_bind_ps_shader
;
3965 sctx
->b
.delete_vs_state
= si_delete_shader_selector
;
3966 sctx
->b
.delete_tcs_state
= si_delete_shader_selector
;
3967 sctx
->b
.delete_tes_state
= si_delete_shader_selector
;
3968 sctx
->b
.delete_gs_state
= si_delete_shader_selector
;
3969 sctx
->b
.delete_fs_state
= si_delete_shader_selector
;