2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
31 #include "radeon/r600_cs.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/hash_table.h"
36 #include "util/crc32.h"
37 #include "util/u_memory.h"
38 #include "util/u_prim.h"
40 #include "util/disk_cache.h"
41 #include "util/mesa-sha1.h"
42 #include "ac_exp_param.h"
47 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
50 static void *si_get_tgsi_binary(struct si_shader_selector
*sel
)
52 unsigned tgsi_size
= tgsi_num_tokens(sel
->tokens
) *
53 sizeof(struct tgsi_token
);
54 unsigned size
= 4 + tgsi_size
+ sizeof(sel
->so
);
55 char *result
= (char*)MALLOC(size
);
60 *((uint32_t*)result
) = size
;
61 memcpy(result
+ 4, sel
->tokens
, tgsi_size
);
62 memcpy(result
+ 4 + tgsi_size
, &sel
->so
, sizeof(sel
->so
));
66 /** Copy "data" to "ptr" and return the next dword following copied data. */
67 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
69 /* data may be NULL if size == 0 */
71 memcpy(ptr
, data
, size
);
72 ptr
+= DIV_ROUND_UP(size
, 4);
76 /** Read data from "ptr". Return the next dword following the data. */
77 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
79 memcpy(data
, ptr
, size
);
80 ptr
+= DIV_ROUND_UP(size
, 4);
85 * Write the size as uint followed by the data. Return the next dword
86 * following the copied data.
88 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
91 return write_data(ptr
, data
, size
);
95 * Read the size as uint followed by the data. Return both via parameters.
96 * Return the next dword following the data.
98 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
101 assert(*data
== NULL
);
104 *data
= malloc(*size
);
105 return read_data(ptr
, *data
, *size
);
109 * Return the shader binary in a buffer. The first 4 bytes contain its size
112 static void *si_get_shader_binary(struct si_shader
*shader
)
114 /* There is always a size of data followed by the data itself. */
115 unsigned relocs_size
= shader
->binary
.reloc_count
*
116 sizeof(shader
->binary
.relocs
[0]);
117 unsigned disasm_size
= shader
->binary
.disasm_string
?
118 strlen(shader
->binary
.disasm_string
) + 1 : 0;
119 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
120 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
123 4 + /* CRC32 of the data below */
124 align(sizeof(shader
->config
), 4) +
125 align(sizeof(shader
->info
), 4) +
126 4 + align(shader
->binary
.code_size
, 4) +
127 4 + align(shader
->binary
.rodata_size
, 4) +
128 4 + align(relocs_size
, 4) +
129 4 + align(disasm_size
, 4) +
130 4 + align(llvm_ir_size
, 4);
131 void *buffer
= CALLOC(1, size
);
132 uint32_t *ptr
= (uint32_t*)buffer
;
138 ptr
++; /* CRC32 is calculated at the end. */
140 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
141 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
142 ptr
= write_chunk(ptr
, shader
->binary
.code
, shader
->binary
.code_size
);
143 ptr
= write_chunk(ptr
, shader
->binary
.rodata
, shader
->binary
.rodata_size
);
144 ptr
= write_chunk(ptr
, shader
->binary
.relocs
, relocs_size
);
145 ptr
= write_chunk(ptr
, shader
->binary
.disasm_string
, disasm_size
);
146 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
147 assert((char *)ptr
- (char *)buffer
== size
);
150 ptr
= (uint32_t*)buffer
;
152 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
157 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
159 uint32_t *ptr
= (uint32_t*)binary
;
160 uint32_t size
= *ptr
++;
161 uint32_t crc32
= *ptr
++;
164 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
165 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
169 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
170 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
171 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.code
,
172 &shader
->binary
.code_size
);
173 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.rodata
,
174 &shader
->binary
.rodata_size
);
175 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.relocs
, &chunk_size
);
176 shader
->binary
.reloc_count
= chunk_size
/ sizeof(shader
->binary
.relocs
[0]);
177 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.disasm_string
, &chunk_size
);
178 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
184 * Insert a shader into the cache. It's assumed the shader is not in the cache.
185 * Use si_shader_cache_load_shader before calling this.
187 * Returns false on failure, in which case the tgsi_binary should be freed.
189 static bool si_shader_cache_insert_shader(struct si_screen
*sscreen
,
191 struct si_shader
*shader
,
192 bool insert_into_disk_cache
)
195 struct hash_entry
*entry
;
196 uint8_t key
[CACHE_KEY_SIZE
];
198 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, tgsi_binary
);
200 return false; /* already added */
202 hw_binary
= si_get_shader_binary(shader
);
206 if (_mesa_hash_table_insert(sscreen
->shader_cache
, tgsi_binary
,
207 hw_binary
) == NULL
) {
212 if (sscreen
->b
.disk_shader_cache
&& insert_into_disk_cache
) {
213 disk_cache_compute_key(sscreen
->b
.disk_shader_cache
, tgsi_binary
,
214 *((uint32_t *)tgsi_binary
), key
);
215 disk_cache_put(sscreen
->b
.disk_shader_cache
, key
, hw_binary
,
216 *((uint32_t *) hw_binary
));
222 static bool si_shader_cache_load_shader(struct si_screen
*sscreen
,
224 struct si_shader
*shader
)
226 struct hash_entry
*entry
=
227 _mesa_hash_table_search(sscreen
->shader_cache
, tgsi_binary
);
229 if (sscreen
->b
.disk_shader_cache
) {
230 unsigned char sha1
[CACHE_KEY_SIZE
];
231 size_t tg_size
= *((uint32_t *) tgsi_binary
);
233 disk_cache_compute_key(sscreen
->b
.disk_shader_cache
,
234 tgsi_binary
, tg_size
, sha1
);
238 disk_cache_get(sscreen
->b
.disk_shader_cache
,
243 if (binary_size
< sizeof(uint32_t) ||
244 *((uint32_t*)buffer
) != binary_size
) {
245 /* Something has gone wrong discard the item
246 * from the cache and rebuild/link from
249 assert(!"Invalid radeonsi shader disk cache "
252 disk_cache_remove(sscreen
->b
.disk_shader_cache
,
259 if (!si_load_shader_binary(shader
, buffer
)) {
265 if (!si_shader_cache_insert_shader(sscreen
, tgsi_binary
,
272 if (si_load_shader_binary(shader
, entry
->data
))
277 p_atomic_inc(&sscreen
->b
.num_shader_cache_hits
);
281 static uint32_t si_shader_cache_key_hash(const void *key
)
283 /* The first dword is the key size. */
284 return util_hash_crc32(key
, *(uint32_t*)key
);
287 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
289 uint32_t *keya
= (uint32_t*)a
;
290 uint32_t *keyb
= (uint32_t*)b
;
292 /* The first dword is the key size. */
296 return memcmp(keya
, keyb
, *keya
) == 0;
299 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
301 FREE((void*)entry
->key
);
305 bool si_init_shader_cache(struct si_screen
*sscreen
)
307 (void) mtx_init(&sscreen
->shader_cache_mutex
, mtx_plain
);
308 sscreen
->shader_cache
=
309 _mesa_hash_table_create(NULL
,
310 si_shader_cache_key_hash
,
311 si_shader_cache_key_equals
);
313 return sscreen
->shader_cache
!= NULL
;
316 void si_destroy_shader_cache(struct si_screen
*sscreen
)
318 if (sscreen
->shader_cache
)
319 _mesa_hash_table_destroy(sscreen
->shader_cache
,
320 si_destroy_shader_cache_entry
);
321 mtx_destroy(&sscreen
->shader_cache_mutex
);
326 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
327 struct si_shader_selector
*tes
,
328 struct si_pm4_state
*pm4
)
330 struct tgsi_shader_info
*info
= &tes
->info
;
331 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
332 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
333 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
334 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
335 unsigned type
, partitioning
, topology
, distribution_mode
;
337 switch (tes_prim_mode
) {
338 case PIPE_PRIM_LINES
:
339 type
= V_028B6C_TESS_ISOLINE
;
341 case PIPE_PRIM_TRIANGLES
:
342 type
= V_028B6C_TESS_TRIANGLE
;
344 case PIPE_PRIM_QUADS
:
345 type
= V_028B6C_TESS_QUAD
;
352 switch (tes_spacing
) {
353 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
354 partitioning
= V_028B6C_PART_FRAC_ODD
;
356 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
357 partitioning
= V_028B6C_PART_FRAC_EVEN
;
359 case PIPE_TESS_SPACING_EQUAL
:
360 partitioning
= V_028B6C_PART_INTEGER
;
368 topology
= V_028B6C_OUTPUT_POINT
;
369 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
370 topology
= V_028B6C_OUTPUT_LINE
;
371 else if (tes_vertex_order_cw
)
372 /* for some reason, this must be the other way around */
373 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
375 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
377 if (sscreen
->has_distributed_tess
) {
378 if (sscreen
->b
.family
== CHIP_FIJI
||
379 sscreen
->b
.family
>= CHIP_POLARIS10
)
380 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
382 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
384 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
386 si_pm4_set_reg(pm4
, R_028B6C_VGT_TF_PARAM
,
387 S_028B6C_TYPE(type
) |
388 S_028B6C_PARTITIONING(partitioning
) |
389 S_028B6C_TOPOLOGY(topology
) |
390 S_028B6C_DISTRIBUTION_MODE(distribution_mode
));
393 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
394 * whether the "fractional odd" tessellation spacing is used.
396 * Possible VGT configurations and which state should set the register:
398 * Reg set in | VGT shader configuration | Value
399 * ------------------------------------------------------
401 * VS as ES | ES -> GS -> VS | 30
402 * TES as VS | LS -> HS -> VS | 14 or 30
403 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
405 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
407 static void polaris_set_vgt_vertex_reuse(struct si_screen
*sscreen
,
408 struct si_shader_selector
*sel
,
409 struct si_shader
*shader
,
410 struct si_pm4_state
*pm4
)
412 unsigned type
= sel
->type
;
414 if (sscreen
->b
.family
< CHIP_POLARIS10
)
417 /* VS as VS, or VS as ES: */
418 if ((type
== PIPE_SHADER_VERTEX
&&
420 (!shader
->key
.as_ls
&& !shader
->is_gs_copy_shader
))) ||
421 /* TES as VS, or TES as ES: */
422 type
== PIPE_SHADER_TESS_EVAL
) {
423 unsigned vtx_reuse_depth
= 30;
425 if (type
== PIPE_SHADER_TESS_EVAL
&&
426 sel
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] ==
427 PIPE_TESS_SPACING_FRACTIONAL_ODD
)
428 vtx_reuse_depth
= 14;
430 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
435 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
438 si_pm4_clear_state(shader
->pm4
);
440 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
445 static void si_shader_ls(struct si_screen
*sscreen
, struct si_shader
*shader
)
447 struct si_pm4_state
*pm4
;
448 unsigned vgpr_comp_cnt
;
451 assert(sscreen
->b
.chip_class
<= VI
);
453 pm4
= si_get_shader_pm4_state(shader
);
457 va
= shader
->bo
->gpu_address
;
458 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
460 /* We need at least 2 components for LS.
461 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
462 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
464 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
466 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
467 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, va
>> 40);
469 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
470 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
471 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt
) |
472 S_00B528_DX10_CLAMP(1) |
473 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
474 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(SI_VS_NUM_USER_SGPR
) |
475 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
478 static void si_shader_hs(struct si_screen
*sscreen
, struct si_shader
*shader
)
480 struct si_pm4_state
*pm4
;
482 unsigned ls_vgpr_comp_cnt
= 0;
484 pm4
= si_get_shader_pm4_state(shader
);
488 va
= shader
->bo
->gpu_address
;
489 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
491 if (sscreen
->b
.chip_class
>= GFX9
) {
492 si_pm4_set_reg(pm4
, R_00B410_SPI_SHADER_PGM_LO_LS
, va
>> 8);
493 si_pm4_set_reg(pm4
, R_00B414_SPI_SHADER_PGM_HI_LS
, va
>> 40);
495 /* We need at least 2 components for LS.
496 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
497 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
499 ls_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
501 if (shader
->config
.scratch_bytes_per_wave
) {
502 fprintf(stderr
, "HS: scratch buffer unsupported");
506 shader
->config
.rsrc2
=
507 S_00B42C_USER_SGPR(GFX9_TCS_NUM_USER_SGPR
) |
508 S_00B42C_USER_SGPR_MSB(GFX9_TCS_NUM_USER_SGPR
>> 5) |
509 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
511 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
512 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, va
>> 40);
514 shader
->config
.rsrc2
=
515 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR
) |
516 S_00B42C_OC_LDS_EN(1) |
517 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
520 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
521 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
522 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
523 S_00B428_DX10_CLAMP(1) |
524 S_00B428_FLOAT_MODE(shader
->config
.float_mode
) |
525 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt
));
527 if (sscreen
->b
.chip_class
<= VI
) {
528 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
529 shader
->config
.rsrc2
);
533 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
535 struct si_pm4_state
*pm4
;
536 unsigned num_user_sgprs
;
537 unsigned vgpr_comp_cnt
;
541 assert(sscreen
->b
.chip_class
<= VI
);
543 pm4
= si_get_shader_pm4_state(shader
);
547 va
= shader
->bo
->gpu_address
;
548 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
550 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
551 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
552 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
553 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
554 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
555 vgpr_comp_cnt
= shader
->selector
->info
.uses_primid
? 3 : 2;
556 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
558 unreachable("invalid shader selector type");
560 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
562 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
563 shader
->selector
->esgs_itemsize
/ 4);
564 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
565 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
566 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
567 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
568 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
569 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
570 S_00B328_DX10_CLAMP(1) |
571 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
572 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
573 S_00B32C_USER_SGPR(num_user_sgprs
) |
574 S_00B32C_OC_LDS_EN(oc_lds_en
) |
575 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
577 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
578 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
580 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
584 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
587 static uint32_t si_vgt_gs_mode(struct si_shader_selector
*sel
)
589 enum chip_class chip_class
= sel
->screen
->b
.chip_class
;
590 unsigned gs_max_vert_out
= sel
->gs_max_out_vertices
;
593 if (gs_max_vert_out
<= 128) {
594 cut_mode
= V_028A40_GS_CUT_128
;
595 } else if (gs_max_vert_out
<= 256) {
596 cut_mode
= V_028A40_GS_CUT_256
;
597 } else if (gs_max_vert_out
<= 512) {
598 cut_mode
= V_028A40_GS_CUT_512
;
600 assert(gs_max_vert_out
<= 1024);
601 cut_mode
= V_028A40_GS_CUT_1024
;
604 return S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
605 S_028A40_CUT_MODE(cut_mode
)|
606 S_028A40_ES_WRITE_OPTIMIZE(chip_class
<= VI
) |
607 S_028A40_GS_WRITE_OPTIMIZE(1) |
608 S_028A40_ONCHIP(chip_class
>= GFX9
? 1 : 0);
611 struct gfx9_gs_info
{
612 unsigned es_verts_per_subgroup
;
613 unsigned gs_prims_per_subgroup
;
614 unsigned gs_inst_prims_in_subgroup
;
615 unsigned max_prims_per_subgroup
;
619 static void gfx9_get_gs_info(struct si_shader_selector
*es
,
620 struct si_shader_selector
*gs
,
621 struct gfx9_gs_info
*out
)
623 unsigned gs_num_invocations
= MAX2(gs
->gs_num_invocations
, 1);
624 unsigned input_prim
= gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
625 bool uses_adjacency
= input_prim
>= PIPE_PRIM_LINES_ADJACENCY
&&
626 input_prim
<= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
;
628 /* All these are in dwords: */
629 /* We can't allow using the whole LDS, because GS waves compete with
630 * other shader stages for LDS space. */
631 const unsigned max_lds_size
= 8 * 1024;
632 const unsigned esgs_itemsize
= es
->esgs_itemsize
/ 4;
633 unsigned esgs_lds_size
;
635 /* All these are per subgroup: */
636 const unsigned max_out_prims
= 32 * 1024;
637 const unsigned max_es_verts
= 255;
638 const unsigned ideal_gs_prims
= 64;
639 unsigned max_gs_prims
, gs_prims
;
640 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
642 assert(gs_num_invocations
<= 32); /* GL maximum */
644 if (uses_adjacency
|| gs_num_invocations
> 1)
645 max_gs_prims
= 127 / gs_num_invocations
;
649 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
650 * Make sure we don't go over the maximum value.
652 max_gs_prims
= MIN2(max_gs_prims
,
654 (gs
->gs_max_out_vertices
* gs_num_invocations
));
655 assert(max_gs_prims
> 0);
657 /* If the primitive has adjacency, halve the number of vertices
658 * that will be reused in multiple primitives.
660 min_es_verts
= gs
->gs_input_verts_per_prim
/ (uses_adjacency
? 2 : 1);
662 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
663 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
665 /* Compute ESGS LDS size based on the worst case number of ES vertices
666 * needed to create the target number of GS prims per subgroup.
668 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
670 /* If total LDS usage is too big, refactor partitions based on ratio
671 * of ESGS item sizes.
673 if (esgs_lds_size
> max_lds_size
) {
674 /* Our target GS Prims Per Subgroup was too large. Calculate
675 * the maximum number of GS Prims Per Subgroup that will fit
676 * into LDS, capped by the maximum that the hardware can support.
678 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
680 assert(gs_prims
> 0);
681 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
684 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
685 assert(esgs_lds_size
<= max_lds_size
);
688 /* Now calculate remaining ESGS information. */
690 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
692 es_verts
= max_es_verts
;
694 /* Vertices for adjacency primitives are not always reused, so restore
695 * it for ES_VERTS_PER_SUBGRP.
697 min_es_verts
= gs
->gs_input_verts_per_prim
;
699 /* For normal primitives, the VGT only checks if they are past the ES
700 * verts per subgroup after allocating a full GS primitive and if they
701 * are, kick off a new subgroup. But if those additional ES verts are
702 * unique (e.g. not reused) we need to make sure there is enough LDS
703 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
705 es_verts
-= min_es_verts
- 1;
707 out
->es_verts_per_subgroup
= es_verts
;
708 out
->gs_prims_per_subgroup
= gs_prims
;
709 out
->gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
710 out
->max_prims_per_subgroup
= out
->gs_inst_prims_in_subgroup
*
711 gs
->gs_max_out_vertices
;
712 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
714 assert(out
->max_prims_per_subgroup
<= max_out_prims
);
717 static void si_shader_gs(struct si_screen
*sscreen
, struct si_shader
*shader
)
719 struct si_shader_selector
*sel
= shader
->selector
;
720 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
721 unsigned gs_num_invocations
= sel
->gs_num_invocations
;
722 struct si_pm4_state
*pm4
;
724 unsigned max_stream
= sel
->max_gs_stream
;
727 pm4
= si_get_shader_pm4_state(shader
);
731 offset
= num_components
[0] * sel
->gs_max_out_vertices
;
732 si_pm4_set_reg(pm4
, R_028A60_VGT_GSVS_RING_OFFSET_1
, offset
);
734 offset
+= num_components
[1] * sel
->gs_max_out_vertices
;
735 si_pm4_set_reg(pm4
, R_028A64_VGT_GSVS_RING_OFFSET_2
, offset
);
737 offset
+= num_components
[2] * sel
->gs_max_out_vertices
;
738 si_pm4_set_reg(pm4
, R_028A68_VGT_GSVS_RING_OFFSET_3
, offset
);
740 offset
+= num_components
[3] * sel
->gs_max_out_vertices
;
741 si_pm4_set_reg(pm4
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
743 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
744 assert(offset
< (1 << 15));
746 si_pm4_set_reg(pm4
, R_028B38_VGT_GS_MAX_VERT_OUT
, sel
->gs_max_out_vertices
);
748 si_pm4_set_reg(pm4
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, num_components
[0]);
749 si_pm4_set_reg(pm4
, R_028B60_VGT_GS_VERT_ITEMSIZE_1
, (max_stream
>= 1) ? num_components
[1] : 0);
750 si_pm4_set_reg(pm4
, R_028B64_VGT_GS_VERT_ITEMSIZE_2
, (max_stream
>= 2) ? num_components
[2] : 0);
751 si_pm4_set_reg(pm4
, R_028B68_VGT_GS_VERT_ITEMSIZE_3
, (max_stream
>= 3) ? num_components
[3] : 0);
753 si_pm4_set_reg(pm4
, R_028B90_VGT_GS_INSTANCE_CNT
,
754 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
755 S_028B90_ENABLE(gs_num_invocations
> 0));
757 va
= shader
->bo
->gpu_address
;
758 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
760 if (sscreen
->b
.chip_class
>= GFX9
) {
761 unsigned input_prim
= sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
762 unsigned es_type
= shader
->key
.part
.gs
.es
->type
;
763 unsigned es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
764 struct gfx9_gs_info gs_info
;
766 if (es_type
== PIPE_SHADER_VERTEX
)
767 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
768 es_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
769 else if (es_type
== PIPE_SHADER_TESS_EVAL
)
770 es_vgpr_comp_cnt
= shader
->key
.part
.gs
.es
->info
.uses_primid
? 3 : 2;
772 unreachable("invalid shader selector type");
774 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
775 * VGPR[0:4] are always loaded.
777 if (sel
->info
.uses_invocationid
)
778 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
779 else if (sel
->info
.uses_primid
)
780 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
781 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
782 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
784 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
786 gfx9_get_gs_info(shader
->key
.part
.gs
.es
, sel
, &gs_info
);
788 si_pm4_set_reg(pm4
, R_00B210_SPI_SHADER_PGM_LO_ES
, va
>> 8);
789 si_pm4_set_reg(pm4
, R_00B214_SPI_SHADER_PGM_HI_ES
, va
>> 40);
791 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
792 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
793 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
794 S_00B228_DX10_CLAMP(1) |
795 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
796 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
));
797 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
798 S_00B22C_USER_SGPR(GFX9_GS_NUM_USER_SGPR
) |
799 S_00B22C_USER_SGPR_MSB(GFX9_GS_NUM_USER_SGPR
>> 5) |
800 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
801 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
802 S_00B22C_LDS_SIZE(gs_info
.lds_size
) |
803 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
805 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
806 S_028A44_ES_VERTS_PER_SUBGRP(gs_info
.es_verts_per_subgroup
) |
807 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info
.gs_prims_per_subgroup
) |
808 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info
.gs_inst_prims_in_subgroup
));
809 si_pm4_set_reg(pm4
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
810 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info
.max_prims_per_subgroup
));
811 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
812 shader
->key
.part
.gs
.es
->esgs_itemsize
/ 4);
814 if (es_type
== PIPE_SHADER_TESS_EVAL
)
815 si_set_tesseval_regs(sscreen
, shader
->key
.part
.gs
.es
, pm4
);
817 polaris_set_vgt_vertex_reuse(sscreen
, shader
->key
.part
.gs
.es
,
820 if (shader
->config
.scratch_bytes_per_wave
) {
821 fprintf(stderr
, "GS: scratch buffer unsupported");
825 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
826 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, va
>> 40);
828 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
829 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
830 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
831 S_00B228_DX10_CLAMP(1) |
832 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
833 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
834 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR
) |
835 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
840 * Compute the state for \p shader, which will run as a vertex shader on the
843 * If \p gs is non-NULL, it points to the geometry shader for which this shader
844 * is the copy shader.
846 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
847 struct si_shader_selector
*gs
)
849 struct si_pm4_state
*pm4
;
850 unsigned num_user_sgprs
;
851 unsigned nparams
, vgpr_comp_cnt
;
854 unsigned window_space
=
855 shader
->selector
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
856 bool enable_prim_id
= shader
->key
.mono
.vs_export_prim_id
;
858 pm4
= si_get_shader_pm4_state(shader
);
862 /* We always write VGT_GS_MODE in the VS state, because every switch
863 * between different shader pipelines involving a different GS or no
864 * GS at all involves a switch of the VS (different GS use different
865 * copy shaders). On the other hand, when the API switches from a GS to
866 * no GS and then back to the same GS used originally, the GS state is
872 /* PrimID needs GS scenario A.
873 * GFX9 also needs it when ViewportIndex is enabled.
875 if (enable_prim_id
||
876 (sscreen
->b
.chip_class
>= GFX9
&&
877 shader
->selector
->info
.writes_viewport_index
))
878 mode
= V_028A40_GS_SCENARIO_A
;
880 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, S_028A40_MODE(mode
));
881 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, enable_prim_id
);
883 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, si_vgt_gs_mode(gs
));
884 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
887 va
= shader
->bo
->gpu_address
;
888 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
891 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
892 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
893 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
894 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
895 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
896 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
898 vgpr_comp_cnt
= enable_prim_id
? 2 : (shader
->info
.uses_instanceid
? 1 : 0);
899 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
900 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
901 vgpr_comp_cnt
= shader
->selector
->info
.uses_primid
? 3 : 2;
902 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
904 unreachable("invalid shader selector type");
906 /* VS is required to export at least one param. */
907 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
908 si_pm4_set_reg(pm4
, R_0286C4_SPI_VS_OUT_CONFIG
,
909 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
911 si_pm4_set_reg(pm4
, R_02870C_SPI_SHADER_POS_FORMAT
,
912 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
913 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
914 V_02870C_SPI_SHADER_4COMP
:
915 V_02870C_SPI_SHADER_NONE
) |
916 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
917 V_02870C_SPI_SHADER_4COMP
:
918 V_02870C_SPI_SHADER_NONE
) |
919 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
920 V_02870C_SPI_SHADER_4COMP
:
921 V_02870C_SPI_SHADER_NONE
));
923 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
925 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
926 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, va
>> 40);
927 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
928 S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
929 S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
930 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
931 S_00B128_DX10_CLAMP(1) |
932 S_00B128_FLOAT_MODE(shader
->config
.float_mode
));
933 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
934 S_00B12C_USER_SGPR(num_user_sgprs
) |
935 S_00B12C_OC_LDS_EN(oc_lds_en
) |
936 S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
937 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
938 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
939 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
940 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
) |
941 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
943 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
944 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
946 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
947 S_028818_VTX_W0_FMT(1) |
948 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
949 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
950 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
952 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
953 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
955 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
958 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
960 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
961 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
962 !!(info
->colors_read
& 0xf0);
963 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
964 (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
966 assert(num_interp
<= 32);
967 return MIN2(num_interp
, 32);
970 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
972 unsigned value
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
973 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
975 /* If the i-th target format is set, all previous target formats must
976 * be non-zero to avoid hangs.
978 for (i
= 0; i
< num_targets
; i
++)
979 if (!(value
& (0xf << (i
* 4))))
980 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
985 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format
)
987 unsigned i
, cb_shader_mask
= 0;
989 for (i
= 0; i
< 8; i
++) {
990 switch ((spi_shader_col_format
>> (i
* 4)) & 0xf) {
991 case V_028714_SPI_SHADER_ZERO
:
993 case V_028714_SPI_SHADER_32_R
:
994 cb_shader_mask
|= 0x1 << (i
* 4);
996 case V_028714_SPI_SHADER_32_GR
:
997 cb_shader_mask
|= 0x3 << (i
* 4);
999 case V_028714_SPI_SHADER_32_AR
:
1000 cb_shader_mask
|= 0x9 << (i
* 4);
1002 case V_028714_SPI_SHADER_FP16_ABGR
:
1003 case V_028714_SPI_SHADER_UNORM16_ABGR
:
1004 case V_028714_SPI_SHADER_SNORM16_ABGR
:
1005 case V_028714_SPI_SHADER_UINT16_ABGR
:
1006 case V_028714_SPI_SHADER_SINT16_ABGR
:
1007 case V_028714_SPI_SHADER_32_ABGR
:
1008 cb_shader_mask
|= 0xf << (i
* 4);
1014 return cb_shader_mask
;
1017 static void si_shader_ps(struct si_shader
*shader
)
1019 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1020 struct si_pm4_state
*pm4
;
1021 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
1022 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
1024 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
1026 /* we need to enable at least one of them, otherwise we hang the GPU */
1027 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1028 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1029 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1030 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
1031 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
1032 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1033 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
1034 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
1035 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1036 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
1037 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1038 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1039 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1040 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
1042 /* Validate interpolation optimization flags (read as implications). */
1043 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1044 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1045 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1046 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1047 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1048 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1049 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
1050 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
1051 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1052 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
1053 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
1054 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1055 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
1056 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1057 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1058 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
1059 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1060 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1062 /* Validate cases when the optimizations are off (read as implications). */
1063 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1064 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1065 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
1066 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1067 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1068 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
1070 pm4
= si_get_shader_pm4_state(shader
);
1074 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1076 * 0 -> Position = pixel center
1077 * 1 -> Position = pixel centroid
1078 * 2 -> Position = at sample position
1080 * From GLSL 4.5 specification, section 7.1:
1081 * "The variable gl_FragCoord is available as an input variable from
1082 * within fragment shaders and it holds the window relative coordinates
1083 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1084 * value can be for any location within the pixel, or one of the
1085 * fragment samples. The use of centroid does not further restrict
1086 * this value to be inside the current primitive."
1088 * Meaning that centroid has no effect and we can return anything within
1089 * the pixel. Thus, return the value at sample position, because that's
1090 * the most accurate one shaders can get.
1092 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1094 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
1095 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
1096 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
1098 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
1099 cb_shader_mask
= si_get_cb_shader_mask(spi_shader_col_format
);
1101 /* Ensure that some export memory is always allocated, for two reasons:
1103 * 1) Correctness: The hardware ignores the EXEC mask if no export
1104 * memory is allocated, so KILL and alpha test do not work correctly
1106 * 2) Performance: Every shader needs at least a NULL export, even when
1107 * it writes no color/depth output. The NULL export instruction
1108 * stalls without this setting.
1110 * Don't add this to CB_SHADER_MASK.
1112 if (!spi_shader_col_format
&&
1113 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
1114 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
1116 si_pm4_set_reg(pm4
, R_0286CC_SPI_PS_INPUT_ENA
, input_ena
);
1117 si_pm4_set_reg(pm4
, R_0286D0_SPI_PS_INPUT_ADDR
,
1118 shader
->config
.spi_ps_input_addr
);
1120 /* Set interpolation controls. */
1121 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
));
1123 /* Set registers. */
1124 si_pm4_set_reg(pm4
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
1125 si_pm4_set_reg(pm4
, R_0286D8_SPI_PS_IN_CONTROL
, spi_ps_in_control
);
1127 si_pm4_set_reg(pm4
, R_028710_SPI_SHADER_Z_FORMAT
,
1128 si_get_spi_shader_z_format(info
->writes_z
,
1129 info
->writes_stencil
,
1130 info
->writes_samplemask
));
1132 si_pm4_set_reg(pm4
, R_028714_SPI_SHADER_COL_FORMAT
, spi_shader_col_format
);
1133 si_pm4_set_reg(pm4
, R_02823C_CB_SHADER_MASK
, cb_shader_mask
);
1135 va
= shader
->bo
->gpu_address
;
1136 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1137 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
1138 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, va
>> 40);
1140 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
,
1141 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1142 S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
1143 S_00B028_DX10_CLAMP(1) |
1144 S_00B028_FLOAT_MODE(shader
->config
.float_mode
));
1145 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
1146 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
1147 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
1148 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1151 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
1152 struct si_shader
*shader
)
1154 switch (shader
->selector
->type
) {
1155 case PIPE_SHADER_VERTEX
:
1156 if (shader
->key
.as_ls
)
1157 si_shader_ls(sscreen
, shader
);
1158 else if (shader
->key
.as_es
)
1159 si_shader_es(sscreen
, shader
);
1161 si_shader_vs(sscreen
, shader
, NULL
);
1163 case PIPE_SHADER_TESS_CTRL
:
1164 si_shader_hs(sscreen
, shader
);
1166 case PIPE_SHADER_TESS_EVAL
:
1167 if (shader
->key
.as_es
)
1168 si_shader_es(sscreen
, shader
);
1170 si_shader_vs(sscreen
, shader
, NULL
);
1172 case PIPE_SHADER_GEOMETRY
:
1173 si_shader_gs(sscreen
, shader
);
1175 case PIPE_SHADER_FRAGMENT
:
1176 si_shader_ps(shader
);
1183 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
1185 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1186 if (sctx
->queued
.named
.dsa
)
1187 return sctx
->queued
.named
.dsa
->alpha_func
;
1189 return PIPE_FUNC_ALWAYS
;
1192 static void si_shader_selector_key_vs(struct si_context
*sctx
,
1193 struct si_shader_selector
*vs
,
1194 struct si_shader_key
*key
,
1195 struct si_vs_prolog_bits
*prolog_key
)
1197 if (!sctx
->vertex_elements
)
1200 unsigned count
= MIN2(vs
->info
.num_inputs
,
1201 sctx
->vertex_elements
->count
);
1202 for (unsigned i
= 0; i
< count
; ++i
) {
1203 prolog_key
->instance_divisors
[i
] =
1204 sctx
->vertex_elements
->elements
[i
].instance_divisor
;
1207 memcpy(key
->mono
.vs_fix_fetch
, sctx
->vertex_elements
->fix_fetch
, count
);
1210 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
,
1211 struct si_shader_selector
*vs
,
1212 struct si_shader_key
*key
)
1214 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1216 key
->opt
.hw_vs
.clip_disable
=
1217 sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
1218 (vs
->info
.clipdist_writemask
||
1219 vs
->info
.writes_clipvertex
) &&
1220 !vs
->info
.culldist_writemask
;
1222 /* Find out if PS is disabled. */
1223 bool ps_disabled
= true;
1225 bool ps_modifies_zs
= ps
->info
.uses_kill
||
1226 ps
->info
.writes_z
||
1227 ps
->info
.writes_stencil
||
1228 ps
->info
.writes_samplemask
||
1229 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
1231 unsigned ps_colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
&
1232 sctx
->queued
.named
.blend
->cb_target_mask
;
1233 if (!ps
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
])
1234 ps_colormask
&= ps
->colors_written_4bit
;
1236 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
1239 !ps
->info
.writes_memory
);
1242 /* Find out which VS outputs aren't used by the PS. */
1243 uint64_t outputs_written
= vs
->outputs_written
;
1244 uint32_t outputs_written2
= vs
->outputs_written2
;
1245 uint64_t inputs_read
= 0;
1246 uint32_t inputs_read2
= 0;
1248 outputs_written
&= ~0x3; /* ignore POSITION, PSIZE */
1251 inputs_read
= ps
->inputs_read
;
1252 inputs_read2
= ps
->inputs_read2
;
1255 uint64_t linked
= outputs_written
& inputs_read
;
1256 uint32_t linked2
= outputs_written2
& inputs_read2
;
1258 key
->opt
.hw_vs
.kill_outputs
= ~linked
& outputs_written
;
1259 key
->opt
.hw_vs
.kill_outputs2
= ~linked2
& outputs_written2
;
1262 /* Compute the key for the hw shader variant */
1263 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
1264 struct si_shader_selector
*sel
,
1265 struct si_shader_key
*key
)
1267 struct si_context
*sctx
= (struct si_context
*)ctx
;
1269 memset(key
, 0, sizeof(*key
));
1271 switch (sel
->type
) {
1272 case PIPE_SHADER_VERTEX
:
1273 si_shader_selector_key_vs(sctx
, sel
, key
, &key
->part
.vs
.prolog
);
1275 if (sctx
->tes_shader
.cso
)
1277 else if (sctx
->gs_shader
.cso
)
1280 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1282 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1283 key
->mono
.vs_export_prim_id
= 1;
1286 case PIPE_SHADER_TESS_CTRL
:
1287 if (sctx
->b
.chip_class
>= GFX9
) {
1288 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1289 key
, &key
->part
.tcs
.ls_prolog
);
1290 key
->part
.tcs
.ls
= sctx
->vs_shader
.cso
;
1293 key
->part
.tcs
.epilog
.prim_mode
=
1294 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1295 key
->part
.tcs
.epilog
.tes_reads_tess_factors
=
1296 sctx
->tes_shader
.cso
->info
.reads_tess_factors
;
1298 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
1299 key
->mono
.ff_tcs_inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
1301 case PIPE_SHADER_TESS_EVAL
:
1302 if (sctx
->gs_shader
.cso
)
1305 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1307 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1308 key
->mono
.vs_export_prim_id
= 1;
1311 case PIPE_SHADER_GEOMETRY
:
1312 if (sctx
->b
.chip_class
>= GFX9
) {
1313 if (sctx
->tes_shader
.cso
) {
1314 key
->part
.gs
.es
= sctx
->tes_shader
.cso
;
1316 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1317 key
, &key
->part
.gs
.vs_prolog
);
1318 key
->part
.gs
.es
= sctx
->vs_shader
.cso
;
1321 /* Merged ES-GS can have unbalanced wave usage.
1323 * ES threads are per-vertex, while GS threads are
1324 * per-primitive. So without any amplification, there
1325 * are fewer GS threads than ES threads, which can result
1326 * in empty (no-op) GS waves. With too much amplification,
1327 * there are more GS threads than ES threads, which
1328 * can result in empty (no-op) ES waves.
1330 * Non-monolithic shaders are implemented by setting EXEC
1331 * at the beginning of shader parts, and don't jump to
1332 * the end if EXEC is 0.
1334 * Monolithic shaders use conditional blocks, so they can
1335 * jump and skip empty waves of ES or GS. So set this to
1336 * always use optimized variants, which are monolithic.
1338 key
->opt
.prefer_mono
= 1;
1340 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
1342 case PIPE_SHADER_FRAGMENT
: {
1343 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1344 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1346 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
1347 sel
->info
.colors_written
== 0x1)
1348 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
1351 /* Select the shader color format based on whether
1352 * blending or alpha are needed.
1354 key
->part
.ps
.epilog
.spi_shader_col_format
=
1355 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1356 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
1357 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1358 sctx
->framebuffer
.spi_shader_col_format_blend
) |
1359 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1360 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
1361 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1362 sctx
->framebuffer
.spi_shader_col_format
);
1364 /* The output for dual source blending should have
1365 * the same format as the first output.
1367 if (blend
->dual_src_blend
)
1368 key
->part
.ps
.epilog
.spi_shader_col_format
|=
1369 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
1371 key
->part
.ps
.epilog
.spi_shader_col_format
= sctx
->framebuffer
.spi_shader_col_format
;
1373 /* If alpha-to-coverage is enabled, we have to export alpha
1374 * even if there is no color buffer.
1376 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) &&
1377 blend
&& blend
->alpha_to_coverage
)
1378 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
1380 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1381 * to the range supported by the type if a channel has less
1382 * than 16 bits and the export format is 16_ABGR.
1384 if (sctx
->b
.chip_class
<= CIK
&& sctx
->b
.family
!= CHIP_HAWAII
) {
1385 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
1386 key
->part
.ps
.epilog
.color_is_int10
= sctx
->framebuffer
.color_is_int10
;
1389 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1390 if (!key
->part
.ps
.epilog
.last_cbuf
) {
1391 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
1392 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
1393 key
->part
.ps
.epilog
.color_is_int10
&= sel
->info
.colors_written
;
1397 bool is_poly
= (sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES
&&
1398 sctx
->current_rast_prim
<= PIPE_PRIM_POLYGON
) ||
1399 sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES_ADJACENCY
;
1400 bool is_line
= !is_poly
&& sctx
->current_rast_prim
!= PIPE_PRIM_POINTS
;
1402 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
1403 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
1405 if (sctx
->queued
.named
.blend
) {
1406 key
->part
.ps
.epilog
.alpha_to_one
= sctx
->queued
.named
.blend
->alpha_to_one
&&
1407 rs
->multisample_enable
;
1410 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
1411 key
->part
.ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
1412 (is_line
&& rs
->line_smooth
)) &&
1413 sctx
->framebuffer
.nr_samples
<= 1;
1414 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
1416 if (rs
->force_persample_interp
&&
1417 rs
->multisample_enable
&&
1418 sctx
->framebuffer
.nr_samples
> 1 &&
1419 sctx
->ps_iter_samples
> 1) {
1420 key
->part
.ps
.prolog
.force_persp_sample_interp
=
1421 sel
->info
.uses_persp_center
||
1422 sel
->info
.uses_persp_centroid
;
1424 key
->part
.ps
.prolog
.force_linear_sample_interp
=
1425 sel
->info
.uses_linear_center
||
1426 sel
->info
.uses_linear_centroid
;
1427 } else if (rs
->multisample_enable
&&
1428 sctx
->framebuffer
.nr_samples
> 1) {
1429 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
1430 sel
->info
.uses_persp_center
&&
1431 sel
->info
.uses_persp_centroid
;
1432 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
1433 sel
->info
.uses_linear_center
&&
1434 sel
->info
.uses_linear_centroid
;
1436 /* Make sure SPI doesn't compute more than 1 pair
1437 * of (i,j), which is the optimization here. */
1438 key
->part
.ps
.prolog
.force_persp_center_interp
=
1439 sel
->info
.uses_persp_center
+
1440 sel
->info
.uses_persp_centroid
+
1441 sel
->info
.uses_persp_sample
> 1;
1443 key
->part
.ps
.prolog
.force_linear_center_interp
=
1444 sel
->info
.uses_linear_center
+
1445 sel
->info
.uses_linear_centroid
+
1446 sel
->info
.uses_linear_sample
> 1;
1450 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
1458 static void si_build_shader_variant(void *job
, int thread_index
)
1460 struct si_shader
*shader
= (struct si_shader
*)job
;
1461 struct si_shader_selector
*sel
= shader
->selector
;
1462 struct si_screen
*sscreen
= sel
->screen
;
1463 LLVMTargetMachineRef tm
;
1464 struct pipe_debug_callback
*debug
= &shader
->compiler_ctx_state
.debug
;
1467 if (thread_index
>= 0) {
1468 assert(thread_index
< ARRAY_SIZE(sscreen
->tm
));
1469 tm
= sscreen
->tm
[thread_index
];
1473 tm
= shader
->compiler_ctx_state
.tm
;
1476 r
= si_shader_create(sscreen
, tm
, shader
, debug
);
1478 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1480 shader
->compilation_failed
= true;
1484 if (shader
->compiler_ctx_state
.is_debug_context
) {
1485 FILE *f
= open_memstream(&shader
->shader_log
,
1486 &shader
->shader_log_size
);
1488 si_shader_dump(sscreen
, shader
, NULL
, sel
->type
, f
, false);
1493 si_shader_init_pm4_state(sscreen
, shader
);
1496 static const struct si_shader_key zeroed
;
1498 static bool si_check_missing_main_part(struct si_screen
*sscreen
,
1499 struct si_shader_selector
*sel
,
1500 struct si_compiler_ctx_state
*compiler_state
,
1501 struct si_shader_key
*key
)
1503 struct si_shader
**mainp
= si_get_main_shader_part(sel
, key
);
1506 struct si_shader
*main_part
= CALLOC_STRUCT(si_shader
);
1511 main_part
->selector
= sel
;
1512 main_part
->key
.as_es
= key
->as_es
;
1513 main_part
->key
.as_ls
= key
->as_ls
;
1515 if (si_compile_tgsi_shader(sscreen
, compiler_state
->tm
,
1517 &compiler_state
->debug
) != 0) {
1526 static void si_destroy_shader_selector(struct si_context
*sctx
,
1527 struct si_shader_selector
*sel
);
1529 static void si_shader_selector_reference(struct si_context
*sctx
,
1530 struct si_shader_selector
**dst
,
1531 struct si_shader_selector
*src
)
1533 if (pipe_reference(&(*dst
)->reference
, &src
->reference
))
1534 si_destroy_shader_selector(sctx
, *dst
);
1539 /* Select the hw shader variant depending on the current state. */
1540 static int si_shader_select_with_key(struct si_screen
*sscreen
,
1541 struct si_shader_ctx_state
*state
,
1542 struct si_compiler_ctx_state
*compiler_state
,
1543 struct si_shader_key
*key
,
1546 struct si_shader_selector
*sel
= state
->cso
;
1547 struct si_shader_selector
*previous_stage_sel
= NULL
;
1548 struct si_shader
*current
= state
->current
;
1549 struct si_shader
*iter
, *shader
= NULL
;
1551 if (unlikely(sscreen
->b
.debug_flags
& DBG_NO_OPT_VARIANT
)) {
1552 memset(&key
->opt
, 0, sizeof(key
->opt
));
1556 /* Check if we don't need to change anything.
1557 * This path is also used for most shaders that don't need multiple
1558 * variants, it will cost just a computation of the key and this
1560 if (likely(current
&&
1561 memcmp(¤t
->key
, key
, sizeof(*key
)) == 0 &&
1562 (!current
->is_optimized
||
1563 util_queue_fence_is_signalled(¤t
->optimized_ready
))))
1564 return current
->compilation_failed
? -1 : 0;
1566 /* This must be done before the mutex is locked, because async GS
1567 * compilation calls this function too, and therefore must enter
1570 * Only wait if we are in a draw call. Don't wait if we are
1571 * in a compiler thread.
1573 if (thread_index
< 0)
1574 util_queue_fence_wait(&sel
->ready
);
1576 mtx_lock(&sel
->mutex
);
1578 /* Find the shader variant. */
1579 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
1580 /* Don't check the "current" shader. We checked it above. */
1581 if (current
!= iter
&&
1582 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
1583 /* If it's an optimized shader and its compilation has
1584 * been started but isn't done, use the unoptimized
1585 * shader so as not to cause a stall due to compilation.
1587 if (iter
->is_optimized
&&
1588 !util_queue_fence_is_signalled(&iter
->optimized_ready
)) {
1589 memset(&key
->opt
, 0, sizeof(key
->opt
));
1590 mtx_unlock(&sel
->mutex
);
1594 if (iter
->compilation_failed
) {
1595 mtx_unlock(&sel
->mutex
);
1596 return -1; /* skip the draw call */
1599 state
->current
= iter
;
1600 mtx_unlock(&sel
->mutex
);
1605 /* Build a new shader. */
1606 shader
= CALLOC_STRUCT(si_shader
);
1608 mtx_unlock(&sel
->mutex
);
1611 shader
->selector
= sel
;
1613 shader
->compiler_ctx_state
= *compiler_state
;
1615 /* If this is a merged shader, get the first shader's selector. */
1616 if (sscreen
->b
.chip_class
>= GFX9
) {
1617 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
1618 previous_stage_sel
= key
->part
.tcs
.ls
;
1619 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
1620 previous_stage_sel
= key
->part
.gs
.es
;
1623 /* Compile the main shader part if it doesn't exist. This can happen
1624 * if the initial guess was wrong. */
1625 bool is_pure_monolithic
=
1626 sscreen
->use_monolithic_shaders
||
1627 memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
1629 if (!is_pure_monolithic
) {
1632 /* Make sure the main shader part is present. This is needed
1633 * for shaders that can be compiled as VS, LS, or ES, and only
1634 * one of them is compiled at creation.
1636 * For merged shaders, check that the starting shader's main
1639 if (previous_stage_sel
) {
1640 struct si_shader_key shader1_key
= zeroed
;
1642 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
1643 shader1_key
.as_ls
= 1;
1644 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
1645 shader1_key
.as_es
= 1;
1649 ok
= si_check_missing_main_part(sscreen
,
1651 compiler_state
, &shader1_key
);
1653 ok
= si_check_missing_main_part(sscreen
, sel
,
1654 compiler_state
, key
);
1658 mtx_unlock(&sel
->mutex
);
1659 return -ENOMEM
; /* skip the draw call */
1663 /* Keep the reference to the 1st shader of merged shaders, so that
1664 * Gallium can't destroy it before we destroy the 2nd shader.
1666 * Set sctx = NULL, because it's unused if we're not releasing
1667 * the shader, and we don't have any sctx here.
1669 si_shader_selector_reference(NULL
, &shader
->previous_stage_sel
,
1670 previous_stage_sel
);
1672 /* Monolithic-only shaders don't make a distinction between optimized
1673 * and unoptimized. */
1674 shader
->is_monolithic
=
1675 is_pure_monolithic
||
1676 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1678 shader
->is_optimized
=
1679 !is_pure_monolithic
&&
1680 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1681 if (shader
->is_optimized
)
1682 util_queue_fence_init(&shader
->optimized_ready
);
1684 if (!sel
->last_variant
) {
1685 sel
->first_variant
= shader
;
1686 sel
->last_variant
= shader
;
1688 sel
->last_variant
->next_variant
= shader
;
1689 sel
->last_variant
= shader
;
1692 /* If it's an optimized shader, compile it asynchronously. */
1693 if (shader
->is_optimized
&&
1694 !is_pure_monolithic
&&
1696 /* Compile it asynchronously. */
1697 util_queue_add_job(&sscreen
->shader_compiler_queue
,
1698 shader
, &shader
->optimized_ready
,
1699 si_build_shader_variant
, NULL
);
1701 /* Use the default (unoptimized) shader for now. */
1702 memset(&key
->opt
, 0, sizeof(key
->opt
));
1703 mtx_unlock(&sel
->mutex
);
1707 assert(!shader
->is_optimized
);
1708 si_build_shader_variant(shader
, thread_index
);
1710 if (!shader
->compilation_failed
)
1711 state
->current
= shader
;
1713 mtx_unlock(&sel
->mutex
);
1714 return shader
->compilation_failed
? -1 : 0;
1717 static int si_shader_select(struct pipe_context
*ctx
,
1718 struct si_shader_ctx_state
*state
,
1719 struct si_compiler_ctx_state
*compiler_state
)
1721 struct si_context
*sctx
= (struct si_context
*)ctx
;
1722 struct si_shader_key key
;
1724 si_shader_selector_key(ctx
, state
->cso
, &key
);
1725 return si_shader_select_with_key(sctx
->screen
, state
, compiler_state
,
1729 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
1730 struct si_shader_key
*key
)
1732 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
1734 switch (info
->processor
) {
1735 case PIPE_SHADER_VERTEX
:
1736 switch (next_shader
) {
1737 case PIPE_SHADER_GEOMETRY
:
1740 case PIPE_SHADER_TESS_CTRL
:
1741 case PIPE_SHADER_TESS_EVAL
:
1745 /* If POSITION isn't written, it can't be a HW VS.
1746 * Assume that it's a HW LS. (the next shader is TCS)
1747 * This heuristic is needed for separate shader objects.
1749 if (!info
->writes_position
)
1754 case PIPE_SHADER_TESS_EVAL
:
1755 if (next_shader
== PIPE_SHADER_GEOMETRY
||
1756 !info
->writes_position
)
1763 * Compile the main shader part or the monolithic shader as part of
1764 * si_shader_selector initialization. Since it can be done asynchronously,
1765 * there is no way to report compile failures to applications.
1767 void si_init_shader_selector_async(void *job
, int thread_index
)
1769 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
1770 struct si_screen
*sscreen
= sel
->screen
;
1771 LLVMTargetMachineRef tm
;
1772 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
1775 if (thread_index
>= 0) {
1776 assert(thread_index
< ARRAY_SIZE(sscreen
->tm
));
1777 tm
= sscreen
->tm
[thread_index
];
1781 tm
= sel
->compiler_ctx_state
.tm
;
1784 /* Compile the main shader part for use with a prolog and/or epilog.
1785 * If this fails, the driver will try to compile a monolithic shader
1788 if (!sscreen
->use_monolithic_shaders
) {
1789 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
1793 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
1797 shader
->selector
= sel
;
1798 si_parse_next_shader_property(&sel
->info
, &shader
->key
);
1800 tgsi_binary
= si_get_tgsi_binary(sel
);
1802 /* Try to load the shader from the shader cache. */
1803 mtx_lock(&sscreen
->shader_cache_mutex
);
1806 si_shader_cache_load_shader(sscreen
, tgsi_binary
, shader
)) {
1807 mtx_unlock(&sscreen
->shader_cache_mutex
);
1809 mtx_unlock(&sscreen
->shader_cache_mutex
);
1811 /* Compile the shader if it hasn't been loaded from the cache. */
1812 if (si_compile_tgsi_shader(sscreen
, tm
, shader
, false,
1816 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
1821 mtx_lock(&sscreen
->shader_cache_mutex
);
1822 if (!si_shader_cache_insert_shader(sscreen
, tgsi_binary
, shader
, true))
1824 mtx_unlock(&sscreen
->shader_cache_mutex
);
1828 *si_get_main_shader_part(sel
, &shader
->key
) = shader
;
1830 /* Unset "outputs_written" flags for outputs converted to
1831 * DEFAULT_VAL, so that later inter-shader optimizations don't
1832 * try to eliminate outputs that don't exist in the final
1835 * This is only done if non-monolithic shaders are enabled.
1837 if ((sel
->type
== PIPE_SHADER_VERTEX
||
1838 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
1839 !shader
->key
.as_ls
&&
1840 !shader
->key
.as_es
) {
1843 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
1844 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
1846 if (offset
<= AC_EXP_PARAM_OFFSET_31
)
1849 unsigned name
= sel
->info
.output_semantic_name
[i
];
1850 unsigned index
= sel
->info
.output_semantic_index
[i
];
1854 case TGSI_SEMANTIC_GENERIC
:
1855 /* don't process indices the function can't handle */
1859 case TGSI_SEMANTIC_CLIPDIST
:
1860 id
= si_shader_io_get_unique_index(name
, index
);
1861 sel
->outputs_written
&= ~(1ull << id
);
1863 case TGSI_SEMANTIC_POSITION
: /* ignore these */
1864 case TGSI_SEMANTIC_PSIZE
:
1865 case TGSI_SEMANTIC_CLIPVERTEX
:
1866 case TGSI_SEMANTIC_EDGEFLAG
:
1869 id
= si_shader_io_get_unique_index2(name
, index
);
1870 sel
->outputs_written2
&= ~(1u << id
);
1876 /* Pre-compilation. */
1877 if (sscreen
->b
.debug_flags
& DBG_PRECOMPILE
) {
1878 struct si_shader_ctx_state state
= {sel
};
1879 struct si_shader_key key
;
1881 memset(&key
, 0, sizeof(key
));
1882 si_parse_next_shader_property(&sel
->info
, &key
);
1884 /* Set reasonable defaults, so that the shader key doesn't
1885 * cause any code to be eliminated.
1887 switch (sel
->type
) {
1888 case PIPE_SHADER_TESS_CTRL
:
1889 key
.part
.tcs
.epilog
.prim_mode
= PIPE_PRIM_TRIANGLES
;
1891 case PIPE_SHADER_FRAGMENT
:
1892 key
.part
.ps
.prolog
.bc_optimize_for_persp
=
1893 sel
->info
.uses_persp_center
&&
1894 sel
->info
.uses_persp_centroid
;
1895 key
.part
.ps
.prolog
.bc_optimize_for_linear
=
1896 sel
->info
.uses_linear_center
&&
1897 sel
->info
.uses_linear_centroid
;
1898 key
.part
.ps
.epilog
.alpha_func
= PIPE_FUNC_ALWAYS
;
1899 for (i
= 0; i
< 8; i
++)
1900 if (sel
->info
.colors_written
& (1 << i
))
1901 key
.part
.ps
.epilog
.spi_shader_col_format
|=
1902 V_028710_SPI_SHADER_FP16_ABGR
<< (i
* 4);
1906 if (si_shader_select_with_key(sscreen
, &state
,
1907 &sel
->compiler_ctx_state
, &key
,
1909 fprintf(stderr
, "radeonsi: can't create a monolithic shader\n");
1912 /* The GS copy shader is always pre-compiled. */
1913 if (sel
->type
== PIPE_SHADER_GEOMETRY
) {
1914 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, tm
, sel
, debug
);
1915 if (!sel
->gs_copy_shader
) {
1916 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
1920 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
1924 static void *si_create_shader_selector(struct pipe_context
*ctx
,
1925 const struct pipe_shader_state
*state
)
1927 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
1928 struct si_context
*sctx
= (struct si_context
*)ctx
;
1929 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
1935 pipe_reference_init(&sel
->reference
, 1);
1936 sel
->screen
= sscreen
;
1937 sel
->compiler_ctx_state
.tm
= sctx
->tm
;
1938 sel
->compiler_ctx_state
.debug
= sctx
->b
.debug
;
1939 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
1940 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
1946 sel
->so
= state
->stream_output
;
1947 tgsi_scan_shader(state
->tokens
, &sel
->info
);
1948 sel
->type
= sel
->info
.processor
;
1949 p_atomic_inc(&sscreen
->b
.num_shaders_created
);
1951 /* The prolog is a no-op if there are no inputs. */
1952 sel
->vs_needs_prolog
= sel
->type
== PIPE_SHADER_VERTEX
&&
1953 sel
->info
.num_inputs
;
1955 /* Set which opcode uses which (i,j) pair. */
1956 if (sel
->info
.uses_persp_opcode_interp_centroid
)
1957 sel
->info
.uses_persp_centroid
= true;
1959 if (sel
->info
.uses_linear_opcode_interp_centroid
)
1960 sel
->info
.uses_linear_centroid
= true;
1962 if (sel
->info
.uses_persp_opcode_interp_offset
||
1963 sel
->info
.uses_persp_opcode_interp_sample
)
1964 sel
->info
.uses_persp_center
= true;
1966 if (sel
->info
.uses_linear_opcode_interp_offset
||
1967 sel
->info
.uses_linear_opcode_interp_sample
)
1968 sel
->info
.uses_linear_center
= true;
1970 switch (sel
->type
) {
1971 case PIPE_SHADER_GEOMETRY
:
1972 sel
->gs_output_prim
=
1973 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
1974 sel
->gs_max_out_vertices
=
1975 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
1976 sel
->gs_num_invocations
=
1977 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
1978 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
1979 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
1980 sel
->gs_max_out_vertices
;
1982 sel
->max_gs_stream
= 0;
1983 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
1984 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
1985 sel
->so
.output
[i
].stream
);
1987 sel
->gs_input_verts_per_prim
=
1988 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
1991 case PIPE_SHADER_TESS_CTRL
:
1992 /* Always reserve space for these. */
1993 sel
->patch_outputs_written
|=
1994 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER
, 0)) |
1995 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER
, 0));
1997 case PIPE_SHADER_VERTEX
:
1998 case PIPE_SHADER_TESS_EVAL
:
1999 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2000 unsigned name
= sel
->info
.output_semantic_name
[i
];
2001 unsigned index
= sel
->info
.output_semantic_index
[i
];
2004 case TGSI_SEMANTIC_TESSINNER
:
2005 case TGSI_SEMANTIC_TESSOUTER
:
2006 case TGSI_SEMANTIC_PATCH
:
2007 sel
->patch_outputs_written
|=
2008 1llu << si_shader_io_get_unique_index(name
, index
);
2011 case TGSI_SEMANTIC_GENERIC
:
2012 /* don't process indices the function can't handle */
2016 case TGSI_SEMANTIC_POSITION
:
2017 case TGSI_SEMANTIC_PSIZE
:
2018 case TGSI_SEMANTIC_CLIPDIST
:
2019 sel
->outputs_written
|=
2020 1llu << si_shader_io_get_unique_index(name
, index
);
2022 case TGSI_SEMANTIC_CLIPVERTEX
: /* ignore these */
2023 case TGSI_SEMANTIC_EDGEFLAG
:
2026 sel
->outputs_written2
|=
2027 1u << si_shader_io_get_unique_index2(name
, index
);
2030 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
2032 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2033 * conflicts, i.e. each vertex will start at a different bank.
2035 if (sctx
->b
.chip_class
>= GFX9
)
2036 sel
->esgs_itemsize
+= 4;
2039 case PIPE_SHADER_FRAGMENT
:
2040 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2041 unsigned name
= sel
->info
.input_semantic_name
[i
];
2042 unsigned index
= sel
->info
.input_semantic_index
[i
];
2045 case TGSI_SEMANTIC_CLIPDIST
:
2046 case TGSI_SEMANTIC_GENERIC
:
2048 1llu << si_shader_io_get_unique_index(name
, index
);
2050 case TGSI_SEMANTIC_PCOORD
: /* ignore this */
2053 sel
->inputs_read2
|=
2054 1u << si_shader_io_get_unique_index2(name
, index
);
2058 for (i
= 0; i
< 8; i
++)
2059 if (sel
->info
.colors_written
& (1 << i
))
2060 sel
->colors_written_4bit
|= 0xf << (4 * i
);
2062 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2063 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
2064 int index
= sel
->info
.input_semantic_index
[i
];
2065 sel
->color_attr_index
[index
] = i
;
2071 /* DB_SHADER_CONTROL */
2072 sel
->db_shader_control
=
2073 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
2074 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
2075 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
2076 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
2078 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
2079 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2080 sel
->db_shader_control
|=
2081 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2083 case TGSI_FS_DEPTH_LAYOUT_LESS
:
2084 sel
->db_shader_control
|=
2085 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2089 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2091 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2092 * --|-----------|------------|------------|--------------------|-------------------|-------------
2093 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2094 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2095 * 2 | false | true | n/a | LateZ | 1 | 0
2096 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2097 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2099 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2100 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2102 * Don't use ReZ without profiling !!!
2104 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2107 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
2109 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
2110 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
2111 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
2112 } else if (sel
->info
.writes_memory
) {
2114 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) |
2115 S_02880C_EXEC_ON_HIER_FAIL(1);
2118 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2121 (void) mtx_init(&sel
->mutex
, mtx_plain
);
2122 util_queue_fence_init(&sel
->ready
);
2124 if ((sctx
->b
.debug
.debug_message
&& !sctx
->b
.debug
.async
) ||
2126 r600_can_dump_shader(&sscreen
->b
, sel
->info
.processor
))
2127 si_init_shader_selector_async(sel
, -1);
2129 util_queue_add_job(&sscreen
->shader_compiler_queue
, sel
,
2130 &sel
->ready
, si_init_shader_selector_async
,
2136 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
2138 struct si_context
*sctx
= (struct si_context
*)ctx
;
2139 struct si_shader_selector
*sel
= state
;
2141 if (sctx
->vs_shader
.cso
== sel
)
2144 sctx
->vs_shader
.cso
= sel
;
2145 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2146 sctx
->do_update_shaders
= true;
2147 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
2148 r600_update_vs_writes_viewport_index(&sctx
->b
, si_get_vs_info(sctx
));
2151 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
2153 struct si_context
*sctx
= (struct si_context
*)ctx
;
2154 struct si_shader_selector
*sel
= state
;
2155 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
2157 if (sctx
->gs_shader
.cso
== sel
)
2160 sctx
->gs_shader
.cso
= sel
;
2161 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2162 sctx
->ia_multi_vgt_param_key
.u
.uses_gs
= sel
!= NULL
;
2163 sctx
->do_update_shaders
= true;
2164 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
2165 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2168 si_shader_change_notify(sctx
);
2169 r600_update_vs_writes_viewport_index(&sctx
->b
, si_get_vs_info(sctx
));
2172 static void si_update_tcs_tes_uses_prim_id(struct si_context
*sctx
)
2174 sctx
->ia_multi_vgt_param_key
.u
.tcs_tes_uses_prim_id
=
2175 (sctx
->tes_shader
.cso
&&
2176 sctx
->tes_shader
.cso
->info
.uses_primid
) ||
2177 (sctx
->tcs_shader
.cso
&&
2178 sctx
->tcs_shader
.cso
->info
.uses_primid
);
2181 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
2183 struct si_context
*sctx
= (struct si_context
*)ctx
;
2184 struct si_shader_selector
*sel
= state
;
2185 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
2187 if (sctx
->tcs_shader
.cso
== sel
)
2190 sctx
->tcs_shader
.cso
= sel
;
2191 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2192 si_update_tcs_tes_uses_prim_id(sctx
);
2193 sctx
->do_update_shaders
= true;
2196 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
2199 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
2201 struct si_context
*sctx
= (struct si_context
*)ctx
;
2202 struct si_shader_selector
*sel
= state
;
2203 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
2205 if (sctx
->tes_shader
.cso
== sel
)
2208 sctx
->tes_shader
.cso
= sel
;
2209 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
2210 sctx
->ia_multi_vgt_param_key
.u
.uses_tess
= sel
!= NULL
;
2211 si_update_tcs_tes_uses_prim_id(sctx
);
2212 sctx
->do_update_shaders
= true;
2213 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
2214 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2216 if (enable_changed
) {
2217 si_shader_change_notify(sctx
);
2218 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
2220 r600_update_vs_writes_viewport_index(&sctx
->b
, si_get_vs_info(sctx
));
2223 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
2225 struct si_context
*sctx
= (struct si_context
*)ctx
;
2226 struct si_shader_selector
*sel
= state
;
2228 /* skip if supplied shader is one already in use */
2229 if (sctx
->ps_shader
.cso
== sel
)
2232 sctx
->ps_shader
.cso
= sel
;
2233 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
2234 sctx
->do_update_shaders
= true;
2235 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
2238 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
2240 if (shader
->is_optimized
) {
2241 util_queue_fence_wait(&shader
->optimized_ready
);
2242 util_queue_fence_destroy(&shader
->optimized_ready
);
2246 switch (shader
->selector
->type
) {
2247 case PIPE_SHADER_VERTEX
:
2248 if (shader
->key
.as_ls
) {
2249 assert(sctx
->b
.chip_class
<= VI
);
2250 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
2251 } else if (shader
->key
.as_es
) {
2252 assert(sctx
->b
.chip_class
<= VI
);
2253 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2255 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2258 case PIPE_SHADER_TESS_CTRL
:
2259 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
2261 case PIPE_SHADER_TESS_EVAL
:
2262 if (shader
->key
.as_es
) {
2263 assert(sctx
->b
.chip_class
<= VI
);
2264 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2266 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2269 case PIPE_SHADER_GEOMETRY
:
2270 if (shader
->is_gs_copy_shader
)
2271 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2273 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
2275 case PIPE_SHADER_FRAGMENT
:
2276 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
2281 si_shader_selector_reference(sctx
, &shader
->previous_stage_sel
, NULL
);
2282 si_shader_destroy(shader
);
2286 static void si_destroy_shader_selector(struct si_context
*sctx
,
2287 struct si_shader_selector
*sel
)
2289 struct si_shader
*p
= sel
->first_variant
, *c
;
2290 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
2291 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
2292 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
2293 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
2294 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
2295 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
2298 util_queue_fence_wait(&sel
->ready
);
2300 if (current_shader
[sel
->type
]->cso
== sel
) {
2301 current_shader
[sel
->type
]->cso
= NULL
;
2302 current_shader
[sel
->type
]->current
= NULL
;
2306 c
= p
->next_variant
;
2307 si_delete_shader(sctx
, p
);
2311 if (sel
->main_shader_part
)
2312 si_delete_shader(sctx
, sel
->main_shader_part
);
2313 if (sel
->main_shader_part_ls
)
2314 si_delete_shader(sctx
, sel
->main_shader_part_ls
);
2315 if (sel
->main_shader_part_es
)
2316 si_delete_shader(sctx
, sel
->main_shader_part_es
);
2317 if (sel
->gs_copy_shader
)
2318 si_delete_shader(sctx
, sel
->gs_copy_shader
);
2320 util_queue_fence_destroy(&sel
->ready
);
2321 mtx_destroy(&sel
->mutex
);
2326 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
2328 struct si_context
*sctx
= (struct si_context
*)ctx
;
2329 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
2331 si_shader_selector_reference(sctx
, &sel
, NULL
);
2334 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
2335 struct si_shader
*vs
, unsigned name
,
2336 unsigned index
, unsigned interpolate
)
2338 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
2339 unsigned j
, offset
, ps_input_cntl
= 0;
2341 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2342 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
))
2343 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
2345 if (name
== TGSI_SEMANTIC_PCOORD
||
2346 (name
== TGSI_SEMANTIC_TEXCOORD
&&
2347 sctx
->sprite_coord_enable
& (1 << index
))) {
2348 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
2351 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
2352 if (name
== vsinfo
->output_semantic_name
[j
] &&
2353 index
== vsinfo
->output_semantic_index
[j
]) {
2354 offset
= vs
->info
.vs_output_param_offset
[j
];
2356 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
2357 /* The input is loaded from parameter memory. */
2358 ps_input_cntl
|= S_028644_OFFSET(offset
);
2359 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2360 if (offset
== AC_EXP_PARAM_UNDEFINED
) {
2361 /* This can happen with depth-only rendering. */
2364 /* The input is a DEFAULT_VAL constant. */
2365 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
2366 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
2367 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
2370 ps_input_cntl
= S_028644_OFFSET(0x20) |
2371 S_028644_DEFAULT_VAL(offset
);
2377 if (name
== TGSI_SEMANTIC_PRIMID
)
2378 /* PrimID is written after the last output. */
2379 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
2380 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2381 /* No corresponding output found, load defaults into input.
2382 * Don't set any other bits.
2383 * (FLAT_SHADE=1 completely changes behavior) */
2384 ps_input_cntl
= S_028644_OFFSET(0x20);
2385 /* D3D 9 behaviour. GL is undefined */
2386 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
2387 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
2389 return ps_input_cntl
;
2392 static void si_emit_spi_map(struct si_context
*sctx
, struct r600_atom
*atom
)
2394 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2395 struct si_shader
*ps
= sctx
->ps_shader
.current
;
2396 struct si_shader
*vs
= si_get_vs_state(sctx
);
2397 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
2398 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
2400 if (!ps
|| !ps
->selector
->info
.num_inputs
)
2403 num_interp
= si_get_ps_num_interp(ps
);
2404 assert(num_interp
> 0);
2405 radeon_set_context_reg_seq(cs
, R_028644_SPI_PS_INPUT_CNTL_0
, num_interp
);
2407 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
2408 unsigned name
= psinfo
->input_semantic_name
[i
];
2409 unsigned index
= psinfo
->input_semantic_index
[i
];
2410 unsigned interpolate
= psinfo
->input_interpolate
[i
];
2412 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, name
, index
,
2416 if (name
== TGSI_SEMANTIC_COLOR
) {
2417 assert(index
< ARRAY_SIZE(bcol_interp
));
2418 bcol_interp
[index
] = interpolate
;
2422 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
2423 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
2425 for (i
= 0; i
< 2; i
++) {
2426 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
2429 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, bcol
,
2430 i
, bcol_interp
[i
]));
2434 assert(num_interp
== num_written
);
2438 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2440 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
2442 if (sctx
->init_config_has_vgt_flush
)
2445 /* Done by Vulkan before VGT_FLUSH. */
2446 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2447 si_pm4_cmd_add(sctx
->init_config
,
2448 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2449 si_pm4_cmd_end(sctx
->init_config
, false);
2451 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2452 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2453 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
2454 si_pm4_cmd_end(sctx
->init_config
, false);
2455 sctx
->init_config_has_vgt_flush
= true;
2458 /* Initialize state related to ESGS / GSVS ring buffers */
2459 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
2461 struct si_shader_selector
*es
=
2462 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
2463 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
2464 struct si_pm4_state
*pm4
;
2466 /* Chip constants. */
2467 unsigned num_se
= sctx
->screen
->b
.info
.max_se
;
2468 unsigned wave_size
= 64;
2469 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
2470 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2471 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2473 unsigned gs_vertex_reuse
= (sctx
->b
.chip_class
>= VI
? 32 : 16) * num_se
;
2474 unsigned alignment
= 256 * num_se
;
2475 /* The maximum size is 63.999 MB per SE. */
2476 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
2478 /* Calculate the minimum size. */
2479 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
2480 wave_size
, alignment
);
2482 /* These are recommended sizes, not minimum sizes. */
2483 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
2484 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
2485 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
2486 gs
->max_gsvs_emit_size
;
2488 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
2489 esgs_ring_size
= align(esgs_ring_size
, alignment
);
2490 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
2492 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
2493 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
2495 /* Some rings don't have to be allocated if shaders don't use them.
2496 * (e.g. no varyings between ES and GS or GS and VS)
2498 * GFX9 doesn't have the ESGS ring.
2500 bool update_esgs
= sctx
->b
.chip_class
<= VI
&&
2502 (!sctx
->esgs_ring
||
2503 sctx
->esgs_ring
->width0
< esgs_ring_size
);
2504 bool update_gsvs
= gsvs_ring_size
&&
2505 (!sctx
->gsvs_ring
||
2506 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
2508 if (!update_esgs
&& !update_gsvs
)
2512 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
2514 r600_aligned_buffer_create(sctx
->b
.b
.screen
,
2515 R600_RESOURCE_FLAG_UNMAPPABLE
,
2517 esgs_ring_size
, alignment
);
2518 if (!sctx
->esgs_ring
)
2523 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
2525 r600_aligned_buffer_create(sctx
->b
.b
.screen
,
2526 R600_RESOURCE_FLAG_UNMAPPABLE
,
2528 gsvs_ring_size
, alignment
);
2529 if (!sctx
->gsvs_ring
)
2533 /* Create the "init_config_gs_rings" state. */
2534 pm4
= CALLOC_STRUCT(si_pm4_state
);
2538 if (sctx
->b
.chip_class
>= CIK
) {
2539 if (sctx
->esgs_ring
) {
2540 assert(sctx
->b
.chip_class
<= VI
);
2541 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
2542 sctx
->esgs_ring
->width0
/ 256);
2544 if (sctx
->gsvs_ring
)
2545 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
2546 sctx
->gsvs_ring
->width0
/ 256);
2548 if (sctx
->esgs_ring
)
2549 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
2550 sctx
->esgs_ring
->width0
/ 256);
2551 if (sctx
->gsvs_ring
)
2552 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
2553 sctx
->gsvs_ring
->width0
/ 256);
2556 /* Set the state. */
2557 if (sctx
->init_config_gs_rings
)
2558 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
2559 sctx
->init_config_gs_rings
= pm4
;
2561 if (!sctx
->init_config_has_vgt_flush
) {
2562 si_init_config_add_vgt_flush(sctx
);
2563 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
2566 /* Flush the context to re-emit both init_config states. */
2567 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
2568 si_context_gfx_flush(sctx
, RADEON_FLUSH_ASYNC
, NULL
);
2570 /* Set ring bindings. */
2571 if (sctx
->esgs_ring
) {
2572 assert(sctx
->b
.chip_class
<= VI
);
2573 si_set_ring_buffer(&sctx
->b
.b
, SI_ES_RING_ESGS
,
2574 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
2575 true, true, 4, 64, 0);
2576 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_ESGS
,
2577 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
2578 false, false, 0, 0, 0);
2580 if (sctx
->gsvs_ring
) {
2581 si_set_ring_buffer(&sctx
->b
.b
, SI_RING_GSVS
,
2582 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
2583 false, false, 0, 0, 0);
2589 static void si_shader_lock(struct si_shader
*shader
)
2591 mtx_lock(&shader
->selector
->mutex
);
2592 if (shader
->previous_stage_sel
) {
2593 assert(shader
->previous_stage_sel
!= shader
->selector
);
2594 mtx_lock(&shader
->previous_stage_sel
->mutex
);
2598 static void si_shader_unlock(struct si_shader
*shader
)
2600 if (shader
->previous_stage_sel
)
2601 mtx_unlock(&shader
->previous_stage_sel
->mutex
);
2602 mtx_unlock(&shader
->selector
->mutex
);
2606 * @returns 1 if \p sel has been updated to use a new scratch buffer
2608 * < 0 if there was a failure
2610 static int si_update_scratch_buffer(struct si_context
*sctx
,
2611 struct si_shader
*shader
)
2613 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
2619 /* This shader doesn't need a scratch buffer */
2620 if (shader
->config
.scratch_bytes_per_wave
== 0)
2623 /* Prevent race conditions when updating:
2624 * - si_shader::scratch_bo
2625 * - si_shader::binary::code
2626 * - si_shader::previous_stage::binary::code.
2628 si_shader_lock(shader
);
2630 /* This shader is already configured to use the current
2631 * scratch buffer. */
2632 if (shader
->scratch_bo
== sctx
->scratch_buffer
) {
2633 si_shader_unlock(shader
);
2637 assert(sctx
->scratch_buffer
);
2639 if (shader
->previous_stage
)
2640 si_shader_apply_scratch_relocs(shader
->previous_stage
, scratch_va
);
2642 si_shader_apply_scratch_relocs(shader
, scratch_va
);
2644 /* Replace the shader bo with a new bo that has the relocs applied. */
2645 r
= si_shader_binary_upload(sctx
->screen
, shader
);
2647 si_shader_unlock(shader
);
2651 /* Update the shader state to use the new shader bo. */
2652 si_shader_init_pm4_state(sctx
->screen
, shader
);
2654 r600_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
2656 si_shader_unlock(shader
);
2660 static unsigned si_get_current_scratch_buffer_size(struct si_context
*sctx
)
2662 return sctx
->scratch_buffer
? sctx
->scratch_buffer
->b
.b
.width0
: 0;
2665 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
2667 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
2670 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context
*sctx
)
2674 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
2675 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
2676 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
2677 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tcs_shader
.current
));
2678 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
2682 static bool si_update_scratch_relocs(struct si_context
*sctx
)
2686 /* Update the shaders, so that they are using the latest scratch.
2687 * The scratch buffer may have been changed since these shaders were
2688 * last used, so we still need to try to update them, even if they
2689 * require scratch buffers smaller than the current size.
2691 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
2695 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
2697 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
2701 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
2703 r
= si_update_scratch_buffer(sctx
, sctx
->tcs_shader
.current
);
2707 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
2709 /* VS can be bound as LS, ES, or VS. */
2710 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
2714 if (sctx
->tes_shader
.current
)
2715 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
2716 else if (sctx
->gs_shader
.current
)
2717 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
2719 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
2722 /* TES can be bound as ES or VS. */
2723 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
2727 if (sctx
->gs_shader
.current
)
2728 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
2730 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
2736 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
2738 unsigned current_scratch_buffer_size
=
2739 si_get_current_scratch_buffer_size(sctx
);
2740 unsigned scratch_bytes_per_wave
=
2741 si_get_max_scratch_bytes_per_wave(sctx
);
2742 unsigned scratch_needed_size
= scratch_bytes_per_wave
*
2743 sctx
->scratch_waves
;
2744 unsigned spi_tmpring_size
;
2746 if (scratch_needed_size
> 0) {
2747 if (scratch_needed_size
> current_scratch_buffer_size
) {
2748 /* Create a bigger scratch buffer */
2749 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
2751 sctx
->scratch_buffer
= (struct r600_resource
*)
2752 r600_aligned_buffer_create(&sctx
->screen
->b
.b
,
2753 R600_RESOURCE_FLAG_UNMAPPABLE
,
2755 scratch_needed_size
, 256);
2756 if (!sctx
->scratch_buffer
)
2759 si_mark_atom_dirty(sctx
, &sctx
->scratch_state
);
2760 r600_context_add_resource_size(&sctx
->b
.b
,
2761 &sctx
->scratch_buffer
->b
.b
);
2764 if (!si_update_scratch_relocs(sctx
))
2768 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
2769 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
2770 "scratch size should already be aligned correctly.");
2772 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
2773 S_0286E8_WAVESIZE(scratch_bytes_per_wave
>> 10);
2774 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
2775 sctx
->spi_tmpring_size
= spi_tmpring_size
;
2776 si_mark_atom_dirty(sctx
, &sctx
->scratch_state
);
2781 static void si_init_tess_factor_ring(struct si_context
*sctx
)
2783 bool double_offchip_buffers
= sctx
->b
.chip_class
>= CIK
&&
2784 sctx
->b
.family
!= CHIP_CARRIZO
&&
2785 sctx
->b
.family
!= CHIP_STONEY
;
2786 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
2787 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
2788 sctx
->screen
->b
.info
.max_se
;
2789 unsigned offchip_granularity
;
2791 switch (sctx
->screen
->tess_offchip_block_dw_size
) {
2796 offchip_granularity
= V_03093C_X_8K_DWORDS
;
2799 offchip_granularity
= V_03093C_X_4K_DWORDS
;
2803 switch (sctx
->b
.chip_class
) {
2805 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
2810 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
2817 assert(!sctx
->tf_ring
);
2818 /* Use 64K alignment for both rings, so that we can pass the address
2819 * to shaders as one SGPR containing bits [16:47].
2821 sctx
->tf_ring
= r600_aligned_buffer_create(sctx
->b
.b
.screen
,
2822 R600_RESOURCE_FLAG_UNMAPPABLE
,
2824 32768 * sctx
->screen
->b
.info
.max_se
,
2829 assert(((sctx
->tf_ring
->width0
/ 4) & C_030938_SIZE
) == 0);
2831 sctx
->tess_offchip_ring
=
2832 r600_aligned_buffer_create(sctx
->b
.b
.screen
,
2833 R600_RESOURCE_FLAG_UNMAPPABLE
,
2835 max_offchip_buffers
*
2836 sctx
->screen
->tess_offchip_block_dw_size
* 4,
2838 if (!sctx
->tess_offchip_ring
)
2841 si_init_config_add_vgt_flush(sctx
);
2843 uint64_t offchip_va
= r600_resource(sctx
->tess_offchip_ring
)->gpu_address
;
2844 uint64_t factor_va
= r600_resource(sctx
->tf_ring
)->gpu_address
;
2845 assert((offchip_va
& 0xffff) == 0);
2846 assert((factor_va
& 0xffff) == 0);
2848 si_pm4_add_bo(sctx
->init_config
, r600_resource(sctx
->tess_offchip_ring
),
2849 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
2850 si_pm4_add_bo(sctx
->init_config
, r600_resource(sctx
->tf_ring
),
2851 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
2853 /* Append these registers to the init config state. */
2854 if (sctx
->b
.chip_class
>= CIK
) {
2855 if (sctx
->b
.chip_class
>= VI
)
2856 --max_offchip_buffers
;
2858 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
2859 S_030938_SIZE(sctx
->tf_ring
->width0
/ 4));
2860 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
2862 if (sctx
->b
.chip_class
>= GFX9
)
2863 si_pm4_set_reg(sctx
->init_config
, R_030944_VGT_TF_MEMORY_BASE_HI
,
2865 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
2866 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
2867 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
));
2869 assert(offchip_granularity
== V_03093C_X_8K_DWORDS
);
2870 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
2871 S_008988_SIZE(sctx
->tf_ring
->width0
/ 4));
2872 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
2874 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
2875 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
));
2878 if (sctx
->b
.chip_class
>= GFX9
) {
2879 si_pm4_set_reg(sctx
->init_config
,
2880 R_00B430_SPI_SHADER_USER_DATA_LS_0
+
2881 GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K
* 4,
2883 si_pm4_set_reg(sctx
->init_config
,
2884 R_00B430_SPI_SHADER_USER_DATA_LS_0
+
2885 GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K
* 4,
2888 si_pm4_set_reg(sctx
->init_config
,
2889 R_00B430_SPI_SHADER_USER_DATA_HS_0
+
2890 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K
* 4,
2892 si_pm4_set_reg(sctx
->init_config
,
2893 R_00B430_SPI_SHADER_USER_DATA_HS_0
+
2894 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K
* 4,
2898 /* Flush the context to re-emit the init_config state.
2899 * This is done only once in a lifetime of a context.
2901 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
2902 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
2903 si_context_gfx_flush(sctx
, RADEON_FLUSH_ASYNC
, NULL
);
2907 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
2908 * VS passes its outputs to TES directly, so the fixed-function shader only
2909 * has to write TESSOUTER and TESSINNER.
2911 static void si_generate_fixed_func_tcs(struct si_context
*sctx
)
2913 struct ureg_src outer
, inner
;
2914 struct ureg_dst tessouter
, tessinner
;
2915 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_TESS_CTRL
);
2918 return; /* if we get here, we're screwed */
2920 assert(!sctx
->fixed_func_tcs_shader
.cso
);
2922 outer
= ureg_DECL_system_value(ureg
,
2923 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
, 0);
2924 inner
= ureg_DECL_system_value(ureg
,
2925 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
, 0);
2927 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
2928 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
2930 ureg_MOV(ureg
, tessouter
, outer
);
2931 ureg_MOV(ureg
, tessinner
, inner
);
2934 sctx
->fixed_func_tcs_shader
.cso
=
2935 ureg_create_shader_and_destroy(ureg
, &sctx
->b
.b
);
2938 static void si_update_vgt_shader_config(struct si_context
*sctx
)
2940 /* Calculate the index of the config.
2941 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
2942 unsigned index
= 2*!!sctx
->tes_shader
.cso
+ !!sctx
->gs_shader
.cso
;
2943 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[index
];
2946 uint32_t stages
= 0;
2948 *pm4
= CALLOC_STRUCT(si_pm4_state
);
2950 if (sctx
->tes_shader
.cso
) {
2951 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
2952 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2954 if (sctx
->gs_shader
.cso
)
2955 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
2957 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
2959 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
2960 } else if (sctx
->gs_shader
.cso
) {
2961 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
2963 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
2966 if (sctx
->b
.chip_class
>= GFX9
)
2967 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2969 si_pm4_set_reg(*pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
2971 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
2974 static void si_update_so(struct si_context
*sctx
, struct si_shader_selector
*shader
)
2976 struct pipe_stream_output_info
*so
= &shader
->so
;
2977 uint32_t enabled_stream_buffers_mask
= 0;
2980 for (i
= 0; i
< so
->num_outputs
; i
++)
2981 enabled_stream_buffers_mask
|= (1 << so
->output
[i
].output_buffer
) << (so
->output
[i
].stream
* 4);
2982 sctx
->b
.streamout
.enabled_stream_buffers_mask
= enabled_stream_buffers_mask
;
2983 sctx
->b
.streamout
.stride_in_dw
= shader
->so
.stride
;
2986 bool si_update_shaders(struct si_context
*sctx
)
2988 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
2989 struct si_compiler_ctx_state compiler_state
;
2990 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
2991 struct si_shader
*old_vs
= si_get_vs_state(sctx
);
2992 bool old_clip_disable
= old_vs
? old_vs
->key
.opt
.hw_vs
.clip_disable
: false;
2995 compiler_state
.tm
= sctx
->tm
;
2996 compiler_state
.debug
= sctx
->b
.debug
;
2997 compiler_state
.is_debug_context
= sctx
->is_debug
;
2999 /* Update stages before GS. */
3000 if (sctx
->tes_shader
.cso
) {
3001 if (!sctx
->tf_ring
) {
3002 si_init_tess_factor_ring(sctx
);
3008 if (sctx
->b
.chip_class
<= VI
) {
3009 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
3013 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3016 if (sctx
->tcs_shader
.cso
) {
3017 r
= si_shader_select(ctx
, &sctx
->tcs_shader
,
3021 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
3023 if (!sctx
->fixed_func_tcs_shader
.cso
) {
3024 si_generate_fixed_func_tcs(sctx
);
3025 if (!sctx
->fixed_func_tcs_shader
.cso
)
3029 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
,
3033 si_pm4_bind_state(sctx
, hs
,
3034 sctx
->fixed_func_tcs_shader
.current
->pm4
);
3037 if (sctx
->gs_shader
.cso
) {
3039 if (sctx
->b
.chip_class
<= VI
) {
3040 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
3044 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3048 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
3052 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3053 si_update_so(sctx
, sctx
->tes_shader
.cso
);
3055 } else if (sctx
->gs_shader
.cso
) {
3056 if (sctx
->b
.chip_class
<= VI
) {
3058 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
3062 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3064 si_pm4_bind_state(sctx
, ls
, NULL
);
3065 si_pm4_bind_state(sctx
, hs
, NULL
);
3069 r
= si_shader_select(ctx
, &sctx
->vs_shader
, &compiler_state
);
3072 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3073 si_update_so(sctx
, sctx
->vs_shader
.cso
);
3075 si_pm4_bind_state(sctx
, ls
, NULL
);
3076 si_pm4_bind_state(sctx
, hs
, NULL
);
3080 if (sctx
->gs_shader
.cso
) {
3081 r
= si_shader_select(ctx
, &sctx
->gs_shader
, &compiler_state
);
3084 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3085 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
3086 si_update_so(sctx
, sctx
->gs_shader
.cso
);
3088 if (!si_update_gs_ring_buffers(sctx
))
3091 si_pm4_bind_state(sctx
, gs
, NULL
);
3092 if (sctx
->b
.chip_class
<= VI
)
3093 si_pm4_bind_state(sctx
, es
, NULL
);
3096 si_update_vgt_shader_config(sctx
);
3098 if (old_clip_disable
!= si_get_vs_state(sctx
)->key
.opt
.hw_vs
.clip_disable
)
3099 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
3101 if (sctx
->ps_shader
.cso
) {
3102 unsigned db_shader_control
;
3104 r
= si_shader_select(ctx
, &sctx
->ps_shader
, &compiler_state
);
3107 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3110 sctx
->ps_shader
.cso
->db_shader_control
|
3111 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
3113 if (si_pm4_state_changed(sctx
, ps
) || si_pm4_state_changed(sctx
, vs
) ||
3114 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
3115 sctx
->flatshade
!= rs
->flatshade
) {
3116 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
3117 sctx
->flatshade
= rs
->flatshade
;
3118 si_mark_atom_dirty(sctx
, &sctx
->spi_map
);
3121 if (sctx
->screen
->b
.rbplus_allowed
&& si_pm4_state_changed(sctx
, ps
))
3122 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
3124 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
3125 sctx
->ps_db_shader_control
= db_shader_control
;
3126 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
3129 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
3130 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
3131 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
3133 if (sctx
->b
.chip_class
== SI
)
3134 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
3136 if (sctx
->framebuffer
.nr_samples
<= 1)
3137 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
3141 if (si_pm4_state_changed(sctx
, ls
) ||
3142 si_pm4_state_changed(sctx
, hs
) ||
3143 si_pm4_state_changed(sctx
, es
) ||
3144 si_pm4_state_changed(sctx
, gs
) ||
3145 si_pm4_state_changed(sctx
, vs
) ||
3146 si_pm4_state_changed(sctx
, ps
)) {
3147 if (!si_update_spi_tmpring_size(sctx
))
3151 if (sctx
->b
.chip_class
>= CIK
)
3152 si_mark_atom_dirty(sctx
, &sctx
->prefetch_L2
);
3154 sctx
->do_update_shaders
= false;
3158 static void si_emit_scratch_state(struct si_context
*sctx
,
3159 struct r600_atom
*atom
)
3161 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
3163 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
3164 sctx
->spi_tmpring_size
);
3166 if (sctx
->scratch_buffer
) {
3167 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
3168 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
3169 RADEON_PRIO_SCRATCH_BUFFER
);
3173 void si_init_shader_functions(struct si_context
*sctx
)
3175 si_init_atom(sctx
, &sctx
->spi_map
, &sctx
->atoms
.s
.spi_map
, si_emit_spi_map
);
3176 si_init_atom(sctx
, &sctx
->scratch_state
, &sctx
->atoms
.s
.scratch_state
,
3177 si_emit_scratch_state
);
3179 sctx
->b
.b
.create_vs_state
= si_create_shader_selector
;
3180 sctx
->b
.b
.create_tcs_state
= si_create_shader_selector
;
3181 sctx
->b
.b
.create_tes_state
= si_create_shader_selector
;
3182 sctx
->b
.b
.create_gs_state
= si_create_shader_selector
;
3183 sctx
->b
.b
.create_fs_state
= si_create_shader_selector
;
3185 sctx
->b
.b
.bind_vs_state
= si_bind_vs_shader
;
3186 sctx
->b
.b
.bind_tcs_state
= si_bind_tcs_shader
;
3187 sctx
->b
.b
.bind_tes_state
= si_bind_tes_shader
;
3188 sctx
->b
.b
.bind_gs_state
= si_bind_gs_shader
;
3189 sctx
->b
.b
.bind_fs_state
= si_bind_ps_shader
;
3191 sctx
->b
.b
.delete_vs_state
= si_delete_shader_selector
;
3192 sctx
->b
.b
.delete_tcs_state
= si_delete_shader_selector
;
3193 sctx
->b
.b
.delete_tes_state
= si_delete_shader_selector
;
3194 sctx
->b
.b
.delete_gs_state
= si_delete_shader_selector
;
3195 sctx
->b
.b
.delete_fs_state
= si_delete_shader_selector
;