2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "util/hash_table.h"
32 #include "util/crc32.h"
33 #include "util/u_async_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
37 #include "util/disk_cache.h"
38 #include "util/mesa-sha1.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
45 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
48 void *si_get_ir_binary(struct si_shader_selector
*sel
)
55 ir_binary
= sel
->tokens
;
56 ir_size
= tgsi_num_tokens(sel
->tokens
) *
57 sizeof(struct tgsi_token
);
62 nir_serialize(&blob
, sel
->nir
);
63 ir_binary
= blob
.data
;
67 unsigned size
= 4 + ir_size
+ sizeof(sel
->so
);
68 char *result
= (char*)MALLOC(size
);
72 *((uint32_t*)result
) = size
;
73 memcpy(result
+ 4, ir_binary
, ir_size
);
74 memcpy(result
+ 4 + ir_size
, &sel
->so
, sizeof(sel
->so
));
82 /** Copy "data" to "ptr" and return the next dword following copied data. */
83 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
85 /* data may be NULL if size == 0 */
87 memcpy(ptr
, data
, size
);
88 ptr
+= DIV_ROUND_UP(size
, 4);
92 /** Read data from "ptr". Return the next dword following the data. */
93 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
95 memcpy(data
, ptr
, size
);
96 ptr
+= DIV_ROUND_UP(size
, 4);
101 * Write the size as uint followed by the data. Return the next dword
102 * following the copied data.
104 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
107 return write_data(ptr
, data
, size
);
111 * Read the size as uint followed by the data. Return both via parameters.
112 * Return the next dword following the data.
114 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
117 assert(*data
== NULL
);
120 *data
= malloc(*size
);
121 return read_data(ptr
, *data
, *size
);
125 * Return the shader binary in a buffer. The first 4 bytes contain its size
128 static void *si_get_shader_binary(struct si_shader
*shader
)
130 /* There is always a size of data followed by the data itself. */
131 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
132 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
134 /* Refuse to allocate overly large buffers and guard against integer
136 if (shader
->binary
.elf_size
> UINT_MAX
/ 4 ||
137 llvm_ir_size
> UINT_MAX
/ 4)
142 4 + /* CRC32 of the data below */
143 align(sizeof(shader
->config
), 4) +
144 align(sizeof(shader
->info
), 4) +
145 4 + align(shader
->binary
.elf_size
, 4) +
146 4 + align(llvm_ir_size
, 4);
147 void *buffer
= CALLOC(1, size
);
148 uint32_t *ptr
= (uint32_t*)buffer
;
154 ptr
++; /* CRC32 is calculated at the end. */
156 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
157 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
158 ptr
= write_chunk(ptr
, shader
->binary
.elf_buffer
, shader
->binary
.elf_size
);
159 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
160 assert((char *)ptr
- (char *)buffer
== size
);
163 ptr
= (uint32_t*)buffer
;
165 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
170 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
172 uint32_t *ptr
= (uint32_t*)binary
;
173 uint32_t size
= *ptr
++;
174 uint32_t crc32
= *ptr
++;
178 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
179 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
183 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
184 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
185 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.elf_buffer
,
187 shader
->binary
.elf_size
= elf_size
;
188 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
194 * Insert a shader into the cache. It's assumed the shader is not in the cache.
195 * Use si_shader_cache_load_shader before calling this.
197 * Returns false on failure, in which case the ir_binary should be freed.
199 bool si_shader_cache_insert_shader(struct si_screen
*sscreen
, void *ir_binary
,
200 struct si_shader
*shader
,
201 bool insert_into_disk_cache
)
204 struct hash_entry
*entry
;
205 uint8_t key
[CACHE_KEY_SIZE
];
207 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
209 return false; /* already added */
211 hw_binary
= si_get_shader_binary(shader
);
215 if (_mesa_hash_table_insert(sscreen
->shader_cache
, ir_binary
,
216 hw_binary
) == NULL
) {
221 if (sscreen
->disk_shader_cache
&& insert_into_disk_cache
) {
222 disk_cache_compute_key(sscreen
->disk_shader_cache
, ir_binary
,
223 *((uint32_t *)ir_binary
), key
);
224 disk_cache_put(sscreen
->disk_shader_cache
, key
, hw_binary
,
225 *((uint32_t *) hw_binary
), NULL
);
231 bool si_shader_cache_load_shader(struct si_screen
*sscreen
, void *ir_binary
,
232 struct si_shader
*shader
)
234 struct hash_entry
*entry
=
235 _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
237 if (sscreen
->disk_shader_cache
) {
238 unsigned char sha1
[CACHE_KEY_SIZE
];
239 size_t tg_size
= *((uint32_t *) ir_binary
);
241 disk_cache_compute_key(sscreen
->disk_shader_cache
,
242 ir_binary
, tg_size
, sha1
);
246 disk_cache_get(sscreen
->disk_shader_cache
,
251 if (binary_size
< sizeof(uint32_t) ||
252 *((uint32_t*)buffer
) != binary_size
) {
253 /* Something has gone wrong discard the item
254 * from the cache and rebuild/link from
257 assert(!"Invalid radeonsi shader disk cache "
260 disk_cache_remove(sscreen
->disk_shader_cache
,
267 if (!si_load_shader_binary(shader
, buffer
)) {
273 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
,
280 if (si_load_shader_binary(shader
, entry
->data
))
285 p_atomic_inc(&sscreen
->num_shader_cache_hits
);
289 static uint32_t si_shader_cache_key_hash(const void *key
)
291 /* The first dword is the key size. */
292 return util_hash_crc32(key
, *(uint32_t*)key
);
295 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
297 uint32_t *keya
= (uint32_t*)a
;
298 uint32_t *keyb
= (uint32_t*)b
;
300 /* The first dword is the key size. */
304 return memcmp(keya
, keyb
, *keya
) == 0;
307 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
309 FREE((void*)entry
->key
);
313 bool si_init_shader_cache(struct si_screen
*sscreen
)
315 (void) mtx_init(&sscreen
->shader_cache_mutex
, mtx_plain
);
316 sscreen
->shader_cache
=
317 _mesa_hash_table_create(NULL
,
318 si_shader_cache_key_hash
,
319 si_shader_cache_key_equals
);
321 return sscreen
->shader_cache
!= NULL
;
324 void si_destroy_shader_cache(struct si_screen
*sscreen
)
326 if (sscreen
->shader_cache
)
327 _mesa_hash_table_destroy(sscreen
->shader_cache
,
328 si_destroy_shader_cache_entry
);
329 mtx_destroy(&sscreen
->shader_cache_mutex
);
334 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
335 const struct si_shader_selector
*tes
,
336 struct si_pm4_state
*pm4
)
338 const struct tgsi_shader_info
*info
= &tes
->info
;
339 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
340 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
341 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
342 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
343 unsigned type
, partitioning
, topology
, distribution_mode
;
345 switch (tes_prim_mode
) {
346 case PIPE_PRIM_LINES
:
347 type
= V_028B6C_TESS_ISOLINE
;
349 case PIPE_PRIM_TRIANGLES
:
350 type
= V_028B6C_TESS_TRIANGLE
;
352 case PIPE_PRIM_QUADS
:
353 type
= V_028B6C_TESS_QUAD
;
360 switch (tes_spacing
) {
361 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
362 partitioning
= V_028B6C_PART_FRAC_ODD
;
364 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
365 partitioning
= V_028B6C_PART_FRAC_EVEN
;
367 case PIPE_TESS_SPACING_EQUAL
:
368 partitioning
= V_028B6C_PART_INTEGER
;
376 topology
= V_028B6C_OUTPUT_POINT
;
377 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
378 topology
= V_028B6C_OUTPUT_LINE
;
379 else if (tes_vertex_order_cw
)
380 /* for some reason, this must be the other way around */
381 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
383 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
385 if (sscreen
->has_distributed_tess
) {
386 if (sscreen
->info
.family
== CHIP_FIJI
||
387 sscreen
->info
.family
>= CHIP_POLARIS10
)
388 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
390 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
392 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
395 pm4
->shader
->vgt_tf_param
= S_028B6C_TYPE(type
) |
396 S_028B6C_PARTITIONING(partitioning
) |
397 S_028B6C_TOPOLOGY(topology
) |
398 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
401 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
402 * whether the "fractional odd" tessellation spacing is used.
404 * Possible VGT configurations and which state should set the register:
406 * Reg set in | VGT shader configuration | Value
407 * ------------------------------------------------------
409 * VS as ES | ES -> GS -> VS | 30
410 * TES as VS | LS -> HS -> VS | 14 or 30
411 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
413 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
415 static void polaris_set_vgt_vertex_reuse(struct si_screen
*sscreen
,
416 struct si_shader_selector
*sel
,
417 struct si_shader
*shader
,
418 struct si_pm4_state
*pm4
)
420 unsigned type
= sel
->type
;
422 if (sscreen
->info
.family
< CHIP_POLARIS10
||
423 sscreen
->info
.chip_class
>= GFX10
)
426 /* VS as VS, or VS as ES: */
427 if ((type
== PIPE_SHADER_VERTEX
&&
429 (!shader
->key
.as_ls
&& !shader
->is_gs_copy_shader
))) ||
430 /* TES as VS, or TES as ES: */
431 type
== PIPE_SHADER_TESS_EVAL
) {
432 unsigned vtx_reuse_depth
= 30;
434 if (type
== PIPE_SHADER_TESS_EVAL
&&
435 sel
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] ==
436 PIPE_TESS_SPACING_FRACTIONAL_ODD
)
437 vtx_reuse_depth
= 14;
440 pm4
->shader
->vgt_vertex_reuse_block_cntl
= vtx_reuse_depth
;
444 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
447 si_pm4_clear_state(shader
->pm4
);
449 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
452 shader
->pm4
->shader
= shader
;
455 fprintf(stderr
, "radeonsi: Failed to create pm4 state.\n");
460 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs
)
462 /* Add the pointer to VBO descriptors. */
463 return num_always_on_user_sgprs
+ 1;
466 static void si_shader_ls(struct si_screen
*sscreen
, struct si_shader
*shader
)
468 struct si_pm4_state
*pm4
;
469 unsigned vgpr_comp_cnt
;
472 assert(sscreen
->info
.chip_class
<= GFX8
);
474 pm4
= si_get_shader_pm4_state(shader
);
478 va
= shader
->bo
->gpu_address
;
479 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
481 /* We need at least 2 components for LS.
482 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
483 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
485 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
487 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
488 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
490 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
491 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
492 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt
) |
493 S_00B528_DX10_CLAMP(1) |
494 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
495 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
)) |
496 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
499 static void si_shader_hs(struct si_screen
*sscreen
, struct si_shader
*shader
)
501 struct si_pm4_state
*pm4
;
503 unsigned ls_vgpr_comp_cnt
= 0;
505 pm4
= si_get_shader_pm4_state(shader
);
509 va
= shader
->bo
->gpu_address
;
510 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
512 if (sscreen
->info
.chip_class
>= GFX9
) {
513 if (sscreen
->info
.chip_class
>= GFX10
) {
514 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
515 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
517 si_pm4_set_reg(pm4
, R_00B410_SPI_SHADER_PGM_LO_LS
, va
>> 8);
518 si_pm4_set_reg(pm4
, R_00B414_SPI_SHADER_PGM_HI_LS
, S_00B414_MEM_BASE(va
>> 40));
521 /* We need at least 2 components for LS.
522 * GFX9 VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
523 * GFX10 VGPR0-3: (VertexID, RelAutoindex, UserVGPR1, InstanceID).
524 * On gfx9, StepRate0 is set to 1 so that VGPR3 doesn't have to
527 ls_vgpr_comp_cnt
= 1;
528 if (shader
->info
.uses_instanceid
) {
529 if (sscreen
->info
.chip_class
>= GFX10
)
530 ls_vgpr_comp_cnt
= 3;
532 ls_vgpr_comp_cnt
= 2;
535 unsigned num_user_sgprs
=
536 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR
);
538 shader
->config
.rsrc2
=
539 S_00B42C_USER_SGPR(num_user_sgprs
) |
540 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
542 if (sscreen
->info
.chip_class
>= GFX10
)
543 shader
->config
.rsrc2
|= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
545 shader
->config
.rsrc2
|= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
547 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
548 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, S_00B424_MEM_BASE(va
>> 40));
550 shader
->config
.rsrc2
=
551 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR
) |
552 S_00B42C_OC_LDS_EN(1) |
553 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
556 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
557 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) /
558 (sscreen
->ge_wave_size
== 32 ? 8 : 4)) |
559 (sscreen
->info
.chip_class
<= GFX9
?
560 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) : 0) |
561 S_00B428_DX10_CLAMP(1) |
562 S_00B428_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
563 S_00B428_WGP_MODE(sscreen
->info
.chip_class
>= GFX10
) |
564 S_00B428_FLOAT_MODE(shader
->config
.float_mode
) |
565 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt
));
567 if (sscreen
->info
.chip_class
<= GFX8
) {
568 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
569 shader
->config
.rsrc2
);
573 static void si_emit_shader_es(struct si_context
*sctx
)
575 struct si_shader
*shader
= sctx
->queued
.named
.es
->shader
;
576 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
581 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
582 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
583 shader
->selector
->esgs_itemsize
/ 4);
585 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
586 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
587 SI_TRACKED_VGT_TF_PARAM
,
588 shader
->vgt_tf_param
);
590 if (shader
->vgt_vertex_reuse_block_cntl
)
591 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
592 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
593 shader
->vgt_vertex_reuse_block_cntl
);
595 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
596 sctx
->context_roll
= true;
599 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
601 struct si_pm4_state
*pm4
;
602 unsigned num_user_sgprs
;
603 unsigned vgpr_comp_cnt
;
607 assert(sscreen
->info
.chip_class
<= GFX8
);
609 pm4
= si_get_shader_pm4_state(shader
);
613 pm4
->atom
.emit
= si_emit_shader_es
;
614 va
= shader
->bo
->gpu_address
;
615 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
617 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
618 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
619 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
620 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
621 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
622 vgpr_comp_cnt
= shader
->selector
->info
.uses_primid
? 3 : 2;
623 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
625 unreachable("invalid shader selector type");
627 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
629 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
630 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
631 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
632 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
633 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
634 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
635 S_00B328_DX10_CLAMP(1) |
636 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
637 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
638 S_00B32C_USER_SGPR(num_user_sgprs
) |
639 S_00B32C_OC_LDS_EN(oc_lds_en
) |
640 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
642 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
643 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
645 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
648 void gfx9_get_gs_info(struct si_shader_selector
*es
,
649 struct si_shader_selector
*gs
,
650 struct gfx9_gs_info
*out
)
652 unsigned gs_num_invocations
= MAX2(gs
->gs_num_invocations
, 1);
653 unsigned input_prim
= gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
654 bool uses_adjacency
= input_prim
>= PIPE_PRIM_LINES_ADJACENCY
&&
655 input_prim
<= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
;
657 /* All these are in dwords: */
658 /* We can't allow using the whole LDS, because GS waves compete with
659 * other shader stages for LDS space. */
660 const unsigned max_lds_size
= 8 * 1024;
661 const unsigned esgs_itemsize
= es
->esgs_itemsize
/ 4;
662 unsigned esgs_lds_size
;
664 /* All these are per subgroup: */
665 const unsigned max_out_prims
= 32 * 1024;
666 const unsigned max_es_verts
= 255;
667 const unsigned ideal_gs_prims
= 64;
668 unsigned max_gs_prims
, gs_prims
;
669 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
671 if (uses_adjacency
|| gs_num_invocations
> 1)
672 max_gs_prims
= 127 / gs_num_invocations
;
676 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
677 * Make sure we don't go over the maximum value.
679 if (gs
->gs_max_out_vertices
> 0) {
680 max_gs_prims
= MIN2(max_gs_prims
,
682 (gs
->gs_max_out_vertices
* gs_num_invocations
));
684 assert(max_gs_prims
> 0);
686 /* If the primitive has adjacency, halve the number of vertices
687 * that will be reused in multiple primitives.
689 min_es_verts
= gs
->gs_input_verts_per_prim
/ (uses_adjacency
? 2 : 1);
691 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
692 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
694 /* Compute ESGS LDS size based on the worst case number of ES vertices
695 * needed to create the target number of GS prims per subgroup.
697 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
699 /* If total LDS usage is too big, refactor partitions based on ratio
700 * of ESGS item sizes.
702 if (esgs_lds_size
> max_lds_size
) {
703 /* Our target GS Prims Per Subgroup was too large. Calculate
704 * the maximum number of GS Prims Per Subgroup that will fit
705 * into LDS, capped by the maximum that the hardware can support.
707 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
709 assert(gs_prims
> 0);
710 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
713 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
714 assert(esgs_lds_size
<= max_lds_size
);
717 /* Now calculate remaining ESGS information. */
719 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
721 es_verts
= max_es_verts
;
723 /* Vertices for adjacency primitives are not always reused, so restore
724 * it for ES_VERTS_PER_SUBGRP.
726 min_es_verts
= gs
->gs_input_verts_per_prim
;
728 /* For normal primitives, the VGT only checks if they are past the ES
729 * verts per subgroup after allocating a full GS primitive and if they
730 * are, kick off a new subgroup. But if those additional ES verts are
731 * unique (e.g. not reused) we need to make sure there is enough LDS
732 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
734 es_verts
-= min_es_verts
- 1;
736 out
->es_verts_per_subgroup
= es_verts
;
737 out
->gs_prims_per_subgroup
= gs_prims
;
738 out
->gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
739 out
->max_prims_per_subgroup
= out
->gs_inst_prims_in_subgroup
*
740 gs
->gs_max_out_vertices
;
741 out
->esgs_ring_size
= 4 * esgs_lds_size
;
743 assert(out
->max_prims_per_subgroup
<= max_out_prims
);
746 static void si_emit_shader_gs(struct si_context
*sctx
)
748 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
749 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
754 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
755 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
756 radeon_opt_set_context_reg3(sctx
, R_028A60_VGT_GSVS_RING_OFFSET_1
,
757 SI_TRACKED_VGT_GSVS_RING_OFFSET_1
,
758 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
,
759 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
,
760 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
);
762 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
763 radeon_opt_set_context_reg(sctx
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
,
764 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE
,
765 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
);
767 /* R_028B38_VGT_GS_MAX_VERT_OUT */
768 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
769 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
770 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
);
772 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
773 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
774 radeon_opt_set_context_reg4(sctx
, R_028B5C_VGT_GS_VERT_ITEMSIZE
,
775 SI_TRACKED_VGT_GS_VERT_ITEMSIZE
,
776 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
,
777 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
,
778 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
,
779 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
);
781 /* R_028B90_VGT_GS_INSTANCE_CNT */
782 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
,
783 SI_TRACKED_VGT_GS_INSTANCE_CNT
,
784 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
);
786 if (sctx
->chip_class
>= GFX9
) {
787 /* R_028A44_VGT_GS_ONCHIP_CNTL */
788 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
789 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
790 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
);
791 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
792 radeon_opt_set_context_reg(sctx
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
793 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
794 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
);
795 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
796 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
797 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
798 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
);
800 if (shader
->key
.part
.gs
.es
->type
== PIPE_SHADER_TESS_EVAL
)
801 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
802 SI_TRACKED_VGT_TF_PARAM
,
803 shader
->vgt_tf_param
);
804 if (shader
->vgt_vertex_reuse_block_cntl
)
805 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
806 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
807 shader
->vgt_vertex_reuse_block_cntl
);
810 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
811 sctx
->context_roll
= true;
814 static void si_shader_gs(struct si_screen
*sscreen
, struct si_shader
*shader
)
816 struct si_shader_selector
*sel
= shader
->selector
;
817 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
818 unsigned gs_num_invocations
= sel
->gs_num_invocations
;
819 struct si_pm4_state
*pm4
;
821 unsigned max_stream
= sel
->max_gs_stream
;
824 pm4
= si_get_shader_pm4_state(shader
);
828 pm4
->atom
.emit
= si_emit_shader_gs
;
830 offset
= num_components
[0] * sel
->gs_max_out_vertices
;
831 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
= offset
;
834 offset
+= num_components
[1] * sel
->gs_max_out_vertices
;
835 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
= offset
;
838 offset
+= num_components
[2] * sel
->gs_max_out_vertices
;
839 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
= offset
;
842 offset
+= num_components
[3] * sel
->gs_max_out_vertices
;
843 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
= offset
;
845 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
846 assert(offset
< (1 << 15));
848 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
= sel
->gs_max_out_vertices
;
850 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
= num_components
[0];
851 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
= (max_stream
>= 1) ? num_components
[1] : 0;
852 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
= (max_stream
>= 2) ? num_components
[2] : 0;
853 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
= (max_stream
>= 3) ? num_components
[3] : 0;
855 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
= S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
856 S_028B90_ENABLE(gs_num_invocations
> 0);
858 va
= shader
->bo
->gpu_address
;
859 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
861 if (sscreen
->info
.chip_class
>= GFX9
) {
862 unsigned input_prim
= sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
863 unsigned es_type
= shader
->key
.part
.gs
.es
->type
;
864 unsigned es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
866 if (es_type
== PIPE_SHADER_VERTEX
)
867 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
868 es_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
869 else if (es_type
== PIPE_SHADER_TESS_EVAL
)
870 es_vgpr_comp_cnt
= shader
->key
.part
.gs
.es
->info
.uses_primid
? 3 : 2;
872 unreachable("invalid shader selector type");
874 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
875 * VGPR[0:4] are always loaded.
877 if (sel
->info
.uses_invocationid
)
878 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
879 else if (sel
->info
.uses_primid
)
880 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
881 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
882 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
884 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
886 unsigned num_user_sgprs
;
887 if (es_type
== PIPE_SHADER_VERTEX
)
888 num_user_sgprs
= si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR
);
890 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
892 if (sscreen
->info
.chip_class
>= GFX10
) {
893 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
894 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
896 si_pm4_set_reg(pm4
, R_00B210_SPI_SHADER_PGM_LO_ES
, va
>> 8);
897 si_pm4_set_reg(pm4
, R_00B214_SPI_SHADER_PGM_HI_ES
, S_00B214_MEM_BASE(va
>> 40));
901 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
902 S_00B228_DX10_CLAMP(1) |
903 S_00B228_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
904 S_00B228_WGP_MODE(sscreen
->info
.chip_class
>= GFX10
) |
905 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
906 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
);
908 S_00B22C_USER_SGPR(num_user_sgprs
) |
909 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
910 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
911 S_00B22C_LDS_SIZE(shader
->config
.lds_size
) |
912 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
914 if (sscreen
->info
.chip_class
>= GFX10
) {
915 rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
917 rsrc1
|= S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
918 rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
921 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, rsrc1
);
922 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
, rsrc2
);
924 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
=
925 S_028A44_ES_VERTS_PER_SUBGRP(shader
->gs_info
.es_verts_per_subgroup
) |
926 S_028A44_GS_PRIMS_PER_SUBGRP(shader
->gs_info
.gs_prims_per_subgroup
) |
927 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader
->gs_info
.gs_inst_prims_in_subgroup
);
928 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
=
929 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader
->gs_info
.max_prims_per_subgroup
);
930 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
=
931 shader
->key
.part
.gs
.es
->esgs_itemsize
/ 4;
933 if (es_type
== PIPE_SHADER_TESS_EVAL
)
934 si_set_tesseval_regs(sscreen
, shader
->key
.part
.gs
.es
, pm4
);
936 polaris_set_vgt_vertex_reuse(sscreen
, shader
->key
.part
.gs
.es
,
939 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
940 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, S_00B224_MEM_BASE(va
>> 40));
942 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
943 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
944 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
945 S_00B228_DX10_CLAMP(1) |
946 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
947 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
948 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR
) |
949 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
953 /* Common tail code for NGG primitive shaders. */
954 static void gfx10_emit_shader_ngg_tail(struct si_context
*sctx
,
955 struct si_shader
*shader
,
956 unsigned initial_cdw
)
958 radeon_opt_set_context_reg(sctx
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
959 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP
,
960 shader
->ctx_reg
.ngg
.ge_max_output_per_subgroup
);
961 radeon_opt_set_context_reg(sctx
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
962 SI_TRACKED_GE_NGG_SUBGRP_CNTL
,
963 shader
->ctx_reg
.ngg
.ge_ngg_subgrp_cntl
);
964 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
,
965 SI_TRACKED_VGT_PRIMITIVEID_EN
,
966 shader
->ctx_reg
.ngg
.vgt_primitiveid_en
);
967 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
968 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
969 shader
->ctx_reg
.ngg
.vgt_gs_onchip_cntl
);
970 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
,
971 SI_TRACKED_VGT_GS_INSTANCE_CNT
,
972 shader
->ctx_reg
.ngg
.vgt_gs_instance_cnt
);
973 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
974 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
975 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
);
976 radeon_opt_set_context_reg(sctx
, R_028AB4_VGT_REUSE_OFF
,
977 SI_TRACKED_VGT_REUSE_OFF
,
978 shader
->ctx_reg
.ngg
.vgt_reuse_off
);
979 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
,
980 SI_TRACKED_SPI_VS_OUT_CONFIG
,
981 shader
->ctx_reg
.ngg
.spi_vs_out_config
);
982 radeon_opt_set_context_reg2(sctx
, R_028708_SPI_SHADER_IDX_FORMAT
,
983 SI_TRACKED_SPI_SHADER_IDX_FORMAT
,
984 shader
->ctx_reg
.ngg
.spi_shader_idx_format
,
985 shader
->ctx_reg
.ngg
.spi_shader_pos_format
);
986 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
,
987 SI_TRACKED_PA_CL_VTE_CNTL
,
988 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
);
989 radeon_opt_set_context_reg(sctx
, R_028838_PA_CL_NGG_CNTL
,
990 SI_TRACKED_PA_CL_NGG_CNTL
,
991 shader
->ctx_reg
.ngg
.pa_cl_ngg_cntl
);
993 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
994 sctx
->context_roll
= true;
997 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context
*sctx
)
999 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1000 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1005 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1008 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context
*sctx
)
1010 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1011 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1016 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1017 SI_TRACKED_VGT_TF_PARAM
,
1018 shader
->vgt_tf_param
);
1020 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1023 static void gfx10_emit_shader_ngg_notess_gs(struct si_context
*sctx
)
1025 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1026 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1031 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
1032 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
1033 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
);
1035 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1038 static void gfx10_emit_shader_ngg_tess_gs(struct si_context
*sctx
)
1040 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1041 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1046 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
1047 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
1048 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
);
1049 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1050 SI_TRACKED_VGT_TF_PARAM
,
1051 shader
->vgt_tf_param
);
1053 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1056 static void si_set_ge_pc_alloc(struct si_screen
*sscreen
,
1057 struct si_pm4_state
*pm4
, bool culling
)
1059 si_pm4_set_reg(pm4
, R_030980_GE_PC_ALLOC
,
1060 S_030980_OVERSUB_EN(1) |
1061 S_030980_NUM_PC_LINES((culling
? 256 : 128) * sscreen
->info
.max_se
- 1));
1064 unsigned si_get_input_prim(const struct si_shader_selector
*gs
)
1066 if (gs
->type
== PIPE_SHADER_GEOMETRY
)
1067 return gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
1069 if (gs
->type
== PIPE_SHADER_TESS_EVAL
) {
1070 if (gs
->info
.properties
[TGSI_PROPERTY_TES_POINT_MODE
])
1071 return PIPE_PRIM_POINTS
;
1072 if (gs
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] == PIPE_PRIM_LINES
)
1073 return PIPE_PRIM_LINES
;
1074 return PIPE_PRIM_TRIANGLES
;
1077 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1078 return PIPE_PRIM_TRIANGLES
; /* worst case for all callers */
1082 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1085 static void gfx10_shader_ngg(struct si_screen
*sscreen
, struct si_shader
*shader
)
1087 const struct si_shader_selector
*gs_sel
= shader
->selector
;
1088 const struct tgsi_shader_info
*gs_info
= &gs_sel
->info
;
1089 enum pipe_shader_type gs_type
= shader
->selector
->type
;
1090 const struct si_shader_selector
*es_sel
=
1091 shader
->previous_stage_sel
? shader
->previous_stage_sel
: shader
->selector
;
1092 const struct tgsi_shader_info
*es_info
= &es_sel
->info
;
1093 enum pipe_shader_type es_type
= es_sel
->type
;
1094 unsigned num_user_sgprs
;
1095 unsigned nparams
, es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
1097 unsigned window_space
=
1098 gs_info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
1099 bool es_enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| es_info
->uses_primid
;
1100 unsigned gs_num_invocations
= MAX2(gs_sel
->gs_num_invocations
, 1);
1101 unsigned input_prim
= si_get_input_prim(gs_sel
);
1102 bool break_wave_at_eoi
= false;
1103 struct si_pm4_state
*pm4
= si_get_shader_pm4_state(shader
);
1107 if (es_type
== PIPE_SHADER_TESS_EVAL
) {
1108 pm4
->atom
.emit
= gs_type
== PIPE_SHADER_GEOMETRY
? gfx10_emit_shader_ngg_tess_gs
1109 : gfx10_emit_shader_ngg_tess_nogs
;
1111 pm4
->atom
.emit
= gs_type
== PIPE_SHADER_GEOMETRY
? gfx10_emit_shader_ngg_notess_gs
1112 : gfx10_emit_shader_ngg_notess_nogs
;
1115 va
= shader
->bo
->gpu_address
;
1116 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1118 if (es_type
== PIPE_SHADER_VERTEX
) {
1119 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
1120 es_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 3 : 0;
1122 if (es_info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
]) {
1123 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
1124 es_info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
1126 num_user_sgprs
= si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR
);
1129 assert(es_type
== PIPE_SHADER_TESS_EVAL
);
1130 es_vgpr_comp_cnt
= es_enable_prim_id
? 3 : 2;
1131 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
1133 if (es_enable_prim_id
|| gs_info
->uses_primid
)
1134 break_wave_at_eoi
= true;
1137 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1138 * VGPR[0:4] are always loaded.
1140 * Vertex shaders always need to load VGPR3, because they need to
1141 * pass edge flags for decomposed primitives (such as quads) to the PA
1142 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1144 if (gs_info
->uses_invocationid
|| gs_type
== PIPE_SHADER_VERTEX
)
1145 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID, edge flags. */
1146 else if (gs_info
->uses_primid
)
1147 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
1148 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
1149 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
1151 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
1153 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
1154 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
1155 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
1156 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) /
1157 (sscreen
->ge_wave_size
== 32 ? 8 : 4)) |
1158 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
1159 S_00B228_DX10_CLAMP(1) |
1160 S_00B228_MEM_ORDERED(1) |
1161 S_00B228_WGP_MODE(1) |
1162 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
));
1163 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
1164 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0) |
1165 S_00B22C_USER_SGPR(num_user_sgprs
) |
1166 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
1167 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5) |
1168 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
1169 S_00B22C_LDS_SIZE(shader
->config
.lds_size
));
1170 si_set_ge_pc_alloc(sscreen
, pm4
, false);
1172 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1173 shader
->ctx_reg
.ngg
.spi_vs_out_config
=
1174 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
1175 S_0286C4_NO_PC_EXPORT(shader
->info
.nr_param_exports
== 0);
1177 shader
->ctx_reg
.ngg
.spi_shader_idx_format
=
1178 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
);
1179 shader
->ctx_reg
.ngg
.spi_shader_pos_format
=
1180 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1181 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
1182 V_02870C_SPI_SHADER_4COMP
:
1183 V_02870C_SPI_SHADER_NONE
) |
1184 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
1185 V_02870C_SPI_SHADER_4COMP
:
1186 V_02870C_SPI_SHADER_NONE
) |
1187 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
1188 V_02870C_SPI_SHADER_4COMP
:
1189 V_02870C_SPI_SHADER_NONE
);
1191 shader
->ctx_reg
.ngg
.vgt_primitiveid_en
=
1192 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
1193 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id
);
1195 if (gs_type
== PIPE_SHADER_GEOMETRY
) {
1196 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
= es_sel
->esgs_itemsize
/ 4;
1197 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
= gs_sel
->gs_max_out_vertices
;
1199 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
= 1;
1202 if (es_type
== PIPE_SHADER_TESS_EVAL
)
1203 si_set_tesseval_regs(sscreen
, es_sel
, pm4
);
1205 shader
->ctx_reg
.ngg
.vgt_gs_onchip_cntl
=
1206 S_028A44_ES_VERTS_PER_SUBGRP(shader
->ngg
.hw_max_esverts
) |
1207 S_028A44_GS_PRIMS_PER_SUBGRP(shader
->ngg
.max_gsprims
) |
1208 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader
->ngg
.max_gsprims
* gs_num_invocations
);
1209 shader
->ctx_reg
.ngg
.ge_max_output_per_subgroup
=
1210 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader
->ngg
.max_out_verts
);
1211 shader
->ctx_reg
.ngg
.ge_ngg_subgrp_cntl
=
1212 S_028B4C_PRIM_AMP_FACTOR(shader
->ngg
.prim_amp_factor
) |
1213 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1214 shader
->ctx_reg
.ngg
.vgt_gs_instance_cnt
=
1215 S_028B90_CNT(gs_num_invocations
) |
1216 S_028B90_ENABLE(gs_num_invocations
> 1) |
1217 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1218 shader
->ngg
.max_vert_out_per_gs_instance
);
1220 /* Always output hw-generated edge flags and pass them via the prim
1221 * export to prevent drawing lines on internal edges of decomposed
1222 * primitives (such as quads) with polygon mode = lines. Only VS needs
1225 shader
->ctx_reg
.ngg
.pa_cl_ngg_cntl
=
1226 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type
== PIPE_SHADER_VERTEX
);
1229 S_03096C_PRIM_GRP_SIZE(shader
->ngg
.max_gsprims
) |
1230 S_03096C_VERT_GRP_SIZE(shader
->ngg
.hw_max_esverts
) |
1231 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
1234 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
=
1235 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1237 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
=
1238 S_028818_VTX_W0_FMT(1) |
1239 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1240 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1241 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1244 shader
->ctx_reg
.ngg
.vgt_reuse_off
=
1245 S_028AB4_REUSE_OFF(sscreen
->info
.family
== CHIP_NAVI10
&&
1246 sscreen
->info
.chip_external_rev
== 0x1 &&
1247 es_type
== PIPE_SHADER_TESS_EVAL
);
1250 static void si_emit_shader_vs(struct si_context
*sctx
)
1252 struct si_shader
*shader
= sctx
->queued
.named
.vs
->shader
;
1253 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1258 radeon_opt_set_context_reg(sctx
, R_028A40_VGT_GS_MODE
,
1259 SI_TRACKED_VGT_GS_MODE
,
1260 shader
->ctx_reg
.vs
.vgt_gs_mode
);
1261 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
,
1262 SI_TRACKED_VGT_PRIMITIVEID_EN
,
1263 shader
->ctx_reg
.vs
.vgt_primitiveid_en
);
1265 if (sctx
->chip_class
<= GFX8
) {
1266 radeon_opt_set_context_reg(sctx
, R_028AB4_VGT_REUSE_OFF
,
1267 SI_TRACKED_VGT_REUSE_OFF
,
1268 shader
->ctx_reg
.vs
.vgt_reuse_off
);
1271 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
,
1272 SI_TRACKED_SPI_VS_OUT_CONFIG
,
1273 shader
->ctx_reg
.vs
.spi_vs_out_config
);
1275 radeon_opt_set_context_reg(sctx
, R_02870C_SPI_SHADER_POS_FORMAT
,
1276 SI_TRACKED_SPI_SHADER_POS_FORMAT
,
1277 shader
->ctx_reg
.vs
.spi_shader_pos_format
);
1279 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
,
1280 SI_TRACKED_PA_CL_VTE_CNTL
,
1281 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
);
1283 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
1284 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1285 SI_TRACKED_VGT_TF_PARAM
,
1286 shader
->vgt_tf_param
);
1288 if (shader
->vgt_vertex_reuse_block_cntl
)
1289 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1290 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1291 shader
->vgt_vertex_reuse_block_cntl
);
1293 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1294 sctx
->context_roll
= true;
1298 * Compute the state for \p shader, which will run as a vertex shader on the
1301 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1302 * is the copy shader.
1304 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
1305 struct si_shader_selector
*gs
)
1307 const struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1308 struct si_pm4_state
*pm4
;
1309 unsigned num_user_sgprs
, vgpr_comp_cnt
;
1311 unsigned nparams
, oc_lds_en
;
1312 unsigned window_space
=
1313 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
1314 bool enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| info
->uses_primid
;
1316 pm4
= si_get_shader_pm4_state(shader
);
1320 pm4
->atom
.emit
= si_emit_shader_vs
;
1322 /* We always write VGT_GS_MODE in the VS state, because every switch
1323 * between different shader pipelines involving a different GS or no
1324 * GS at all involves a switch of the VS (different GS use different
1325 * copy shaders). On the other hand, when the API switches from a GS to
1326 * no GS and then back to the same GS used originally, the GS state is
1330 unsigned mode
= V_028A40_GS_OFF
;
1332 /* PrimID needs GS scenario A. */
1334 mode
= V_028A40_GS_SCENARIO_A
;
1336 shader
->ctx_reg
.vs
.vgt_gs_mode
= S_028A40_MODE(mode
);
1337 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= enable_prim_id
;
1339 shader
->ctx_reg
.vs
.vgt_gs_mode
= ac_vgt_gs_mode(gs
->gs_max_out_vertices
,
1340 sscreen
->info
.chip_class
);
1341 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= 0;
1344 if (sscreen
->info
.chip_class
<= GFX8
) {
1345 /* Reuse needs to be set off if we write oViewport. */
1346 shader
->ctx_reg
.vs
.vgt_reuse_off
=
1347 S_028AB4_REUSE_OFF(info
->writes_viewport_index
);
1350 va
= shader
->bo
->gpu_address
;
1351 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1354 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
1355 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
1356 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
1357 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1358 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1359 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1361 vgpr_comp_cnt
= enable_prim_id
? 2 : (shader
->info
.uses_instanceid
? 1 : 0);
1363 if (info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
]) {
1364 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
1365 info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
1367 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
1369 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
1370 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
1371 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
1373 unreachable("invalid shader selector type");
1375 /* VS is required to export at least one param. */
1376 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1377 shader
->ctx_reg
.vs
.spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
1379 if (sscreen
->info
.chip_class
>= GFX10
) {
1380 shader
->ctx_reg
.vs
.spi_vs_out_config
|=
1381 S_0286C4_NO_PC_EXPORT(shader
->info
.nr_param_exports
== 0);
1384 shader
->ctx_reg
.vs
.spi_shader_pos_format
=
1385 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1386 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
1387 V_02870C_SPI_SHADER_4COMP
:
1388 V_02870C_SPI_SHADER_NONE
) |
1389 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
1390 V_02870C_SPI_SHADER_4COMP
:
1391 V_02870C_SPI_SHADER_NONE
) |
1392 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
1393 V_02870C_SPI_SHADER_4COMP
:
1394 V_02870C_SPI_SHADER_NONE
);
1396 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
1398 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
1399 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, S_00B124_MEM_BASE(va
>> 40));
1400 if (sscreen
->info
.chip_class
>= GFX10
)
1401 si_set_ge_pc_alloc(sscreen
, pm4
, false);
1403 uint32_t rsrc1
= S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) /
1404 (sscreen
->ge_wave_size
== 32 ? 8 : 4)) |
1405 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
1406 S_00B128_DX10_CLAMP(1) |
1407 S_00B128_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
1408 S_00B128_FLOAT_MODE(shader
->config
.float_mode
);
1409 uint32_t rsrc2
= S_00B12C_USER_SGPR(num_user_sgprs
) |
1410 S_00B12C_OC_LDS_EN(oc_lds_en
) |
1411 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
1413 if (sscreen
->info
.chip_class
<= GFX9
) {
1414 rsrc1
|= S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
1415 rsrc2
|= S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
1416 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
1417 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
1418 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
1419 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
);
1422 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
, rsrc1
);
1423 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
, rsrc2
);
1426 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1427 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1429 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1430 S_028818_VTX_W0_FMT(1) |
1431 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1432 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1433 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1435 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
1436 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
1438 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
1441 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
1443 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
1444 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
1445 !!(info
->colors_read
& 0xf0);
1446 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
1447 (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
1449 assert(num_interp
<= 32);
1450 return MIN2(num_interp
, 32);
1453 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
1455 unsigned value
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
1456 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
1458 /* If the i-th target format is set, all previous target formats must
1459 * be non-zero to avoid hangs.
1461 for (i
= 0; i
< num_targets
; i
++)
1462 if (!(value
& (0xf << (i
* 4))))
1463 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
1468 static void si_emit_shader_ps(struct si_context
*sctx
)
1470 struct si_shader
*shader
= sctx
->queued
.named
.ps
->shader
;
1471 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1476 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1477 radeon_opt_set_context_reg2(sctx
, R_0286CC_SPI_PS_INPUT_ENA
,
1478 SI_TRACKED_SPI_PS_INPUT_ENA
,
1479 shader
->ctx_reg
.ps
.spi_ps_input_ena
,
1480 shader
->ctx_reg
.ps
.spi_ps_input_addr
);
1482 radeon_opt_set_context_reg(sctx
, R_0286E0_SPI_BARYC_CNTL
,
1483 SI_TRACKED_SPI_BARYC_CNTL
,
1484 shader
->ctx_reg
.ps
.spi_baryc_cntl
);
1485 radeon_opt_set_context_reg(sctx
, R_0286D8_SPI_PS_IN_CONTROL
,
1486 SI_TRACKED_SPI_PS_IN_CONTROL
,
1487 shader
->ctx_reg
.ps
.spi_ps_in_control
);
1489 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1490 radeon_opt_set_context_reg2(sctx
, R_028710_SPI_SHADER_Z_FORMAT
,
1491 SI_TRACKED_SPI_SHADER_Z_FORMAT
,
1492 shader
->ctx_reg
.ps
.spi_shader_z_format
,
1493 shader
->ctx_reg
.ps
.spi_shader_col_format
);
1495 radeon_opt_set_context_reg(sctx
, R_02823C_CB_SHADER_MASK
,
1496 SI_TRACKED_CB_SHADER_MASK
,
1497 shader
->ctx_reg
.ps
.cb_shader_mask
);
1499 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1500 sctx
->context_roll
= true;
1503 static void si_shader_ps(struct si_screen
*sscreen
, struct si_shader
*shader
)
1505 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1506 struct si_pm4_state
*pm4
;
1507 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
1508 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
1510 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
1512 /* we need to enable at least one of them, otherwise we hang the GPU */
1513 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1514 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1515 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1516 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
1517 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
1518 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1519 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
1520 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
1521 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1522 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
1523 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1524 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1525 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1526 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
1528 /* Validate interpolation optimization flags (read as implications). */
1529 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1530 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1531 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1532 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1533 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1534 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1535 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
1536 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
1537 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1538 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
1539 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
1540 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1541 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
1542 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1543 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1544 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
1545 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1546 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1548 /* Validate cases when the optimizations are off (read as implications). */
1549 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1550 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1551 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
1552 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1553 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1554 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
1556 pm4
= si_get_shader_pm4_state(shader
);
1560 pm4
->atom
.emit
= si_emit_shader_ps
;
1562 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1564 * 0 -> Position = pixel center
1565 * 1 -> Position = pixel centroid
1566 * 2 -> Position = at sample position
1568 * From GLSL 4.5 specification, section 7.1:
1569 * "The variable gl_FragCoord is available as an input variable from
1570 * within fragment shaders and it holds the window relative coordinates
1571 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1572 * value can be for any location within the pixel, or one of the
1573 * fragment samples. The use of centroid does not further restrict
1574 * this value to be inside the current primitive."
1576 * Meaning that centroid has no effect and we can return anything within
1577 * the pixel. Thus, return the value at sample position, because that's
1578 * the most accurate one shaders can get.
1580 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1582 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
1583 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
1584 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
1586 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
1587 cb_shader_mask
= ac_get_cb_shader_mask(spi_shader_col_format
);
1589 /* Ensure that some export memory is always allocated, for two reasons:
1591 * 1) Correctness: The hardware ignores the EXEC mask if no export
1592 * memory is allocated, so KILL and alpha test do not work correctly
1594 * 2) Performance: Every shader needs at least a NULL export, even when
1595 * it writes no color/depth output. The NULL export instruction
1596 * stalls without this setting.
1598 * Don't add this to CB_SHADER_MASK.
1600 * GFX10 supports pixel shaders without exports by setting both
1601 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1602 * instructions if any are present.
1604 if ((sscreen
->info
.chip_class
<= GFX9
||
1606 shader
->key
.part
.ps
.epilog
.alpha_func
!= PIPE_FUNC_ALWAYS
) &&
1607 !spi_shader_col_format
&&
1608 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
1609 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
1611 shader
->ctx_reg
.ps
.spi_ps_input_ena
= input_ena
;
1612 shader
->ctx_reg
.ps
.spi_ps_input_addr
= shader
->config
.spi_ps_input_addr
;
1614 /* Set interpolation controls. */
1615 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
)) |
1616 S_0286D8_PS_W32_EN(sscreen
->ps_wave_size
== 32);
1618 shader
->ctx_reg
.ps
.spi_baryc_cntl
= spi_baryc_cntl
;
1619 shader
->ctx_reg
.ps
.spi_ps_in_control
= spi_ps_in_control
;
1620 shader
->ctx_reg
.ps
.spi_shader_z_format
=
1621 ac_get_spi_shader_z_format(info
->writes_z
,
1622 info
->writes_stencil
,
1623 info
->writes_samplemask
);
1624 shader
->ctx_reg
.ps
.spi_shader_col_format
= spi_shader_col_format
;
1625 shader
->ctx_reg
.ps
.cb_shader_mask
= cb_shader_mask
;
1627 va
= shader
->bo
->gpu_address
;
1628 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1629 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
1630 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, S_00B024_MEM_BASE(va
>> 40));
1633 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) /
1634 (sscreen
->ps_wave_size
== 32 ? 8 : 4)) |
1635 S_00B028_DX10_CLAMP(1) |
1636 S_00B028_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
1637 S_00B028_FLOAT_MODE(shader
->config
.float_mode
);
1639 if (sscreen
->info
.chip_class
< GFX10
) {
1640 rsrc1
|= S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
1643 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
, rsrc1
);
1644 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
1645 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
1646 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
1647 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1650 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
1651 struct si_shader
*shader
)
1653 switch (shader
->selector
->type
) {
1654 case PIPE_SHADER_VERTEX
:
1655 if (shader
->key
.as_ls
)
1656 si_shader_ls(sscreen
, shader
);
1657 else if (shader
->key
.as_es
)
1658 si_shader_es(sscreen
, shader
);
1659 else if (shader
->key
.as_ngg
)
1660 gfx10_shader_ngg(sscreen
, shader
);
1662 si_shader_vs(sscreen
, shader
, NULL
);
1664 case PIPE_SHADER_TESS_CTRL
:
1665 si_shader_hs(sscreen
, shader
);
1667 case PIPE_SHADER_TESS_EVAL
:
1668 if (shader
->key
.as_es
)
1669 si_shader_es(sscreen
, shader
);
1670 else if (shader
->key
.as_ngg
)
1671 gfx10_shader_ngg(sscreen
, shader
);
1673 si_shader_vs(sscreen
, shader
, NULL
);
1675 case PIPE_SHADER_GEOMETRY
:
1676 if (shader
->key
.as_ngg
)
1677 gfx10_shader_ngg(sscreen
, shader
);
1679 si_shader_gs(sscreen
, shader
);
1681 case PIPE_SHADER_FRAGMENT
:
1682 si_shader_ps(sscreen
, shader
);
1689 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
1691 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1692 if (sctx
->queued
.named
.dsa
)
1693 return sctx
->queued
.named
.dsa
->alpha_func
;
1695 return PIPE_FUNC_ALWAYS
;
1698 void si_shader_selector_key_vs(struct si_context
*sctx
,
1699 struct si_shader_selector
*vs
,
1700 struct si_shader_key
*key
,
1701 struct si_vs_prolog_bits
*prolog_key
)
1703 if (!sctx
->vertex_elements
||
1704 vs
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
])
1707 struct si_vertex_elements
*elts
= sctx
->vertex_elements
;
1709 prolog_key
->instance_divisor_is_one
= elts
->instance_divisor_is_one
;
1710 prolog_key
->instance_divisor_is_fetched
= elts
->instance_divisor_is_fetched
;
1711 prolog_key
->unpack_instance_id_from_vertex_id
=
1712 sctx
->prim_discard_cs_instancing
;
1714 /* Prefer a monolithic shader to allow scheduling divisions around
1716 if (prolog_key
->instance_divisor_is_fetched
)
1717 key
->opt
.prefer_mono
= 1;
1719 unsigned count
= MIN2(vs
->info
.num_inputs
, elts
->count
);
1720 unsigned count_mask
= (1 << count
) - 1;
1721 unsigned fix
= elts
->fix_fetch_always
& count_mask
;
1722 unsigned opencode
= elts
->fix_fetch_opencode
& count_mask
;
1724 if (sctx
->vertex_buffer_unaligned
& elts
->vb_alignment_check_mask
) {
1725 uint32_t mask
= elts
->fix_fetch_unaligned
& count_mask
;
1727 unsigned i
= u_bit_scan(&mask
);
1728 unsigned log_hw_load_size
= 1 + ((elts
->hw_load_is_dword
>> i
) & 1);
1729 unsigned vbidx
= elts
->vertex_buffer_index
[i
];
1730 struct pipe_vertex_buffer
*vb
= &sctx
->vertex_buffer
[vbidx
];
1731 unsigned align_mask
= (1 << log_hw_load_size
) - 1;
1732 if (vb
->buffer_offset
& align_mask
||
1733 vb
->stride
& align_mask
) {
1741 unsigned i
= u_bit_scan(&fix
);
1742 key
->mono
.vs_fix_fetch
[i
].bits
= elts
->fix_fetch
[i
];
1744 key
->mono
.vs_fetch_opencode
= opencode
;
1747 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
,
1748 struct si_shader_selector
*vs
,
1749 struct si_shader_key
*key
)
1751 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1753 key
->opt
.clip_disable
=
1754 sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
1755 (vs
->info
.clipdist_writemask
||
1756 vs
->info
.writes_clipvertex
) &&
1757 !vs
->info
.culldist_writemask
;
1759 /* Find out if PS is disabled. */
1760 bool ps_disabled
= true;
1762 bool ps_modifies_zs
= ps
->info
.uses_kill
||
1763 ps
->info
.writes_z
||
1764 ps
->info
.writes_stencil
||
1765 ps
->info
.writes_samplemask
||
1766 sctx
->queued
.named
.blend
->alpha_to_coverage
||
1767 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
1768 unsigned ps_colormask
= si_get_total_colormask(sctx
);
1770 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
1773 !ps
->info
.writes_memory
);
1776 /* Find out which VS outputs aren't used by the PS. */
1777 uint64_t outputs_written
= vs
->outputs_written_before_ps
;
1778 uint64_t inputs_read
= 0;
1780 /* Ignore outputs that are not passed from VS to PS. */
1781 outputs_written
&= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION
, 0, true)) |
1782 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE
, 0, true)) |
1783 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX
, 0, true)));
1786 inputs_read
= ps
->inputs_read
;
1789 uint64_t linked
= outputs_written
& inputs_read
;
1791 key
->opt
.kill_outputs
= ~linked
& outputs_written
;
1794 /* Compute the key for the hw shader variant */
1795 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
1796 struct si_shader_selector
*sel
,
1797 union si_vgt_stages_key stages_key
,
1798 struct si_shader_key
*key
)
1800 struct si_context
*sctx
= (struct si_context
*)ctx
;
1802 memset(key
, 0, sizeof(*key
));
1804 switch (sel
->type
) {
1805 case PIPE_SHADER_VERTEX
:
1806 si_shader_selector_key_vs(sctx
, sel
, key
, &key
->part
.vs
.prolog
);
1808 if (sctx
->tes_shader
.cso
)
1810 else if (sctx
->gs_shader
.cso
)
1813 key
->as_ngg
= stages_key
.u
.ngg
;
1814 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1816 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1817 key
->mono
.u
.vs_export_prim_id
= 1;
1820 case PIPE_SHADER_TESS_CTRL
:
1821 if (sctx
->chip_class
>= GFX9
) {
1822 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1823 key
, &key
->part
.tcs
.ls_prolog
);
1824 key
->part
.tcs
.ls
= sctx
->vs_shader
.cso
;
1826 /* When the LS VGPR fix is needed, monolithic shaders
1828 * - avoid initializing EXEC in both the LS prolog
1829 * and the LS main part when !vs_needs_prolog
1830 * - remove the fixup for unused input VGPRs
1832 key
->part
.tcs
.ls_prolog
.ls_vgpr_fix
= sctx
->ls_vgpr_fix
;
1834 /* The LS output / HS input layout can be communicated
1835 * directly instead of via user SGPRs for merged LS-HS.
1836 * The LS VGPR fix prefers this too.
1838 key
->opt
.prefer_mono
= 1;
1841 key
->part
.tcs
.epilog
.prim_mode
=
1842 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1843 key
->part
.tcs
.epilog
.invoc0_tess_factors_are_def
=
1844 sel
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1845 key
->part
.tcs
.epilog
.tes_reads_tess_factors
=
1846 sctx
->tes_shader
.cso
->info
.reads_tess_factors
;
1848 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
1849 key
->mono
.u
.ff_tcs_inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
1851 case PIPE_SHADER_TESS_EVAL
:
1852 key
->as_ngg
= stages_key
.u
.ngg
;
1854 if (sctx
->gs_shader
.cso
)
1857 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1859 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1860 key
->mono
.u
.vs_export_prim_id
= 1;
1863 case PIPE_SHADER_GEOMETRY
:
1864 if (sctx
->chip_class
>= GFX9
) {
1865 if (sctx
->tes_shader
.cso
) {
1866 key
->part
.gs
.es
= sctx
->tes_shader
.cso
;
1868 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1869 key
, &key
->part
.gs
.vs_prolog
);
1870 key
->part
.gs
.es
= sctx
->vs_shader
.cso
;
1871 key
->part
.gs
.prolog
.gfx9_prev_is_vs
= 1;
1874 key
->as_ngg
= stages_key
.u
.ngg
;
1876 /* Merged ES-GS can have unbalanced wave usage.
1878 * ES threads are per-vertex, while GS threads are
1879 * per-primitive. So without any amplification, there
1880 * are fewer GS threads than ES threads, which can result
1881 * in empty (no-op) GS waves. With too much amplification,
1882 * there are more GS threads than ES threads, which
1883 * can result in empty (no-op) ES waves.
1885 * Non-monolithic shaders are implemented by setting EXEC
1886 * at the beginning of shader parts, and don't jump to
1887 * the end if EXEC is 0.
1889 * Monolithic shaders use conditional blocks, so they can
1890 * jump and skip empty waves of ES or GS. So set this to
1891 * always use optimized variants, which are monolithic.
1893 key
->opt
.prefer_mono
= 1;
1895 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
1897 case PIPE_SHADER_FRAGMENT
: {
1898 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1899 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1901 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
1902 sel
->info
.colors_written
== 0x1)
1903 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
1905 /* Select the shader color format based on whether
1906 * blending or alpha are needed.
1908 key
->part
.ps
.epilog
.spi_shader_col_format
=
1909 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1910 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
1911 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1912 sctx
->framebuffer
.spi_shader_col_format_blend
) |
1913 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1914 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
1915 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1916 sctx
->framebuffer
.spi_shader_col_format
);
1917 key
->part
.ps
.epilog
.spi_shader_col_format
&= blend
->cb_target_enabled_4bit
;
1919 /* The output for dual source blending should have
1920 * the same format as the first output.
1922 if (blend
->dual_src_blend
) {
1923 key
->part
.ps
.epilog
.spi_shader_col_format
|=
1924 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
1927 /* If alpha-to-coverage is enabled, we have to export alpha
1928 * even if there is no color buffer.
1930 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) &&
1931 blend
->alpha_to_coverage
)
1932 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
1934 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1935 * to the range supported by the type if a channel has less
1936 * than 16 bits and the export format is 16_ABGR.
1938 if (sctx
->chip_class
<= GFX7
&& sctx
->family
!= CHIP_HAWAII
) {
1939 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
1940 key
->part
.ps
.epilog
.color_is_int10
= sctx
->framebuffer
.color_is_int10
;
1943 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1944 if (!key
->part
.ps
.epilog
.last_cbuf
) {
1945 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
1946 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
1947 key
->part
.ps
.epilog
.color_is_int10
&= sel
->info
.colors_written
;
1950 bool is_poly
= !util_prim_is_points_or_lines(sctx
->current_rast_prim
);
1951 bool is_line
= util_prim_is_lines(sctx
->current_rast_prim
);
1953 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
1954 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
1956 key
->part
.ps
.epilog
.alpha_to_one
= blend
->alpha_to_one
&&
1957 rs
->multisample_enable
;
1959 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
1960 key
->part
.ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
1961 (is_line
&& rs
->line_smooth
)) &&
1962 sctx
->framebuffer
.nr_samples
<= 1;
1963 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
1965 if (sctx
->ps_iter_samples
> 1 &&
1966 sel
->info
.reads_samplemask
) {
1967 key
->part
.ps
.prolog
.samplemask_log_ps_iter
=
1968 util_logbase2(sctx
->ps_iter_samples
);
1971 if (rs
->force_persample_interp
&&
1972 rs
->multisample_enable
&&
1973 sctx
->framebuffer
.nr_samples
> 1 &&
1974 sctx
->ps_iter_samples
> 1) {
1975 key
->part
.ps
.prolog
.force_persp_sample_interp
=
1976 sel
->info
.uses_persp_center
||
1977 sel
->info
.uses_persp_centroid
;
1979 key
->part
.ps
.prolog
.force_linear_sample_interp
=
1980 sel
->info
.uses_linear_center
||
1981 sel
->info
.uses_linear_centroid
;
1982 } else if (rs
->multisample_enable
&&
1983 sctx
->framebuffer
.nr_samples
> 1) {
1984 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
1985 sel
->info
.uses_persp_center
&&
1986 sel
->info
.uses_persp_centroid
;
1987 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
1988 sel
->info
.uses_linear_center
&&
1989 sel
->info
.uses_linear_centroid
;
1991 /* Make sure SPI doesn't compute more than 1 pair
1992 * of (i,j), which is the optimization here. */
1993 key
->part
.ps
.prolog
.force_persp_center_interp
=
1994 sel
->info
.uses_persp_center
+
1995 sel
->info
.uses_persp_centroid
+
1996 sel
->info
.uses_persp_sample
> 1;
1998 key
->part
.ps
.prolog
.force_linear_center_interp
=
1999 sel
->info
.uses_linear_center
+
2000 sel
->info
.uses_linear_centroid
+
2001 sel
->info
.uses_linear_sample
> 1;
2003 if (sel
->info
.uses_persp_opcode_interp_sample
||
2004 sel
->info
.uses_linear_opcode_interp_sample
)
2005 key
->mono
.u
.ps
.interpolate_at_sample_force_center
= 1;
2008 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
2010 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2011 if (sctx
->ps_uses_fbfetch
&& !sctx
->blitter
->running
) {
2012 struct pipe_surface
*cb0
= sctx
->framebuffer
.state
.cbufs
[0];
2013 struct pipe_resource
*tex
= cb0
->texture
;
2015 /* 1D textures are allocated and used as 2D on GFX9. */
2016 key
->mono
.u
.ps
.fbfetch_msaa
= sctx
->framebuffer
.nr_samples
> 1;
2017 key
->mono
.u
.ps
.fbfetch_is_1D
= sctx
->chip_class
!= GFX9
&&
2018 (tex
->target
== PIPE_TEXTURE_1D
||
2019 tex
->target
== PIPE_TEXTURE_1D_ARRAY
);
2020 key
->mono
.u
.ps
.fbfetch_layered
= tex
->target
== PIPE_TEXTURE_1D_ARRAY
||
2021 tex
->target
== PIPE_TEXTURE_2D_ARRAY
||
2022 tex
->target
== PIPE_TEXTURE_CUBE
||
2023 tex
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
2024 tex
->target
== PIPE_TEXTURE_3D
;
2032 if (unlikely(sctx
->screen
->debug_flags
& DBG(NO_OPT_VARIANT
)))
2033 memset(&key
->opt
, 0, sizeof(key
->opt
));
2036 static void si_build_shader_variant(struct si_shader
*shader
,
2040 struct si_shader_selector
*sel
= shader
->selector
;
2041 struct si_screen
*sscreen
= sel
->screen
;
2042 struct ac_llvm_compiler
*compiler
;
2043 struct pipe_debug_callback
*debug
= &shader
->compiler_ctx_state
.debug
;
2045 if (thread_index
>= 0) {
2047 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler_lowp
));
2048 compiler
= &sscreen
->compiler_lowp
[thread_index
];
2050 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
2051 compiler
= &sscreen
->compiler
[thread_index
];
2056 assert(!low_priority
);
2057 compiler
= shader
->compiler_ctx_state
.compiler
;
2060 if (unlikely(!si_shader_create(sscreen
, compiler
, shader
, debug
))) {
2061 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2063 shader
->compilation_failed
= true;
2067 if (shader
->compiler_ctx_state
.is_debug_context
) {
2068 FILE *f
= open_memstream(&shader
->shader_log
,
2069 &shader
->shader_log_size
);
2071 si_shader_dump(sscreen
, shader
, NULL
, f
, false);
2076 si_shader_init_pm4_state(sscreen
, shader
);
2079 static void si_build_shader_variant_low_priority(void *job
, int thread_index
)
2081 struct si_shader
*shader
= (struct si_shader
*)job
;
2083 assert(thread_index
>= 0);
2085 si_build_shader_variant(shader
, thread_index
, true);
2088 static const struct si_shader_key zeroed
;
2090 static bool si_check_missing_main_part(struct si_screen
*sscreen
,
2091 struct si_shader_selector
*sel
,
2092 struct si_compiler_ctx_state
*compiler_state
,
2093 struct si_shader_key
*key
)
2095 struct si_shader
**mainp
= si_get_main_shader_part(sel
, key
);
2098 struct si_shader
*main_part
= CALLOC_STRUCT(si_shader
);
2103 /* We can leave the fence as permanently signaled because the
2104 * main part becomes visible globally only after it has been
2106 util_queue_fence_init(&main_part
->ready
);
2108 main_part
->selector
= sel
;
2109 main_part
->key
.as_es
= key
->as_es
;
2110 main_part
->key
.as_ls
= key
->as_ls
;
2111 main_part
->key
.as_ngg
= key
->as_ngg
;
2112 main_part
->is_monolithic
= false;
2114 if (si_compile_tgsi_shader(sscreen
, compiler_state
->compiler
,
2115 main_part
, &compiler_state
->debug
) != 0) {
2125 * Select a shader variant according to the shader key.
2127 * \param optimized_or_none If the key describes an optimized shader variant and
2128 * the compilation isn't finished, don't select any
2129 * shader and return an error.
2131 int si_shader_select_with_key(struct si_screen
*sscreen
,
2132 struct si_shader_ctx_state
*state
,
2133 struct si_compiler_ctx_state
*compiler_state
,
2134 struct si_shader_key
*key
,
2136 bool optimized_or_none
)
2138 struct si_shader_selector
*sel
= state
->cso
;
2139 struct si_shader_selector
*previous_stage_sel
= NULL
;
2140 struct si_shader
*current
= state
->current
;
2141 struct si_shader
*iter
, *shader
= NULL
;
2144 /* Check if we don't need to change anything.
2145 * This path is also used for most shaders that don't need multiple
2146 * variants, it will cost just a computation of the key and this
2148 if (likely(current
&&
2149 memcmp(¤t
->key
, key
, sizeof(*key
)) == 0)) {
2150 if (unlikely(!util_queue_fence_is_signalled(¤t
->ready
))) {
2151 if (current
->is_optimized
) {
2152 if (optimized_or_none
)
2155 memset(&key
->opt
, 0, sizeof(key
->opt
));
2156 goto current_not_ready
;
2159 util_queue_fence_wait(¤t
->ready
);
2162 return current
->compilation_failed
? -1 : 0;
2166 /* This must be done before the mutex is locked, because async GS
2167 * compilation calls this function too, and therefore must enter
2170 * Only wait if we are in a draw call. Don't wait if we are
2171 * in a compiler thread.
2173 if (thread_index
< 0)
2174 util_queue_fence_wait(&sel
->ready
);
2176 mtx_lock(&sel
->mutex
);
2178 /* Find the shader variant. */
2179 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
2180 /* Don't check the "current" shader. We checked it above. */
2181 if (current
!= iter
&&
2182 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
2183 mtx_unlock(&sel
->mutex
);
2185 if (unlikely(!util_queue_fence_is_signalled(&iter
->ready
))) {
2186 /* If it's an optimized shader and its compilation has
2187 * been started but isn't done, use the unoptimized
2188 * shader so as not to cause a stall due to compilation.
2190 if (iter
->is_optimized
) {
2191 if (optimized_or_none
)
2193 memset(&key
->opt
, 0, sizeof(key
->opt
));
2197 util_queue_fence_wait(&iter
->ready
);
2200 if (iter
->compilation_failed
) {
2201 return -1; /* skip the draw call */
2204 state
->current
= iter
;
2209 /* Build a new shader. */
2210 shader
= CALLOC_STRUCT(si_shader
);
2212 mtx_unlock(&sel
->mutex
);
2216 util_queue_fence_init(&shader
->ready
);
2218 shader
->selector
= sel
;
2220 shader
->compiler_ctx_state
= *compiler_state
;
2222 /* If this is a merged shader, get the first shader's selector. */
2223 if (sscreen
->info
.chip_class
>= GFX9
) {
2224 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
2225 previous_stage_sel
= key
->part
.tcs
.ls
;
2226 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
2227 previous_stage_sel
= key
->part
.gs
.es
;
2229 /* We need to wait for the previous shader. */
2230 if (previous_stage_sel
&& thread_index
< 0)
2231 util_queue_fence_wait(&previous_stage_sel
->ready
);
2234 bool is_pure_monolithic
=
2235 sscreen
->use_monolithic_shaders
||
2236 memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
2238 /* Compile the main shader part if it doesn't exist. This can happen
2239 * if the initial guess was wrong.
2241 * The prim discard CS doesn't need the main shader part.
2243 if (!is_pure_monolithic
&&
2244 !key
->opt
.vs_as_prim_discard_cs
) {
2247 /* Make sure the main shader part is present. This is needed
2248 * for shaders that can be compiled as VS, LS, or ES, and only
2249 * one of them is compiled at creation.
2251 * It is also needed for GS, which can be compiled as non-NGG
2254 * For merged shaders, check that the starting shader's main
2257 if (previous_stage_sel
) {
2258 struct si_shader_key shader1_key
= zeroed
;
2260 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
2261 shader1_key
.as_ls
= 1;
2262 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
2263 shader1_key
.as_es
= 1;
2267 if (sel
->type
== PIPE_SHADER_GEOMETRY
&&
2268 previous_stage_sel
->type
== PIPE_SHADER_TESS_EVAL
)
2269 shader1_key
.as_ngg
= key
->as_ngg
;
2271 mtx_lock(&previous_stage_sel
->mutex
);
2272 ok
= si_check_missing_main_part(sscreen
,
2274 compiler_state
, &shader1_key
);
2275 mtx_unlock(&previous_stage_sel
->mutex
);
2279 ok
= si_check_missing_main_part(sscreen
, sel
,
2280 compiler_state
, key
);
2285 mtx_unlock(&sel
->mutex
);
2286 return -ENOMEM
; /* skip the draw call */
2290 /* Keep the reference to the 1st shader of merged shaders, so that
2291 * Gallium can't destroy it before we destroy the 2nd shader.
2293 * Set sctx = NULL, because it's unused if we're not releasing
2294 * the shader, and we don't have any sctx here.
2296 si_shader_selector_reference(NULL
, &shader
->previous_stage_sel
,
2297 previous_stage_sel
);
2299 /* Monolithic-only shaders don't make a distinction between optimized
2300 * and unoptimized. */
2301 shader
->is_monolithic
=
2302 is_pure_monolithic
||
2303 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
2305 /* The prim discard CS is always optimized. */
2306 shader
->is_optimized
=
2307 (!is_pure_monolithic
|| key
->opt
.vs_as_prim_discard_cs
) &&
2308 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
2310 /* If it's an optimized shader, compile it asynchronously. */
2311 if (shader
->is_optimized
&& thread_index
< 0) {
2312 /* Compile it asynchronously. */
2313 util_queue_add_job(&sscreen
->shader_compiler_queue_low_priority
,
2314 shader
, &shader
->ready
,
2315 si_build_shader_variant_low_priority
, NULL
);
2317 /* Add only after the ready fence was reset, to guard against a
2318 * race with si_bind_XX_shader. */
2319 if (!sel
->last_variant
) {
2320 sel
->first_variant
= shader
;
2321 sel
->last_variant
= shader
;
2323 sel
->last_variant
->next_variant
= shader
;
2324 sel
->last_variant
= shader
;
2327 /* Use the default (unoptimized) shader for now. */
2328 memset(&key
->opt
, 0, sizeof(key
->opt
));
2329 mtx_unlock(&sel
->mutex
);
2331 if (sscreen
->options
.sync_compile
)
2332 util_queue_fence_wait(&shader
->ready
);
2334 if (optimized_or_none
)
2339 /* Reset the fence before adding to the variant list. */
2340 util_queue_fence_reset(&shader
->ready
);
2342 if (!sel
->last_variant
) {
2343 sel
->first_variant
= shader
;
2344 sel
->last_variant
= shader
;
2346 sel
->last_variant
->next_variant
= shader
;
2347 sel
->last_variant
= shader
;
2350 mtx_unlock(&sel
->mutex
);
2352 assert(!shader
->is_optimized
);
2353 si_build_shader_variant(shader
, thread_index
, false);
2355 util_queue_fence_signal(&shader
->ready
);
2357 if (!shader
->compilation_failed
)
2358 state
->current
= shader
;
2360 return shader
->compilation_failed
? -1 : 0;
2363 static int si_shader_select(struct pipe_context
*ctx
,
2364 struct si_shader_ctx_state
*state
,
2365 union si_vgt_stages_key stages_key
,
2366 struct si_compiler_ctx_state
*compiler_state
)
2368 struct si_context
*sctx
= (struct si_context
*)ctx
;
2369 struct si_shader_key key
;
2371 si_shader_selector_key(ctx
, state
->cso
, stages_key
, &key
);
2372 return si_shader_select_with_key(sctx
->screen
, state
, compiler_state
,
2376 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
2378 struct si_shader_key
*key
)
2380 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
2382 switch (info
->processor
) {
2383 case PIPE_SHADER_VERTEX
:
2384 switch (next_shader
) {
2385 case PIPE_SHADER_GEOMETRY
:
2388 case PIPE_SHADER_TESS_CTRL
:
2389 case PIPE_SHADER_TESS_EVAL
:
2393 /* If POSITION isn't written, it can only be a HW VS
2394 * if streamout is used. If streamout isn't used,
2395 * assume that it's a HW LS. (the next shader is TCS)
2396 * This heuristic is needed for separate shader objects.
2398 if (!info
->writes_position
&& !streamout
)
2403 case PIPE_SHADER_TESS_EVAL
:
2404 if (next_shader
== PIPE_SHADER_GEOMETRY
||
2405 !info
->writes_position
)
2412 * Compile the main shader part or the monolithic shader as part of
2413 * si_shader_selector initialization. Since it can be done asynchronously,
2414 * there is no way to report compile failures to applications.
2416 static void si_init_shader_selector_async(void *job
, int thread_index
)
2418 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
2419 struct si_screen
*sscreen
= sel
->screen
;
2420 struct ac_llvm_compiler
*compiler
;
2421 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
2423 assert(!debug
->debug_message
|| debug
->async
);
2424 assert(thread_index
>= 0);
2425 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
2426 compiler
= &sscreen
->compiler
[thread_index
];
2429 /* TODO: GS always sets wave size = default. Legacy GS will have
2430 * incorrect subgroup_size and ballot_bit_size. */
2431 si_lower_nir(sel
, si_get_wave_size(sscreen
, sel
->type
, true, false));
2434 /* Compile the main shader part for use with a prolog and/or epilog.
2435 * If this fails, the driver will try to compile a monolithic shader
2438 if (!sscreen
->use_monolithic_shaders
) {
2439 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
2440 void *ir_binary
= NULL
;
2443 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
2447 /* We can leave the fence signaled because use of the default
2448 * main part is guarded by the selector's ready fence. */
2449 util_queue_fence_init(&shader
->ready
);
2451 shader
->selector
= sel
;
2452 shader
->is_monolithic
= false;
2453 si_parse_next_shader_property(&sel
->info
,
2454 sel
->so
.num_outputs
!= 0,
2456 if (sscreen
->info
.chip_class
>= GFX10
&&
2457 ((sel
->type
== PIPE_SHADER_VERTEX
&&
2458 !shader
->key
.as_ls
&& !shader
->key
.as_es
) ||
2459 sel
->type
== PIPE_SHADER_TESS_EVAL
||
2460 sel
->type
== PIPE_SHADER_GEOMETRY
))
2461 shader
->key
.as_ngg
= 1;
2463 if (sel
->tokens
|| sel
->nir
)
2464 ir_binary
= si_get_ir_binary(sel
);
2466 /* Try to load the shader from the shader cache. */
2467 mtx_lock(&sscreen
->shader_cache_mutex
);
2470 si_shader_cache_load_shader(sscreen
, ir_binary
, shader
)) {
2471 mtx_unlock(&sscreen
->shader_cache_mutex
);
2472 si_shader_dump_stats_for_shader_db(sscreen
, shader
, debug
);
2474 mtx_unlock(&sscreen
->shader_cache_mutex
);
2476 /* Compile the shader if it hasn't been loaded from the cache. */
2477 if (si_compile_tgsi_shader(sscreen
, compiler
, shader
,
2481 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
2486 mtx_lock(&sscreen
->shader_cache_mutex
);
2487 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
, shader
, true))
2489 mtx_unlock(&sscreen
->shader_cache_mutex
);
2493 *si_get_main_shader_part(sel
, &shader
->key
) = shader
;
2495 /* Unset "outputs_written" flags for outputs converted to
2496 * DEFAULT_VAL, so that later inter-shader optimizations don't
2497 * try to eliminate outputs that don't exist in the final
2500 * This is only done if non-monolithic shaders are enabled.
2502 if ((sel
->type
== PIPE_SHADER_VERTEX
||
2503 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
2504 !shader
->key
.as_ls
&&
2505 !shader
->key
.as_es
) {
2508 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2509 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
2511 if (offset
<= AC_EXP_PARAM_OFFSET_31
)
2514 unsigned name
= sel
->info
.output_semantic_name
[i
];
2515 unsigned index
= sel
->info
.output_semantic_index
[i
];
2519 case TGSI_SEMANTIC_GENERIC
:
2520 /* don't process indices the function can't handle */
2521 if (index
>= SI_MAX_IO_GENERIC
)
2525 id
= si_shader_io_get_unique_index(name
, index
, true);
2526 sel
->outputs_written_before_ps
&= ~(1ull << id
);
2528 case TGSI_SEMANTIC_POSITION
: /* ignore these */
2529 case TGSI_SEMANTIC_PSIZE
:
2530 case TGSI_SEMANTIC_CLIPVERTEX
:
2531 case TGSI_SEMANTIC_EDGEFLAG
:
2538 /* The GS copy shader is always pre-compiled. */
2539 if (sel
->type
== PIPE_SHADER_GEOMETRY
&&
2540 (sscreen
->info
.chip_class
<= GFX9
|| sel
->tess_turns_off_ngg
)) {
2541 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, compiler
, sel
, debug
);
2542 if (!sel
->gs_copy_shader
) {
2543 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
2547 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
2551 void si_schedule_initial_compile(struct si_context
*sctx
, unsigned processor
,
2552 struct util_queue_fence
*ready_fence
,
2553 struct si_compiler_ctx_state
*compiler_ctx_state
,
2554 void *job
, util_queue_execute_func execute
)
2556 util_queue_fence_init(ready_fence
);
2558 struct util_async_debug_callback async_debug
;
2560 (sctx
->debug
.debug_message
&& !sctx
->debug
.async
) ||
2562 si_can_dump_shader(sctx
->screen
, processor
);
2565 u_async_debug_init(&async_debug
);
2566 compiler_ctx_state
->debug
= async_debug
.base
;
2569 util_queue_add_job(&sctx
->screen
->shader_compiler_queue
, job
,
2570 ready_fence
, execute
, NULL
);
2573 util_queue_fence_wait(ready_fence
);
2574 u_async_debug_drain(&async_debug
, &sctx
->debug
);
2575 u_async_debug_cleanup(&async_debug
);
2578 if (sctx
->screen
->options
.sync_compile
)
2579 util_queue_fence_wait(ready_fence
);
2582 /* Return descriptor slot usage masks from the given shader info. */
2583 void si_get_active_slot_masks(const struct tgsi_shader_info
*info
,
2584 uint32_t *const_and_shader_buffers
,
2585 uint64_t *samplers_and_images
)
2587 unsigned start
, num_shaderbufs
, num_constbufs
, num_images
, num_samplers
;
2589 num_shaderbufs
= util_last_bit(info
->shader_buffers_declared
);
2590 num_constbufs
= util_last_bit(info
->const_buffers_declared
);
2591 /* two 8-byte images share one 16-byte slot */
2592 num_images
= align(util_last_bit(info
->images_declared
), 2);
2593 num_samplers
= util_last_bit(info
->samplers_declared
);
2595 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2596 start
= si_get_shaderbuf_slot(num_shaderbufs
- 1);
2597 *const_and_shader_buffers
=
2598 u_bit_consecutive(start
, num_shaderbufs
+ num_constbufs
);
2600 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2601 start
= si_get_image_slot(num_images
- 1) / 2;
2602 *samplers_and_images
=
2603 u_bit_consecutive64(start
, num_images
/ 2 + num_samplers
);
2606 static void *si_create_shader_selector(struct pipe_context
*ctx
,
2607 const struct pipe_shader_state
*state
)
2609 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
2610 struct si_context
*sctx
= (struct si_context
*)ctx
;
2611 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
2617 pipe_reference_init(&sel
->reference
, 1);
2618 sel
->screen
= sscreen
;
2619 sel
->compiler_ctx_state
.debug
= sctx
->debug
;
2620 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
2622 sel
->so
= state
->stream_output
;
2624 if (state
->type
== PIPE_SHADER_IR_TGSI
&&
2625 !sscreen
->options
.always_nir
) {
2626 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
2632 tgsi_scan_shader(state
->tokens
, &sel
->info
);
2633 tgsi_scan_tess_ctrl(state
->tokens
, &sel
->info
, &sel
->tcs_info
);
2635 /* Fixup for TGSI: Set which opcode uses which (i,j) pair. */
2636 if (sel
->info
.uses_persp_opcode_interp_centroid
)
2637 sel
->info
.uses_persp_centroid
= true;
2639 if (sel
->info
.uses_linear_opcode_interp_centroid
)
2640 sel
->info
.uses_linear_centroid
= true;
2642 if (sel
->info
.uses_persp_opcode_interp_offset
||
2643 sel
->info
.uses_persp_opcode_interp_sample
)
2644 sel
->info
.uses_persp_center
= true;
2646 if (sel
->info
.uses_linear_opcode_interp_offset
||
2647 sel
->info
.uses_linear_opcode_interp_sample
)
2648 sel
->info
.uses_linear_center
= true;
2650 if (state
->type
== PIPE_SHADER_IR_TGSI
) {
2651 sel
->nir
= tgsi_to_nir(state
->tokens
, ctx
->screen
);
2653 assert(state
->type
== PIPE_SHADER_IR_NIR
);
2654 sel
->nir
= state
->ir
.nir
;
2657 si_nir_lower_ps_inputs(sel
->nir
);
2658 si_nir_opts(sel
->nir
);
2659 si_nir_scan_shader(sel
->nir
, &sel
->info
);
2660 si_nir_scan_tess_ctrl(sel
->nir
, &sel
->tcs_info
);
2663 sel
->type
= sel
->info
.processor
;
2664 p_atomic_inc(&sscreen
->num_shaders_created
);
2665 si_get_active_slot_masks(&sel
->info
,
2666 &sel
->active_const_and_shader_buffers
,
2667 &sel
->active_samplers_and_images
);
2669 /* Record which streamout buffers are enabled. */
2670 for (i
= 0; i
< sel
->so
.num_outputs
; i
++) {
2671 sel
->enabled_streamout_buffer_mask
|=
2672 (1 << sel
->so
.output
[i
].output_buffer
) <<
2673 (sel
->so
.output
[i
].stream
* 4);
2676 /* The prolog is a no-op if there are no inputs. */
2677 sel
->vs_needs_prolog
= sel
->type
== PIPE_SHADER_VERTEX
&&
2678 sel
->info
.num_inputs
&&
2679 !sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
2681 sel
->force_correct_derivs_after_kill
=
2682 sel
->type
== PIPE_SHADER_FRAGMENT
&&
2683 sel
->info
.uses_derivatives
&&
2684 sel
->info
.uses_kill
&&
2685 sctx
->screen
->debug_flags
& DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
2687 sel
->prim_discard_cs_allowed
=
2688 sel
->type
== PIPE_SHADER_VERTEX
&&
2689 !sel
->info
.uses_bindless_images
&&
2690 !sel
->info
.uses_bindless_samplers
&&
2691 !sel
->info
.writes_memory
&&
2692 !sel
->info
.writes_viewport_index
&&
2693 !sel
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] &&
2694 !sel
->so
.num_outputs
;
2696 if (sel
->type
== PIPE_SHADER_VERTEX
&&
2697 sel
->info
.writes_edgeflag
) {
2698 if (sscreen
->info
.chip_class
>= GFX10
)
2699 sel
->ngg_writes_edgeflag
= true;
2701 sel
->pos_writes_edgeflag
= true;
2704 switch (sel
->type
) {
2705 case PIPE_SHADER_GEOMETRY
:
2706 sel
->gs_output_prim
=
2707 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
2709 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2710 sel
->rast_prim
= sel
->gs_output_prim
;
2711 if (util_rast_prim_is_triangles(sel
->rast_prim
))
2712 sel
->rast_prim
= PIPE_PRIM_TRIANGLES
;
2714 sel
->gs_max_out_vertices
=
2715 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
2716 sel
->gs_num_invocations
=
2717 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
2718 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
2719 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
2720 sel
->gs_max_out_vertices
;
2722 sel
->max_gs_stream
= 0;
2723 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
2724 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
2725 sel
->so
.output
[i
].stream
);
2727 sel
->gs_input_verts_per_prim
=
2728 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
2730 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2731 sel
->tess_turns_off_ngg
=
2732 (sscreen
->info
.family
== CHIP_NAVI10
||
2733 sscreen
->info
.family
== CHIP_NAVI12
||
2734 sscreen
->info
.family
== CHIP_NAVI14
) &&
2735 sel
->gs_num_invocations
* sel
->gs_max_out_vertices
> 256;
2738 case PIPE_SHADER_TESS_CTRL
:
2739 /* Always reserve space for these. */
2740 sel
->patch_outputs_written
|=
2741 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0)) |
2742 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0));
2744 case PIPE_SHADER_VERTEX
:
2745 case PIPE_SHADER_TESS_EVAL
:
2746 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2747 unsigned name
= sel
->info
.output_semantic_name
[i
];
2748 unsigned index
= sel
->info
.output_semantic_index
[i
];
2751 case TGSI_SEMANTIC_TESSINNER
:
2752 case TGSI_SEMANTIC_TESSOUTER
:
2753 case TGSI_SEMANTIC_PATCH
:
2754 sel
->patch_outputs_written
|=
2755 1ull << si_shader_io_get_unique_index_patch(name
, index
);
2758 case TGSI_SEMANTIC_GENERIC
:
2759 /* don't process indices the function can't handle */
2760 if (index
>= SI_MAX_IO_GENERIC
)
2764 sel
->outputs_written
|=
2765 1ull << si_shader_io_get_unique_index(name
, index
, false);
2766 sel
->outputs_written_before_ps
|=
2767 1ull << si_shader_io_get_unique_index(name
, index
, true);
2769 case TGSI_SEMANTIC_EDGEFLAG
:
2773 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
2774 sel
->lshs_vertex_stride
= sel
->esgs_itemsize
;
2776 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2777 * will start on a different bank. (except for the maximum 32*16).
2779 if (sel
->lshs_vertex_stride
< 32*16)
2780 sel
->lshs_vertex_stride
+= 4;
2782 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2783 * conflicts, i.e. each vertex will start at a different bank.
2785 if (sctx
->chip_class
>= GFX9
)
2786 sel
->esgs_itemsize
+= 4;
2788 assert(((sel
->esgs_itemsize
/ 4) & C_028AAC_ITEMSIZE
) == 0);
2791 if (sel
->info
.properties
[TGSI_PROPERTY_TES_POINT_MODE
])
2792 sel
->rast_prim
= PIPE_PRIM_POINTS
;
2793 else if (sel
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] == PIPE_PRIM_LINES
)
2794 sel
->rast_prim
= PIPE_PRIM_LINE_STRIP
;
2796 sel
->rast_prim
= PIPE_PRIM_TRIANGLES
;
2799 case PIPE_SHADER_FRAGMENT
:
2800 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2801 unsigned name
= sel
->info
.input_semantic_name
[i
];
2802 unsigned index
= sel
->info
.input_semantic_index
[i
];
2805 case TGSI_SEMANTIC_GENERIC
:
2806 /* don't process indices the function can't handle */
2807 if (index
>= SI_MAX_IO_GENERIC
)
2812 1ull << si_shader_io_get_unique_index(name
, index
, true);
2814 case TGSI_SEMANTIC_PCOORD
: /* ignore this */
2819 for (i
= 0; i
< 8; i
++)
2820 if (sel
->info
.colors_written
& (1 << i
))
2821 sel
->colors_written_4bit
|= 0xf << (4 * i
);
2823 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2824 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
2825 int index
= sel
->info
.input_semantic_index
[i
];
2826 sel
->color_attr_index
[index
] = i
;
2833 /* PA_CL_VS_OUT_CNTL */
2835 sel
->info
.writes_psize
|| sel
->pos_writes_edgeflag
||
2836 sel
->info
.writes_layer
|| sel
->info
.writes_viewport_index
;
2837 sel
->pa_cl_vs_out_cntl
=
2838 S_02881C_USE_VTX_POINT_SIZE(sel
->info
.writes_psize
) |
2839 S_02881C_USE_VTX_EDGE_FLAG(sel
->pos_writes_edgeflag
) |
2840 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel
->info
.writes_layer
) |
2841 S_02881C_USE_VTX_VIEWPORT_INDX(sel
->info
.writes_viewport_index
) |
2842 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
2843 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
);
2844 sel
->clipdist_mask
= sel
->info
.writes_clipvertex
?
2845 SIX_BITS
: sel
->info
.clipdist_writemask
;
2846 sel
->culldist_mask
= sel
->info
.culldist_writemask
<<
2847 sel
->info
.num_written_clipdistance
;
2849 /* DB_SHADER_CONTROL */
2850 sel
->db_shader_control
=
2851 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
2852 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
2853 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
2854 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
2856 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
2857 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2858 sel
->db_shader_control
|=
2859 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2861 case TGSI_FS_DEPTH_LAYOUT_LESS
:
2862 sel
->db_shader_control
|=
2863 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2867 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2869 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2870 * --|-----------|------------|------------|--------------------|-------------------|-------------
2871 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2872 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2873 * 2 | false | true | n/a | LateZ | 1 | 0
2874 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2875 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2877 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2878 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2880 * Don't use ReZ without profiling !!!
2882 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2885 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
2887 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
2888 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
2889 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
2890 } else if (sel
->info
.writes_memory
) {
2892 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) |
2893 S_02880C_EXEC_ON_HIER_FAIL(1);
2896 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2899 if (sel
->info
.properties
[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
])
2900 sel
->db_shader_control
|= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2902 (void) mtx_init(&sel
->mutex
, mtx_plain
);
2904 si_schedule_initial_compile(sctx
, sel
->info
.processor
, &sel
->ready
,
2905 &sel
->compiler_ctx_state
, sel
,
2906 si_init_shader_selector_async
);
2910 static void si_update_streamout_state(struct si_context
*sctx
)
2912 struct si_shader_selector
*shader_with_so
= si_get_vs(sctx
)->cso
;
2914 if (!shader_with_so
)
2917 sctx
->streamout
.enabled_stream_buffers_mask
=
2918 shader_with_so
->enabled_streamout_buffer_mask
;
2919 sctx
->streamout
.stride_in_dw
= shader_with_so
->so
.stride
;
2922 static void si_update_clip_regs(struct si_context
*sctx
,
2923 struct si_shader_selector
*old_hw_vs
,
2924 struct si_shader
*old_hw_vs_variant
,
2925 struct si_shader_selector
*next_hw_vs
,
2926 struct si_shader
*next_hw_vs_variant
)
2930 old_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] !=
2931 next_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] ||
2932 old_hw_vs
->pa_cl_vs_out_cntl
!= next_hw_vs
->pa_cl_vs_out_cntl
||
2933 old_hw_vs
->clipdist_mask
!= next_hw_vs
->clipdist_mask
||
2934 old_hw_vs
->culldist_mask
!= next_hw_vs
->culldist_mask
||
2935 !old_hw_vs_variant
||
2936 !next_hw_vs_variant
||
2937 old_hw_vs_variant
->key
.opt
.clip_disable
!=
2938 next_hw_vs_variant
->key
.opt
.clip_disable
))
2939 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
2942 static void si_update_common_shader_state(struct si_context
*sctx
)
2944 sctx
->uses_bindless_samplers
=
2945 si_shader_uses_bindless_samplers(sctx
->vs_shader
.cso
) ||
2946 si_shader_uses_bindless_samplers(sctx
->gs_shader
.cso
) ||
2947 si_shader_uses_bindless_samplers(sctx
->ps_shader
.cso
) ||
2948 si_shader_uses_bindless_samplers(sctx
->tcs_shader
.cso
) ||
2949 si_shader_uses_bindless_samplers(sctx
->tes_shader
.cso
);
2950 sctx
->uses_bindless_images
=
2951 si_shader_uses_bindless_images(sctx
->vs_shader
.cso
) ||
2952 si_shader_uses_bindless_images(sctx
->gs_shader
.cso
) ||
2953 si_shader_uses_bindless_images(sctx
->ps_shader
.cso
) ||
2954 si_shader_uses_bindless_images(sctx
->tcs_shader
.cso
) ||
2955 si_shader_uses_bindless_images(sctx
->tes_shader
.cso
);
2956 sctx
->do_update_shaders
= true;
2959 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
2961 struct si_context
*sctx
= (struct si_context
*)ctx
;
2962 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2963 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2964 struct si_shader_selector
*sel
= state
;
2966 if (sctx
->vs_shader
.cso
== sel
)
2969 sctx
->vs_shader
.cso
= sel
;
2970 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2971 sctx
->num_vs_blit_sgprs
= sel
? sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
] : 0;
2973 si_update_common_shader_state(sctx
);
2974 si_update_vs_viewport_state(sctx
);
2975 si_set_active_descriptors_for_shader(sctx
, sel
);
2976 si_update_streamout_state(sctx
);
2977 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2978 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2981 static void si_update_tess_uses_prim_id(struct si_context
*sctx
)
2983 sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
=
2984 (sctx
->tes_shader
.cso
&&
2985 sctx
->tes_shader
.cso
->info
.uses_primid
) ||
2986 (sctx
->tcs_shader
.cso
&&
2987 sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
2988 (sctx
->gs_shader
.cso
&&
2989 sctx
->gs_shader
.cso
->info
.uses_primid
) ||
2990 (sctx
->ps_shader
.cso
&& !sctx
->gs_shader
.cso
&&
2991 sctx
->ps_shader
.cso
->info
.uses_primid
);
2994 static bool si_update_ngg(struct si_context
*sctx
)
2996 if (sctx
->chip_class
<= GFX9
)
2999 bool new_ngg
= true;
3001 if (sctx
->gs_shader
.cso
&& sctx
->tes_shader
.cso
&&
3002 sctx
->gs_shader
.cso
->tess_turns_off_ngg
)
3005 if (new_ngg
!= sctx
->ngg
) {
3006 sctx
->ngg
= new_ngg
;
3007 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
3013 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
3015 struct si_context
*sctx
= (struct si_context
*)ctx
;
3016 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
3017 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
3018 struct si_shader_selector
*sel
= state
;
3019 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
3022 if (sctx
->gs_shader
.cso
== sel
)
3025 sctx
->gs_shader
.cso
= sel
;
3026 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
3027 sctx
->ia_multi_vgt_param_key
.u
.uses_gs
= sel
!= NULL
;
3029 si_update_common_shader_state(sctx
);
3030 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
3032 ngg_changed
= si_update_ngg(sctx
);
3033 if (ngg_changed
|| enable_changed
)
3034 si_shader_change_notify(sctx
);
3035 if (enable_changed
) {
3036 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
3037 si_update_tess_uses_prim_id(sctx
);
3039 si_update_vs_viewport_state(sctx
);
3040 si_set_active_descriptors_for_shader(sctx
, sel
);
3041 si_update_streamout_state(sctx
);
3042 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
3043 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
3046 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
3048 struct si_context
*sctx
= (struct si_context
*)ctx
;
3049 struct si_shader_selector
*sel
= state
;
3050 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
3052 if (sctx
->tcs_shader
.cso
== sel
)
3055 sctx
->tcs_shader
.cso
= sel
;
3056 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
3057 si_update_tess_uses_prim_id(sctx
);
3059 si_update_common_shader_state(sctx
);
3062 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
3064 si_set_active_descriptors_for_shader(sctx
, sel
);
3067 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
3069 struct si_context
*sctx
= (struct si_context
*)ctx
;
3070 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
3071 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
3072 struct si_shader_selector
*sel
= state
;
3073 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
3075 if (sctx
->tes_shader
.cso
== sel
)
3078 sctx
->tes_shader
.cso
= sel
;
3079 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
3080 sctx
->ia_multi_vgt_param_key
.u
.uses_tess
= sel
!= NULL
;
3081 si_update_tess_uses_prim_id(sctx
);
3083 si_update_common_shader_state(sctx
);
3084 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
3086 if (enable_changed
) {
3087 si_update_ngg(sctx
);
3088 si_shader_change_notify(sctx
);
3089 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
3091 si_update_vs_viewport_state(sctx
);
3092 si_set_active_descriptors_for_shader(sctx
, sel
);
3093 si_update_streamout_state(sctx
);
3094 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
3095 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
3098 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
3100 struct si_context
*sctx
= (struct si_context
*)ctx
;
3101 struct si_shader_selector
*old_sel
= sctx
->ps_shader
.cso
;
3102 struct si_shader_selector
*sel
= state
;
3104 /* skip if supplied shader is one already in use */
3108 sctx
->ps_shader
.cso
= sel
;
3109 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
3111 si_update_common_shader_state(sctx
);
3113 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
3114 si_update_tess_uses_prim_id(sctx
);
3117 old_sel
->info
.colors_written
!= sel
->info
.colors_written
)
3118 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3120 if (sctx
->screen
->has_out_of_order_rast
&&
3122 old_sel
->info
.writes_memory
!= sel
->info
.writes_memory
||
3123 old_sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] !=
3124 sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]))
3125 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3127 si_set_active_descriptors_for_shader(sctx
, sel
);
3128 si_update_ps_colorbuf0_slot(sctx
);
3131 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
3133 if (shader
->is_optimized
) {
3134 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue_low_priority
,
3138 util_queue_fence_destroy(&shader
->ready
);
3141 /* If destroyed shaders were not unbound, the next compiled
3142 * shader variant could get the same pointer address and so
3143 * binding it to the same shader stage would be considered
3144 * a no-op, causing random behavior.
3146 switch (shader
->selector
->type
) {
3147 case PIPE_SHADER_VERTEX
:
3148 if (shader
->key
.as_ls
) {
3149 assert(sctx
->chip_class
<= GFX8
);
3150 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
3151 } else if (shader
->key
.as_es
) {
3152 assert(sctx
->chip_class
<= GFX8
);
3153 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
3154 } else if (shader
->key
.as_ngg
) {
3155 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3157 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3160 case PIPE_SHADER_TESS_CTRL
:
3161 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
3163 case PIPE_SHADER_TESS_EVAL
:
3164 if (shader
->key
.as_es
) {
3165 assert(sctx
->chip_class
<= GFX8
);
3166 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
3167 } else if (shader
->key
.as_ngg
) {
3168 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3170 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3173 case PIPE_SHADER_GEOMETRY
:
3174 if (shader
->is_gs_copy_shader
)
3175 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3177 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3179 case PIPE_SHADER_FRAGMENT
:
3180 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
3186 si_shader_selector_reference(sctx
, &shader
->previous_stage_sel
, NULL
);
3187 si_shader_destroy(shader
);
3191 void si_destroy_shader_selector(struct si_context
*sctx
,
3192 struct si_shader_selector
*sel
)
3194 struct si_shader
*p
= sel
->first_variant
, *c
;
3195 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
3196 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
3197 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
3198 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
3199 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
3200 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
3203 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue
, &sel
->ready
);
3205 if (current_shader
[sel
->type
]->cso
== sel
) {
3206 current_shader
[sel
->type
]->cso
= NULL
;
3207 current_shader
[sel
->type
]->current
= NULL
;
3211 c
= p
->next_variant
;
3212 si_delete_shader(sctx
, p
);
3216 if (sel
->main_shader_part
)
3217 si_delete_shader(sctx
, sel
->main_shader_part
);
3218 if (sel
->main_shader_part_ls
)
3219 si_delete_shader(sctx
, sel
->main_shader_part_ls
);
3220 if (sel
->main_shader_part_es
)
3221 si_delete_shader(sctx
, sel
->main_shader_part_es
);
3222 if (sel
->main_shader_part_ngg
)
3223 si_delete_shader(sctx
, sel
->main_shader_part_ngg
);
3224 if (sel
->gs_copy_shader
)
3225 si_delete_shader(sctx
, sel
->gs_copy_shader
);
3227 util_queue_fence_destroy(&sel
->ready
);
3228 mtx_destroy(&sel
->mutex
);
3230 ralloc_free(sel
->nir
);
3234 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
3236 struct si_context
*sctx
= (struct si_context
*)ctx
;
3237 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
3239 si_shader_selector_reference(sctx
, &sel
, NULL
);
3242 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
3243 struct si_shader
*vs
, unsigned name
,
3244 unsigned index
, unsigned interpolate
)
3246 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
3247 unsigned j
, offset
, ps_input_cntl
= 0;
3249 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
3250 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
) ||
3251 name
== TGSI_SEMANTIC_PRIMID
)
3252 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
3254 if (name
== TGSI_SEMANTIC_PCOORD
||
3255 (name
== TGSI_SEMANTIC_TEXCOORD
&&
3256 sctx
->sprite_coord_enable
& (1 << index
))) {
3257 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
3260 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
3261 if (name
== vsinfo
->output_semantic_name
[j
] &&
3262 index
== vsinfo
->output_semantic_index
[j
]) {
3263 offset
= vs
->info
.vs_output_param_offset
[j
];
3265 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
3266 /* The input is loaded from parameter memory. */
3267 ps_input_cntl
|= S_028644_OFFSET(offset
);
3268 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
3269 if (offset
== AC_EXP_PARAM_UNDEFINED
) {
3270 /* This can happen with depth-only rendering. */
3273 /* The input is a DEFAULT_VAL constant. */
3274 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
3275 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
3276 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
3279 ps_input_cntl
= S_028644_OFFSET(0x20) |
3280 S_028644_DEFAULT_VAL(offset
);
3286 if (j
== vsinfo
->num_outputs
&& name
== TGSI_SEMANTIC_PRIMID
)
3287 /* PrimID is written after the last output when HW VS is used. */
3288 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
3289 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
3290 /* No corresponding output found, load defaults into input.
3291 * Don't set any other bits.
3292 * (FLAT_SHADE=1 completely changes behavior) */
3293 ps_input_cntl
= S_028644_OFFSET(0x20);
3294 /* D3D 9 behaviour. GL is undefined */
3295 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
3296 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
3298 return ps_input_cntl
;
3301 static void si_emit_spi_map(struct si_context
*sctx
)
3303 struct si_shader
*ps
= sctx
->ps_shader
.current
;
3304 struct si_shader
*vs
= si_get_vs_state(sctx
);
3305 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
3306 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
3307 unsigned spi_ps_input_cntl
[32];
3309 if (!ps
|| !ps
->selector
->info
.num_inputs
)
3312 num_interp
= si_get_ps_num_interp(ps
);
3313 assert(num_interp
> 0);
3315 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
3316 unsigned name
= psinfo
->input_semantic_name
[i
];
3317 unsigned index
= psinfo
->input_semantic_index
[i
];
3318 unsigned interpolate
= psinfo
->input_interpolate
[i
];
3320 spi_ps_input_cntl
[num_written
++] = si_get_ps_input_cntl(sctx
, vs
, name
,
3321 index
, interpolate
);
3323 if (name
== TGSI_SEMANTIC_COLOR
) {
3324 assert(index
< ARRAY_SIZE(bcol_interp
));
3325 bcol_interp
[index
] = interpolate
;
3329 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
3330 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
3332 for (i
= 0; i
< 2; i
++) {
3333 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
3336 spi_ps_input_cntl
[num_written
++] =
3337 si_get_ps_input_cntl(sctx
, vs
, bcol
, i
, bcol_interp
[i
]);
3341 assert(num_interp
== num_written
);
3343 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3344 /* Dota 2: Only ~16% of SPI map updates set different values. */
3345 /* Talos: Only ~9% of SPI map updates set different values. */
3346 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
3347 radeon_opt_set_context_regn(sctx
, R_028644_SPI_PS_INPUT_CNTL_0
,
3349 sctx
->tracked_regs
.spi_ps_input_cntl
, num_interp
);
3351 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
3352 sctx
->context_roll
= true;
3356 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3358 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
3360 if (sctx
->init_config_has_vgt_flush
)
3363 /* Done by Vulkan before VGT_FLUSH. */
3364 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
3365 si_pm4_cmd_add(sctx
->init_config
,
3366 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3367 si_pm4_cmd_end(sctx
->init_config
, false);
3369 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3370 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
3371 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
3372 si_pm4_cmd_end(sctx
->init_config
, false);
3373 sctx
->init_config_has_vgt_flush
= true;
3376 /* Initialize state related to ESGS / GSVS ring buffers */
3377 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
3379 struct si_shader_selector
*es
=
3380 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
3381 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
3382 struct si_pm4_state
*pm4
;
3384 /* Chip constants. */
3385 unsigned num_se
= sctx
->screen
->info
.max_se
;
3386 unsigned wave_size
= 64;
3387 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
3388 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3389 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3391 unsigned gs_vertex_reuse
= (sctx
->chip_class
>= GFX8
? 32 : 16) * num_se
;
3392 unsigned alignment
= 256 * num_se
;
3393 /* The maximum size is 63.999 MB per SE. */
3394 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
3396 /* Calculate the minimum size. */
3397 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
3398 wave_size
, alignment
);
3400 /* These are recommended sizes, not minimum sizes. */
3401 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
3402 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
3403 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
3404 gs
->max_gsvs_emit_size
;
3406 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
3407 esgs_ring_size
= align(esgs_ring_size
, alignment
);
3408 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
3410 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
3411 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
3413 /* Some rings don't have to be allocated if shaders don't use them.
3414 * (e.g. no varyings between ES and GS or GS and VS)
3416 * GFX9 doesn't have the ESGS ring.
3418 bool update_esgs
= sctx
->chip_class
<= GFX8
&&
3420 (!sctx
->esgs_ring
||
3421 sctx
->esgs_ring
->width0
< esgs_ring_size
);
3422 bool update_gsvs
= gsvs_ring_size
&&
3423 (!sctx
->gsvs_ring
||
3424 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
3426 if (!update_esgs
&& !update_gsvs
)
3430 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
3432 pipe_aligned_buffer_create(sctx
->b
.screen
,
3433 SI_RESOURCE_FLAG_UNMAPPABLE
,
3435 esgs_ring_size
, alignment
);
3436 if (!sctx
->esgs_ring
)
3441 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
3443 pipe_aligned_buffer_create(sctx
->b
.screen
,
3444 SI_RESOURCE_FLAG_UNMAPPABLE
,
3446 gsvs_ring_size
, alignment
);
3447 if (!sctx
->gsvs_ring
)
3451 /* Create the "init_config_gs_rings" state. */
3452 pm4
= CALLOC_STRUCT(si_pm4_state
);
3456 if (sctx
->chip_class
>= GFX7
) {
3457 if (sctx
->esgs_ring
) {
3458 assert(sctx
->chip_class
<= GFX8
);
3459 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
3460 sctx
->esgs_ring
->width0
/ 256);
3462 if (sctx
->gsvs_ring
)
3463 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
3464 sctx
->gsvs_ring
->width0
/ 256);
3466 if (sctx
->esgs_ring
)
3467 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
3468 sctx
->esgs_ring
->width0
/ 256);
3469 if (sctx
->gsvs_ring
)
3470 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
3471 sctx
->gsvs_ring
->width0
/ 256);
3474 /* Set the state. */
3475 if (sctx
->init_config_gs_rings
)
3476 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
3477 sctx
->init_config_gs_rings
= pm4
;
3479 if (!sctx
->init_config_has_vgt_flush
) {
3480 si_init_config_add_vgt_flush(sctx
);
3481 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3484 /* Flush the context to re-emit both init_config states. */
3485 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3486 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3488 /* Set ring bindings. */
3489 if (sctx
->esgs_ring
) {
3490 assert(sctx
->chip_class
<= GFX8
);
3491 si_set_ring_buffer(sctx
, SI_ES_RING_ESGS
,
3492 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
3493 true, true, 4, 64, 0);
3494 si_set_ring_buffer(sctx
, SI_GS_RING_ESGS
,
3495 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
3496 false, false, 0, 0, 0);
3498 if (sctx
->gsvs_ring
) {
3499 si_set_ring_buffer(sctx
, SI_RING_GSVS
,
3500 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
3501 false, false, 0, 0, 0);
3507 static void si_shader_lock(struct si_shader
*shader
)
3509 mtx_lock(&shader
->selector
->mutex
);
3510 if (shader
->previous_stage_sel
) {
3511 assert(shader
->previous_stage_sel
!= shader
->selector
);
3512 mtx_lock(&shader
->previous_stage_sel
->mutex
);
3516 static void si_shader_unlock(struct si_shader
*shader
)
3518 if (shader
->previous_stage_sel
)
3519 mtx_unlock(&shader
->previous_stage_sel
->mutex
);
3520 mtx_unlock(&shader
->selector
->mutex
);
3524 * @returns 1 if \p sel has been updated to use a new scratch buffer
3526 * < 0 if there was a failure
3528 static int si_update_scratch_buffer(struct si_context
*sctx
,
3529 struct si_shader
*shader
)
3531 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
3536 /* This shader doesn't need a scratch buffer */
3537 if (shader
->config
.scratch_bytes_per_wave
== 0)
3540 /* Prevent race conditions when updating:
3541 * - si_shader::scratch_bo
3542 * - si_shader::binary::code
3543 * - si_shader::previous_stage::binary::code.
3545 si_shader_lock(shader
);
3547 /* This shader is already configured to use the current
3548 * scratch buffer. */
3549 if (shader
->scratch_bo
== sctx
->scratch_buffer
) {
3550 si_shader_unlock(shader
);
3554 assert(sctx
->scratch_buffer
);
3556 /* Replace the shader bo with a new bo that has the relocs applied. */
3557 if (!si_shader_binary_upload(sctx
->screen
, shader
, scratch_va
)) {
3558 si_shader_unlock(shader
);
3562 /* Update the shader state to use the new shader bo. */
3563 si_shader_init_pm4_state(sctx
->screen
, shader
);
3565 si_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
3567 si_shader_unlock(shader
);
3571 static unsigned si_get_current_scratch_buffer_size(struct si_context
*sctx
)
3573 return sctx
->scratch_buffer
? sctx
->scratch_buffer
->b
.b
.width0
: 0;
3576 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
3578 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
3581 static struct si_shader
*si_get_tcs_current(struct si_context
*sctx
)
3583 if (!sctx
->tes_shader
.cso
)
3584 return NULL
; /* tessellation disabled */
3586 return sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.current
:
3587 sctx
->fixed_func_tcs_shader
.current
;
3590 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context
*sctx
)
3594 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
3595 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
3596 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
3597 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
3599 if (sctx
->tes_shader
.cso
) {
3600 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
3602 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(tcs
));
3607 static bool si_update_scratch_relocs(struct si_context
*sctx
)
3609 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
3612 /* Update the shaders, so that they are using the latest scratch.
3613 * The scratch buffer may have been changed since these shaders were
3614 * last used, so we still need to try to update them, even if they
3615 * require scratch buffers smaller than the current size.
3617 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
3621 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3623 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
3627 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3629 r
= si_update_scratch_buffer(sctx
, tcs
);
3633 si_pm4_bind_state(sctx
, hs
, tcs
->pm4
);
3635 /* VS can be bound as LS, ES, or VS. */
3636 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
3640 if (sctx
->vs_shader
.current
->key
.as_ls
)
3641 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3642 else if (sctx
->vs_shader
.current
->key
.as_es
)
3643 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3644 else if (sctx
->vs_shader
.current
->key
.as_ngg
)
3645 si_pm4_bind_state(sctx
, gs
, sctx
->vs_shader
.current
->pm4
);
3647 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3650 /* TES can be bound as ES or VS. */
3651 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
3655 if (sctx
->tes_shader
.current
->key
.as_es
)
3656 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3657 else if (sctx
->tes_shader
.current
->key
.as_ngg
)
3658 si_pm4_bind_state(sctx
, gs
, sctx
->tes_shader
.current
->pm4
);
3660 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3666 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
3668 unsigned current_scratch_buffer_size
=
3669 si_get_current_scratch_buffer_size(sctx
);
3670 unsigned scratch_bytes_per_wave
=
3671 si_get_max_scratch_bytes_per_wave(sctx
);
3672 unsigned scratch_needed_size
= scratch_bytes_per_wave
*
3673 sctx
->scratch_waves
;
3674 unsigned spi_tmpring_size
;
3676 if (scratch_needed_size
> 0) {
3677 if (scratch_needed_size
> current_scratch_buffer_size
) {
3678 /* Create a bigger scratch buffer */
3679 si_resource_reference(&sctx
->scratch_buffer
, NULL
);
3681 sctx
->scratch_buffer
=
3682 si_aligned_buffer_create(&sctx
->screen
->b
,
3683 SI_RESOURCE_FLAG_UNMAPPABLE
,
3685 scratch_needed_size
, 256);
3686 if (!sctx
->scratch_buffer
)
3689 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3690 si_context_add_resource_size(sctx
,
3691 &sctx
->scratch_buffer
->b
.b
);
3694 if (!si_update_scratch_relocs(sctx
))
3698 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3699 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
3700 "scratch size should already be aligned correctly.");
3702 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
3703 S_0286E8_WAVESIZE(scratch_bytes_per_wave
>> 10);
3704 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
3705 sctx
->spi_tmpring_size
= spi_tmpring_size
;
3706 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3711 static void si_init_tess_factor_ring(struct si_context
*sctx
)
3713 assert(!sctx
->tess_rings
);
3715 /* The address must be aligned to 2^19, because the shader only
3716 * receives the high 13 bits.
3718 sctx
->tess_rings
= pipe_aligned_buffer_create(sctx
->b
.screen
,
3719 SI_RESOURCE_FLAG_32BIT
,
3721 sctx
->screen
->tess_offchip_ring_size
+
3722 sctx
->screen
->tess_factor_ring_size
,
3724 if (!sctx
->tess_rings
)
3727 si_init_config_add_vgt_flush(sctx
);
3729 si_pm4_add_bo(sctx
->init_config
, si_resource(sctx
->tess_rings
),
3730 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
3732 uint64_t factor_va
= si_resource(sctx
->tess_rings
)->gpu_address
+
3733 sctx
->screen
->tess_offchip_ring_size
;
3735 /* Append these registers to the init config state. */
3736 if (sctx
->chip_class
>= GFX7
) {
3737 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
3738 S_030938_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3739 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
3741 if (sctx
->chip_class
>= GFX10
)
3742 si_pm4_set_reg(sctx
->init_config
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
3743 S_030984_BASE_HI(factor_va
>> 40));
3744 else if (sctx
->chip_class
== GFX9
)
3745 si_pm4_set_reg(sctx
->init_config
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3746 S_030944_BASE_HI(factor_va
>> 40));
3747 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3748 sctx
->screen
->vgt_hs_offchip_param
);
3750 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
3751 S_008988_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3752 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
3754 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3755 sctx
->screen
->vgt_hs_offchip_param
);
3758 /* Flush the context to re-emit the init_config state.
3759 * This is done only once in a lifetime of a context.
3761 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3762 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3763 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3766 static struct si_pm4_state
*si_build_vgt_shader_config(struct si_screen
*screen
,
3767 union si_vgt_stages_key key
)
3769 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
3770 uint32_t stages
= 0;
3773 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3774 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3777 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3780 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
3782 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3783 } else if (key
.u
.gs
) {
3784 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3786 } else if (key
.u
.ngg
) {
3787 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
3791 stages
|= S_028B54_PRIMGEN_EN(1);
3792 if (key
.u
.streamout
)
3793 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
3794 } else if (key
.u
.gs
)
3795 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3797 if (screen
->info
.chip_class
>= GFX9
)
3798 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3800 if (screen
->info
.chip_class
>= GFX10
&& screen
->ge_wave_size
== 32) {
3801 stages
|= S_028B54_HS_W32_EN(1) |
3802 S_028B54_GS_W32_EN(key
.u
.ngg
) | /* legacy GS only supports Wave64 */
3803 S_028B54_VS_W32_EN(1);
3806 si_pm4_set_reg(pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
3810 static void si_update_vgt_shader_config(struct si_context
*sctx
,
3811 union si_vgt_stages_key key
)
3813 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[key
.index
];
3815 if (unlikely(!*pm4
))
3816 *pm4
= si_build_vgt_shader_config(sctx
->screen
, key
);
3817 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
3820 bool si_update_shaders(struct si_context
*sctx
)
3822 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
3823 struct si_compiler_ctx_state compiler_state
;
3824 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3825 struct si_shader
*old_vs
= si_get_vs_state(sctx
);
3826 bool old_clip_disable
= old_vs
? old_vs
->key
.opt
.clip_disable
: false;
3827 struct si_shader
*old_ps
= sctx
->ps_shader
.current
;
3828 union si_vgt_stages_key key
;
3829 unsigned old_spi_shader_col_format
=
3830 old_ps
? old_ps
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
3833 compiler_state
.compiler
= &sctx
->compiler
;
3834 compiler_state
.debug
= sctx
->debug
;
3835 compiler_state
.is_debug_context
= sctx
->is_debug
;
3839 if (sctx
->tes_shader
.cso
)
3841 if (sctx
->gs_shader
.cso
)
3844 if (sctx
->chip_class
>= GFX10
) {
3845 key
.u
.ngg
= sctx
->ngg
;
3847 if (sctx
->gs_shader
.cso
)
3848 key
.u
.streamout
= !!sctx
->gs_shader
.cso
->so
.num_outputs
;
3849 else if (sctx
->tes_shader
.cso
)
3850 key
.u
.streamout
= !!sctx
->tes_shader
.cso
->so
.num_outputs
;
3852 key
.u
.streamout
= !!sctx
->vs_shader
.cso
->so
.num_outputs
;
3855 /* Update TCS and TES. */
3856 if (sctx
->tes_shader
.cso
) {
3857 if (!sctx
->tess_rings
) {
3858 si_init_tess_factor_ring(sctx
);
3859 if (!sctx
->tess_rings
)
3863 if (sctx
->tcs_shader
.cso
) {
3864 r
= si_shader_select(ctx
, &sctx
->tcs_shader
, key
,
3868 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
3870 if (!sctx
->fixed_func_tcs_shader
.cso
) {
3871 sctx
->fixed_func_tcs_shader
.cso
=
3872 si_create_fixed_func_tcs(sctx
);
3873 if (!sctx
->fixed_func_tcs_shader
.cso
)
3877 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
,
3878 key
, &compiler_state
);
3881 si_pm4_bind_state(sctx
, hs
,
3882 sctx
->fixed_func_tcs_shader
.current
->pm4
);
3885 if (!sctx
->gs_shader
.cso
|| sctx
->chip_class
<= GFX8
) {
3886 r
= si_shader_select(ctx
, &sctx
->tes_shader
, key
, &compiler_state
);
3890 if (sctx
->gs_shader
.cso
) {
3892 assert(sctx
->chip_class
<= GFX8
);
3893 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3894 } else if (key
.u
.ngg
) {
3895 si_pm4_bind_state(sctx
, gs
, sctx
->tes_shader
.current
->pm4
);
3897 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3901 if (sctx
->chip_class
<= GFX8
)
3902 si_pm4_bind_state(sctx
, ls
, NULL
);
3903 si_pm4_bind_state(sctx
, hs
, NULL
);
3907 if (sctx
->gs_shader
.cso
) {
3908 r
= si_shader_select(ctx
, &sctx
->gs_shader
, key
, &compiler_state
);
3911 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3913 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
3915 if (!si_update_gs_ring_buffers(sctx
))
3918 si_pm4_bind_state(sctx
, vs
, NULL
);
3922 si_pm4_bind_state(sctx
, gs
, NULL
);
3923 if (sctx
->chip_class
<= GFX8
)
3924 si_pm4_bind_state(sctx
, es
, NULL
);
3929 if ((!key
.u
.tess
&& !key
.u
.gs
) || sctx
->chip_class
<= GFX8
) {
3930 r
= si_shader_select(ctx
, &sctx
->vs_shader
, key
, &compiler_state
);
3934 if (!key
.u
.tess
&& !key
.u
.gs
) {
3936 si_pm4_bind_state(sctx
, gs
, sctx
->vs_shader
.current
->pm4
);
3937 si_pm4_bind_state(sctx
, vs
, NULL
);
3939 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3941 } else if (sctx
->tes_shader
.cso
) {
3942 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3944 assert(sctx
->gs_shader
.cso
);
3945 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3949 si_update_vgt_shader_config(sctx
, key
);
3951 if (old_clip_disable
!= si_get_vs_state(sctx
)->key
.opt
.clip_disable
)
3952 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
3954 if (sctx
->ps_shader
.cso
) {
3955 unsigned db_shader_control
;
3957 r
= si_shader_select(ctx
, &sctx
->ps_shader
, key
, &compiler_state
);
3960 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3963 sctx
->ps_shader
.cso
->db_shader_control
|
3964 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
3966 if (si_pm4_state_changed(sctx
, ps
) ||
3967 si_pm4_state_changed(sctx
, vs
) ||
3968 (key
.u
.ngg
&& si_pm4_state_changed(sctx
, gs
)) ||
3969 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
3970 sctx
->flatshade
!= rs
->flatshade
) {
3971 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
3972 sctx
->flatshade
= rs
->flatshade
;
3973 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.spi_map
);
3976 if (sctx
->screen
->rbplus_allowed
&&
3977 si_pm4_state_changed(sctx
, ps
) &&
3979 old_spi_shader_col_format
!=
3980 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
))
3981 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3983 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
3984 sctx
->ps_db_shader_control
= db_shader_control
;
3985 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3986 if (sctx
->screen
->dpbb_allowed
)
3987 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3990 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
3991 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
3992 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3994 if (sctx
->chip_class
== GFX6
)
3995 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3997 if (sctx
->framebuffer
.nr_samples
<= 1)
3998 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
4002 if (si_pm4_state_enabled_and_changed(sctx
, ls
) ||
4003 si_pm4_state_enabled_and_changed(sctx
, hs
) ||
4004 si_pm4_state_enabled_and_changed(sctx
, es
) ||
4005 si_pm4_state_enabled_and_changed(sctx
, gs
) ||
4006 si_pm4_state_enabled_and_changed(sctx
, vs
) ||
4007 si_pm4_state_enabled_and_changed(sctx
, ps
)) {
4008 if (!si_update_spi_tmpring_size(sctx
))
4012 if (sctx
->chip_class
>= GFX7
) {
4013 if (si_pm4_state_enabled_and_changed(sctx
, ls
))
4014 sctx
->prefetch_L2_mask
|= SI_PREFETCH_LS
;
4015 else if (!sctx
->queued
.named
.ls
)
4016 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_LS
;
4018 if (si_pm4_state_enabled_and_changed(sctx
, hs
))
4019 sctx
->prefetch_L2_mask
|= SI_PREFETCH_HS
;
4020 else if (!sctx
->queued
.named
.hs
)
4021 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_HS
;
4023 if (si_pm4_state_enabled_and_changed(sctx
, es
))
4024 sctx
->prefetch_L2_mask
|= SI_PREFETCH_ES
;
4025 else if (!sctx
->queued
.named
.es
)
4026 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_ES
;
4028 if (si_pm4_state_enabled_and_changed(sctx
, gs
))
4029 sctx
->prefetch_L2_mask
|= SI_PREFETCH_GS
;
4030 else if (!sctx
->queued
.named
.gs
)
4031 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_GS
;
4033 if (si_pm4_state_enabled_and_changed(sctx
, vs
))
4034 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VS
;
4035 else if (!sctx
->queued
.named
.vs
)
4036 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_VS
;
4038 if (si_pm4_state_enabled_and_changed(sctx
, ps
))
4039 sctx
->prefetch_L2_mask
|= SI_PREFETCH_PS
;
4040 else if (!sctx
->queued
.named
.ps
)
4041 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_PS
;
4044 sctx
->do_update_shaders
= false;
4048 static void si_emit_scratch_state(struct si_context
*sctx
)
4050 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
4052 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
4053 sctx
->spi_tmpring_size
);
4055 if (sctx
->scratch_buffer
) {
4056 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
4057 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
4058 RADEON_PRIO_SCRATCH_BUFFER
);
4062 void si_init_shader_functions(struct si_context
*sctx
)
4064 sctx
->atoms
.s
.spi_map
.emit
= si_emit_spi_map
;
4065 sctx
->atoms
.s
.scratch_state
.emit
= si_emit_scratch_state
;
4067 sctx
->b
.create_vs_state
= si_create_shader_selector
;
4068 sctx
->b
.create_tcs_state
= si_create_shader_selector
;
4069 sctx
->b
.create_tes_state
= si_create_shader_selector
;
4070 sctx
->b
.create_gs_state
= si_create_shader_selector
;
4071 sctx
->b
.create_fs_state
= si_create_shader_selector
;
4073 sctx
->b
.bind_vs_state
= si_bind_vs_shader
;
4074 sctx
->b
.bind_tcs_state
= si_bind_tcs_shader
;
4075 sctx
->b
.bind_tes_state
= si_bind_tes_shader
;
4076 sctx
->b
.bind_gs_state
= si_bind_gs_shader
;
4077 sctx
->b
.bind_fs_state
= si_bind_ps_shader
;
4079 sctx
->b
.delete_vs_state
= si_delete_shader_selector
;
4080 sctx
->b
.delete_tcs_state
= si_delete_shader_selector
;
4081 sctx
->b
.delete_tes_state
= si_delete_shader_selector
;
4082 sctx
->b
.delete_gs_state
= si_delete_shader_selector
;
4083 sctx
->b
.delete_fs_state
= si_delete_shader_selector
;