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radeonsi: disable the TGSI merge registers pass
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "sid.h"
30 #include "gfx9d.h"
31 #include "radeon/r600_cs.h"
32
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/hash_table.h"
36 #include "util/crc32.h"
37 #include "util/u_memory.h"
38 #include "util/u_prim.h"
39
40 #include "util/disk_cache.h"
41 #include "util/mesa-sha1.h"
42
43 /* SHADER_CACHE */
44
45 /**
46 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
47 * integer.
48 */
49 static void *si_get_tgsi_binary(struct si_shader_selector *sel)
50 {
51 unsigned tgsi_size = tgsi_num_tokens(sel->tokens) *
52 sizeof(struct tgsi_token);
53 unsigned size = 4 + tgsi_size + sizeof(sel->so);
54 char *result = (char*)MALLOC(size);
55
56 if (!result)
57 return NULL;
58
59 *((uint32_t*)result) = size;
60 memcpy(result + 4, sel->tokens, tgsi_size);
61 memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so));
62 return result;
63 }
64
65 /** Copy "data" to "ptr" and return the next dword following copied data. */
66 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
67 {
68 /* data may be NULL if size == 0 */
69 if (size)
70 memcpy(ptr, data, size);
71 ptr += DIV_ROUND_UP(size, 4);
72 return ptr;
73 }
74
75 /** Read data from "ptr". Return the next dword following the data. */
76 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
77 {
78 memcpy(data, ptr, size);
79 ptr += DIV_ROUND_UP(size, 4);
80 return ptr;
81 }
82
83 /**
84 * Write the size as uint followed by the data. Return the next dword
85 * following the copied data.
86 */
87 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
88 {
89 *ptr++ = size;
90 return write_data(ptr, data, size);
91 }
92
93 /**
94 * Read the size as uint followed by the data. Return both via parameters.
95 * Return the next dword following the data.
96 */
97 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
98 {
99 *size = *ptr++;
100 assert(*data == NULL);
101 if (!*size)
102 return ptr;
103 *data = malloc(*size);
104 return read_data(ptr, *data, *size);
105 }
106
107 /**
108 * Return the shader binary in a buffer. The first 4 bytes contain its size
109 * as integer.
110 */
111 static void *si_get_shader_binary(struct si_shader *shader)
112 {
113 /* There is always a size of data followed by the data itself. */
114 unsigned relocs_size = shader->binary.reloc_count *
115 sizeof(shader->binary.relocs[0]);
116 unsigned disasm_size = shader->binary.disasm_string ?
117 strlen(shader->binary.disasm_string) + 1 : 0;
118 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
119 strlen(shader->binary.llvm_ir_string) + 1 : 0;
120 unsigned size =
121 4 + /* total size */
122 4 + /* CRC32 of the data below */
123 align(sizeof(shader->config), 4) +
124 align(sizeof(shader->info), 4) +
125 4 + align(shader->binary.code_size, 4) +
126 4 + align(shader->binary.rodata_size, 4) +
127 4 + align(relocs_size, 4) +
128 4 + align(disasm_size, 4) +
129 4 + align(llvm_ir_size, 4);
130 void *buffer = CALLOC(1, size);
131 uint32_t *ptr = (uint32_t*)buffer;
132
133 if (!buffer)
134 return NULL;
135
136 *ptr++ = size;
137 ptr++; /* CRC32 is calculated at the end. */
138
139 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
140 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
141 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
142 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
143 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
144 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
145 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
146 assert((char *)ptr - (char *)buffer == size);
147
148 /* Compute CRC32. */
149 ptr = (uint32_t*)buffer;
150 ptr++;
151 *ptr = util_hash_crc32(ptr + 1, size - 8);
152
153 return buffer;
154 }
155
156 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
157 {
158 uint32_t *ptr = (uint32_t*)binary;
159 uint32_t size = *ptr++;
160 uint32_t crc32 = *ptr++;
161 unsigned chunk_size;
162
163 if (util_hash_crc32(ptr, size - 8) != crc32) {
164 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
165 return false;
166 }
167
168 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
169 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
170 ptr = read_chunk(ptr, (void**)&shader->binary.code,
171 &shader->binary.code_size);
172 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
173 &shader->binary.rodata_size);
174 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
175 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
176 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
177 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
178
179 return true;
180 }
181
182 /**
183 * Insert a shader into the cache. It's assumed the shader is not in the cache.
184 * Use si_shader_cache_load_shader before calling this.
185 *
186 * Returns false on failure, in which case the tgsi_binary should be freed.
187 */
188 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
189 void *tgsi_binary,
190 struct si_shader *shader,
191 bool insert_into_disk_cache)
192 {
193 void *hw_binary;
194 struct hash_entry *entry;
195 uint8_t key[CACHE_KEY_SIZE];
196
197 entry = _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
198 if (entry)
199 return false; /* already added */
200
201 hw_binary = si_get_shader_binary(shader);
202 if (!hw_binary)
203 return false;
204
205 if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
206 hw_binary) == NULL) {
207 FREE(hw_binary);
208 return false;
209 }
210
211 if (sscreen->b.disk_shader_cache && insert_into_disk_cache) {
212 disk_cache_compute_key(sscreen->b.disk_shader_cache, tgsi_binary,
213 *((uint32_t *)tgsi_binary), key);
214 disk_cache_put(sscreen->b.disk_shader_cache, key, hw_binary,
215 *((uint32_t *) hw_binary));
216 }
217
218 return true;
219 }
220
221 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
222 void *tgsi_binary,
223 struct si_shader *shader)
224 {
225 struct hash_entry *entry =
226 _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
227 if (!entry) {
228 if (sscreen->b.disk_shader_cache) {
229 unsigned char sha1[CACHE_KEY_SIZE];
230 size_t tg_size = *((uint32_t *) tgsi_binary);
231
232 disk_cache_compute_key(sscreen->b.disk_shader_cache,
233 tgsi_binary, tg_size, sha1);
234
235 size_t binary_size;
236 uint8_t *buffer =
237 disk_cache_get(sscreen->b.disk_shader_cache,
238 sha1, &binary_size);
239 if (!buffer)
240 return false;
241
242 if (binary_size < sizeof(uint32_t) ||
243 *((uint32_t*)buffer) != binary_size) {
244 /* Something has gone wrong discard the item
245 * from the cache and rebuild/link from
246 * source.
247 */
248 assert(!"Invalid radeonsi shader disk cache "
249 "item!");
250
251 disk_cache_remove(sscreen->b.disk_shader_cache,
252 sha1);
253 free(buffer);
254
255 return false;
256 }
257
258 if (!si_load_shader_binary(shader, buffer)) {
259 free(buffer);
260 return false;
261 }
262 free(buffer);
263
264 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary,
265 shader, false))
266 FREE(tgsi_binary);
267 } else {
268 return false;
269 }
270 } else {
271 if (si_load_shader_binary(shader, entry->data))
272 FREE(tgsi_binary);
273 else
274 return false;
275 }
276 p_atomic_inc(&sscreen->b.num_shader_cache_hits);
277 return true;
278 }
279
280 static uint32_t si_shader_cache_key_hash(const void *key)
281 {
282 /* The first dword is the key size. */
283 return util_hash_crc32(key, *(uint32_t*)key);
284 }
285
286 static bool si_shader_cache_key_equals(const void *a, const void *b)
287 {
288 uint32_t *keya = (uint32_t*)a;
289 uint32_t *keyb = (uint32_t*)b;
290
291 /* The first dword is the key size. */
292 if (*keya != *keyb)
293 return false;
294
295 return memcmp(keya, keyb, *keya) == 0;
296 }
297
298 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
299 {
300 FREE((void*)entry->key);
301 FREE(entry->data);
302 }
303
304 bool si_init_shader_cache(struct si_screen *sscreen)
305 {
306 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
307 sscreen->shader_cache =
308 _mesa_hash_table_create(NULL,
309 si_shader_cache_key_hash,
310 si_shader_cache_key_equals);
311
312 return sscreen->shader_cache != NULL;
313 }
314
315 void si_destroy_shader_cache(struct si_screen *sscreen)
316 {
317 if (sscreen->shader_cache)
318 _mesa_hash_table_destroy(sscreen->shader_cache,
319 si_destroy_shader_cache_entry);
320 mtx_destroy(&sscreen->shader_cache_mutex);
321 }
322
323 /* SHADER STATES */
324
325 static void si_set_tesseval_regs(struct si_screen *sscreen,
326 struct si_shader *shader,
327 struct si_pm4_state *pm4)
328 {
329 struct tgsi_shader_info *info = &shader->selector->info;
330 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
331 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
332 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
333 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
334 unsigned type, partitioning, topology, distribution_mode;
335
336 switch (tes_prim_mode) {
337 case PIPE_PRIM_LINES:
338 type = V_028B6C_TESS_ISOLINE;
339 break;
340 case PIPE_PRIM_TRIANGLES:
341 type = V_028B6C_TESS_TRIANGLE;
342 break;
343 case PIPE_PRIM_QUADS:
344 type = V_028B6C_TESS_QUAD;
345 break;
346 default:
347 assert(0);
348 return;
349 }
350
351 switch (tes_spacing) {
352 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
353 partitioning = V_028B6C_PART_FRAC_ODD;
354 break;
355 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
356 partitioning = V_028B6C_PART_FRAC_EVEN;
357 break;
358 case PIPE_TESS_SPACING_EQUAL:
359 partitioning = V_028B6C_PART_INTEGER;
360 break;
361 default:
362 assert(0);
363 return;
364 }
365
366 if (tes_point_mode)
367 topology = V_028B6C_OUTPUT_POINT;
368 else if (tes_prim_mode == PIPE_PRIM_LINES)
369 topology = V_028B6C_OUTPUT_LINE;
370 else if (tes_vertex_order_cw)
371 /* for some reason, this must be the other way around */
372 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
373 else
374 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
375
376 if (sscreen->has_distributed_tess) {
377 if (sscreen->b.family == CHIP_FIJI ||
378 sscreen->b.family >= CHIP_POLARIS10)
379 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
380 else
381 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
382 } else
383 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
384
385 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
386 S_028B6C_TYPE(type) |
387 S_028B6C_PARTITIONING(partitioning) |
388 S_028B6C_TOPOLOGY(topology) |
389 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
390 }
391
392 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
393 * whether the "fractional odd" tessellation spacing is used.
394 *
395 * Possible VGT configurations and which state should set the register:
396 *
397 * Reg set in | VGT shader configuration | Value
398 * ------------------------------------------------------
399 * VS as VS | VS | 30
400 * VS as ES | ES -> GS -> VS | 30
401 * TES as VS | LS -> HS -> VS | 14 or 30
402 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
403 */
404 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
405 struct si_shader *shader,
406 struct si_pm4_state *pm4)
407 {
408 unsigned type = shader->selector->type;
409
410 if (sscreen->b.family < CHIP_POLARIS10)
411 return;
412
413 /* VS as VS, or VS as ES: */
414 if ((type == PIPE_SHADER_VERTEX &&
415 !shader->key.as_ls &&
416 !shader->is_gs_copy_shader) ||
417 /* TES as VS, or TES as ES: */
418 type == PIPE_SHADER_TESS_EVAL) {
419 unsigned vtx_reuse_depth = 30;
420
421 if (type == PIPE_SHADER_TESS_EVAL &&
422 shader->selector->info.properties[TGSI_PROPERTY_TES_SPACING] ==
423 PIPE_TESS_SPACING_FRACTIONAL_ODD)
424 vtx_reuse_depth = 14;
425
426 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
427 vtx_reuse_depth);
428 }
429 }
430
431 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
432 {
433 if (shader->pm4)
434 si_pm4_clear_state(shader->pm4);
435 else
436 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
437
438 return shader->pm4;
439 }
440
441 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
442 {
443 struct si_pm4_state *pm4;
444 unsigned vgpr_comp_cnt;
445 uint64_t va;
446
447 assert(sscreen->b.chip_class <= VI);
448
449 pm4 = si_get_shader_pm4_state(shader);
450 if (!pm4)
451 return;
452
453 va = shader->bo->gpu_address;
454 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
455
456 /* We need at least 2 components for LS.
457 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
458 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 1;
459
460 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
461 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
462
463 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
464 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
465 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
466 S_00B528_DX10_CLAMP(1) |
467 S_00B528_FLOAT_MODE(shader->config.float_mode);
468 shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_VS_NUM_USER_SGPR) |
469 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
470 }
471
472 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
473 {
474 struct si_pm4_state *pm4;
475 uint64_t va;
476
477 pm4 = si_get_shader_pm4_state(shader);
478 if (!pm4)
479 return;
480
481 va = shader->bo->gpu_address;
482 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
483
484 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
485 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
486 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
487 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
488 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
489 S_00B428_DX10_CLAMP(1) |
490 S_00B428_FLOAT_MODE(shader->config.float_mode));
491 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
492 S_00B42C_USER_SGPR(SI_TCS_NUM_USER_SGPR) |
493 S_00B42C_OC_LDS_EN(sscreen->b.chip_class <= VI) |
494 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
495 }
496
497 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
498 {
499 struct si_pm4_state *pm4;
500 unsigned num_user_sgprs;
501 unsigned vgpr_comp_cnt;
502 uint64_t va;
503 unsigned oc_lds_en;
504
505 assert(sscreen->b.chip_class <= VI);
506
507 pm4 = si_get_shader_pm4_state(shader);
508 if (!pm4)
509 return;
510
511 va = shader->bo->gpu_address;
512 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
513
514 if (shader->selector->type == PIPE_SHADER_VERTEX) {
515 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
516 num_user_sgprs = SI_VS_NUM_USER_SGPR;
517 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
518 vgpr_comp_cnt = 3; /* all components are needed for TES */
519 num_user_sgprs = SI_TES_NUM_USER_SGPR;
520 } else
521 unreachable("invalid shader selector type");
522
523 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
524
525 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
526 shader->selector->esgs_itemsize / 4);
527 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
528 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
529 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
530 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
531 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
532 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
533 S_00B328_DX10_CLAMP(1) |
534 S_00B328_FLOAT_MODE(shader->config.float_mode));
535 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
536 S_00B32C_USER_SGPR(num_user_sgprs) |
537 S_00B32C_OC_LDS_EN(oc_lds_en) |
538 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
539
540 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
541 si_set_tesseval_regs(sscreen, shader, pm4);
542
543 polaris_set_vgt_vertex_reuse(sscreen, shader, pm4);
544 }
545
546 /**
547 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
548 * geometry shader.
549 */
550 static uint32_t si_vgt_gs_mode(struct si_shader_selector *sel)
551 {
552 unsigned gs_max_vert_out = sel->gs_max_out_vertices;
553 unsigned cut_mode;
554
555 if (gs_max_vert_out <= 128) {
556 cut_mode = V_028A40_GS_CUT_128;
557 } else if (gs_max_vert_out <= 256) {
558 cut_mode = V_028A40_GS_CUT_256;
559 } else if (gs_max_vert_out <= 512) {
560 cut_mode = V_028A40_GS_CUT_512;
561 } else {
562 assert(gs_max_vert_out <= 1024);
563 cut_mode = V_028A40_GS_CUT_1024;
564 }
565
566 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
567 S_028A40_CUT_MODE(cut_mode)|
568 S_028A40_ES_WRITE_OPTIMIZE(1) |
569 S_028A40_GS_WRITE_OPTIMIZE(1);
570 }
571
572 static void si_shader_gs(struct si_shader *shader)
573 {
574 struct si_shader_selector *sel = shader->selector;
575 const ubyte *num_components = sel->info.num_stream_output_components;
576 unsigned gs_num_invocations = sel->gs_num_invocations;
577 struct si_pm4_state *pm4;
578 uint64_t va;
579 unsigned max_stream = sel->max_gs_stream;
580 unsigned offset;
581
582 pm4 = si_get_shader_pm4_state(shader);
583 if (!pm4)
584 return;
585
586 offset = num_components[0] * sel->gs_max_out_vertices;
587 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, offset);
588 if (max_stream >= 1)
589 offset += num_components[1] * sel->gs_max_out_vertices;
590 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, offset);
591 if (max_stream >= 2)
592 offset += num_components[2] * sel->gs_max_out_vertices;
593 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, offset);
594 if (max_stream >= 3)
595 offset += num_components[3] * sel->gs_max_out_vertices;
596 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
597
598 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
599 assert(offset < (1 << 15));
600
601 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, shader->selector->gs_max_out_vertices);
602
603 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, num_components[0]);
604 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? num_components[1] : 0);
605 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? num_components[2] : 0);
606 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? num_components[3] : 0);
607
608 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
609 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
610 S_028B90_ENABLE(gs_num_invocations > 0));
611
612 va = shader->bo->gpu_address;
613 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
614 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
615 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
616
617 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
618 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
619 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
620 S_00B228_DX10_CLAMP(1) |
621 S_00B228_FLOAT_MODE(shader->config.float_mode));
622 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
623 S_00B22C_USER_SGPR(SI_GS_NUM_USER_SGPR) |
624 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
625 }
626
627 /**
628 * Compute the state for \p shader, which will run as a vertex shader on the
629 * hardware.
630 *
631 * If \p gs is non-NULL, it points to the geometry shader for which this shader
632 * is the copy shader.
633 */
634 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
635 struct si_shader_selector *gs)
636 {
637 struct si_pm4_state *pm4;
638 unsigned num_user_sgprs;
639 unsigned nparams, vgpr_comp_cnt;
640 uint64_t va;
641 unsigned oc_lds_en;
642 unsigned window_space =
643 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
644 bool enable_prim_id = si_vs_exports_prim_id(shader);
645
646 pm4 = si_get_shader_pm4_state(shader);
647 if (!pm4)
648 return;
649
650 /* We always write VGT_GS_MODE in the VS state, because every switch
651 * between different shader pipelines involving a different GS or no
652 * GS at all involves a switch of the VS (different GS use different
653 * copy shaders). On the other hand, when the API switches from a GS to
654 * no GS and then back to the same GS used originally, the GS state is
655 * not sent again.
656 */
657 if (!gs) {
658 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
659 S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
660 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
661 } else {
662 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
663 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
664 }
665
666 va = shader->bo->gpu_address;
667 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
668
669 if (gs) {
670 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
671 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
672 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
673 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
674 num_user_sgprs = SI_VS_NUM_USER_SGPR;
675 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
676 vgpr_comp_cnt = 3; /* all components are needed for TES */
677 num_user_sgprs = SI_TES_NUM_USER_SGPR;
678 } else
679 unreachable("invalid shader selector type");
680
681 /* VS is required to export at least one param. */
682 nparams = MAX2(shader->info.nr_param_exports, 1);
683 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
684 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
685
686 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
687 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
688 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
689 V_02870C_SPI_SHADER_4COMP :
690 V_02870C_SPI_SHADER_NONE) |
691 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
692 V_02870C_SPI_SHADER_4COMP :
693 V_02870C_SPI_SHADER_NONE) |
694 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
695 V_02870C_SPI_SHADER_4COMP :
696 V_02870C_SPI_SHADER_NONE));
697
698 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
699
700 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
701 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
702 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
703 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
704 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
705 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
706 S_00B128_DX10_CLAMP(1) |
707 S_00B128_FLOAT_MODE(shader->config.float_mode));
708 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
709 S_00B12C_USER_SGPR(num_user_sgprs) |
710 S_00B12C_OC_LDS_EN(oc_lds_en) |
711 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
712 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
713 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
714 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
715 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
716 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
717 if (window_space)
718 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
719 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
720 else
721 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
722 S_028818_VTX_W0_FMT(1) |
723 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
724 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
725 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
726
727 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
728 si_set_tesseval_regs(sscreen, shader, pm4);
729
730 polaris_set_vgt_vertex_reuse(sscreen, shader, pm4);
731 }
732
733 static unsigned si_get_ps_num_interp(struct si_shader *ps)
734 {
735 struct tgsi_shader_info *info = &ps->selector->info;
736 unsigned num_colors = !!(info->colors_read & 0x0f) +
737 !!(info->colors_read & 0xf0);
738 unsigned num_interp = ps->selector->info.num_inputs +
739 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
740
741 assert(num_interp <= 32);
742 return MIN2(num_interp, 32);
743 }
744
745 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
746 {
747 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
748 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
749
750 /* If the i-th target format is set, all previous target formats must
751 * be non-zero to avoid hangs.
752 */
753 for (i = 0; i < num_targets; i++)
754 if (!(value & (0xf << (i * 4))))
755 value |= V_028714_SPI_SHADER_32_R << (i * 4);
756
757 return value;
758 }
759
760 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
761 {
762 unsigned i, cb_shader_mask = 0;
763
764 for (i = 0; i < 8; i++) {
765 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
766 case V_028714_SPI_SHADER_ZERO:
767 break;
768 case V_028714_SPI_SHADER_32_R:
769 cb_shader_mask |= 0x1 << (i * 4);
770 break;
771 case V_028714_SPI_SHADER_32_GR:
772 cb_shader_mask |= 0x3 << (i * 4);
773 break;
774 case V_028714_SPI_SHADER_32_AR:
775 cb_shader_mask |= 0x9 << (i * 4);
776 break;
777 case V_028714_SPI_SHADER_FP16_ABGR:
778 case V_028714_SPI_SHADER_UNORM16_ABGR:
779 case V_028714_SPI_SHADER_SNORM16_ABGR:
780 case V_028714_SPI_SHADER_UINT16_ABGR:
781 case V_028714_SPI_SHADER_SINT16_ABGR:
782 case V_028714_SPI_SHADER_32_ABGR:
783 cb_shader_mask |= 0xf << (i * 4);
784 break;
785 default:
786 assert(0);
787 }
788 }
789 return cb_shader_mask;
790 }
791
792 static void si_shader_ps(struct si_shader *shader)
793 {
794 struct tgsi_shader_info *info = &shader->selector->info;
795 struct si_pm4_state *pm4;
796 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
797 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
798 uint64_t va;
799 unsigned input_ena = shader->config.spi_ps_input_ena;
800
801 /* we need to enable at least one of them, otherwise we hang the GPU */
802 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
803 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
804 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
805 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
806 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
807 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
808 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
809 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
810 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
811 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
812 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
813 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
814 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
815 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
816
817 /* Validate interpolation optimization flags (read as implications). */
818 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
819 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
820 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
821 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
822 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
823 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
824 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
825 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
826 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
827 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
828 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
829 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
830 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
831 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
832 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
833 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
834 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
835 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
836
837 /* Validate cases when the optimizations are off (read as implications). */
838 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
839 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
840 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
841 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
842 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
843 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
844
845 pm4 = si_get_shader_pm4_state(shader);
846 if (!pm4)
847 return;
848
849 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
850 * Possible vaules:
851 * 0 -> Position = pixel center
852 * 1 -> Position = pixel centroid
853 * 2 -> Position = at sample position
854 *
855 * From GLSL 4.5 specification, section 7.1:
856 * "The variable gl_FragCoord is available as an input variable from
857 * within fragment shaders and it holds the window relative coordinates
858 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
859 * value can be for any location within the pixel, or one of the
860 * fragment samples. The use of centroid does not further restrict
861 * this value to be inside the current primitive."
862 *
863 * Meaning that centroid has no effect and we can return anything within
864 * the pixel. Thus, return the value at sample position, because that's
865 * the most accurate one shaders can get.
866 */
867 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
868
869 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
870 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
871 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
872
873 spi_shader_col_format = si_get_spi_shader_col_format(shader);
874 cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
875
876 /* Ensure that some export memory is always allocated, for two reasons:
877 *
878 * 1) Correctness: The hardware ignores the EXEC mask if no export
879 * memory is allocated, so KILL and alpha test do not work correctly
880 * without this.
881 * 2) Performance: Every shader needs at least a NULL export, even when
882 * it writes no color/depth output. The NULL export instruction
883 * stalls without this setting.
884 *
885 * Don't add this to CB_SHADER_MASK.
886 */
887 if (!spi_shader_col_format &&
888 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
889 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
890
891 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
892 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
893 shader->config.spi_ps_input_addr);
894
895 /* Set interpolation controls. */
896 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
897
898 /* Set registers. */
899 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
900 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
901
902 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
903 si_get_spi_shader_z_format(info->writes_z,
904 info->writes_stencil,
905 info->writes_samplemask));
906
907 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
908 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
909
910 va = shader->bo->gpu_address;
911 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
912 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
913 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
914
915 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
916 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
917 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
918 S_00B028_DX10_CLAMP(1) |
919 S_00B028_FLOAT_MODE(shader->config.float_mode));
920 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
921 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
922 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
923 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
924 }
925
926 static void si_shader_init_pm4_state(struct si_screen *sscreen,
927 struct si_shader *shader)
928 {
929 switch (shader->selector->type) {
930 case PIPE_SHADER_VERTEX:
931 if (shader->key.as_ls)
932 si_shader_ls(sscreen, shader);
933 else if (shader->key.as_es)
934 si_shader_es(sscreen, shader);
935 else
936 si_shader_vs(sscreen, shader, NULL);
937 break;
938 case PIPE_SHADER_TESS_CTRL:
939 si_shader_hs(sscreen, shader);
940 break;
941 case PIPE_SHADER_TESS_EVAL:
942 if (shader->key.as_es)
943 si_shader_es(sscreen, shader);
944 else
945 si_shader_vs(sscreen, shader, NULL);
946 break;
947 case PIPE_SHADER_GEOMETRY:
948 si_shader_gs(shader);
949 break;
950 case PIPE_SHADER_FRAGMENT:
951 si_shader_ps(shader);
952 break;
953 default:
954 assert(0);
955 }
956 }
957
958 static unsigned si_get_alpha_test_func(struct si_context *sctx)
959 {
960 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
961 if (sctx->queued.named.dsa)
962 return sctx->queued.named.dsa->alpha_func;
963
964 return PIPE_FUNC_ALWAYS;
965 }
966
967 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
968 struct si_shader_selector *vs,
969 struct si_shader_key *key)
970 {
971 struct si_shader_selector *ps = sctx->ps_shader.cso;
972
973 key->opt.hw_vs.clip_disable =
974 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
975 (vs->info.clipdist_writemask ||
976 vs->info.writes_clipvertex) &&
977 !vs->info.culldist_writemask;
978
979 /* Find out if PS is disabled. */
980 bool ps_disabled = true;
981 if (ps) {
982 bool ps_modifies_zs = ps->info.uses_kill ||
983 ps->info.writes_z ||
984 ps->info.writes_stencil ||
985 ps->info.writes_samplemask ||
986 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
987
988 unsigned ps_colormask = sctx->framebuffer.colorbuf_enabled_4bit &
989 sctx->queued.named.blend->cb_target_mask;
990 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
991 ps_colormask &= ps->colors_written_4bit;
992
993 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
994 (!ps_colormask &&
995 !ps_modifies_zs &&
996 !ps->info.writes_memory);
997 }
998
999 /* Find out which VS outputs aren't used by the PS. */
1000 uint64_t outputs_written = vs->outputs_written;
1001 uint32_t outputs_written2 = vs->outputs_written2;
1002 uint64_t inputs_read = 0;
1003 uint32_t inputs_read2 = 0;
1004
1005 outputs_written &= ~0x3; /* ignore POSITION, PSIZE */
1006
1007 if (!ps_disabled) {
1008 inputs_read = ps->inputs_read;
1009 inputs_read2 = ps->inputs_read2;
1010 }
1011
1012 uint64_t linked = outputs_written & inputs_read;
1013 uint32_t linked2 = outputs_written2 & inputs_read2;
1014
1015 key->opt.hw_vs.kill_outputs = ~linked & outputs_written;
1016 key->opt.hw_vs.kill_outputs2 = ~linked2 & outputs_written2;
1017 }
1018
1019 /* Compute the key for the hw shader variant */
1020 static inline void si_shader_selector_key(struct pipe_context *ctx,
1021 struct si_shader_selector *sel,
1022 struct si_shader_key *key)
1023 {
1024 struct si_context *sctx = (struct si_context *)ctx;
1025 unsigned i;
1026
1027 memset(key, 0, sizeof(*key));
1028
1029 switch (sel->type) {
1030 case PIPE_SHADER_VERTEX:
1031 if (sctx->vertex_elements) {
1032 unsigned count = MIN2(sel->info.num_inputs,
1033 sctx->vertex_elements->count);
1034 for (i = 0; i < count; ++i)
1035 key->part.vs.prolog.instance_divisors[i] =
1036 sctx->vertex_elements->elements[i].instance_divisor;
1037
1038 memcpy(key->mono.vs_fix_fetch,
1039 sctx->vertex_elements->fix_fetch, count);
1040 }
1041 if (sctx->tes_shader.cso)
1042 key->as_ls = 1;
1043 else if (sctx->gs_shader.cso)
1044 key->as_es = 1;
1045 else {
1046 si_shader_selector_key_hw_vs(sctx, sel, key);
1047
1048 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1049 key->part.vs.epilog.export_prim_id = 1;
1050 }
1051 break;
1052 case PIPE_SHADER_TESS_CTRL:
1053 key->part.tcs.epilog.prim_mode =
1054 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1055 key->part.tcs.epilog.tes_reads_tess_factors =
1056 sctx->tes_shader.cso->info.reads_tess_factors;
1057
1058 if (sel == sctx->fixed_func_tcs_shader.cso)
1059 key->mono.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1060 break;
1061 case PIPE_SHADER_TESS_EVAL:
1062 if (sctx->gs_shader.cso)
1063 key->as_es = 1;
1064 else {
1065 si_shader_selector_key_hw_vs(sctx, sel, key);
1066
1067 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1068 key->part.tes.epilog.export_prim_id = 1;
1069 }
1070 break;
1071 case PIPE_SHADER_GEOMETRY:
1072 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1073 break;
1074 case PIPE_SHADER_FRAGMENT: {
1075 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1076 struct si_state_blend *blend = sctx->queued.named.blend;
1077
1078 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1079 sel->info.colors_written == 0x1)
1080 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1081
1082 if (blend) {
1083 /* Select the shader color format based on whether
1084 * blending or alpha are needed.
1085 */
1086 key->part.ps.epilog.spi_shader_col_format =
1087 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1088 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1089 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1090 sctx->framebuffer.spi_shader_col_format_blend) |
1091 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1092 sctx->framebuffer.spi_shader_col_format_alpha) |
1093 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1094 sctx->framebuffer.spi_shader_col_format);
1095
1096 /* The output for dual source blending should have
1097 * the same format as the first output.
1098 */
1099 if (blend->dual_src_blend)
1100 key->part.ps.epilog.spi_shader_col_format |=
1101 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1102 } else
1103 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1104
1105 /* If alpha-to-coverage is enabled, we have to export alpha
1106 * even if there is no color buffer.
1107 */
1108 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1109 blend && blend->alpha_to_coverage)
1110 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1111
1112 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1113 * to the range supported by the type if a channel has less
1114 * than 16 bits and the export format is 16_ABGR.
1115 */
1116 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII) {
1117 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1118 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1119 }
1120
1121 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1122 if (!key->part.ps.epilog.last_cbuf) {
1123 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1124 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1125 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1126 }
1127
1128 if (rs) {
1129 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
1130 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
1131 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
1132 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
1133
1134 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1135 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1136
1137 if (sctx->queued.named.blend) {
1138 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1139 rs->multisample_enable;
1140 }
1141
1142 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1143 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1144 (is_line && rs->line_smooth)) &&
1145 sctx->framebuffer.nr_samples <= 1;
1146 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1147
1148 if (rs->force_persample_interp &&
1149 rs->multisample_enable &&
1150 sctx->framebuffer.nr_samples > 1 &&
1151 sctx->ps_iter_samples > 1) {
1152 key->part.ps.prolog.force_persp_sample_interp =
1153 sel->info.uses_persp_center ||
1154 sel->info.uses_persp_centroid;
1155
1156 key->part.ps.prolog.force_linear_sample_interp =
1157 sel->info.uses_linear_center ||
1158 sel->info.uses_linear_centroid;
1159 } else if (rs->multisample_enable &&
1160 sctx->framebuffer.nr_samples > 1) {
1161 key->part.ps.prolog.bc_optimize_for_persp =
1162 sel->info.uses_persp_center &&
1163 sel->info.uses_persp_centroid;
1164 key->part.ps.prolog.bc_optimize_for_linear =
1165 sel->info.uses_linear_center &&
1166 sel->info.uses_linear_centroid;
1167 } else {
1168 /* Make sure SPI doesn't compute more than 1 pair
1169 * of (i,j), which is the optimization here. */
1170 key->part.ps.prolog.force_persp_center_interp =
1171 sel->info.uses_persp_center +
1172 sel->info.uses_persp_centroid +
1173 sel->info.uses_persp_sample > 1;
1174
1175 key->part.ps.prolog.force_linear_center_interp =
1176 sel->info.uses_linear_center +
1177 sel->info.uses_linear_centroid +
1178 sel->info.uses_linear_sample > 1;
1179 }
1180 }
1181
1182 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1183 break;
1184 }
1185 default:
1186 assert(0);
1187 }
1188 }
1189
1190 static void si_build_shader_variant(void *job, int thread_index)
1191 {
1192 struct si_shader *shader = (struct si_shader *)job;
1193 struct si_shader_selector *sel = shader->selector;
1194 struct si_screen *sscreen = sel->screen;
1195 LLVMTargetMachineRef tm;
1196 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1197 int r;
1198
1199 if (thread_index >= 0) {
1200 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1201 tm = sscreen->tm[thread_index];
1202 if (!debug->async)
1203 debug = NULL;
1204 } else {
1205 tm = shader->compiler_ctx_state.tm;
1206 }
1207
1208 r = si_shader_create(sscreen, tm, shader, debug);
1209 if (unlikely(r)) {
1210 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1211 sel->type, r);
1212 shader->compilation_failed = true;
1213 return;
1214 }
1215
1216 if (shader->compiler_ctx_state.is_debug_context) {
1217 FILE *f = open_memstream(&shader->shader_log,
1218 &shader->shader_log_size);
1219 if (f) {
1220 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1221 fclose(f);
1222 }
1223 }
1224
1225 si_shader_init_pm4_state(sscreen, shader);
1226 }
1227
1228 /* Select the hw shader variant depending on the current state. */
1229 static int si_shader_select_with_key(struct si_screen *sscreen,
1230 struct si_shader_ctx_state *state,
1231 struct si_compiler_ctx_state *compiler_state,
1232 struct si_shader_key *key,
1233 int thread_index)
1234 {
1235 static const struct si_shader_key zeroed;
1236 struct si_shader_selector *sel = state->cso;
1237 struct si_shader *current = state->current;
1238 struct si_shader *iter, *shader = NULL;
1239
1240 if (unlikely(sscreen->b.debug_flags & DBG_NO_OPT_VARIANT)) {
1241 memset(&key->opt, 0, sizeof(key->opt));
1242 }
1243
1244 again:
1245 /* Check if we don't need to change anything.
1246 * This path is also used for most shaders that don't need multiple
1247 * variants, it will cost just a computation of the key and this
1248 * test. */
1249 if (likely(current &&
1250 memcmp(&current->key, key, sizeof(*key)) == 0 &&
1251 (!current->is_optimized ||
1252 util_queue_fence_is_signalled(&current->optimized_ready))))
1253 return current->compilation_failed ? -1 : 0;
1254
1255 /* This must be done before the mutex is locked, because async GS
1256 * compilation calls this function too, and therefore must enter
1257 * the mutex first.
1258 *
1259 * Only wait if we are in a draw call. Don't wait if we are
1260 * in a compiler thread.
1261 */
1262 if (thread_index < 0)
1263 util_queue_fence_wait(&sel->ready);
1264
1265 mtx_lock(&sel->mutex);
1266
1267 /* Find the shader variant. */
1268 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1269 /* Don't check the "current" shader. We checked it above. */
1270 if (current != iter &&
1271 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1272 /* If it's an optimized shader and its compilation has
1273 * been started but isn't done, use the unoptimized
1274 * shader so as not to cause a stall due to compilation.
1275 */
1276 if (iter->is_optimized &&
1277 !util_queue_fence_is_signalled(&iter->optimized_ready)) {
1278 memset(&key->opt, 0, sizeof(key->opt));
1279 mtx_unlock(&sel->mutex);
1280 goto again;
1281 }
1282
1283 if (iter->compilation_failed) {
1284 mtx_unlock(&sel->mutex);
1285 return -1; /* skip the draw call */
1286 }
1287
1288 state->current = iter;
1289 mtx_unlock(&sel->mutex);
1290 return 0;
1291 }
1292 }
1293
1294 /* Build a new shader. */
1295 shader = CALLOC_STRUCT(si_shader);
1296 if (!shader) {
1297 mtx_unlock(&sel->mutex);
1298 return -ENOMEM;
1299 }
1300 shader->selector = sel;
1301 shader->key = *key;
1302 shader->compiler_ctx_state = *compiler_state;
1303
1304 /* Compile the main shader part if it doesn't exist. This can happen
1305 * if the initial guess was wrong. */
1306 struct si_shader **mainp = si_get_main_shader_part(sel, key);
1307 bool is_pure_monolithic =
1308 sscreen->use_monolithic_shaders ||
1309 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1310
1311 if (!*mainp && !is_pure_monolithic) {
1312 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1313
1314 if (!main_part) {
1315 FREE(shader);
1316 mtx_unlock(&sel->mutex);
1317 return -ENOMEM; /* skip the draw call */
1318 }
1319
1320 main_part->selector = sel;
1321 main_part->key.as_es = key->as_es;
1322 main_part->key.as_ls = key->as_ls;
1323
1324 if (si_compile_tgsi_shader(sscreen, compiler_state->tm,
1325 main_part, false,
1326 &compiler_state->debug) != 0) {
1327 FREE(main_part);
1328 FREE(shader);
1329 mtx_unlock(&sel->mutex);
1330 return -ENOMEM; /* skip the draw call */
1331 }
1332 *mainp = main_part;
1333 }
1334
1335 /* Monolithic-only shaders don't make a distinction between optimized
1336 * and unoptimized. */
1337 shader->is_monolithic =
1338 is_pure_monolithic ||
1339 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1340
1341 shader->is_optimized =
1342 !is_pure_monolithic &&
1343 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1344 if (shader->is_optimized)
1345 util_queue_fence_init(&shader->optimized_ready);
1346
1347 if (!sel->last_variant) {
1348 sel->first_variant = shader;
1349 sel->last_variant = shader;
1350 } else {
1351 sel->last_variant->next_variant = shader;
1352 sel->last_variant = shader;
1353 }
1354
1355 /* If it's an optimized shader, compile it asynchronously. */
1356 if (shader->is_optimized &&
1357 !is_pure_monolithic &&
1358 thread_index < 0) {
1359 /* Compile it asynchronously. */
1360 util_queue_add_job(&sscreen->shader_compiler_queue,
1361 shader, &shader->optimized_ready,
1362 si_build_shader_variant, NULL);
1363
1364 /* Use the default (unoptimized) shader for now. */
1365 memset(&key->opt, 0, sizeof(key->opt));
1366 mtx_unlock(&sel->mutex);
1367 goto again;
1368 }
1369
1370 assert(!shader->is_optimized);
1371 si_build_shader_variant(shader, thread_index);
1372
1373 if (!shader->compilation_failed)
1374 state->current = shader;
1375
1376 mtx_unlock(&sel->mutex);
1377 return shader->compilation_failed ? -1 : 0;
1378 }
1379
1380 static int si_shader_select(struct pipe_context *ctx,
1381 struct si_shader_ctx_state *state,
1382 struct si_compiler_ctx_state *compiler_state)
1383 {
1384 struct si_context *sctx = (struct si_context *)ctx;
1385 struct si_shader_key key;
1386
1387 si_shader_selector_key(ctx, state->cso, &key);
1388 return si_shader_select_with_key(sctx->screen, state, compiler_state,
1389 &key, -1);
1390 }
1391
1392 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1393 struct si_shader_key *key)
1394 {
1395 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1396
1397 switch (info->processor) {
1398 case PIPE_SHADER_VERTEX:
1399 switch (next_shader) {
1400 case PIPE_SHADER_GEOMETRY:
1401 key->as_es = 1;
1402 break;
1403 case PIPE_SHADER_TESS_CTRL:
1404 case PIPE_SHADER_TESS_EVAL:
1405 key->as_ls = 1;
1406 break;
1407 default:
1408 /* If POSITION isn't written, it can't be a HW VS.
1409 * Assume that it's a HW LS. (the next shader is TCS)
1410 * This heuristic is needed for separate shader objects.
1411 */
1412 if (!info->writes_position)
1413 key->as_ls = 1;
1414 }
1415 break;
1416
1417 case PIPE_SHADER_TESS_EVAL:
1418 if (next_shader == PIPE_SHADER_GEOMETRY ||
1419 !info->writes_position)
1420 key->as_es = 1;
1421 break;
1422 }
1423 }
1424
1425 /**
1426 * Compile the main shader part or the monolithic shader as part of
1427 * si_shader_selector initialization. Since it can be done asynchronously,
1428 * there is no way to report compile failures to applications.
1429 */
1430 void si_init_shader_selector_async(void *job, int thread_index)
1431 {
1432 struct si_shader_selector *sel = (struct si_shader_selector *)job;
1433 struct si_screen *sscreen = sel->screen;
1434 LLVMTargetMachineRef tm;
1435 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
1436 unsigned i;
1437
1438 if (thread_index >= 0) {
1439 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1440 tm = sscreen->tm[thread_index];
1441 if (!debug->async)
1442 debug = NULL;
1443 } else {
1444 tm = sel->compiler_ctx_state.tm;
1445 }
1446
1447 /* Compile the main shader part for use with a prolog and/or epilog.
1448 * If this fails, the driver will try to compile a monolithic shader
1449 * on demand.
1450 */
1451 if (!sscreen->use_monolithic_shaders) {
1452 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1453 void *tgsi_binary;
1454
1455 if (!shader) {
1456 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
1457 return;
1458 }
1459
1460 shader->selector = sel;
1461 si_parse_next_shader_property(&sel->info, &shader->key);
1462
1463 tgsi_binary = si_get_tgsi_binary(sel);
1464
1465 /* Try to load the shader from the shader cache. */
1466 mtx_lock(&sscreen->shader_cache_mutex);
1467
1468 if (tgsi_binary &&
1469 si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
1470 mtx_unlock(&sscreen->shader_cache_mutex);
1471 } else {
1472 mtx_unlock(&sscreen->shader_cache_mutex);
1473
1474 /* Compile the shader if it hasn't been loaded from the cache. */
1475 if (si_compile_tgsi_shader(sscreen, tm, shader, false,
1476 debug) != 0) {
1477 FREE(shader);
1478 FREE(tgsi_binary);
1479 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
1480 return;
1481 }
1482
1483 if (tgsi_binary) {
1484 mtx_lock(&sscreen->shader_cache_mutex);
1485 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary, shader, true))
1486 FREE(tgsi_binary);
1487 mtx_unlock(&sscreen->shader_cache_mutex);
1488 }
1489 }
1490
1491 *si_get_main_shader_part(sel, &shader->key) = shader;
1492
1493 /* Unset "outputs_written" flags for outputs converted to
1494 * DEFAULT_VAL, so that later inter-shader optimizations don't
1495 * try to eliminate outputs that don't exist in the final
1496 * shader.
1497 *
1498 * This is only done if non-monolithic shaders are enabled.
1499 */
1500 if ((sel->type == PIPE_SHADER_VERTEX ||
1501 sel->type == PIPE_SHADER_TESS_EVAL) &&
1502 !shader->key.as_ls &&
1503 !shader->key.as_es) {
1504 unsigned i;
1505
1506 for (i = 0; i < sel->info.num_outputs; i++) {
1507 unsigned offset = shader->info.vs_output_param_offset[i];
1508
1509 if (offset <= EXP_PARAM_OFFSET_31)
1510 continue;
1511
1512 unsigned name = sel->info.output_semantic_name[i];
1513 unsigned index = sel->info.output_semantic_index[i];
1514 unsigned id;
1515
1516 switch (name) {
1517 case TGSI_SEMANTIC_GENERIC:
1518 /* don't process indices the function can't handle */
1519 if (index >= 60)
1520 break;
1521 /* fall through */
1522 case TGSI_SEMANTIC_CLIPDIST:
1523 id = si_shader_io_get_unique_index(name, index);
1524 sel->outputs_written &= ~(1ull << id);
1525 break;
1526 case TGSI_SEMANTIC_POSITION: /* ignore these */
1527 case TGSI_SEMANTIC_PSIZE:
1528 case TGSI_SEMANTIC_CLIPVERTEX:
1529 case TGSI_SEMANTIC_EDGEFLAG:
1530 break;
1531 default:
1532 id = si_shader_io_get_unique_index2(name, index);
1533 sel->outputs_written2 &= ~(1u << id);
1534 }
1535 }
1536 }
1537 }
1538
1539 /* Pre-compilation. */
1540 if (sscreen->b.debug_flags & DBG_PRECOMPILE) {
1541 struct si_shader_ctx_state state = {sel};
1542 struct si_shader_key key;
1543
1544 memset(&key, 0, sizeof(key));
1545 si_parse_next_shader_property(&sel->info, &key);
1546
1547 /* Set reasonable defaults, so that the shader key doesn't
1548 * cause any code to be eliminated.
1549 */
1550 switch (sel->type) {
1551 case PIPE_SHADER_TESS_CTRL:
1552 key.part.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
1553 break;
1554 case PIPE_SHADER_FRAGMENT:
1555 key.part.ps.prolog.bc_optimize_for_persp =
1556 sel->info.uses_persp_center &&
1557 sel->info.uses_persp_centroid;
1558 key.part.ps.prolog.bc_optimize_for_linear =
1559 sel->info.uses_linear_center &&
1560 sel->info.uses_linear_centroid;
1561 key.part.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
1562 for (i = 0; i < 8; i++)
1563 if (sel->info.colors_written & (1 << i))
1564 key.part.ps.epilog.spi_shader_col_format |=
1565 V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
1566 break;
1567 }
1568
1569 if (si_shader_select_with_key(sscreen, &state,
1570 &sel->compiler_ctx_state, &key,
1571 thread_index))
1572 fprintf(stderr, "radeonsi: can't create a monolithic shader\n");
1573 }
1574
1575 /* The GS copy shader is always pre-compiled. */
1576 if (sel->type == PIPE_SHADER_GEOMETRY) {
1577 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, tm, sel, debug);
1578 if (!sel->gs_copy_shader) {
1579 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
1580 return;
1581 }
1582
1583 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
1584 }
1585 }
1586
1587 static void *si_create_shader_selector(struct pipe_context *ctx,
1588 const struct pipe_shader_state *state)
1589 {
1590 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
1591 struct si_context *sctx = (struct si_context*)ctx;
1592 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
1593 int i;
1594
1595 if (!sel)
1596 return NULL;
1597
1598 sel->screen = sscreen;
1599 sel->compiler_ctx_state.tm = sctx->tm;
1600 sel->compiler_ctx_state.debug = sctx->b.debug;
1601 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
1602 sel->tokens = tgsi_dup_tokens(state->tokens);
1603 if (!sel->tokens) {
1604 FREE(sel);
1605 return NULL;
1606 }
1607
1608 sel->so = state->stream_output;
1609 tgsi_scan_shader(state->tokens, &sel->info);
1610 sel->type = sel->info.processor;
1611 p_atomic_inc(&sscreen->b.num_shaders_created);
1612
1613 /* The prolog is a no-op if there are no inputs. */
1614 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
1615 sel->info.num_inputs;
1616
1617 /* Set which opcode uses which (i,j) pair. */
1618 if (sel->info.uses_persp_opcode_interp_centroid)
1619 sel->info.uses_persp_centroid = true;
1620
1621 if (sel->info.uses_linear_opcode_interp_centroid)
1622 sel->info.uses_linear_centroid = true;
1623
1624 if (sel->info.uses_persp_opcode_interp_offset ||
1625 sel->info.uses_persp_opcode_interp_sample)
1626 sel->info.uses_persp_center = true;
1627
1628 if (sel->info.uses_linear_opcode_interp_offset ||
1629 sel->info.uses_linear_opcode_interp_sample)
1630 sel->info.uses_linear_center = true;
1631
1632 switch (sel->type) {
1633 case PIPE_SHADER_GEOMETRY:
1634 sel->gs_output_prim =
1635 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
1636 sel->gs_max_out_vertices =
1637 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
1638 sel->gs_num_invocations =
1639 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
1640 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
1641 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
1642 sel->gs_max_out_vertices;
1643
1644 sel->max_gs_stream = 0;
1645 for (i = 0; i < sel->so.num_outputs; i++)
1646 sel->max_gs_stream = MAX2(sel->max_gs_stream,
1647 sel->so.output[i].stream);
1648
1649 sel->gs_input_verts_per_prim =
1650 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
1651 break;
1652
1653 case PIPE_SHADER_TESS_CTRL:
1654 /* Always reserve space for these. */
1655 sel->patch_outputs_written |=
1656 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0)) |
1657 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0));
1658 /* fall through */
1659 case PIPE_SHADER_VERTEX:
1660 case PIPE_SHADER_TESS_EVAL:
1661 for (i = 0; i < sel->info.num_outputs; i++) {
1662 unsigned name = sel->info.output_semantic_name[i];
1663 unsigned index = sel->info.output_semantic_index[i];
1664
1665 switch (name) {
1666 case TGSI_SEMANTIC_TESSINNER:
1667 case TGSI_SEMANTIC_TESSOUTER:
1668 case TGSI_SEMANTIC_PATCH:
1669 sel->patch_outputs_written |=
1670 1llu << si_shader_io_get_unique_index(name, index);
1671 break;
1672
1673 case TGSI_SEMANTIC_GENERIC:
1674 /* don't process indices the function can't handle */
1675 if (index >= 60)
1676 break;
1677 /* fall through */
1678 case TGSI_SEMANTIC_POSITION:
1679 case TGSI_SEMANTIC_PSIZE:
1680 case TGSI_SEMANTIC_CLIPDIST:
1681 sel->outputs_written |=
1682 1llu << si_shader_io_get_unique_index(name, index);
1683 break;
1684 case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */
1685 case TGSI_SEMANTIC_EDGEFLAG:
1686 break;
1687 default:
1688 sel->outputs_written2 |=
1689 1u << si_shader_io_get_unique_index2(name, index);
1690 }
1691 }
1692 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
1693 break;
1694
1695 case PIPE_SHADER_FRAGMENT:
1696 for (i = 0; i < sel->info.num_inputs; i++) {
1697 unsigned name = sel->info.input_semantic_name[i];
1698 unsigned index = sel->info.input_semantic_index[i];
1699
1700 switch (name) {
1701 case TGSI_SEMANTIC_CLIPDIST:
1702 case TGSI_SEMANTIC_GENERIC:
1703 sel->inputs_read |=
1704 1llu << si_shader_io_get_unique_index(name, index);
1705 break;
1706 case TGSI_SEMANTIC_PCOORD: /* ignore this */
1707 break;
1708 default:
1709 sel->inputs_read2 |=
1710 1u << si_shader_io_get_unique_index2(name, index);
1711 }
1712 }
1713
1714 for (i = 0; i < 8; i++)
1715 if (sel->info.colors_written & (1 << i))
1716 sel->colors_written_4bit |= 0xf << (4 * i);
1717
1718 for (i = 0; i < sel->info.num_inputs; i++) {
1719 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
1720 int index = sel->info.input_semantic_index[i];
1721 sel->color_attr_index[index] = i;
1722 }
1723 }
1724 break;
1725 }
1726
1727 /* DB_SHADER_CONTROL */
1728 sel->db_shader_control =
1729 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
1730 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
1731 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
1732 S_02880C_KILL_ENABLE(sel->info.uses_kill);
1733
1734 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
1735 case TGSI_FS_DEPTH_LAYOUT_GREATER:
1736 sel->db_shader_control |=
1737 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
1738 break;
1739 case TGSI_FS_DEPTH_LAYOUT_LESS:
1740 sel->db_shader_control |=
1741 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
1742 break;
1743 }
1744
1745 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
1746 *
1747 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
1748 * --|-----------|------------|------------|--------------------|-------------------|-------------
1749 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
1750 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
1751 * 2 | false | true | n/a | LateZ | 1 | 0
1752 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
1753 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
1754 *
1755 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
1756 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
1757 *
1758 * Don't use ReZ without profiling !!!
1759 *
1760 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
1761 * shaders.
1762 */
1763 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
1764 /* Cases 3, 4. */
1765 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
1766 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
1767 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
1768 } else if (sel->info.writes_memory) {
1769 /* Case 2. */
1770 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
1771 S_02880C_EXEC_ON_HIER_FAIL(1);
1772 } else {
1773 /* Case 1. */
1774 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
1775 }
1776
1777 (void) mtx_init(&sel->mutex, mtx_plain);
1778 util_queue_fence_init(&sel->ready);
1779
1780 if ((sctx->b.debug.debug_message && !sctx->b.debug.async) ||
1781 sctx->is_debug ||
1782 r600_can_dump_shader(&sscreen->b, sel->info.processor))
1783 si_init_shader_selector_async(sel, -1);
1784 else
1785 util_queue_add_job(&sscreen->shader_compiler_queue, sel,
1786 &sel->ready, si_init_shader_selector_async,
1787 NULL);
1788
1789 return sel;
1790 }
1791
1792 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
1793 {
1794 struct si_context *sctx = (struct si_context *)ctx;
1795 struct si_shader_selector *sel = state;
1796
1797 if (sctx->vs_shader.cso == sel)
1798 return;
1799
1800 sctx->vs_shader.cso = sel;
1801 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
1802 sctx->do_update_shaders = true;
1803 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1804 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1805 }
1806
1807 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
1808 {
1809 struct si_context *sctx = (struct si_context *)ctx;
1810 struct si_shader_selector *sel = state;
1811 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
1812
1813 if (sctx->gs_shader.cso == sel)
1814 return;
1815
1816 sctx->gs_shader.cso = sel;
1817 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
1818 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
1819 sctx->do_update_shaders = true;
1820 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1821 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1822
1823 if (enable_changed)
1824 si_shader_change_notify(sctx);
1825 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1826 }
1827
1828 static void si_update_tcs_tes_uses_prim_id(struct si_context *sctx)
1829 {
1830 sctx->ia_multi_vgt_param_key.u.tcs_tes_uses_prim_id =
1831 (sctx->tes_shader.cso &&
1832 sctx->tes_shader.cso->info.uses_primid) ||
1833 (sctx->tcs_shader.cso &&
1834 sctx->tcs_shader.cso->info.uses_primid);
1835 }
1836
1837 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
1838 {
1839 struct si_context *sctx = (struct si_context *)ctx;
1840 struct si_shader_selector *sel = state;
1841 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
1842
1843 if (sctx->tcs_shader.cso == sel)
1844 return;
1845
1846 sctx->tcs_shader.cso = sel;
1847 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
1848 si_update_tcs_tes_uses_prim_id(sctx);
1849 sctx->do_update_shaders = true;
1850
1851 if (enable_changed)
1852 sctx->last_tcs = NULL; /* invalidate derived tess state */
1853 }
1854
1855 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
1856 {
1857 struct si_context *sctx = (struct si_context *)ctx;
1858 struct si_shader_selector *sel = state;
1859 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
1860
1861 if (sctx->tes_shader.cso == sel)
1862 return;
1863
1864 sctx->tes_shader.cso = sel;
1865 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
1866 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
1867 si_update_tcs_tes_uses_prim_id(sctx);
1868 sctx->do_update_shaders = true;
1869 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1870 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1871
1872 if (enable_changed) {
1873 si_shader_change_notify(sctx);
1874 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
1875 }
1876 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1877 }
1878
1879 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
1880 {
1881 struct si_context *sctx = (struct si_context *)ctx;
1882 struct si_shader_selector *sel = state;
1883
1884 /* skip if supplied shader is one already in use */
1885 if (sctx->ps_shader.cso == sel)
1886 return;
1887
1888 sctx->ps_shader.cso = sel;
1889 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
1890 sctx->do_update_shaders = true;
1891 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
1892 }
1893
1894 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
1895 {
1896 if (shader->is_optimized) {
1897 util_queue_fence_wait(&shader->optimized_ready);
1898 util_queue_fence_destroy(&shader->optimized_ready);
1899 }
1900
1901 if (shader->pm4) {
1902 switch (shader->selector->type) {
1903 case PIPE_SHADER_VERTEX:
1904 if (shader->key.as_ls) {
1905 assert(sctx->b.chip_class <= VI);
1906 si_pm4_delete_state(sctx, ls, shader->pm4);
1907 } else if (shader->key.as_es) {
1908 assert(sctx->b.chip_class <= VI);
1909 si_pm4_delete_state(sctx, es, shader->pm4);
1910 } else {
1911 si_pm4_delete_state(sctx, vs, shader->pm4);
1912 }
1913 break;
1914 case PIPE_SHADER_TESS_CTRL:
1915 si_pm4_delete_state(sctx, hs, shader->pm4);
1916 break;
1917 case PIPE_SHADER_TESS_EVAL:
1918 if (shader->key.as_es) {
1919 assert(sctx->b.chip_class <= VI);
1920 si_pm4_delete_state(sctx, es, shader->pm4);
1921 } else {
1922 si_pm4_delete_state(sctx, vs, shader->pm4);
1923 }
1924 break;
1925 case PIPE_SHADER_GEOMETRY:
1926 if (shader->is_gs_copy_shader)
1927 si_pm4_delete_state(sctx, vs, shader->pm4);
1928 else
1929 si_pm4_delete_state(sctx, gs, shader->pm4);
1930 break;
1931 case PIPE_SHADER_FRAGMENT:
1932 si_pm4_delete_state(sctx, ps, shader->pm4);
1933 break;
1934 }
1935 }
1936
1937 si_shader_destroy(shader);
1938 free(shader);
1939 }
1940
1941 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
1942 {
1943 struct si_context *sctx = (struct si_context *)ctx;
1944 struct si_shader_selector *sel = (struct si_shader_selector *)state;
1945 struct si_shader *p = sel->first_variant, *c;
1946 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
1947 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
1948 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
1949 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
1950 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
1951 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
1952 };
1953
1954 util_queue_fence_wait(&sel->ready);
1955
1956 if (current_shader[sel->type]->cso == sel) {
1957 current_shader[sel->type]->cso = NULL;
1958 current_shader[sel->type]->current = NULL;
1959 }
1960
1961 while (p) {
1962 c = p->next_variant;
1963 si_delete_shader(sctx, p);
1964 p = c;
1965 }
1966
1967 if (sel->main_shader_part)
1968 si_delete_shader(sctx, sel->main_shader_part);
1969 if (sel->main_shader_part_ls)
1970 si_delete_shader(sctx, sel->main_shader_part_ls);
1971 if (sel->main_shader_part_es)
1972 si_delete_shader(sctx, sel->main_shader_part_es);
1973 if (sel->gs_copy_shader)
1974 si_delete_shader(sctx, sel->gs_copy_shader);
1975
1976 util_queue_fence_destroy(&sel->ready);
1977 mtx_destroy(&sel->mutex);
1978 free(sel->tokens);
1979 free(sel);
1980 }
1981
1982 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
1983 struct si_shader *vs, unsigned name,
1984 unsigned index, unsigned interpolate)
1985 {
1986 struct tgsi_shader_info *vsinfo = &vs->selector->info;
1987 unsigned j, offset, ps_input_cntl = 0;
1988
1989 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
1990 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
1991 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1992
1993 if (name == TGSI_SEMANTIC_PCOORD ||
1994 (name == TGSI_SEMANTIC_TEXCOORD &&
1995 sctx->sprite_coord_enable & (1 << index))) {
1996 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
1997 }
1998
1999 for (j = 0; j < vsinfo->num_outputs; j++) {
2000 if (name == vsinfo->output_semantic_name[j] &&
2001 index == vsinfo->output_semantic_index[j]) {
2002 offset = vs->info.vs_output_param_offset[j];
2003
2004 if (offset <= EXP_PARAM_OFFSET_31) {
2005 /* The input is loaded from parameter memory. */
2006 ps_input_cntl |= S_028644_OFFSET(offset);
2007 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2008 if (offset == EXP_PARAM_UNDEFINED) {
2009 /* This can happen with depth-only rendering. */
2010 offset = 0;
2011 } else {
2012 /* The input is a DEFAULT_VAL constant. */
2013 assert(offset >= EXP_PARAM_DEFAULT_VAL_0000 &&
2014 offset <= EXP_PARAM_DEFAULT_VAL_1111);
2015 offset -= EXP_PARAM_DEFAULT_VAL_0000;
2016 }
2017
2018 ps_input_cntl = S_028644_OFFSET(0x20) |
2019 S_028644_DEFAULT_VAL(offset);
2020 }
2021 break;
2022 }
2023 }
2024
2025 if (name == TGSI_SEMANTIC_PRIMID)
2026 /* PrimID is written after the last output. */
2027 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
2028 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2029 /* No corresponding output found, load defaults into input.
2030 * Don't set any other bits.
2031 * (FLAT_SHADE=1 completely changes behavior) */
2032 ps_input_cntl = S_028644_OFFSET(0x20);
2033 /* D3D 9 behaviour. GL is undefined */
2034 if (name == TGSI_SEMANTIC_COLOR && index == 0)
2035 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
2036 }
2037 return ps_input_cntl;
2038 }
2039
2040 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
2041 {
2042 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2043 struct si_shader *ps = sctx->ps_shader.current;
2044 struct si_shader *vs = si_get_vs_state(sctx);
2045 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
2046 unsigned i, num_interp, num_written = 0, bcol_interp[2];
2047
2048 if (!ps || !ps->selector->info.num_inputs)
2049 return;
2050
2051 num_interp = si_get_ps_num_interp(ps);
2052 assert(num_interp > 0);
2053 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
2054
2055 for (i = 0; i < psinfo->num_inputs; i++) {
2056 unsigned name = psinfo->input_semantic_name[i];
2057 unsigned index = psinfo->input_semantic_index[i];
2058 unsigned interpolate = psinfo->input_interpolate[i];
2059
2060 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
2061 interpolate));
2062 num_written++;
2063
2064 if (name == TGSI_SEMANTIC_COLOR) {
2065 assert(index < ARRAY_SIZE(bcol_interp));
2066 bcol_interp[index] = interpolate;
2067 }
2068 }
2069
2070 if (ps->key.part.ps.prolog.color_two_side) {
2071 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
2072
2073 for (i = 0; i < 2; i++) {
2074 if (!(psinfo->colors_read & (0xf << (i * 4))))
2075 continue;
2076
2077 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
2078 i, bcol_interp[i]));
2079 num_written++;
2080 }
2081 }
2082 assert(num_interp == num_written);
2083 }
2084
2085 /**
2086 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2087 */
2088 static void si_init_config_add_vgt_flush(struct si_context *sctx)
2089 {
2090 if (sctx->init_config_has_vgt_flush)
2091 return;
2092
2093 /* Done by Vulkan before VGT_FLUSH. */
2094 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2095 si_pm4_cmd_add(sctx->init_config,
2096 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2097 si_pm4_cmd_end(sctx->init_config, false);
2098
2099 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2100 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2101 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2102 si_pm4_cmd_end(sctx->init_config, false);
2103 sctx->init_config_has_vgt_flush = true;
2104 }
2105
2106 /* Initialize state related to ESGS / GSVS ring buffers */
2107 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2108 {
2109 struct si_shader_selector *es =
2110 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2111 struct si_shader_selector *gs = sctx->gs_shader.cso;
2112 struct si_pm4_state *pm4;
2113
2114 /* Chip constants. */
2115 unsigned num_se = sctx->screen->b.info.max_se;
2116 unsigned wave_size = 64;
2117 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2118 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2119 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2120 */
2121 unsigned gs_vertex_reuse = (sctx->b.chip_class >= VI ? 32 : 16) * num_se;
2122 unsigned alignment = 256 * num_se;
2123 /* The maximum size is 63.999 MB per SE. */
2124 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2125
2126 /* Calculate the minimum size. */
2127 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
2128 wave_size, alignment);
2129
2130 /* These are recommended sizes, not minimum sizes. */
2131 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2132 es->esgs_itemsize * gs->gs_input_verts_per_prim;
2133 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2134 gs->max_gsvs_emit_size;
2135
2136 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2137 esgs_ring_size = align(esgs_ring_size, alignment);
2138 gsvs_ring_size = align(gsvs_ring_size, alignment);
2139
2140 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2141 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2142
2143 /* Some rings don't have to be allocated if shaders don't use them.
2144 * (e.g. no varyings between ES and GS or GS and VS)
2145 *
2146 * GFX9 doesn't have the ESGS ring.
2147 */
2148 bool update_esgs = sctx->b.chip_class <= VI &&
2149 esgs_ring_size &&
2150 (!sctx->esgs_ring ||
2151 sctx->esgs_ring->width0 < esgs_ring_size);
2152 bool update_gsvs = gsvs_ring_size &&
2153 (!sctx->gsvs_ring ||
2154 sctx->gsvs_ring->width0 < gsvs_ring_size);
2155
2156 if (!update_esgs && !update_gsvs)
2157 return true;
2158
2159 if (update_esgs) {
2160 pipe_resource_reference(&sctx->esgs_ring, NULL);
2161 sctx->esgs_ring =
2162 r600_aligned_buffer_create(sctx->b.b.screen,
2163 R600_RESOURCE_FLAG_UNMAPPABLE,
2164 PIPE_USAGE_DEFAULT,
2165 esgs_ring_size, alignment);
2166 if (!sctx->esgs_ring)
2167 return false;
2168 }
2169
2170 if (update_gsvs) {
2171 pipe_resource_reference(&sctx->gsvs_ring, NULL);
2172 sctx->gsvs_ring =
2173 r600_aligned_buffer_create(sctx->b.b.screen,
2174 R600_RESOURCE_FLAG_UNMAPPABLE,
2175 PIPE_USAGE_DEFAULT,
2176 gsvs_ring_size, alignment);
2177 if (!sctx->gsvs_ring)
2178 return false;
2179 }
2180
2181 /* Create the "init_config_gs_rings" state. */
2182 pm4 = CALLOC_STRUCT(si_pm4_state);
2183 if (!pm4)
2184 return false;
2185
2186 if (sctx->b.chip_class >= CIK) {
2187 if (sctx->esgs_ring) {
2188 assert(sctx->b.chip_class <= VI);
2189 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2190 sctx->esgs_ring->width0 / 256);
2191 }
2192 if (sctx->gsvs_ring)
2193 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2194 sctx->gsvs_ring->width0 / 256);
2195 } else {
2196 if (sctx->esgs_ring)
2197 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2198 sctx->esgs_ring->width0 / 256);
2199 if (sctx->gsvs_ring)
2200 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2201 sctx->gsvs_ring->width0 / 256);
2202 }
2203
2204 /* Set the state. */
2205 if (sctx->init_config_gs_rings)
2206 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
2207 sctx->init_config_gs_rings = pm4;
2208
2209 if (!sctx->init_config_has_vgt_flush) {
2210 si_init_config_add_vgt_flush(sctx);
2211 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2212 }
2213
2214 /* Flush the context to re-emit both init_config states. */
2215 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2216 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2217
2218 /* Set ring bindings. */
2219 if (sctx->esgs_ring) {
2220 assert(sctx->b.chip_class <= VI);
2221 si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
2222 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2223 true, true, 4, 64, 0);
2224 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
2225 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2226 false, false, 0, 0, 0);
2227 }
2228 if (sctx->gsvs_ring) {
2229 si_set_ring_buffer(&sctx->b.b, SI_RING_GSVS,
2230 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
2231 false, false, 0, 0, 0);
2232 }
2233
2234 return true;
2235 }
2236
2237 /**
2238 * @returns 1 if \p sel has been updated to use a new scratch buffer
2239 * 0 if not
2240 * < 0 if there was a failure
2241 */
2242 static int si_update_scratch_buffer(struct si_context *sctx,
2243 struct si_shader *shader)
2244 {
2245 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
2246 int r;
2247
2248 if (!shader)
2249 return 0;
2250
2251 /* This shader doesn't need a scratch buffer */
2252 if (shader->config.scratch_bytes_per_wave == 0)
2253 return 0;
2254
2255 /* This shader is already configured to use the current
2256 * scratch buffer. */
2257 if (shader->scratch_bo == sctx->scratch_buffer)
2258 return 0;
2259
2260 assert(sctx->scratch_buffer);
2261
2262 si_shader_apply_scratch_relocs(sctx, shader, &shader->config, scratch_va);
2263
2264 /* Replace the shader bo with a new bo that has the relocs applied. */
2265 r = si_shader_binary_upload(sctx->screen, shader);
2266 if (r)
2267 return r;
2268
2269 /* Update the shader state to use the new shader bo. */
2270 si_shader_init_pm4_state(sctx->screen, shader);
2271
2272 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
2273
2274 return 1;
2275 }
2276
2277 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
2278 {
2279 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
2280 }
2281
2282 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
2283 {
2284 return shader ? shader->config.scratch_bytes_per_wave : 0;
2285 }
2286
2287 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
2288 {
2289 unsigned bytes = 0;
2290
2291 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
2292 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
2293 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
2294 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tcs_shader.current));
2295 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
2296 return bytes;
2297 }
2298
2299 static bool si_update_spi_tmpring_size(struct si_context *sctx)
2300 {
2301 unsigned current_scratch_buffer_size =
2302 si_get_current_scratch_buffer_size(sctx);
2303 unsigned scratch_bytes_per_wave =
2304 si_get_max_scratch_bytes_per_wave(sctx);
2305 unsigned scratch_needed_size = scratch_bytes_per_wave *
2306 sctx->scratch_waves;
2307 unsigned spi_tmpring_size;
2308 int r;
2309
2310 if (scratch_needed_size > 0) {
2311 if (scratch_needed_size > current_scratch_buffer_size) {
2312 /* Create a bigger scratch buffer */
2313 r600_resource_reference(&sctx->scratch_buffer, NULL);
2314
2315 sctx->scratch_buffer = (struct r600_resource*)
2316 r600_aligned_buffer_create(&sctx->screen->b.b,
2317 R600_RESOURCE_FLAG_UNMAPPABLE,
2318 PIPE_USAGE_DEFAULT,
2319 scratch_needed_size, 256);
2320 if (!sctx->scratch_buffer)
2321 return false;
2322
2323 si_mark_atom_dirty(sctx, &sctx->scratch_state);
2324 r600_context_add_resource_size(&sctx->b.b,
2325 &sctx->scratch_buffer->b.b);
2326 }
2327
2328 /* Update the shaders, so they are using the latest scratch. The
2329 * scratch buffer may have been changed since these shaders were
2330 * last used, so we still need to try to update them, even if
2331 * they require scratch buffers smaller than the current size.
2332 */
2333 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
2334 if (r < 0)
2335 return false;
2336 if (r == 1)
2337 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2338
2339 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
2340 if (r < 0)
2341 return false;
2342 if (r == 1)
2343 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2344
2345 r = si_update_scratch_buffer(sctx, sctx->tcs_shader.current);
2346 if (r < 0)
2347 return false;
2348 if (r == 1)
2349 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
2350
2351 /* VS can be bound as LS, ES, or VS. */
2352 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
2353 if (r < 0)
2354 return false;
2355 if (r == 1) {
2356 if (sctx->tes_shader.current)
2357 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2358 else if (sctx->gs_shader.current)
2359 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2360 else
2361 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2362 }
2363
2364 /* TES can be bound as ES or VS. */
2365 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
2366 if (r < 0)
2367 return false;
2368 if (r == 1) {
2369 if (sctx->gs_shader.current)
2370 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2371 else
2372 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2373 }
2374 }
2375
2376 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
2377 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
2378 "scratch size should already be aligned correctly.");
2379
2380 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
2381 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
2382 if (spi_tmpring_size != sctx->spi_tmpring_size) {
2383 sctx->spi_tmpring_size = spi_tmpring_size;
2384 si_mark_atom_dirty(sctx, &sctx->scratch_state);
2385 }
2386 return true;
2387 }
2388
2389 static void si_init_tess_factor_ring(struct si_context *sctx)
2390 {
2391 bool double_offchip_buffers = sctx->b.chip_class >= CIK &&
2392 sctx->b.family != CHIP_CARRIZO &&
2393 sctx->b.family != CHIP_STONEY;
2394 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2395 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
2396 sctx->screen->b.info.max_se;
2397 unsigned offchip_granularity;
2398
2399 switch (sctx->screen->tess_offchip_block_dw_size) {
2400 default:
2401 assert(0);
2402 /* fall through */
2403 case 8192:
2404 offchip_granularity = V_03093C_X_8K_DWORDS;
2405 break;
2406 case 4096:
2407 offchip_granularity = V_03093C_X_4K_DWORDS;
2408 break;
2409 }
2410
2411 switch (sctx->b.chip_class) {
2412 case SI:
2413 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2414 break;
2415 case CIK:
2416 case VI:
2417 case GFX9:
2418 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2419 break;
2420 default:
2421 assert(0);
2422 return;
2423 }
2424
2425 assert(!sctx->tf_ring);
2426 sctx->tf_ring = r600_aligned_buffer_create(sctx->b.b.screen,
2427 R600_RESOURCE_FLAG_UNMAPPABLE,
2428 PIPE_USAGE_DEFAULT,
2429 32768 * sctx->screen->b.info.max_se,
2430 256);
2431 if (!sctx->tf_ring)
2432 return;
2433
2434 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
2435
2436 sctx->tess_offchip_ring =
2437 r600_aligned_buffer_create(sctx->b.b.screen,
2438 R600_RESOURCE_FLAG_UNMAPPABLE,
2439 PIPE_USAGE_DEFAULT,
2440 max_offchip_buffers *
2441 sctx->screen->tess_offchip_block_dw_size * 4,
2442 256);
2443 if (!sctx->tess_offchip_ring)
2444 return;
2445
2446 si_init_config_add_vgt_flush(sctx);
2447
2448 /* Append these registers to the init config state. */
2449 if (sctx->b.chip_class >= CIK) {
2450 if (sctx->b.chip_class >= VI)
2451 --max_offchip_buffers;
2452
2453 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
2454 S_030938_SIZE(sctx->tf_ring->width0 / 4));
2455 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
2456 r600_resource(sctx->tf_ring)->gpu_address >> 8);
2457 if (sctx->b.chip_class >= GFX9)
2458 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
2459 r600_resource(sctx->tf_ring)->gpu_address >> 40);
2460 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
2461 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2462 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity));
2463 } else {
2464 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
2465 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
2466 S_008988_SIZE(sctx->tf_ring->width0 / 4));
2467 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
2468 r600_resource(sctx->tf_ring)->gpu_address >> 8);
2469 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2470 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers));
2471 }
2472
2473 /* Flush the context to re-emit the init_config state.
2474 * This is done only once in a lifetime of a context.
2475 */
2476 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2477 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2478 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2479
2480 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_FACTOR, sctx->tf_ring,
2481 0, sctx->tf_ring->width0, false, false, 0, 0, 0);
2482
2483 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_OFFCHIP,
2484 sctx->tess_offchip_ring, 0,
2485 sctx->tess_offchip_ring->width0, false, false, 0, 0, 0);
2486 }
2487
2488 /**
2489 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
2490 * VS passes its outputs to TES directly, so the fixed-function shader only
2491 * has to write TESSOUTER and TESSINNER.
2492 */
2493 static void si_generate_fixed_func_tcs(struct si_context *sctx)
2494 {
2495 struct ureg_src outer, inner;
2496 struct ureg_dst tessouter, tessinner;
2497 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
2498
2499 if (!ureg)
2500 return; /* if we get here, we're screwed */
2501
2502 assert(!sctx->fixed_func_tcs_shader.cso);
2503
2504 outer = ureg_DECL_system_value(ureg,
2505 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
2506 inner = ureg_DECL_system_value(ureg,
2507 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
2508
2509 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
2510 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
2511
2512 ureg_MOV(ureg, tessouter, outer);
2513 ureg_MOV(ureg, tessinner, inner);
2514 ureg_END(ureg);
2515
2516 sctx->fixed_func_tcs_shader.cso =
2517 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
2518 }
2519
2520 static void si_update_vgt_shader_config(struct si_context *sctx)
2521 {
2522 /* Calculate the index of the config.
2523 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
2524 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
2525 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
2526
2527 if (!*pm4) {
2528 uint32_t stages = 0;
2529
2530 *pm4 = CALLOC_STRUCT(si_pm4_state);
2531
2532 if (sctx->tes_shader.cso) {
2533 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2534 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2535
2536 if (sctx->gs_shader.cso)
2537 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2538 S_028B54_GS_EN(1) |
2539 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2540 else
2541 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2542 } else if (sctx->gs_shader.cso) {
2543 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2544 S_028B54_GS_EN(1) |
2545 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2546 }
2547
2548 if (sctx->b.chip_class >= GFX9)
2549 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2550
2551 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
2552 }
2553 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
2554 }
2555
2556 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
2557 {
2558 struct pipe_stream_output_info *so = &shader->so;
2559 uint32_t enabled_stream_buffers_mask = 0;
2560 int i;
2561
2562 for (i = 0; i < so->num_outputs; i++)
2563 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
2564 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
2565 sctx->b.streamout.stride_in_dw = shader->so.stride;
2566 }
2567
2568 bool si_update_shaders(struct si_context *sctx)
2569 {
2570 struct pipe_context *ctx = (struct pipe_context*)sctx;
2571 struct si_compiler_ctx_state compiler_state;
2572 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2573 struct si_shader *old_vs = si_get_vs_state(sctx);
2574 bool old_clip_disable = old_vs ? old_vs->key.opt.hw_vs.clip_disable : false;
2575 int r;
2576
2577 compiler_state.tm = sctx->tm;
2578 compiler_state.debug = sctx->b.debug;
2579 compiler_state.is_debug_context = sctx->is_debug;
2580
2581 /* Update stages before GS. */
2582 if (sctx->tes_shader.cso) {
2583 if (!sctx->tf_ring) {
2584 si_init_tess_factor_ring(sctx);
2585 if (!sctx->tf_ring)
2586 return false;
2587 }
2588
2589 /* VS as LS */
2590 if (sctx->b.chip_class <= VI) {
2591 r = si_shader_select(ctx, &sctx->vs_shader,
2592 &compiler_state);
2593 if (r)
2594 return false;
2595 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2596 }
2597
2598 if (sctx->tcs_shader.cso) {
2599 r = si_shader_select(ctx, &sctx->tcs_shader,
2600 &compiler_state);
2601 if (r)
2602 return false;
2603 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
2604 } else {
2605 if (!sctx->fixed_func_tcs_shader.cso) {
2606 si_generate_fixed_func_tcs(sctx);
2607 if (!sctx->fixed_func_tcs_shader.cso)
2608 return false;
2609 }
2610
2611 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
2612 &compiler_state);
2613 if (r)
2614 return false;
2615 si_pm4_bind_state(sctx, hs,
2616 sctx->fixed_func_tcs_shader.current->pm4);
2617 }
2618
2619 if (sctx->gs_shader.cso) {
2620 /* TES as ES */
2621 if (sctx->b.chip_class <= VI) {
2622 r = si_shader_select(ctx, &sctx->tes_shader,
2623 &compiler_state);
2624 if (r)
2625 return false;
2626 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2627 }
2628 } else {
2629 /* TES as VS */
2630 r = si_shader_select(ctx, &sctx->tes_shader,
2631 &compiler_state);
2632 if (r)
2633 return false;
2634 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2635 si_update_so(sctx, sctx->tes_shader.cso);
2636 }
2637 } else if (sctx->gs_shader.cso) {
2638 if (sctx->b.chip_class <= VI) {
2639 /* VS as ES */
2640 r = si_shader_select(ctx, &sctx->vs_shader,
2641 &compiler_state);
2642 if (r)
2643 return false;
2644 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2645
2646 si_pm4_bind_state(sctx, ls, NULL);
2647 si_pm4_bind_state(sctx, hs, NULL);
2648 }
2649 } else {
2650 /* VS as VS */
2651 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
2652 if (r)
2653 return false;
2654 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2655 si_update_so(sctx, sctx->vs_shader.cso);
2656
2657 si_pm4_bind_state(sctx, ls, NULL);
2658 si_pm4_bind_state(sctx, hs, NULL);
2659 }
2660
2661 /* Update GS. */
2662 if (sctx->gs_shader.cso) {
2663 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
2664 if (r)
2665 return false;
2666 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2667 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
2668 si_update_so(sctx, sctx->gs_shader.cso);
2669
2670 if (!si_update_gs_ring_buffers(sctx))
2671 return false;
2672 } else {
2673 si_pm4_bind_state(sctx, gs, NULL);
2674 if (sctx->b.chip_class <= VI)
2675 si_pm4_bind_state(sctx, es, NULL);
2676 }
2677
2678 si_update_vgt_shader_config(sctx);
2679
2680 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.hw_vs.clip_disable)
2681 si_mark_atom_dirty(sctx, &sctx->clip_regs);
2682
2683 if (sctx->ps_shader.cso) {
2684 unsigned db_shader_control;
2685
2686 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
2687 if (r)
2688 return false;
2689 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2690
2691 db_shader_control =
2692 sctx->ps_shader.cso->db_shader_control |
2693 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
2694
2695 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
2696 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
2697 sctx->flatshade != rs->flatshade) {
2698 sctx->sprite_coord_enable = rs->sprite_coord_enable;
2699 sctx->flatshade = rs->flatshade;
2700 si_mark_atom_dirty(sctx, &sctx->spi_map);
2701 }
2702
2703 if (sctx->screen->b.rbplus_allowed && si_pm4_state_changed(sctx, ps))
2704 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2705
2706 if (sctx->ps_db_shader_control != db_shader_control) {
2707 sctx->ps_db_shader_control = db_shader_control;
2708 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2709 }
2710
2711 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
2712 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
2713 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2714
2715 if (sctx->b.chip_class == SI)
2716 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2717
2718 if (sctx->framebuffer.nr_samples <= 1)
2719 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2720 }
2721 }
2722
2723 if (si_pm4_state_changed(sctx, ls) ||
2724 si_pm4_state_changed(sctx, hs) ||
2725 si_pm4_state_changed(sctx, es) ||
2726 si_pm4_state_changed(sctx, gs) ||
2727 si_pm4_state_changed(sctx, vs) ||
2728 si_pm4_state_changed(sctx, ps)) {
2729 if (!si_update_spi_tmpring_size(sctx))
2730 return false;
2731 }
2732
2733 if (sctx->b.chip_class >= CIK)
2734 si_mark_atom_dirty(sctx, &sctx->prefetch_L2);
2735
2736 sctx->do_update_shaders = false;
2737 return true;
2738 }
2739
2740 static void si_emit_scratch_state(struct si_context *sctx,
2741 struct r600_atom *atom)
2742 {
2743 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2744
2745 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
2746 sctx->spi_tmpring_size);
2747
2748 if (sctx->scratch_buffer) {
2749 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2750 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
2751 RADEON_PRIO_SCRATCH_BUFFER);
2752 }
2753 }
2754
2755 void si_init_shader_functions(struct si_context *sctx)
2756 {
2757 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
2758 si_init_atom(sctx, &sctx->scratch_state, &sctx->atoms.s.scratch_state,
2759 si_emit_scratch_state);
2760
2761 sctx->b.b.create_vs_state = si_create_shader_selector;
2762 sctx->b.b.create_tcs_state = si_create_shader_selector;
2763 sctx->b.b.create_tes_state = si_create_shader_selector;
2764 sctx->b.b.create_gs_state = si_create_shader_selector;
2765 sctx->b.b.create_fs_state = si_create_shader_selector;
2766
2767 sctx->b.b.bind_vs_state = si_bind_vs_shader;
2768 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
2769 sctx->b.b.bind_tes_state = si_bind_tes_shader;
2770 sctx->b.b.bind_gs_state = si_bind_gs_shader;
2771 sctx->b.b.bind_fs_state = si_bind_ps_shader;
2772
2773 sctx->b.b.delete_vs_state = si_delete_shader_selector;
2774 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
2775 sctx->b.b.delete_tes_state = si_delete_shader_selector;
2776 sctx->b.b.delete_gs_state = si_delete_shader_selector;
2777 sctx->b.b.delete_fs_state = si_delete_shader_selector;
2778 }