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broadcom/vc5: Use u_transfer_helper for MSAA mappings.
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "sid.h"
26 #include "gfx9d.h"
27 #include "radeon/r600_cs.h"
28
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_ureg.h"
31 #include "util/hash_table.h"
32 #include "util/crc32.h"
33 #include "util/u_async_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
36
37 #include "util/disk_cache.h"
38 #include "util/mesa-sha1.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41
42 /* SHADER_CACHE */
43
44 /**
45 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
46 * integer.
47 */
48 static void *si_get_tgsi_binary(struct si_shader_selector *sel)
49 {
50 unsigned tgsi_size = tgsi_num_tokens(sel->tokens) *
51 sizeof(struct tgsi_token);
52 unsigned size = 4 + tgsi_size + sizeof(sel->so);
53 char *result = (char*)MALLOC(size);
54
55 if (!result)
56 return NULL;
57
58 *((uint32_t*)result) = size;
59 memcpy(result + 4, sel->tokens, tgsi_size);
60 memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so));
61 return result;
62 }
63
64 /** Copy "data" to "ptr" and return the next dword following copied data. */
65 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
66 {
67 /* data may be NULL if size == 0 */
68 if (size)
69 memcpy(ptr, data, size);
70 ptr += DIV_ROUND_UP(size, 4);
71 return ptr;
72 }
73
74 /** Read data from "ptr". Return the next dword following the data. */
75 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
76 {
77 memcpy(data, ptr, size);
78 ptr += DIV_ROUND_UP(size, 4);
79 return ptr;
80 }
81
82 /**
83 * Write the size as uint followed by the data. Return the next dword
84 * following the copied data.
85 */
86 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
87 {
88 *ptr++ = size;
89 return write_data(ptr, data, size);
90 }
91
92 /**
93 * Read the size as uint followed by the data. Return both via parameters.
94 * Return the next dword following the data.
95 */
96 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
97 {
98 *size = *ptr++;
99 assert(*data == NULL);
100 if (!*size)
101 return ptr;
102 *data = malloc(*size);
103 return read_data(ptr, *data, *size);
104 }
105
106 /**
107 * Return the shader binary in a buffer. The first 4 bytes contain its size
108 * as integer.
109 */
110 static void *si_get_shader_binary(struct si_shader *shader)
111 {
112 /* There is always a size of data followed by the data itself. */
113 unsigned relocs_size = shader->binary.reloc_count *
114 sizeof(shader->binary.relocs[0]);
115 unsigned disasm_size = shader->binary.disasm_string ?
116 strlen(shader->binary.disasm_string) + 1 : 0;
117 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
118 strlen(shader->binary.llvm_ir_string) + 1 : 0;
119 unsigned size =
120 4 + /* total size */
121 4 + /* CRC32 of the data below */
122 align(sizeof(shader->config), 4) +
123 align(sizeof(shader->info), 4) +
124 4 + align(shader->binary.code_size, 4) +
125 4 + align(shader->binary.rodata_size, 4) +
126 4 + align(relocs_size, 4) +
127 4 + align(disasm_size, 4) +
128 4 + align(llvm_ir_size, 4);
129 void *buffer = CALLOC(1, size);
130 uint32_t *ptr = (uint32_t*)buffer;
131
132 if (!buffer)
133 return NULL;
134
135 *ptr++ = size;
136 ptr++; /* CRC32 is calculated at the end. */
137
138 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
139 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
140 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
141 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
142 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
143 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
144 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
145 assert((char *)ptr - (char *)buffer == size);
146
147 /* Compute CRC32. */
148 ptr = (uint32_t*)buffer;
149 ptr++;
150 *ptr = util_hash_crc32(ptr + 1, size - 8);
151
152 return buffer;
153 }
154
155 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
156 {
157 uint32_t *ptr = (uint32_t*)binary;
158 uint32_t size = *ptr++;
159 uint32_t crc32 = *ptr++;
160 unsigned chunk_size;
161
162 if (util_hash_crc32(ptr, size - 8) != crc32) {
163 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
164 return false;
165 }
166
167 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
168 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
169 ptr = read_chunk(ptr, (void**)&shader->binary.code,
170 &shader->binary.code_size);
171 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
172 &shader->binary.rodata_size);
173 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
174 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
175 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
176 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
177
178 return true;
179 }
180
181 /**
182 * Insert a shader into the cache. It's assumed the shader is not in the cache.
183 * Use si_shader_cache_load_shader before calling this.
184 *
185 * Returns false on failure, in which case the tgsi_binary should be freed.
186 */
187 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
188 void *tgsi_binary,
189 struct si_shader *shader,
190 bool insert_into_disk_cache)
191 {
192 void *hw_binary;
193 struct hash_entry *entry;
194 uint8_t key[CACHE_KEY_SIZE];
195
196 entry = _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
197 if (entry)
198 return false; /* already added */
199
200 hw_binary = si_get_shader_binary(shader);
201 if (!hw_binary)
202 return false;
203
204 if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
205 hw_binary) == NULL) {
206 FREE(hw_binary);
207 return false;
208 }
209
210 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
211 disk_cache_compute_key(sscreen->disk_shader_cache, tgsi_binary,
212 *((uint32_t *)tgsi_binary), key);
213 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
214 *((uint32_t *) hw_binary), NULL);
215 }
216
217 return true;
218 }
219
220 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
221 void *tgsi_binary,
222 struct si_shader *shader)
223 {
224 struct hash_entry *entry =
225 _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
226 if (!entry) {
227 if (sscreen->disk_shader_cache) {
228 unsigned char sha1[CACHE_KEY_SIZE];
229 size_t tg_size = *((uint32_t *) tgsi_binary);
230
231 disk_cache_compute_key(sscreen->disk_shader_cache,
232 tgsi_binary, tg_size, sha1);
233
234 size_t binary_size;
235 uint8_t *buffer =
236 disk_cache_get(sscreen->disk_shader_cache,
237 sha1, &binary_size);
238 if (!buffer)
239 return false;
240
241 if (binary_size < sizeof(uint32_t) ||
242 *((uint32_t*)buffer) != binary_size) {
243 /* Something has gone wrong discard the item
244 * from the cache and rebuild/link from
245 * source.
246 */
247 assert(!"Invalid radeonsi shader disk cache "
248 "item!");
249
250 disk_cache_remove(sscreen->disk_shader_cache,
251 sha1);
252 free(buffer);
253
254 return false;
255 }
256
257 if (!si_load_shader_binary(shader, buffer)) {
258 free(buffer);
259 return false;
260 }
261 free(buffer);
262
263 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary,
264 shader, false))
265 FREE(tgsi_binary);
266 } else {
267 return false;
268 }
269 } else {
270 if (si_load_shader_binary(shader, entry->data))
271 FREE(tgsi_binary);
272 else
273 return false;
274 }
275 p_atomic_inc(&sscreen->num_shader_cache_hits);
276 return true;
277 }
278
279 static uint32_t si_shader_cache_key_hash(const void *key)
280 {
281 /* The first dword is the key size. */
282 return util_hash_crc32(key, *(uint32_t*)key);
283 }
284
285 static bool si_shader_cache_key_equals(const void *a, const void *b)
286 {
287 uint32_t *keya = (uint32_t*)a;
288 uint32_t *keyb = (uint32_t*)b;
289
290 /* The first dword is the key size. */
291 if (*keya != *keyb)
292 return false;
293
294 return memcmp(keya, keyb, *keya) == 0;
295 }
296
297 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
298 {
299 FREE((void*)entry->key);
300 FREE(entry->data);
301 }
302
303 bool si_init_shader_cache(struct si_screen *sscreen)
304 {
305 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
306 sscreen->shader_cache =
307 _mesa_hash_table_create(NULL,
308 si_shader_cache_key_hash,
309 si_shader_cache_key_equals);
310
311 return sscreen->shader_cache != NULL;
312 }
313
314 void si_destroy_shader_cache(struct si_screen *sscreen)
315 {
316 if (sscreen->shader_cache)
317 _mesa_hash_table_destroy(sscreen->shader_cache,
318 si_destroy_shader_cache_entry);
319 mtx_destroy(&sscreen->shader_cache_mutex);
320 }
321
322 /* SHADER STATES */
323
324 static void si_set_tesseval_regs(struct si_screen *sscreen,
325 struct si_shader_selector *tes,
326 struct si_pm4_state *pm4)
327 {
328 struct tgsi_shader_info *info = &tes->info;
329 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
330 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
331 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
332 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
333 unsigned type, partitioning, topology, distribution_mode;
334
335 switch (tes_prim_mode) {
336 case PIPE_PRIM_LINES:
337 type = V_028B6C_TESS_ISOLINE;
338 break;
339 case PIPE_PRIM_TRIANGLES:
340 type = V_028B6C_TESS_TRIANGLE;
341 break;
342 case PIPE_PRIM_QUADS:
343 type = V_028B6C_TESS_QUAD;
344 break;
345 default:
346 assert(0);
347 return;
348 }
349
350 switch (tes_spacing) {
351 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
352 partitioning = V_028B6C_PART_FRAC_ODD;
353 break;
354 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
355 partitioning = V_028B6C_PART_FRAC_EVEN;
356 break;
357 case PIPE_TESS_SPACING_EQUAL:
358 partitioning = V_028B6C_PART_INTEGER;
359 break;
360 default:
361 assert(0);
362 return;
363 }
364
365 if (tes_point_mode)
366 topology = V_028B6C_OUTPUT_POINT;
367 else if (tes_prim_mode == PIPE_PRIM_LINES)
368 topology = V_028B6C_OUTPUT_LINE;
369 else if (tes_vertex_order_cw)
370 /* for some reason, this must be the other way around */
371 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
372 else
373 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
374
375 if (sscreen->has_distributed_tess) {
376 if (sscreen->info.family == CHIP_FIJI ||
377 sscreen->info.family >= CHIP_POLARIS10)
378 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
379 else
380 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
381 } else
382 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
383
384 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
385 S_028B6C_TYPE(type) |
386 S_028B6C_PARTITIONING(partitioning) |
387 S_028B6C_TOPOLOGY(topology) |
388 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
389 }
390
391 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
392 * whether the "fractional odd" tessellation spacing is used.
393 *
394 * Possible VGT configurations and which state should set the register:
395 *
396 * Reg set in | VGT shader configuration | Value
397 * ------------------------------------------------------
398 * VS as VS | VS | 30
399 * VS as ES | ES -> GS -> VS | 30
400 * TES as VS | LS -> HS -> VS | 14 or 30
401 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
402 *
403 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
404 */
405 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
406 struct si_shader_selector *sel,
407 struct si_shader *shader,
408 struct si_pm4_state *pm4)
409 {
410 unsigned type = sel->type;
411
412 if (sscreen->info.family < CHIP_POLARIS10)
413 return;
414
415 /* VS as VS, or VS as ES: */
416 if ((type == PIPE_SHADER_VERTEX &&
417 (!shader ||
418 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
419 /* TES as VS, or TES as ES: */
420 type == PIPE_SHADER_TESS_EVAL) {
421 unsigned vtx_reuse_depth = 30;
422
423 if (type == PIPE_SHADER_TESS_EVAL &&
424 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
425 PIPE_TESS_SPACING_FRACTIONAL_ODD)
426 vtx_reuse_depth = 14;
427
428 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
429 vtx_reuse_depth);
430 }
431 }
432
433 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
434 {
435 if (shader->pm4)
436 si_pm4_clear_state(shader->pm4);
437 else
438 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
439
440 return shader->pm4;
441 }
442
443 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
444 {
445 struct si_pm4_state *pm4;
446 unsigned vgpr_comp_cnt;
447 uint64_t va;
448
449 assert(sscreen->info.chip_class <= VI);
450
451 pm4 = si_get_shader_pm4_state(shader);
452 if (!pm4)
453 return;
454
455 va = shader->bo->gpu_address;
456 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
457
458 /* We need at least 2 components for LS.
459 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
460 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
461 */
462 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
463
464 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
465 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
466
467 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
468 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
469 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
470 S_00B528_DX10_CLAMP(1) |
471 S_00B528_FLOAT_MODE(shader->config.float_mode);
472 shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_VS_NUM_USER_SGPR) |
473 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
474 }
475
476 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
477 {
478 struct si_pm4_state *pm4;
479 uint64_t va;
480 unsigned ls_vgpr_comp_cnt = 0;
481
482 pm4 = si_get_shader_pm4_state(shader);
483 if (!pm4)
484 return;
485
486 va = shader->bo->gpu_address;
487 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
488
489 if (sscreen->info.chip_class >= GFX9) {
490 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
491 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, va >> 40);
492
493 /* We need at least 2 components for LS.
494 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
495 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
496 */
497 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
498
499 shader->config.rsrc2 =
500 S_00B42C_USER_SGPR(GFX9_TCS_NUM_USER_SGPR) |
501 S_00B42C_USER_SGPR_MSB(GFX9_TCS_NUM_USER_SGPR >> 5) |
502 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
503 } else {
504 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
505 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
506
507 shader->config.rsrc2 =
508 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
509 S_00B42C_OC_LDS_EN(1) |
510 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
511 }
512
513 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
514 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
515 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
516 S_00B428_DX10_CLAMP(1) |
517 S_00B428_FLOAT_MODE(shader->config.float_mode) |
518 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
519
520 if (sscreen->info.chip_class <= VI) {
521 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
522 shader->config.rsrc2);
523 }
524 }
525
526 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
527 {
528 struct si_pm4_state *pm4;
529 unsigned num_user_sgprs;
530 unsigned vgpr_comp_cnt;
531 uint64_t va;
532 unsigned oc_lds_en;
533
534 assert(sscreen->info.chip_class <= VI);
535
536 pm4 = si_get_shader_pm4_state(shader);
537 if (!pm4)
538 return;
539
540 va = shader->bo->gpu_address;
541 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
542
543 if (shader->selector->type == PIPE_SHADER_VERTEX) {
544 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
545 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
546 num_user_sgprs = SI_VS_NUM_USER_SGPR;
547 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
548 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
549 num_user_sgprs = SI_TES_NUM_USER_SGPR;
550 } else
551 unreachable("invalid shader selector type");
552
553 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
554
555 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
556 shader->selector->esgs_itemsize / 4);
557 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
558 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
559 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
560 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
561 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
562 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
563 S_00B328_DX10_CLAMP(1) |
564 S_00B328_FLOAT_MODE(shader->config.float_mode));
565 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
566 S_00B32C_USER_SGPR(num_user_sgprs) |
567 S_00B32C_OC_LDS_EN(oc_lds_en) |
568 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
569
570 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
571 si_set_tesseval_regs(sscreen, shader->selector, pm4);
572
573 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
574 }
575
576 struct gfx9_gs_info {
577 unsigned es_verts_per_subgroup;
578 unsigned gs_prims_per_subgroup;
579 unsigned gs_inst_prims_in_subgroup;
580 unsigned max_prims_per_subgroup;
581 unsigned lds_size;
582 };
583
584 static void gfx9_get_gs_info(struct si_shader_selector *es,
585 struct si_shader_selector *gs,
586 struct gfx9_gs_info *out)
587 {
588 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
589 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
590 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
591 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
592
593 /* All these are in dwords: */
594 /* We can't allow using the whole LDS, because GS waves compete with
595 * other shader stages for LDS space. */
596 const unsigned max_lds_size = 8 * 1024;
597 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
598 unsigned esgs_lds_size;
599
600 /* All these are per subgroup: */
601 const unsigned max_out_prims = 32 * 1024;
602 const unsigned max_es_verts = 255;
603 const unsigned ideal_gs_prims = 64;
604 unsigned max_gs_prims, gs_prims;
605 unsigned min_es_verts, es_verts, worst_case_es_verts;
606
607 assert(gs_num_invocations <= 32); /* GL maximum */
608
609 if (uses_adjacency || gs_num_invocations > 1)
610 max_gs_prims = 127 / gs_num_invocations;
611 else
612 max_gs_prims = 255;
613
614 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
615 * Make sure we don't go over the maximum value.
616 */
617 if (gs->gs_max_out_vertices > 0) {
618 max_gs_prims = MIN2(max_gs_prims,
619 max_out_prims /
620 (gs->gs_max_out_vertices * gs_num_invocations));
621 }
622 assert(max_gs_prims > 0);
623
624 /* If the primitive has adjacency, halve the number of vertices
625 * that will be reused in multiple primitives.
626 */
627 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
628
629 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
630 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
631
632 /* Compute ESGS LDS size based on the worst case number of ES vertices
633 * needed to create the target number of GS prims per subgroup.
634 */
635 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
636
637 /* If total LDS usage is too big, refactor partitions based on ratio
638 * of ESGS item sizes.
639 */
640 if (esgs_lds_size > max_lds_size) {
641 /* Our target GS Prims Per Subgroup was too large. Calculate
642 * the maximum number of GS Prims Per Subgroup that will fit
643 * into LDS, capped by the maximum that the hardware can support.
644 */
645 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
646 max_gs_prims);
647 assert(gs_prims > 0);
648 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
649 max_es_verts);
650
651 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
652 assert(esgs_lds_size <= max_lds_size);
653 }
654
655 /* Now calculate remaining ESGS information. */
656 if (esgs_lds_size)
657 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
658 else
659 es_verts = max_es_verts;
660
661 /* Vertices for adjacency primitives are not always reused, so restore
662 * it for ES_VERTS_PER_SUBGRP.
663 */
664 min_es_verts = gs->gs_input_verts_per_prim;
665
666 /* For normal primitives, the VGT only checks if they are past the ES
667 * verts per subgroup after allocating a full GS primitive and if they
668 * are, kick off a new subgroup. But if those additional ES verts are
669 * unique (e.g. not reused) we need to make sure there is enough LDS
670 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
671 */
672 es_verts -= min_es_verts - 1;
673
674 out->es_verts_per_subgroup = es_verts;
675 out->gs_prims_per_subgroup = gs_prims;
676 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
677 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
678 gs->gs_max_out_vertices;
679 out->lds_size = align(esgs_lds_size, 128) / 128;
680
681 assert(out->max_prims_per_subgroup <= max_out_prims);
682 }
683
684 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
685 {
686 struct si_shader_selector *sel = shader->selector;
687 const ubyte *num_components = sel->info.num_stream_output_components;
688 unsigned gs_num_invocations = sel->gs_num_invocations;
689 struct si_pm4_state *pm4;
690 uint64_t va;
691 unsigned max_stream = sel->max_gs_stream;
692 unsigned offset;
693
694 pm4 = si_get_shader_pm4_state(shader);
695 if (!pm4)
696 return;
697
698 offset = num_components[0] * sel->gs_max_out_vertices;
699 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, offset);
700 if (max_stream >= 1)
701 offset += num_components[1] * sel->gs_max_out_vertices;
702 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, offset);
703 if (max_stream >= 2)
704 offset += num_components[2] * sel->gs_max_out_vertices;
705 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, offset);
706 if (max_stream >= 3)
707 offset += num_components[3] * sel->gs_max_out_vertices;
708 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
709
710 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
711 assert(offset < (1 << 15));
712
713 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, sel->gs_max_out_vertices);
714
715 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, num_components[0]);
716 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? num_components[1] : 0);
717 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? num_components[2] : 0);
718 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? num_components[3] : 0);
719
720 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
721 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
722 S_028B90_ENABLE(gs_num_invocations > 0));
723
724 va = shader->bo->gpu_address;
725 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
726
727 if (sscreen->info.chip_class >= GFX9) {
728 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
729 unsigned es_type = shader->key.part.gs.es->type;
730 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
731 struct gfx9_gs_info gs_info;
732
733 if (es_type == PIPE_SHADER_VERTEX)
734 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
735 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
736 else if (es_type == PIPE_SHADER_TESS_EVAL)
737 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
738 else
739 unreachable("invalid shader selector type");
740
741 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
742 * VGPR[0:4] are always loaded.
743 */
744 if (sel->info.uses_invocationid)
745 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
746 else if (sel->info.uses_primid)
747 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
748 else if (input_prim >= PIPE_PRIM_TRIANGLES)
749 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
750 else
751 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
752
753 gfx9_get_gs_info(shader->key.part.gs.es, sel, &gs_info);
754
755 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
756 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, va >> 40);
757
758 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
759 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
760 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
761 S_00B228_DX10_CLAMP(1) |
762 S_00B228_FLOAT_MODE(shader->config.float_mode) |
763 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
764 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
765 S_00B22C_USER_SGPR(GFX9_GS_NUM_USER_SGPR) |
766 S_00B22C_USER_SGPR_MSB(GFX9_GS_NUM_USER_SGPR >> 5) |
767 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
768 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
769 S_00B22C_LDS_SIZE(gs_info.lds_size) |
770 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
771
772 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
773 S_028A44_ES_VERTS_PER_SUBGRP(gs_info.es_verts_per_subgroup) |
774 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info.gs_prims_per_subgroup) |
775 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info.gs_inst_prims_in_subgroup));
776 si_pm4_set_reg(pm4, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
777 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info.max_prims_per_subgroup));
778 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
779 shader->key.part.gs.es->esgs_itemsize / 4);
780
781 if (es_type == PIPE_SHADER_TESS_EVAL)
782 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
783
784 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
785 NULL, pm4);
786 } else {
787 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
788 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
789
790 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
791 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
792 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
793 S_00B228_DX10_CLAMP(1) |
794 S_00B228_FLOAT_MODE(shader->config.float_mode));
795 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
796 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
797 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
798 }
799 }
800
801 /**
802 * Compute the state for \p shader, which will run as a vertex shader on the
803 * hardware.
804 *
805 * If \p gs is non-NULL, it points to the geometry shader for which this shader
806 * is the copy shader.
807 */
808 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
809 struct si_shader_selector *gs)
810 {
811 const struct tgsi_shader_info *info = &shader->selector->info;
812 struct si_pm4_state *pm4;
813 unsigned num_user_sgprs;
814 unsigned nparams, vgpr_comp_cnt;
815 uint64_t va;
816 unsigned oc_lds_en;
817 unsigned window_space =
818 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
819 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
820
821 pm4 = si_get_shader_pm4_state(shader);
822 if (!pm4)
823 return;
824
825 /* We always write VGT_GS_MODE in the VS state, because every switch
826 * between different shader pipelines involving a different GS or no
827 * GS at all involves a switch of the VS (different GS use different
828 * copy shaders). On the other hand, when the API switches from a GS to
829 * no GS and then back to the same GS used originally, the GS state is
830 * not sent again.
831 */
832 if (!gs) {
833 unsigned mode = V_028A40_GS_OFF;
834
835 /* PrimID needs GS scenario A. */
836 if (enable_prim_id)
837 mode = V_028A40_GS_SCENARIO_A;
838
839 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, S_028A40_MODE(mode));
840 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
841 } else {
842 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
843 ac_vgt_gs_mode(gs->gs_max_out_vertices,
844 sscreen->info.chip_class));
845 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
846 }
847
848 if (sscreen->info.chip_class <= VI) {
849 /* Reuse needs to be set off if we write oViewport. */
850 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF,
851 S_028AB4_REUSE_OFF(info->writes_viewport_index));
852 }
853
854 va = shader->bo->gpu_address;
855 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
856
857 if (gs) {
858 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
859 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
860 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
861 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
862 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
863 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
864 */
865 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
866
867 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
868 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
869 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
870 } else {
871 num_user_sgprs = SI_VS_NUM_USER_SGPR;
872 }
873 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
874 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
875 num_user_sgprs = SI_TES_NUM_USER_SGPR;
876 } else
877 unreachable("invalid shader selector type");
878
879 /* VS is required to export at least one param. */
880 nparams = MAX2(shader->info.nr_param_exports, 1);
881 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
882 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
883
884 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
885 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
886 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
887 V_02870C_SPI_SHADER_4COMP :
888 V_02870C_SPI_SHADER_NONE) |
889 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
890 V_02870C_SPI_SHADER_4COMP :
891 V_02870C_SPI_SHADER_NONE) |
892 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
893 V_02870C_SPI_SHADER_4COMP :
894 V_02870C_SPI_SHADER_NONE));
895
896 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
897
898 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
899 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
900 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
901 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
902 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
903 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
904 S_00B128_DX10_CLAMP(1) |
905 S_00B128_FLOAT_MODE(shader->config.float_mode));
906 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
907 S_00B12C_USER_SGPR(num_user_sgprs) |
908 S_00B12C_OC_LDS_EN(oc_lds_en) |
909 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
910 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
911 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
912 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
913 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
914 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
915 if (window_space)
916 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
917 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
918 else
919 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
920 S_028818_VTX_W0_FMT(1) |
921 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
922 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
923 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
924
925 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
926 si_set_tesseval_regs(sscreen, shader->selector, pm4);
927
928 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
929 }
930
931 static unsigned si_get_ps_num_interp(struct si_shader *ps)
932 {
933 struct tgsi_shader_info *info = &ps->selector->info;
934 unsigned num_colors = !!(info->colors_read & 0x0f) +
935 !!(info->colors_read & 0xf0);
936 unsigned num_interp = ps->selector->info.num_inputs +
937 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
938
939 assert(num_interp <= 32);
940 return MIN2(num_interp, 32);
941 }
942
943 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
944 {
945 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
946 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
947
948 /* If the i-th target format is set, all previous target formats must
949 * be non-zero to avoid hangs.
950 */
951 for (i = 0; i < num_targets; i++)
952 if (!(value & (0xf << (i * 4))))
953 value |= V_028714_SPI_SHADER_32_R << (i * 4);
954
955 return value;
956 }
957
958 static void si_shader_ps(struct si_shader *shader)
959 {
960 struct tgsi_shader_info *info = &shader->selector->info;
961 struct si_pm4_state *pm4;
962 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
963 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
964 uint64_t va;
965 unsigned input_ena = shader->config.spi_ps_input_ena;
966
967 /* we need to enable at least one of them, otherwise we hang the GPU */
968 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
969 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
970 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
971 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
972 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
973 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
974 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
975 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
976 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
977 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
978 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
979 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
980 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
981 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
982
983 /* Validate interpolation optimization flags (read as implications). */
984 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
985 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
986 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
987 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
988 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
989 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
990 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
991 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
992 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
993 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
994 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
995 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
996 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
997 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
998 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
999 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1000 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1001 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1002
1003 /* Validate cases when the optimizations are off (read as implications). */
1004 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1005 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1006 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1007 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1008 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1009 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1010
1011 pm4 = si_get_shader_pm4_state(shader);
1012 if (!pm4)
1013 return;
1014
1015 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1016 * Possible vaules:
1017 * 0 -> Position = pixel center
1018 * 1 -> Position = pixel centroid
1019 * 2 -> Position = at sample position
1020 *
1021 * From GLSL 4.5 specification, section 7.1:
1022 * "The variable gl_FragCoord is available as an input variable from
1023 * within fragment shaders and it holds the window relative coordinates
1024 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1025 * value can be for any location within the pixel, or one of the
1026 * fragment samples. The use of centroid does not further restrict
1027 * this value to be inside the current primitive."
1028 *
1029 * Meaning that centroid has no effect and we can return anything within
1030 * the pixel. Thus, return the value at sample position, because that's
1031 * the most accurate one shaders can get.
1032 */
1033 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1034
1035 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1036 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1037 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1038
1039 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1040 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1041
1042 /* Ensure that some export memory is always allocated, for two reasons:
1043 *
1044 * 1) Correctness: The hardware ignores the EXEC mask if no export
1045 * memory is allocated, so KILL and alpha test do not work correctly
1046 * without this.
1047 * 2) Performance: Every shader needs at least a NULL export, even when
1048 * it writes no color/depth output. The NULL export instruction
1049 * stalls without this setting.
1050 *
1051 * Don't add this to CB_SHADER_MASK.
1052 */
1053 if (!spi_shader_col_format &&
1054 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1055 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1056
1057 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
1058 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
1059 shader->config.spi_ps_input_addr);
1060
1061 /* Set interpolation controls. */
1062 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1063
1064 /* Set registers. */
1065 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1066 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
1067
1068 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
1069 ac_get_spi_shader_z_format(info->writes_z,
1070 info->writes_stencil,
1071 info->writes_samplemask));
1072
1073 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
1074 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
1075
1076 va = shader->bo->gpu_address;
1077 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1078 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1079 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
1080
1081 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
1082 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1083 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
1084 S_00B028_DX10_CLAMP(1) |
1085 S_00B028_FLOAT_MODE(shader->config.float_mode));
1086 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1087 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1088 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1089 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1090 }
1091
1092 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1093 struct si_shader *shader)
1094 {
1095 switch (shader->selector->type) {
1096 case PIPE_SHADER_VERTEX:
1097 if (shader->key.as_ls)
1098 si_shader_ls(sscreen, shader);
1099 else if (shader->key.as_es)
1100 si_shader_es(sscreen, shader);
1101 else
1102 si_shader_vs(sscreen, shader, NULL);
1103 break;
1104 case PIPE_SHADER_TESS_CTRL:
1105 si_shader_hs(sscreen, shader);
1106 break;
1107 case PIPE_SHADER_TESS_EVAL:
1108 if (shader->key.as_es)
1109 si_shader_es(sscreen, shader);
1110 else
1111 si_shader_vs(sscreen, shader, NULL);
1112 break;
1113 case PIPE_SHADER_GEOMETRY:
1114 si_shader_gs(sscreen, shader);
1115 break;
1116 case PIPE_SHADER_FRAGMENT:
1117 si_shader_ps(shader);
1118 break;
1119 default:
1120 assert(0);
1121 }
1122 }
1123
1124 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1125 {
1126 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1127 if (sctx->queued.named.dsa)
1128 return sctx->queued.named.dsa->alpha_func;
1129
1130 return PIPE_FUNC_ALWAYS;
1131 }
1132
1133 static void si_shader_selector_key_vs(struct si_context *sctx,
1134 struct si_shader_selector *vs,
1135 struct si_shader_key *key,
1136 struct si_vs_prolog_bits *prolog_key)
1137 {
1138 if (!sctx->vertex_elements)
1139 return;
1140
1141 prolog_key->instance_divisor_is_one =
1142 sctx->vertex_elements->instance_divisor_is_one;
1143 prolog_key->instance_divisor_is_fetched =
1144 sctx->vertex_elements->instance_divisor_is_fetched;
1145
1146 /* Prefer a monolithic shader to allow scheduling divisions around
1147 * VBO loads. */
1148 if (prolog_key->instance_divisor_is_fetched)
1149 key->opt.prefer_mono = 1;
1150
1151 unsigned count = MIN2(vs->info.num_inputs,
1152 sctx->vertex_elements->count);
1153 memcpy(key->mono.vs_fix_fetch, sctx->vertex_elements->fix_fetch, count);
1154 }
1155
1156 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1157 struct si_shader_selector *vs,
1158 struct si_shader_key *key)
1159 {
1160 struct si_shader_selector *ps = sctx->ps_shader.cso;
1161
1162 key->opt.clip_disable =
1163 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1164 (vs->info.clipdist_writemask ||
1165 vs->info.writes_clipvertex) &&
1166 !vs->info.culldist_writemask;
1167
1168 /* Find out if PS is disabled. */
1169 bool ps_disabled = true;
1170 if (ps) {
1171 bool ps_modifies_zs = ps->info.uses_kill ||
1172 ps->info.writes_z ||
1173 ps->info.writes_stencil ||
1174 ps->info.writes_samplemask ||
1175 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1176
1177 unsigned ps_colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1178 sctx->queued.named.blend->cb_target_mask;
1179 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1180 ps_colormask &= ps->colors_written_4bit;
1181
1182 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1183 (!ps_colormask &&
1184 !ps_modifies_zs &&
1185 !ps->info.writes_memory);
1186 }
1187
1188 /* Find out which VS outputs aren't used by the PS. */
1189 uint64_t outputs_written = vs->outputs_written;
1190 uint64_t inputs_read = 0;
1191
1192 /* ignore POSITION, PSIZE */
1193 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0) |
1194 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0))));
1195
1196 if (!ps_disabled) {
1197 inputs_read = ps->inputs_read;
1198 }
1199
1200 uint64_t linked = outputs_written & inputs_read;
1201
1202 key->opt.kill_outputs = ~linked & outputs_written;
1203 }
1204
1205 /* Compute the key for the hw shader variant */
1206 static inline void si_shader_selector_key(struct pipe_context *ctx,
1207 struct si_shader_selector *sel,
1208 struct si_shader_key *key)
1209 {
1210 struct si_context *sctx = (struct si_context *)ctx;
1211
1212 memset(key, 0, sizeof(*key));
1213
1214 switch (sel->type) {
1215 case PIPE_SHADER_VERTEX:
1216 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1217
1218 if (sctx->tes_shader.cso)
1219 key->as_ls = 1;
1220 else if (sctx->gs_shader.cso)
1221 key->as_es = 1;
1222 else {
1223 si_shader_selector_key_hw_vs(sctx, sel, key);
1224
1225 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1226 key->mono.u.vs_export_prim_id = 1;
1227 }
1228 break;
1229 case PIPE_SHADER_TESS_CTRL:
1230 if (sctx->b.chip_class >= GFX9) {
1231 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1232 key, &key->part.tcs.ls_prolog);
1233 key->part.tcs.ls = sctx->vs_shader.cso;
1234
1235 /* When the LS VGPR fix is needed, monolithic shaders
1236 * can:
1237 * - avoid initializing EXEC in both the LS prolog
1238 * and the LS main part when !vs_needs_prolog
1239 * - remove the fixup for unused input VGPRs
1240 */
1241 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1242
1243 /* The LS output / HS input layout can be communicated
1244 * directly instead of via user SGPRs for merged LS-HS.
1245 * The LS VGPR fix prefers this too.
1246 */
1247 key->opt.prefer_mono = 1;
1248 }
1249
1250 key->part.tcs.epilog.prim_mode =
1251 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1252 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1253 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1254 key->part.tcs.epilog.tes_reads_tess_factors =
1255 sctx->tes_shader.cso->info.reads_tess_factors;
1256
1257 if (sel == sctx->fixed_func_tcs_shader.cso)
1258 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1259 break;
1260 case PIPE_SHADER_TESS_EVAL:
1261 if (sctx->gs_shader.cso)
1262 key->as_es = 1;
1263 else {
1264 si_shader_selector_key_hw_vs(sctx, sel, key);
1265
1266 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1267 key->mono.u.vs_export_prim_id = 1;
1268 }
1269 break;
1270 case PIPE_SHADER_GEOMETRY:
1271 if (sctx->b.chip_class >= GFX9) {
1272 if (sctx->tes_shader.cso) {
1273 key->part.gs.es = sctx->tes_shader.cso;
1274 } else {
1275 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1276 key, &key->part.gs.vs_prolog);
1277 key->part.gs.es = sctx->vs_shader.cso;
1278 }
1279
1280 /* Merged ES-GS can have unbalanced wave usage.
1281 *
1282 * ES threads are per-vertex, while GS threads are
1283 * per-primitive. So without any amplification, there
1284 * are fewer GS threads than ES threads, which can result
1285 * in empty (no-op) GS waves. With too much amplification,
1286 * there are more GS threads than ES threads, which
1287 * can result in empty (no-op) ES waves.
1288 *
1289 * Non-monolithic shaders are implemented by setting EXEC
1290 * at the beginning of shader parts, and don't jump to
1291 * the end if EXEC is 0.
1292 *
1293 * Monolithic shaders use conditional blocks, so they can
1294 * jump and skip empty waves of ES or GS. So set this to
1295 * always use optimized variants, which are monolithic.
1296 */
1297 key->opt.prefer_mono = 1;
1298 }
1299 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1300 break;
1301 case PIPE_SHADER_FRAGMENT: {
1302 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1303 struct si_state_blend *blend = sctx->queued.named.blend;
1304
1305 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1306 sel->info.colors_written == 0x1)
1307 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1308
1309 if (blend) {
1310 /* Select the shader color format based on whether
1311 * blending or alpha are needed.
1312 */
1313 key->part.ps.epilog.spi_shader_col_format =
1314 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1315 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1316 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1317 sctx->framebuffer.spi_shader_col_format_blend) |
1318 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1319 sctx->framebuffer.spi_shader_col_format_alpha) |
1320 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1321 sctx->framebuffer.spi_shader_col_format);
1322 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1323
1324 /* The output for dual source blending should have
1325 * the same format as the first output.
1326 */
1327 if (blend->dual_src_blend)
1328 key->part.ps.epilog.spi_shader_col_format |=
1329 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1330 } else
1331 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1332
1333 /* If alpha-to-coverage is enabled, we have to export alpha
1334 * even if there is no color buffer.
1335 */
1336 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1337 blend && blend->alpha_to_coverage)
1338 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1339
1340 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1341 * to the range supported by the type if a channel has less
1342 * than 16 bits and the export format is 16_ABGR.
1343 */
1344 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII) {
1345 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1346 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1347 }
1348
1349 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1350 if (!key->part.ps.epilog.last_cbuf) {
1351 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1352 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1353 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1354 }
1355
1356 if (rs) {
1357 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
1358 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
1359 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
1360 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
1361
1362 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1363 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1364
1365 if (sctx->queued.named.blend) {
1366 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1367 rs->multisample_enable;
1368 }
1369
1370 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1371 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1372 (is_line && rs->line_smooth)) &&
1373 sctx->framebuffer.nr_samples <= 1;
1374 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1375
1376 if (sctx->ps_iter_samples > 1 &&
1377 sel->info.reads_samplemask) {
1378 key->part.ps.prolog.samplemask_log_ps_iter =
1379 util_logbase2(util_next_power_of_two(sctx->ps_iter_samples));
1380 }
1381
1382 if (rs->force_persample_interp &&
1383 rs->multisample_enable &&
1384 sctx->framebuffer.nr_samples > 1 &&
1385 sctx->ps_iter_samples > 1) {
1386 key->part.ps.prolog.force_persp_sample_interp =
1387 sel->info.uses_persp_center ||
1388 sel->info.uses_persp_centroid;
1389
1390 key->part.ps.prolog.force_linear_sample_interp =
1391 sel->info.uses_linear_center ||
1392 sel->info.uses_linear_centroid;
1393 } else if (rs->multisample_enable &&
1394 sctx->framebuffer.nr_samples > 1) {
1395 key->part.ps.prolog.bc_optimize_for_persp =
1396 sel->info.uses_persp_center &&
1397 sel->info.uses_persp_centroid;
1398 key->part.ps.prolog.bc_optimize_for_linear =
1399 sel->info.uses_linear_center &&
1400 sel->info.uses_linear_centroid;
1401 } else {
1402 /* Make sure SPI doesn't compute more than 1 pair
1403 * of (i,j), which is the optimization here. */
1404 key->part.ps.prolog.force_persp_center_interp =
1405 sel->info.uses_persp_center +
1406 sel->info.uses_persp_centroid +
1407 sel->info.uses_persp_sample > 1;
1408
1409 key->part.ps.prolog.force_linear_center_interp =
1410 sel->info.uses_linear_center +
1411 sel->info.uses_linear_centroid +
1412 sel->info.uses_linear_sample > 1;
1413
1414 if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
1415 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1416 }
1417 }
1418
1419 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1420 break;
1421 }
1422 default:
1423 assert(0);
1424 }
1425
1426 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
1427 memset(&key->opt, 0, sizeof(key->opt));
1428 }
1429
1430 static void si_build_shader_variant(struct si_shader *shader,
1431 int thread_index,
1432 bool low_priority)
1433 {
1434 struct si_shader_selector *sel = shader->selector;
1435 struct si_screen *sscreen = sel->screen;
1436 LLVMTargetMachineRef tm;
1437 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1438 int r;
1439
1440 if (thread_index >= 0) {
1441 if (low_priority) {
1442 assert(thread_index < ARRAY_SIZE(sscreen->tm_low_priority));
1443 tm = sscreen->tm_low_priority[thread_index];
1444 } else {
1445 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1446 tm = sscreen->tm[thread_index];
1447 }
1448 if (!debug->async)
1449 debug = NULL;
1450 } else {
1451 assert(!low_priority);
1452 tm = shader->compiler_ctx_state.tm;
1453 }
1454
1455 r = si_shader_create(sscreen, tm, shader, debug);
1456 if (unlikely(r)) {
1457 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1458 sel->type, r);
1459 shader->compilation_failed = true;
1460 return;
1461 }
1462
1463 if (shader->compiler_ctx_state.is_debug_context) {
1464 FILE *f = open_memstream(&shader->shader_log,
1465 &shader->shader_log_size);
1466 if (f) {
1467 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1468 fclose(f);
1469 }
1470 }
1471
1472 si_shader_init_pm4_state(sscreen, shader);
1473 }
1474
1475 static void si_build_shader_variant_low_priority(void *job, int thread_index)
1476 {
1477 struct si_shader *shader = (struct si_shader *)job;
1478
1479 assert(thread_index >= 0);
1480
1481 si_build_shader_variant(shader, thread_index, true);
1482 }
1483
1484 static const struct si_shader_key zeroed;
1485
1486 static bool si_check_missing_main_part(struct si_screen *sscreen,
1487 struct si_shader_selector *sel,
1488 struct si_compiler_ctx_state *compiler_state,
1489 struct si_shader_key *key)
1490 {
1491 struct si_shader **mainp = si_get_main_shader_part(sel, key);
1492
1493 if (!*mainp) {
1494 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1495
1496 if (!main_part)
1497 return false;
1498
1499 /* We can leave the fence as permanently signaled because the
1500 * main part becomes visible globally only after it has been
1501 * compiled. */
1502 util_queue_fence_init(&main_part->ready);
1503
1504 main_part->selector = sel;
1505 main_part->key.as_es = key->as_es;
1506 main_part->key.as_ls = key->as_ls;
1507
1508 if (si_compile_tgsi_shader(sscreen, compiler_state->tm,
1509 main_part, false,
1510 &compiler_state->debug) != 0) {
1511 FREE(main_part);
1512 return false;
1513 }
1514 *mainp = main_part;
1515 }
1516 return true;
1517 }
1518
1519 /* Select the hw shader variant depending on the current state. */
1520 static int si_shader_select_with_key(struct si_screen *sscreen,
1521 struct si_shader_ctx_state *state,
1522 struct si_compiler_ctx_state *compiler_state,
1523 struct si_shader_key *key,
1524 int thread_index)
1525 {
1526 struct si_shader_selector *sel = state->cso;
1527 struct si_shader_selector *previous_stage_sel = NULL;
1528 struct si_shader *current = state->current;
1529 struct si_shader *iter, *shader = NULL;
1530
1531 again:
1532 /* Check if we don't need to change anything.
1533 * This path is also used for most shaders that don't need multiple
1534 * variants, it will cost just a computation of the key and this
1535 * test. */
1536 if (likely(current &&
1537 memcmp(&current->key, key, sizeof(*key)) == 0)) {
1538 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
1539 if (current->is_optimized) {
1540 memset(&key->opt, 0, sizeof(key->opt));
1541 goto current_not_ready;
1542 }
1543
1544 util_queue_fence_wait(&current->ready);
1545 }
1546
1547 return current->compilation_failed ? -1 : 0;
1548 }
1549 current_not_ready:
1550
1551 /* This must be done before the mutex is locked, because async GS
1552 * compilation calls this function too, and therefore must enter
1553 * the mutex first.
1554 *
1555 * Only wait if we are in a draw call. Don't wait if we are
1556 * in a compiler thread.
1557 */
1558 if (thread_index < 0)
1559 util_queue_fence_wait(&sel->ready);
1560
1561 mtx_lock(&sel->mutex);
1562
1563 /* Find the shader variant. */
1564 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1565 /* Don't check the "current" shader. We checked it above. */
1566 if (current != iter &&
1567 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1568 mtx_unlock(&sel->mutex);
1569
1570 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
1571 /* If it's an optimized shader and its compilation has
1572 * been started but isn't done, use the unoptimized
1573 * shader so as not to cause a stall due to compilation.
1574 */
1575 if (iter->is_optimized) {
1576 memset(&key->opt, 0, sizeof(key->opt));
1577 goto again;
1578 }
1579
1580 util_queue_fence_wait(&iter->ready);
1581 }
1582
1583 if (iter->compilation_failed) {
1584 return -1; /* skip the draw call */
1585 }
1586
1587 state->current = iter;
1588 return 0;
1589 }
1590 }
1591
1592 /* Build a new shader. */
1593 shader = CALLOC_STRUCT(si_shader);
1594 if (!shader) {
1595 mtx_unlock(&sel->mutex);
1596 return -ENOMEM;
1597 }
1598
1599 util_queue_fence_init(&shader->ready);
1600
1601 shader->selector = sel;
1602 shader->key = *key;
1603 shader->compiler_ctx_state = *compiler_state;
1604
1605 /* If this is a merged shader, get the first shader's selector. */
1606 if (sscreen->info.chip_class >= GFX9) {
1607 if (sel->type == PIPE_SHADER_TESS_CTRL)
1608 previous_stage_sel = key->part.tcs.ls;
1609 else if (sel->type == PIPE_SHADER_GEOMETRY)
1610 previous_stage_sel = key->part.gs.es;
1611
1612 /* We need to wait for the previous shader. */
1613 if (previous_stage_sel && thread_index < 0)
1614 util_queue_fence_wait(&previous_stage_sel->ready);
1615 }
1616
1617 /* Compile the main shader part if it doesn't exist. This can happen
1618 * if the initial guess was wrong. */
1619 bool is_pure_monolithic =
1620 sscreen->use_monolithic_shaders ||
1621 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1622
1623 if (!is_pure_monolithic) {
1624 bool ok;
1625
1626 /* Make sure the main shader part is present. This is needed
1627 * for shaders that can be compiled as VS, LS, or ES, and only
1628 * one of them is compiled at creation.
1629 *
1630 * For merged shaders, check that the starting shader's main
1631 * part is present.
1632 */
1633 if (previous_stage_sel) {
1634 struct si_shader_key shader1_key = zeroed;
1635
1636 if (sel->type == PIPE_SHADER_TESS_CTRL)
1637 shader1_key.as_ls = 1;
1638 else if (sel->type == PIPE_SHADER_GEOMETRY)
1639 shader1_key.as_es = 1;
1640 else
1641 assert(0);
1642
1643 mtx_lock(&previous_stage_sel->mutex);
1644 ok = si_check_missing_main_part(sscreen,
1645 previous_stage_sel,
1646 compiler_state, &shader1_key);
1647 mtx_unlock(&previous_stage_sel->mutex);
1648 } else {
1649 ok = si_check_missing_main_part(sscreen, sel,
1650 compiler_state, key);
1651 }
1652 if (!ok) {
1653 FREE(shader);
1654 mtx_unlock(&sel->mutex);
1655 return -ENOMEM; /* skip the draw call */
1656 }
1657 }
1658
1659 /* Keep the reference to the 1st shader of merged shaders, so that
1660 * Gallium can't destroy it before we destroy the 2nd shader.
1661 *
1662 * Set sctx = NULL, because it's unused if we're not releasing
1663 * the shader, and we don't have any sctx here.
1664 */
1665 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
1666 previous_stage_sel);
1667
1668 /* Monolithic-only shaders don't make a distinction between optimized
1669 * and unoptimized. */
1670 shader->is_monolithic =
1671 is_pure_monolithic ||
1672 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1673
1674 shader->is_optimized =
1675 !is_pure_monolithic &&
1676 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1677
1678 /* If it's an optimized shader, compile it asynchronously. */
1679 if (shader->is_optimized &&
1680 !is_pure_monolithic &&
1681 thread_index < 0) {
1682 /* Compile it asynchronously. */
1683 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
1684 shader, &shader->ready,
1685 si_build_shader_variant_low_priority, NULL);
1686
1687 /* Add only after the ready fence was reset, to guard against a
1688 * race with si_bind_XX_shader. */
1689 if (!sel->last_variant) {
1690 sel->first_variant = shader;
1691 sel->last_variant = shader;
1692 } else {
1693 sel->last_variant->next_variant = shader;
1694 sel->last_variant = shader;
1695 }
1696
1697 /* Use the default (unoptimized) shader for now. */
1698 memset(&key->opt, 0, sizeof(key->opt));
1699 mtx_unlock(&sel->mutex);
1700 goto again;
1701 }
1702
1703 /* Reset the fence before adding to the variant list. */
1704 util_queue_fence_reset(&shader->ready);
1705
1706 if (!sel->last_variant) {
1707 sel->first_variant = shader;
1708 sel->last_variant = shader;
1709 } else {
1710 sel->last_variant->next_variant = shader;
1711 sel->last_variant = shader;
1712 }
1713
1714 mtx_unlock(&sel->mutex);
1715
1716 assert(!shader->is_optimized);
1717 si_build_shader_variant(shader, thread_index, false);
1718
1719 util_queue_fence_signal(&shader->ready);
1720
1721 if (!shader->compilation_failed)
1722 state->current = shader;
1723
1724 return shader->compilation_failed ? -1 : 0;
1725 }
1726
1727 static int si_shader_select(struct pipe_context *ctx,
1728 struct si_shader_ctx_state *state,
1729 struct si_compiler_ctx_state *compiler_state)
1730 {
1731 struct si_context *sctx = (struct si_context *)ctx;
1732 struct si_shader_key key;
1733
1734 si_shader_selector_key(ctx, state->cso, &key);
1735 return si_shader_select_with_key(sctx->screen, state, compiler_state,
1736 &key, -1);
1737 }
1738
1739 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1740 bool streamout,
1741 struct si_shader_key *key)
1742 {
1743 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1744
1745 switch (info->processor) {
1746 case PIPE_SHADER_VERTEX:
1747 switch (next_shader) {
1748 case PIPE_SHADER_GEOMETRY:
1749 key->as_es = 1;
1750 break;
1751 case PIPE_SHADER_TESS_CTRL:
1752 case PIPE_SHADER_TESS_EVAL:
1753 key->as_ls = 1;
1754 break;
1755 default:
1756 /* If POSITION isn't written, it can only be a HW VS
1757 * if streamout is used. If streamout isn't used,
1758 * assume that it's a HW LS. (the next shader is TCS)
1759 * This heuristic is needed for separate shader objects.
1760 */
1761 if (!info->writes_position && !streamout)
1762 key->as_ls = 1;
1763 }
1764 break;
1765
1766 case PIPE_SHADER_TESS_EVAL:
1767 if (next_shader == PIPE_SHADER_GEOMETRY ||
1768 !info->writes_position)
1769 key->as_es = 1;
1770 break;
1771 }
1772 }
1773
1774 /**
1775 * Compile the main shader part or the monolithic shader as part of
1776 * si_shader_selector initialization. Since it can be done asynchronously,
1777 * there is no way to report compile failures to applications.
1778 */
1779 static void si_init_shader_selector_async(void *job, int thread_index)
1780 {
1781 struct si_shader_selector *sel = (struct si_shader_selector *)job;
1782 struct si_screen *sscreen = sel->screen;
1783 LLVMTargetMachineRef tm;
1784 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
1785 unsigned i;
1786
1787 assert(!debug->debug_message || debug->async);
1788 assert(thread_index >= 0);
1789 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1790 tm = sscreen->tm[thread_index];
1791
1792 /* Compile the main shader part for use with a prolog and/or epilog.
1793 * If this fails, the driver will try to compile a monolithic shader
1794 * on demand.
1795 */
1796 if (!sscreen->use_monolithic_shaders) {
1797 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1798 void *tgsi_binary = NULL;
1799
1800 if (!shader) {
1801 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
1802 return;
1803 }
1804
1805 /* We can leave the fence signaled because use of the default
1806 * main part is guarded by the selector's ready fence. */
1807 util_queue_fence_init(&shader->ready);
1808
1809 shader->selector = sel;
1810 si_parse_next_shader_property(&sel->info,
1811 sel->so.num_outputs != 0,
1812 &shader->key);
1813
1814 if (sel->tokens)
1815 tgsi_binary = si_get_tgsi_binary(sel);
1816
1817 /* Try to load the shader from the shader cache. */
1818 mtx_lock(&sscreen->shader_cache_mutex);
1819
1820 if (tgsi_binary &&
1821 si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
1822 mtx_unlock(&sscreen->shader_cache_mutex);
1823 } else {
1824 mtx_unlock(&sscreen->shader_cache_mutex);
1825
1826 /* Compile the shader if it hasn't been loaded from the cache. */
1827 if (si_compile_tgsi_shader(sscreen, tm, shader, false,
1828 debug) != 0) {
1829 FREE(shader);
1830 FREE(tgsi_binary);
1831 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
1832 return;
1833 }
1834
1835 if (tgsi_binary) {
1836 mtx_lock(&sscreen->shader_cache_mutex);
1837 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary, shader, true))
1838 FREE(tgsi_binary);
1839 mtx_unlock(&sscreen->shader_cache_mutex);
1840 }
1841 }
1842
1843 *si_get_main_shader_part(sel, &shader->key) = shader;
1844
1845 /* Unset "outputs_written" flags for outputs converted to
1846 * DEFAULT_VAL, so that later inter-shader optimizations don't
1847 * try to eliminate outputs that don't exist in the final
1848 * shader.
1849 *
1850 * This is only done if non-monolithic shaders are enabled.
1851 */
1852 if ((sel->type == PIPE_SHADER_VERTEX ||
1853 sel->type == PIPE_SHADER_TESS_EVAL) &&
1854 !shader->key.as_ls &&
1855 !shader->key.as_es) {
1856 unsigned i;
1857
1858 for (i = 0; i < sel->info.num_outputs; i++) {
1859 unsigned offset = shader->info.vs_output_param_offset[i];
1860
1861 if (offset <= AC_EXP_PARAM_OFFSET_31)
1862 continue;
1863
1864 unsigned name = sel->info.output_semantic_name[i];
1865 unsigned index = sel->info.output_semantic_index[i];
1866 unsigned id;
1867
1868 switch (name) {
1869 case TGSI_SEMANTIC_GENERIC:
1870 /* don't process indices the function can't handle */
1871 if (index >= SI_MAX_IO_GENERIC)
1872 break;
1873 /* fall through */
1874 default:
1875 id = si_shader_io_get_unique_index(name, index);
1876 sel->outputs_written &= ~(1ull << id);
1877 break;
1878 case TGSI_SEMANTIC_POSITION: /* ignore these */
1879 case TGSI_SEMANTIC_PSIZE:
1880 case TGSI_SEMANTIC_CLIPVERTEX:
1881 case TGSI_SEMANTIC_EDGEFLAG:
1882 break;
1883 }
1884 }
1885 }
1886 }
1887
1888 /* Pre-compilation. */
1889 if (sscreen->debug_flags & DBG(PRECOMPILE) &&
1890 /* GFX9 needs LS or ES for compilation, which we don't have here. */
1891 (sscreen->info.chip_class <= VI ||
1892 (sel->type != PIPE_SHADER_TESS_CTRL &&
1893 sel->type != PIPE_SHADER_GEOMETRY))) {
1894 struct si_shader_ctx_state state = {sel};
1895 struct si_shader_key key;
1896
1897 memset(&key, 0, sizeof(key));
1898 si_parse_next_shader_property(&sel->info,
1899 sel->so.num_outputs != 0,
1900 &key);
1901
1902 /* GFX9 doesn't have LS and ES. */
1903 if (sscreen->info.chip_class >= GFX9) {
1904 key.as_ls = 0;
1905 key.as_es = 0;
1906 }
1907
1908 /* Set reasonable defaults, so that the shader key doesn't
1909 * cause any code to be eliminated.
1910 */
1911 switch (sel->type) {
1912 case PIPE_SHADER_TESS_CTRL:
1913 key.part.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
1914 break;
1915 case PIPE_SHADER_FRAGMENT:
1916 key.part.ps.prolog.bc_optimize_for_persp =
1917 sel->info.uses_persp_center &&
1918 sel->info.uses_persp_centroid;
1919 key.part.ps.prolog.bc_optimize_for_linear =
1920 sel->info.uses_linear_center &&
1921 sel->info.uses_linear_centroid;
1922 key.part.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
1923 for (i = 0; i < 8; i++)
1924 if (sel->info.colors_written & (1 << i))
1925 key.part.ps.epilog.spi_shader_col_format |=
1926 V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
1927 break;
1928 }
1929
1930 if (si_shader_select_with_key(sscreen, &state,
1931 &sel->compiler_ctx_state, &key,
1932 thread_index))
1933 fprintf(stderr, "radeonsi: can't create a monolithic shader\n");
1934 }
1935
1936 /* The GS copy shader is always pre-compiled. */
1937 if (sel->type == PIPE_SHADER_GEOMETRY) {
1938 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, tm, sel, debug);
1939 if (!sel->gs_copy_shader) {
1940 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
1941 return;
1942 }
1943
1944 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
1945 }
1946 }
1947
1948 /* Return descriptor slot usage masks from the given shader info. */
1949 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
1950 uint32_t *const_and_shader_buffers,
1951 uint64_t *samplers_and_images)
1952 {
1953 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
1954
1955 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
1956 num_constbufs = util_last_bit(info->const_buffers_declared);
1957 /* two 8-byte images share one 16-byte slot */
1958 num_images = align(util_last_bit(info->images_declared), 2);
1959 num_samplers = util_last_bit(info->samplers_declared);
1960
1961 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
1962 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
1963 *const_and_shader_buffers =
1964 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
1965
1966 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
1967 start = si_get_image_slot(num_images - 1) / 2;
1968 *samplers_and_images =
1969 u_bit_consecutive64(start, num_images / 2 + num_samplers);
1970 }
1971
1972 static void *si_create_shader_selector(struct pipe_context *ctx,
1973 const struct pipe_shader_state *state)
1974 {
1975 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
1976 struct si_context *sctx = (struct si_context*)ctx;
1977 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
1978 int i;
1979
1980 if (!sel)
1981 return NULL;
1982
1983 pipe_reference_init(&sel->reference, 1);
1984 sel->screen = sscreen;
1985 sel->compiler_ctx_state.debug = sctx->debug;
1986 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
1987
1988 sel->so = state->stream_output;
1989
1990 if (state->type == PIPE_SHADER_IR_TGSI) {
1991 sel->tokens = tgsi_dup_tokens(state->tokens);
1992 if (!sel->tokens) {
1993 FREE(sel);
1994 return NULL;
1995 }
1996
1997 tgsi_scan_shader(state->tokens, &sel->info);
1998 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
1999 } else {
2000 assert(state->type == PIPE_SHADER_IR_NIR);
2001
2002 sel->nir = state->ir.nir;
2003
2004 si_nir_scan_shader(sel->nir, &sel->info);
2005
2006 si_lower_nir(sel);
2007 }
2008
2009 sel->type = sel->info.processor;
2010 p_atomic_inc(&sscreen->num_shaders_created);
2011 si_get_active_slot_masks(&sel->info,
2012 &sel->active_const_and_shader_buffers,
2013 &sel->active_samplers_and_images);
2014
2015 /* Record which streamout buffers are enabled. */
2016 for (i = 0; i < sel->so.num_outputs; i++) {
2017 sel->enabled_streamout_buffer_mask |=
2018 (1 << sel->so.output[i].output_buffer) <<
2019 (sel->so.output[i].stream * 4);
2020 }
2021
2022 /* The prolog is a no-op if there are no inputs. */
2023 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2024 sel->info.num_inputs &&
2025 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2026
2027 sel->force_correct_derivs_after_kill =
2028 sel->type == PIPE_SHADER_FRAGMENT &&
2029 sel->info.uses_derivatives &&
2030 sel->info.uses_kill &&
2031 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2032
2033 /* Set which opcode uses which (i,j) pair. */
2034 if (sel->info.uses_persp_opcode_interp_centroid)
2035 sel->info.uses_persp_centroid = true;
2036
2037 if (sel->info.uses_linear_opcode_interp_centroid)
2038 sel->info.uses_linear_centroid = true;
2039
2040 if (sel->info.uses_persp_opcode_interp_offset ||
2041 sel->info.uses_persp_opcode_interp_sample)
2042 sel->info.uses_persp_center = true;
2043
2044 if (sel->info.uses_linear_opcode_interp_offset ||
2045 sel->info.uses_linear_opcode_interp_sample)
2046 sel->info.uses_linear_center = true;
2047
2048 switch (sel->type) {
2049 case PIPE_SHADER_GEOMETRY:
2050 sel->gs_output_prim =
2051 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2052 sel->gs_max_out_vertices =
2053 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2054 sel->gs_num_invocations =
2055 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2056 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2057 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2058 sel->gs_max_out_vertices;
2059
2060 sel->max_gs_stream = 0;
2061 for (i = 0; i < sel->so.num_outputs; i++)
2062 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2063 sel->so.output[i].stream);
2064
2065 sel->gs_input_verts_per_prim =
2066 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2067 break;
2068
2069 case PIPE_SHADER_TESS_CTRL:
2070 /* Always reserve space for these. */
2071 sel->patch_outputs_written |=
2072 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2073 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2074 /* fall through */
2075 case PIPE_SHADER_VERTEX:
2076 case PIPE_SHADER_TESS_EVAL:
2077 for (i = 0; i < sel->info.num_outputs; i++) {
2078 unsigned name = sel->info.output_semantic_name[i];
2079 unsigned index = sel->info.output_semantic_index[i];
2080
2081 switch (name) {
2082 case TGSI_SEMANTIC_TESSINNER:
2083 case TGSI_SEMANTIC_TESSOUTER:
2084 case TGSI_SEMANTIC_PATCH:
2085 sel->patch_outputs_written |=
2086 1ull << si_shader_io_get_unique_index_patch(name, index);
2087 break;
2088
2089 case TGSI_SEMANTIC_GENERIC:
2090 /* don't process indices the function can't handle */
2091 if (index >= SI_MAX_IO_GENERIC)
2092 break;
2093 /* fall through */
2094 default:
2095 sel->outputs_written |=
2096 1ull << si_shader_io_get_unique_index(name, index);
2097 break;
2098 case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */
2099 case TGSI_SEMANTIC_EDGEFLAG:
2100 break;
2101 }
2102 }
2103 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2104
2105 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2106 * conflicts, i.e. each vertex will start at a different bank.
2107 */
2108 if (sctx->b.chip_class >= GFX9)
2109 sel->esgs_itemsize += 4;
2110 break;
2111
2112 case PIPE_SHADER_FRAGMENT:
2113 for (i = 0; i < sel->info.num_inputs; i++) {
2114 unsigned name = sel->info.input_semantic_name[i];
2115 unsigned index = sel->info.input_semantic_index[i];
2116
2117 switch (name) {
2118 case TGSI_SEMANTIC_GENERIC:
2119 /* don't process indices the function can't handle */
2120 if (index >= SI_MAX_IO_GENERIC)
2121 break;
2122 /* fall through */
2123 default:
2124 sel->inputs_read |=
2125 1ull << si_shader_io_get_unique_index(name, index);
2126 break;
2127 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2128 break;
2129 }
2130 }
2131
2132 for (i = 0; i < 8; i++)
2133 if (sel->info.colors_written & (1 << i))
2134 sel->colors_written_4bit |= 0xf << (4 * i);
2135
2136 for (i = 0; i < sel->info.num_inputs; i++) {
2137 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2138 int index = sel->info.input_semantic_index[i];
2139 sel->color_attr_index[index] = i;
2140 }
2141 }
2142 break;
2143 }
2144
2145 /* PA_CL_VS_OUT_CNTL */
2146 bool misc_vec_ena =
2147 sel->info.writes_psize || sel->info.writes_edgeflag ||
2148 sel->info.writes_layer || sel->info.writes_viewport_index;
2149 sel->pa_cl_vs_out_cntl =
2150 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2151 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2152 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2153 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2154 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2155 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2156 sel->clipdist_mask = sel->info.writes_clipvertex ?
2157 SIX_BITS : sel->info.clipdist_writemask;
2158 sel->culldist_mask = sel->info.culldist_writemask <<
2159 sel->info.num_written_clipdistance;
2160
2161 /* DB_SHADER_CONTROL */
2162 sel->db_shader_control =
2163 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2164 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2165 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2166 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2167
2168 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2169 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2170 sel->db_shader_control |=
2171 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2172 break;
2173 case TGSI_FS_DEPTH_LAYOUT_LESS:
2174 sel->db_shader_control |=
2175 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2176 break;
2177 }
2178
2179 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2180 *
2181 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2182 * --|-----------|------------|------------|--------------------|-------------------|-------------
2183 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2184 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2185 * 2 | false | true | n/a | LateZ | 1 | 0
2186 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2187 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2188 *
2189 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2190 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2191 *
2192 * Don't use ReZ without profiling !!!
2193 *
2194 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2195 * shaders.
2196 */
2197 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2198 /* Cases 3, 4. */
2199 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2200 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2201 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2202 } else if (sel->info.writes_memory) {
2203 /* Case 2. */
2204 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2205 S_02880C_EXEC_ON_HIER_FAIL(1);
2206 } else {
2207 /* Case 1. */
2208 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2209 }
2210
2211 (void) mtx_init(&sel->mutex, mtx_plain);
2212 util_queue_fence_init(&sel->ready);
2213
2214 struct util_async_debug_callback async_debug;
2215 bool wait =
2216 (sctx->debug.debug_message && !sctx->debug.async) ||
2217 sctx->is_debug ||
2218 si_can_dump_shader(sscreen, sel->info.processor);
2219
2220 if (wait) {
2221 u_async_debug_init(&async_debug);
2222 sel->compiler_ctx_state.debug = async_debug.base;
2223 }
2224
2225 util_queue_add_job(&sscreen->shader_compiler_queue, sel,
2226 &sel->ready, si_init_shader_selector_async,
2227 NULL);
2228
2229 if (wait) {
2230 util_queue_fence_wait(&sel->ready);
2231 u_async_debug_drain(&async_debug, &sctx->debug);
2232 u_async_debug_cleanup(&async_debug);
2233 }
2234
2235 return sel;
2236 }
2237
2238 static void si_update_streamout_state(struct si_context *sctx)
2239 {
2240 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2241
2242 if (!shader_with_so)
2243 return;
2244
2245 sctx->streamout.enabled_stream_buffers_mask =
2246 shader_with_so->enabled_streamout_buffer_mask;
2247 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2248 }
2249
2250 static void si_update_clip_regs(struct si_context *sctx,
2251 struct si_shader_selector *old_hw_vs,
2252 struct si_shader *old_hw_vs_variant,
2253 struct si_shader_selector *next_hw_vs,
2254 struct si_shader *next_hw_vs_variant)
2255 {
2256 if (next_hw_vs &&
2257 (!old_hw_vs ||
2258 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2259 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2260 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2261 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2262 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2263 !old_hw_vs_variant ||
2264 !next_hw_vs_variant ||
2265 old_hw_vs_variant->key.opt.clip_disable !=
2266 next_hw_vs_variant->key.opt.clip_disable))
2267 si_mark_atom_dirty(sctx, &sctx->clip_regs);
2268 }
2269
2270 static void si_update_common_shader_state(struct si_context *sctx)
2271 {
2272 sctx->uses_bindless_samplers =
2273 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2274 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2275 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2276 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2277 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2278 sctx->uses_bindless_images =
2279 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2280 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2281 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2282 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2283 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2284 sctx->do_update_shaders = true;
2285 }
2286
2287 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2288 {
2289 struct si_context *sctx = (struct si_context *)ctx;
2290 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2291 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2292 struct si_shader_selector *sel = state;
2293
2294 if (sctx->vs_shader.cso == sel)
2295 return;
2296
2297 sctx->vs_shader.cso = sel;
2298 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2299 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2300
2301 si_update_common_shader_state(sctx);
2302 si_update_vs_viewport_state(sctx);
2303 si_set_active_descriptors_for_shader(sctx, sel);
2304 si_update_streamout_state(sctx);
2305 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2306 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2307 }
2308
2309 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2310 {
2311 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2312 (sctx->tes_shader.cso &&
2313 sctx->tes_shader.cso->info.uses_primid) ||
2314 (sctx->tcs_shader.cso &&
2315 sctx->tcs_shader.cso->info.uses_primid) ||
2316 (sctx->gs_shader.cso &&
2317 sctx->gs_shader.cso->info.uses_primid) ||
2318 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2319 sctx->ps_shader.cso->info.uses_primid);
2320 }
2321
2322 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2323 {
2324 struct si_context *sctx = (struct si_context *)ctx;
2325 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2326 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2327 struct si_shader_selector *sel = state;
2328 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2329
2330 if (sctx->gs_shader.cso == sel)
2331 return;
2332
2333 sctx->gs_shader.cso = sel;
2334 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2335 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2336
2337 si_update_common_shader_state(sctx);
2338 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2339
2340 if (enable_changed) {
2341 si_shader_change_notify(sctx);
2342 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2343 si_update_tess_uses_prim_id(sctx);
2344 }
2345 si_update_vs_viewport_state(sctx);
2346 si_set_active_descriptors_for_shader(sctx, sel);
2347 si_update_streamout_state(sctx);
2348 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2349 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2350 }
2351
2352 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2353 {
2354 struct si_context *sctx = (struct si_context *)ctx;
2355 struct si_shader_selector *sel = state;
2356 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2357
2358 if (sctx->tcs_shader.cso == sel)
2359 return;
2360
2361 sctx->tcs_shader.cso = sel;
2362 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
2363 si_update_tess_uses_prim_id(sctx);
2364
2365 si_update_common_shader_state(sctx);
2366
2367 if (enable_changed)
2368 sctx->last_tcs = NULL; /* invalidate derived tess state */
2369
2370 si_set_active_descriptors_for_shader(sctx, sel);
2371 }
2372
2373 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
2374 {
2375 struct si_context *sctx = (struct si_context *)ctx;
2376 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2377 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2378 struct si_shader_selector *sel = state;
2379 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
2380
2381 if (sctx->tes_shader.cso == sel)
2382 return;
2383
2384 sctx->tes_shader.cso = sel;
2385 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
2386 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
2387 si_update_tess_uses_prim_id(sctx);
2388
2389 si_update_common_shader_state(sctx);
2390 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2391
2392 if (enable_changed) {
2393 si_shader_change_notify(sctx);
2394 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
2395 }
2396 si_update_vs_viewport_state(sctx);
2397 si_set_active_descriptors_for_shader(sctx, sel);
2398 si_update_streamout_state(sctx);
2399 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2400 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2401 }
2402
2403 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2404 {
2405 struct si_context *sctx = (struct si_context *)ctx;
2406 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
2407 struct si_shader_selector *sel = state;
2408
2409 /* skip if supplied shader is one already in use */
2410 if (old_sel == sel)
2411 return;
2412
2413 sctx->ps_shader.cso = sel;
2414 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
2415
2416 si_update_common_shader_state(sctx);
2417 if (sel) {
2418 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2419 si_update_tess_uses_prim_id(sctx);
2420
2421 if (!old_sel ||
2422 old_sel->info.colors_written != sel->info.colors_written)
2423 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2424
2425 if (sctx->screen->has_out_of_order_rast &&
2426 (!old_sel ||
2427 old_sel->info.writes_memory != sel->info.writes_memory ||
2428 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
2429 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
2430 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2431 }
2432 si_set_active_descriptors_for_shader(sctx, sel);
2433 }
2434
2435 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
2436 {
2437 if (shader->is_optimized) {
2438 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
2439 &shader->ready);
2440 }
2441
2442 util_queue_fence_destroy(&shader->ready);
2443
2444 if (shader->pm4) {
2445 switch (shader->selector->type) {
2446 case PIPE_SHADER_VERTEX:
2447 if (shader->key.as_ls) {
2448 assert(sctx->b.chip_class <= VI);
2449 si_pm4_delete_state(sctx, ls, shader->pm4);
2450 } else if (shader->key.as_es) {
2451 assert(sctx->b.chip_class <= VI);
2452 si_pm4_delete_state(sctx, es, shader->pm4);
2453 } else {
2454 si_pm4_delete_state(sctx, vs, shader->pm4);
2455 }
2456 break;
2457 case PIPE_SHADER_TESS_CTRL:
2458 si_pm4_delete_state(sctx, hs, shader->pm4);
2459 break;
2460 case PIPE_SHADER_TESS_EVAL:
2461 if (shader->key.as_es) {
2462 assert(sctx->b.chip_class <= VI);
2463 si_pm4_delete_state(sctx, es, shader->pm4);
2464 } else {
2465 si_pm4_delete_state(sctx, vs, shader->pm4);
2466 }
2467 break;
2468 case PIPE_SHADER_GEOMETRY:
2469 if (shader->is_gs_copy_shader)
2470 si_pm4_delete_state(sctx, vs, shader->pm4);
2471 else
2472 si_pm4_delete_state(sctx, gs, shader->pm4);
2473 break;
2474 case PIPE_SHADER_FRAGMENT:
2475 si_pm4_delete_state(sctx, ps, shader->pm4);
2476 break;
2477 }
2478 }
2479
2480 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
2481 si_shader_destroy(shader);
2482 free(shader);
2483 }
2484
2485 void si_destroy_shader_selector(struct si_context *sctx,
2486 struct si_shader_selector *sel)
2487 {
2488 struct si_shader *p = sel->first_variant, *c;
2489 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
2490 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
2491 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
2492 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
2493 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
2494 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
2495 };
2496
2497 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
2498
2499 if (current_shader[sel->type]->cso == sel) {
2500 current_shader[sel->type]->cso = NULL;
2501 current_shader[sel->type]->current = NULL;
2502 }
2503
2504 while (p) {
2505 c = p->next_variant;
2506 si_delete_shader(sctx, p);
2507 p = c;
2508 }
2509
2510 if (sel->main_shader_part)
2511 si_delete_shader(sctx, sel->main_shader_part);
2512 if (sel->main_shader_part_ls)
2513 si_delete_shader(sctx, sel->main_shader_part_ls);
2514 if (sel->main_shader_part_es)
2515 si_delete_shader(sctx, sel->main_shader_part_es);
2516 if (sel->gs_copy_shader)
2517 si_delete_shader(sctx, sel->gs_copy_shader);
2518
2519 util_queue_fence_destroy(&sel->ready);
2520 mtx_destroy(&sel->mutex);
2521 free(sel->tokens);
2522 ralloc_free(sel->nir);
2523 free(sel);
2524 }
2525
2526 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
2527 {
2528 struct si_context *sctx = (struct si_context *)ctx;
2529 struct si_shader_selector *sel = (struct si_shader_selector *)state;
2530
2531 si_shader_selector_reference(sctx, &sel, NULL);
2532 }
2533
2534 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
2535 struct si_shader *vs, unsigned name,
2536 unsigned index, unsigned interpolate)
2537 {
2538 struct tgsi_shader_info *vsinfo = &vs->selector->info;
2539 unsigned j, offset, ps_input_cntl = 0;
2540
2541 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
2542 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
2543 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2544
2545 if (name == TGSI_SEMANTIC_PCOORD ||
2546 (name == TGSI_SEMANTIC_TEXCOORD &&
2547 sctx->sprite_coord_enable & (1 << index))) {
2548 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
2549 }
2550
2551 for (j = 0; j < vsinfo->num_outputs; j++) {
2552 if (name == vsinfo->output_semantic_name[j] &&
2553 index == vsinfo->output_semantic_index[j]) {
2554 offset = vs->info.vs_output_param_offset[j];
2555
2556 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2557 /* The input is loaded from parameter memory. */
2558 ps_input_cntl |= S_028644_OFFSET(offset);
2559 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2560 if (offset == AC_EXP_PARAM_UNDEFINED) {
2561 /* This can happen with depth-only rendering. */
2562 offset = 0;
2563 } else {
2564 /* The input is a DEFAULT_VAL constant. */
2565 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2566 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2567 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2568 }
2569
2570 ps_input_cntl = S_028644_OFFSET(0x20) |
2571 S_028644_DEFAULT_VAL(offset);
2572 }
2573 break;
2574 }
2575 }
2576
2577 if (name == TGSI_SEMANTIC_PRIMID)
2578 /* PrimID is written after the last output. */
2579 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
2580 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2581 /* No corresponding output found, load defaults into input.
2582 * Don't set any other bits.
2583 * (FLAT_SHADE=1 completely changes behavior) */
2584 ps_input_cntl = S_028644_OFFSET(0x20);
2585 /* D3D 9 behaviour. GL is undefined */
2586 if (name == TGSI_SEMANTIC_COLOR && index == 0)
2587 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
2588 }
2589 return ps_input_cntl;
2590 }
2591
2592 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
2593 {
2594 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2595 struct si_shader *ps = sctx->ps_shader.current;
2596 struct si_shader *vs = si_get_vs_state(sctx);
2597 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
2598 unsigned i, num_interp, num_written = 0, bcol_interp[2];
2599
2600 if (!ps || !ps->selector->info.num_inputs)
2601 return;
2602
2603 num_interp = si_get_ps_num_interp(ps);
2604 assert(num_interp > 0);
2605 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
2606
2607 for (i = 0; i < psinfo->num_inputs; i++) {
2608 unsigned name = psinfo->input_semantic_name[i];
2609 unsigned index = psinfo->input_semantic_index[i];
2610 unsigned interpolate = psinfo->input_interpolate[i];
2611
2612 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
2613 interpolate));
2614 num_written++;
2615
2616 if (name == TGSI_SEMANTIC_COLOR) {
2617 assert(index < ARRAY_SIZE(bcol_interp));
2618 bcol_interp[index] = interpolate;
2619 }
2620 }
2621
2622 if (ps->key.part.ps.prolog.color_two_side) {
2623 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
2624
2625 for (i = 0; i < 2; i++) {
2626 if (!(psinfo->colors_read & (0xf << (i * 4))))
2627 continue;
2628
2629 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
2630 i, bcol_interp[i]));
2631 num_written++;
2632 }
2633 }
2634 assert(num_interp == num_written);
2635 }
2636
2637 /**
2638 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2639 */
2640 static void si_init_config_add_vgt_flush(struct si_context *sctx)
2641 {
2642 if (sctx->init_config_has_vgt_flush)
2643 return;
2644
2645 /* Done by Vulkan before VGT_FLUSH. */
2646 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2647 si_pm4_cmd_add(sctx->init_config,
2648 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2649 si_pm4_cmd_end(sctx->init_config, false);
2650
2651 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2652 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2653 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2654 si_pm4_cmd_end(sctx->init_config, false);
2655 sctx->init_config_has_vgt_flush = true;
2656 }
2657
2658 /* Initialize state related to ESGS / GSVS ring buffers */
2659 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2660 {
2661 struct si_shader_selector *es =
2662 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2663 struct si_shader_selector *gs = sctx->gs_shader.cso;
2664 struct si_pm4_state *pm4;
2665
2666 /* Chip constants. */
2667 unsigned num_se = sctx->screen->info.max_se;
2668 unsigned wave_size = 64;
2669 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2670 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2671 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2672 */
2673 unsigned gs_vertex_reuse = (sctx->b.chip_class >= VI ? 32 : 16) * num_se;
2674 unsigned alignment = 256 * num_se;
2675 /* The maximum size is 63.999 MB per SE. */
2676 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2677
2678 /* Calculate the minimum size. */
2679 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
2680 wave_size, alignment);
2681
2682 /* These are recommended sizes, not minimum sizes. */
2683 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2684 es->esgs_itemsize * gs->gs_input_verts_per_prim;
2685 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2686 gs->max_gsvs_emit_size;
2687
2688 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2689 esgs_ring_size = align(esgs_ring_size, alignment);
2690 gsvs_ring_size = align(gsvs_ring_size, alignment);
2691
2692 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2693 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2694
2695 /* Some rings don't have to be allocated if shaders don't use them.
2696 * (e.g. no varyings between ES and GS or GS and VS)
2697 *
2698 * GFX9 doesn't have the ESGS ring.
2699 */
2700 bool update_esgs = sctx->b.chip_class <= VI &&
2701 esgs_ring_size &&
2702 (!sctx->esgs_ring ||
2703 sctx->esgs_ring->width0 < esgs_ring_size);
2704 bool update_gsvs = gsvs_ring_size &&
2705 (!sctx->gsvs_ring ||
2706 sctx->gsvs_ring->width0 < gsvs_ring_size);
2707
2708 if (!update_esgs && !update_gsvs)
2709 return true;
2710
2711 if (update_esgs) {
2712 pipe_resource_reference(&sctx->esgs_ring, NULL);
2713 sctx->esgs_ring =
2714 si_aligned_buffer_create(sctx->b.b.screen,
2715 R600_RESOURCE_FLAG_UNMAPPABLE,
2716 PIPE_USAGE_DEFAULT,
2717 esgs_ring_size, alignment);
2718 if (!sctx->esgs_ring)
2719 return false;
2720 }
2721
2722 if (update_gsvs) {
2723 pipe_resource_reference(&sctx->gsvs_ring, NULL);
2724 sctx->gsvs_ring =
2725 si_aligned_buffer_create(sctx->b.b.screen,
2726 R600_RESOURCE_FLAG_UNMAPPABLE,
2727 PIPE_USAGE_DEFAULT,
2728 gsvs_ring_size, alignment);
2729 if (!sctx->gsvs_ring)
2730 return false;
2731 }
2732
2733 /* Create the "init_config_gs_rings" state. */
2734 pm4 = CALLOC_STRUCT(si_pm4_state);
2735 if (!pm4)
2736 return false;
2737
2738 if (sctx->b.chip_class >= CIK) {
2739 if (sctx->esgs_ring) {
2740 assert(sctx->b.chip_class <= VI);
2741 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2742 sctx->esgs_ring->width0 / 256);
2743 }
2744 if (sctx->gsvs_ring)
2745 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2746 sctx->gsvs_ring->width0 / 256);
2747 } else {
2748 if (sctx->esgs_ring)
2749 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2750 sctx->esgs_ring->width0 / 256);
2751 if (sctx->gsvs_ring)
2752 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2753 sctx->gsvs_ring->width0 / 256);
2754 }
2755
2756 /* Set the state. */
2757 if (sctx->init_config_gs_rings)
2758 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
2759 sctx->init_config_gs_rings = pm4;
2760
2761 if (!sctx->init_config_has_vgt_flush) {
2762 si_init_config_add_vgt_flush(sctx);
2763 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2764 }
2765
2766 /* Flush the context to re-emit both init_config states. */
2767 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2768 si_context_gfx_flush(sctx, PIPE_FLUSH_ASYNC, NULL);
2769
2770 /* Set ring bindings. */
2771 if (sctx->esgs_ring) {
2772 assert(sctx->b.chip_class <= VI);
2773 si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
2774 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2775 true, true, 4, 64, 0);
2776 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
2777 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2778 false, false, 0, 0, 0);
2779 }
2780 if (sctx->gsvs_ring) {
2781 si_set_ring_buffer(&sctx->b.b, SI_RING_GSVS,
2782 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
2783 false, false, 0, 0, 0);
2784 }
2785
2786 return true;
2787 }
2788
2789 static void si_shader_lock(struct si_shader *shader)
2790 {
2791 mtx_lock(&shader->selector->mutex);
2792 if (shader->previous_stage_sel) {
2793 assert(shader->previous_stage_sel != shader->selector);
2794 mtx_lock(&shader->previous_stage_sel->mutex);
2795 }
2796 }
2797
2798 static void si_shader_unlock(struct si_shader *shader)
2799 {
2800 if (shader->previous_stage_sel)
2801 mtx_unlock(&shader->previous_stage_sel->mutex);
2802 mtx_unlock(&shader->selector->mutex);
2803 }
2804
2805 /**
2806 * @returns 1 if \p sel has been updated to use a new scratch buffer
2807 * 0 if not
2808 * < 0 if there was a failure
2809 */
2810 static int si_update_scratch_buffer(struct si_context *sctx,
2811 struct si_shader *shader)
2812 {
2813 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
2814 int r;
2815
2816 if (!shader)
2817 return 0;
2818
2819 /* This shader doesn't need a scratch buffer */
2820 if (shader->config.scratch_bytes_per_wave == 0)
2821 return 0;
2822
2823 /* Prevent race conditions when updating:
2824 * - si_shader::scratch_bo
2825 * - si_shader::binary::code
2826 * - si_shader::previous_stage::binary::code.
2827 */
2828 si_shader_lock(shader);
2829
2830 /* This shader is already configured to use the current
2831 * scratch buffer. */
2832 if (shader->scratch_bo == sctx->scratch_buffer) {
2833 si_shader_unlock(shader);
2834 return 0;
2835 }
2836
2837 assert(sctx->scratch_buffer);
2838
2839 if (shader->previous_stage)
2840 si_shader_apply_scratch_relocs(shader->previous_stage, scratch_va);
2841
2842 si_shader_apply_scratch_relocs(shader, scratch_va);
2843
2844 /* Replace the shader bo with a new bo that has the relocs applied. */
2845 r = si_shader_binary_upload(sctx->screen, shader);
2846 if (r) {
2847 si_shader_unlock(shader);
2848 return r;
2849 }
2850
2851 /* Update the shader state to use the new shader bo. */
2852 si_shader_init_pm4_state(sctx->screen, shader);
2853
2854 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
2855
2856 si_shader_unlock(shader);
2857 return 1;
2858 }
2859
2860 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
2861 {
2862 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
2863 }
2864
2865 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
2866 {
2867 return shader ? shader->config.scratch_bytes_per_wave : 0;
2868 }
2869
2870 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
2871 {
2872 if (!sctx->tes_shader.cso)
2873 return NULL; /* tessellation disabled */
2874
2875 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
2876 sctx->fixed_func_tcs_shader.current;
2877 }
2878
2879 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
2880 {
2881 unsigned bytes = 0;
2882
2883 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
2884 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
2885 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
2886 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
2887
2888 if (sctx->tes_shader.cso) {
2889 struct si_shader *tcs = si_get_tcs_current(sctx);
2890
2891 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
2892 }
2893 return bytes;
2894 }
2895
2896 static bool si_update_scratch_relocs(struct si_context *sctx)
2897 {
2898 struct si_shader *tcs = si_get_tcs_current(sctx);
2899 int r;
2900
2901 /* Update the shaders, so that they are using the latest scratch.
2902 * The scratch buffer may have been changed since these shaders were
2903 * last used, so we still need to try to update them, even if they
2904 * require scratch buffers smaller than the current size.
2905 */
2906 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
2907 if (r < 0)
2908 return false;
2909 if (r == 1)
2910 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2911
2912 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
2913 if (r < 0)
2914 return false;
2915 if (r == 1)
2916 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2917
2918 r = si_update_scratch_buffer(sctx, tcs);
2919 if (r < 0)
2920 return false;
2921 if (r == 1)
2922 si_pm4_bind_state(sctx, hs, tcs->pm4);
2923
2924 /* VS can be bound as LS, ES, or VS. */
2925 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
2926 if (r < 0)
2927 return false;
2928 if (r == 1) {
2929 if (sctx->tes_shader.current)
2930 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2931 else if (sctx->gs_shader.current)
2932 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2933 else
2934 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2935 }
2936
2937 /* TES can be bound as ES or VS. */
2938 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
2939 if (r < 0)
2940 return false;
2941 if (r == 1) {
2942 if (sctx->gs_shader.current)
2943 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2944 else
2945 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2946 }
2947
2948 return true;
2949 }
2950
2951 static bool si_update_spi_tmpring_size(struct si_context *sctx)
2952 {
2953 unsigned current_scratch_buffer_size =
2954 si_get_current_scratch_buffer_size(sctx);
2955 unsigned scratch_bytes_per_wave =
2956 si_get_max_scratch_bytes_per_wave(sctx);
2957 unsigned scratch_needed_size = scratch_bytes_per_wave *
2958 sctx->scratch_waves;
2959 unsigned spi_tmpring_size;
2960
2961 if (scratch_needed_size > 0) {
2962 if (scratch_needed_size > current_scratch_buffer_size) {
2963 /* Create a bigger scratch buffer */
2964 r600_resource_reference(&sctx->scratch_buffer, NULL);
2965
2966 sctx->scratch_buffer = (struct r600_resource*)
2967 si_aligned_buffer_create(&sctx->screen->b,
2968 R600_RESOURCE_FLAG_UNMAPPABLE,
2969 PIPE_USAGE_DEFAULT,
2970 scratch_needed_size, 256);
2971 if (!sctx->scratch_buffer)
2972 return false;
2973
2974 si_mark_atom_dirty(sctx, &sctx->scratch_state);
2975 si_context_add_resource_size(&sctx->b.b,
2976 &sctx->scratch_buffer->b.b);
2977 }
2978
2979 if (!si_update_scratch_relocs(sctx))
2980 return false;
2981 }
2982
2983 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
2984 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
2985 "scratch size should already be aligned correctly.");
2986
2987 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
2988 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
2989 if (spi_tmpring_size != sctx->spi_tmpring_size) {
2990 sctx->spi_tmpring_size = spi_tmpring_size;
2991 si_mark_atom_dirty(sctx, &sctx->scratch_state);
2992 }
2993 return true;
2994 }
2995
2996 static void si_init_tess_factor_ring(struct si_context *sctx)
2997 {
2998 bool double_offchip_buffers = sctx->b.chip_class >= CIK &&
2999 sctx->b.family != CHIP_CARRIZO &&
3000 sctx->b.family != CHIP_STONEY;
3001 /* This must be one less than the maximum number due to a hw limitation.
3002 * Various hardware bugs in SI, CIK, and GFX9 need this.
3003 */
3004 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
3005 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
3006 sctx->screen->info.max_se;
3007 unsigned offchip_granularity;
3008
3009 switch (sctx->screen->tess_offchip_block_dw_size) {
3010 default:
3011 assert(0);
3012 /* fall through */
3013 case 8192:
3014 offchip_granularity = V_03093C_X_8K_DWORDS;
3015 break;
3016 case 4096:
3017 offchip_granularity = V_03093C_X_4K_DWORDS;
3018 break;
3019 }
3020
3021 assert(!sctx->tf_ring);
3022 /* Use 64K alignment for both rings, so that we can pass the address
3023 * to shaders as one SGPR containing bits [16:47].
3024 */
3025 sctx->tf_ring = si_aligned_buffer_create(sctx->b.b.screen,
3026 R600_RESOURCE_FLAG_UNMAPPABLE,
3027 PIPE_USAGE_DEFAULT,
3028 32768 * sctx->screen->info.max_se,
3029 64 * 1024);
3030 if (!sctx->tf_ring)
3031 return;
3032
3033 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
3034
3035 sctx->tess_offchip_ring =
3036 si_aligned_buffer_create(sctx->b.b.screen,
3037 R600_RESOURCE_FLAG_UNMAPPABLE,
3038 PIPE_USAGE_DEFAULT,
3039 max_offchip_buffers *
3040 sctx->screen->tess_offchip_block_dw_size * 4,
3041 64 * 1024);
3042 if (!sctx->tess_offchip_ring)
3043 return;
3044
3045 si_init_config_add_vgt_flush(sctx);
3046
3047 uint64_t offchip_va = r600_resource(sctx->tess_offchip_ring)->gpu_address;
3048 uint64_t factor_va = r600_resource(sctx->tf_ring)->gpu_address;
3049 assert((offchip_va & 0xffff) == 0);
3050 assert((factor_va & 0xffff) == 0);
3051
3052 si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_offchip_ring),
3053 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3054 si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tf_ring),
3055 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3056
3057 /* Append these registers to the init config state. */
3058 if (sctx->b.chip_class >= CIK) {
3059 if (sctx->b.chip_class >= VI)
3060 --max_offchip_buffers;
3061
3062 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3063 S_030938_SIZE(sctx->tf_ring->width0 / 4));
3064 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3065 factor_va >> 8);
3066 if (sctx->b.chip_class >= GFX9)
3067 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3068 factor_va >> 40);
3069 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3070 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
3071 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity));
3072 } else {
3073 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
3074 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3075 S_008988_SIZE(sctx->tf_ring->width0 / 4));
3076 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3077 factor_va >> 8);
3078 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3079 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers));
3080 }
3081
3082 if (sctx->b.chip_class >= GFX9) {
3083 si_pm4_set_reg(sctx->init_config,
3084 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
3085 GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K * 4,
3086 offchip_va >> 16);
3087 si_pm4_set_reg(sctx->init_config,
3088 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
3089 GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K * 4,
3090 factor_va >> 16);
3091 } else {
3092 si_pm4_set_reg(sctx->init_config,
3093 R_00B430_SPI_SHADER_USER_DATA_HS_0 +
3094 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K * 4,
3095 offchip_va >> 16);
3096 si_pm4_set_reg(sctx->init_config,
3097 R_00B430_SPI_SHADER_USER_DATA_HS_0 +
3098 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K * 4,
3099 factor_va >> 16);
3100 }
3101
3102 /* Flush the context to re-emit the init_config state.
3103 * This is done only once in a lifetime of a context.
3104 */
3105 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3106 sctx->b.initial_gfx_cs_size = 0; /* force flush */
3107 si_context_gfx_flush(sctx, PIPE_FLUSH_ASYNC, NULL);
3108 }
3109
3110 /**
3111 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
3112 * VS passes its outputs to TES directly, so the fixed-function shader only
3113 * has to write TESSOUTER and TESSINNER.
3114 */
3115 static void si_generate_fixed_func_tcs(struct si_context *sctx)
3116 {
3117 struct ureg_src outer, inner;
3118 struct ureg_dst tessouter, tessinner;
3119 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
3120
3121 if (!ureg)
3122 return; /* if we get here, we're screwed */
3123
3124 assert(!sctx->fixed_func_tcs_shader.cso);
3125
3126 outer = ureg_DECL_system_value(ureg,
3127 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
3128 inner = ureg_DECL_system_value(ureg,
3129 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
3130
3131 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
3132 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
3133
3134 ureg_MOV(ureg, tessouter, outer);
3135 ureg_MOV(ureg, tessinner, inner);
3136 ureg_END(ureg);
3137
3138 sctx->fixed_func_tcs_shader.cso =
3139 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
3140 }
3141
3142 static void si_update_vgt_shader_config(struct si_context *sctx)
3143 {
3144 /* Calculate the index of the config.
3145 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3146 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
3147 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
3148
3149 if (!*pm4) {
3150 uint32_t stages = 0;
3151
3152 *pm4 = CALLOC_STRUCT(si_pm4_state);
3153
3154 if (sctx->tes_shader.cso) {
3155 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3156 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3157
3158 if (sctx->gs_shader.cso)
3159 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3160 S_028B54_GS_EN(1) |
3161 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3162 else
3163 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3164 } else if (sctx->gs_shader.cso) {
3165 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3166 S_028B54_GS_EN(1) |
3167 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3168 }
3169
3170 if (sctx->b.chip_class >= GFX9)
3171 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3172
3173 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3174 }
3175 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3176 }
3177
3178 bool si_update_shaders(struct si_context *sctx)
3179 {
3180 struct pipe_context *ctx = (struct pipe_context*)sctx;
3181 struct si_compiler_ctx_state compiler_state;
3182 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3183 struct si_shader *old_vs = si_get_vs_state(sctx);
3184 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3185 struct si_shader *old_ps = sctx->ps_shader.current;
3186 unsigned old_spi_shader_col_format =
3187 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3188 int r;
3189
3190 compiler_state.tm = sctx->tm;
3191 compiler_state.debug = sctx->debug;
3192 compiler_state.is_debug_context = sctx->is_debug;
3193
3194 /* Update stages before GS. */
3195 if (sctx->tes_shader.cso) {
3196 if (!sctx->tf_ring) {
3197 si_init_tess_factor_ring(sctx);
3198 if (!sctx->tf_ring)
3199 return false;
3200 }
3201
3202 /* VS as LS */
3203 if (sctx->b.chip_class <= VI) {
3204 r = si_shader_select(ctx, &sctx->vs_shader,
3205 &compiler_state);
3206 if (r)
3207 return false;
3208 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3209 }
3210
3211 if (sctx->tcs_shader.cso) {
3212 r = si_shader_select(ctx, &sctx->tcs_shader,
3213 &compiler_state);
3214 if (r)
3215 return false;
3216 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3217 } else {
3218 if (!sctx->fixed_func_tcs_shader.cso) {
3219 si_generate_fixed_func_tcs(sctx);
3220 if (!sctx->fixed_func_tcs_shader.cso)
3221 return false;
3222 }
3223
3224 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3225 &compiler_state);
3226 if (r)
3227 return false;
3228 si_pm4_bind_state(sctx, hs,
3229 sctx->fixed_func_tcs_shader.current->pm4);
3230 }
3231
3232 if (sctx->gs_shader.cso) {
3233 /* TES as ES */
3234 if (sctx->b.chip_class <= VI) {
3235 r = si_shader_select(ctx, &sctx->tes_shader,
3236 &compiler_state);
3237 if (r)
3238 return false;
3239 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3240 }
3241 } else {
3242 /* TES as VS */
3243 r = si_shader_select(ctx, &sctx->tes_shader,
3244 &compiler_state);
3245 if (r)
3246 return false;
3247 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3248 }
3249 } else if (sctx->gs_shader.cso) {
3250 if (sctx->b.chip_class <= VI) {
3251 /* VS as ES */
3252 r = si_shader_select(ctx, &sctx->vs_shader,
3253 &compiler_state);
3254 if (r)
3255 return false;
3256 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3257
3258 si_pm4_bind_state(sctx, ls, NULL);
3259 si_pm4_bind_state(sctx, hs, NULL);
3260 }
3261 } else {
3262 /* VS as VS */
3263 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
3264 if (r)
3265 return false;
3266 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3267 si_pm4_bind_state(sctx, ls, NULL);
3268 si_pm4_bind_state(sctx, hs, NULL);
3269 }
3270
3271 /* Update GS. */
3272 if (sctx->gs_shader.cso) {
3273 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
3274 if (r)
3275 return false;
3276 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3277 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3278
3279 if (!si_update_gs_ring_buffers(sctx))
3280 return false;
3281 } else {
3282 si_pm4_bind_state(sctx, gs, NULL);
3283 if (sctx->b.chip_class <= VI)
3284 si_pm4_bind_state(sctx, es, NULL);
3285 }
3286
3287 si_update_vgt_shader_config(sctx);
3288
3289 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3290 si_mark_atom_dirty(sctx, &sctx->clip_regs);
3291
3292 if (sctx->ps_shader.cso) {
3293 unsigned db_shader_control;
3294
3295 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
3296 if (r)
3297 return false;
3298 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3299
3300 db_shader_control =
3301 sctx->ps_shader.cso->db_shader_control |
3302 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3303
3304 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3305 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3306 sctx->flatshade != rs->flatshade) {
3307 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3308 sctx->flatshade = rs->flatshade;
3309 si_mark_atom_dirty(sctx, &sctx->spi_map);
3310 }
3311
3312 if (sctx->screen->rbplus_allowed &&
3313 si_pm4_state_changed(sctx, ps) &&
3314 (!old_ps ||
3315 old_spi_shader_col_format !=
3316 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3317 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
3318
3319 if (sctx->ps_db_shader_control != db_shader_control) {
3320 sctx->ps_db_shader_control = db_shader_control;
3321 si_mark_atom_dirty(sctx, &sctx->db_render_state);
3322 if (sctx->screen->dpbb_allowed)
3323 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
3324 }
3325
3326 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3327 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3328 si_mark_atom_dirty(sctx, &sctx->msaa_config);
3329
3330 if (sctx->b.chip_class == SI)
3331 si_mark_atom_dirty(sctx, &sctx->db_render_state);
3332
3333 if (sctx->framebuffer.nr_samples <= 1)
3334 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
3335 }
3336 }
3337
3338 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3339 si_pm4_state_enabled_and_changed(sctx, hs) ||
3340 si_pm4_state_enabled_and_changed(sctx, es) ||
3341 si_pm4_state_enabled_and_changed(sctx, gs) ||
3342 si_pm4_state_enabled_and_changed(sctx, vs) ||
3343 si_pm4_state_enabled_and_changed(sctx, ps)) {
3344 if (!si_update_spi_tmpring_size(sctx))
3345 return false;
3346 }
3347
3348 if (sctx->b.chip_class >= CIK) {
3349 if (si_pm4_state_enabled_and_changed(sctx, ls))
3350 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3351 else if (!sctx->queued.named.ls)
3352 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3353
3354 if (si_pm4_state_enabled_and_changed(sctx, hs))
3355 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3356 else if (!sctx->queued.named.hs)
3357 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3358
3359 if (si_pm4_state_enabled_and_changed(sctx, es))
3360 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
3361 else if (!sctx->queued.named.es)
3362 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
3363
3364 if (si_pm4_state_enabled_and_changed(sctx, gs))
3365 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
3366 else if (!sctx->queued.named.gs)
3367 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
3368
3369 if (si_pm4_state_enabled_and_changed(sctx, vs))
3370 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
3371 else if (!sctx->queued.named.vs)
3372 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
3373
3374 if (si_pm4_state_enabled_and_changed(sctx, ps))
3375 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
3376 else if (!sctx->queued.named.ps)
3377 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
3378 }
3379
3380 sctx->do_update_shaders = false;
3381 return true;
3382 }
3383
3384 static void si_emit_scratch_state(struct si_context *sctx,
3385 struct r600_atom *atom)
3386 {
3387 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3388
3389 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3390 sctx->spi_tmpring_size);
3391
3392 if (sctx->scratch_buffer) {
3393 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
3394 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3395 RADEON_PRIO_SCRATCH_BUFFER);
3396 }
3397 }
3398
3399 void *si_get_blit_vs(struct si_context *sctx, enum blitter_attrib_type type,
3400 unsigned num_layers)
3401 {
3402 struct pipe_context *pipe = &sctx->b.b;
3403 unsigned vs_blit_property;
3404 void **vs;
3405
3406 switch (type) {
3407 case UTIL_BLITTER_ATTRIB_NONE:
3408 vs = num_layers > 1 ? &sctx->vs_blit_pos_layered :
3409 &sctx->vs_blit_pos;
3410 vs_blit_property = SI_VS_BLIT_SGPRS_POS;
3411 break;
3412 case UTIL_BLITTER_ATTRIB_COLOR:
3413 vs = num_layers > 1 ? &sctx->vs_blit_color_layered :
3414 &sctx->vs_blit_color;
3415 vs_blit_property = SI_VS_BLIT_SGPRS_POS_COLOR;
3416 break;
3417 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
3418 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
3419 assert(num_layers == 1);
3420 vs = &sctx->vs_blit_texcoord;
3421 vs_blit_property = SI_VS_BLIT_SGPRS_POS_TEXCOORD;
3422 break;
3423 default:
3424 assert(0);
3425 return NULL;
3426 }
3427 if (*vs)
3428 return *vs;
3429
3430 struct ureg_program *ureg = ureg_create(PIPE_SHADER_VERTEX);
3431 if (!ureg)
3432 return NULL;
3433
3434 /* Tell the shader to load VS inputs from SGPRs: */
3435 ureg_property(ureg, TGSI_PROPERTY_VS_BLIT_SGPRS, vs_blit_property);
3436 ureg_property(ureg, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION, true);
3437
3438 /* This is just a pass-through shader with 1-3 MOV instructions. */
3439 ureg_MOV(ureg,
3440 ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0),
3441 ureg_DECL_vs_input(ureg, 0));
3442
3443 if (type != UTIL_BLITTER_ATTRIB_NONE) {
3444 ureg_MOV(ureg,
3445 ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, 0),
3446 ureg_DECL_vs_input(ureg, 1));
3447 }
3448
3449 if (num_layers > 1) {
3450 struct ureg_src instance_id =
3451 ureg_DECL_system_value(ureg, TGSI_SEMANTIC_INSTANCEID, 0);
3452 struct ureg_dst layer =
3453 ureg_DECL_output(ureg, TGSI_SEMANTIC_LAYER, 0);
3454
3455 ureg_MOV(ureg, ureg_writemask(layer, TGSI_WRITEMASK_X),
3456 ureg_scalar(instance_id, TGSI_SWIZZLE_X));
3457 }
3458 ureg_END(ureg);
3459
3460 *vs = ureg_create_shader_and_destroy(ureg, pipe);
3461 return *vs;
3462 }
3463
3464 void si_init_shader_functions(struct si_context *sctx)
3465 {
3466 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
3467 si_init_atom(sctx, &sctx->scratch_state, &sctx->atoms.s.scratch_state,
3468 si_emit_scratch_state);
3469
3470 sctx->b.b.create_vs_state = si_create_shader_selector;
3471 sctx->b.b.create_tcs_state = si_create_shader_selector;
3472 sctx->b.b.create_tes_state = si_create_shader_selector;
3473 sctx->b.b.create_gs_state = si_create_shader_selector;
3474 sctx->b.b.create_fs_state = si_create_shader_selector;
3475
3476 sctx->b.b.bind_vs_state = si_bind_vs_shader;
3477 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
3478 sctx->b.b.bind_tes_state = si_bind_tes_shader;
3479 sctx->b.b.bind_gs_state = si_bind_gs_shader;
3480 sctx->b.b.bind_fs_state = si_bind_ps_shader;
3481
3482 sctx->b.b.delete_vs_state = si_delete_shader_selector;
3483 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
3484 sctx->b.b.delete_tes_state = si_delete_shader_selector;
3485 sctx->b.b.delete_gs_state = si_delete_shader_selector;
3486 sctx->b.b.delete_fs_state = si_delete_shader_selector;
3487 }