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gallium/radeon: inline the r600_rings structure
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "si_shader.h"
30 #include "sid.h"
31 #include "radeon/r600_cs.h"
32
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/u_memory.h"
36 #include "util/u_simple_shaders.h"
37
38 static void si_set_tesseval_regs(struct si_shader *shader,
39 struct si_pm4_state *pm4)
40 {
41 struct tgsi_shader_info *info = &shader->selector->info;
42 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
43 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
44 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
45 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
46 unsigned type, partitioning, topology;
47
48 switch (tes_prim_mode) {
49 case PIPE_PRIM_LINES:
50 type = V_028B6C_TESS_ISOLINE;
51 break;
52 case PIPE_PRIM_TRIANGLES:
53 type = V_028B6C_TESS_TRIANGLE;
54 break;
55 case PIPE_PRIM_QUADS:
56 type = V_028B6C_TESS_QUAD;
57 break;
58 default:
59 assert(0);
60 return;
61 }
62
63 switch (tes_spacing) {
64 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
65 partitioning = V_028B6C_PART_FRAC_ODD;
66 break;
67 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
68 partitioning = V_028B6C_PART_FRAC_EVEN;
69 break;
70 case PIPE_TESS_SPACING_EQUAL:
71 partitioning = V_028B6C_PART_INTEGER;
72 break;
73 default:
74 assert(0);
75 return;
76 }
77
78 if (tes_point_mode)
79 topology = V_028B6C_OUTPUT_POINT;
80 else if (tes_prim_mode == PIPE_PRIM_LINES)
81 topology = V_028B6C_OUTPUT_LINE;
82 else if (tes_vertex_order_cw)
83 /* for some reason, this must be the other way around */
84 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
85 else
86 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
87
88 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
89 S_028B6C_TYPE(type) |
90 S_028B6C_PARTITIONING(partitioning) |
91 S_028B6C_TOPOLOGY(topology));
92 }
93
94 static void si_shader_ls(struct si_shader *shader)
95 {
96 struct si_pm4_state *pm4;
97 unsigned num_sgprs, num_user_sgprs;
98 unsigned vgpr_comp_cnt;
99 uint64_t va;
100
101 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
102 if (pm4 == NULL)
103 return;
104
105 va = shader->bo->gpu_address;
106 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
107
108 /* We need at least 2 components for LS.
109 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
110 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 1;
111
112 num_user_sgprs = SI_LS_NUM_USER_SGPR;
113 num_sgprs = shader->num_sgprs;
114 if (num_user_sgprs > num_sgprs) {
115 /* Last 2 reserved SGPRs are used for VCC */
116 num_sgprs = num_user_sgprs + 2;
117 }
118 assert(num_sgprs <= 104);
119
120 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
121 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
122
123 shader->ls_rsrc1 = S_00B528_VGPRS((shader->num_vgprs - 1) / 4) |
124 S_00B528_SGPRS((num_sgprs - 1) / 8) |
125 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
126 S_00B528_DX10_CLAMP(shader->dx10_clamp_mode);
127 shader->ls_rsrc2 = S_00B52C_USER_SGPR(num_user_sgprs) |
128 S_00B52C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0);
129 }
130
131 static void si_shader_hs(struct si_shader *shader)
132 {
133 struct si_pm4_state *pm4;
134 unsigned num_sgprs, num_user_sgprs;
135 uint64_t va;
136
137 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
138 if (pm4 == NULL)
139 return;
140
141 va = shader->bo->gpu_address;
142 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
143
144 num_user_sgprs = SI_TCS_NUM_USER_SGPR;
145 num_sgprs = shader->num_sgprs;
146 /* One SGPR after user SGPRs is pre-loaded with tessellation factor
147 * buffer offset. */
148 if ((num_user_sgprs + 1) > num_sgprs) {
149 /* Last 2 reserved SGPRs are used for VCC */
150 num_sgprs = num_user_sgprs + 1 + 2;
151 }
152 assert(num_sgprs <= 104);
153
154 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
155 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
156 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
157 S_00B428_VGPRS((shader->num_vgprs - 1) / 4) |
158 S_00B428_SGPRS((num_sgprs - 1) / 8) |
159 S_00B428_DX10_CLAMP(shader->dx10_clamp_mode));
160 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
161 S_00B42C_USER_SGPR(num_user_sgprs) |
162 S_00B42C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
163 }
164
165 static void si_shader_es(struct si_shader *shader)
166 {
167 struct si_pm4_state *pm4;
168 unsigned num_sgprs, num_user_sgprs;
169 unsigned vgpr_comp_cnt;
170 uint64_t va;
171
172 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
173
174 if (pm4 == NULL)
175 return;
176
177 va = shader->bo->gpu_address;
178 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
179
180 if (shader->selector->type == PIPE_SHADER_VERTEX) {
181 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
182 num_user_sgprs = SI_ES_NUM_USER_SGPR;
183 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
184 vgpr_comp_cnt = 3; /* all components are needed for TES */
185 num_user_sgprs = SI_TES_NUM_USER_SGPR;
186 } else
187 unreachable("invalid shader selector type");
188
189 num_sgprs = shader->num_sgprs;
190 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
191 if ((num_user_sgprs + 1) > num_sgprs) {
192 /* Last 2 reserved SGPRs are used for VCC */
193 num_sgprs = num_user_sgprs + 1 + 2;
194 }
195 assert(num_sgprs <= 104);
196
197 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
198 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
199 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
200 S_00B328_VGPRS((shader->num_vgprs - 1) / 4) |
201 S_00B328_SGPRS((num_sgprs - 1) / 8) |
202 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
203 S_00B328_DX10_CLAMP(shader->dx10_clamp_mode));
204 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
205 S_00B32C_USER_SGPR(num_user_sgprs) |
206 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
207
208 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
209 si_set_tesseval_regs(shader, pm4);
210 }
211
212 static unsigned si_gs_get_max_stream(struct si_shader *shader)
213 {
214 struct pipe_stream_output_info *so = &shader->selector->so;
215 unsigned max_stream = 0, i;
216
217 if (so->num_outputs == 0)
218 return 0;
219
220 for (i = 0; i < so->num_outputs; i++) {
221 if (so->output[i].stream > max_stream)
222 max_stream = so->output[i].stream;
223 }
224 return max_stream;
225 }
226
227 static void si_shader_gs(struct si_shader *shader)
228 {
229 unsigned gs_vert_itemsize = shader->selector->info.num_outputs * 16;
230 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
231 unsigned gsvs_itemsize = (gs_vert_itemsize * gs_max_vert_out) >> 2;
232 unsigned gs_num_invocations = shader->selector->gs_num_invocations;
233 unsigned cut_mode;
234 struct si_pm4_state *pm4;
235 unsigned num_sgprs, num_user_sgprs;
236 uint64_t va;
237 unsigned max_stream = si_gs_get_max_stream(shader);
238
239 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
240 assert(gsvs_itemsize < (1 << 15));
241
242 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
243
244 if (pm4 == NULL)
245 return;
246
247 if (gs_max_vert_out <= 128) {
248 cut_mode = V_028A40_GS_CUT_128;
249 } else if (gs_max_vert_out <= 256) {
250 cut_mode = V_028A40_GS_CUT_256;
251 } else if (gs_max_vert_out <= 512) {
252 cut_mode = V_028A40_GS_CUT_512;
253 } else {
254 assert(gs_max_vert_out <= 1024);
255 cut_mode = V_028A40_GS_CUT_1024;
256 }
257
258 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
259 S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
260 S_028A40_CUT_MODE(cut_mode)|
261 S_028A40_ES_WRITE_OPTIMIZE(1) |
262 S_028A40_GS_WRITE_OPTIMIZE(1));
263
264 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
265 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize * ((max_stream >= 2) ? 2 : 1));
266 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize * ((max_stream >= 3) ? 3 : 1));
267
268 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
269 util_bitcount64(shader->selector->inputs_read) * (16 >> 2));
270 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize * (max_stream + 1));
271
272 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, gs_max_vert_out);
273
274 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize >> 2);
275 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? gs_vert_itemsize >> 2 : 0);
276 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? gs_vert_itemsize >> 2 : 0);
277 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? gs_vert_itemsize >> 2 : 0);
278
279 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
280 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
281 S_028B90_ENABLE(gs_num_invocations > 0));
282
283 va = shader->bo->gpu_address;
284 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
285 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
286 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
287
288 num_user_sgprs = SI_GS_NUM_USER_SGPR;
289 num_sgprs = shader->num_sgprs;
290 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
291 if ((num_user_sgprs + 2) > num_sgprs) {
292 /* Last 2 reserved SGPRs are used for VCC */
293 num_sgprs = num_user_sgprs + 2 + 2;
294 }
295 assert(num_sgprs <= 104);
296
297 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
298 S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
299 S_00B228_SGPRS((num_sgprs - 1) / 8) |
300 S_00B228_DX10_CLAMP(shader->dx10_clamp_mode));
301 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
302 S_00B22C_USER_SGPR(num_user_sgprs) |
303 S_00B22C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
304 }
305
306 static void si_shader_vs(struct si_shader *shader)
307 {
308 struct si_pm4_state *pm4;
309 unsigned num_sgprs, num_user_sgprs;
310 unsigned nparams, vgpr_comp_cnt;
311 uint64_t va;
312 unsigned window_space =
313 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
314 bool enable_prim_id = si_vs_exports_prim_id(shader);
315
316 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
317
318 if (pm4 == NULL)
319 return;
320
321 /* If this is the GS copy shader, the GS state writes this register.
322 * Otherwise, the VS state writes it.
323 */
324 if (!shader->is_gs_copy_shader) {
325 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
326 S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
327 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
328 } else
329 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
330
331 va = shader->bo->gpu_address;
332 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
333
334 if (shader->is_gs_copy_shader) {
335 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
336 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
337 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
338 vgpr_comp_cnt = shader->uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
339 num_user_sgprs = SI_VS_NUM_USER_SGPR;
340 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
341 vgpr_comp_cnt = 3; /* all components are needed for TES */
342 num_user_sgprs = SI_TES_NUM_USER_SGPR;
343 } else
344 unreachable("invalid shader selector type");
345
346 num_sgprs = shader->num_sgprs;
347 if (num_user_sgprs > num_sgprs) {
348 /* Last 2 reserved SGPRs are used for VCC */
349 num_sgprs = num_user_sgprs + 2;
350 }
351 assert(num_sgprs <= 104);
352
353 /* VS is required to export at least one param. */
354 nparams = MAX2(shader->nr_param_exports, 1);
355 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
356 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
357
358 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
359 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
360 S_02870C_POS1_EXPORT_FORMAT(shader->nr_pos_exports > 1 ?
361 V_02870C_SPI_SHADER_4COMP :
362 V_02870C_SPI_SHADER_NONE) |
363 S_02870C_POS2_EXPORT_FORMAT(shader->nr_pos_exports > 2 ?
364 V_02870C_SPI_SHADER_4COMP :
365 V_02870C_SPI_SHADER_NONE) |
366 S_02870C_POS3_EXPORT_FORMAT(shader->nr_pos_exports > 3 ?
367 V_02870C_SPI_SHADER_4COMP :
368 V_02870C_SPI_SHADER_NONE));
369
370 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
371 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
372 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
373 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
374 S_00B128_SGPRS((num_sgprs - 1) / 8) |
375 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
376 S_00B128_DX10_CLAMP(shader->dx10_clamp_mode));
377 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
378 S_00B12C_USER_SGPR(num_user_sgprs) |
379 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
380 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
381 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
382 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
383 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
384 S_00B12C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
385 if (window_space)
386 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
387 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
388 else
389 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
390 S_028818_VTX_W0_FMT(1) |
391 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
392 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
393 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
394
395 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
396 si_set_tesseval_regs(shader, pm4);
397 }
398
399 static void si_shader_ps(struct si_shader *shader)
400 {
401 struct tgsi_shader_info *info = &shader->selector->info;
402 struct si_pm4_state *pm4;
403 unsigned i, spi_ps_in_control;
404 unsigned num_sgprs, num_user_sgprs;
405 unsigned spi_baryc_cntl = 0;
406 uint64_t va;
407 bool has_centroid;
408
409 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
410
411 if (pm4 == NULL)
412 return;
413
414 for (i = 0; i < info->num_inputs; i++) {
415 switch (info->input_semantic_name[i]) {
416 case TGSI_SEMANTIC_POSITION:
417 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
418 * Possible vaules:
419 * 0 -> Position = pixel center (default)
420 * 1 -> Position = pixel centroid
421 * 2 -> Position = at sample position
422 */
423 switch (info->input_interpolate_loc[i]) {
424 case TGSI_INTERPOLATE_LOC_CENTROID:
425 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
426 break;
427 case TGSI_INTERPOLATE_LOC_SAMPLE:
428 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
429 break;
430 }
431
432 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
433 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
434 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
435 break;
436 }
437 }
438
439 has_centroid = G_0286CC_PERSP_CENTROID_ENA(shader->spi_ps_input_ena) ||
440 G_0286CC_LINEAR_CENTROID_ENA(shader->spi_ps_input_ena);
441
442 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->nparam) |
443 S_0286D8_BC_OPTIMIZE_DISABLE(has_centroid);
444
445 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
446 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
447
448 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
449 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
450 shader->spi_shader_col_format);
451 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
452
453 va = shader->bo->gpu_address;
454 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
455 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
456 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
457
458 num_user_sgprs = SI_PS_NUM_USER_SGPR;
459 num_sgprs = shader->num_sgprs;
460 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
461 if ((num_user_sgprs + 1) > num_sgprs) {
462 /* Last 2 reserved SGPRs are used for VCC */
463 num_sgprs = num_user_sgprs + 1 + 2;
464 }
465 assert(num_sgprs <= 104);
466
467 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
468 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
469 S_00B028_SGPRS((num_sgprs - 1) / 8) |
470 S_00B028_DX10_CLAMP(shader->dx10_clamp_mode));
471 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
472 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
473 S_00B02C_USER_SGPR(num_user_sgprs) |
474 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
475 }
476
477 static void si_shader_init_pm4_state(struct si_shader *shader)
478 {
479
480 if (shader->pm4)
481 si_pm4_free_state_simple(shader->pm4);
482
483 switch (shader->selector->type) {
484 case PIPE_SHADER_VERTEX:
485 if (shader->key.vs.as_ls)
486 si_shader_ls(shader);
487 else if (shader->key.vs.as_es)
488 si_shader_es(shader);
489 else
490 si_shader_vs(shader);
491 break;
492 case PIPE_SHADER_TESS_CTRL:
493 si_shader_hs(shader);
494 break;
495 case PIPE_SHADER_TESS_EVAL:
496 if (shader->key.tes.as_es)
497 si_shader_es(shader);
498 else
499 si_shader_vs(shader);
500 break;
501 case PIPE_SHADER_GEOMETRY:
502 si_shader_gs(shader);
503 si_shader_vs(shader->gs_copy_shader);
504 break;
505 case PIPE_SHADER_FRAGMENT:
506 si_shader_ps(shader);
507 break;
508 default:
509 assert(0);
510 }
511 }
512
513 /* Compute the key for the hw shader variant */
514 static inline void si_shader_selector_key(struct pipe_context *ctx,
515 struct si_shader_selector *sel,
516 union si_shader_key *key)
517 {
518 struct si_context *sctx = (struct si_context *)ctx;
519 unsigned i;
520
521 memset(key, 0, sizeof(*key));
522
523 switch (sel->type) {
524 case PIPE_SHADER_VERTEX:
525 if (sctx->vertex_elements)
526 for (i = 0; i < sctx->vertex_elements->count; ++i)
527 key->vs.instance_divisors[i] =
528 sctx->vertex_elements->elements[i].instance_divisor;
529
530 if (sctx->tes_shader.cso)
531 key->vs.as_ls = 1;
532 else if (sctx->gs_shader.cso) {
533 key->vs.as_es = 1;
534 key->vs.es_enabled_outputs = sctx->gs_shader.cso->inputs_read;
535 }
536
537 if (!sctx->gs_shader.cso && sctx->ps_shader.cso &&
538 sctx->ps_shader.cso->info.uses_primid)
539 key->vs.export_prim_id = 1;
540 break;
541 case PIPE_SHADER_TESS_CTRL:
542 key->tcs.prim_mode =
543 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
544 break;
545 case PIPE_SHADER_TESS_EVAL:
546 if (sctx->gs_shader.cso) {
547 key->tes.as_es = 1;
548 key->tes.es_enabled_outputs = sctx->gs_shader.cso->inputs_read;
549 } else if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
550 key->tes.export_prim_id = 1;
551 break;
552 case PIPE_SHADER_GEOMETRY:
553 break;
554 case PIPE_SHADER_FRAGMENT: {
555 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
556
557 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
558 key->ps.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
559 key->ps.export_16bpc = sctx->framebuffer.export_16bpc;
560
561 if (rs) {
562 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
563 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
564 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
565 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
566
567 key->ps.color_two_side = rs->two_side;
568
569 if (sctx->queued.named.blend) {
570 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
571 rs->multisample_enable &&
572 !sctx->framebuffer.cb0_is_integer;
573 }
574
575 key->ps.poly_stipple = rs->poly_stipple_enable && is_poly;
576 key->ps.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
577 (is_line && rs->line_smooth)) &&
578 sctx->framebuffer.nr_samples <= 1;
579 key->ps.clamp_color = rs->clamp_fragment_color;
580 }
581
582 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
583 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
584 if (sctx->queued.named.dsa &&
585 !sctx->framebuffer.cb0_is_integer)
586 key->ps.alpha_func = sctx->queued.named.dsa->alpha_func;
587 break;
588 }
589 default:
590 assert(0);
591 }
592 }
593
594 /* Select the hw shader variant depending on the current state. */
595 static int si_shader_select(struct pipe_context *ctx,
596 struct si_shader_ctx_state *state)
597 {
598 struct si_context *sctx = (struct si_context *)ctx;
599 struct si_shader_selector *sel = state->cso;
600 struct si_shader *current = state->current;
601 union si_shader_key key;
602 struct si_shader *iter, *shader = NULL;
603 int r;
604
605 si_shader_selector_key(ctx, sel, &key);
606
607 /* Check if we don't need to change anything.
608 * This path is also used for most shaders that don't need multiple
609 * variants, it will cost just a computation of the key and this
610 * test. */
611 if (likely(current && memcmp(&current->key, &key, sizeof(key)) == 0))
612 return 0;
613
614 pipe_mutex_lock(sel->mutex);
615
616 /* Find the shader variant. */
617 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
618 /* Don't check the "current" shader. We checked it above. */
619 if (current != iter &&
620 memcmp(&iter->key, &key, sizeof(key)) == 0) {
621 state->current = iter;
622 pipe_mutex_unlock(sel->mutex);
623 return 0;
624 }
625 }
626
627 /* Build a new shader. */
628 shader = CALLOC_STRUCT(si_shader);
629 if (!shader) {
630 pipe_mutex_unlock(sel->mutex);
631 return -ENOMEM;
632 }
633 shader->selector = sel;
634 shader->key = key;
635
636 r = si_shader_create(sctx->screen, sctx->tm, shader);
637 if (unlikely(r)) {
638 R600_ERR("Failed to build shader variant (type=%u) %d\n",
639 sel->type, r);
640 FREE(shader);
641 pipe_mutex_unlock(sel->mutex);
642 return r;
643 }
644 si_shader_init_pm4_state(shader);
645
646 if (!sel->last_variant) {
647 sel->first_variant = shader;
648 sel->last_variant = shader;
649 } else {
650 sel->last_variant->next_variant = shader;
651 sel->last_variant = shader;
652 }
653 state->current = shader;
654 p_atomic_inc(&sctx->screen->b.num_compilations);
655 pipe_mutex_unlock(sel->mutex);
656 return 0;
657 }
658
659 static void *si_create_shader_selector(struct pipe_context *ctx,
660 const struct pipe_shader_state *state)
661 {
662 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
663 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
664 int i;
665
666 if (!sel)
667 return NULL;
668
669 sel->tokens = tgsi_dup_tokens(state->tokens);
670 if (!sel->tokens) {
671 FREE(sel);
672 return NULL;
673 }
674
675 sel->so = state->stream_output;
676 tgsi_scan_shader(state->tokens, &sel->info);
677 sel->type = util_pipe_shader_from_tgsi_processor(sel->info.processor);
678 p_atomic_inc(&sscreen->b.num_shaders_created);
679
680 /* First set which opcode uses which (i,j) pair. */
681 if (sel->info.uses_persp_opcode_interp_centroid)
682 sel->info.uses_persp_centroid = true;
683
684 if (sel->info.uses_linear_opcode_interp_centroid)
685 sel->info.uses_linear_centroid = true;
686
687 if (sel->info.uses_persp_opcode_interp_offset ||
688 sel->info.uses_persp_opcode_interp_sample)
689 sel->info.uses_persp_center = true;
690
691 if (sel->info.uses_linear_opcode_interp_offset ||
692 sel->info.uses_linear_opcode_interp_sample)
693 sel->info.uses_linear_center = true;
694
695 /* Determine if the shader has to use a conditional assignment when
696 * emulating force_persample_interp.
697 */
698 sel->forces_persample_interp_for_persp =
699 sel->info.uses_persp_center +
700 sel->info.uses_persp_centroid +
701 sel->info.uses_persp_sample >= 2;
702
703 sel->forces_persample_interp_for_linear =
704 sel->info.uses_linear_center +
705 sel->info.uses_linear_centroid +
706 sel->info.uses_linear_sample >= 2;
707
708 switch (sel->type) {
709 case PIPE_SHADER_GEOMETRY:
710 sel->gs_output_prim =
711 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
712 sel->gs_max_out_vertices =
713 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
714 sel->gs_num_invocations =
715 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
716 sel->gsvs_itemsize = sel->info.num_outputs * 16 *
717 sel->gs_max_out_vertices;
718
719 for (i = 0; i < sel->info.num_inputs; i++) {
720 unsigned name = sel->info.input_semantic_name[i];
721 unsigned index = sel->info.input_semantic_index[i];
722
723 switch (name) {
724 case TGSI_SEMANTIC_PRIMID:
725 break;
726 default:
727 sel->inputs_read |=
728 1llu << si_shader_io_get_unique_index(name, index);
729 }
730 }
731 break;
732
733 case PIPE_SHADER_VERTEX:
734 case PIPE_SHADER_TESS_CTRL:
735 for (i = 0; i < sel->info.num_outputs; i++) {
736 unsigned name = sel->info.output_semantic_name[i];
737 unsigned index = sel->info.output_semantic_index[i];
738
739 switch (name) {
740 case TGSI_SEMANTIC_TESSINNER:
741 case TGSI_SEMANTIC_TESSOUTER:
742 case TGSI_SEMANTIC_PATCH:
743 sel->patch_outputs_written |=
744 1llu << si_shader_io_get_unique_index(name, index);
745 break;
746 default:
747 sel->outputs_written |=
748 1llu << si_shader_io_get_unique_index(name, index);
749 }
750 }
751 break;
752 case PIPE_SHADER_FRAGMENT:
753 for (i = 0; i < sel->info.num_outputs; i++) {
754 unsigned name = sel->info.output_semantic_name[i];
755 unsigned index = sel->info.output_semantic_index[i];
756
757 if (name == TGSI_SEMANTIC_COLOR)
758 sel->ps_colors_written |= 1 << index;
759 }
760 break;
761 }
762
763 if (sscreen->b.debug_flags & DBG_PRECOMPILE) {
764 struct si_shader_ctx_state state = {sel};
765
766 if (si_shader_select(ctx, &state)) {
767 fprintf(stderr, "radeonsi: can't create a shader\n");
768 tgsi_free_tokens(sel->tokens);
769 FREE(sel);
770 return NULL;
771 }
772 }
773
774 pipe_mutex_init(sel->mutex);
775 return sel;
776 }
777
778 /**
779 * Normally, we only emit 1 viewport and 1 scissor if no shader is using
780 * the VIEWPORT_INDEX output, and emitting the other viewports and scissors
781 * is delayed. When a shader with VIEWPORT_INDEX appears, this should be
782 * called to emit the rest.
783 */
784 static void si_update_viewports_and_scissors(struct si_context *sctx)
785 {
786 struct tgsi_shader_info *info = si_get_vs_info(sctx);
787
788 if (!info || !info->writes_viewport_index)
789 return;
790
791 if (sctx->scissors.dirty_mask)
792 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
793 if (sctx->viewports.dirty_mask)
794 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
795 }
796
797 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
798 {
799 struct si_context *sctx = (struct si_context *)ctx;
800 struct si_shader_selector *sel = state;
801
802 if (sctx->vs_shader.cso == sel)
803 return;
804
805 sctx->vs_shader.cso = sel;
806 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
807 si_mark_atom_dirty(sctx, &sctx->clip_regs);
808 si_update_viewports_and_scissors(sctx);
809 }
810
811 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
812 {
813 struct si_context *sctx = (struct si_context *)ctx;
814 struct si_shader_selector *sel = state;
815 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
816
817 if (sctx->gs_shader.cso == sel)
818 return;
819
820 sctx->gs_shader.cso = sel;
821 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
822 si_mark_atom_dirty(sctx, &sctx->clip_regs);
823 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
824
825 if (enable_changed)
826 si_shader_change_notify(sctx);
827 si_update_viewports_and_scissors(sctx);
828 }
829
830 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
831 {
832 struct si_context *sctx = (struct si_context *)ctx;
833 struct si_shader_selector *sel = state;
834 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
835
836 if (sctx->tcs_shader.cso == sel)
837 return;
838
839 sctx->tcs_shader.cso = sel;
840 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
841
842 if (enable_changed)
843 sctx->last_tcs = NULL; /* invalidate derived tess state */
844 }
845
846 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
847 {
848 struct si_context *sctx = (struct si_context *)ctx;
849 struct si_shader_selector *sel = state;
850 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
851
852 if (sctx->tes_shader.cso == sel)
853 return;
854
855 sctx->tes_shader.cso = sel;
856 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
857 si_mark_atom_dirty(sctx, &sctx->clip_regs);
858 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
859
860 if (enable_changed) {
861 si_shader_change_notify(sctx);
862 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
863 }
864 si_update_viewports_and_scissors(sctx);
865 }
866
867 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
868 {
869 struct si_context *sctx = (struct si_context *)ctx;
870 struct si_shader_selector *sel = state;
871
872 /* skip if supplied shader is one already in use */
873 if (sctx->ps_shader.cso == sel)
874 return;
875
876 sctx->ps_shader.cso = sel;
877 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
878 si_mark_atom_dirty(sctx, &sctx->cb_target_mask);
879 }
880
881 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
882 {
883 struct si_context *sctx = (struct si_context *)ctx;
884 struct si_shader_selector *sel = (struct si_shader_selector *)state;
885 struct si_shader *p = sel->first_variant, *c;
886 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
887 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
888 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
889 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
890 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
891 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
892 };
893
894 if (current_shader[sel->type]->cso == sel) {
895 current_shader[sel->type]->cso = NULL;
896 current_shader[sel->type]->current = NULL;
897 }
898
899 while (p) {
900 c = p->next_variant;
901 switch (sel->type) {
902 case PIPE_SHADER_VERTEX:
903 if (p->key.vs.as_ls)
904 si_pm4_delete_state(sctx, ls, p->pm4);
905 else if (p->key.vs.as_es)
906 si_pm4_delete_state(sctx, es, p->pm4);
907 else
908 si_pm4_delete_state(sctx, vs, p->pm4);
909 break;
910 case PIPE_SHADER_TESS_CTRL:
911 si_pm4_delete_state(sctx, hs, p->pm4);
912 break;
913 case PIPE_SHADER_TESS_EVAL:
914 if (p->key.tes.as_es)
915 si_pm4_delete_state(sctx, es, p->pm4);
916 else
917 si_pm4_delete_state(sctx, vs, p->pm4);
918 break;
919 case PIPE_SHADER_GEOMETRY:
920 si_pm4_delete_state(sctx, gs, p->pm4);
921 si_pm4_delete_state(sctx, vs, p->gs_copy_shader->pm4);
922 break;
923 case PIPE_SHADER_FRAGMENT:
924 si_pm4_delete_state(sctx, ps, p->pm4);
925 break;
926 }
927
928 si_shader_destroy(p);
929 free(p);
930 p = c;
931 }
932
933 pipe_mutex_destroy(sel->mutex);
934 free(sel->tokens);
935 free(sel);
936 }
937
938 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
939 {
940 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
941 struct si_shader *ps = sctx->ps_shader.current;
942 struct si_shader *vs = si_get_vs_state(sctx);
943 struct tgsi_shader_info *psinfo;
944 struct tgsi_shader_info *vsinfo = &vs->selector->info;
945 unsigned i, j, tmp, num_written = 0;
946
947 if (!ps || !ps->nparam)
948 return;
949
950 psinfo = &ps->selector->info;
951
952 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, ps->nparam);
953
954 for (i = 0; i < psinfo->num_inputs; i++) {
955 unsigned name = psinfo->input_semantic_name[i];
956 unsigned index = psinfo->input_semantic_index[i];
957 unsigned interpolate = psinfo->input_interpolate[i];
958 unsigned param_offset = ps->ps_input_param_offset[i];
959
960 if (name == TGSI_SEMANTIC_POSITION ||
961 name == TGSI_SEMANTIC_FACE)
962 /* Read from preloaded VGPRs, not parameters */
963 continue;
964
965 bcolor:
966 tmp = 0;
967
968 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
969 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
970 tmp |= S_028644_FLAT_SHADE(1);
971
972 if (name == TGSI_SEMANTIC_PCOORD ||
973 (name == TGSI_SEMANTIC_TEXCOORD &&
974 sctx->sprite_coord_enable & (1 << index))) {
975 tmp |= S_028644_PT_SPRITE_TEX(1);
976 }
977
978 for (j = 0; j < vsinfo->num_outputs; j++) {
979 if (name == vsinfo->output_semantic_name[j] &&
980 index == vsinfo->output_semantic_index[j]) {
981 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[j]);
982 break;
983 }
984 }
985
986 if (name == TGSI_SEMANTIC_PRIMID)
987 /* PrimID is written after the last output. */
988 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[vsinfo->num_outputs]);
989 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(tmp)) {
990 /* No corresponding output found, load defaults into input.
991 * Don't set any other bits.
992 * (FLAT_SHADE=1 completely changes behavior) */
993 tmp = S_028644_OFFSET(0x20);
994 }
995
996 assert(param_offset == num_written);
997 radeon_emit(cs, tmp);
998 num_written++;
999
1000 if (name == TGSI_SEMANTIC_COLOR &&
1001 ps->key.ps.color_two_side) {
1002 name = TGSI_SEMANTIC_BCOLOR;
1003 param_offset++;
1004 goto bcolor;
1005 }
1006 }
1007 assert(ps->nparam == num_written);
1008 }
1009
1010 static void si_emit_spi_ps_input(struct si_context *sctx, struct r600_atom *atom)
1011 {
1012 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1013 struct si_shader *ps = sctx->ps_shader.current;
1014 unsigned input_ena;
1015
1016 if (!ps)
1017 return;
1018
1019 input_ena = ps->spi_ps_input_ena;
1020
1021 /* we need to enable at least one of them, otherwise we hang the GPU */
1022 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1023 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1024 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1025 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1026 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1027 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1028 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1029 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1030
1031 if (sctx->force_persample_interp) {
1032 unsigned num_persp = G_0286CC_PERSP_SAMPLE_ENA(input_ena) +
1033 G_0286CC_PERSP_CENTER_ENA(input_ena) +
1034 G_0286CC_PERSP_CENTROID_ENA(input_ena);
1035 unsigned num_linear = G_0286CC_LINEAR_SAMPLE_ENA(input_ena) +
1036 G_0286CC_LINEAR_CENTER_ENA(input_ena) +
1037 G_0286CC_LINEAR_CENTROID_ENA(input_ena);
1038
1039 /* If only one set of (i,j) coordinates is used, we can disable
1040 * CENTER/CENTROID, enable SAMPLE and it will load SAMPLE coordinates
1041 * where CENTER/CENTROID are expected, effectively forcing per-sample
1042 * interpolation.
1043 */
1044 if (num_persp == 1) {
1045 input_ena &= C_0286CC_PERSP_CENTER_ENA;
1046 input_ena &= C_0286CC_PERSP_CENTROID_ENA;
1047 input_ena |= G_0286CC_PERSP_SAMPLE_ENA(1);
1048 }
1049 if (num_linear == 1) {
1050 input_ena &= C_0286CC_LINEAR_CENTER_ENA;
1051 input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
1052 input_ena |= G_0286CC_LINEAR_SAMPLE_ENA(1);
1053 }
1054
1055 /* If at least 2 sets of coordinates are used, we can't use this
1056 * trick and have to select SAMPLE using a conditional assignment
1057 * in the shader with "force_persample_interp" being a shader constant.
1058 */
1059 }
1060
1061 radeon_set_context_reg_seq(cs, R_0286CC_SPI_PS_INPUT_ENA, 2);
1062 radeon_emit(cs, input_ena);
1063 radeon_emit(cs, input_ena);
1064
1065 if (ps->selector->forces_persample_interp_for_persp ||
1066 ps->selector->forces_persample_interp_for_linear)
1067 radeon_set_sh_reg(cs, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1068 SI_SGPR_PS_STATE_BITS * 4,
1069 sctx->force_persample_interp);
1070 }
1071
1072 /**
1073 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
1074 */
1075 static void si_init_config_add_vgt_flush(struct si_context *sctx)
1076 {
1077 if (sctx->init_config_has_vgt_flush)
1078 return;
1079
1080 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
1081 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1082 si_pm4_cmd_end(sctx->init_config, false);
1083 sctx->init_config_has_vgt_flush = true;
1084 }
1085
1086 /* Initialize state related to ESGS / GSVS ring buffers */
1087 static void si_init_gs_rings(struct si_context *sctx)
1088 {
1089 unsigned esgs_ring_size = 128 * 1024;
1090 unsigned gsvs_ring_size = 60 * 1024 * 1024;
1091
1092 assert(!sctx->esgs_ring && !sctx->gsvs_ring);
1093
1094 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1095 PIPE_USAGE_DEFAULT, esgs_ring_size);
1096 if (!sctx->esgs_ring)
1097 return;
1098
1099 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1100 PIPE_USAGE_DEFAULT, gsvs_ring_size);
1101 if (!sctx->gsvs_ring) {
1102 pipe_resource_reference(&sctx->esgs_ring, NULL);
1103 return;
1104 }
1105
1106 si_init_config_add_vgt_flush(sctx);
1107
1108 /* Append these registers to the init config state. */
1109 if (sctx->b.chip_class >= CIK) {
1110 if (sctx->b.chip_class >= VI) {
1111 /* The maximum sizes are 63.999 MB on VI, because
1112 * the register fields only have 18 bits. */
1113 assert(esgs_ring_size / 256 < (1 << 18));
1114 assert(gsvs_ring_size / 256 < (1 << 18));
1115 }
1116 si_pm4_set_reg(sctx->init_config, R_030900_VGT_ESGS_RING_SIZE,
1117 esgs_ring_size / 256);
1118 si_pm4_set_reg(sctx->init_config, R_030904_VGT_GSVS_RING_SIZE,
1119 gsvs_ring_size / 256);
1120 } else {
1121 si_pm4_set_reg(sctx->init_config, R_0088C8_VGT_ESGS_RING_SIZE,
1122 esgs_ring_size / 256);
1123 si_pm4_set_reg(sctx->init_config, R_0088CC_VGT_GSVS_RING_SIZE,
1124 gsvs_ring_size / 256);
1125 }
1126
1127 /* Flush the context to re-emit the init_config state.
1128 * This is done only once in a lifetime of a context.
1129 */
1130 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1131 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1132 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1133
1134 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
1135 sctx->esgs_ring, 0, esgs_ring_size,
1136 true, true, 4, 64, 0);
1137 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
1138 sctx->esgs_ring, 0, esgs_ring_size,
1139 false, false, 0, 0, 0);
1140 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
1141 sctx->gsvs_ring, 0, gsvs_ring_size,
1142 false, false, 0, 0, 0);
1143 }
1144
1145 static void si_update_gs_rings(struct si_context *sctx)
1146 {
1147 unsigned gsvs_itemsize = sctx->gs_shader.cso->gsvs_itemsize;
1148 uint64_t offset;
1149
1150 if (gsvs_itemsize == sctx->last_gsvs_itemsize)
1151 return;
1152
1153 sctx->last_gsvs_itemsize = gsvs_itemsize;
1154
1155 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
1156 sctx->gsvs_ring, gsvs_itemsize,
1157 64, true, true, 4, 16, 0);
1158
1159 offset = gsvs_itemsize * 64;
1160 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_1,
1161 sctx->gsvs_ring, gsvs_itemsize,
1162 64, true, true, 4, 16, offset);
1163
1164 offset = (gsvs_itemsize * 2) * 64;
1165 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_2,
1166 sctx->gsvs_ring, gsvs_itemsize,
1167 64, true, true, 4, 16, offset);
1168
1169 offset = (gsvs_itemsize * 3) * 64;
1170 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_3,
1171 sctx->gsvs_ring, gsvs_itemsize,
1172 64, true, true, 4, 16, offset);
1173 }
1174
1175 /**
1176 * @returns 1 if \p sel has been updated to use a new scratch buffer
1177 * 0 if not
1178 * < 0 if there was a failure
1179 */
1180 static int si_update_scratch_buffer(struct si_context *sctx,
1181 struct si_shader *shader)
1182 {
1183 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
1184 int r;
1185
1186 if (!shader)
1187 return 0;
1188
1189 /* This shader doesn't need a scratch buffer */
1190 if (shader->scratch_bytes_per_wave == 0)
1191 return 0;
1192
1193 /* This shader is already configured to use the current
1194 * scratch buffer. */
1195 if (shader->scratch_bo == sctx->scratch_buffer)
1196 return 0;
1197
1198 assert(sctx->scratch_buffer);
1199
1200 si_shader_apply_scratch_relocs(sctx, shader, scratch_va);
1201
1202 /* Replace the shader bo with a new bo that has the relocs applied. */
1203 r = si_shader_binary_upload(sctx->screen, shader);
1204 if (r)
1205 return r;
1206
1207 /* Update the shader state to use the new shader bo. */
1208 si_shader_init_pm4_state(shader);
1209
1210 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
1211
1212 return 1;
1213 }
1214
1215 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
1216 {
1217 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
1218 }
1219
1220 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
1221 {
1222 return shader ? shader->scratch_bytes_per_wave : 0;
1223 }
1224
1225 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
1226 {
1227 unsigned bytes = 0;
1228
1229 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
1230 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
1231 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
1232 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tcs_shader.current));
1233 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
1234 return bytes;
1235 }
1236
1237 static bool si_update_spi_tmpring_size(struct si_context *sctx)
1238 {
1239 unsigned current_scratch_buffer_size =
1240 si_get_current_scratch_buffer_size(sctx);
1241 unsigned scratch_bytes_per_wave =
1242 si_get_max_scratch_bytes_per_wave(sctx);
1243 unsigned scratch_needed_size = scratch_bytes_per_wave *
1244 sctx->scratch_waves;
1245 int r;
1246
1247 if (scratch_needed_size > 0) {
1248 if (scratch_needed_size > current_scratch_buffer_size) {
1249 /* Create a bigger scratch buffer */
1250 pipe_resource_reference(
1251 (struct pipe_resource**)&sctx->scratch_buffer,
1252 NULL);
1253
1254 sctx->scratch_buffer =
1255 si_resource_create_custom(&sctx->screen->b.b,
1256 PIPE_USAGE_DEFAULT, scratch_needed_size);
1257 if (!sctx->scratch_buffer)
1258 return false;
1259 sctx->emit_scratch_reloc = true;
1260 }
1261
1262 /* Update the shaders, so they are using the latest scratch. The
1263 * scratch buffer may have been changed since these shaders were
1264 * last used, so we still need to try to update them, even if
1265 * they require scratch buffers smaller than the current size.
1266 */
1267 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
1268 if (r < 0)
1269 return false;
1270 if (r == 1)
1271 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
1272
1273 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
1274 if (r < 0)
1275 return false;
1276 if (r == 1)
1277 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1278
1279 r = si_update_scratch_buffer(sctx, sctx->tcs_shader.current);
1280 if (r < 0)
1281 return false;
1282 if (r == 1)
1283 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1284
1285 /* VS can be bound as LS, ES, or VS. */
1286 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
1287 if (r < 0)
1288 return false;
1289 if (r == 1) {
1290 if (sctx->tes_shader.current)
1291 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1292 else if (sctx->gs_shader.current)
1293 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1294 else
1295 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1296 }
1297
1298 /* TES can be bound as ES or VS. */
1299 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
1300 if (r < 0)
1301 return false;
1302 if (r == 1) {
1303 if (sctx->gs_shader.current)
1304 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1305 else
1306 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1307 }
1308 }
1309
1310 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
1311 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
1312 "scratch size should already be aligned correctly.");
1313
1314 sctx->spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
1315 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
1316 return true;
1317 }
1318
1319 static void si_init_tess_factor_ring(struct si_context *sctx)
1320 {
1321 assert(!sctx->tf_ring);
1322
1323 sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1324 PIPE_USAGE_DEFAULT,
1325 32768 * sctx->screen->b.info.max_se);
1326 if (!sctx->tf_ring)
1327 return;
1328
1329 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
1330
1331 si_init_config_add_vgt_flush(sctx);
1332
1333 /* Append these registers to the init config state. */
1334 if (sctx->b.chip_class >= CIK) {
1335 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
1336 S_030938_SIZE(sctx->tf_ring->width0 / 4));
1337 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
1338 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1339 } else {
1340 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
1341 S_008988_SIZE(sctx->tf_ring->width0 / 4));
1342 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
1343 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1344 }
1345
1346 /* Flush the context to re-emit the init_config state.
1347 * This is done only once in a lifetime of a context.
1348 */
1349 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1350 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1351 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1352
1353 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_TESS_CTRL,
1354 SI_RING_TESS_FACTOR, sctx->tf_ring, 0,
1355 sctx->tf_ring->width0, false, false, 0, 0, 0);
1356 }
1357
1358 /**
1359 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
1360 * VS passes its outputs to TES directly, so the fixed-function shader only
1361 * has to write TESSOUTER and TESSINNER.
1362 */
1363 static void si_generate_fixed_func_tcs(struct si_context *sctx)
1364 {
1365 struct ureg_src const0, const1;
1366 struct ureg_dst tessouter, tessinner;
1367 struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
1368
1369 if (!ureg)
1370 return; /* if we get here, we're screwed */
1371
1372 assert(!sctx->fixed_func_tcs_shader.cso);
1373
1374 ureg_DECL_constant2D(ureg, 0, 1, SI_DRIVER_STATE_CONST_BUF);
1375 const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 0),
1376 SI_DRIVER_STATE_CONST_BUF);
1377 const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 1),
1378 SI_DRIVER_STATE_CONST_BUF);
1379
1380 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1381 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1382
1383 ureg_MOV(ureg, tessouter, const0);
1384 ureg_MOV(ureg, tessinner, const1);
1385 ureg_END(ureg);
1386
1387 sctx->fixed_func_tcs_shader.cso =
1388 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
1389 }
1390
1391 static void si_update_vgt_shader_config(struct si_context *sctx)
1392 {
1393 /* Calculate the index of the config.
1394 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
1395 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
1396 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
1397
1398 if (!*pm4) {
1399 uint32_t stages = 0;
1400
1401 *pm4 = CALLOC_STRUCT(si_pm4_state);
1402
1403 if (sctx->tes_shader.cso) {
1404 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
1405 S_028B54_HS_EN(1);
1406
1407 if (sctx->gs_shader.cso)
1408 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
1409 S_028B54_GS_EN(1) |
1410 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1411 else
1412 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
1413 } else if (sctx->gs_shader.cso) {
1414 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1415 S_028B54_GS_EN(1) |
1416 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1417 }
1418
1419 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
1420 }
1421 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
1422 }
1423
1424 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
1425 {
1426 struct pipe_stream_output_info *so = &shader->so;
1427 uint32_t enabled_stream_buffers_mask = 0;
1428 int i;
1429
1430 for (i = 0; i < so->num_outputs; i++)
1431 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
1432 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
1433 sctx->b.streamout.stride_in_dw = shader->so.stride;
1434 }
1435
1436 bool si_update_shaders(struct si_context *sctx)
1437 {
1438 struct pipe_context *ctx = (struct pipe_context*)sctx;
1439 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1440 int r;
1441
1442 /* Update stages before GS. */
1443 if (sctx->tes_shader.cso) {
1444 if (!sctx->tf_ring) {
1445 si_init_tess_factor_ring(sctx);
1446 if (!sctx->tf_ring)
1447 return false;
1448 }
1449
1450 /* VS as LS */
1451 r = si_shader_select(ctx, &sctx->vs_shader);
1452 if (r)
1453 return false;
1454 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1455
1456 if (sctx->tcs_shader.cso) {
1457 r = si_shader_select(ctx, &sctx->tcs_shader);
1458 if (r)
1459 return false;
1460 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1461 } else {
1462 if (!sctx->fixed_func_tcs_shader.cso) {
1463 si_generate_fixed_func_tcs(sctx);
1464 if (!sctx->fixed_func_tcs_shader.cso)
1465 return false;
1466 }
1467
1468 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader);
1469 if (r)
1470 return false;
1471 si_pm4_bind_state(sctx, hs,
1472 sctx->fixed_func_tcs_shader.current->pm4);
1473 }
1474
1475 r = si_shader_select(ctx, &sctx->tes_shader);
1476 if (r)
1477 return false;
1478
1479 if (sctx->gs_shader.cso) {
1480 /* TES as ES */
1481 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1482 } else {
1483 /* TES as VS */
1484 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1485 si_update_so(sctx, sctx->tes_shader.cso);
1486 }
1487 } else if (sctx->gs_shader.cso) {
1488 /* VS as ES */
1489 r = si_shader_select(ctx, &sctx->vs_shader);
1490 if (r)
1491 return false;
1492 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1493 } else {
1494 /* VS as VS */
1495 r = si_shader_select(ctx, &sctx->vs_shader);
1496 if (r)
1497 return false;
1498 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1499 si_update_so(sctx, sctx->vs_shader.cso);
1500 }
1501
1502 /* Update GS. */
1503 if (sctx->gs_shader.cso) {
1504 r = si_shader_select(ctx, &sctx->gs_shader);
1505 if (r)
1506 return false;
1507 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1508 si_pm4_bind_state(sctx, vs, sctx->gs_shader.current->gs_copy_shader->pm4);
1509 si_update_so(sctx, sctx->gs_shader.cso);
1510
1511 if (!sctx->gsvs_ring) {
1512 si_init_gs_rings(sctx);
1513 if (!sctx->gsvs_ring)
1514 return false;
1515 }
1516
1517 si_update_gs_rings(sctx);
1518 } else {
1519 si_pm4_bind_state(sctx, gs, NULL);
1520 si_pm4_bind_state(sctx, es, NULL);
1521 }
1522
1523 si_update_vgt_shader_config(sctx);
1524
1525 if (sctx->ps_shader.cso) {
1526 r = si_shader_select(ctx, &sctx->ps_shader);
1527 if (r)
1528 return false;
1529 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
1530
1531 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
1532 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
1533 sctx->flatshade != rs->flatshade) {
1534 sctx->sprite_coord_enable = rs->sprite_coord_enable;
1535 sctx->flatshade = rs->flatshade;
1536 si_mark_atom_dirty(sctx, &sctx->spi_map);
1537 }
1538
1539 if (si_pm4_state_changed(sctx, ps) ||
1540 sctx->force_persample_interp != rs->force_persample_interp) {
1541 sctx->force_persample_interp = rs->force_persample_interp;
1542 si_mark_atom_dirty(sctx, &sctx->spi_ps_input);
1543 }
1544
1545 if (sctx->ps_db_shader_control != sctx->ps_shader.current->db_shader_control) {
1546 sctx->ps_db_shader_control = sctx->ps_shader.current->db_shader_control;
1547 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1548 }
1549
1550 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.ps.poly_line_smoothing) {
1551 sctx->smoothing_enabled = sctx->ps_shader.current->key.ps.poly_line_smoothing;
1552 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1553
1554 if (sctx->b.chip_class == SI)
1555 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1556 }
1557 }
1558
1559 if (si_pm4_state_changed(sctx, ls) ||
1560 si_pm4_state_changed(sctx, hs) ||
1561 si_pm4_state_changed(sctx, es) ||
1562 si_pm4_state_changed(sctx, gs) ||
1563 si_pm4_state_changed(sctx, vs) ||
1564 si_pm4_state_changed(sctx, ps)) {
1565 if (!si_update_spi_tmpring_size(sctx))
1566 return false;
1567 }
1568 return true;
1569 }
1570
1571 void si_init_shader_functions(struct si_context *sctx)
1572 {
1573 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
1574 si_init_atom(sctx, &sctx->spi_ps_input, &sctx->atoms.s.spi_ps_input, si_emit_spi_ps_input);
1575
1576 sctx->b.b.create_vs_state = si_create_shader_selector;
1577 sctx->b.b.create_tcs_state = si_create_shader_selector;
1578 sctx->b.b.create_tes_state = si_create_shader_selector;
1579 sctx->b.b.create_gs_state = si_create_shader_selector;
1580 sctx->b.b.create_fs_state = si_create_shader_selector;
1581
1582 sctx->b.b.bind_vs_state = si_bind_vs_shader;
1583 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
1584 sctx->b.b.bind_tes_state = si_bind_tes_shader;
1585 sctx->b.b.bind_gs_state = si_bind_gs_shader;
1586 sctx->b.b.bind_fs_state = si_bind_ps_shader;
1587
1588 sctx->b.b.delete_vs_state = si_delete_shader_selector;
1589 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
1590 sctx->b.b.delete_tes_state = si_delete_shader_selector;
1591 sctx->b.b.delete_gs_state = si_delete_shader_selector;
1592 sctx->b.b.delete_fs_state = si_delete_shader_selector;
1593 }