2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
31 #include "radeon/r600_cs.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/hash_table.h"
36 #include "util/crc32.h"
37 #include "util/u_memory.h"
38 #include "util/u_prim.h"
40 #include "util/disk_cache.h"
41 #include "util/mesa-sha1.h"
46 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
49 static void *si_get_tgsi_binary(struct si_shader_selector
*sel
)
51 unsigned tgsi_size
= tgsi_num_tokens(sel
->tokens
) *
52 sizeof(struct tgsi_token
);
53 unsigned size
= 4 + tgsi_size
+ sizeof(sel
->so
);
54 char *result
= (char*)MALLOC(size
);
59 *((uint32_t*)result
) = size
;
60 memcpy(result
+ 4, sel
->tokens
, tgsi_size
);
61 memcpy(result
+ 4 + tgsi_size
, &sel
->so
, sizeof(sel
->so
));
65 /** Copy "data" to "ptr" and return the next dword following copied data. */
66 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
68 /* data may be NULL if size == 0 */
70 memcpy(ptr
, data
, size
);
71 ptr
+= DIV_ROUND_UP(size
, 4);
75 /** Read data from "ptr". Return the next dword following the data. */
76 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
78 memcpy(data
, ptr
, size
);
79 ptr
+= DIV_ROUND_UP(size
, 4);
84 * Write the size as uint followed by the data. Return the next dword
85 * following the copied data.
87 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
90 return write_data(ptr
, data
, size
);
94 * Read the size as uint followed by the data. Return both via parameters.
95 * Return the next dword following the data.
97 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
100 assert(*data
== NULL
);
103 *data
= malloc(*size
);
104 return read_data(ptr
, *data
, *size
);
108 * Return the shader binary in a buffer. The first 4 bytes contain its size
111 static void *si_get_shader_binary(struct si_shader
*shader
)
113 /* There is always a size of data followed by the data itself. */
114 unsigned relocs_size
= shader
->binary
.reloc_count
*
115 sizeof(shader
->binary
.relocs
[0]);
116 unsigned disasm_size
= shader
->binary
.disasm_string
?
117 strlen(shader
->binary
.disasm_string
) + 1 : 0;
118 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
119 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
122 4 + /* CRC32 of the data below */
123 align(sizeof(shader
->config
), 4) +
124 align(sizeof(shader
->info
), 4) +
125 4 + align(shader
->binary
.code_size
, 4) +
126 4 + align(shader
->binary
.rodata_size
, 4) +
127 4 + align(relocs_size
, 4) +
128 4 + align(disasm_size
, 4) +
129 4 + align(llvm_ir_size
, 4);
130 void *buffer
= CALLOC(1, size
);
131 uint32_t *ptr
= (uint32_t*)buffer
;
137 ptr
++; /* CRC32 is calculated at the end. */
139 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
140 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
141 ptr
= write_chunk(ptr
, shader
->binary
.code
, shader
->binary
.code_size
);
142 ptr
= write_chunk(ptr
, shader
->binary
.rodata
, shader
->binary
.rodata_size
);
143 ptr
= write_chunk(ptr
, shader
->binary
.relocs
, relocs_size
);
144 ptr
= write_chunk(ptr
, shader
->binary
.disasm_string
, disasm_size
);
145 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
146 assert((char *)ptr
- (char *)buffer
== size
);
149 ptr
= (uint32_t*)buffer
;
151 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
156 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
158 uint32_t *ptr
= (uint32_t*)binary
;
159 uint32_t size
= *ptr
++;
160 uint32_t crc32
= *ptr
++;
163 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
164 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
168 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
169 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
170 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.code
,
171 &shader
->binary
.code_size
);
172 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.rodata
,
173 &shader
->binary
.rodata_size
);
174 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.relocs
, &chunk_size
);
175 shader
->binary
.reloc_count
= chunk_size
/ sizeof(shader
->binary
.relocs
[0]);
176 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.disasm_string
, &chunk_size
);
177 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
183 * Insert a shader into the cache. It's assumed the shader is not in the cache.
184 * Use si_shader_cache_load_shader before calling this.
186 * Returns false on failure, in which case the tgsi_binary should be freed.
188 static bool si_shader_cache_insert_shader(struct si_screen
*sscreen
,
190 struct si_shader
*shader
,
191 bool insert_into_disk_cache
)
194 struct hash_entry
*entry
;
195 uint8_t key
[CACHE_KEY_SIZE
];
197 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, tgsi_binary
);
199 return false; /* already added */
201 hw_binary
= si_get_shader_binary(shader
);
205 if (_mesa_hash_table_insert(sscreen
->shader_cache
, tgsi_binary
,
206 hw_binary
) == NULL
) {
211 if (sscreen
->b
.disk_shader_cache
&& insert_into_disk_cache
) {
212 disk_cache_compute_key(sscreen
->b
.disk_shader_cache
, tgsi_binary
,
213 *((uint32_t *)tgsi_binary
), key
);
214 disk_cache_put(sscreen
->b
.disk_shader_cache
, key
, hw_binary
,
215 *((uint32_t *) hw_binary
));
221 static bool si_shader_cache_load_shader(struct si_screen
*sscreen
,
223 struct si_shader
*shader
)
225 struct hash_entry
*entry
=
226 _mesa_hash_table_search(sscreen
->shader_cache
, tgsi_binary
);
228 if (sscreen
->b
.disk_shader_cache
) {
229 unsigned char sha1
[CACHE_KEY_SIZE
];
230 size_t tg_size
= *((uint32_t *) tgsi_binary
);
232 disk_cache_compute_key(sscreen
->b
.disk_shader_cache
,
233 tgsi_binary
, tg_size
, sha1
);
237 disk_cache_get(sscreen
->b
.disk_shader_cache
,
242 if (binary_size
< sizeof(uint32_t) ||
243 *((uint32_t*)buffer
) != binary_size
) {
244 /* Something has gone wrong discard the item
245 * from the cache and rebuild/link from
248 assert(!"Invalid radeonsi shader disk cache "
251 disk_cache_remove(sscreen
->b
.disk_shader_cache
,
258 if (!si_load_shader_binary(shader
, buffer
)) {
264 if (!si_shader_cache_insert_shader(sscreen
, tgsi_binary
,
271 if (si_load_shader_binary(shader
, entry
->data
))
276 p_atomic_inc(&sscreen
->b
.num_shader_cache_hits
);
280 static uint32_t si_shader_cache_key_hash(const void *key
)
282 /* The first dword is the key size. */
283 return util_hash_crc32(key
, *(uint32_t*)key
);
286 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
288 uint32_t *keya
= (uint32_t*)a
;
289 uint32_t *keyb
= (uint32_t*)b
;
291 /* The first dword is the key size. */
295 return memcmp(keya
, keyb
, *keya
) == 0;
298 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
300 FREE((void*)entry
->key
);
304 bool si_init_shader_cache(struct si_screen
*sscreen
)
306 (void) mtx_init(&sscreen
->shader_cache_mutex
, mtx_plain
);
307 sscreen
->shader_cache
=
308 _mesa_hash_table_create(NULL
,
309 si_shader_cache_key_hash
,
310 si_shader_cache_key_equals
);
312 return sscreen
->shader_cache
!= NULL
;
315 void si_destroy_shader_cache(struct si_screen
*sscreen
)
317 if (sscreen
->shader_cache
)
318 _mesa_hash_table_destroy(sscreen
->shader_cache
,
319 si_destroy_shader_cache_entry
);
320 mtx_destroy(&sscreen
->shader_cache_mutex
);
325 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
326 struct si_shader
*shader
,
327 struct si_pm4_state
*pm4
)
329 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
330 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
331 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
332 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
333 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
334 unsigned type
, partitioning
, topology
, distribution_mode
;
336 switch (tes_prim_mode
) {
337 case PIPE_PRIM_LINES
:
338 type
= V_028B6C_TESS_ISOLINE
;
340 case PIPE_PRIM_TRIANGLES
:
341 type
= V_028B6C_TESS_TRIANGLE
;
343 case PIPE_PRIM_QUADS
:
344 type
= V_028B6C_TESS_QUAD
;
351 switch (tes_spacing
) {
352 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
353 partitioning
= V_028B6C_PART_FRAC_ODD
;
355 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
356 partitioning
= V_028B6C_PART_FRAC_EVEN
;
358 case PIPE_TESS_SPACING_EQUAL
:
359 partitioning
= V_028B6C_PART_INTEGER
;
367 topology
= V_028B6C_OUTPUT_POINT
;
368 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
369 topology
= V_028B6C_OUTPUT_LINE
;
370 else if (tes_vertex_order_cw
)
371 /* for some reason, this must be the other way around */
372 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
374 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
376 if (sscreen
->has_distributed_tess
) {
377 if (sscreen
->b
.family
== CHIP_FIJI
||
378 sscreen
->b
.family
>= CHIP_POLARIS10
)
379 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
381 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
383 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
385 si_pm4_set_reg(pm4
, R_028B6C_VGT_TF_PARAM
,
386 S_028B6C_TYPE(type
) |
387 S_028B6C_PARTITIONING(partitioning
) |
388 S_028B6C_TOPOLOGY(topology
) |
389 S_028B6C_DISTRIBUTION_MODE(distribution_mode
));
392 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
393 * whether the "fractional odd" tessellation spacing is used.
395 * Possible VGT configurations and which state should set the register:
397 * Reg set in | VGT shader configuration | Value
398 * ------------------------------------------------------
400 * VS as ES | ES -> GS -> VS | 30
401 * TES as VS | LS -> HS -> VS | 14 or 30
402 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
404 static void polaris_set_vgt_vertex_reuse(struct si_screen
*sscreen
,
405 struct si_shader
*shader
,
406 struct si_pm4_state
*pm4
)
408 unsigned type
= shader
->selector
->type
;
410 if (sscreen
->b
.family
< CHIP_POLARIS10
)
413 /* VS as VS, or VS as ES: */
414 if ((type
== PIPE_SHADER_VERTEX
&&
415 !shader
->key
.as_ls
&&
416 !shader
->is_gs_copy_shader
) ||
417 /* TES as VS, or TES as ES: */
418 type
== PIPE_SHADER_TESS_EVAL
) {
419 unsigned vtx_reuse_depth
= 30;
421 if (type
== PIPE_SHADER_TESS_EVAL
&&
422 shader
->selector
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] ==
423 PIPE_TESS_SPACING_FRACTIONAL_ODD
)
424 vtx_reuse_depth
= 14;
426 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
431 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
434 si_pm4_clear_state(shader
->pm4
);
436 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
441 static void si_shader_ls(struct si_screen
*sscreen
, struct si_shader
*shader
)
443 struct si_pm4_state
*pm4
;
444 unsigned vgpr_comp_cnt
;
447 assert(sscreen
->b
.chip_class
<= VI
);
449 pm4
= si_get_shader_pm4_state(shader
);
453 va
= shader
->bo
->gpu_address
;
454 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
456 /* We need at least 2 components for LS.
457 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
458 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 3 : 1;
460 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
461 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, va
>> 40);
463 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
464 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
465 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt
) |
466 S_00B528_DX10_CLAMP(1) |
467 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
468 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(SI_VS_NUM_USER_SGPR
) |
469 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
472 static void si_shader_hs(struct si_screen
*sscreen
, struct si_shader
*shader
)
474 struct si_pm4_state
*pm4
;
477 pm4
= si_get_shader_pm4_state(shader
);
481 va
= shader
->bo
->gpu_address
;
482 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
484 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
485 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, va
>> 40);
486 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
487 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
488 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
489 S_00B428_DX10_CLAMP(1) |
490 S_00B428_FLOAT_MODE(shader
->config
.float_mode
));
491 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
492 S_00B42C_USER_SGPR(SI_TCS_NUM_USER_SGPR
) |
493 S_00B42C_OC_LDS_EN(sscreen
->b
.chip_class
<= VI
) |
494 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
497 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
499 struct si_pm4_state
*pm4
;
500 unsigned num_user_sgprs
;
501 unsigned vgpr_comp_cnt
;
505 assert(sscreen
->b
.chip_class
<= VI
);
507 pm4
= si_get_shader_pm4_state(shader
);
511 va
= shader
->bo
->gpu_address
;
512 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
514 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
515 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 3 : 0;
516 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
517 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
518 vgpr_comp_cnt
= 3; /* all components are needed for TES */
519 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
521 unreachable("invalid shader selector type");
523 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
525 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
526 shader
->selector
->esgs_itemsize
/ 4);
527 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
528 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
529 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
530 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
531 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
532 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
533 S_00B328_DX10_CLAMP(1) |
534 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
535 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
536 S_00B32C_USER_SGPR(num_user_sgprs
) |
537 S_00B32C_OC_LDS_EN(oc_lds_en
) |
538 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
540 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
541 si_set_tesseval_regs(sscreen
, shader
, pm4
);
543 polaris_set_vgt_vertex_reuse(sscreen
, shader
, pm4
);
547 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
550 static uint32_t si_vgt_gs_mode(struct si_shader_selector
*sel
)
552 unsigned gs_max_vert_out
= sel
->gs_max_out_vertices
;
555 if (gs_max_vert_out
<= 128) {
556 cut_mode
= V_028A40_GS_CUT_128
;
557 } else if (gs_max_vert_out
<= 256) {
558 cut_mode
= V_028A40_GS_CUT_256
;
559 } else if (gs_max_vert_out
<= 512) {
560 cut_mode
= V_028A40_GS_CUT_512
;
562 assert(gs_max_vert_out
<= 1024);
563 cut_mode
= V_028A40_GS_CUT_1024
;
566 return S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
567 S_028A40_CUT_MODE(cut_mode
)|
568 S_028A40_ES_WRITE_OPTIMIZE(1) |
569 S_028A40_GS_WRITE_OPTIMIZE(1);
572 static void si_shader_gs(struct si_shader
*shader
)
574 struct si_shader_selector
*sel
= shader
->selector
;
575 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
576 unsigned gs_num_invocations
= sel
->gs_num_invocations
;
577 struct si_pm4_state
*pm4
;
579 unsigned max_stream
= sel
->max_gs_stream
;
582 pm4
= si_get_shader_pm4_state(shader
);
586 offset
= num_components
[0] * sel
->gs_max_out_vertices
;
587 si_pm4_set_reg(pm4
, R_028A60_VGT_GSVS_RING_OFFSET_1
, offset
);
589 offset
+= num_components
[1] * sel
->gs_max_out_vertices
;
590 si_pm4_set_reg(pm4
, R_028A64_VGT_GSVS_RING_OFFSET_2
, offset
);
592 offset
+= num_components
[2] * sel
->gs_max_out_vertices
;
593 si_pm4_set_reg(pm4
, R_028A68_VGT_GSVS_RING_OFFSET_3
, offset
);
595 offset
+= num_components
[3] * sel
->gs_max_out_vertices
;
596 si_pm4_set_reg(pm4
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
598 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
599 assert(offset
< (1 << 15));
601 si_pm4_set_reg(pm4
, R_028B38_VGT_GS_MAX_VERT_OUT
, shader
->selector
->gs_max_out_vertices
);
603 si_pm4_set_reg(pm4
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, num_components
[0]);
604 si_pm4_set_reg(pm4
, R_028B60_VGT_GS_VERT_ITEMSIZE_1
, (max_stream
>= 1) ? num_components
[1] : 0);
605 si_pm4_set_reg(pm4
, R_028B64_VGT_GS_VERT_ITEMSIZE_2
, (max_stream
>= 2) ? num_components
[2] : 0);
606 si_pm4_set_reg(pm4
, R_028B68_VGT_GS_VERT_ITEMSIZE_3
, (max_stream
>= 3) ? num_components
[3] : 0);
608 si_pm4_set_reg(pm4
, R_028B90_VGT_GS_INSTANCE_CNT
,
609 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
610 S_028B90_ENABLE(gs_num_invocations
> 0));
612 va
= shader
->bo
->gpu_address
;
613 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
614 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
615 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, va
>> 40);
617 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
618 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
619 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
620 S_00B228_DX10_CLAMP(1) |
621 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
622 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
623 S_00B22C_USER_SGPR(SI_GS_NUM_USER_SGPR
) |
624 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
628 * Compute the state for \p shader, which will run as a vertex shader on the
631 * If \p gs is non-NULL, it points to the geometry shader for which this shader
632 * is the copy shader.
634 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
635 struct si_shader_selector
*gs
)
637 struct si_pm4_state
*pm4
;
638 unsigned num_user_sgprs
;
639 unsigned nparams
, vgpr_comp_cnt
;
642 unsigned window_space
=
643 shader
->selector
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
644 bool enable_prim_id
= si_vs_exports_prim_id(shader
);
646 pm4
= si_get_shader_pm4_state(shader
);
650 /* We always write VGT_GS_MODE in the VS state, because every switch
651 * between different shader pipelines involving a different GS or no
652 * GS at all involves a switch of the VS (different GS use different
653 * copy shaders). On the other hand, when the API switches from a GS to
654 * no GS and then back to the same GS used originally, the GS state is
658 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
,
659 S_028A40_MODE(enable_prim_id
? V_028A40_GS_SCENARIO_A
: 0));
660 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, enable_prim_id
);
662 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, si_vgt_gs_mode(gs
));
663 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
666 va
= shader
->bo
->gpu_address
;
667 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
670 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
671 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
672 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
673 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 3 : (enable_prim_id
? 2 : 0);
674 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
675 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
676 vgpr_comp_cnt
= 3; /* all components are needed for TES */
677 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
679 unreachable("invalid shader selector type");
681 /* VS is required to export at least one param. */
682 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
683 si_pm4_set_reg(pm4
, R_0286C4_SPI_VS_OUT_CONFIG
,
684 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
686 si_pm4_set_reg(pm4
, R_02870C_SPI_SHADER_POS_FORMAT
,
687 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
688 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
689 V_02870C_SPI_SHADER_4COMP
:
690 V_02870C_SPI_SHADER_NONE
) |
691 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
692 V_02870C_SPI_SHADER_4COMP
:
693 V_02870C_SPI_SHADER_NONE
) |
694 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
695 V_02870C_SPI_SHADER_4COMP
:
696 V_02870C_SPI_SHADER_NONE
));
698 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
700 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
701 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, va
>> 40);
702 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
703 S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
704 S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
705 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
706 S_00B128_DX10_CLAMP(1) |
707 S_00B128_FLOAT_MODE(shader
->config
.float_mode
));
708 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
709 S_00B12C_USER_SGPR(num_user_sgprs
) |
710 S_00B12C_OC_LDS_EN(oc_lds_en
) |
711 S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
712 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
713 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
714 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
715 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
) |
716 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
718 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
719 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
721 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
722 S_028818_VTX_W0_FMT(1) |
723 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
724 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
725 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
727 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
728 si_set_tesseval_regs(sscreen
, shader
, pm4
);
730 polaris_set_vgt_vertex_reuse(sscreen
, shader
, pm4
);
733 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
735 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
736 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
737 !!(info
->colors_read
& 0xf0);
738 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
739 (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
741 assert(num_interp
<= 32);
742 return MIN2(num_interp
, 32);
745 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
747 unsigned value
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
748 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
750 /* If the i-th target format is set, all previous target formats must
751 * be non-zero to avoid hangs.
753 for (i
= 0; i
< num_targets
; i
++)
754 if (!(value
& (0xf << (i
* 4))))
755 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
760 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format
)
762 unsigned i
, cb_shader_mask
= 0;
764 for (i
= 0; i
< 8; i
++) {
765 switch ((spi_shader_col_format
>> (i
* 4)) & 0xf) {
766 case V_028714_SPI_SHADER_ZERO
:
768 case V_028714_SPI_SHADER_32_R
:
769 cb_shader_mask
|= 0x1 << (i
* 4);
771 case V_028714_SPI_SHADER_32_GR
:
772 cb_shader_mask
|= 0x3 << (i
* 4);
774 case V_028714_SPI_SHADER_32_AR
:
775 cb_shader_mask
|= 0x9 << (i
* 4);
777 case V_028714_SPI_SHADER_FP16_ABGR
:
778 case V_028714_SPI_SHADER_UNORM16_ABGR
:
779 case V_028714_SPI_SHADER_SNORM16_ABGR
:
780 case V_028714_SPI_SHADER_UINT16_ABGR
:
781 case V_028714_SPI_SHADER_SINT16_ABGR
:
782 case V_028714_SPI_SHADER_32_ABGR
:
783 cb_shader_mask
|= 0xf << (i
* 4);
789 return cb_shader_mask
;
792 static void si_shader_ps(struct si_shader
*shader
)
794 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
795 struct si_pm4_state
*pm4
;
796 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
797 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
799 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
801 /* we need to enable at least one of them, otherwise we hang the GPU */
802 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
803 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
804 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
805 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
806 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
807 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
808 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
809 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
810 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
811 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
812 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
813 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
814 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
815 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
817 /* Validate interpolation optimization flags (read as implications). */
818 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
819 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
820 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
821 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
822 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
823 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
824 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
825 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
826 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
827 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
828 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
829 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
830 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
831 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
832 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
833 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
834 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
835 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
837 /* Validate cases when the optimizations are off (read as implications). */
838 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
839 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
840 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
841 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
842 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
843 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
845 pm4
= si_get_shader_pm4_state(shader
);
849 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
851 * 0 -> Position = pixel center
852 * 1 -> Position = pixel centroid
853 * 2 -> Position = at sample position
855 * From GLSL 4.5 specification, section 7.1:
856 * "The variable gl_FragCoord is available as an input variable from
857 * within fragment shaders and it holds the window relative coordinates
858 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
859 * value can be for any location within the pixel, or one of the
860 * fragment samples. The use of centroid does not further restrict
861 * this value to be inside the current primitive."
863 * Meaning that centroid has no effect and we can return anything within
864 * the pixel. Thus, return the value at sample position, because that's
865 * the most accurate one shaders can get.
867 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
869 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
870 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
871 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
873 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
874 cb_shader_mask
= si_get_cb_shader_mask(spi_shader_col_format
);
876 /* Ensure that some export memory is always allocated, for two reasons:
878 * 1) Correctness: The hardware ignores the EXEC mask if no export
879 * memory is allocated, so KILL and alpha test do not work correctly
881 * 2) Performance: Every shader needs at least a NULL export, even when
882 * it writes no color/depth output. The NULL export instruction
883 * stalls without this setting.
885 * Don't add this to CB_SHADER_MASK.
887 if (!spi_shader_col_format
&&
888 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
889 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
891 si_pm4_set_reg(pm4
, R_0286CC_SPI_PS_INPUT_ENA
, input_ena
);
892 si_pm4_set_reg(pm4
, R_0286D0_SPI_PS_INPUT_ADDR
,
893 shader
->config
.spi_ps_input_addr
);
895 /* Set interpolation controls. */
896 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
));
899 si_pm4_set_reg(pm4
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
900 si_pm4_set_reg(pm4
, R_0286D8_SPI_PS_IN_CONTROL
, spi_ps_in_control
);
902 si_pm4_set_reg(pm4
, R_028710_SPI_SHADER_Z_FORMAT
,
903 si_get_spi_shader_z_format(info
->writes_z
,
904 info
->writes_stencil
,
905 info
->writes_samplemask
));
907 si_pm4_set_reg(pm4
, R_028714_SPI_SHADER_COL_FORMAT
, spi_shader_col_format
);
908 si_pm4_set_reg(pm4
, R_02823C_CB_SHADER_MASK
, cb_shader_mask
);
910 va
= shader
->bo
->gpu_address
;
911 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
912 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
913 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, va
>> 40);
915 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
,
916 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
917 S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
918 S_00B028_DX10_CLAMP(1) |
919 S_00B028_FLOAT_MODE(shader
->config
.float_mode
));
920 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
921 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
922 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
923 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
926 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
927 struct si_shader
*shader
)
929 switch (shader
->selector
->type
) {
930 case PIPE_SHADER_VERTEX
:
931 if (shader
->key
.as_ls
)
932 si_shader_ls(sscreen
, shader
);
933 else if (shader
->key
.as_es
)
934 si_shader_es(sscreen
, shader
);
936 si_shader_vs(sscreen
, shader
, NULL
);
938 case PIPE_SHADER_TESS_CTRL
:
939 si_shader_hs(sscreen
, shader
);
941 case PIPE_SHADER_TESS_EVAL
:
942 if (shader
->key
.as_es
)
943 si_shader_es(sscreen
, shader
);
945 si_shader_vs(sscreen
, shader
, NULL
);
947 case PIPE_SHADER_GEOMETRY
:
948 si_shader_gs(shader
);
950 case PIPE_SHADER_FRAGMENT
:
951 si_shader_ps(shader
);
958 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
960 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
961 if (sctx
->queued
.named
.dsa
)
962 return sctx
->queued
.named
.dsa
->alpha_func
;
964 return PIPE_FUNC_ALWAYS
;
967 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
,
968 struct si_shader_selector
*vs
,
969 struct si_shader_key
*key
)
971 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
973 key
->opt
.hw_vs
.clip_disable
=
974 sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
975 (vs
->info
.clipdist_writemask
||
976 vs
->info
.writes_clipvertex
) &&
977 !vs
->info
.culldist_writemask
;
979 /* Find out if PS is disabled. */
980 bool ps_disabled
= true;
982 bool ps_modifies_zs
= ps
->info
.uses_kill
||
984 ps
->info
.writes_stencil
||
985 ps
->info
.writes_samplemask
||
986 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
988 unsigned ps_colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
&
989 sctx
->queued
.named
.blend
->cb_target_mask
;
990 if (!ps
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
])
991 ps_colormask
&= ps
->colors_written_4bit
;
993 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
996 !ps
->info
.writes_memory
);
999 /* Find out which VS outputs aren't used by the PS. */
1000 uint64_t outputs_written
= vs
->outputs_written
;
1001 uint32_t outputs_written2
= vs
->outputs_written2
;
1002 uint64_t inputs_read
= 0;
1003 uint32_t inputs_read2
= 0;
1005 outputs_written
&= ~0x3; /* ignore POSITION, PSIZE */
1008 inputs_read
= ps
->inputs_read
;
1009 inputs_read2
= ps
->inputs_read2
;
1012 uint64_t linked
= outputs_written
& inputs_read
;
1013 uint32_t linked2
= outputs_written2
& inputs_read2
;
1015 key
->opt
.hw_vs
.kill_outputs
= ~linked
& outputs_written
;
1016 key
->opt
.hw_vs
.kill_outputs2
= ~linked2
& outputs_written2
;
1019 /* Compute the key for the hw shader variant */
1020 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
1021 struct si_shader_selector
*sel
,
1022 struct si_shader_key
*key
)
1024 struct si_context
*sctx
= (struct si_context
*)ctx
;
1027 memset(key
, 0, sizeof(*key
));
1029 switch (sel
->type
) {
1030 case PIPE_SHADER_VERTEX
:
1031 if (sctx
->vertex_elements
) {
1032 unsigned count
= MIN2(sel
->info
.num_inputs
,
1033 sctx
->vertex_elements
->count
);
1034 for (i
= 0; i
< count
; ++i
)
1035 key
->part
.vs
.prolog
.instance_divisors
[i
] =
1036 sctx
->vertex_elements
->elements
[i
].instance_divisor
;
1038 memcpy(key
->mono
.vs
.fix_fetch
,
1039 sctx
->vertex_elements
->fix_fetch
, count
);
1041 if (sctx
->tes_shader
.cso
)
1043 else if (sctx
->gs_shader
.cso
)
1046 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1048 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1049 key
->part
.vs
.epilog
.export_prim_id
= 1;
1052 case PIPE_SHADER_TESS_CTRL
:
1053 key
->part
.tcs
.epilog
.prim_mode
=
1054 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1055 key
->part
.tcs
.epilog
.tes_reads_tess_factors
=
1056 sctx
->tes_shader
.cso
->info
.reads_tess_factors
;
1058 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
1059 key
->mono
.tcs
.inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
1061 case PIPE_SHADER_TESS_EVAL
:
1062 if (sctx
->gs_shader
.cso
)
1065 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1067 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1068 key
->part
.tes
.epilog
.export_prim_id
= 1;
1071 case PIPE_SHADER_GEOMETRY
:
1072 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
1074 case PIPE_SHADER_FRAGMENT
: {
1075 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1076 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1078 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
1079 sel
->info
.colors_written
== 0x1)
1080 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
1083 /* Select the shader color format based on whether
1084 * blending or alpha are needed.
1086 key
->part
.ps
.epilog
.spi_shader_col_format
=
1087 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1088 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
1089 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1090 sctx
->framebuffer
.spi_shader_col_format_blend
) |
1091 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1092 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
1093 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1094 sctx
->framebuffer
.spi_shader_col_format
);
1096 /* The output for dual source blending should have
1097 * the same format as the first output.
1099 if (blend
->dual_src_blend
)
1100 key
->part
.ps
.epilog
.spi_shader_col_format
|=
1101 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
1103 key
->part
.ps
.epilog
.spi_shader_col_format
= sctx
->framebuffer
.spi_shader_col_format
;
1105 /* If alpha-to-coverage is enabled, we have to export alpha
1106 * even if there is no color buffer.
1108 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) &&
1109 blend
&& blend
->alpha_to_coverage
)
1110 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
1112 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1113 * to the range supported by the type if a channel has less
1114 * than 16 bits and the export format is 16_ABGR.
1116 if (sctx
->b
.chip_class
<= CIK
&& sctx
->b
.family
!= CHIP_HAWAII
) {
1117 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
1118 key
->part
.ps
.epilog
.color_is_int10
= sctx
->framebuffer
.color_is_int10
;
1121 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1122 if (!key
->part
.ps
.epilog
.last_cbuf
) {
1123 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
1124 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
1125 key
->part
.ps
.epilog
.color_is_int10
&= sel
->info
.colors_written
;
1129 bool is_poly
= (sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES
&&
1130 sctx
->current_rast_prim
<= PIPE_PRIM_POLYGON
) ||
1131 sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES_ADJACENCY
;
1132 bool is_line
= !is_poly
&& sctx
->current_rast_prim
!= PIPE_PRIM_POINTS
;
1134 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
1135 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
1137 if (sctx
->queued
.named
.blend
) {
1138 key
->part
.ps
.epilog
.alpha_to_one
= sctx
->queued
.named
.blend
->alpha_to_one
&&
1139 rs
->multisample_enable
;
1142 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
1143 key
->part
.ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
1144 (is_line
&& rs
->line_smooth
)) &&
1145 sctx
->framebuffer
.nr_samples
<= 1;
1146 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
1148 if (rs
->force_persample_interp
&&
1149 rs
->multisample_enable
&&
1150 sctx
->framebuffer
.nr_samples
> 1 &&
1151 sctx
->ps_iter_samples
> 1) {
1152 key
->part
.ps
.prolog
.force_persp_sample_interp
=
1153 sel
->info
.uses_persp_center
||
1154 sel
->info
.uses_persp_centroid
;
1156 key
->part
.ps
.prolog
.force_linear_sample_interp
=
1157 sel
->info
.uses_linear_center
||
1158 sel
->info
.uses_linear_centroid
;
1159 } else if (rs
->multisample_enable
&&
1160 sctx
->framebuffer
.nr_samples
> 1) {
1161 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
1162 sel
->info
.uses_persp_center
&&
1163 sel
->info
.uses_persp_centroid
;
1164 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
1165 sel
->info
.uses_linear_center
&&
1166 sel
->info
.uses_linear_centroid
;
1168 /* Make sure SPI doesn't compute more than 1 pair
1169 * of (i,j), which is the optimization here. */
1170 key
->part
.ps
.prolog
.force_persp_center_interp
=
1171 sel
->info
.uses_persp_center
+
1172 sel
->info
.uses_persp_centroid
+
1173 sel
->info
.uses_persp_sample
> 1;
1175 key
->part
.ps
.prolog
.force_linear_center_interp
=
1176 sel
->info
.uses_linear_center
+
1177 sel
->info
.uses_linear_centroid
+
1178 sel
->info
.uses_linear_sample
> 1;
1182 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
1190 static void si_build_shader_variant(void *job
, int thread_index
)
1192 struct si_shader
*shader
= (struct si_shader
*)job
;
1193 struct si_shader_selector
*sel
= shader
->selector
;
1194 struct si_screen
*sscreen
= sel
->screen
;
1195 LLVMTargetMachineRef tm
;
1196 struct pipe_debug_callback
*debug
= &shader
->compiler_ctx_state
.debug
;
1199 if (thread_index
>= 0) {
1200 assert(thread_index
< ARRAY_SIZE(sscreen
->tm
));
1201 tm
= sscreen
->tm
[thread_index
];
1205 tm
= shader
->compiler_ctx_state
.tm
;
1208 r
= si_shader_create(sscreen
, tm
, shader
, debug
);
1210 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1212 shader
->compilation_failed
= true;
1216 if (shader
->compiler_ctx_state
.is_debug_context
) {
1217 FILE *f
= open_memstream(&shader
->shader_log
,
1218 &shader
->shader_log_size
);
1220 si_shader_dump(sscreen
, shader
, NULL
, sel
->type
, f
, false);
1225 si_shader_init_pm4_state(sscreen
, shader
);
1228 /* Select the hw shader variant depending on the current state. */
1229 static int si_shader_select_with_key(struct si_screen
*sscreen
,
1230 struct si_shader_ctx_state
*state
,
1231 struct si_compiler_ctx_state
*compiler_state
,
1232 struct si_shader_key
*key
,
1235 static const struct si_shader_key zeroed
;
1236 struct si_shader_selector
*sel
= state
->cso
;
1237 struct si_shader
*current
= state
->current
;
1238 struct si_shader
*iter
, *shader
= NULL
;
1240 if (unlikely(sscreen
->b
.debug_flags
& DBG_NO_OPT_VARIANT
)) {
1241 memset(&key
->opt
, 0, sizeof(key
->opt
));
1245 /* Check if we don't need to change anything.
1246 * This path is also used for most shaders that don't need multiple
1247 * variants, it will cost just a computation of the key and this
1249 if (likely(current
&&
1250 memcmp(¤t
->key
, key
, sizeof(*key
)) == 0 &&
1251 (!current
->is_optimized
||
1252 util_queue_fence_is_signalled(¤t
->optimized_ready
))))
1253 return current
->compilation_failed
? -1 : 0;
1255 /* This must be done before the mutex is locked, because async GS
1256 * compilation calls this function too, and therefore must enter
1259 * Only wait if we are in a draw call. Don't wait if we are
1260 * in a compiler thread.
1262 if (thread_index
< 0)
1263 util_queue_fence_wait(&sel
->ready
);
1265 mtx_lock(&sel
->mutex
);
1267 /* Find the shader variant. */
1268 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
1269 /* Don't check the "current" shader. We checked it above. */
1270 if (current
!= iter
&&
1271 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
1272 /* If it's an optimized shader and its compilation has
1273 * been started but isn't done, use the unoptimized
1274 * shader so as not to cause a stall due to compilation.
1276 if (iter
->is_optimized
&&
1277 !util_queue_fence_is_signalled(&iter
->optimized_ready
)) {
1278 memset(&key
->opt
, 0, sizeof(key
->opt
));
1279 mtx_unlock(&sel
->mutex
);
1283 if (iter
->compilation_failed
) {
1284 mtx_unlock(&sel
->mutex
);
1285 return -1; /* skip the draw call */
1288 state
->current
= iter
;
1289 mtx_unlock(&sel
->mutex
);
1294 /* Build a new shader. */
1295 shader
= CALLOC_STRUCT(si_shader
);
1297 mtx_unlock(&sel
->mutex
);
1300 shader
->selector
= sel
;
1302 shader
->compiler_ctx_state
= *compiler_state
;
1304 /* Compile the main shader part if it doesn't exist. This can happen
1305 * if the initial guess was wrong. */
1306 struct si_shader
**mainp
= si_get_main_shader_part(sel
, key
);
1307 bool is_pure_monolithic
=
1308 sscreen
->use_monolithic_shaders
||
1309 memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
1311 if (!*mainp
&& !is_pure_monolithic
) {
1312 struct si_shader
*main_part
= CALLOC_STRUCT(si_shader
);
1316 mtx_unlock(&sel
->mutex
);
1317 return -ENOMEM
; /* skip the draw call */
1320 main_part
->selector
= sel
;
1321 main_part
->key
.as_es
= key
->as_es
;
1322 main_part
->key
.as_ls
= key
->as_ls
;
1324 if (si_compile_tgsi_shader(sscreen
, compiler_state
->tm
,
1326 &compiler_state
->debug
) != 0) {
1329 mtx_unlock(&sel
->mutex
);
1330 return -ENOMEM
; /* skip the draw call */
1335 /* Monolithic-only shaders don't make a distinction between optimized
1336 * and unoptimized. */
1337 shader
->is_monolithic
=
1338 is_pure_monolithic
||
1339 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1341 shader
->is_optimized
=
1342 !is_pure_monolithic
&&
1343 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1344 if (shader
->is_optimized
)
1345 util_queue_fence_init(&shader
->optimized_ready
);
1347 if (!sel
->last_variant
) {
1348 sel
->first_variant
= shader
;
1349 sel
->last_variant
= shader
;
1351 sel
->last_variant
->next_variant
= shader
;
1352 sel
->last_variant
= shader
;
1355 /* If it's an optimized shader, compile it asynchronously. */
1356 if (shader
->is_optimized
&&
1357 !is_pure_monolithic
&&
1359 /* Compile it asynchronously. */
1360 util_queue_add_job(&sscreen
->shader_compiler_queue
,
1361 shader
, &shader
->optimized_ready
,
1362 si_build_shader_variant
, NULL
);
1364 /* Use the default (unoptimized) shader for now. */
1365 memset(&key
->opt
, 0, sizeof(key
->opt
));
1366 mtx_unlock(&sel
->mutex
);
1370 assert(!shader
->is_optimized
);
1371 si_build_shader_variant(shader
, thread_index
);
1373 if (!shader
->compilation_failed
)
1374 state
->current
= shader
;
1376 mtx_unlock(&sel
->mutex
);
1377 return shader
->compilation_failed
? -1 : 0;
1380 static int si_shader_select(struct pipe_context
*ctx
,
1381 struct si_shader_ctx_state
*state
,
1382 struct si_compiler_ctx_state
*compiler_state
)
1384 struct si_context
*sctx
= (struct si_context
*)ctx
;
1385 struct si_shader_key key
;
1387 si_shader_selector_key(ctx
, state
->cso
, &key
);
1388 return si_shader_select_with_key(sctx
->screen
, state
, compiler_state
,
1392 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
1393 struct si_shader_key
*key
)
1395 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
1397 switch (info
->processor
) {
1398 case PIPE_SHADER_VERTEX
:
1399 switch (next_shader
) {
1400 case PIPE_SHADER_GEOMETRY
:
1403 case PIPE_SHADER_TESS_CTRL
:
1404 case PIPE_SHADER_TESS_EVAL
:
1408 /* If POSITION isn't written, it can't be a HW VS.
1409 * Assume that it's a HW LS. (the next shader is TCS)
1410 * This heuristic is needed for separate shader objects.
1412 if (!info
->writes_position
)
1417 case PIPE_SHADER_TESS_EVAL
:
1418 if (next_shader
== PIPE_SHADER_GEOMETRY
||
1419 !info
->writes_position
)
1426 * Compile the main shader part or the monolithic shader as part of
1427 * si_shader_selector initialization. Since it can be done asynchronously,
1428 * there is no way to report compile failures to applications.
1430 void si_init_shader_selector_async(void *job
, int thread_index
)
1432 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
1433 struct si_screen
*sscreen
= sel
->screen
;
1434 LLVMTargetMachineRef tm
;
1435 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
1438 if (thread_index
>= 0) {
1439 assert(thread_index
< ARRAY_SIZE(sscreen
->tm
));
1440 tm
= sscreen
->tm
[thread_index
];
1444 tm
= sel
->compiler_ctx_state
.tm
;
1447 /* Compile the main shader part for use with a prolog and/or epilog.
1448 * If this fails, the driver will try to compile a monolithic shader
1451 if (!sscreen
->use_monolithic_shaders
) {
1452 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
1456 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
1460 shader
->selector
= sel
;
1461 si_parse_next_shader_property(&sel
->info
, &shader
->key
);
1463 tgsi_binary
= si_get_tgsi_binary(sel
);
1465 /* Try to load the shader from the shader cache. */
1466 mtx_lock(&sscreen
->shader_cache_mutex
);
1469 si_shader_cache_load_shader(sscreen
, tgsi_binary
, shader
)) {
1470 mtx_unlock(&sscreen
->shader_cache_mutex
);
1472 mtx_unlock(&sscreen
->shader_cache_mutex
);
1474 /* Compile the shader if it hasn't been loaded from the cache. */
1475 if (si_compile_tgsi_shader(sscreen
, tm
, shader
, false,
1479 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
1484 mtx_lock(&sscreen
->shader_cache_mutex
);
1485 if (!si_shader_cache_insert_shader(sscreen
, tgsi_binary
, shader
, true))
1487 mtx_unlock(&sscreen
->shader_cache_mutex
);
1491 *si_get_main_shader_part(sel
, &shader
->key
) = shader
;
1493 /* Unset "outputs_written" flags for outputs converted to
1494 * DEFAULT_VAL, so that later inter-shader optimizations don't
1495 * try to eliminate outputs that don't exist in the final
1498 * This is only done if non-monolithic shaders are enabled.
1500 if ((sel
->type
== PIPE_SHADER_VERTEX
||
1501 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
1502 !shader
->key
.as_ls
&&
1503 !shader
->key
.as_es
) {
1506 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
1507 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
1509 if (offset
<= EXP_PARAM_OFFSET_31
)
1512 unsigned name
= sel
->info
.output_semantic_name
[i
];
1513 unsigned index
= sel
->info
.output_semantic_index
[i
];
1517 case TGSI_SEMANTIC_GENERIC
:
1518 /* don't process indices the function can't handle */
1522 case TGSI_SEMANTIC_CLIPDIST
:
1523 id
= si_shader_io_get_unique_index(name
, index
);
1524 sel
->outputs_written
&= ~(1ull << id
);
1526 case TGSI_SEMANTIC_POSITION
: /* ignore these */
1527 case TGSI_SEMANTIC_PSIZE
:
1528 case TGSI_SEMANTIC_CLIPVERTEX
:
1529 case TGSI_SEMANTIC_EDGEFLAG
:
1532 id
= si_shader_io_get_unique_index2(name
, index
);
1533 sel
->outputs_written2
&= ~(1u << id
);
1539 /* Pre-compilation. */
1540 if (sscreen
->b
.debug_flags
& DBG_PRECOMPILE
) {
1541 struct si_shader_ctx_state state
= {sel
};
1542 struct si_shader_key key
;
1544 memset(&key
, 0, sizeof(key
));
1545 si_parse_next_shader_property(&sel
->info
, &key
);
1547 /* Set reasonable defaults, so that the shader key doesn't
1548 * cause any code to be eliminated.
1550 switch (sel
->type
) {
1551 case PIPE_SHADER_TESS_CTRL
:
1552 key
.part
.tcs
.epilog
.prim_mode
= PIPE_PRIM_TRIANGLES
;
1554 case PIPE_SHADER_FRAGMENT
:
1555 key
.part
.ps
.prolog
.bc_optimize_for_persp
=
1556 sel
->info
.uses_persp_center
&&
1557 sel
->info
.uses_persp_centroid
;
1558 key
.part
.ps
.prolog
.bc_optimize_for_linear
=
1559 sel
->info
.uses_linear_center
&&
1560 sel
->info
.uses_linear_centroid
;
1561 key
.part
.ps
.epilog
.alpha_func
= PIPE_FUNC_ALWAYS
;
1562 for (i
= 0; i
< 8; i
++)
1563 if (sel
->info
.colors_written
& (1 << i
))
1564 key
.part
.ps
.epilog
.spi_shader_col_format
|=
1565 V_028710_SPI_SHADER_FP16_ABGR
<< (i
* 4);
1569 if (si_shader_select_with_key(sscreen
, &state
,
1570 &sel
->compiler_ctx_state
, &key
,
1572 fprintf(stderr
, "radeonsi: can't create a monolithic shader\n");
1575 /* The GS copy shader is always pre-compiled. */
1576 if (sel
->type
== PIPE_SHADER_GEOMETRY
) {
1577 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, tm
, sel
, debug
);
1578 if (!sel
->gs_copy_shader
) {
1579 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
1583 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
1587 static void *si_create_shader_selector(struct pipe_context
*ctx
,
1588 const struct pipe_shader_state
*state
)
1590 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
1591 struct si_context
*sctx
= (struct si_context
*)ctx
;
1592 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
1598 sel
->screen
= sscreen
;
1599 sel
->compiler_ctx_state
.tm
= sctx
->tm
;
1600 sel
->compiler_ctx_state
.debug
= sctx
->b
.debug
;
1601 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
1602 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
1608 sel
->so
= state
->stream_output
;
1609 tgsi_scan_shader(state
->tokens
, &sel
->info
);
1610 sel
->type
= sel
->info
.processor
;
1611 p_atomic_inc(&sscreen
->b
.num_shaders_created
);
1613 /* Set which opcode uses which (i,j) pair. */
1614 if (sel
->info
.uses_persp_opcode_interp_centroid
)
1615 sel
->info
.uses_persp_centroid
= true;
1617 if (sel
->info
.uses_linear_opcode_interp_centroid
)
1618 sel
->info
.uses_linear_centroid
= true;
1620 if (sel
->info
.uses_persp_opcode_interp_offset
||
1621 sel
->info
.uses_persp_opcode_interp_sample
)
1622 sel
->info
.uses_persp_center
= true;
1624 if (sel
->info
.uses_linear_opcode_interp_offset
||
1625 sel
->info
.uses_linear_opcode_interp_sample
)
1626 sel
->info
.uses_linear_center
= true;
1628 switch (sel
->type
) {
1629 case PIPE_SHADER_GEOMETRY
:
1630 sel
->gs_output_prim
=
1631 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
1632 sel
->gs_max_out_vertices
=
1633 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
1634 sel
->gs_num_invocations
=
1635 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
1636 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
1637 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
1638 sel
->gs_max_out_vertices
;
1640 sel
->max_gs_stream
= 0;
1641 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
1642 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
1643 sel
->so
.output
[i
].stream
);
1645 sel
->gs_input_verts_per_prim
=
1646 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
1649 case PIPE_SHADER_TESS_CTRL
:
1650 /* Always reserve space for these. */
1651 sel
->patch_outputs_written
|=
1652 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER
, 0)) |
1653 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER
, 0));
1655 case PIPE_SHADER_VERTEX
:
1656 case PIPE_SHADER_TESS_EVAL
:
1657 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
1658 unsigned name
= sel
->info
.output_semantic_name
[i
];
1659 unsigned index
= sel
->info
.output_semantic_index
[i
];
1662 case TGSI_SEMANTIC_TESSINNER
:
1663 case TGSI_SEMANTIC_TESSOUTER
:
1664 case TGSI_SEMANTIC_PATCH
:
1665 sel
->patch_outputs_written
|=
1666 1llu << si_shader_io_get_unique_index(name
, index
);
1669 case TGSI_SEMANTIC_GENERIC
:
1670 /* don't process indices the function can't handle */
1674 case TGSI_SEMANTIC_POSITION
:
1675 case TGSI_SEMANTIC_PSIZE
:
1676 case TGSI_SEMANTIC_CLIPDIST
:
1677 sel
->outputs_written
|=
1678 1llu << si_shader_io_get_unique_index(name
, index
);
1680 case TGSI_SEMANTIC_CLIPVERTEX
: /* ignore these */
1681 case TGSI_SEMANTIC_EDGEFLAG
:
1684 sel
->outputs_written2
|=
1685 1u << si_shader_io_get_unique_index2(name
, index
);
1688 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
1691 case PIPE_SHADER_FRAGMENT
:
1692 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
1693 unsigned name
= sel
->info
.input_semantic_name
[i
];
1694 unsigned index
= sel
->info
.input_semantic_index
[i
];
1697 case TGSI_SEMANTIC_CLIPDIST
:
1698 case TGSI_SEMANTIC_GENERIC
:
1700 1llu << si_shader_io_get_unique_index(name
, index
);
1702 case TGSI_SEMANTIC_PCOORD
: /* ignore this */
1705 sel
->inputs_read2
|=
1706 1u << si_shader_io_get_unique_index2(name
, index
);
1710 for (i
= 0; i
< 8; i
++)
1711 if (sel
->info
.colors_written
& (1 << i
))
1712 sel
->colors_written_4bit
|= 0xf << (4 * i
);
1714 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
1715 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
1716 int index
= sel
->info
.input_semantic_index
[i
];
1717 sel
->color_attr_index
[index
] = i
;
1723 /* DB_SHADER_CONTROL */
1724 sel
->db_shader_control
=
1725 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
1726 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
1727 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
1728 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
1730 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
1731 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
1732 sel
->db_shader_control
|=
1733 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
1735 case TGSI_FS_DEPTH_LAYOUT_LESS
:
1736 sel
->db_shader_control
|=
1737 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
1741 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
1743 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
1744 * --|-----------|------------|------------|--------------------|-------------------|-------------
1745 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
1746 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
1747 * 2 | false | true | n/a | LateZ | 1 | 0
1748 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
1749 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
1751 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
1752 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
1754 * Don't use ReZ without profiling !!!
1756 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
1759 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
1761 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
1762 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
1763 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
1764 } else if (sel
->info
.writes_memory
) {
1766 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) |
1767 S_02880C_EXEC_ON_HIER_FAIL(1);
1770 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
1773 (void) mtx_init(&sel
->mutex
, mtx_plain
);
1774 util_queue_fence_init(&sel
->ready
);
1776 if ((sctx
->b
.debug
.debug_message
&& !sctx
->b
.debug
.async
) ||
1778 r600_can_dump_shader(&sscreen
->b
, sel
->info
.processor
))
1779 si_init_shader_selector_async(sel
, -1);
1781 util_queue_add_job(&sscreen
->shader_compiler_queue
, sel
,
1782 &sel
->ready
, si_init_shader_selector_async
,
1788 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
1790 struct si_context
*sctx
= (struct si_context
*)ctx
;
1791 struct si_shader_selector
*sel
= state
;
1793 if (sctx
->vs_shader
.cso
== sel
)
1796 sctx
->vs_shader
.cso
= sel
;
1797 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
1798 sctx
->do_update_shaders
= true;
1799 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
1800 r600_update_vs_writes_viewport_index(&sctx
->b
, si_get_vs_info(sctx
));
1803 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
1805 struct si_context
*sctx
= (struct si_context
*)ctx
;
1806 struct si_shader_selector
*sel
= state
;
1807 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
1809 if (sctx
->gs_shader
.cso
== sel
)
1812 sctx
->gs_shader
.cso
= sel
;
1813 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
1814 sctx
->ia_multi_vgt_param_key
.u
.uses_gs
= sel
!= NULL
;
1815 sctx
->do_update_shaders
= true;
1816 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
1817 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
1820 si_shader_change_notify(sctx
);
1821 r600_update_vs_writes_viewport_index(&sctx
->b
, si_get_vs_info(sctx
));
1824 static void si_update_tcs_tes_uses_prim_id(struct si_context
*sctx
)
1826 sctx
->ia_multi_vgt_param_key
.u
.tcs_tes_uses_prim_id
=
1827 (sctx
->tes_shader
.cso
&&
1828 sctx
->tes_shader
.cso
->info
.uses_primid
) ||
1829 (sctx
->tcs_shader
.cso
&&
1830 sctx
->tcs_shader
.cso
->info
.uses_primid
);
1833 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
1835 struct si_context
*sctx
= (struct si_context
*)ctx
;
1836 struct si_shader_selector
*sel
= state
;
1837 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
1839 if (sctx
->tcs_shader
.cso
== sel
)
1842 sctx
->tcs_shader
.cso
= sel
;
1843 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
1844 si_update_tcs_tes_uses_prim_id(sctx
);
1845 sctx
->do_update_shaders
= true;
1848 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
1851 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
1853 struct si_context
*sctx
= (struct si_context
*)ctx
;
1854 struct si_shader_selector
*sel
= state
;
1855 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
1857 if (sctx
->tes_shader
.cso
== sel
)
1860 sctx
->tes_shader
.cso
= sel
;
1861 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
1862 sctx
->ia_multi_vgt_param_key
.u
.uses_tess
= sel
!= NULL
;
1863 si_update_tcs_tes_uses_prim_id(sctx
);
1864 sctx
->do_update_shaders
= true;
1865 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
1866 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
1868 if (enable_changed
) {
1869 si_shader_change_notify(sctx
);
1870 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
1872 r600_update_vs_writes_viewport_index(&sctx
->b
, si_get_vs_info(sctx
));
1875 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
1877 struct si_context
*sctx
= (struct si_context
*)ctx
;
1878 struct si_shader_selector
*sel
= state
;
1880 /* skip if supplied shader is one already in use */
1881 if (sctx
->ps_shader
.cso
== sel
)
1884 sctx
->ps_shader
.cso
= sel
;
1885 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
1886 sctx
->do_update_shaders
= true;
1887 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
1890 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
1892 if (shader
->is_optimized
) {
1893 util_queue_fence_wait(&shader
->optimized_ready
);
1894 util_queue_fence_destroy(&shader
->optimized_ready
);
1898 switch (shader
->selector
->type
) {
1899 case PIPE_SHADER_VERTEX
:
1900 if (shader
->key
.as_ls
) {
1901 assert(sctx
->b
.chip_class
<= VI
);
1902 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
1903 } else if (shader
->key
.as_es
) {
1904 assert(sctx
->b
.chip_class
<= VI
);
1905 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
1907 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
1910 case PIPE_SHADER_TESS_CTRL
:
1911 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
1913 case PIPE_SHADER_TESS_EVAL
:
1914 if (shader
->key
.as_es
) {
1915 assert(sctx
->b
.chip_class
<= VI
);
1916 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
1918 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
1921 case PIPE_SHADER_GEOMETRY
:
1922 if (shader
->is_gs_copy_shader
)
1923 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
1925 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
1927 case PIPE_SHADER_FRAGMENT
:
1928 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
1933 si_shader_destroy(shader
);
1937 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
1939 struct si_context
*sctx
= (struct si_context
*)ctx
;
1940 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
1941 struct si_shader
*p
= sel
->first_variant
, *c
;
1942 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
1943 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
1944 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
1945 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
1946 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
1947 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
1950 util_queue_fence_wait(&sel
->ready
);
1952 if (current_shader
[sel
->type
]->cso
== sel
) {
1953 current_shader
[sel
->type
]->cso
= NULL
;
1954 current_shader
[sel
->type
]->current
= NULL
;
1958 c
= p
->next_variant
;
1959 si_delete_shader(sctx
, p
);
1963 if (sel
->main_shader_part
)
1964 si_delete_shader(sctx
, sel
->main_shader_part
);
1965 if (sel
->main_shader_part_ls
)
1966 si_delete_shader(sctx
, sel
->main_shader_part_ls
);
1967 if (sel
->main_shader_part_es
)
1968 si_delete_shader(sctx
, sel
->main_shader_part_es
);
1969 if (sel
->gs_copy_shader
)
1970 si_delete_shader(sctx
, sel
->gs_copy_shader
);
1972 util_queue_fence_destroy(&sel
->ready
);
1973 mtx_destroy(&sel
->mutex
);
1978 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
1979 struct si_shader
*vs
, unsigned name
,
1980 unsigned index
, unsigned interpolate
)
1982 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
1983 unsigned j
, offset
, ps_input_cntl
= 0;
1985 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
1986 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
))
1987 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
1989 if (name
== TGSI_SEMANTIC_PCOORD
||
1990 (name
== TGSI_SEMANTIC_TEXCOORD
&&
1991 sctx
->sprite_coord_enable
& (1 << index
))) {
1992 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
1995 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
1996 if (name
== vsinfo
->output_semantic_name
[j
] &&
1997 index
== vsinfo
->output_semantic_index
[j
]) {
1998 offset
= vs
->info
.vs_output_param_offset
[j
];
2000 if (offset
<= EXP_PARAM_OFFSET_31
) {
2001 /* The input is loaded from parameter memory. */
2002 ps_input_cntl
|= S_028644_OFFSET(offset
);
2003 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2004 if (offset
== EXP_PARAM_UNDEFINED
) {
2005 /* This can happen with depth-only rendering. */
2008 /* The input is a DEFAULT_VAL constant. */
2009 assert(offset
>= EXP_PARAM_DEFAULT_VAL_0000
&&
2010 offset
<= EXP_PARAM_DEFAULT_VAL_1111
);
2011 offset
-= EXP_PARAM_DEFAULT_VAL_0000
;
2014 ps_input_cntl
= S_028644_OFFSET(0x20) |
2015 S_028644_DEFAULT_VAL(offset
);
2021 if (name
== TGSI_SEMANTIC_PRIMID
)
2022 /* PrimID is written after the last output. */
2023 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
2024 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2025 /* No corresponding output found, load defaults into input.
2026 * Don't set any other bits.
2027 * (FLAT_SHADE=1 completely changes behavior) */
2028 ps_input_cntl
= S_028644_OFFSET(0x20);
2029 /* D3D 9 behaviour. GL is undefined */
2030 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
2031 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
2033 return ps_input_cntl
;
2036 static void si_emit_spi_map(struct si_context
*sctx
, struct r600_atom
*atom
)
2038 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2039 struct si_shader
*ps
= sctx
->ps_shader
.current
;
2040 struct si_shader
*vs
= si_get_vs_state(sctx
);
2041 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
2042 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
2044 if (!ps
|| !ps
->selector
->info
.num_inputs
)
2047 num_interp
= si_get_ps_num_interp(ps
);
2048 assert(num_interp
> 0);
2049 radeon_set_context_reg_seq(cs
, R_028644_SPI_PS_INPUT_CNTL_0
, num_interp
);
2051 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
2052 unsigned name
= psinfo
->input_semantic_name
[i
];
2053 unsigned index
= psinfo
->input_semantic_index
[i
];
2054 unsigned interpolate
= psinfo
->input_interpolate
[i
];
2056 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, name
, index
,
2060 if (name
== TGSI_SEMANTIC_COLOR
) {
2061 assert(index
< ARRAY_SIZE(bcol_interp
));
2062 bcol_interp
[index
] = interpolate
;
2066 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
2067 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
2069 for (i
= 0; i
< 2; i
++) {
2070 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
2073 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, bcol
,
2074 i
, bcol_interp
[i
]));
2078 assert(num_interp
== num_written
);
2082 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2084 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
2086 if (sctx
->init_config_has_vgt_flush
)
2089 /* Done by Vulkan before VGT_FLUSH. */
2090 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2091 si_pm4_cmd_add(sctx
->init_config
,
2092 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2093 si_pm4_cmd_end(sctx
->init_config
, false);
2095 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2096 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2097 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
2098 si_pm4_cmd_end(sctx
->init_config
, false);
2099 sctx
->init_config_has_vgt_flush
= true;
2102 /* Initialize state related to ESGS / GSVS ring buffers */
2103 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
2105 struct si_shader_selector
*es
=
2106 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
2107 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
2108 struct si_pm4_state
*pm4
;
2110 /* Chip constants. */
2111 unsigned num_se
= sctx
->screen
->b
.info
.max_se
;
2112 unsigned wave_size
= 64;
2113 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
2114 unsigned gs_vertex_reuse
= 16 * num_se
; /* GS_VERTEX_REUSE register (per SE) */
2115 unsigned alignment
= 256 * num_se
;
2116 /* The maximum size is 63.999 MB per SE. */
2117 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
2119 /* Calculate the minimum size. */
2120 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
2121 wave_size
, alignment
);
2123 /* These are recommended sizes, not minimum sizes. */
2124 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
2125 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
2126 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
2127 gs
->max_gsvs_emit_size
;
2129 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
2130 esgs_ring_size
= align(esgs_ring_size
, alignment
);
2131 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
2133 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
2134 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
2136 /* Some rings don't have to be allocated if shaders don't use them.
2137 * (e.g. no varyings between ES and GS or GS and VS)
2139 * GFX9 doesn't have the ESGS ring.
2141 bool update_esgs
= sctx
->b
.chip_class
<= VI
&&
2143 (!sctx
->esgs_ring
||
2144 sctx
->esgs_ring
->width0
< esgs_ring_size
);
2145 bool update_gsvs
= gsvs_ring_size
&&
2146 (!sctx
->gsvs_ring
||
2147 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
2149 if (!update_esgs
&& !update_gsvs
)
2153 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
2155 r600_aligned_buffer_create(sctx
->b
.b
.screen
,
2156 R600_RESOURCE_FLAG_UNMAPPABLE
,
2158 esgs_ring_size
, alignment
);
2159 if (!sctx
->esgs_ring
)
2164 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
2166 r600_aligned_buffer_create(sctx
->b
.b
.screen
,
2167 R600_RESOURCE_FLAG_UNMAPPABLE
,
2169 gsvs_ring_size
, alignment
);
2170 if (!sctx
->gsvs_ring
)
2174 /* Create the "init_config_gs_rings" state. */
2175 pm4
= CALLOC_STRUCT(si_pm4_state
);
2179 if (sctx
->b
.chip_class
>= CIK
) {
2180 if (sctx
->esgs_ring
) {
2181 assert(sctx
->b
.chip_class
<= VI
);
2182 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
2183 sctx
->esgs_ring
->width0
/ 256);
2185 if (sctx
->gsvs_ring
)
2186 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
2187 sctx
->gsvs_ring
->width0
/ 256);
2189 if (sctx
->esgs_ring
)
2190 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
2191 sctx
->esgs_ring
->width0
/ 256);
2192 if (sctx
->gsvs_ring
)
2193 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
2194 sctx
->gsvs_ring
->width0
/ 256);
2197 /* Set the state. */
2198 if (sctx
->init_config_gs_rings
)
2199 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
2200 sctx
->init_config_gs_rings
= pm4
;
2202 if (!sctx
->init_config_has_vgt_flush
) {
2203 si_init_config_add_vgt_flush(sctx
);
2204 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
2207 /* Flush the context to re-emit both init_config states. */
2208 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
2209 si_context_gfx_flush(sctx
, RADEON_FLUSH_ASYNC
, NULL
);
2211 /* Set ring bindings. */
2212 if (sctx
->esgs_ring
) {
2213 assert(sctx
->b
.chip_class
<= VI
);
2214 si_set_ring_buffer(&sctx
->b
.b
, SI_ES_RING_ESGS
,
2215 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
2216 true, true, 4, 64, 0);
2217 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_ESGS
,
2218 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
2219 false, false, 0, 0, 0);
2221 if (sctx
->gsvs_ring
) {
2222 si_set_ring_buffer(&sctx
->b
.b
, SI_RING_GSVS
,
2223 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
2224 false, false, 0, 0, 0);
2231 * @returns 1 if \p sel has been updated to use a new scratch buffer
2233 * < 0 if there was a failure
2235 static int si_update_scratch_buffer(struct si_context
*sctx
,
2236 struct si_shader
*shader
)
2238 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
2244 /* This shader doesn't need a scratch buffer */
2245 if (shader
->config
.scratch_bytes_per_wave
== 0)
2248 /* This shader is already configured to use the current
2249 * scratch buffer. */
2250 if (shader
->scratch_bo
== sctx
->scratch_buffer
)
2253 assert(sctx
->scratch_buffer
);
2255 si_shader_apply_scratch_relocs(sctx
, shader
, &shader
->config
, scratch_va
);
2257 /* Replace the shader bo with a new bo that has the relocs applied. */
2258 r
= si_shader_binary_upload(sctx
->screen
, shader
);
2262 /* Update the shader state to use the new shader bo. */
2263 si_shader_init_pm4_state(sctx
->screen
, shader
);
2265 r600_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
2270 static unsigned si_get_current_scratch_buffer_size(struct si_context
*sctx
)
2272 return sctx
->scratch_buffer
? sctx
->scratch_buffer
->b
.b
.width0
: 0;
2275 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
2277 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
2280 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context
*sctx
)
2284 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
2285 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
2286 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
2287 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tcs_shader
.current
));
2288 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
2292 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
2294 unsigned current_scratch_buffer_size
=
2295 si_get_current_scratch_buffer_size(sctx
);
2296 unsigned scratch_bytes_per_wave
=
2297 si_get_max_scratch_bytes_per_wave(sctx
);
2298 unsigned scratch_needed_size
= scratch_bytes_per_wave
*
2299 sctx
->scratch_waves
;
2300 unsigned spi_tmpring_size
;
2303 if (scratch_needed_size
> 0) {
2304 if (scratch_needed_size
> current_scratch_buffer_size
) {
2305 /* Create a bigger scratch buffer */
2306 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
2308 sctx
->scratch_buffer
= (struct r600_resource
*)
2309 r600_aligned_buffer_create(&sctx
->screen
->b
.b
,
2310 R600_RESOURCE_FLAG_UNMAPPABLE
,
2312 scratch_needed_size
, 256);
2313 if (!sctx
->scratch_buffer
)
2316 si_mark_atom_dirty(sctx
, &sctx
->scratch_state
);
2317 r600_context_add_resource_size(&sctx
->b
.b
,
2318 &sctx
->scratch_buffer
->b
.b
);
2321 /* Update the shaders, so they are using the latest scratch. The
2322 * scratch buffer may have been changed since these shaders were
2323 * last used, so we still need to try to update them, even if
2324 * they require scratch buffers smaller than the current size.
2326 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
2330 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
2332 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
2336 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
2338 r
= si_update_scratch_buffer(sctx
, sctx
->tcs_shader
.current
);
2342 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
2344 /* VS can be bound as LS, ES, or VS. */
2345 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
2349 if (sctx
->tes_shader
.current
)
2350 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
2351 else if (sctx
->gs_shader
.current
)
2352 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
2354 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
2357 /* TES can be bound as ES or VS. */
2358 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
2362 if (sctx
->gs_shader
.current
)
2363 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
2365 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
2369 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
2370 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
2371 "scratch size should already be aligned correctly.");
2373 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
2374 S_0286E8_WAVESIZE(scratch_bytes_per_wave
>> 10);
2375 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
2376 sctx
->spi_tmpring_size
= spi_tmpring_size
;
2377 si_mark_atom_dirty(sctx
, &sctx
->scratch_state
);
2382 static void si_init_tess_factor_ring(struct si_context
*sctx
)
2384 bool double_offchip_buffers
= sctx
->b
.chip_class
>= CIK
&&
2385 sctx
->b
.family
!= CHIP_CARRIZO
&&
2386 sctx
->b
.family
!= CHIP_STONEY
;
2387 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
2388 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
2389 sctx
->screen
->b
.info
.max_se
;
2390 unsigned offchip_granularity
;
2392 switch (sctx
->screen
->tess_offchip_block_dw_size
) {
2397 offchip_granularity
= V_03093C_X_8K_DWORDS
;
2400 offchip_granularity
= V_03093C_X_4K_DWORDS
;
2404 switch (sctx
->b
.chip_class
) {
2406 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
2411 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
2418 assert(!sctx
->tf_ring
);
2419 sctx
->tf_ring
= r600_aligned_buffer_create(sctx
->b
.b
.screen
,
2420 R600_RESOURCE_FLAG_UNMAPPABLE
,
2422 32768 * sctx
->screen
->b
.info
.max_se
,
2427 assert(((sctx
->tf_ring
->width0
/ 4) & C_030938_SIZE
) == 0);
2429 sctx
->tess_offchip_ring
=
2430 r600_aligned_buffer_create(sctx
->b
.b
.screen
,
2431 R600_RESOURCE_FLAG_UNMAPPABLE
,
2433 max_offchip_buffers
*
2434 sctx
->screen
->tess_offchip_block_dw_size
* 4,
2436 if (!sctx
->tess_offchip_ring
)
2439 si_init_config_add_vgt_flush(sctx
);
2441 /* Append these registers to the init config state. */
2442 if (sctx
->b
.chip_class
>= CIK
) {
2443 if (sctx
->b
.chip_class
>= VI
)
2444 --max_offchip_buffers
;
2446 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
2447 S_030938_SIZE(sctx
->tf_ring
->width0
/ 4));
2448 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
2449 r600_resource(sctx
->tf_ring
)->gpu_address
>> 8);
2450 if (sctx
->b
.chip_class
>= GFX9
)
2451 si_pm4_set_reg(sctx
->init_config
, R_030944_VGT_TF_MEMORY_BASE_HI
,
2452 r600_resource(sctx
->tf_ring
)->gpu_address
>> 40);
2453 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
2454 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
2455 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
));
2457 assert(offchip_granularity
== V_03093C_X_8K_DWORDS
);
2458 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
2459 S_008988_SIZE(sctx
->tf_ring
->width0
/ 4));
2460 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
2461 r600_resource(sctx
->tf_ring
)->gpu_address
>> 8);
2462 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
2463 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
));
2466 /* Flush the context to re-emit the init_config state.
2467 * This is done only once in a lifetime of a context.
2469 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
2470 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
2471 si_context_gfx_flush(sctx
, RADEON_FLUSH_ASYNC
, NULL
);
2473 si_set_ring_buffer(&sctx
->b
.b
, SI_HS_RING_TESS_FACTOR
, sctx
->tf_ring
,
2474 0, sctx
->tf_ring
->width0
, false, false, 0, 0, 0);
2476 si_set_ring_buffer(&sctx
->b
.b
, SI_HS_RING_TESS_OFFCHIP
,
2477 sctx
->tess_offchip_ring
, 0,
2478 sctx
->tess_offchip_ring
->width0
, false, false, 0, 0, 0);
2482 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
2483 * VS passes its outputs to TES directly, so the fixed-function shader only
2484 * has to write TESSOUTER and TESSINNER.
2486 static void si_generate_fixed_func_tcs(struct si_context
*sctx
)
2488 struct ureg_src outer
, inner
;
2489 struct ureg_dst tessouter
, tessinner
;
2490 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_TESS_CTRL
);
2493 return; /* if we get here, we're screwed */
2495 assert(!sctx
->fixed_func_tcs_shader
.cso
);
2497 outer
= ureg_DECL_system_value(ureg
,
2498 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
, 0);
2499 inner
= ureg_DECL_system_value(ureg
,
2500 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
, 0);
2502 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
2503 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
2505 ureg_MOV(ureg
, tessouter
, outer
);
2506 ureg_MOV(ureg
, tessinner
, inner
);
2509 sctx
->fixed_func_tcs_shader
.cso
=
2510 ureg_create_shader_and_destroy(ureg
, &sctx
->b
.b
);
2513 static void si_update_vgt_shader_config(struct si_context
*sctx
)
2515 /* Calculate the index of the config.
2516 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
2517 unsigned index
= 2*!!sctx
->tes_shader
.cso
+ !!sctx
->gs_shader
.cso
;
2518 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[index
];
2521 uint32_t stages
= 0;
2523 *pm4
= CALLOC_STRUCT(si_pm4_state
);
2525 if (sctx
->tes_shader
.cso
) {
2526 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
2527 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2529 if (sctx
->gs_shader
.cso
)
2530 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
2532 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
2534 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
2535 } else if (sctx
->gs_shader
.cso
) {
2536 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
2538 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
2541 si_pm4_set_reg(*pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
2543 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
2546 static void si_update_so(struct si_context
*sctx
, struct si_shader_selector
*shader
)
2548 struct pipe_stream_output_info
*so
= &shader
->so
;
2549 uint32_t enabled_stream_buffers_mask
= 0;
2552 for (i
= 0; i
< so
->num_outputs
; i
++)
2553 enabled_stream_buffers_mask
|= (1 << so
->output
[i
].output_buffer
) << (so
->output
[i
].stream
* 4);
2554 sctx
->b
.streamout
.enabled_stream_buffers_mask
= enabled_stream_buffers_mask
;
2555 sctx
->b
.streamout
.stride_in_dw
= shader
->so
.stride
;
2558 bool si_update_shaders(struct si_context
*sctx
)
2560 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
2561 struct si_compiler_ctx_state compiler_state
;
2562 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
2563 struct si_shader
*old_vs
= si_get_vs_state(sctx
);
2564 bool old_clip_disable
= old_vs
? old_vs
->key
.opt
.hw_vs
.clip_disable
: false;
2567 compiler_state
.tm
= sctx
->tm
;
2568 compiler_state
.debug
= sctx
->b
.debug
;
2569 compiler_state
.is_debug_context
= sctx
->is_debug
;
2571 /* Update stages before GS. */
2572 if (sctx
->tes_shader
.cso
) {
2573 if (!sctx
->tf_ring
) {
2574 si_init_tess_factor_ring(sctx
);
2580 if (sctx
->b
.chip_class
<= VI
) {
2581 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
2585 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
2588 if (sctx
->tcs_shader
.cso
) {
2589 r
= si_shader_select(ctx
, &sctx
->tcs_shader
,
2593 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
2595 if (!sctx
->fixed_func_tcs_shader
.cso
) {
2596 si_generate_fixed_func_tcs(sctx
);
2597 if (!sctx
->fixed_func_tcs_shader
.cso
)
2601 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
,
2605 si_pm4_bind_state(sctx
, hs
,
2606 sctx
->fixed_func_tcs_shader
.current
->pm4
);
2609 if (sctx
->gs_shader
.cso
) {
2611 if (sctx
->b
.chip_class
<= VI
) {
2612 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
2616 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
2620 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
2624 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
2625 si_update_so(sctx
, sctx
->tes_shader
.cso
);
2627 } else if (sctx
->gs_shader
.cso
) {
2628 if (sctx
->b
.chip_class
<= VI
) {
2630 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
2634 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
2636 si_pm4_bind_state(sctx
, ls
, NULL
);
2637 si_pm4_bind_state(sctx
, hs
, NULL
);
2641 r
= si_shader_select(ctx
, &sctx
->vs_shader
, &compiler_state
);
2644 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
2645 si_update_so(sctx
, sctx
->vs_shader
.cso
);
2647 si_pm4_bind_state(sctx
, ls
, NULL
);
2648 si_pm4_bind_state(sctx
, hs
, NULL
);
2652 if (sctx
->gs_shader
.cso
) {
2653 r
= si_shader_select(ctx
, &sctx
->gs_shader
, &compiler_state
);
2656 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
2657 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
2658 si_update_so(sctx
, sctx
->gs_shader
.cso
);
2660 if (!si_update_gs_ring_buffers(sctx
))
2663 si_pm4_bind_state(sctx
, gs
, NULL
);
2664 if (sctx
->b
.chip_class
<= VI
)
2665 si_pm4_bind_state(sctx
, es
, NULL
);
2668 si_update_vgt_shader_config(sctx
);
2670 if (old_clip_disable
!= si_get_vs_state(sctx
)->key
.opt
.hw_vs
.clip_disable
)
2671 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
2673 if (sctx
->ps_shader
.cso
) {
2674 unsigned db_shader_control
;
2676 r
= si_shader_select(ctx
, &sctx
->ps_shader
, &compiler_state
);
2679 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
2682 sctx
->ps_shader
.cso
->db_shader_control
|
2683 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
2685 if (si_pm4_state_changed(sctx
, ps
) || si_pm4_state_changed(sctx
, vs
) ||
2686 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
2687 sctx
->flatshade
!= rs
->flatshade
) {
2688 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
2689 sctx
->flatshade
= rs
->flatshade
;
2690 si_mark_atom_dirty(sctx
, &sctx
->spi_map
);
2693 if (sctx
->screen
->b
.rbplus_allowed
&& si_pm4_state_changed(sctx
, ps
))
2694 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
2696 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
2697 sctx
->ps_db_shader_control
= db_shader_control
;
2698 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
2701 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
2702 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
2703 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2705 if (sctx
->b
.chip_class
== SI
)
2706 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
2708 if (sctx
->framebuffer
.nr_samples
<= 1)
2709 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
2713 if (si_pm4_state_changed(sctx
, ls
) ||
2714 si_pm4_state_changed(sctx
, hs
) ||
2715 si_pm4_state_changed(sctx
, es
) ||
2716 si_pm4_state_changed(sctx
, gs
) ||
2717 si_pm4_state_changed(sctx
, vs
) ||
2718 si_pm4_state_changed(sctx
, ps
)) {
2719 if (!si_update_spi_tmpring_size(sctx
))
2723 if (sctx
->b
.chip_class
>= CIK
)
2724 si_mark_atom_dirty(sctx
, &sctx
->prefetch_L2
);
2726 sctx
->do_update_shaders
= false;
2730 static void si_emit_scratch_state(struct si_context
*sctx
,
2731 struct r600_atom
*atom
)
2733 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2735 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
2736 sctx
->spi_tmpring_size
);
2738 if (sctx
->scratch_buffer
) {
2739 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2740 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
2741 RADEON_PRIO_SCRATCH_BUFFER
);
2745 void si_init_shader_functions(struct si_context
*sctx
)
2747 si_init_atom(sctx
, &sctx
->spi_map
, &sctx
->atoms
.s
.spi_map
, si_emit_spi_map
);
2748 si_init_atom(sctx
, &sctx
->scratch_state
, &sctx
->atoms
.s
.scratch_state
,
2749 si_emit_scratch_state
);
2751 sctx
->b
.b
.create_vs_state
= si_create_shader_selector
;
2752 sctx
->b
.b
.create_tcs_state
= si_create_shader_selector
;
2753 sctx
->b
.b
.create_tes_state
= si_create_shader_selector
;
2754 sctx
->b
.b
.create_gs_state
= si_create_shader_selector
;
2755 sctx
->b
.b
.create_fs_state
= si_create_shader_selector
;
2757 sctx
->b
.b
.bind_vs_state
= si_bind_vs_shader
;
2758 sctx
->b
.b
.bind_tcs_state
= si_bind_tcs_shader
;
2759 sctx
->b
.b
.bind_tes_state
= si_bind_tes_shader
;
2760 sctx
->b
.b
.bind_gs_state
= si_bind_gs_shader
;
2761 sctx
->b
.b
.bind_fs_state
= si_bind_ps_shader
;
2763 sctx
->b
.b
.delete_vs_state
= si_delete_shader_selector
;
2764 sctx
->b
.b
.delete_tcs_state
= si_delete_shader_selector
;
2765 sctx
->b
.b
.delete_tes_state
= si_delete_shader_selector
;
2766 sctx
->b
.b
.delete_gs_state
= si_delete_shader_selector
;
2767 sctx
->b
.b
.delete_fs_state
= si_delete_shader_selector
;