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[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "sid.h"
30 #include "gfx9d.h"
31 #include "radeon/r600_cs.h"
32
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/hash_table.h"
36 #include "util/crc32.h"
37 #include "util/u_memory.h"
38 #include "util/u_prim.h"
39
40 #include "util/disk_cache.h"
41 #include "util/mesa-sha1.h"
42 #include "ac_exp_param.h"
43
44 /* SHADER_CACHE */
45
46 /**
47 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
48 * integer.
49 */
50 static void *si_get_tgsi_binary(struct si_shader_selector *sel)
51 {
52 unsigned tgsi_size = tgsi_num_tokens(sel->tokens) *
53 sizeof(struct tgsi_token);
54 unsigned size = 4 + tgsi_size + sizeof(sel->so);
55 char *result = (char*)MALLOC(size);
56
57 if (!result)
58 return NULL;
59
60 *((uint32_t*)result) = size;
61 memcpy(result + 4, sel->tokens, tgsi_size);
62 memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so));
63 return result;
64 }
65
66 /** Copy "data" to "ptr" and return the next dword following copied data. */
67 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
68 {
69 /* data may be NULL if size == 0 */
70 if (size)
71 memcpy(ptr, data, size);
72 ptr += DIV_ROUND_UP(size, 4);
73 return ptr;
74 }
75
76 /** Read data from "ptr". Return the next dword following the data. */
77 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
78 {
79 memcpy(data, ptr, size);
80 ptr += DIV_ROUND_UP(size, 4);
81 return ptr;
82 }
83
84 /**
85 * Write the size as uint followed by the data. Return the next dword
86 * following the copied data.
87 */
88 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
89 {
90 *ptr++ = size;
91 return write_data(ptr, data, size);
92 }
93
94 /**
95 * Read the size as uint followed by the data. Return both via parameters.
96 * Return the next dword following the data.
97 */
98 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
99 {
100 *size = *ptr++;
101 assert(*data == NULL);
102 if (!*size)
103 return ptr;
104 *data = malloc(*size);
105 return read_data(ptr, *data, *size);
106 }
107
108 /**
109 * Return the shader binary in a buffer. The first 4 bytes contain its size
110 * as integer.
111 */
112 static void *si_get_shader_binary(struct si_shader *shader)
113 {
114 /* There is always a size of data followed by the data itself. */
115 unsigned relocs_size = shader->binary.reloc_count *
116 sizeof(shader->binary.relocs[0]);
117 unsigned disasm_size = shader->binary.disasm_string ?
118 strlen(shader->binary.disasm_string) + 1 : 0;
119 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
120 strlen(shader->binary.llvm_ir_string) + 1 : 0;
121 unsigned size =
122 4 + /* total size */
123 4 + /* CRC32 of the data below */
124 align(sizeof(shader->config), 4) +
125 align(sizeof(shader->info), 4) +
126 4 + align(shader->binary.code_size, 4) +
127 4 + align(shader->binary.rodata_size, 4) +
128 4 + align(relocs_size, 4) +
129 4 + align(disasm_size, 4) +
130 4 + align(llvm_ir_size, 4);
131 void *buffer = CALLOC(1, size);
132 uint32_t *ptr = (uint32_t*)buffer;
133
134 if (!buffer)
135 return NULL;
136
137 *ptr++ = size;
138 ptr++; /* CRC32 is calculated at the end. */
139
140 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
141 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
142 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
143 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
144 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
145 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
146 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
147 assert((char *)ptr - (char *)buffer == size);
148
149 /* Compute CRC32. */
150 ptr = (uint32_t*)buffer;
151 ptr++;
152 *ptr = util_hash_crc32(ptr + 1, size - 8);
153
154 return buffer;
155 }
156
157 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
158 {
159 uint32_t *ptr = (uint32_t*)binary;
160 uint32_t size = *ptr++;
161 uint32_t crc32 = *ptr++;
162 unsigned chunk_size;
163
164 if (util_hash_crc32(ptr, size - 8) != crc32) {
165 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
166 return false;
167 }
168
169 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
170 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
171 ptr = read_chunk(ptr, (void**)&shader->binary.code,
172 &shader->binary.code_size);
173 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
174 &shader->binary.rodata_size);
175 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
176 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
177 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
178 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
179
180 return true;
181 }
182
183 /**
184 * Insert a shader into the cache. It's assumed the shader is not in the cache.
185 * Use si_shader_cache_load_shader before calling this.
186 *
187 * Returns false on failure, in which case the tgsi_binary should be freed.
188 */
189 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
190 void *tgsi_binary,
191 struct si_shader *shader,
192 bool insert_into_disk_cache)
193 {
194 void *hw_binary;
195 struct hash_entry *entry;
196 uint8_t key[CACHE_KEY_SIZE];
197
198 entry = _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
199 if (entry)
200 return false; /* already added */
201
202 hw_binary = si_get_shader_binary(shader);
203 if (!hw_binary)
204 return false;
205
206 if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
207 hw_binary) == NULL) {
208 FREE(hw_binary);
209 return false;
210 }
211
212 if (sscreen->b.disk_shader_cache && insert_into_disk_cache) {
213 disk_cache_compute_key(sscreen->b.disk_shader_cache, tgsi_binary,
214 *((uint32_t *)tgsi_binary), key);
215 disk_cache_put(sscreen->b.disk_shader_cache, key, hw_binary,
216 *((uint32_t *) hw_binary));
217 }
218
219 return true;
220 }
221
222 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
223 void *tgsi_binary,
224 struct si_shader *shader)
225 {
226 struct hash_entry *entry =
227 _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
228 if (!entry) {
229 if (sscreen->b.disk_shader_cache) {
230 unsigned char sha1[CACHE_KEY_SIZE];
231 size_t tg_size = *((uint32_t *) tgsi_binary);
232
233 disk_cache_compute_key(sscreen->b.disk_shader_cache,
234 tgsi_binary, tg_size, sha1);
235
236 size_t binary_size;
237 uint8_t *buffer =
238 disk_cache_get(sscreen->b.disk_shader_cache,
239 sha1, &binary_size);
240 if (!buffer)
241 return false;
242
243 if (binary_size < sizeof(uint32_t) ||
244 *((uint32_t*)buffer) != binary_size) {
245 /* Something has gone wrong discard the item
246 * from the cache and rebuild/link from
247 * source.
248 */
249 assert(!"Invalid radeonsi shader disk cache "
250 "item!");
251
252 disk_cache_remove(sscreen->b.disk_shader_cache,
253 sha1);
254 free(buffer);
255
256 return false;
257 }
258
259 if (!si_load_shader_binary(shader, buffer)) {
260 free(buffer);
261 return false;
262 }
263 free(buffer);
264
265 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary,
266 shader, false))
267 FREE(tgsi_binary);
268 } else {
269 return false;
270 }
271 } else {
272 if (si_load_shader_binary(shader, entry->data))
273 FREE(tgsi_binary);
274 else
275 return false;
276 }
277 p_atomic_inc(&sscreen->b.num_shader_cache_hits);
278 return true;
279 }
280
281 static uint32_t si_shader_cache_key_hash(const void *key)
282 {
283 /* The first dword is the key size. */
284 return util_hash_crc32(key, *(uint32_t*)key);
285 }
286
287 static bool si_shader_cache_key_equals(const void *a, const void *b)
288 {
289 uint32_t *keya = (uint32_t*)a;
290 uint32_t *keyb = (uint32_t*)b;
291
292 /* The first dword is the key size. */
293 if (*keya != *keyb)
294 return false;
295
296 return memcmp(keya, keyb, *keya) == 0;
297 }
298
299 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
300 {
301 FREE((void*)entry->key);
302 FREE(entry->data);
303 }
304
305 bool si_init_shader_cache(struct si_screen *sscreen)
306 {
307 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
308 sscreen->shader_cache =
309 _mesa_hash_table_create(NULL,
310 si_shader_cache_key_hash,
311 si_shader_cache_key_equals);
312
313 return sscreen->shader_cache != NULL;
314 }
315
316 void si_destroy_shader_cache(struct si_screen *sscreen)
317 {
318 if (sscreen->shader_cache)
319 _mesa_hash_table_destroy(sscreen->shader_cache,
320 si_destroy_shader_cache_entry);
321 mtx_destroy(&sscreen->shader_cache_mutex);
322 }
323
324 /* SHADER STATES */
325
326 static void si_set_tesseval_regs(struct si_screen *sscreen,
327 struct si_shader *shader,
328 struct si_pm4_state *pm4)
329 {
330 struct tgsi_shader_info *info = &shader->selector->info;
331 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
332 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
333 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
334 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
335 unsigned type, partitioning, topology, distribution_mode;
336
337 switch (tes_prim_mode) {
338 case PIPE_PRIM_LINES:
339 type = V_028B6C_TESS_ISOLINE;
340 break;
341 case PIPE_PRIM_TRIANGLES:
342 type = V_028B6C_TESS_TRIANGLE;
343 break;
344 case PIPE_PRIM_QUADS:
345 type = V_028B6C_TESS_QUAD;
346 break;
347 default:
348 assert(0);
349 return;
350 }
351
352 switch (tes_spacing) {
353 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
354 partitioning = V_028B6C_PART_FRAC_ODD;
355 break;
356 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
357 partitioning = V_028B6C_PART_FRAC_EVEN;
358 break;
359 case PIPE_TESS_SPACING_EQUAL:
360 partitioning = V_028B6C_PART_INTEGER;
361 break;
362 default:
363 assert(0);
364 return;
365 }
366
367 if (tes_point_mode)
368 topology = V_028B6C_OUTPUT_POINT;
369 else if (tes_prim_mode == PIPE_PRIM_LINES)
370 topology = V_028B6C_OUTPUT_LINE;
371 else if (tes_vertex_order_cw)
372 /* for some reason, this must be the other way around */
373 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
374 else
375 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
376
377 if (sscreen->has_distributed_tess) {
378 if (sscreen->b.family == CHIP_FIJI ||
379 sscreen->b.family >= CHIP_POLARIS10)
380 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
381 else
382 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
383 } else
384 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
385
386 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
387 S_028B6C_TYPE(type) |
388 S_028B6C_PARTITIONING(partitioning) |
389 S_028B6C_TOPOLOGY(topology) |
390 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
391 }
392
393 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
394 * whether the "fractional odd" tessellation spacing is used.
395 *
396 * Possible VGT configurations and which state should set the register:
397 *
398 * Reg set in | VGT shader configuration | Value
399 * ------------------------------------------------------
400 * VS as VS | VS | 30
401 * VS as ES | ES -> GS -> VS | 30
402 * TES as VS | LS -> HS -> VS | 14 or 30
403 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
404 */
405 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
406 struct si_shader *shader,
407 struct si_pm4_state *pm4)
408 {
409 unsigned type = shader->selector->type;
410
411 if (sscreen->b.family < CHIP_POLARIS10)
412 return;
413
414 /* VS as VS, or VS as ES: */
415 if ((type == PIPE_SHADER_VERTEX &&
416 !shader->key.as_ls &&
417 !shader->is_gs_copy_shader) ||
418 /* TES as VS, or TES as ES: */
419 type == PIPE_SHADER_TESS_EVAL) {
420 unsigned vtx_reuse_depth = 30;
421
422 if (type == PIPE_SHADER_TESS_EVAL &&
423 shader->selector->info.properties[TGSI_PROPERTY_TES_SPACING] ==
424 PIPE_TESS_SPACING_FRACTIONAL_ODD)
425 vtx_reuse_depth = 14;
426
427 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
428 vtx_reuse_depth);
429 }
430 }
431
432 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
433 {
434 if (shader->pm4)
435 si_pm4_clear_state(shader->pm4);
436 else
437 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
438
439 return shader->pm4;
440 }
441
442 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
443 {
444 struct si_pm4_state *pm4;
445 unsigned vgpr_comp_cnt;
446 uint64_t va;
447
448 assert(sscreen->b.chip_class <= VI);
449
450 pm4 = si_get_shader_pm4_state(shader);
451 if (!pm4)
452 return;
453
454 va = shader->bo->gpu_address;
455 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
456
457 /* We need at least 2 components for LS.
458 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
459 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 1;
460
461 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
462 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
463
464 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
465 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
466 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
467 S_00B528_DX10_CLAMP(1) |
468 S_00B528_FLOAT_MODE(shader->config.float_mode);
469 shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_VS_NUM_USER_SGPR) |
470 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
471 }
472
473 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
474 {
475 struct si_pm4_state *pm4;
476 uint64_t va;
477 unsigned ls_vgpr_comp_cnt = 0;
478
479 pm4 = si_get_shader_pm4_state(shader);
480 if (!pm4)
481 return;
482
483 va = shader->bo->gpu_address;
484 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
485
486 if (sscreen->b.chip_class >= GFX9) {
487 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
488 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, va >> 40);
489
490 /* We need at least 2 components for LS.
491 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
492 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 1;
493
494 shader->config.rsrc2 =
495 S_00B42C_USER_SGPR(SI_TCS_NUM_USER_SGPR) |
496 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
497 } else {
498 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
499 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
500
501 shader->config.rsrc2 =
502 S_00B42C_USER_SGPR(SI_TCS_NUM_USER_SGPR) |
503 S_00B42C_OC_LDS_EN(1) |
504 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
505 }
506
507 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
508 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
509 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
510 S_00B428_DX10_CLAMP(1) |
511 S_00B428_FLOAT_MODE(shader->config.float_mode) |
512 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
513
514 if (sscreen->b.chip_class <= VI) {
515 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
516 shader->config.rsrc2);
517 }
518 }
519
520 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
521 {
522 struct si_pm4_state *pm4;
523 unsigned num_user_sgprs;
524 unsigned vgpr_comp_cnt;
525 uint64_t va;
526 unsigned oc_lds_en;
527
528 assert(sscreen->b.chip_class <= VI);
529
530 pm4 = si_get_shader_pm4_state(shader);
531 if (!pm4)
532 return;
533
534 va = shader->bo->gpu_address;
535 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
536
537 if (shader->selector->type == PIPE_SHADER_VERTEX) {
538 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
539 num_user_sgprs = SI_VS_NUM_USER_SGPR;
540 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
541 vgpr_comp_cnt = 3; /* all components are needed for TES */
542 num_user_sgprs = SI_TES_NUM_USER_SGPR;
543 } else
544 unreachable("invalid shader selector type");
545
546 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
547
548 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
549 shader->selector->esgs_itemsize / 4);
550 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
551 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
552 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
553 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
554 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
555 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
556 S_00B328_DX10_CLAMP(1) |
557 S_00B328_FLOAT_MODE(shader->config.float_mode));
558 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
559 S_00B32C_USER_SGPR(num_user_sgprs) |
560 S_00B32C_OC_LDS_EN(oc_lds_en) |
561 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
562
563 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
564 si_set_tesseval_regs(sscreen, shader, pm4);
565
566 polaris_set_vgt_vertex_reuse(sscreen, shader, pm4);
567 }
568
569 /**
570 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
571 * geometry shader.
572 */
573 static uint32_t si_vgt_gs_mode(struct si_shader_selector *sel)
574 {
575 unsigned gs_max_vert_out = sel->gs_max_out_vertices;
576 unsigned cut_mode;
577
578 if (gs_max_vert_out <= 128) {
579 cut_mode = V_028A40_GS_CUT_128;
580 } else if (gs_max_vert_out <= 256) {
581 cut_mode = V_028A40_GS_CUT_256;
582 } else if (gs_max_vert_out <= 512) {
583 cut_mode = V_028A40_GS_CUT_512;
584 } else {
585 assert(gs_max_vert_out <= 1024);
586 cut_mode = V_028A40_GS_CUT_1024;
587 }
588
589 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
590 S_028A40_CUT_MODE(cut_mode)|
591 S_028A40_ES_WRITE_OPTIMIZE(1) |
592 S_028A40_GS_WRITE_OPTIMIZE(1);
593 }
594
595 static void si_shader_gs(struct si_shader *shader)
596 {
597 struct si_shader_selector *sel = shader->selector;
598 const ubyte *num_components = sel->info.num_stream_output_components;
599 unsigned gs_num_invocations = sel->gs_num_invocations;
600 struct si_pm4_state *pm4;
601 uint64_t va;
602 unsigned max_stream = sel->max_gs_stream;
603 unsigned offset;
604
605 pm4 = si_get_shader_pm4_state(shader);
606 if (!pm4)
607 return;
608
609 offset = num_components[0] * sel->gs_max_out_vertices;
610 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, offset);
611 if (max_stream >= 1)
612 offset += num_components[1] * sel->gs_max_out_vertices;
613 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, offset);
614 if (max_stream >= 2)
615 offset += num_components[2] * sel->gs_max_out_vertices;
616 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, offset);
617 if (max_stream >= 3)
618 offset += num_components[3] * sel->gs_max_out_vertices;
619 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
620
621 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
622 assert(offset < (1 << 15));
623
624 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, shader->selector->gs_max_out_vertices);
625
626 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, num_components[0]);
627 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? num_components[1] : 0);
628 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? num_components[2] : 0);
629 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? num_components[3] : 0);
630
631 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
632 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
633 S_028B90_ENABLE(gs_num_invocations > 0));
634
635 va = shader->bo->gpu_address;
636 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
637 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
638 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
639
640 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
641 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
642 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
643 S_00B228_DX10_CLAMP(1) |
644 S_00B228_FLOAT_MODE(shader->config.float_mode));
645 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
646 S_00B22C_USER_SGPR(SI_GS_NUM_USER_SGPR) |
647 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
648 }
649
650 /**
651 * Compute the state for \p shader, which will run as a vertex shader on the
652 * hardware.
653 *
654 * If \p gs is non-NULL, it points to the geometry shader for which this shader
655 * is the copy shader.
656 */
657 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
658 struct si_shader_selector *gs)
659 {
660 struct si_pm4_state *pm4;
661 unsigned num_user_sgprs;
662 unsigned nparams, vgpr_comp_cnt;
663 uint64_t va;
664 unsigned oc_lds_en;
665 unsigned window_space =
666 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
667 bool enable_prim_id = si_vs_exports_prim_id(shader);
668
669 pm4 = si_get_shader_pm4_state(shader);
670 if (!pm4)
671 return;
672
673 /* We always write VGT_GS_MODE in the VS state, because every switch
674 * between different shader pipelines involving a different GS or no
675 * GS at all involves a switch of the VS (different GS use different
676 * copy shaders). On the other hand, when the API switches from a GS to
677 * no GS and then back to the same GS used originally, the GS state is
678 * not sent again.
679 */
680 if (!gs) {
681 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
682 S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
683 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
684 } else {
685 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
686 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
687 }
688
689 va = shader->bo->gpu_address;
690 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
691
692 if (gs) {
693 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
694 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
695 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
696 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
697 num_user_sgprs = SI_VS_NUM_USER_SGPR;
698 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
699 vgpr_comp_cnt = 3; /* all components are needed for TES */
700 num_user_sgprs = SI_TES_NUM_USER_SGPR;
701 } else
702 unreachable("invalid shader selector type");
703
704 /* VS is required to export at least one param. */
705 nparams = MAX2(shader->info.nr_param_exports, 1);
706 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
707 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
708
709 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
710 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
711 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
712 V_02870C_SPI_SHADER_4COMP :
713 V_02870C_SPI_SHADER_NONE) |
714 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
715 V_02870C_SPI_SHADER_4COMP :
716 V_02870C_SPI_SHADER_NONE) |
717 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
718 V_02870C_SPI_SHADER_4COMP :
719 V_02870C_SPI_SHADER_NONE));
720
721 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
722
723 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
724 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
725 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
726 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
727 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
728 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
729 S_00B128_DX10_CLAMP(1) |
730 S_00B128_FLOAT_MODE(shader->config.float_mode));
731 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
732 S_00B12C_USER_SGPR(num_user_sgprs) |
733 S_00B12C_OC_LDS_EN(oc_lds_en) |
734 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
735 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
736 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
737 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
738 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
739 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
740 if (window_space)
741 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
742 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
743 else
744 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
745 S_028818_VTX_W0_FMT(1) |
746 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
747 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
748 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
749
750 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
751 si_set_tesseval_regs(sscreen, shader, pm4);
752
753 polaris_set_vgt_vertex_reuse(sscreen, shader, pm4);
754 }
755
756 static unsigned si_get_ps_num_interp(struct si_shader *ps)
757 {
758 struct tgsi_shader_info *info = &ps->selector->info;
759 unsigned num_colors = !!(info->colors_read & 0x0f) +
760 !!(info->colors_read & 0xf0);
761 unsigned num_interp = ps->selector->info.num_inputs +
762 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
763
764 assert(num_interp <= 32);
765 return MIN2(num_interp, 32);
766 }
767
768 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
769 {
770 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
771 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
772
773 /* If the i-th target format is set, all previous target formats must
774 * be non-zero to avoid hangs.
775 */
776 for (i = 0; i < num_targets; i++)
777 if (!(value & (0xf << (i * 4))))
778 value |= V_028714_SPI_SHADER_32_R << (i * 4);
779
780 return value;
781 }
782
783 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
784 {
785 unsigned i, cb_shader_mask = 0;
786
787 for (i = 0; i < 8; i++) {
788 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
789 case V_028714_SPI_SHADER_ZERO:
790 break;
791 case V_028714_SPI_SHADER_32_R:
792 cb_shader_mask |= 0x1 << (i * 4);
793 break;
794 case V_028714_SPI_SHADER_32_GR:
795 cb_shader_mask |= 0x3 << (i * 4);
796 break;
797 case V_028714_SPI_SHADER_32_AR:
798 cb_shader_mask |= 0x9 << (i * 4);
799 break;
800 case V_028714_SPI_SHADER_FP16_ABGR:
801 case V_028714_SPI_SHADER_UNORM16_ABGR:
802 case V_028714_SPI_SHADER_SNORM16_ABGR:
803 case V_028714_SPI_SHADER_UINT16_ABGR:
804 case V_028714_SPI_SHADER_SINT16_ABGR:
805 case V_028714_SPI_SHADER_32_ABGR:
806 cb_shader_mask |= 0xf << (i * 4);
807 break;
808 default:
809 assert(0);
810 }
811 }
812 return cb_shader_mask;
813 }
814
815 static void si_shader_ps(struct si_shader *shader)
816 {
817 struct tgsi_shader_info *info = &shader->selector->info;
818 struct si_pm4_state *pm4;
819 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
820 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
821 uint64_t va;
822 unsigned input_ena = shader->config.spi_ps_input_ena;
823
824 /* we need to enable at least one of them, otherwise we hang the GPU */
825 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
826 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
827 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
828 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
829 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
830 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
831 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
832 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
833 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
834 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
835 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
836 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
837 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
838 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
839
840 /* Validate interpolation optimization flags (read as implications). */
841 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
842 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
843 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
844 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
845 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
846 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
847 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
848 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
849 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
850 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
851 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
852 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
853 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
854 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
855 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
856 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
857 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
858 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
859
860 /* Validate cases when the optimizations are off (read as implications). */
861 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
862 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
863 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
864 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
865 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
866 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
867
868 pm4 = si_get_shader_pm4_state(shader);
869 if (!pm4)
870 return;
871
872 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
873 * Possible vaules:
874 * 0 -> Position = pixel center
875 * 1 -> Position = pixel centroid
876 * 2 -> Position = at sample position
877 *
878 * From GLSL 4.5 specification, section 7.1:
879 * "The variable gl_FragCoord is available as an input variable from
880 * within fragment shaders and it holds the window relative coordinates
881 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
882 * value can be for any location within the pixel, or one of the
883 * fragment samples. The use of centroid does not further restrict
884 * this value to be inside the current primitive."
885 *
886 * Meaning that centroid has no effect and we can return anything within
887 * the pixel. Thus, return the value at sample position, because that's
888 * the most accurate one shaders can get.
889 */
890 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
891
892 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
893 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
894 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
895
896 spi_shader_col_format = si_get_spi_shader_col_format(shader);
897 cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
898
899 /* Ensure that some export memory is always allocated, for two reasons:
900 *
901 * 1) Correctness: The hardware ignores the EXEC mask if no export
902 * memory is allocated, so KILL and alpha test do not work correctly
903 * without this.
904 * 2) Performance: Every shader needs at least a NULL export, even when
905 * it writes no color/depth output. The NULL export instruction
906 * stalls without this setting.
907 *
908 * Don't add this to CB_SHADER_MASK.
909 */
910 if (!spi_shader_col_format &&
911 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
912 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
913
914 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
915 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
916 shader->config.spi_ps_input_addr);
917
918 /* Set interpolation controls. */
919 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
920
921 /* Set registers. */
922 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
923 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
924
925 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
926 si_get_spi_shader_z_format(info->writes_z,
927 info->writes_stencil,
928 info->writes_samplemask));
929
930 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
931 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
932
933 va = shader->bo->gpu_address;
934 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
935 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
936 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
937
938 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
939 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
940 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
941 S_00B028_DX10_CLAMP(1) |
942 S_00B028_FLOAT_MODE(shader->config.float_mode));
943 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
944 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
945 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
946 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
947 }
948
949 static void si_shader_init_pm4_state(struct si_screen *sscreen,
950 struct si_shader *shader)
951 {
952 switch (shader->selector->type) {
953 case PIPE_SHADER_VERTEX:
954 if (shader->key.as_ls)
955 si_shader_ls(sscreen, shader);
956 else if (shader->key.as_es)
957 si_shader_es(sscreen, shader);
958 else
959 si_shader_vs(sscreen, shader, NULL);
960 break;
961 case PIPE_SHADER_TESS_CTRL:
962 si_shader_hs(sscreen, shader);
963 break;
964 case PIPE_SHADER_TESS_EVAL:
965 if (shader->key.as_es)
966 si_shader_es(sscreen, shader);
967 else
968 si_shader_vs(sscreen, shader, NULL);
969 break;
970 case PIPE_SHADER_GEOMETRY:
971 si_shader_gs(shader);
972 break;
973 case PIPE_SHADER_FRAGMENT:
974 si_shader_ps(shader);
975 break;
976 default:
977 assert(0);
978 }
979 }
980
981 static unsigned si_get_alpha_test_func(struct si_context *sctx)
982 {
983 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
984 if (sctx->queued.named.dsa)
985 return sctx->queued.named.dsa->alpha_func;
986
987 return PIPE_FUNC_ALWAYS;
988 }
989
990 static void si_shader_selector_key_vs(struct si_context *sctx,
991 struct si_shader_selector *vs,
992 struct si_shader_key *key,
993 struct si_vs_prolog_bits *prolog_key)
994 {
995 if (!sctx->vertex_elements)
996 return;
997
998 unsigned count = MIN2(vs->info.num_inputs,
999 sctx->vertex_elements->count);
1000 for (unsigned i = 0; i < count; ++i) {
1001 prolog_key->instance_divisors[i] =
1002 sctx->vertex_elements->elements[i].instance_divisor;
1003 }
1004
1005 memcpy(key->mono.vs_fix_fetch, sctx->vertex_elements->fix_fetch, count);
1006 }
1007
1008 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1009 struct si_shader_selector *vs,
1010 struct si_shader_key *key)
1011 {
1012 struct si_shader_selector *ps = sctx->ps_shader.cso;
1013
1014 key->opt.hw_vs.clip_disable =
1015 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1016 (vs->info.clipdist_writemask ||
1017 vs->info.writes_clipvertex) &&
1018 !vs->info.culldist_writemask;
1019
1020 /* Find out if PS is disabled. */
1021 bool ps_disabled = true;
1022 if (ps) {
1023 bool ps_modifies_zs = ps->info.uses_kill ||
1024 ps->info.writes_z ||
1025 ps->info.writes_stencil ||
1026 ps->info.writes_samplemask ||
1027 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1028
1029 unsigned ps_colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1030 sctx->queued.named.blend->cb_target_mask;
1031 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1032 ps_colormask &= ps->colors_written_4bit;
1033
1034 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1035 (!ps_colormask &&
1036 !ps_modifies_zs &&
1037 !ps->info.writes_memory);
1038 }
1039
1040 /* Find out which VS outputs aren't used by the PS. */
1041 uint64_t outputs_written = vs->outputs_written;
1042 uint32_t outputs_written2 = vs->outputs_written2;
1043 uint64_t inputs_read = 0;
1044 uint32_t inputs_read2 = 0;
1045
1046 outputs_written &= ~0x3; /* ignore POSITION, PSIZE */
1047
1048 if (!ps_disabled) {
1049 inputs_read = ps->inputs_read;
1050 inputs_read2 = ps->inputs_read2;
1051 }
1052
1053 uint64_t linked = outputs_written & inputs_read;
1054 uint32_t linked2 = outputs_written2 & inputs_read2;
1055
1056 key->opt.hw_vs.kill_outputs = ~linked & outputs_written;
1057 key->opt.hw_vs.kill_outputs2 = ~linked2 & outputs_written2;
1058 }
1059
1060 /* Compute the key for the hw shader variant */
1061 static inline void si_shader_selector_key(struct pipe_context *ctx,
1062 struct si_shader_selector *sel,
1063 struct si_shader_key *key)
1064 {
1065 struct si_context *sctx = (struct si_context *)ctx;
1066
1067 memset(key, 0, sizeof(*key));
1068
1069 switch (sel->type) {
1070 case PIPE_SHADER_VERTEX:
1071 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1072
1073 if (sctx->tes_shader.cso)
1074 key->as_ls = 1;
1075 else if (sctx->gs_shader.cso)
1076 key->as_es = 1;
1077 else {
1078 si_shader_selector_key_hw_vs(sctx, sel, key);
1079
1080 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1081 key->part.vs.epilog.export_prim_id = 1;
1082 }
1083 break;
1084 case PIPE_SHADER_TESS_CTRL:
1085 if (sctx->b.chip_class >= GFX9) {
1086 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1087 key, &key->part.tcs.ls_prolog);
1088 key->part.tcs.ls = sctx->vs_shader.cso;
1089 }
1090
1091 key->part.tcs.epilog.prim_mode =
1092 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1093 key->part.tcs.epilog.tes_reads_tess_factors =
1094 sctx->tes_shader.cso->info.reads_tess_factors;
1095
1096 if (sel == sctx->fixed_func_tcs_shader.cso)
1097 key->mono.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1098 break;
1099 case PIPE_SHADER_TESS_EVAL:
1100 if (sctx->gs_shader.cso)
1101 key->as_es = 1;
1102 else {
1103 si_shader_selector_key_hw_vs(sctx, sel, key);
1104
1105 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1106 key->part.tes.epilog.export_prim_id = 1;
1107 }
1108 break;
1109 case PIPE_SHADER_GEOMETRY:
1110 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1111 break;
1112 case PIPE_SHADER_FRAGMENT: {
1113 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1114 struct si_state_blend *blend = sctx->queued.named.blend;
1115
1116 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1117 sel->info.colors_written == 0x1)
1118 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1119
1120 if (blend) {
1121 /* Select the shader color format based on whether
1122 * blending or alpha are needed.
1123 */
1124 key->part.ps.epilog.spi_shader_col_format =
1125 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1126 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1127 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1128 sctx->framebuffer.spi_shader_col_format_blend) |
1129 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1130 sctx->framebuffer.spi_shader_col_format_alpha) |
1131 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1132 sctx->framebuffer.spi_shader_col_format);
1133
1134 /* The output for dual source blending should have
1135 * the same format as the first output.
1136 */
1137 if (blend->dual_src_blend)
1138 key->part.ps.epilog.spi_shader_col_format |=
1139 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1140 } else
1141 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1142
1143 /* If alpha-to-coverage is enabled, we have to export alpha
1144 * even if there is no color buffer.
1145 */
1146 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1147 blend && blend->alpha_to_coverage)
1148 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1149
1150 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1151 * to the range supported by the type if a channel has less
1152 * than 16 bits and the export format is 16_ABGR.
1153 */
1154 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII) {
1155 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1156 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1157 }
1158
1159 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1160 if (!key->part.ps.epilog.last_cbuf) {
1161 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1162 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1163 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1164 }
1165
1166 if (rs) {
1167 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
1168 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
1169 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
1170 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
1171
1172 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1173 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1174
1175 if (sctx->queued.named.blend) {
1176 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1177 rs->multisample_enable;
1178 }
1179
1180 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1181 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1182 (is_line && rs->line_smooth)) &&
1183 sctx->framebuffer.nr_samples <= 1;
1184 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1185
1186 if (rs->force_persample_interp &&
1187 rs->multisample_enable &&
1188 sctx->framebuffer.nr_samples > 1 &&
1189 sctx->ps_iter_samples > 1) {
1190 key->part.ps.prolog.force_persp_sample_interp =
1191 sel->info.uses_persp_center ||
1192 sel->info.uses_persp_centroid;
1193
1194 key->part.ps.prolog.force_linear_sample_interp =
1195 sel->info.uses_linear_center ||
1196 sel->info.uses_linear_centroid;
1197 } else if (rs->multisample_enable &&
1198 sctx->framebuffer.nr_samples > 1) {
1199 key->part.ps.prolog.bc_optimize_for_persp =
1200 sel->info.uses_persp_center &&
1201 sel->info.uses_persp_centroid;
1202 key->part.ps.prolog.bc_optimize_for_linear =
1203 sel->info.uses_linear_center &&
1204 sel->info.uses_linear_centroid;
1205 } else {
1206 /* Make sure SPI doesn't compute more than 1 pair
1207 * of (i,j), which is the optimization here. */
1208 key->part.ps.prolog.force_persp_center_interp =
1209 sel->info.uses_persp_center +
1210 sel->info.uses_persp_centroid +
1211 sel->info.uses_persp_sample > 1;
1212
1213 key->part.ps.prolog.force_linear_center_interp =
1214 sel->info.uses_linear_center +
1215 sel->info.uses_linear_centroid +
1216 sel->info.uses_linear_sample > 1;
1217 }
1218 }
1219
1220 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1221 break;
1222 }
1223 default:
1224 assert(0);
1225 }
1226 }
1227
1228 static void si_build_shader_variant(void *job, int thread_index)
1229 {
1230 struct si_shader *shader = (struct si_shader *)job;
1231 struct si_shader_selector *sel = shader->selector;
1232 struct si_screen *sscreen = sel->screen;
1233 LLVMTargetMachineRef tm;
1234 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1235 int r;
1236
1237 if (thread_index >= 0) {
1238 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1239 tm = sscreen->tm[thread_index];
1240 if (!debug->async)
1241 debug = NULL;
1242 } else {
1243 tm = shader->compiler_ctx_state.tm;
1244 }
1245
1246 r = si_shader_create(sscreen, tm, shader, debug);
1247 if (unlikely(r)) {
1248 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1249 sel->type, r);
1250 shader->compilation_failed = true;
1251 return;
1252 }
1253
1254 if (shader->compiler_ctx_state.is_debug_context) {
1255 FILE *f = open_memstream(&shader->shader_log,
1256 &shader->shader_log_size);
1257 if (f) {
1258 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1259 fclose(f);
1260 }
1261 }
1262
1263 si_shader_init_pm4_state(sscreen, shader);
1264 }
1265
1266 /* Select the hw shader variant depending on the current state. */
1267 static int si_shader_select_with_key(struct si_screen *sscreen,
1268 struct si_shader_ctx_state *state,
1269 struct si_compiler_ctx_state *compiler_state,
1270 struct si_shader_key *key,
1271 int thread_index)
1272 {
1273 static const struct si_shader_key zeroed;
1274 struct si_shader_selector *sel = state->cso;
1275 struct si_shader *current = state->current;
1276 struct si_shader *iter, *shader = NULL;
1277
1278 if (unlikely(sscreen->b.debug_flags & DBG_NO_OPT_VARIANT)) {
1279 memset(&key->opt, 0, sizeof(key->opt));
1280 }
1281
1282 again:
1283 /* Check if we don't need to change anything.
1284 * This path is also used for most shaders that don't need multiple
1285 * variants, it will cost just a computation of the key and this
1286 * test. */
1287 if (likely(current &&
1288 memcmp(&current->key, key, sizeof(*key)) == 0 &&
1289 (!current->is_optimized ||
1290 util_queue_fence_is_signalled(&current->optimized_ready))))
1291 return current->compilation_failed ? -1 : 0;
1292
1293 /* This must be done before the mutex is locked, because async GS
1294 * compilation calls this function too, and therefore must enter
1295 * the mutex first.
1296 *
1297 * Only wait if we are in a draw call. Don't wait if we are
1298 * in a compiler thread.
1299 */
1300 if (thread_index < 0)
1301 util_queue_fence_wait(&sel->ready);
1302
1303 mtx_lock(&sel->mutex);
1304
1305 /* Find the shader variant. */
1306 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1307 /* Don't check the "current" shader. We checked it above. */
1308 if (current != iter &&
1309 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1310 /* If it's an optimized shader and its compilation has
1311 * been started but isn't done, use the unoptimized
1312 * shader so as not to cause a stall due to compilation.
1313 */
1314 if (iter->is_optimized &&
1315 !util_queue_fence_is_signalled(&iter->optimized_ready)) {
1316 memset(&key->opt, 0, sizeof(key->opt));
1317 mtx_unlock(&sel->mutex);
1318 goto again;
1319 }
1320
1321 if (iter->compilation_failed) {
1322 mtx_unlock(&sel->mutex);
1323 return -1; /* skip the draw call */
1324 }
1325
1326 state->current = iter;
1327 mtx_unlock(&sel->mutex);
1328 return 0;
1329 }
1330 }
1331
1332 /* Build a new shader. */
1333 shader = CALLOC_STRUCT(si_shader);
1334 if (!shader) {
1335 mtx_unlock(&sel->mutex);
1336 return -ENOMEM;
1337 }
1338 shader->selector = sel;
1339 shader->key = *key;
1340 shader->compiler_ctx_state = *compiler_state;
1341
1342 /* Compile the main shader part if it doesn't exist. This can happen
1343 * if the initial guess was wrong. */
1344 struct si_shader **mainp = si_get_main_shader_part(sel, key);
1345 bool is_pure_monolithic =
1346 sscreen->use_monolithic_shaders ||
1347 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1348
1349 if (!*mainp && !is_pure_monolithic) {
1350 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1351
1352 if (!main_part) {
1353 FREE(shader);
1354 mtx_unlock(&sel->mutex);
1355 return -ENOMEM; /* skip the draw call */
1356 }
1357
1358 main_part->selector = sel;
1359 main_part->key.as_es = key->as_es;
1360 main_part->key.as_ls = key->as_ls;
1361
1362 if (si_compile_tgsi_shader(sscreen, compiler_state->tm,
1363 main_part, false,
1364 &compiler_state->debug) != 0) {
1365 FREE(main_part);
1366 FREE(shader);
1367 mtx_unlock(&sel->mutex);
1368 return -ENOMEM; /* skip the draw call */
1369 }
1370 *mainp = main_part;
1371 }
1372
1373 /* Monolithic-only shaders don't make a distinction between optimized
1374 * and unoptimized. */
1375 shader->is_monolithic =
1376 is_pure_monolithic ||
1377 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1378
1379 shader->is_optimized =
1380 !is_pure_monolithic &&
1381 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1382 if (shader->is_optimized)
1383 util_queue_fence_init(&shader->optimized_ready);
1384
1385 if (!sel->last_variant) {
1386 sel->first_variant = shader;
1387 sel->last_variant = shader;
1388 } else {
1389 sel->last_variant->next_variant = shader;
1390 sel->last_variant = shader;
1391 }
1392
1393 /* If it's an optimized shader, compile it asynchronously. */
1394 if (shader->is_optimized &&
1395 !is_pure_monolithic &&
1396 thread_index < 0) {
1397 /* Compile it asynchronously. */
1398 util_queue_add_job(&sscreen->shader_compiler_queue,
1399 shader, &shader->optimized_ready,
1400 si_build_shader_variant, NULL);
1401
1402 /* Use the default (unoptimized) shader for now. */
1403 memset(&key->opt, 0, sizeof(key->opt));
1404 mtx_unlock(&sel->mutex);
1405 goto again;
1406 }
1407
1408 assert(!shader->is_optimized);
1409 si_build_shader_variant(shader, thread_index);
1410
1411 if (!shader->compilation_failed)
1412 state->current = shader;
1413
1414 mtx_unlock(&sel->mutex);
1415 return shader->compilation_failed ? -1 : 0;
1416 }
1417
1418 static int si_shader_select(struct pipe_context *ctx,
1419 struct si_shader_ctx_state *state,
1420 struct si_compiler_ctx_state *compiler_state)
1421 {
1422 struct si_context *sctx = (struct si_context *)ctx;
1423 struct si_shader_key key;
1424
1425 si_shader_selector_key(ctx, state->cso, &key);
1426 return si_shader_select_with_key(sctx->screen, state, compiler_state,
1427 &key, -1);
1428 }
1429
1430 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1431 struct si_shader_key *key)
1432 {
1433 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1434
1435 switch (info->processor) {
1436 case PIPE_SHADER_VERTEX:
1437 switch (next_shader) {
1438 case PIPE_SHADER_GEOMETRY:
1439 key->as_es = 1;
1440 break;
1441 case PIPE_SHADER_TESS_CTRL:
1442 case PIPE_SHADER_TESS_EVAL:
1443 key->as_ls = 1;
1444 break;
1445 default:
1446 /* If POSITION isn't written, it can't be a HW VS.
1447 * Assume that it's a HW LS. (the next shader is TCS)
1448 * This heuristic is needed for separate shader objects.
1449 */
1450 if (!info->writes_position)
1451 key->as_ls = 1;
1452 }
1453 break;
1454
1455 case PIPE_SHADER_TESS_EVAL:
1456 if (next_shader == PIPE_SHADER_GEOMETRY ||
1457 !info->writes_position)
1458 key->as_es = 1;
1459 break;
1460 }
1461 }
1462
1463 /**
1464 * Compile the main shader part or the monolithic shader as part of
1465 * si_shader_selector initialization. Since it can be done asynchronously,
1466 * there is no way to report compile failures to applications.
1467 */
1468 void si_init_shader_selector_async(void *job, int thread_index)
1469 {
1470 struct si_shader_selector *sel = (struct si_shader_selector *)job;
1471 struct si_screen *sscreen = sel->screen;
1472 LLVMTargetMachineRef tm;
1473 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
1474 unsigned i;
1475
1476 if (thread_index >= 0) {
1477 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1478 tm = sscreen->tm[thread_index];
1479 if (!debug->async)
1480 debug = NULL;
1481 } else {
1482 tm = sel->compiler_ctx_state.tm;
1483 }
1484
1485 /* Compile the main shader part for use with a prolog and/or epilog.
1486 * If this fails, the driver will try to compile a monolithic shader
1487 * on demand.
1488 */
1489 if (!sscreen->use_monolithic_shaders) {
1490 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1491 void *tgsi_binary;
1492
1493 if (!shader) {
1494 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
1495 return;
1496 }
1497
1498 shader->selector = sel;
1499 si_parse_next_shader_property(&sel->info, &shader->key);
1500
1501 tgsi_binary = si_get_tgsi_binary(sel);
1502
1503 /* Try to load the shader from the shader cache. */
1504 mtx_lock(&sscreen->shader_cache_mutex);
1505
1506 if (tgsi_binary &&
1507 si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
1508 mtx_unlock(&sscreen->shader_cache_mutex);
1509 } else {
1510 mtx_unlock(&sscreen->shader_cache_mutex);
1511
1512 /* Compile the shader if it hasn't been loaded from the cache. */
1513 if (si_compile_tgsi_shader(sscreen, tm, shader, false,
1514 debug) != 0) {
1515 FREE(shader);
1516 FREE(tgsi_binary);
1517 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
1518 return;
1519 }
1520
1521 if (tgsi_binary) {
1522 mtx_lock(&sscreen->shader_cache_mutex);
1523 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary, shader, true))
1524 FREE(tgsi_binary);
1525 mtx_unlock(&sscreen->shader_cache_mutex);
1526 }
1527 }
1528
1529 *si_get_main_shader_part(sel, &shader->key) = shader;
1530
1531 /* Unset "outputs_written" flags for outputs converted to
1532 * DEFAULT_VAL, so that later inter-shader optimizations don't
1533 * try to eliminate outputs that don't exist in the final
1534 * shader.
1535 *
1536 * This is only done if non-monolithic shaders are enabled.
1537 */
1538 if ((sel->type == PIPE_SHADER_VERTEX ||
1539 sel->type == PIPE_SHADER_TESS_EVAL) &&
1540 !shader->key.as_ls &&
1541 !shader->key.as_es) {
1542 unsigned i;
1543
1544 for (i = 0; i < sel->info.num_outputs; i++) {
1545 unsigned offset = shader->info.vs_output_param_offset[i];
1546
1547 if (offset <= AC_EXP_PARAM_OFFSET_31)
1548 continue;
1549
1550 unsigned name = sel->info.output_semantic_name[i];
1551 unsigned index = sel->info.output_semantic_index[i];
1552 unsigned id;
1553
1554 switch (name) {
1555 case TGSI_SEMANTIC_GENERIC:
1556 /* don't process indices the function can't handle */
1557 if (index >= 60)
1558 break;
1559 /* fall through */
1560 case TGSI_SEMANTIC_CLIPDIST:
1561 id = si_shader_io_get_unique_index(name, index);
1562 sel->outputs_written &= ~(1ull << id);
1563 break;
1564 case TGSI_SEMANTIC_POSITION: /* ignore these */
1565 case TGSI_SEMANTIC_PSIZE:
1566 case TGSI_SEMANTIC_CLIPVERTEX:
1567 case TGSI_SEMANTIC_EDGEFLAG:
1568 break;
1569 default:
1570 id = si_shader_io_get_unique_index2(name, index);
1571 sel->outputs_written2 &= ~(1u << id);
1572 }
1573 }
1574 }
1575 }
1576
1577 /* Pre-compilation. */
1578 if (sscreen->b.debug_flags & DBG_PRECOMPILE) {
1579 struct si_shader_ctx_state state = {sel};
1580 struct si_shader_key key;
1581
1582 memset(&key, 0, sizeof(key));
1583 si_parse_next_shader_property(&sel->info, &key);
1584
1585 /* Set reasonable defaults, so that the shader key doesn't
1586 * cause any code to be eliminated.
1587 */
1588 switch (sel->type) {
1589 case PIPE_SHADER_TESS_CTRL:
1590 key.part.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
1591 break;
1592 case PIPE_SHADER_FRAGMENT:
1593 key.part.ps.prolog.bc_optimize_for_persp =
1594 sel->info.uses_persp_center &&
1595 sel->info.uses_persp_centroid;
1596 key.part.ps.prolog.bc_optimize_for_linear =
1597 sel->info.uses_linear_center &&
1598 sel->info.uses_linear_centroid;
1599 key.part.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
1600 for (i = 0; i < 8; i++)
1601 if (sel->info.colors_written & (1 << i))
1602 key.part.ps.epilog.spi_shader_col_format |=
1603 V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
1604 break;
1605 }
1606
1607 if (si_shader_select_with_key(sscreen, &state,
1608 &sel->compiler_ctx_state, &key,
1609 thread_index))
1610 fprintf(stderr, "radeonsi: can't create a monolithic shader\n");
1611 }
1612
1613 /* The GS copy shader is always pre-compiled. */
1614 if (sel->type == PIPE_SHADER_GEOMETRY) {
1615 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, tm, sel, debug);
1616 if (!sel->gs_copy_shader) {
1617 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
1618 return;
1619 }
1620
1621 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
1622 }
1623 }
1624
1625 static void *si_create_shader_selector(struct pipe_context *ctx,
1626 const struct pipe_shader_state *state)
1627 {
1628 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
1629 struct si_context *sctx = (struct si_context*)ctx;
1630 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
1631 int i;
1632
1633 if (!sel)
1634 return NULL;
1635
1636 sel->screen = sscreen;
1637 sel->compiler_ctx_state.tm = sctx->tm;
1638 sel->compiler_ctx_state.debug = sctx->b.debug;
1639 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
1640 sel->tokens = tgsi_dup_tokens(state->tokens);
1641 if (!sel->tokens) {
1642 FREE(sel);
1643 return NULL;
1644 }
1645
1646 sel->so = state->stream_output;
1647 tgsi_scan_shader(state->tokens, &sel->info);
1648 sel->type = sel->info.processor;
1649 p_atomic_inc(&sscreen->b.num_shaders_created);
1650
1651 /* The prolog is a no-op if there are no inputs. */
1652 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
1653 sel->info.num_inputs;
1654
1655 /* Set which opcode uses which (i,j) pair. */
1656 if (sel->info.uses_persp_opcode_interp_centroid)
1657 sel->info.uses_persp_centroid = true;
1658
1659 if (sel->info.uses_linear_opcode_interp_centroid)
1660 sel->info.uses_linear_centroid = true;
1661
1662 if (sel->info.uses_persp_opcode_interp_offset ||
1663 sel->info.uses_persp_opcode_interp_sample)
1664 sel->info.uses_persp_center = true;
1665
1666 if (sel->info.uses_linear_opcode_interp_offset ||
1667 sel->info.uses_linear_opcode_interp_sample)
1668 sel->info.uses_linear_center = true;
1669
1670 switch (sel->type) {
1671 case PIPE_SHADER_GEOMETRY:
1672 sel->gs_output_prim =
1673 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
1674 sel->gs_max_out_vertices =
1675 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
1676 sel->gs_num_invocations =
1677 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
1678 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
1679 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
1680 sel->gs_max_out_vertices;
1681
1682 sel->max_gs_stream = 0;
1683 for (i = 0; i < sel->so.num_outputs; i++)
1684 sel->max_gs_stream = MAX2(sel->max_gs_stream,
1685 sel->so.output[i].stream);
1686
1687 sel->gs_input_verts_per_prim =
1688 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
1689 break;
1690
1691 case PIPE_SHADER_TESS_CTRL:
1692 /* Always reserve space for these. */
1693 sel->patch_outputs_written |=
1694 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0)) |
1695 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0));
1696 /* fall through */
1697 case PIPE_SHADER_VERTEX:
1698 case PIPE_SHADER_TESS_EVAL:
1699 for (i = 0; i < sel->info.num_outputs; i++) {
1700 unsigned name = sel->info.output_semantic_name[i];
1701 unsigned index = sel->info.output_semantic_index[i];
1702
1703 switch (name) {
1704 case TGSI_SEMANTIC_TESSINNER:
1705 case TGSI_SEMANTIC_TESSOUTER:
1706 case TGSI_SEMANTIC_PATCH:
1707 sel->patch_outputs_written |=
1708 1llu << si_shader_io_get_unique_index(name, index);
1709 break;
1710
1711 case TGSI_SEMANTIC_GENERIC:
1712 /* don't process indices the function can't handle */
1713 if (index >= 60)
1714 break;
1715 /* fall through */
1716 case TGSI_SEMANTIC_POSITION:
1717 case TGSI_SEMANTIC_PSIZE:
1718 case TGSI_SEMANTIC_CLIPDIST:
1719 sel->outputs_written |=
1720 1llu << si_shader_io_get_unique_index(name, index);
1721 break;
1722 case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */
1723 case TGSI_SEMANTIC_EDGEFLAG:
1724 break;
1725 default:
1726 sel->outputs_written2 |=
1727 1u << si_shader_io_get_unique_index2(name, index);
1728 }
1729 }
1730 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
1731 break;
1732
1733 case PIPE_SHADER_FRAGMENT:
1734 for (i = 0; i < sel->info.num_inputs; i++) {
1735 unsigned name = sel->info.input_semantic_name[i];
1736 unsigned index = sel->info.input_semantic_index[i];
1737
1738 switch (name) {
1739 case TGSI_SEMANTIC_CLIPDIST:
1740 case TGSI_SEMANTIC_GENERIC:
1741 sel->inputs_read |=
1742 1llu << si_shader_io_get_unique_index(name, index);
1743 break;
1744 case TGSI_SEMANTIC_PCOORD: /* ignore this */
1745 break;
1746 default:
1747 sel->inputs_read2 |=
1748 1u << si_shader_io_get_unique_index2(name, index);
1749 }
1750 }
1751
1752 for (i = 0; i < 8; i++)
1753 if (sel->info.colors_written & (1 << i))
1754 sel->colors_written_4bit |= 0xf << (4 * i);
1755
1756 for (i = 0; i < sel->info.num_inputs; i++) {
1757 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
1758 int index = sel->info.input_semantic_index[i];
1759 sel->color_attr_index[index] = i;
1760 }
1761 }
1762 break;
1763 }
1764
1765 /* DB_SHADER_CONTROL */
1766 sel->db_shader_control =
1767 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
1768 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
1769 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
1770 S_02880C_KILL_ENABLE(sel->info.uses_kill);
1771
1772 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
1773 case TGSI_FS_DEPTH_LAYOUT_GREATER:
1774 sel->db_shader_control |=
1775 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
1776 break;
1777 case TGSI_FS_DEPTH_LAYOUT_LESS:
1778 sel->db_shader_control |=
1779 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
1780 break;
1781 }
1782
1783 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
1784 *
1785 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
1786 * --|-----------|------------|------------|--------------------|-------------------|-------------
1787 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
1788 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
1789 * 2 | false | true | n/a | LateZ | 1 | 0
1790 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
1791 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
1792 *
1793 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
1794 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
1795 *
1796 * Don't use ReZ without profiling !!!
1797 *
1798 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
1799 * shaders.
1800 */
1801 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
1802 /* Cases 3, 4. */
1803 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
1804 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
1805 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
1806 } else if (sel->info.writes_memory) {
1807 /* Case 2. */
1808 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
1809 S_02880C_EXEC_ON_HIER_FAIL(1);
1810 } else {
1811 /* Case 1. */
1812 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
1813 }
1814
1815 (void) mtx_init(&sel->mutex, mtx_plain);
1816 util_queue_fence_init(&sel->ready);
1817
1818 if ((sctx->b.debug.debug_message && !sctx->b.debug.async) ||
1819 sctx->is_debug ||
1820 r600_can_dump_shader(&sscreen->b, sel->info.processor))
1821 si_init_shader_selector_async(sel, -1);
1822 else
1823 util_queue_add_job(&sscreen->shader_compiler_queue, sel,
1824 &sel->ready, si_init_shader_selector_async,
1825 NULL);
1826
1827 return sel;
1828 }
1829
1830 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
1831 {
1832 struct si_context *sctx = (struct si_context *)ctx;
1833 struct si_shader_selector *sel = state;
1834
1835 if (sctx->vs_shader.cso == sel)
1836 return;
1837
1838 sctx->vs_shader.cso = sel;
1839 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
1840 sctx->do_update_shaders = true;
1841 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1842 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1843 }
1844
1845 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
1846 {
1847 struct si_context *sctx = (struct si_context *)ctx;
1848 struct si_shader_selector *sel = state;
1849 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
1850
1851 if (sctx->gs_shader.cso == sel)
1852 return;
1853
1854 sctx->gs_shader.cso = sel;
1855 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
1856 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
1857 sctx->do_update_shaders = true;
1858 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1859 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1860
1861 if (enable_changed)
1862 si_shader_change_notify(sctx);
1863 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1864 }
1865
1866 static void si_update_tcs_tes_uses_prim_id(struct si_context *sctx)
1867 {
1868 sctx->ia_multi_vgt_param_key.u.tcs_tes_uses_prim_id =
1869 (sctx->tes_shader.cso &&
1870 sctx->tes_shader.cso->info.uses_primid) ||
1871 (sctx->tcs_shader.cso &&
1872 sctx->tcs_shader.cso->info.uses_primid);
1873 }
1874
1875 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
1876 {
1877 struct si_context *sctx = (struct si_context *)ctx;
1878 struct si_shader_selector *sel = state;
1879 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
1880
1881 if (sctx->tcs_shader.cso == sel)
1882 return;
1883
1884 sctx->tcs_shader.cso = sel;
1885 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
1886 si_update_tcs_tes_uses_prim_id(sctx);
1887 sctx->do_update_shaders = true;
1888
1889 if (enable_changed)
1890 sctx->last_tcs = NULL; /* invalidate derived tess state */
1891 }
1892
1893 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
1894 {
1895 struct si_context *sctx = (struct si_context *)ctx;
1896 struct si_shader_selector *sel = state;
1897 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
1898
1899 if (sctx->tes_shader.cso == sel)
1900 return;
1901
1902 sctx->tes_shader.cso = sel;
1903 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
1904 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
1905 si_update_tcs_tes_uses_prim_id(sctx);
1906 sctx->do_update_shaders = true;
1907 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1908 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1909
1910 if (enable_changed) {
1911 si_shader_change_notify(sctx);
1912 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
1913 }
1914 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1915 }
1916
1917 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
1918 {
1919 struct si_context *sctx = (struct si_context *)ctx;
1920 struct si_shader_selector *sel = state;
1921
1922 /* skip if supplied shader is one already in use */
1923 if (sctx->ps_shader.cso == sel)
1924 return;
1925
1926 sctx->ps_shader.cso = sel;
1927 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
1928 sctx->do_update_shaders = true;
1929 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
1930 }
1931
1932 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
1933 {
1934 if (shader->is_optimized) {
1935 util_queue_fence_wait(&shader->optimized_ready);
1936 util_queue_fence_destroy(&shader->optimized_ready);
1937 }
1938
1939 if (shader->pm4) {
1940 switch (shader->selector->type) {
1941 case PIPE_SHADER_VERTEX:
1942 if (shader->key.as_ls) {
1943 assert(sctx->b.chip_class <= VI);
1944 si_pm4_delete_state(sctx, ls, shader->pm4);
1945 } else if (shader->key.as_es) {
1946 assert(sctx->b.chip_class <= VI);
1947 si_pm4_delete_state(sctx, es, shader->pm4);
1948 } else {
1949 si_pm4_delete_state(sctx, vs, shader->pm4);
1950 }
1951 break;
1952 case PIPE_SHADER_TESS_CTRL:
1953 si_pm4_delete_state(sctx, hs, shader->pm4);
1954 break;
1955 case PIPE_SHADER_TESS_EVAL:
1956 if (shader->key.as_es) {
1957 assert(sctx->b.chip_class <= VI);
1958 si_pm4_delete_state(sctx, es, shader->pm4);
1959 } else {
1960 si_pm4_delete_state(sctx, vs, shader->pm4);
1961 }
1962 break;
1963 case PIPE_SHADER_GEOMETRY:
1964 if (shader->is_gs_copy_shader)
1965 si_pm4_delete_state(sctx, vs, shader->pm4);
1966 else
1967 si_pm4_delete_state(sctx, gs, shader->pm4);
1968 break;
1969 case PIPE_SHADER_FRAGMENT:
1970 si_pm4_delete_state(sctx, ps, shader->pm4);
1971 break;
1972 }
1973 }
1974
1975 si_shader_destroy(shader);
1976 free(shader);
1977 }
1978
1979 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
1980 {
1981 struct si_context *sctx = (struct si_context *)ctx;
1982 struct si_shader_selector *sel = (struct si_shader_selector *)state;
1983 struct si_shader *p = sel->first_variant, *c;
1984 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
1985 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
1986 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
1987 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
1988 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
1989 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
1990 };
1991
1992 util_queue_fence_wait(&sel->ready);
1993
1994 if (current_shader[sel->type]->cso == sel) {
1995 current_shader[sel->type]->cso = NULL;
1996 current_shader[sel->type]->current = NULL;
1997 }
1998
1999 while (p) {
2000 c = p->next_variant;
2001 si_delete_shader(sctx, p);
2002 p = c;
2003 }
2004
2005 if (sel->main_shader_part)
2006 si_delete_shader(sctx, sel->main_shader_part);
2007 if (sel->main_shader_part_ls)
2008 si_delete_shader(sctx, sel->main_shader_part_ls);
2009 if (sel->main_shader_part_es)
2010 si_delete_shader(sctx, sel->main_shader_part_es);
2011 if (sel->gs_copy_shader)
2012 si_delete_shader(sctx, sel->gs_copy_shader);
2013
2014 util_queue_fence_destroy(&sel->ready);
2015 mtx_destroy(&sel->mutex);
2016 free(sel->tokens);
2017 free(sel);
2018 }
2019
2020 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
2021 struct si_shader *vs, unsigned name,
2022 unsigned index, unsigned interpolate)
2023 {
2024 struct tgsi_shader_info *vsinfo = &vs->selector->info;
2025 unsigned j, offset, ps_input_cntl = 0;
2026
2027 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
2028 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
2029 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2030
2031 if (name == TGSI_SEMANTIC_PCOORD ||
2032 (name == TGSI_SEMANTIC_TEXCOORD &&
2033 sctx->sprite_coord_enable & (1 << index))) {
2034 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
2035 }
2036
2037 for (j = 0; j < vsinfo->num_outputs; j++) {
2038 if (name == vsinfo->output_semantic_name[j] &&
2039 index == vsinfo->output_semantic_index[j]) {
2040 offset = vs->info.vs_output_param_offset[j];
2041
2042 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2043 /* The input is loaded from parameter memory. */
2044 ps_input_cntl |= S_028644_OFFSET(offset);
2045 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2046 if (offset == AC_EXP_PARAM_UNDEFINED) {
2047 /* This can happen with depth-only rendering. */
2048 offset = 0;
2049 } else {
2050 /* The input is a DEFAULT_VAL constant. */
2051 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2052 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2053 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2054 }
2055
2056 ps_input_cntl = S_028644_OFFSET(0x20) |
2057 S_028644_DEFAULT_VAL(offset);
2058 }
2059 break;
2060 }
2061 }
2062
2063 if (name == TGSI_SEMANTIC_PRIMID)
2064 /* PrimID is written after the last output. */
2065 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
2066 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2067 /* No corresponding output found, load defaults into input.
2068 * Don't set any other bits.
2069 * (FLAT_SHADE=1 completely changes behavior) */
2070 ps_input_cntl = S_028644_OFFSET(0x20);
2071 /* D3D 9 behaviour. GL is undefined */
2072 if (name == TGSI_SEMANTIC_COLOR && index == 0)
2073 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
2074 }
2075 return ps_input_cntl;
2076 }
2077
2078 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
2079 {
2080 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2081 struct si_shader *ps = sctx->ps_shader.current;
2082 struct si_shader *vs = si_get_vs_state(sctx);
2083 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
2084 unsigned i, num_interp, num_written = 0, bcol_interp[2];
2085
2086 if (!ps || !ps->selector->info.num_inputs)
2087 return;
2088
2089 num_interp = si_get_ps_num_interp(ps);
2090 assert(num_interp > 0);
2091 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
2092
2093 for (i = 0; i < psinfo->num_inputs; i++) {
2094 unsigned name = psinfo->input_semantic_name[i];
2095 unsigned index = psinfo->input_semantic_index[i];
2096 unsigned interpolate = psinfo->input_interpolate[i];
2097
2098 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
2099 interpolate));
2100 num_written++;
2101
2102 if (name == TGSI_SEMANTIC_COLOR) {
2103 assert(index < ARRAY_SIZE(bcol_interp));
2104 bcol_interp[index] = interpolate;
2105 }
2106 }
2107
2108 if (ps->key.part.ps.prolog.color_two_side) {
2109 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
2110
2111 for (i = 0; i < 2; i++) {
2112 if (!(psinfo->colors_read & (0xf << (i * 4))))
2113 continue;
2114
2115 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
2116 i, bcol_interp[i]));
2117 num_written++;
2118 }
2119 }
2120 assert(num_interp == num_written);
2121 }
2122
2123 /**
2124 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2125 */
2126 static void si_init_config_add_vgt_flush(struct si_context *sctx)
2127 {
2128 if (sctx->init_config_has_vgt_flush)
2129 return;
2130
2131 /* Done by Vulkan before VGT_FLUSH. */
2132 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2133 si_pm4_cmd_add(sctx->init_config,
2134 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2135 si_pm4_cmd_end(sctx->init_config, false);
2136
2137 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2138 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2139 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2140 si_pm4_cmd_end(sctx->init_config, false);
2141 sctx->init_config_has_vgt_flush = true;
2142 }
2143
2144 /* Initialize state related to ESGS / GSVS ring buffers */
2145 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2146 {
2147 struct si_shader_selector *es =
2148 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2149 struct si_shader_selector *gs = sctx->gs_shader.cso;
2150 struct si_pm4_state *pm4;
2151
2152 /* Chip constants. */
2153 unsigned num_se = sctx->screen->b.info.max_se;
2154 unsigned wave_size = 64;
2155 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2156 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2157 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2158 */
2159 unsigned gs_vertex_reuse = (sctx->b.chip_class >= VI ? 32 : 16) * num_se;
2160 unsigned alignment = 256 * num_se;
2161 /* The maximum size is 63.999 MB per SE. */
2162 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2163
2164 /* Calculate the minimum size. */
2165 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
2166 wave_size, alignment);
2167
2168 /* These are recommended sizes, not minimum sizes. */
2169 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2170 es->esgs_itemsize * gs->gs_input_verts_per_prim;
2171 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2172 gs->max_gsvs_emit_size;
2173
2174 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2175 esgs_ring_size = align(esgs_ring_size, alignment);
2176 gsvs_ring_size = align(gsvs_ring_size, alignment);
2177
2178 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2179 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2180
2181 /* Some rings don't have to be allocated if shaders don't use them.
2182 * (e.g. no varyings between ES and GS or GS and VS)
2183 *
2184 * GFX9 doesn't have the ESGS ring.
2185 */
2186 bool update_esgs = sctx->b.chip_class <= VI &&
2187 esgs_ring_size &&
2188 (!sctx->esgs_ring ||
2189 sctx->esgs_ring->width0 < esgs_ring_size);
2190 bool update_gsvs = gsvs_ring_size &&
2191 (!sctx->gsvs_ring ||
2192 sctx->gsvs_ring->width0 < gsvs_ring_size);
2193
2194 if (!update_esgs && !update_gsvs)
2195 return true;
2196
2197 if (update_esgs) {
2198 pipe_resource_reference(&sctx->esgs_ring, NULL);
2199 sctx->esgs_ring =
2200 r600_aligned_buffer_create(sctx->b.b.screen,
2201 R600_RESOURCE_FLAG_UNMAPPABLE,
2202 PIPE_USAGE_DEFAULT,
2203 esgs_ring_size, alignment);
2204 if (!sctx->esgs_ring)
2205 return false;
2206 }
2207
2208 if (update_gsvs) {
2209 pipe_resource_reference(&sctx->gsvs_ring, NULL);
2210 sctx->gsvs_ring =
2211 r600_aligned_buffer_create(sctx->b.b.screen,
2212 R600_RESOURCE_FLAG_UNMAPPABLE,
2213 PIPE_USAGE_DEFAULT,
2214 gsvs_ring_size, alignment);
2215 if (!sctx->gsvs_ring)
2216 return false;
2217 }
2218
2219 /* Create the "init_config_gs_rings" state. */
2220 pm4 = CALLOC_STRUCT(si_pm4_state);
2221 if (!pm4)
2222 return false;
2223
2224 if (sctx->b.chip_class >= CIK) {
2225 if (sctx->esgs_ring) {
2226 assert(sctx->b.chip_class <= VI);
2227 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2228 sctx->esgs_ring->width0 / 256);
2229 }
2230 if (sctx->gsvs_ring)
2231 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2232 sctx->gsvs_ring->width0 / 256);
2233 } else {
2234 if (sctx->esgs_ring)
2235 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2236 sctx->esgs_ring->width0 / 256);
2237 if (sctx->gsvs_ring)
2238 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2239 sctx->gsvs_ring->width0 / 256);
2240 }
2241
2242 /* Set the state. */
2243 if (sctx->init_config_gs_rings)
2244 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
2245 sctx->init_config_gs_rings = pm4;
2246
2247 if (!sctx->init_config_has_vgt_flush) {
2248 si_init_config_add_vgt_flush(sctx);
2249 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2250 }
2251
2252 /* Flush the context to re-emit both init_config states. */
2253 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2254 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2255
2256 /* Set ring bindings. */
2257 if (sctx->esgs_ring) {
2258 assert(sctx->b.chip_class <= VI);
2259 si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
2260 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2261 true, true, 4, 64, 0);
2262 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
2263 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2264 false, false, 0, 0, 0);
2265 }
2266 if (sctx->gsvs_ring) {
2267 si_set_ring_buffer(&sctx->b.b, SI_RING_GSVS,
2268 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
2269 false, false, 0, 0, 0);
2270 }
2271
2272 return true;
2273 }
2274
2275 /**
2276 * @returns 1 if \p sel has been updated to use a new scratch buffer
2277 * 0 if not
2278 * < 0 if there was a failure
2279 */
2280 static int si_update_scratch_buffer(struct si_context *sctx,
2281 struct si_shader *shader)
2282 {
2283 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
2284 int r;
2285
2286 if (!shader)
2287 return 0;
2288
2289 /* This shader doesn't need a scratch buffer */
2290 if (shader->config.scratch_bytes_per_wave == 0)
2291 return 0;
2292
2293 /* This shader is already configured to use the current
2294 * scratch buffer. */
2295 if (shader->scratch_bo == sctx->scratch_buffer)
2296 return 0;
2297
2298 assert(sctx->scratch_buffer);
2299
2300 si_shader_apply_scratch_relocs(sctx, shader, &shader->config, scratch_va);
2301
2302 /* Replace the shader bo with a new bo that has the relocs applied. */
2303 r = si_shader_binary_upload(sctx->screen, shader);
2304 if (r)
2305 return r;
2306
2307 /* Update the shader state to use the new shader bo. */
2308 si_shader_init_pm4_state(sctx->screen, shader);
2309
2310 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
2311
2312 return 1;
2313 }
2314
2315 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
2316 {
2317 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
2318 }
2319
2320 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
2321 {
2322 return shader ? shader->config.scratch_bytes_per_wave : 0;
2323 }
2324
2325 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
2326 {
2327 unsigned bytes = 0;
2328
2329 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
2330 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
2331 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
2332 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tcs_shader.current));
2333 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
2334 return bytes;
2335 }
2336
2337 static bool si_update_spi_tmpring_size(struct si_context *sctx)
2338 {
2339 unsigned current_scratch_buffer_size =
2340 si_get_current_scratch_buffer_size(sctx);
2341 unsigned scratch_bytes_per_wave =
2342 si_get_max_scratch_bytes_per_wave(sctx);
2343 unsigned scratch_needed_size = scratch_bytes_per_wave *
2344 sctx->scratch_waves;
2345 unsigned spi_tmpring_size;
2346 int r;
2347
2348 if (scratch_needed_size > 0) {
2349 if (scratch_needed_size > current_scratch_buffer_size) {
2350 /* Create a bigger scratch buffer */
2351 r600_resource_reference(&sctx->scratch_buffer, NULL);
2352
2353 sctx->scratch_buffer = (struct r600_resource*)
2354 r600_aligned_buffer_create(&sctx->screen->b.b,
2355 R600_RESOURCE_FLAG_UNMAPPABLE,
2356 PIPE_USAGE_DEFAULT,
2357 scratch_needed_size, 256);
2358 if (!sctx->scratch_buffer)
2359 return false;
2360
2361 si_mark_atom_dirty(sctx, &sctx->scratch_state);
2362 r600_context_add_resource_size(&sctx->b.b,
2363 &sctx->scratch_buffer->b.b);
2364 }
2365
2366 /* Update the shaders, so they are using the latest scratch. The
2367 * scratch buffer may have been changed since these shaders were
2368 * last used, so we still need to try to update them, even if
2369 * they require scratch buffers smaller than the current size.
2370 */
2371 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
2372 if (r < 0)
2373 return false;
2374 if (r == 1)
2375 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2376
2377 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
2378 if (r < 0)
2379 return false;
2380 if (r == 1)
2381 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2382
2383 r = si_update_scratch_buffer(sctx, sctx->tcs_shader.current);
2384 if (r < 0)
2385 return false;
2386 if (r == 1)
2387 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
2388
2389 /* VS can be bound as LS, ES, or VS. */
2390 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
2391 if (r < 0)
2392 return false;
2393 if (r == 1) {
2394 if (sctx->tes_shader.current)
2395 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2396 else if (sctx->gs_shader.current)
2397 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2398 else
2399 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2400 }
2401
2402 /* TES can be bound as ES or VS. */
2403 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
2404 if (r < 0)
2405 return false;
2406 if (r == 1) {
2407 if (sctx->gs_shader.current)
2408 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2409 else
2410 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2411 }
2412 }
2413
2414 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
2415 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
2416 "scratch size should already be aligned correctly.");
2417
2418 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
2419 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
2420 if (spi_tmpring_size != sctx->spi_tmpring_size) {
2421 sctx->spi_tmpring_size = spi_tmpring_size;
2422 si_mark_atom_dirty(sctx, &sctx->scratch_state);
2423 }
2424 return true;
2425 }
2426
2427 static void si_init_tess_factor_ring(struct si_context *sctx)
2428 {
2429 bool double_offchip_buffers = sctx->b.chip_class >= CIK &&
2430 sctx->b.family != CHIP_CARRIZO &&
2431 sctx->b.family != CHIP_STONEY;
2432 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2433 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
2434 sctx->screen->b.info.max_se;
2435 unsigned offchip_granularity;
2436
2437 switch (sctx->screen->tess_offchip_block_dw_size) {
2438 default:
2439 assert(0);
2440 /* fall through */
2441 case 8192:
2442 offchip_granularity = V_03093C_X_8K_DWORDS;
2443 break;
2444 case 4096:
2445 offchip_granularity = V_03093C_X_4K_DWORDS;
2446 break;
2447 }
2448
2449 switch (sctx->b.chip_class) {
2450 case SI:
2451 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2452 break;
2453 case CIK:
2454 case VI:
2455 case GFX9:
2456 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2457 break;
2458 default:
2459 assert(0);
2460 return;
2461 }
2462
2463 assert(!sctx->tf_ring);
2464 sctx->tf_ring = r600_aligned_buffer_create(sctx->b.b.screen,
2465 R600_RESOURCE_FLAG_UNMAPPABLE,
2466 PIPE_USAGE_DEFAULT,
2467 32768 * sctx->screen->b.info.max_se,
2468 256);
2469 if (!sctx->tf_ring)
2470 return;
2471
2472 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
2473
2474 sctx->tess_offchip_ring =
2475 r600_aligned_buffer_create(sctx->b.b.screen,
2476 R600_RESOURCE_FLAG_UNMAPPABLE,
2477 PIPE_USAGE_DEFAULT,
2478 max_offchip_buffers *
2479 sctx->screen->tess_offchip_block_dw_size * 4,
2480 256);
2481 if (!sctx->tess_offchip_ring)
2482 return;
2483
2484 si_init_config_add_vgt_flush(sctx);
2485
2486 /* Append these registers to the init config state. */
2487 if (sctx->b.chip_class >= CIK) {
2488 if (sctx->b.chip_class >= VI)
2489 --max_offchip_buffers;
2490
2491 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
2492 S_030938_SIZE(sctx->tf_ring->width0 / 4));
2493 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
2494 r600_resource(sctx->tf_ring)->gpu_address >> 8);
2495 if (sctx->b.chip_class >= GFX9)
2496 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
2497 r600_resource(sctx->tf_ring)->gpu_address >> 40);
2498 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
2499 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2500 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity));
2501 } else {
2502 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
2503 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
2504 S_008988_SIZE(sctx->tf_ring->width0 / 4));
2505 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
2506 r600_resource(sctx->tf_ring)->gpu_address >> 8);
2507 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2508 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers));
2509 }
2510
2511 /* Flush the context to re-emit the init_config state.
2512 * This is done only once in a lifetime of a context.
2513 */
2514 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2515 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2516 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2517
2518 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_FACTOR, sctx->tf_ring,
2519 0, sctx->tf_ring->width0, false, false, 0, 0, 0);
2520
2521 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_OFFCHIP,
2522 sctx->tess_offchip_ring, 0,
2523 sctx->tess_offchip_ring->width0, false, false, 0, 0, 0);
2524 }
2525
2526 /**
2527 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
2528 * VS passes its outputs to TES directly, so the fixed-function shader only
2529 * has to write TESSOUTER and TESSINNER.
2530 */
2531 static void si_generate_fixed_func_tcs(struct si_context *sctx)
2532 {
2533 struct ureg_src outer, inner;
2534 struct ureg_dst tessouter, tessinner;
2535 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
2536
2537 if (!ureg)
2538 return; /* if we get here, we're screwed */
2539
2540 assert(!sctx->fixed_func_tcs_shader.cso);
2541
2542 outer = ureg_DECL_system_value(ureg,
2543 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
2544 inner = ureg_DECL_system_value(ureg,
2545 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
2546
2547 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
2548 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
2549
2550 ureg_MOV(ureg, tessouter, outer);
2551 ureg_MOV(ureg, tessinner, inner);
2552 ureg_END(ureg);
2553
2554 sctx->fixed_func_tcs_shader.cso =
2555 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
2556 }
2557
2558 static void si_update_vgt_shader_config(struct si_context *sctx)
2559 {
2560 /* Calculate the index of the config.
2561 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
2562 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
2563 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
2564
2565 if (!*pm4) {
2566 uint32_t stages = 0;
2567
2568 *pm4 = CALLOC_STRUCT(si_pm4_state);
2569
2570 if (sctx->tes_shader.cso) {
2571 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2572 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2573
2574 if (sctx->gs_shader.cso)
2575 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2576 S_028B54_GS_EN(1) |
2577 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2578 else
2579 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2580 } else if (sctx->gs_shader.cso) {
2581 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2582 S_028B54_GS_EN(1) |
2583 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2584 }
2585
2586 if (sctx->b.chip_class >= GFX9)
2587 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
2588
2589 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
2590 }
2591 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
2592 }
2593
2594 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
2595 {
2596 struct pipe_stream_output_info *so = &shader->so;
2597 uint32_t enabled_stream_buffers_mask = 0;
2598 int i;
2599
2600 for (i = 0; i < so->num_outputs; i++)
2601 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
2602 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
2603 sctx->b.streamout.stride_in_dw = shader->so.stride;
2604 }
2605
2606 bool si_update_shaders(struct si_context *sctx)
2607 {
2608 struct pipe_context *ctx = (struct pipe_context*)sctx;
2609 struct si_compiler_ctx_state compiler_state;
2610 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2611 struct si_shader *old_vs = si_get_vs_state(sctx);
2612 bool old_clip_disable = old_vs ? old_vs->key.opt.hw_vs.clip_disable : false;
2613 int r;
2614
2615 compiler_state.tm = sctx->tm;
2616 compiler_state.debug = sctx->b.debug;
2617 compiler_state.is_debug_context = sctx->is_debug;
2618
2619 /* Update stages before GS. */
2620 if (sctx->tes_shader.cso) {
2621 if (!sctx->tf_ring) {
2622 si_init_tess_factor_ring(sctx);
2623 if (!sctx->tf_ring)
2624 return false;
2625 }
2626
2627 /* VS as LS */
2628 if (sctx->b.chip_class <= VI) {
2629 r = si_shader_select(ctx, &sctx->vs_shader,
2630 &compiler_state);
2631 if (r)
2632 return false;
2633 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2634 }
2635
2636 if (sctx->tcs_shader.cso) {
2637 r = si_shader_select(ctx, &sctx->tcs_shader,
2638 &compiler_state);
2639 if (r)
2640 return false;
2641 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
2642 } else {
2643 if (!sctx->fixed_func_tcs_shader.cso) {
2644 si_generate_fixed_func_tcs(sctx);
2645 if (!sctx->fixed_func_tcs_shader.cso)
2646 return false;
2647 }
2648
2649 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
2650 &compiler_state);
2651 if (r)
2652 return false;
2653 si_pm4_bind_state(sctx, hs,
2654 sctx->fixed_func_tcs_shader.current->pm4);
2655 }
2656
2657 if (sctx->gs_shader.cso) {
2658 /* TES as ES */
2659 if (sctx->b.chip_class <= VI) {
2660 r = si_shader_select(ctx, &sctx->tes_shader,
2661 &compiler_state);
2662 if (r)
2663 return false;
2664 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2665 }
2666 } else {
2667 /* TES as VS */
2668 r = si_shader_select(ctx, &sctx->tes_shader,
2669 &compiler_state);
2670 if (r)
2671 return false;
2672 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2673 si_update_so(sctx, sctx->tes_shader.cso);
2674 }
2675 } else if (sctx->gs_shader.cso) {
2676 if (sctx->b.chip_class <= VI) {
2677 /* VS as ES */
2678 r = si_shader_select(ctx, &sctx->vs_shader,
2679 &compiler_state);
2680 if (r)
2681 return false;
2682 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2683
2684 si_pm4_bind_state(sctx, ls, NULL);
2685 si_pm4_bind_state(sctx, hs, NULL);
2686 }
2687 } else {
2688 /* VS as VS */
2689 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
2690 if (r)
2691 return false;
2692 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2693 si_update_so(sctx, sctx->vs_shader.cso);
2694
2695 si_pm4_bind_state(sctx, ls, NULL);
2696 si_pm4_bind_state(sctx, hs, NULL);
2697 }
2698
2699 /* Update GS. */
2700 if (sctx->gs_shader.cso) {
2701 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
2702 if (r)
2703 return false;
2704 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2705 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
2706 si_update_so(sctx, sctx->gs_shader.cso);
2707
2708 if (!si_update_gs_ring_buffers(sctx))
2709 return false;
2710 } else {
2711 si_pm4_bind_state(sctx, gs, NULL);
2712 if (sctx->b.chip_class <= VI)
2713 si_pm4_bind_state(sctx, es, NULL);
2714 }
2715
2716 si_update_vgt_shader_config(sctx);
2717
2718 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.hw_vs.clip_disable)
2719 si_mark_atom_dirty(sctx, &sctx->clip_regs);
2720
2721 if (sctx->ps_shader.cso) {
2722 unsigned db_shader_control;
2723
2724 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
2725 if (r)
2726 return false;
2727 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2728
2729 db_shader_control =
2730 sctx->ps_shader.cso->db_shader_control |
2731 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
2732
2733 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
2734 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
2735 sctx->flatshade != rs->flatshade) {
2736 sctx->sprite_coord_enable = rs->sprite_coord_enable;
2737 sctx->flatshade = rs->flatshade;
2738 si_mark_atom_dirty(sctx, &sctx->spi_map);
2739 }
2740
2741 if (sctx->screen->b.rbplus_allowed && si_pm4_state_changed(sctx, ps))
2742 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2743
2744 if (sctx->ps_db_shader_control != db_shader_control) {
2745 sctx->ps_db_shader_control = db_shader_control;
2746 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2747 }
2748
2749 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
2750 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
2751 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2752
2753 if (sctx->b.chip_class == SI)
2754 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2755
2756 if (sctx->framebuffer.nr_samples <= 1)
2757 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2758 }
2759 }
2760
2761 if (si_pm4_state_changed(sctx, ls) ||
2762 si_pm4_state_changed(sctx, hs) ||
2763 si_pm4_state_changed(sctx, es) ||
2764 si_pm4_state_changed(sctx, gs) ||
2765 si_pm4_state_changed(sctx, vs) ||
2766 si_pm4_state_changed(sctx, ps)) {
2767 if (!si_update_spi_tmpring_size(sctx))
2768 return false;
2769 }
2770
2771 if (sctx->b.chip_class >= CIK)
2772 si_mark_atom_dirty(sctx, &sctx->prefetch_L2);
2773
2774 sctx->do_update_shaders = false;
2775 return true;
2776 }
2777
2778 static void si_emit_scratch_state(struct si_context *sctx,
2779 struct r600_atom *atom)
2780 {
2781 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2782
2783 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
2784 sctx->spi_tmpring_size);
2785
2786 if (sctx->scratch_buffer) {
2787 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2788 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
2789 RADEON_PRIO_SCRATCH_BUFFER);
2790 }
2791 }
2792
2793 void si_init_shader_functions(struct si_context *sctx)
2794 {
2795 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
2796 si_init_atom(sctx, &sctx->scratch_state, &sctx->atoms.s.scratch_state,
2797 si_emit_scratch_state);
2798
2799 sctx->b.b.create_vs_state = si_create_shader_selector;
2800 sctx->b.b.create_tcs_state = si_create_shader_selector;
2801 sctx->b.b.create_tes_state = si_create_shader_selector;
2802 sctx->b.b.create_gs_state = si_create_shader_selector;
2803 sctx->b.b.create_fs_state = si_create_shader_selector;
2804
2805 sctx->b.b.bind_vs_state = si_bind_vs_shader;
2806 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
2807 sctx->b.b.bind_tes_state = si_bind_tes_shader;
2808 sctx->b.b.bind_gs_state = si_bind_gs_shader;
2809 sctx->b.b.bind_fs_state = si_bind_ps_shader;
2810
2811 sctx->b.b.delete_vs_state = si_delete_shader_selector;
2812 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
2813 sctx->b.b.delete_tes_state = si_delete_shader_selector;
2814 sctx->b.b.delete_gs_state = si_delete_shader_selector;
2815 sctx->b.b.delete_fs_state = si_delete_shader_selector;
2816 }