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a6480b330cd2be02005cba8d0777c65cc2bea889
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "si_shader.h"
30 #include "sid.h"
31
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_ureg.h"
34 #include "util/u_memory.h"
35 #include "util/u_simple_shaders.h"
36
37 static void si_set_tesseval_regs(struct si_shader *shader,
38 struct si_pm4_state *pm4)
39 {
40 struct tgsi_shader_info *info = &shader->selector->info;
41 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
42 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
43 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
44 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
45 unsigned type, partitioning, topology;
46
47 switch (tes_prim_mode) {
48 case PIPE_PRIM_LINES:
49 type = V_028B6C_TESS_ISOLINE;
50 break;
51 case PIPE_PRIM_TRIANGLES:
52 type = V_028B6C_TESS_TRIANGLE;
53 break;
54 case PIPE_PRIM_QUADS:
55 type = V_028B6C_TESS_QUAD;
56 break;
57 default:
58 assert(0);
59 return;
60 }
61
62 switch (tes_spacing) {
63 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
64 partitioning = V_028B6C_PART_FRAC_ODD;
65 break;
66 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
67 partitioning = V_028B6C_PART_FRAC_EVEN;
68 break;
69 case PIPE_TESS_SPACING_EQUAL:
70 partitioning = V_028B6C_PART_INTEGER;
71 break;
72 default:
73 assert(0);
74 return;
75 }
76
77 if (tes_point_mode)
78 topology = V_028B6C_OUTPUT_POINT;
79 else if (tes_prim_mode == PIPE_PRIM_LINES)
80 topology = V_028B6C_OUTPUT_LINE;
81 else if (tes_vertex_order_cw)
82 /* for some reason, this must be the other way around */
83 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
84 else
85 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
86
87 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
88 S_028B6C_TYPE(type) |
89 S_028B6C_PARTITIONING(partitioning) |
90 S_028B6C_TOPOLOGY(topology));
91 }
92
93 static void si_shader_ls(struct si_shader *shader)
94 {
95 struct si_pm4_state *pm4;
96 unsigned num_sgprs, num_user_sgprs;
97 unsigned vgpr_comp_cnt;
98 uint64_t va;
99
100 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
101 if (pm4 == NULL)
102 return;
103
104 va = shader->bo->gpu_address;
105 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
106
107 /* We need at least 2 components for LS.
108 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
109 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 1;
110
111 num_user_sgprs = SI_LS_NUM_USER_SGPR;
112 num_sgprs = shader->num_sgprs;
113 if (num_user_sgprs > num_sgprs) {
114 /* Last 2 reserved SGPRs are used for VCC */
115 num_sgprs = num_user_sgprs + 2;
116 }
117 assert(num_sgprs <= 104);
118
119 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
120 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
121
122 shader->ls_rsrc1 = S_00B528_VGPRS((shader->num_vgprs - 1) / 4) |
123 S_00B528_SGPRS((num_sgprs - 1) / 8) |
124 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt);
125 shader->ls_rsrc2 = S_00B52C_USER_SGPR(num_user_sgprs) |
126 S_00B52C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0);
127 }
128
129 static void si_shader_hs(struct si_shader *shader)
130 {
131 struct si_pm4_state *pm4;
132 unsigned num_sgprs, num_user_sgprs;
133 uint64_t va;
134
135 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
136 if (pm4 == NULL)
137 return;
138
139 va = shader->bo->gpu_address;
140 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
141
142 num_user_sgprs = SI_TCS_NUM_USER_SGPR;
143 num_sgprs = shader->num_sgprs;
144 /* One SGPR after user SGPRs is pre-loaded with tessellation factor
145 * buffer offset. */
146 if ((num_user_sgprs + 1) > num_sgprs) {
147 /* Last 2 reserved SGPRs are used for VCC */
148 num_sgprs = num_user_sgprs + 1 + 2;
149 }
150 assert(num_sgprs <= 104);
151
152 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
153 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
154 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
155 S_00B428_VGPRS((shader->num_vgprs - 1) / 4) |
156 S_00B428_SGPRS((num_sgprs - 1) / 8));
157 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
158 S_00B42C_USER_SGPR(num_user_sgprs) |
159 S_00B42C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
160 }
161
162 static void si_shader_es(struct si_shader *shader)
163 {
164 struct si_pm4_state *pm4;
165 unsigned num_sgprs, num_user_sgprs;
166 unsigned vgpr_comp_cnt;
167 uint64_t va;
168
169 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
170
171 if (pm4 == NULL)
172 return;
173
174 va = shader->bo->gpu_address;
175 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
176
177 if (shader->selector->type == PIPE_SHADER_VERTEX) {
178 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
179 num_user_sgprs = SI_VS_NUM_USER_SGPR;
180 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
181 vgpr_comp_cnt = 3; /* all components are needed for TES */
182 num_user_sgprs = SI_TES_NUM_USER_SGPR;
183 } else
184 assert(0);
185
186 num_sgprs = shader->num_sgprs;
187 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
188 if ((num_user_sgprs + 1) > num_sgprs) {
189 /* Last 2 reserved SGPRs are used for VCC */
190 num_sgprs = num_user_sgprs + 1 + 2;
191 }
192 assert(num_sgprs <= 104);
193
194 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
195 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
196 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
197 S_00B328_VGPRS((shader->num_vgprs - 1) / 4) |
198 S_00B328_SGPRS((num_sgprs - 1) / 8) |
199 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
200 S_00B328_DX10_CLAMP(shader->dx10_clamp_mode));
201 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
202 S_00B32C_USER_SGPR(num_user_sgprs) |
203 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
204
205 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
206 si_set_tesseval_regs(shader, pm4);
207 }
208
209 static unsigned si_gs_get_max_stream(struct si_shader *shader)
210 {
211 struct pipe_stream_output_info *so = &shader->selector->so;
212 unsigned max_stream = 0, i;
213
214 if (so->num_outputs == 0)
215 return 0;
216
217 for (i = 0; i < so->num_outputs; i++) {
218 if (so->output[i].stream > max_stream)
219 max_stream = so->output[i].stream;
220 }
221 return max_stream;
222 }
223
224 static void si_shader_gs(struct si_shader *shader)
225 {
226 unsigned gs_vert_itemsize = shader->selector->info.num_outputs * 16;
227 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
228 unsigned gsvs_itemsize = (gs_vert_itemsize * gs_max_vert_out) >> 2;
229 unsigned gs_num_invocations = shader->selector->gs_num_invocations;
230 unsigned cut_mode;
231 struct si_pm4_state *pm4;
232 unsigned num_sgprs, num_user_sgprs;
233 uint64_t va;
234 unsigned max_stream = si_gs_get_max_stream(shader);
235
236 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
237 assert(gsvs_itemsize < (1 << 15));
238
239 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
240
241 if (pm4 == NULL)
242 return;
243
244 if (gs_max_vert_out <= 128) {
245 cut_mode = V_028A40_GS_CUT_128;
246 } else if (gs_max_vert_out <= 256) {
247 cut_mode = V_028A40_GS_CUT_256;
248 } else if (gs_max_vert_out <= 512) {
249 cut_mode = V_028A40_GS_CUT_512;
250 } else {
251 assert(gs_max_vert_out <= 1024);
252 cut_mode = V_028A40_GS_CUT_1024;
253 }
254
255 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
256 S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
257 S_028A40_CUT_MODE(cut_mode)|
258 S_028A40_ES_WRITE_OPTIMIZE(1) |
259 S_028A40_GS_WRITE_OPTIMIZE(1));
260
261 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
262 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize * ((max_stream >= 2) ? 2 : 1));
263 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize * ((max_stream >= 3) ? 3 : 1));
264
265 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
266 util_bitcount64(shader->selector->inputs_read) * (16 >> 2));
267 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize * (max_stream + 1));
268
269 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, gs_max_vert_out);
270
271 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize >> 2);
272 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? gs_vert_itemsize >> 2 : 0);
273 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? gs_vert_itemsize >> 2 : 0);
274 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? gs_vert_itemsize >> 2 : 0);
275
276 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
277 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
278 S_028B90_ENABLE(gs_num_invocations > 0));
279
280 va = shader->bo->gpu_address;
281 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
282 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
283 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
284
285 num_user_sgprs = SI_GS_NUM_USER_SGPR;
286 num_sgprs = shader->num_sgprs;
287 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
288 if ((num_user_sgprs + 2) > num_sgprs) {
289 /* Last 2 reserved SGPRs are used for VCC */
290 num_sgprs = num_user_sgprs + 2 + 2;
291 }
292 assert(num_sgprs <= 104);
293
294 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
295 S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
296 S_00B228_SGPRS((num_sgprs - 1) / 8) |
297 S_00B228_DX10_CLAMP(shader->dx10_clamp_mode));
298 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
299 S_00B22C_USER_SGPR(num_user_sgprs) |
300 S_00B22C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
301 }
302
303 static void si_shader_vs(struct si_shader *shader)
304 {
305 struct si_pm4_state *pm4;
306 unsigned num_sgprs, num_user_sgprs;
307 unsigned nparams, vgpr_comp_cnt;
308 uint64_t va;
309 unsigned window_space =
310 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
311
312 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
313
314 if (pm4 == NULL)
315 return;
316
317 /* If this is the GS copy shader, the GS state writes this register.
318 * Otherwise, the VS state writes it.
319 */
320 if (!shader->is_gs_copy_shader)
321 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0);
322
323 va = shader->bo->gpu_address;
324 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
325
326 if (shader->is_gs_copy_shader) {
327 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
328 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
329 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
330 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
331 num_user_sgprs = SI_VS_NUM_USER_SGPR;
332 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
333 vgpr_comp_cnt = 3; /* all components are needed for TES */
334 num_user_sgprs = SI_TES_NUM_USER_SGPR;
335 } else
336 assert(0);
337
338 num_sgprs = shader->num_sgprs;
339 if (num_user_sgprs > num_sgprs) {
340 /* Last 2 reserved SGPRs are used for VCC */
341 num_sgprs = num_user_sgprs + 2;
342 }
343 assert(num_sgprs <= 104);
344
345 /* VS is required to export at least one param. */
346 nparams = MAX2(shader->nr_param_exports, 1);
347 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
348 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
349
350 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
351 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
352 S_02870C_POS1_EXPORT_FORMAT(shader->nr_pos_exports > 1 ?
353 V_02870C_SPI_SHADER_4COMP :
354 V_02870C_SPI_SHADER_NONE) |
355 S_02870C_POS2_EXPORT_FORMAT(shader->nr_pos_exports > 2 ?
356 V_02870C_SPI_SHADER_4COMP :
357 V_02870C_SPI_SHADER_NONE) |
358 S_02870C_POS3_EXPORT_FORMAT(shader->nr_pos_exports > 3 ?
359 V_02870C_SPI_SHADER_4COMP :
360 V_02870C_SPI_SHADER_NONE));
361
362 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
363 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
364 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
365 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
366 S_00B128_SGPRS((num_sgprs - 1) / 8) |
367 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
368 S_00B128_DX10_CLAMP(shader->dx10_clamp_mode));
369 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
370 S_00B12C_USER_SGPR(num_user_sgprs) |
371 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
372 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
373 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
374 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
375 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
376 S_00B12C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
377 if (window_space)
378 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
379 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
380 else
381 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
382 S_028818_VTX_W0_FMT(1) |
383 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
384 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
385 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
386
387 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
388 si_set_tesseval_regs(shader, pm4);
389 }
390
391 static void si_shader_ps(struct si_shader *shader)
392 {
393 struct tgsi_shader_info *info = &shader->selector->info;
394 struct si_pm4_state *pm4;
395 unsigned i, spi_ps_in_control;
396 unsigned num_sgprs, num_user_sgprs;
397 unsigned spi_baryc_cntl = 0, spi_ps_input_ena;
398 uint64_t va;
399
400 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
401
402 if (pm4 == NULL)
403 return;
404
405 for (i = 0; i < info->num_inputs; i++) {
406 switch (info->input_semantic_name[i]) {
407 case TGSI_SEMANTIC_POSITION:
408 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
409 * Possible vaules:
410 * 0 -> Position = pixel center (default)
411 * 1 -> Position = pixel centroid
412 * 2 -> Position = at sample position
413 */
414 switch (info->input_interpolate_loc[i]) {
415 case TGSI_INTERPOLATE_LOC_CENTROID:
416 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
417 break;
418 case TGSI_INTERPOLATE_LOC_SAMPLE:
419 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
420 break;
421 }
422
423 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
424 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
425 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
426 break;
427 }
428 }
429
430 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->nparam) |
431 S_0286D8_BC_OPTIMIZE_DISABLE(1);
432
433 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
434 spi_ps_input_ena = shader->spi_ps_input_ena;
435 /* we need to enable at least one of them, otherwise we hang the GPU */
436 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
437 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
438 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
439 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
440 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
441 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
442 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
443 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
444
445 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
446 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
447 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
448
449 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
450 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
451 shader->spi_shader_col_format);
452 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
453
454 va = shader->bo->gpu_address;
455 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
456 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
457 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
458
459 num_user_sgprs = SI_PS_NUM_USER_SGPR;
460 num_sgprs = shader->num_sgprs;
461 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
462 if ((num_user_sgprs + 1) > num_sgprs) {
463 /* Last 2 reserved SGPRs are used for VCC */
464 num_sgprs = num_user_sgprs + 1 + 2;
465 }
466 assert(num_sgprs <= 104);
467
468 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
469 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
470 S_00B028_SGPRS((num_sgprs - 1) / 8) |
471 S_00B028_DX10_CLAMP(shader->dx10_clamp_mode));
472 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
473 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
474 S_00B02C_USER_SGPR(num_user_sgprs) |
475 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
476 }
477
478 static void si_shader_init_pm4_state(struct si_shader *shader)
479 {
480
481 if (shader->pm4)
482 si_pm4_free_state_simple(shader->pm4);
483
484 switch (shader->selector->type) {
485 case PIPE_SHADER_VERTEX:
486 if (shader->key.vs.as_ls)
487 si_shader_ls(shader);
488 else if (shader->key.vs.as_es)
489 si_shader_es(shader);
490 else
491 si_shader_vs(shader);
492 break;
493 case PIPE_SHADER_TESS_CTRL:
494 si_shader_hs(shader);
495 break;
496 case PIPE_SHADER_TESS_EVAL:
497 if (shader->key.tes.as_es)
498 si_shader_es(shader);
499 else
500 si_shader_vs(shader);
501 break;
502 case PIPE_SHADER_GEOMETRY:
503 si_shader_gs(shader);
504 si_shader_vs(shader->gs_copy_shader);
505 break;
506 case PIPE_SHADER_FRAGMENT:
507 si_shader_ps(shader);
508 break;
509 default:
510 assert(0);
511 }
512 }
513
514 /* Compute the key for the hw shader variant */
515 static inline void si_shader_selector_key(struct pipe_context *ctx,
516 struct si_shader_selector *sel,
517 union si_shader_key *key)
518 {
519 struct si_context *sctx = (struct si_context *)ctx;
520 unsigned i;
521
522 memset(key, 0, sizeof(*key));
523
524 switch (sel->type) {
525 case PIPE_SHADER_VERTEX:
526 if (sctx->vertex_elements)
527 for (i = 0; i < sctx->vertex_elements->count; ++i)
528 key->vs.instance_divisors[i] =
529 sctx->vertex_elements->elements[i].instance_divisor;
530
531 if (sctx->tes_shader)
532 key->vs.as_ls = 1;
533 else if (sctx->gs_shader) {
534 key->vs.as_es = 1;
535 key->vs.es_enabled_outputs = sctx->gs_shader->inputs_read;
536 }
537 break;
538 case PIPE_SHADER_TESS_CTRL:
539 key->tcs.prim_mode =
540 sctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
541 break;
542 case PIPE_SHADER_TESS_EVAL:
543 if (sctx->gs_shader) {
544 key->tes.as_es = 1;
545 key->tes.es_enabled_outputs = sctx->gs_shader->inputs_read;
546 }
547 break;
548 case PIPE_SHADER_GEOMETRY:
549 break;
550 case PIPE_SHADER_FRAGMENT: {
551 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
552
553 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
554 key->ps.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
555 key->ps.export_16bpc = sctx->framebuffer.export_16bpc;
556
557 if (rs) {
558 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
559 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
560 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
561 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
562
563 key->ps.color_two_side = rs->two_side;
564
565 if (sctx->queued.named.blend) {
566 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
567 rs->multisample_enable &&
568 !sctx->framebuffer.cb0_is_integer;
569 }
570
571 key->ps.poly_stipple = rs->poly_stipple_enable && is_poly;
572 key->ps.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
573 (is_line && rs->line_smooth)) &&
574 sctx->framebuffer.nr_samples <= 1;
575 }
576
577 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
578 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
579 if (sctx->queued.named.dsa &&
580 !sctx->framebuffer.cb0_is_integer)
581 key->ps.alpha_func = sctx->queued.named.dsa->alpha_func;
582 break;
583 }
584 default:
585 assert(0);
586 }
587 }
588
589 /* Select the hw shader variant depending on the current state. */
590 static int si_shader_select(struct pipe_context *ctx,
591 struct si_shader_selector *sel)
592 {
593 struct si_context *sctx = (struct si_context *)ctx;
594 union si_shader_key key;
595 struct si_shader * shader = NULL;
596 int r;
597
598 si_shader_selector_key(ctx, sel, &key);
599
600 /* Check if we don't need to change anything.
601 * This path is also used for most shaders that don't need multiple
602 * variants, it will cost just a computation of the key and this
603 * test. */
604 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
605 return 0;
606 }
607
608 /* lookup if we have other variants in the list */
609 if (sel->num_shaders > 1) {
610 struct si_shader *p = sel->current, *c = p->next_variant;
611
612 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
613 p = c;
614 c = c->next_variant;
615 }
616
617 if (c) {
618 p->next_variant = c->next_variant;
619 shader = c;
620 }
621 }
622
623 if (shader) {
624 shader->next_variant = sel->current;
625 sel->current = shader;
626 } else {
627 shader = CALLOC(1, sizeof(struct si_shader));
628 shader->selector = sel;
629 shader->key = key;
630
631 shader->next_variant = sel->current;
632 sel->current = shader;
633 r = si_shader_create((struct si_screen*)ctx->screen, sctx->tm,
634 shader);
635 if (unlikely(r)) {
636 R600_ERR("Failed to build shader variant (type=%u) %d\n",
637 sel->type, r);
638 sel->current = NULL;
639 FREE(shader);
640 return r;
641 }
642 si_shader_init_pm4_state(shader);
643 sel->num_shaders++;
644 p_atomic_inc(&sctx->screen->b.num_compilations);
645 }
646
647 return 0;
648 }
649
650 static void *si_create_shader_state(struct pipe_context *ctx,
651 const struct pipe_shader_state *state,
652 unsigned pipe_shader_type)
653 {
654 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
655 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
656 int i;
657
658 sel->type = pipe_shader_type;
659 sel->tokens = tgsi_dup_tokens(state->tokens);
660 sel->so = state->stream_output;
661 tgsi_scan_shader(state->tokens, &sel->info);
662 p_atomic_inc(&sscreen->b.num_shaders_created);
663
664 switch (pipe_shader_type) {
665 case PIPE_SHADER_GEOMETRY:
666 sel->gs_output_prim =
667 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
668 sel->gs_max_out_vertices =
669 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
670 sel->gs_num_invocations =
671 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
672
673 for (i = 0; i < sel->info.num_inputs; i++) {
674 unsigned name = sel->info.input_semantic_name[i];
675 unsigned index = sel->info.input_semantic_index[i];
676
677 switch (name) {
678 case TGSI_SEMANTIC_PRIMID:
679 break;
680 default:
681 sel->inputs_read |=
682 1llu << si_shader_io_get_unique_index(name, index);
683 }
684 }
685 break;
686
687 case PIPE_SHADER_VERTEX:
688 case PIPE_SHADER_TESS_CTRL:
689 for (i = 0; i < sel->info.num_outputs; i++) {
690 unsigned name = sel->info.output_semantic_name[i];
691 unsigned index = sel->info.output_semantic_index[i];
692
693 switch (name) {
694 case TGSI_SEMANTIC_TESSINNER:
695 case TGSI_SEMANTIC_TESSOUTER:
696 case TGSI_SEMANTIC_PATCH:
697 sel->patch_outputs_written |=
698 1llu << si_shader_io_get_unique_index(name, index);
699 break;
700 default:
701 sel->outputs_written |=
702 1llu << si_shader_io_get_unique_index(name, index);
703 }
704 }
705 break;
706 }
707
708 if (sscreen->b.debug_flags & DBG_PRECOMPILE)
709 si_shader_select(ctx, sel);
710
711 return sel;
712 }
713
714 static void *si_create_fs_state(struct pipe_context *ctx,
715 const struct pipe_shader_state *state)
716 {
717 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
718 }
719
720 static void *si_create_gs_state(struct pipe_context *ctx,
721 const struct pipe_shader_state *state)
722 {
723 return si_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
724 }
725
726 static void *si_create_vs_state(struct pipe_context *ctx,
727 const struct pipe_shader_state *state)
728 {
729 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
730 }
731
732 static void *si_create_tcs_state(struct pipe_context *ctx,
733 const struct pipe_shader_state *state)
734 {
735 return si_create_shader_state(ctx, state, PIPE_SHADER_TESS_CTRL);
736 }
737
738 static void *si_create_tes_state(struct pipe_context *ctx,
739 const struct pipe_shader_state *state)
740 {
741 return si_create_shader_state(ctx, state, PIPE_SHADER_TESS_EVAL);
742 }
743
744 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
745 {
746 struct si_context *sctx = (struct si_context *)ctx;
747 struct si_shader_selector *sel = state;
748
749 if (sctx->vs_shader == sel || !sel)
750 return;
751
752 sctx->vs_shader = sel;
753 si_mark_atom_dirty(sctx, &sctx->clip_regs);
754 }
755
756 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
757 {
758 struct si_context *sctx = (struct si_context *)ctx;
759 struct si_shader_selector *sel = state;
760 bool enable_changed = !!sctx->gs_shader != !!sel;
761
762 if (sctx->gs_shader == sel)
763 return;
764
765 sctx->gs_shader = sel;
766 si_mark_atom_dirty(sctx, &sctx->clip_regs);
767 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
768
769 if (enable_changed)
770 si_shader_change_notify(sctx);
771 }
772
773 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
774 {
775 struct si_context *sctx = (struct si_context *)ctx;
776 struct si_shader_selector *sel = state;
777 bool enable_changed = !!sctx->tcs_shader != !!sel;
778
779 if (sctx->tcs_shader == sel)
780 return;
781
782 sctx->tcs_shader = sel;
783
784 if (enable_changed)
785 sctx->last_tcs = NULL; /* invalidate derived tess state */
786 }
787
788 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
789 {
790 struct si_context *sctx = (struct si_context *)ctx;
791 struct si_shader_selector *sel = state;
792 bool enable_changed = !!sctx->tes_shader != !!sel;
793
794 if (sctx->tes_shader == sel)
795 return;
796
797 sctx->tes_shader = sel;
798 si_mark_atom_dirty(sctx, &sctx->clip_regs);
799 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
800
801 if (enable_changed) {
802 si_shader_change_notify(sctx);
803 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
804 }
805 }
806
807 static void si_make_dummy_ps(struct si_context *sctx)
808 {
809 if (!sctx->dummy_pixel_shader) {
810 sctx->dummy_pixel_shader =
811 util_make_fragment_cloneinput_shader(&sctx->b.b, 0,
812 TGSI_SEMANTIC_GENERIC,
813 TGSI_INTERPOLATE_CONSTANT);
814 }
815 }
816
817 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
818 {
819 struct si_context *sctx = (struct si_context *)ctx;
820 struct si_shader_selector *sel = state;
821
822 /* skip if supplied shader is one already in use */
823 if (sctx->ps_shader == sel)
824 return;
825
826 /* use a dummy shader if binding a NULL shader */
827 if (!sel) {
828 si_make_dummy_ps(sctx);
829 sel = sctx->dummy_pixel_shader;
830 }
831
832 sctx->ps_shader = sel;
833 }
834
835 static void si_delete_shader_selector(struct pipe_context *ctx,
836 struct si_shader_selector *sel)
837 {
838 struct si_context *sctx = (struct si_context *)ctx;
839 struct si_shader *p = sel->current, *c;
840
841 while (p) {
842 c = p->next_variant;
843 switch (sel->type) {
844 case PIPE_SHADER_VERTEX:
845 if (p->key.vs.as_ls)
846 si_pm4_delete_state(sctx, ls, p->pm4);
847 else if (p->key.vs.as_es)
848 si_pm4_delete_state(sctx, es, p->pm4);
849 else
850 si_pm4_delete_state(sctx, vs, p->pm4);
851 break;
852 case PIPE_SHADER_TESS_CTRL:
853 si_pm4_delete_state(sctx, hs, p->pm4);
854 break;
855 case PIPE_SHADER_TESS_EVAL:
856 if (p->key.tes.as_es)
857 si_pm4_delete_state(sctx, es, p->pm4);
858 else
859 si_pm4_delete_state(sctx, vs, p->pm4);
860 break;
861 case PIPE_SHADER_GEOMETRY:
862 si_pm4_delete_state(sctx, gs, p->pm4);
863 si_pm4_delete_state(sctx, vs, p->gs_copy_shader->pm4);
864 break;
865 case PIPE_SHADER_FRAGMENT:
866 si_pm4_delete_state(sctx, ps, p->pm4);
867 break;
868 }
869
870 si_shader_destroy(ctx, p);
871 free(p);
872 p = c;
873 }
874
875 free(sel->tokens);
876 free(sel);
877 }
878
879 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
880 {
881 struct si_context *sctx = (struct si_context *)ctx;
882 struct si_shader_selector *sel = (struct si_shader_selector *)state;
883
884 if (sctx->vs_shader == sel) {
885 sctx->vs_shader = NULL;
886 }
887
888 si_delete_shader_selector(ctx, sel);
889 }
890
891 static void si_delete_gs_shader(struct pipe_context *ctx, void *state)
892 {
893 struct si_context *sctx = (struct si_context *)ctx;
894 struct si_shader_selector *sel = (struct si_shader_selector *)state;
895
896 if (sctx->gs_shader == sel) {
897 sctx->gs_shader = NULL;
898 }
899
900 si_delete_shader_selector(ctx, sel);
901 }
902
903 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
904 {
905 struct si_context *sctx = (struct si_context *)ctx;
906 struct si_shader_selector *sel = (struct si_shader_selector *)state;
907
908 if (sctx->ps_shader == sel) {
909 sctx->ps_shader = NULL;
910 }
911
912 si_delete_shader_selector(ctx, sel);
913 }
914
915 static void si_delete_tcs_shader(struct pipe_context *ctx, void *state)
916 {
917 struct si_context *sctx = (struct si_context *)ctx;
918 struct si_shader_selector *sel = (struct si_shader_selector *)state;
919
920 if (sctx->tcs_shader == sel) {
921 sctx->tcs_shader = NULL;
922 }
923
924 si_delete_shader_selector(ctx, sel);
925 }
926
927 static void si_delete_tes_shader(struct pipe_context *ctx, void *state)
928 {
929 struct si_context *sctx = (struct si_context *)ctx;
930 struct si_shader_selector *sel = (struct si_shader_selector *)state;
931
932 if (sctx->tes_shader == sel) {
933 sctx->tes_shader = NULL;
934 }
935
936 si_delete_shader_selector(ctx, sel);
937 }
938
939 static void si_update_spi_map(struct si_context *sctx)
940 {
941 struct si_shader *ps = sctx->ps_shader->current;
942 struct si_shader *vs = si_get_vs_state(sctx);
943 struct tgsi_shader_info *psinfo = &ps->selector->info;
944 struct tgsi_shader_info *vsinfo = &vs->selector->info;
945 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
946 unsigned i, j, tmp;
947
948 for (i = 0; i < psinfo->num_inputs; i++) {
949 unsigned name = psinfo->input_semantic_name[i];
950 unsigned index = psinfo->input_semantic_index[i];
951 unsigned interpolate = psinfo->input_interpolate[i];
952 unsigned param_offset = ps->ps_input_param_offset[i];
953
954 if (name == TGSI_SEMANTIC_POSITION ||
955 name == TGSI_SEMANTIC_FACE)
956 /* Read from preloaded VGPRs, not parameters */
957 continue;
958
959 bcolor:
960 tmp = 0;
961
962 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
963 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
964 tmp |= S_028644_FLAT_SHADE(1);
965
966 if (name == TGSI_SEMANTIC_PCOORD ||
967 (name == TGSI_SEMANTIC_TEXCOORD &&
968 sctx->sprite_coord_enable & (1 << index))) {
969 tmp |= S_028644_PT_SPRITE_TEX(1);
970 }
971
972 for (j = 0; j < vsinfo->num_outputs; j++) {
973 if (name == vsinfo->output_semantic_name[j] &&
974 index == vsinfo->output_semantic_index[j]) {
975 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[j]);
976 break;
977 }
978 }
979
980 if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(tmp)) {
981 /* No corresponding output found, load defaults into input.
982 * Don't set any other bits.
983 * (FLAT_SHADE=1 completely changes behavior) */
984 tmp = S_028644_OFFSET(0x20);
985 }
986
987 si_pm4_set_reg(pm4,
988 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
989 tmp);
990
991 if (name == TGSI_SEMANTIC_COLOR &&
992 ps->key.ps.color_two_side) {
993 name = TGSI_SEMANTIC_BCOLOR;
994 param_offset++;
995 goto bcolor;
996 }
997 }
998
999 si_pm4_set_state(sctx, spi, pm4);
1000 }
1001
1002 /* Initialize state related to ESGS / GSVS ring buffers */
1003 static void si_init_gs_rings(struct si_context *sctx)
1004 {
1005 unsigned esgs_ring_size = 128 * 1024;
1006 unsigned gsvs_ring_size = 64 * 1024 * 1024;
1007
1008 assert(!sctx->gs_rings);
1009 sctx->gs_rings = CALLOC_STRUCT(si_pm4_state);
1010
1011 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1012 PIPE_USAGE_DEFAULT, esgs_ring_size);
1013
1014 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1015 PIPE_USAGE_DEFAULT, gsvs_ring_size);
1016
1017 if (sctx->b.chip_class >= CIK) {
1018 si_pm4_set_reg(sctx->gs_rings, R_030900_VGT_ESGS_RING_SIZE,
1019 esgs_ring_size / 256);
1020 si_pm4_set_reg(sctx->gs_rings, R_030904_VGT_GSVS_RING_SIZE,
1021 gsvs_ring_size / 256);
1022 } else {
1023 si_pm4_set_reg(sctx->gs_rings, R_0088C8_VGT_ESGS_RING_SIZE,
1024 esgs_ring_size / 256);
1025 si_pm4_set_reg(sctx->gs_rings, R_0088CC_VGT_GSVS_RING_SIZE,
1026 gsvs_ring_size / 256);
1027 }
1028
1029 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
1030 sctx->esgs_ring, 0, esgs_ring_size,
1031 true, true, 4, 64, 0);
1032 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
1033 sctx->esgs_ring, 0, esgs_ring_size,
1034 false, false, 0, 0, 0);
1035 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
1036 sctx->gsvs_ring, 0, gsvs_ring_size,
1037 false, false, 0, 0, 0);
1038 }
1039
1040 static void si_update_gs_rings(struct si_context *sctx)
1041 {
1042 unsigned gs_vert_itemsize = sctx->gs_shader->info.num_outputs * 16;
1043 unsigned gs_max_vert_out = sctx->gs_shader->gs_max_out_vertices;
1044 unsigned gsvs_itemsize = gs_vert_itemsize * gs_max_vert_out;
1045 uint64_t offset;
1046
1047 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
1048 sctx->gsvs_ring, gsvs_itemsize,
1049 64, true, true, 4, 16, 0);
1050
1051 offset = gsvs_itemsize * 64;
1052 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_1,
1053 sctx->gsvs_ring, gsvs_itemsize,
1054 64, true, true, 4, 16, offset);
1055
1056 offset = (gsvs_itemsize * 2) * 64;
1057 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_2,
1058 sctx->gsvs_ring, gsvs_itemsize,
1059 64, true, true, 4, 16, offset);
1060
1061 offset = (gsvs_itemsize * 3) * 64;
1062 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_3,
1063 sctx->gsvs_ring, gsvs_itemsize,
1064 64, true, true, 4, 16, offset);
1065
1066 }
1067 /**
1068 * @returns 1 if \p sel has been updated to use a new scratch buffer and 0
1069 * otherwise.
1070 */
1071 static unsigned si_update_scratch_buffer(struct si_context *sctx,
1072 struct si_shader_selector *sel)
1073 {
1074 struct si_shader *shader;
1075 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
1076
1077 if (!sel)
1078 return 0;
1079
1080 shader = sel->current;
1081
1082 /* This shader doesn't need a scratch buffer */
1083 if (shader->scratch_bytes_per_wave == 0)
1084 return 0;
1085
1086 /* This shader is already configured to use the current
1087 * scratch buffer. */
1088 if (shader->scratch_bo == sctx->scratch_buffer)
1089 return 0;
1090
1091 assert(sctx->scratch_buffer);
1092
1093 si_shader_apply_scratch_relocs(sctx, shader, scratch_va);
1094
1095 /* Replace the shader bo with a new bo that has the relocs applied. */
1096 si_shader_binary_upload(sctx->screen, shader);
1097
1098 /* Update the shader state to use the new shader bo. */
1099 si_shader_init_pm4_state(shader);
1100
1101 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
1102
1103 return 1;
1104 }
1105
1106 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
1107 {
1108 if (!sctx->scratch_buffer)
1109 return 0;
1110
1111 return sctx->scratch_buffer->b.b.width0;
1112 }
1113
1114 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_context *sctx,
1115 struct si_shader_selector *sel)
1116 {
1117 if (!sel)
1118 return 0;
1119
1120 return sel->current->scratch_bytes_per_wave;
1121 }
1122
1123 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
1124 {
1125 unsigned bytes = 0;
1126
1127 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx, sctx->ps_shader));
1128 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx, sctx->gs_shader));
1129 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx, sctx->vs_shader));
1130 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx, sctx->tcs_shader));
1131 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx, sctx->tes_shader));
1132 return bytes;
1133 }
1134
1135 static void si_update_spi_tmpring_size(struct si_context *sctx)
1136 {
1137 unsigned current_scratch_buffer_size =
1138 si_get_current_scratch_buffer_size(sctx);
1139 unsigned scratch_bytes_per_wave =
1140 si_get_max_scratch_bytes_per_wave(sctx);
1141 unsigned scratch_needed_size = scratch_bytes_per_wave *
1142 sctx->scratch_waves;
1143
1144 if (scratch_needed_size > 0) {
1145
1146 if (scratch_needed_size > current_scratch_buffer_size) {
1147 /* Create a bigger scratch buffer */
1148 pipe_resource_reference(
1149 (struct pipe_resource**)&sctx->scratch_buffer,
1150 NULL);
1151
1152 sctx->scratch_buffer =
1153 si_resource_create_custom(&sctx->screen->b.b,
1154 PIPE_USAGE_DEFAULT, scratch_needed_size);
1155 }
1156
1157 /* Update the shaders, so they are using the latest scratch. The
1158 * scratch buffer may have been changed since these shaders were
1159 * last used, so we still need to try to update them, even if
1160 * they require scratch buffers smaller than the current size.
1161 */
1162 if (si_update_scratch_buffer(sctx, sctx->ps_shader))
1163 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
1164 if (si_update_scratch_buffer(sctx, sctx->gs_shader))
1165 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
1166 if (si_update_scratch_buffer(sctx, sctx->tcs_shader))
1167 si_pm4_bind_state(sctx, hs, sctx->tcs_shader->current->pm4);
1168
1169 /* VS can be bound as LS, ES, or VS. */
1170 if (sctx->tes_shader) {
1171 if (si_update_scratch_buffer(sctx, sctx->vs_shader))
1172 si_pm4_bind_state(sctx, ls, sctx->vs_shader->current->pm4);
1173 } else if (sctx->gs_shader) {
1174 if (si_update_scratch_buffer(sctx, sctx->vs_shader))
1175 si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
1176 } else {
1177 if (si_update_scratch_buffer(sctx, sctx->vs_shader))
1178 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
1179 }
1180
1181 /* TES can be bound as ES or VS. */
1182 if (sctx->gs_shader) {
1183 if (si_update_scratch_buffer(sctx, sctx->tes_shader))
1184 si_pm4_bind_state(sctx, es, sctx->tes_shader->current->pm4);
1185 } else {
1186 if (si_update_scratch_buffer(sctx, sctx->tes_shader))
1187 si_pm4_bind_state(sctx, vs, sctx->tes_shader->current->pm4);
1188 }
1189 }
1190
1191 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
1192 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
1193 "scratch size should already be aligned correctly.");
1194
1195 sctx->spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
1196 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
1197 }
1198
1199 static void si_init_tess_factor_ring(struct si_context *sctx)
1200 {
1201 assert(!sctx->tf_state);
1202 sctx->tf_state = CALLOC_STRUCT(si_pm4_state);
1203
1204 sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1205 PIPE_USAGE_DEFAULT,
1206 32768 * sctx->screen->b.info.max_se);
1207 sctx->b.clear_buffer(&sctx->b.b, sctx->tf_ring, 0,
1208 sctx->tf_ring->width0, fui(0), false);
1209 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
1210
1211 if (sctx->b.chip_class >= CIK) {
1212 si_pm4_set_reg(sctx->tf_state, R_030938_VGT_TF_RING_SIZE,
1213 S_030938_SIZE(sctx->tf_ring->width0 / 4));
1214 si_pm4_set_reg(sctx->tf_state, R_030940_VGT_TF_MEMORY_BASE,
1215 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1216 } else {
1217 si_pm4_set_reg(sctx->tf_state, R_008988_VGT_TF_RING_SIZE,
1218 S_008988_SIZE(sctx->tf_ring->width0 / 4));
1219 si_pm4_set_reg(sctx->tf_state, R_0089B8_VGT_TF_MEMORY_BASE,
1220 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1221 }
1222 si_pm4_add_bo(sctx->tf_state, r600_resource(sctx->tf_ring),
1223 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RESOURCE_RW);
1224 si_pm4_bind_state(sctx, tf_ring, sctx->tf_state);
1225
1226 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_TESS_CTRL,
1227 SI_RING_TESS_FACTOR, sctx->tf_ring, 0,
1228 sctx->tf_ring->width0, false, false, 0, 0, 0);
1229
1230 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
1231 }
1232
1233 /**
1234 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
1235 * VS passes its outputs to TES directly, so the fixed-function shader only
1236 * has to write TESSOUTER and TESSINNER.
1237 */
1238 static void si_generate_fixed_func_tcs(struct si_context *sctx)
1239 {
1240 struct ureg_src const0, const1;
1241 struct ureg_dst tessouter, tessinner;
1242 struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
1243
1244 if (!ureg)
1245 return; /* if we get here, we're screwed */
1246
1247 assert(!sctx->fixed_func_tcs_shader);
1248
1249 ureg_DECL_constant2D(ureg, 0, 1, SI_DRIVER_STATE_CONST_BUF);
1250 const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 0),
1251 SI_DRIVER_STATE_CONST_BUF);
1252 const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 1),
1253 SI_DRIVER_STATE_CONST_BUF);
1254
1255 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1256 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1257
1258 ureg_MOV(ureg, tessouter, const0);
1259 ureg_MOV(ureg, tessinner, const1);
1260 ureg_END(ureg);
1261
1262 sctx->fixed_func_tcs_shader =
1263 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
1264 assert(sctx->fixed_func_tcs_shader);
1265 }
1266
1267 static void si_update_vgt_shader_config(struct si_context *sctx)
1268 {
1269 /* Calculate the index of the config.
1270 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
1271 unsigned index = 2*!!sctx->tes_shader + !!sctx->gs_shader;
1272 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
1273
1274 if (!*pm4) {
1275 uint32_t stages = 0;
1276
1277 *pm4 = CALLOC_STRUCT(si_pm4_state);
1278
1279 if (sctx->tes_shader) {
1280 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
1281 S_028B54_HS_EN(1);
1282
1283 if (sctx->gs_shader)
1284 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
1285 S_028B54_GS_EN(1) |
1286 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1287 else
1288 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
1289 } else if (sctx->gs_shader) {
1290 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1291 S_028B54_GS_EN(1) |
1292 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1293 }
1294
1295 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
1296 }
1297 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
1298 }
1299
1300 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
1301 {
1302 struct pipe_stream_output_info *so = &shader->so;
1303 uint32_t enabled_stream_buffers_mask = 0;
1304 int i;
1305
1306 for (i = 0; i < so->num_outputs; i++)
1307 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
1308 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
1309 sctx->b.streamout.stride_in_dw = shader->so.stride;
1310 }
1311
1312 void si_update_shaders(struct si_context *sctx)
1313 {
1314 struct pipe_context *ctx = (struct pipe_context*)sctx;
1315 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1316
1317 /* Update stages before GS. */
1318 if (sctx->tes_shader) {
1319 if (!sctx->tf_state)
1320 si_init_tess_factor_ring(sctx);
1321
1322 /* VS as LS */
1323 si_shader_select(ctx, sctx->vs_shader);
1324 si_pm4_bind_state(sctx, ls, sctx->vs_shader->current->pm4);
1325
1326 if (sctx->tcs_shader) {
1327 si_shader_select(ctx, sctx->tcs_shader);
1328 si_pm4_bind_state(sctx, hs, sctx->tcs_shader->current->pm4);
1329 } else {
1330 if (!sctx->fixed_func_tcs_shader)
1331 si_generate_fixed_func_tcs(sctx);
1332 si_shader_select(ctx, sctx->fixed_func_tcs_shader);
1333 si_pm4_bind_state(sctx, hs,
1334 sctx->fixed_func_tcs_shader->current->pm4);
1335 }
1336
1337 si_shader_select(ctx, sctx->tes_shader);
1338 if (sctx->gs_shader) {
1339 /* TES as ES */
1340 si_pm4_bind_state(sctx, es, sctx->tes_shader->current->pm4);
1341 } else {
1342 /* TES as VS */
1343 si_pm4_bind_state(sctx, vs, sctx->tes_shader->current->pm4);
1344 si_update_so(sctx, sctx->tes_shader);
1345 }
1346 } else if (sctx->gs_shader) {
1347 /* VS as ES */
1348 si_shader_select(ctx, sctx->vs_shader);
1349 si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
1350 } else {
1351 /* VS as VS */
1352 si_shader_select(ctx, sctx->vs_shader);
1353 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
1354 si_update_so(sctx, sctx->vs_shader);
1355 }
1356
1357 /* Update GS. */
1358 if (sctx->gs_shader) {
1359 si_shader_select(ctx, sctx->gs_shader);
1360 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
1361 si_pm4_bind_state(sctx, vs, sctx->gs_shader->current->gs_copy_shader->pm4);
1362 si_update_so(sctx, sctx->gs_shader);
1363
1364 if (!sctx->gs_rings)
1365 si_init_gs_rings(sctx);
1366
1367 if (sctx->emitted.named.gs_rings != sctx->gs_rings)
1368 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
1369 si_pm4_bind_state(sctx, gs_rings, sctx->gs_rings);
1370
1371 si_update_gs_rings(sctx);
1372 } else {
1373 si_pm4_bind_state(sctx, gs_rings, NULL);
1374 si_pm4_bind_state(sctx, gs, NULL);
1375 si_pm4_bind_state(sctx, es, NULL);
1376 }
1377
1378 si_update_vgt_shader_config(sctx);
1379
1380 si_shader_select(ctx, sctx->ps_shader);
1381
1382 if (!sctx->ps_shader->current) {
1383 struct si_shader_selector *sel;
1384
1385 /* use a dummy shader if compiling the shader (variant) failed */
1386 si_make_dummy_ps(sctx);
1387 sel = sctx->dummy_pixel_shader;
1388 si_shader_select(ctx, sel);
1389 sctx->ps_shader->current = sel->current;
1390 }
1391
1392 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
1393
1394 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
1395 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
1396 sctx->flatshade != rs->flatshade) {
1397 sctx->sprite_coord_enable = rs->sprite_coord_enable;
1398 sctx->flatshade = rs->flatshade;
1399 si_update_spi_map(sctx);
1400 }
1401
1402 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
1403 si_pm4_state_changed(sctx, gs)) {
1404 si_update_spi_tmpring_size(sctx);
1405 }
1406
1407 if (sctx->ps_db_shader_control != sctx->ps_shader->current->db_shader_control) {
1408 sctx->ps_db_shader_control = sctx->ps_shader->current->db_shader_control;
1409 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1410 }
1411
1412 if (sctx->smoothing_enabled != sctx->ps_shader->current->key.ps.poly_line_smoothing) {
1413 sctx->smoothing_enabled = sctx->ps_shader->current->key.ps.poly_line_smoothing;
1414 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1415
1416 if (sctx->b.chip_class == SI)
1417 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1418 }
1419 }
1420
1421 void si_init_shader_functions(struct si_context *sctx)
1422 {
1423 sctx->b.b.create_vs_state = si_create_vs_state;
1424 sctx->b.b.create_tcs_state = si_create_tcs_state;
1425 sctx->b.b.create_tes_state = si_create_tes_state;
1426 sctx->b.b.create_gs_state = si_create_gs_state;
1427 sctx->b.b.create_fs_state = si_create_fs_state;
1428
1429 sctx->b.b.bind_vs_state = si_bind_vs_shader;
1430 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
1431 sctx->b.b.bind_tes_state = si_bind_tes_shader;
1432 sctx->b.b.bind_gs_state = si_bind_gs_shader;
1433 sctx->b.b.bind_fs_state = si_bind_ps_shader;
1434
1435 sctx->b.b.delete_vs_state = si_delete_vs_shader;
1436 sctx->b.b.delete_tcs_state = si_delete_tcs_shader;
1437 sctx->b.b.delete_tes_state = si_delete_tes_shader;
1438 sctx->b.b.delete_gs_state = si_delete_gs_shader;
1439 sctx->b.b.delete_fs_state = si_delete_ps_shader;
1440 }