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[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "si_shader.h"
30 #include "sid.h"
31 #include "radeon/r600_cs.h"
32
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/hash_table.h"
36 #include "util/u_hash.h"
37 #include "util/u_memory.h"
38 #include "util/u_prim.h"
39 #include "util/u_simple_shaders.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
45 * integer.
46 */
47 static void *si_get_tgsi_binary(struct si_shader_selector *sel)
48 {
49 unsigned tgsi_size = tgsi_num_tokens(sel->tokens) *
50 sizeof(struct tgsi_token);
51 unsigned size = 4 + tgsi_size + sizeof(sel->so);
52 char *result = (char*)MALLOC(size);
53
54 if (!result)
55 return NULL;
56
57 *((uint32_t*)result) = size;
58 memcpy(result + 4, sel->tokens, tgsi_size);
59 memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so));
60 return result;
61 }
62
63 /** Copy "data" to "ptr" and return the next dword following copied data. */
64 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
65 {
66 memcpy(ptr, data, size);
67 ptr += DIV_ROUND_UP(size, 4);
68 return ptr;
69 }
70
71 /** Read data from "ptr". Return the next dword following the data. */
72 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
73 {
74 memcpy(data, ptr, size);
75 ptr += DIV_ROUND_UP(size, 4);
76 return ptr;
77 }
78
79 /**
80 * Write the size as uint followed by the data. Return the next dword
81 * following the copied data.
82 */
83 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
84 {
85 *ptr++ = size;
86 return write_data(ptr, data, size);
87 }
88
89 /**
90 * Read the size as uint followed by the data. Return both via parameters.
91 * Return the next dword following the data.
92 */
93 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
94 {
95 *size = *ptr++;
96 assert(*data == NULL);
97 *data = malloc(*size);
98 return read_data(ptr, *data, *size);
99 }
100
101 /**
102 * Return the shader binary in a buffer. The first 4 bytes contain its size
103 * as integer.
104 */
105 static void *si_get_shader_binary(struct si_shader *shader)
106 {
107 /* There is always a size of data followed by the data itself. */
108 unsigned relocs_size = shader->binary.reloc_count *
109 sizeof(shader->binary.relocs[0]);
110 unsigned disasm_size = strlen(shader->binary.disasm_string) + 1;
111 unsigned size =
112 4 + /* total size */
113 4 + /* CRC32 of the data below */
114 align(sizeof(shader->config), 4) +
115 align(sizeof(shader->info), 4) +
116 4 + align(shader->binary.code_size, 4) +
117 4 + align(shader->binary.rodata_size, 4) +
118 4 + align(relocs_size, 4) +
119 4 + align(disasm_size, 4);
120 void *buffer = CALLOC(1, size);
121 uint32_t *ptr = (uint32_t*)buffer;
122
123 if (!buffer)
124 return NULL;
125
126 *ptr++ = size;
127 ptr++; /* CRC32 is calculated at the end. */
128
129 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
130 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
131 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
132 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
133 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
134 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
135 assert((char *)ptr - (char *)buffer == size);
136
137 /* Compute CRC32. */
138 ptr = (uint32_t*)buffer;
139 ptr++;
140 *ptr = util_hash_crc32(ptr + 1, size - 8);
141
142 return buffer;
143 }
144
145 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
146 {
147 uint32_t *ptr = (uint32_t*)binary;
148 uint32_t size = *ptr++;
149 uint32_t crc32 = *ptr++;
150 unsigned chunk_size;
151
152 if (util_hash_crc32(ptr, size - 8) != crc32) {
153 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
154 return false;
155 }
156
157 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
158 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
159 ptr = read_chunk(ptr, (void**)&shader->binary.code,
160 &shader->binary.code_size);
161 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
162 &shader->binary.rodata_size);
163 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
164 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
165 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
166
167 return true;
168 }
169
170 /**
171 * Insert a shader into the cache. It's assumed the shader is not in the cache.
172 * Use si_shader_cache_load_shader before calling this.
173 *
174 * Returns false on failure, in which case the tgsi_binary should be freed.
175 */
176 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
177 void *tgsi_binary,
178 struct si_shader *shader)
179 {
180 void *hw_binary = si_get_shader_binary(shader);
181
182 if (!hw_binary)
183 return false;
184
185 if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
186 hw_binary) == NULL) {
187 FREE(hw_binary);
188 return false;
189 }
190
191 return true;
192 }
193
194 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
195 void *tgsi_binary,
196 struct si_shader *shader)
197 {
198 struct hash_entry *entry =
199 _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
200 if (!entry)
201 return false;
202
203 return si_load_shader_binary(shader, entry->data);
204 }
205
206 static uint32_t si_shader_cache_key_hash(const void *key)
207 {
208 /* The first dword is the key size. */
209 return util_hash_crc32(key, *(uint32_t*)key);
210 }
211
212 static bool si_shader_cache_key_equals(const void *a, const void *b)
213 {
214 uint32_t *keya = (uint32_t*)a;
215 uint32_t *keyb = (uint32_t*)b;
216
217 /* The first dword is the key size. */
218 if (*keya != *keyb)
219 return false;
220
221 return memcmp(keya, keyb, *keya) == 0;
222 }
223
224 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
225 {
226 FREE((void*)entry->key);
227 FREE(entry->data);
228 }
229
230 bool si_init_shader_cache(struct si_screen *sscreen)
231 {
232 pipe_mutex_init(sscreen->shader_cache_mutex);
233 sscreen->shader_cache =
234 _mesa_hash_table_create(NULL,
235 si_shader_cache_key_hash,
236 si_shader_cache_key_equals);
237 return sscreen->shader_cache != NULL;
238 }
239
240 void si_destroy_shader_cache(struct si_screen *sscreen)
241 {
242 if (sscreen->shader_cache)
243 _mesa_hash_table_destroy(sscreen->shader_cache,
244 si_destroy_shader_cache_entry);
245 pipe_mutex_destroy(sscreen->shader_cache_mutex);
246 }
247
248 /* SHADER STATES */
249
250 static void si_set_tesseval_regs(struct si_shader *shader,
251 struct si_pm4_state *pm4)
252 {
253 struct tgsi_shader_info *info = &shader->selector->info;
254 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
255 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
256 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
257 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
258 unsigned type, partitioning, topology;
259
260 switch (tes_prim_mode) {
261 case PIPE_PRIM_LINES:
262 type = V_028B6C_TESS_ISOLINE;
263 break;
264 case PIPE_PRIM_TRIANGLES:
265 type = V_028B6C_TESS_TRIANGLE;
266 break;
267 case PIPE_PRIM_QUADS:
268 type = V_028B6C_TESS_QUAD;
269 break;
270 default:
271 assert(0);
272 return;
273 }
274
275 switch (tes_spacing) {
276 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
277 partitioning = V_028B6C_PART_FRAC_ODD;
278 break;
279 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
280 partitioning = V_028B6C_PART_FRAC_EVEN;
281 break;
282 case PIPE_TESS_SPACING_EQUAL:
283 partitioning = V_028B6C_PART_INTEGER;
284 break;
285 default:
286 assert(0);
287 return;
288 }
289
290 if (tes_point_mode)
291 topology = V_028B6C_OUTPUT_POINT;
292 else if (tes_prim_mode == PIPE_PRIM_LINES)
293 topology = V_028B6C_OUTPUT_LINE;
294 else if (tes_vertex_order_cw)
295 /* for some reason, this must be the other way around */
296 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
297 else
298 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
299
300 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
301 S_028B6C_TYPE(type) |
302 S_028B6C_PARTITIONING(partitioning) |
303 S_028B6C_TOPOLOGY(topology));
304 }
305
306 static void si_shader_ls(struct si_shader *shader)
307 {
308 struct si_pm4_state *pm4;
309 unsigned num_sgprs, num_user_sgprs;
310 unsigned vgpr_comp_cnt;
311 uint64_t va;
312
313 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
314 if (!pm4)
315 return;
316
317 va = shader->bo->gpu_address;
318 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
319
320 /* We need at least 2 components for LS.
321 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
322 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 1;
323
324 num_user_sgprs = SI_LS_NUM_USER_SGPR;
325 num_sgprs = shader->config.num_sgprs;
326 if (num_user_sgprs > num_sgprs) {
327 /* Last 2 reserved SGPRs are used for VCC */
328 num_sgprs = num_user_sgprs + 2;
329 }
330 assert(num_sgprs <= 104);
331
332 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
333 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
334
335 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
336 S_00B528_SGPRS((num_sgprs - 1) / 8) |
337 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
338 S_00B528_DX10_CLAMP(1) |
339 S_00B528_FLOAT_MODE(shader->config.float_mode);
340 shader->config.rsrc2 = S_00B52C_USER_SGPR(num_user_sgprs) |
341 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
342 }
343
344 static void si_shader_hs(struct si_shader *shader)
345 {
346 struct si_pm4_state *pm4;
347 unsigned num_sgprs, num_user_sgprs;
348 uint64_t va;
349
350 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
351 if (!pm4)
352 return;
353
354 va = shader->bo->gpu_address;
355 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
356
357 num_user_sgprs = SI_TCS_NUM_USER_SGPR;
358 num_sgprs = shader->config.num_sgprs;
359 /* One SGPR after user SGPRs is pre-loaded with tessellation factor
360 * buffer offset. */
361 if ((num_user_sgprs + 1) > num_sgprs) {
362 /* Last 2 reserved SGPRs are used for VCC */
363 num_sgprs = num_user_sgprs + 1 + 2;
364 }
365 assert(num_sgprs <= 104);
366
367 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
368 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
369 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
370 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
371 S_00B428_SGPRS((num_sgprs - 1) / 8) |
372 S_00B428_DX10_CLAMP(1) |
373 S_00B428_FLOAT_MODE(shader->config.float_mode));
374 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
375 S_00B42C_USER_SGPR(num_user_sgprs) |
376 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
377 }
378
379 static void si_shader_es(struct si_shader *shader)
380 {
381 struct si_pm4_state *pm4;
382 unsigned num_sgprs, num_user_sgprs;
383 unsigned vgpr_comp_cnt;
384 uint64_t va;
385
386 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
387
388 if (!pm4)
389 return;
390
391 va = shader->bo->gpu_address;
392 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
393
394 if (shader->selector->type == PIPE_SHADER_VERTEX) {
395 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
396 num_user_sgprs = SI_ES_NUM_USER_SGPR;
397 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
398 vgpr_comp_cnt = 3; /* all components are needed for TES */
399 num_user_sgprs = SI_TES_NUM_USER_SGPR;
400 } else
401 unreachable("invalid shader selector type");
402
403 num_sgprs = shader->config.num_sgprs;
404 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
405 if ((num_user_sgprs + 1) > num_sgprs) {
406 /* Last 2 reserved SGPRs are used for VCC */
407 num_sgprs = num_user_sgprs + 1 + 2;
408 }
409 assert(num_sgprs <= 104);
410
411 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
412 shader->selector->esgs_itemsize / 4);
413 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
414 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
415 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
416 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
417 S_00B328_SGPRS((num_sgprs - 1) / 8) |
418 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
419 S_00B328_DX10_CLAMP(1) |
420 S_00B328_FLOAT_MODE(shader->config.float_mode));
421 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
422 S_00B32C_USER_SGPR(num_user_sgprs) |
423 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
424
425 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
426 si_set_tesseval_regs(shader, pm4);
427 }
428
429 /**
430 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
431 * geometry shader.
432 */
433 static uint32_t si_vgt_gs_mode(struct si_shader *shader)
434 {
435 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
436 unsigned cut_mode;
437
438 if (gs_max_vert_out <= 128) {
439 cut_mode = V_028A40_GS_CUT_128;
440 } else if (gs_max_vert_out <= 256) {
441 cut_mode = V_028A40_GS_CUT_256;
442 } else if (gs_max_vert_out <= 512) {
443 cut_mode = V_028A40_GS_CUT_512;
444 } else {
445 assert(gs_max_vert_out <= 1024);
446 cut_mode = V_028A40_GS_CUT_1024;
447 }
448
449 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
450 S_028A40_CUT_MODE(cut_mode)|
451 S_028A40_ES_WRITE_OPTIMIZE(1) |
452 S_028A40_GS_WRITE_OPTIMIZE(1);
453 }
454
455 static void si_shader_gs(struct si_shader *shader)
456 {
457 unsigned gs_vert_itemsize = shader->selector->gsvs_vertex_size;
458 unsigned gsvs_itemsize = shader->selector->max_gsvs_emit_size >> 2;
459 unsigned gs_num_invocations = shader->selector->gs_num_invocations;
460 struct si_pm4_state *pm4;
461 unsigned num_sgprs, num_user_sgprs;
462 uint64_t va;
463 unsigned max_stream = shader->selector->max_gs_stream;
464
465 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
466 assert(gsvs_itemsize < (1 << 15));
467
468 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
469
470 if (!pm4)
471 return;
472
473 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(shader));
474
475 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
476 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize * ((max_stream >= 2) ? 2 : 1));
477 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize * ((max_stream >= 3) ? 3 : 1));
478
479 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize * (max_stream + 1));
480
481 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, shader->selector->gs_max_out_vertices);
482
483 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize >> 2);
484 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? gs_vert_itemsize >> 2 : 0);
485 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? gs_vert_itemsize >> 2 : 0);
486 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? gs_vert_itemsize >> 2 : 0);
487
488 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
489 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
490 S_028B90_ENABLE(gs_num_invocations > 0));
491
492 va = shader->bo->gpu_address;
493 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
494 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
495 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
496
497 num_user_sgprs = SI_GS_NUM_USER_SGPR;
498 num_sgprs = shader->config.num_sgprs;
499 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
500 if ((num_user_sgprs + 2) > num_sgprs) {
501 /* Last 2 reserved SGPRs are used for VCC */
502 num_sgprs = num_user_sgprs + 2 + 2;
503 }
504 assert(num_sgprs <= 104);
505
506 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
507 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
508 S_00B228_SGPRS((num_sgprs - 1) / 8) |
509 S_00B228_DX10_CLAMP(1) |
510 S_00B228_FLOAT_MODE(shader->config.float_mode));
511 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
512 S_00B22C_USER_SGPR(num_user_sgprs) |
513 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
514 }
515
516 /**
517 * Compute the state for \p shader, which will run as a vertex shader on the
518 * hardware.
519 *
520 * If \p gs is non-NULL, it points to the geometry shader for which this shader
521 * is the copy shader.
522 */
523 static void si_shader_vs(struct si_shader *shader, struct si_shader *gs)
524 {
525 struct si_pm4_state *pm4;
526 unsigned num_sgprs, num_user_sgprs;
527 unsigned nparams, vgpr_comp_cnt;
528 uint64_t va;
529 unsigned window_space =
530 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
531 bool enable_prim_id = si_vs_exports_prim_id(shader);
532
533 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
534
535 if (!pm4)
536 return;
537
538 /* We always write VGT_GS_MODE in the VS state, because every switch
539 * between different shader pipelines involving a different GS or no
540 * GS at all involves a switch of the VS (different GS use different
541 * copy shaders). On the other hand, when the API switches from a GS to
542 * no GS and then back to the same GS used originally, the GS state is
543 * not sent again.
544 */
545 if (!gs) {
546 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
547 S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
548 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
549 } else {
550 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
551 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
552 }
553
554 va = shader->bo->gpu_address;
555 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
556
557 if (gs) {
558 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
559 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
560 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
561 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
562 num_user_sgprs = SI_VS_NUM_USER_SGPR;
563 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
564 vgpr_comp_cnt = 3; /* all components are needed for TES */
565 num_user_sgprs = SI_TES_NUM_USER_SGPR;
566 } else
567 unreachable("invalid shader selector type");
568
569 num_sgprs = shader->config.num_sgprs;
570 if (num_user_sgprs > num_sgprs) {
571 /* Last 2 reserved SGPRs are used for VCC */
572 num_sgprs = num_user_sgprs + 2;
573 }
574 assert(num_sgprs <= 104);
575
576 /* VS is required to export at least one param. */
577 nparams = MAX2(shader->info.nr_param_exports, 1);
578 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
579 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
580
581 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
582 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
583 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
584 V_02870C_SPI_SHADER_4COMP :
585 V_02870C_SPI_SHADER_NONE) |
586 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
587 V_02870C_SPI_SHADER_4COMP :
588 V_02870C_SPI_SHADER_NONE) |
589 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
590 V_02870C_SPI_SHADER_4COMP :
591 V_02870C_SPI_SHADER_NONE));
592
593 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
594 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
595 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
596 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
597 S_00B128_SGPRS((num_sgprs - 1) / 8) |
598 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
599 S_00B128_DX10_CLAMP(1) |
600 S_00B128_FLOAT_MODE(shader->config.float_mode));
601 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
602 S_00B12C_USER_SGPR(num_user_sgprs) |
603 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
604 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
605 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
606 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
607 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
608 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
609 if (window_space)
610 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
611 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
612 else
613 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
614 S_028818_VTX_W0_FMT(1) |
615 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
616 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
617 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
618
619 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
620 si_set_tesseval_regs(shader, pm4);
621 }
622
623 static unsigned si_get_ps_num_interp(struct si_shader *ps)
624 {
625 struct tgsi_shader_info *info = &ps->selector->info;
626 unsigned num_colors = !!(info->colors_read & 0x0f) +
627 !!(info->colors_read & 0xf0);
628 unsigned num_interp = ps->selector->info.num_inputs +
629 (ps->key.ps.prolog.color_two_side ? num_colors : 0);
630
631 assert(num_interp <= 32);
632 return MIN2(num_interp, 32);
633 }
634
635 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
636 {
637 unsigned value = shader->key.ps.epilog.spi_shader_col_format;
638 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
639
640 /* If the i-th target format is set, all previous target formats must
641 * be non-zero to avoid hangs.
642 */
643 for (i = 0; i < num_targets; i++)
644 if (!(value & (0xf << (i * 4))))
645 value |= V_028714_SPI_SHADER_32_R << (i * 4);
646
647 return value;
648 }
649
650 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
651 {
652 unsigned i, cb_shader_mask = 0;
653
654 for (i = 0; i < 8; i++) {
655 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
656 case V_028714_SPI_SHADER_ZERO:
657 break;
658 case V_028714_SPI_SHADER_32_R:
659 cb_shader_mask |= 0x1 << (i * 4);
660 break;
661 case V_028714_SPI_SHADER_32_GR:
662 cb_shader_mask |= 0x3 << (i * 4);
663 break;
664 case V_028714_SPI_SHADER_32_AR:
665 cb_shader_mask |= 0x9 << (i * 4);
666 break;
667 case V_028714_SPI_SHADER_FP16_ABGR:
668 case V_028714_SPI_SHADER_UNORM16_ABGR:
669 case V_028714_SPI_SHADER_SNORM16_ABGR:
670 case V_028714_SPI_SHADER_UINT16_ABGR:
671 case V_028714_SPI_SHADER_SINT16_ABGR:
672 case V_028714_SPI_SHADER_32_ABGR:
673 cb_shader_mask |= 0xf << (i * 4);
674 break;
675 default:
676 assert(0);
677 }
678 }
679 return cb_shader_mask;
680 }
681
682 static void si_shader_ps(struct si_shader *shader)
683 {
684 struct tgsi_shader_info *info = &shader->selector->info;
685 struct si_pm4_state *pm4;
686 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
687 unsigned num_sgprs, num_user_sgprs;
688 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
689 uint64_t va;
690 bool has_centroid;
691 unsigned input_ena = shader->config.spi_ps_input_ena;
692
693 /* we need to enable at least one of them, otherwise we hang the GPU */
694 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
695 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
696 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
697 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
698 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
699 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
700 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
701 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
702
703 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
704
705 if (!pm4)
706 return;
707
708 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
709 * Possible vaules:
710 * 0 -> Position = pixel center
711 * 1 -> Position = pixel centroid
712 * 2 -> Position = at sample position
713 *
714 * From GLSL 4.5 specification, section 7.1:
715 * "The variable gl_FragCoord is available as an input variable from
716 * within fragment shaders and it holds the window relative coordinates
717 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
718 * value can be for any location within the pixel, or one of the
719 * fragment samples. The use of centroid does not further restrict
720 * this value to be inside the current primitive."
721 *
722 * Meaning that centroid has no effect and we can return anything within
723 * the pixel. Thus, return the value at sample position, because that's
724 * the most accurate one shaders can get.
725 */
726 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
727
728 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
729 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
730 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
731
732 spi_shader_col_format = si_get_spi_shader_col_format(shader);
733 cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
734
735 /* This must be non-zero for alpha-test/kill to work.
736 * The hardware ignores the EXEC mask if no export memory is allocated.
737 * Don't add this to CB_SHADER_MASK.
738 */
739 if (!spi_shader_col_format &&
740 !info->writes_z && !info->writes_stencil && !info->writes_samplemask &&
741 (shader->selector->info.uses_kill ||
742 shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS))
743 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
744
745 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
746 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
747 shader->config.spi_ps_input_addr);
748
749 /* Set interpolation controls. */
750 has_centroid = G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena) ||
751 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena);
752
753 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
754 S_0286D8_BC_OPTIMIZE_DISABLE(has_centroid);
755
756 /* Set registers. */
757 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
758 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
759
760 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
761 info->writes_samplemask ? V_028710_SPI_SHADER_32_ABGR :
762 info->writes_stencil ? V_028710_SPI_SHADER_32_GR :
763 info->writes_z ? V_028710_SPI_SHADER_32_R :
764 V_028710_SPI_SHADER_ZERO);
765
766 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
767 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
768
769 va = shader->bo->gpu_address;
770 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
771 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
772 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
773
774 num_user_sgprs = SI_PS_NUM_USER_SGPR;
775 num_sgprs = shader->config.num_sgprs;
776 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
777 if ((num_user_sgprs + 1) > num_sgprs) {
778 /* Last 2 reserved SGPRs are used for VCC */
779 num_sgprs = num_user_sgprs + 1 + 2;
780 }
781 assert(num_sgprs <= 104);
782
783 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
784 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
785 S_00B028_SGPRS((num_sgprs - 1) / 8) |
786 S_00B028_DX10_CLAMP(1) |
787 S_00B028_FLOAT_MODE(shader->config.float_mode));
788 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
789 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
790 S_00B02C_USER_SGPR(num_user_sgprs) |
791 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
792 }
793
794 static void si_shader_init_pm4_state(struct si_shader *shader)
795 {
796
797 if (shader->pm4)
798 si_pm4_free_state_simple(shader->pm4);
799
800 switch (shader->selector->type) {
801 case PIPE_SHADER_VERTEX:
802 if (shader->key.vs.as_ls)
803 si_shader_ls(shader);
804 else if (shader->key.vs.as_es)
805 si_shader_es(shader);
806 else
807 si_shader_vs(shader, NULL);
808 break;
809 case PIPE_SHADER_TESS_CTRL:
810 si_shader_hs(shader);
811 break;
812 case PIPE_SHADER_TESS_EVAL:
813 if (shader->key.tes.as_es)
814 si_shader_es(shader);
815 else
816 si_shader_vs(shader, NULL);
817 break;
818 case PIPE_SHADER_GEOMETRY:
819 si_shader_gs(shader);
820 si_shader_vs(shader->gs_copy_shader, shader);
821 break;
822 case PIPE_SHADER_FRAGMENT:
823 si_shader_ps(shader);
824 break;
825 default:
826 assert(0);
827 }
828 }
829
830 static unsigned si_get_alpha_test_func(struct si_context *sctx)
831 {
832 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
833 if (sctx->queued.named.dsa &&
834 !sctx->framebuffer.cb0_is_integer)
835 return sctx->queued.named.dsa->alpha_func;
836
837 return PIPE_FUNC_ALWAYS;
838 }
839
840 /* Compute the key for the hw shader variant */
841 static inline void si_shader_selector_key(struct pipe_context *ctx,
842 struct si_shader_selector *sel,
843 union si_shader_key *key)
844 {
845 struct si_context *sctx = (struct si_context *)ctx;
846 unsigned i;
847
848 memset(key, 0, sizeof(*key));
849
850 switch (sel->type) {
851 case PIPE_SHADER_VERTEX:
852 if (sctx->vertex_elements) {
853 unsigned count = MIN2(sel->info.num_inputs,
854 sctx->vertex_elements->count);
855 for (i = 0; i < count; ++i)
856 key->vs.prolog.instance_divisors[i] =
857 sctx->vertex_elements->elements[i].instance_divisor;
858 }
859 if (sctx->tes_shader.cso)
860 key->vs.as_ls = 1;
861 else if (sctx->gs_shader.cso)
862 key->vs.as_es = 1;
863
864 if (!sctx->gs_shader.cso && sctx->ps_shader.cso &&
865 sctx->ps_shader.cso->info.uses_primid)
866 key->vs.epilog.export_prim_id = 1;
867 break;
868 case PIPE_SHADER_TESS_CTRL:
869 key->tcs.epilog.prim_mode =
870 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
871 break;
872 case PIPE_SHADER_TESS_EVAL:
873 if (sctx->gs_shader.cso)
874 key->tes.as_es = 1;
875 else if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
876 key->tes.epilog.export_prim_id = 1;
877 break;
878 case PIPE_SHADER_GEOMETRY:
879 break;
880 case PIPE_SHADER_FRAGMENT: {
881 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
882 struct si_state_blend *blend = sctx->queued.named.blend;
883
884 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
885 sel->info.colors_written == 0x1)
886 key->ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
887
888 if (blend) {
889 /* Select the shader color format based on whether
890 * blending or alpha are needed.
891 */
892 key->ps.epilog.spi_shader_col_format =
893 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
894 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
895 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
896 sctx->framebuffer.spi_shader_col_format_blend) |
897 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
898 sctx->framebuffer.spi_shader_col_format_alpha) |
899 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
900 sctx->framebuffer.spi_shader_col_format);
901 } else
902 key->ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
903
904 /* If alpha-to-coverage is enabled, we have to export alpha
905 * even if there is no color buffer.
906 */
907 if (!(key->ps.epilog.spi_shader_col_format & 0xf) &&
908 blend && blend->alpha_to_coverage)
909 key->ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
910
911 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
912 * to the range supported by the type if a channel has less
913 * than 16 bits and the export format is 16_ABGR.
914 */
915 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII)
916 key->ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
917
918 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
919 if (!key->ps.epilog.last_cbuf) {
920 key->ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
921 key->ps.epilog.color_is_int8 &= sel->info.colors_written;
922 }
923
924 if (rs) {
925 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
926 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
927 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
928 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
929
930 key->ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
931
932 if (sctx->queued.named.blend) {
933 key->ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
934 rs->multisample_enable &&
935 !sctx->framebuffer.cb0_is_integer;
936 }
937
938 key->ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
939 key->ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
940 (is_line && rs->line_smooth)) &&
941 sctx->framebuffer.nr_samples <= 1;
942 key->ps.epilog.clamp_color = rs->clamp_fragment_color;
943
944 key->ps.prolog.force_persample_interp =
945 rs->force_persample_interp &&
946 rs->multisample_enable &&
947 sctx->framebuffer.nr_samples > 1 &&
948 sctx->ps_iter_samples > 1 &&
949 (sel->info.uses_persp_center ||
950 sel->info.uses_persp_centroid ||
951 sel->info.uses_linear_center ||
952 sel->info.uses_linear_centroid);
953 }
954
955 key->ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
956 break;
957 }
958 default:
959 assert(0);
960 }
961 }
962
963 /* Select the hw shader variant depending on the current state. */
964 static int si_shader_select_with_key(struct pipe_context *ctx,
965 struct si_shader_ctx_state *state,
966 union si_shader_key *key)
967 {
968 struct si_context *sctx = (struct si_context *)ctx;
969 struct si_shader_selector *sel = state->cso;
970 struct si_shader *current = state->current;
971 struct si_shader *iter, *shader = NULL;
972 int r;
973
974 /* Check if we don't need to change anything.
975 * This path is also used for most shaders that don't need multiple
976 * variants, it will cost just a computation of the key and this
977 * test. */
978 if (likely(current && memcmp(&current->key, key, sizeof(*key)) == 0))
979 return 0;
980
981 pipe_mutex_lock(sel->mutex);
982
983 /* Find the shader variant. */
984 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
985 /* Don't check the "current" shader. We checked it above. */
986 if (current != iter &&
987 memcmp(&iter->key, key, sizeof(*key)) == 0) {
988 state->current = iter;
989 pipe_mutex_unlock(sel->mutex);
990 return 0;
991 }
992 }
993
994 /* Build a new shader. */
995 shader = CALLOC_STRUCT(si_shader);
996 if (!shader) {
997 pipe_mutex_unlock(sel->mutex);
998 return -ENOMEM;
999 }
1000 shader->selector = sel;
1001 shader->key = *key;
1002
1003 r = si_shader_create(sctx->screen, sctx->tm, shader, &sctx->b.debug);
1004 if (unlikely(r)) {
1005 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1006 sel->type, r);
1007 FREE(shader);
1008 pipe_mutex_unlock(sel->mutex);
1009 return r;
1010 }
1011 si_shader_init_pm4_state(shader);
1012
1013 if (!sel->last_variant) {
1014 sel->first_variant = shader;
1015 sel->last_variant = shader;
1016 } else {
1017 sel->last_variant->next_variant = shader;
1018 sel->last_variant = shader;
1019 }
1020 state->current = shader;
1021 pipe_mutex_unlock(sel->mutex);
1022 return 0;
1023 }
1024
1025 static int si_shader_select(struct pipe_context *ctx,
1026 struct si_shader_ctx_state *state)
1027 {
1028 union si_shader_key key;
1029
1030 si_shader_selector_key(ctx, state->cso, &key);
1031 return si_shader_select_with_key(ctx, state, &key);
1032 }
1033
1034 static void *si_create_shader_selector(struct pipe_context *ctx,
1035 const struct pipe_shader_state *state)
1036 {
1037 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
1038 struct si_context *sctx = (struct si_context*)ctx;
1039 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
1040 int i;
1041
1042 if (!sel)
1043 return NULL;
1044
1045 sel->tokens = tgsi_dup_tokens(state->tokens);
1046 if (!sel->tokens) {
1047 FREE(sel);
1048 return NULL;
1049 }
1050
1051 sel->so = state->stream_output;
1052 tgsi_scan_shader(state->tokens, &sel->info);
1053 sel->type = util_pipe_shader_from_tgsi_processor(sel->info.processor);
1054 p_atomic_inc(&sscreen->b.num_shaders_created);
1055
1056 /* Set which opcode uses which (i,j) pair. */
1057 if (sel->info.uses_persp_opcode_interp_centroid)
1058 sel->info.uses_persp_centroid = true;
1059
1060 if (sel->info.uses_linear_opcode_interp_centroid)
1061 sel->info.uses_linear_centroid = true;
1062
1063 if (sel->info.uses_persp_opcode_interp_offset ||
1064 sel->info.uses_persp_opcode_interp_sample)
1065 sel->info.uses_persp_center = true;
1066
1067 if (sel->info.uses_linear_opcode_interp_offset ||
1068 sel->info.uses_linear_opcode_interp_sample)
1069 sel->info.uses_linear_center = true;
1070
1071 switch (sel->type) {
1072 case PIPE_SHADER_GEOMETRY:
1073 sel->gs_output_prim =
1074 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
1075 sel->gs_max_out_vertices =
1076 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
1077 sel->gs_num_invocations =
1078 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
1079 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
1080 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
1081 sel->gs_max_out_vertices;
1082
1083 sel->max_gs_stream = 0;
1084 for (i = 0; i < sel->so.num_outputs; i++)
1085 sel->max_gs_stream = MAX2(sel->max_gs_stream,
1086 sel->so.output[i].stream);
1087
1088 sel->gs_input_verts_per_prim =
1089 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
1090 break;
1091
1092 case PIPE_SHADER_VERTEX:
1093 case PIPE_SHADER_TESS_CTRL:
1094 case PIPE_SHADER_TESS_EVAL:
1095 for (i = 0; i < sel->info.num_outputs; i++) {
1096 unsigned name = sel->info.output_semantic_name[i];
1097 unsigned index = sel->info.output_semantic_index[i];
1098
1099 switch (name) {
1100 case TGSI_SEMANTIC_TESSINNER:
1101 case TGSI_SEMANTIC_TESSOUTER:
1102 case TGSI_SEMANTIC_PATCH:
1103 sel->patch_outputs_written |=
1104 1llu << si_shader_io_get_unique_index(name, index);
1105 break;
1106 default:
1107 sel->outputs_written |=
1108 1llu << si_shader_io_get_unique_index(name, index);
1109 }
1110 }
1111 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
1112 break;
1113
1114 case PIPE_SHADER_FRAGMENT:
1115 for (i = 0; i < 8; i++)
1116 if (sel->info.colors_written & (1 << i))
1117 sel->colors_written_4bit |= 0xf << (4 * i);
1118
1119 for (i = 0; i < sel->info.num_inputs; i++) {
1120 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
1121 int index = sel->info.input_semantic_index[i];
1122 sel->color_attr_index[index] = i;
1123 }
1124 }
1125 break;
1126 }
1127
1128 /* DB_SHADER_CONTROL */
1129 sel->db_shader_control =
1130 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
1131 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
1132 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
1133 S_02880C_KILL_ENABLE(sel->info.uses_kill);
1134
1135 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
1136 case TGSI_FS_DEPTH_LAYOUT_GREATER:
1137 sel->db_shader_control |=
1138 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
1139 break;
1140 case TGSI_FS_DEPTH_LAYOUT_LESS:
1141 sel->db_shader_control |=
1142 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
1143 break;
1144 }
1145
1146 /* Compile the main shader part for use with a prolog and/or epilog. */
1147 if (sel->type != PIPE_SHADER_GEOMETRY &&
1148 !sscreen->use_monolithic_shaders) {
1149 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1150 void *tgsi_binary;
1151
1152 if (!shader)
1153 goto error;
1154
1155 shader->selector = sel;
1156
1157 tgsi_binary = si_get_tgsi_binary(sel);
1158
1159 /* Try to load the shader from the shader cache. */
1160 pipe_mutex_lock(sscreen->shader_cache_mutex);
1161
1162 if (tgsi_binary &&
1163 si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
1164 FREE(tgsi_binary);
1165 } else {
1166 /* Compile the shader if it hasn't been loaded from the cache. */
1167 if (si_compile_tgsi_shader(sscreen, sctx->tm, shader, false,
1168 &sctx->b.debug) != 0) {
1169 FREE(shader);
1170 FREE(tgsi_binary);
1171 pipe_mutex_unlock(sscreen->shader_cache_mutex);
1172 goto error;
1173 }
1174
1175 if (tgsi_binary &&
1176 !si_shader_cache_insert_shader(sscreen, tgsi_binary, shader))
1177 FREE(tgsi_binary);
1178 }
1179 pipe_mutex_unlock(sscreen->shader_cache_mutex);
1180
1181 sel->main_shader_part = shader;
1182 }
1183
1184 /* Pre-compilation. */
1185 if (sel->type == PIPE_SHADER_GEOMETRY ||
1186 sscreen->b.debug_flags & DBG_PRECOMPILE) {
1187 struct si_shader_ctx_state state = {sel};
1188 union si_shader_key key;
1189
1190 memset(&key, 0, sizeof(key));
1191
1192 /* Set reasonable defaults, so that the shader key doesn't
1193 * cause any code to be eliminated.
1194 */
1195 switch (sel->type) {
1196 case PIPE_SHADER_TESS_CTRL:
1197 key.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
1198 break;
1199 case PIPE_SHADER_FRAGMENT:
1200 key.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
1201 for (i = 0; i < 8; i++)
1202 if (sel->info.colors_written & (1 << i))
1203 key.ps.epilog.spi_shader_col_format |=
1204 V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
1205 break;
1206 }
1207
1208 if (si_shader_select_with_key(ctx, &state, &key))
1209 goto error;
1210 }
1211
1212 pipe_mutex_init(sel->mutex);
1213 return sel;
1214
1215 error:
1216 fprintf(stderr, "radeonsi: can't create a shader\n");
1217 tgsi_free_tokens(sel->tokens);
1218 FREE(sel);
1219 return NULL;
1220 }
1221
1222 /**
1223 * Normally, we only emit 1 viewport and 1 scissor if no shader is using
1224 * the VIEWPORT_INDEX output, and emitting the other viewports and scissors
1225 * is delayed. When a shader with VIEWPORT_INDEX appears, this should be
1226 * called to emit the rest.
1227 */
1228 static void si_update_viewports_and_scissors(struct si_context *sctx)
1229 {
1230 struct tgsi_shader_info *info = si_get_vs_info(sctx);
1231
1232 if (!info || !info->writes_viewport_index)
1233 return;
1234
1235 if (sctx->scissors.dirty_mask)
1236 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
1237 if (sctx->viewports.dirty_mask)
1238 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
1239 }
1240
1241 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
1242 {
1243 struct si_context *sctx = (struct si_context *)ctx;
1244 struct si_shader_selector *sel = state;
1245
1246 if (sctx->vs_shader.cso == sel)
1247 return;
1248
1249 sctx->vs_shader.cso = sel;
1250 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
1251 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1252 si_update_viewports_and_scissors(sctx);
1253 }
1254
1255 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
1256 {
1257 struct si_context *sctx = (struct si_context *)ctx;
1258 struct si_shader_selector *sel = state;
1259 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
1260
1261 if (sctx->gs_shader.cso == sel)
1262 return;
1263
1264 sctx->gs_shader.cso = sel;
1265 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
1266 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1267 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1268
1269 if (enable_changed)
1270 si_shader_change_notify(sctx);
1271 si_update_viewports_and_scissors(sctx);
1272 }
1273
1274 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
1275 {
1276 struct si_context *sctx = (struct si_context *)ctx;
1277 struct si_shader_selector *sel = state;
1278 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
1279
1280 if (sctx->tcs_shader.cso == sel)
1281 return;
1282
1283 sctx->tcs_shader.cso = sel;
1284 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
1285
1286 if (enable_changed)
1287 sctx->last_tcs = NULL; /* invalidate derived tess state */
1288 }
1289
1290 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
1291 {
1292 struct si_context *sctx = (struct si_context *)ctx;
1293 struct si_shader_selector *sel = state;
1294 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
1295
1296 if (sctx->tes_shader.cso == sel)
1297 return;
1298
1299 sctx->tes_shader.cso = sel;
1300 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
1301 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1302 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1303
1304 if (enable_changed) {
1305 si_shader_change_notify(sctx);
1306 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
1307 }
1308 si_update_viewports_and_scissors(sctx);
1309 }
1310
1311 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
1312 {
1313 struct si_context *sctx = (struct si_context *)ctx;
1314 struct si_shader_selector *sel = state;
1315
1316 /* skip if supplied shader is one already in use */
1317 if (sctx->ps_shader.cso == sel)
1318 return;
1319
1320 sctx->ps_shader.cso = sel;
1321 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
1322 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
1323 }
1324
1325 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
1326 {
1327 if (shader->pm4) {
1328 switch (shader->selector->type) {
1329 case PIPE_SHADER_VERTEX:
1330 if (shader->key.vs.as_ls)
1331 si_pm4_delete_state(sctx, ls, shader->pm4);
1332 else if (shader->key.vs.as_es)
1333 si_pm4_delete_state(sctx, es, shader->pm4);
1334 else
1335 si_pm4_delete_state(sctx, vs, shader->pm4);
1336 break;
1337 case PIPE_SHADER_TESS_CTRL:
1338 si_pm4_delete_state(sctx, hs, shader->pm4);
1339 break;
1340 case PIPE_SHADER_TESS_EVAL:
1341 if (shader->key.tes.as_es)
1342 si_pm4_delete_state(sctx, es, shader->pm4);
1343 else
1344 si_pm4_delete_state(sctx, vs, shader->pm4);
1345 break;
1346 case PIPE_SHADER_GEOMETRY:
1347 si_pm4_delete_state(sctx, gs, shader->pm4);
1348 si_pm4_delete_state(sctx, vs, shader->gs_copy_shader->pm4);
1349 break;
1350 case PIPE_SHADER_FRAGMENT:
1351 si_pm4_delete_state(sctx, ps, shader->pm4);
1352 break;
1353 }
1354 }
1355
1356 si_shader_destroy(shader);
1357 free(shader);
1358 }
1359
1360 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
1361 {
1362 struct si_context *sctx = (struct si_context *)ctx;
1363 struct si_shader_selector *sel = (struct si_shader_selector *)state;
1364 struct si_shader *p = sel->first_variant, *c;
1365 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
1366 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
1367 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
1368 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
1369 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
1370 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
1371 };
1372
1373 if (current_shader[sel->type]->cso == sel) {
1374 current_shader[sel->type]->cso = NULL;
1375 current_shader[sel->type]->current = NULL;
1376 }
1377
1378 while (p) {
1379 c = p->next_variant;
1380 si_delete_shader(sctx, p);
1381 p = c;
1382 }
1383
1384 if (sel->main_shader_part)
1385 si_delete_shader(sctx, sel->main_shader_part);
1386
1387 pipe_mutex_destroy(sel->mutex);
1388 free(sel->tokens);
1389 free(sel);
1390 }
1391
1392 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
1393 struct si_shader *vs, unsigned name,
1394 unsigned index, unsigned interpolate)
1395 {
1396 struct tgsi_shader_info *vsinfo = &vs->selector->info;
1397 unsigned j, ps_input_cntl = 0;
1398
1399 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
1400 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
1401 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1402
1403 if (name == TGSI_SEMANTIC_PCOORD ||
1404 (name == TGSI_SEMANTIC_TEXCOORD &&
1405 sctx->sprite_coord_enable & (1 << index))) {
1406 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
1407 }
1408
1409 for (j = 0; j < vsinfo->num_outputs; j++) {
1410 if (name == vsinfo->output_semantic_name[j] &&
1411 index == vsinfo->output_semantic_index[j]) {
1412 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[j]);
1413 break;
1414 }
1415 }
1416
1417 if (name == TGSI_SEMANTIC_PRIMID)
1418 /* PrimID is written after the last output. */
1419 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
1420 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
1421 /* No corresponding output found, load defaults into input.
1422 * Don't set any other bits.
1423 * (FLAT_SHADE=1 completely changes behavior) */
1424 ps_input_cntl = S_028644_OFFSET(0x20);
1425 }
1426 return ps_input_cntl;
1427 }
1428
1429 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
1430 {
1431 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1432 struct si_shader *ps = sctx->ps_shader.current;
1433 struct si_shader *vs = si_get_vs_state(sctx);
1434 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
1435 unsigned i, num_interp, num_written = 0, bcol_interp[2];
1436
1437 if (!ps || !ps->selector->info.num_inputs)
1438 return;
1439
1440 num_interp = si_get_ps_num_interp(ps);
1441 assert(num_interp > 0);
1442 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
1443
1444 for (i = 0; i < psinfo->num_inputs; i++) {
1445 unsigned name = psinfo->input_semantic_name[i];
1446 unsigned index = psinfo->input_semantic_index[i];
1447 unsigned interpolate = psinfo->input_interpolate[i];
1448
1449 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
1450 interpolate));
1451 num_written++;
1452
1453 if (name == TGSI_SEMANTIC_COLOR) {
1454 assert(index < ARRAY_SIZE(bcol_interp));
1455 bcol_interp[index] = interpolate;
1456 }
1457 }
1458
1459 if (ps->key.ps.prolog.color_two_side) {
1460 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
1461
1462 for (i = 0; i < 2; i++) {
1463 if (!(psinfo->colors_read & (0xf << (i * 4))))
1464 continue;
1465
1466 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
1467 i, bcol_interp[i]));
1468 num_written++;
1469 }
1470 }
1471 assert(num_interp == num_written);
1472 }
1473
1474 /**
1475 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
1476 */
1477 static void si_init_config_add_vgt_flush(struct si_context *sctx)
1478 {
1479 if (sctx->init_config_has_vgt_flush)
1480 return;
1481
1482 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
1483 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
1484 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1485 si_pm4_cmd_end(sctx->init_config, false);
1486 sctx->init_config_has_vgt_flush = true;
1487 }
1488
1489 /* Initialize state related to ESGS / GSVS ring buffers */
1490 static bool si_update_gs_ring_buffers(struct si_context *sctx)
1491 {
1492 struct si_shader_selector *es =
1493 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
1494 struct si_shader_selector *gs = sctx->gs_shader.cso;
1495 struct si_pm4_state *pm4;
1496
1497 /* Chip constants. */
1498 unsigned num_se = sctx->screen->b.info.max_se;
1499 unsigned wave_size = 64;
1500 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1501 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1502 unsigned alignment = 256 * num_se;
1503 /* The maximum size is 63.999 MB per SE. */
1504 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1505
1506 /* Calculate the minimum size. */
1507 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
1508 wave_size, alignment);
1509
1510 /* These are recommended sizes, not minimum sizes. */
1511 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1512 es->esgs_itemsize * gs->gs_input_verts_per_prim;
1513 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1514 gs->max_gsvs_emit_size * (gs->max_gs_stream + 1);
1515
1516 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1517 esgs_ring_size = align(esgs_ring_size, alignment);
1518 gsvs_ring_size = align(gsvs_ring_size, alignment);
1519
1520 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1521 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1522
1523 /* Some rings don't have to be allocated if shaders don't use them.
1524 * (e.g. no varyings between ES and GS or GS and VS)
1525 */
1526 bool update_esgs = esgs_ring_size &&
1527 (!sctx->esgs_ring ||
1528 sctx->esgs_ring->width0 < esgs_ring_size);
1529 bool update_gsvs = gsvs_ring_size &&
1530 (!sctx->gsvs_ring ||
1531 sctx->gsvs_ring->width0 < gsvs_ring_size);
1532
1533 if (!update_esgs && !update_gsvs)
1534 return true;
1535
1536 if (update_esgs) {
1537 pipe_resource_reference(&sctx->esgs_ring, NULL);
1538 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1539 PIPE_USAGE_DEFAULT,
1540 esgs_ring_size);
1541 if (!sctx->esgs_ring)
1542 return false;
1543 }
1544
1545 if (update_gsvs) {
1546 pipe_resource_reference(&sctx->gsvs_ring, NULL);
1547 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1548 PIPE_USAGE_DEFAULT,
1549 gsvs_ring_size);
1550 if (!sctx->gsvs_ring)
1551 return false;
1552 }
1553
1554 /* Create the "init_config_gs_rings" state. */
1555 pm4 = CALLOC_STRUCT(si_pm4_state);
1556 if (!pm4)
1557 return false;
1558
1559 if (sctx->b.chip_class >= CIK) {
1560 if (sctx->esgs_ring)
1561 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
1562 sctx->esgs_ring->width0 / 256);
1563 if (sctx->gsvs_ring)
1564 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
1565 sctx->gsvs_ring->width0 / 256);
1566 } else {
1567 if (sctx->esgs_ring)
1568 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
1569 sctx->esgs_ring->width0 / 256);
1570 if (sctx->gsvs_ring)
1571 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
1572 sctx->gsvs_ring->width0 / 256);
1573 }
1574
1575 /* Set the state. */
1576 if (sctx->init_config_gs_rings)
1577 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
1578 sctx->init_config_gs_rings = pm4;
1579
1580 if (!sctx->init_config_has_vgt_flush) {
1581 si_init_config_add_vgt_flush(sctx);
1582 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1583 }
1584
1585 /* Flush the context to re-emit both init_config states. */
1586 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1587 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1588
1589 /* Set ring bindings. */
1590 if (sctx->esgs_ring) {
1591 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
1592 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1593 true, true, 4, 64, 0);
1594 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
1595 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1596 false, false, 0, 0, 0);
1597 }
1598 if (sctx->gsvs_ring)
1599 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
1600 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
1601 false, false, 0, 0, 0);
1602 return true;
1603 }
1604
1605 static void si_update_gsvs_ring_bindings(struct si_context *sctx)
1606 {
1607 unsigned gsvs_itemsize = sctx->gs_shader.cso->max_gsvs_emit_size;
1608 uint64_t offset;
1609
1610 if (!sctx->gsvs_ring || gsvs_itemsize == sctx->last_gsvs_itemsize)
1611 return;
1612
1613 sctx->last_gsvs_itemsize = gsvs_itemsize;
1614
1615 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
1616 sctx->gsvs_ring, gsvs_itemsize,
1617 64, true, true, 4, 16, 0);
1618
1619 offset = gsvs_itemsize * 64;
1620 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_1,
1621 sctx->gsvs_ring, gsvs_itemsize,
1622 64, true, true, 4, 16, offset);
1623
1624 offset = (gsvs_itemsize * 2) * 64;
1625 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_2,
1626 sctx->gsvs_ring, gsvs_itemsize,
1627 64, true, true, 4, 16, offset);
1628
1629 offset = (gsvs_itemsize * 3) * 64;
1630 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_3,
1631 sctx->gsvs_ring, gsvs_itemsize,
1632 64, true, true, 4, 16, offset);
1633 }
1634
1635 /**
1636 * @returns 1 if \p sel has been updated to use a new scratch buffer
1637 * 0 if not
1638 * < 0 if there was a failure
1639 */
1640 static int si_update_scratch_buffer(struct si_context *sctx,
1641 struct si_shader *shader)
1642 {
1643 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
1644 int r;
1645
1646 if (!shader)
1647 return 0;
1648
1649 /* This shader doesn't need a scratch buffer */
1650 if (shader->config.scratch_bytes_per_wave == 0)
1651 return 0;
1652
1653 /* This shader is already configured to use the current
1654 * scratch buffer. */
1655 if (shader->scratch_bo == sctx->scratch_buffer)
1656 return 0;
1657
1658 assert(sctx->scratch_buffer);
1659
1660 si_shader_apply_scratch_relocs(sctx, shader, scratch_va);
1661
1662 /* Replace the shader bo with a new bo that has the relocs applied. */
1663 r = si_shader_binary_upload(sctx->screen, shader);
1664 if (r)
1665 return r;
1666
1667 /* Update the shader state to use the new shader bo. */
1668 si_shader_init_pm4_state(shader);
1669
1670 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
1671
1672 return 1;
1673 }
1674
1675 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
1676 {
1677 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
1678 }
1679
1680 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
1681 {
1682 return shader ? shader->config.scratch_bytes_per_wave : 0;
1683 }
1684
1685 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
1686 {
1687 unsigned bytes = 0;
1688
1689 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
1690 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
1691 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
1692 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tcs_shader.current));
1693 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
1694 return bytes;
1695 }
1696
1697 static bool si_update_spi_tmpring_size(struct si_context *sctx)
1698 {
1699 unsigned current_scratch_buffer_size =
1700 si_get_current_scratch_buffer_size(sctx);
1701 unsigned scratch_bytes_per_wave =
1702 si_get_max_scratch_bytes_per_wave(sctx);
1703 unsigned scratch_needed_size = scratch_bytes_per_wave *
1704 sctx->scratch_waves;
1705 unsigned spi_tmpring_size;
1706 int r;
1707
1708 if (scratch_needed_size > 0) {
1709 if (scratch_needed_size > current_scratch_buffer_size) {
1710 /* Create a bigger scratch buffer */
1711 pipe_resource_reference(
1712 (struct pipe_resource**)&sctx->scratch_buffer,
1713 NULL);
1714
1715 sctx->scratch_buffer =
1716 si_resource_create_custom(&sctx->screen->b.b,
1717 PIPE_USAGE_DEFAULT, scratch_needed_size);
1718 if (!sctx->scratch_buffer)
1719 return false;
1720 sctx->emit_scratch_reloc = true;
1721 }
1722
1723 /* Update the shaders, so they are using the latest scratch. The
1724 * scratch buffer may have been changed since these shaders were
1725 * last used, so we still need to try to update them, even if
1726 * they require scratch buffers smaller than the current size.
1727 */
1728 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
1729 if (r < 0)
1730 return false;
1731 if (r == 1)
1732 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
1733
1734 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
1735 if (r < 0)
1736 return false;
1737 if (r == 1)
1738 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1739
1740 r = si_update_scratch_buffer(sctx, sctx->tcs_shader.current);
1741 if (r < 0)
1742 return false;
1743 if (r == 1)
1744 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1745
1746 /* VS can be bound as LS, ES, or VS. */
1747 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
1748 if (r < 0)
1749 return false;
1750 if (r == 1) {
1751 if (sctx->tes_shader.current)
1752 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1753 else if (sctx->gs_shader.current)
1754 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1755 else
1756 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1757 }
1758
1759 /* TES can be bound as ES or VS. */
1760 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
1761 if (r < 0)
1762 return false;
1763 if (r == 1) {
1764 if (sctx->gs_shader.current)
1765 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1766 else
1767 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1768 }
1769 }
1770
1771 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
1772 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
1773 "scratch size should already be aligned correctly.");
1774
1775 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
1776 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
1777 if (spi_tmpring_size != sctx->spi_tmpring_size) {
1778 sctx->spi_tmpring_size = spi_tmpring_size;
1779 sctx->emit_scratch_reloc = true;
1780 }
1781 return true;
1782 }
1783
1784 static void si_init_tess_factor_ring(struct si_context *sctx)
1785 {
1786 assert(!sctx->tf_ring);
1787
1788 sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1789 PIPE_USAGE_DEFAULT,
1790 32768 * sctx->screen->b.info.max_se);
1791 if (!sctx->tf_ring)
1792 return;
1793
1794 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
1795
1796 si_init_config_add_vgt_flush(sctx);
1797
1798 /* Append these registers to the init config state. */
1799 if (sctx->b.chip_class >= CIK) {
1800 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
1801 S_030938_SIZE(sctx->tf_ring->width0 / 4));
1802 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
1803 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1804 } else {
1805 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
1806 S_008988_SIZE(sctx->tf_ring->width0 / 4));
1807 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
1808 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1809 }
1810
1811 /* Flush the context to re-emit the init_config state.
1812 * This is done only once in a lifetime of a context.
1813 */
1814 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1815 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1816 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1817
1818 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_TESS_CTRL,
1819 SI_RING_TESS_FACTOR, sctx->tf_ring, 0,
1820 sctx->tf_ring->width0, false, false, 0, 0, 0);
1821 }
1822
1823 /**
1824 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
1825 * VS passes its outputs to TES directly, so the fixed-function shader only
1826 * has to write TESSOUTER and TESSINNER.
1827 */
1828 static void si_generate_fixed_func_tcs(struct si_context *sctx)
1829 {
1830 struct ureg_src const0, const1;
1831 struct ureg_dst tessouter, tessinner;
1832 struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
1833
1834 if (!ureg)
1835 return; /* if we get here, we're screwed */
1836
1837 assert(!sctx->fixed_func_tcs_shader.cso);
1838
1839 ureg_DECL_constant2D(ureg, 0, 1, SI_DRIVER_STATE_CONST_BUF);
1840 const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 0),
1841 SI_DRIVER_STATE_CONST_BUF);
1842 const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 1),
1843 SI_DRIVER_STATE_CONST_BUF);
1844
1845 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1846 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1847
1848 ureg_MOV(ureg, tessouter, const0);
1849 ureg_MOV(ureg, tessinner, const1);
1850 ureg_END(ureg);
1851
1852 sctx->fixed_func_tcs_shader.cso =
1853 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
1854 }
1855
1856 static void si_update_vgt_shader_config(struct si_context *sctx)
1857 {
1858 /* Calculate the index of the config.
1859 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
1860 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
1861 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
1862
1863 if (!*pm4) {
1864 uint32_t stages = 0;
1865
1866 *pm4 = CALLOC_STRUCT(si_pm4_state);
1867
1868 if (sctx->tes_shader.cso) {
1869 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
1870 S_028B54_HS_EN(1);
1871
1872 if (sctx->gs_shader.cso)
1873 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
1874 S_028B54_GS_EN(1) |
1875 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1876 else
1877 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
1878 } else if (sctx->gs_shader.cso) {
1879 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1880 S_028B54_GS_EN(1) |
1881 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1882 }
1883
1884 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
1885 }
1886 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
1887 }
1888
1889 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
1890 {
1891 struct pipe_stream_output_info *so = &shader->so;
1892 uint32_t enabled_stream_buffers_mask = 0;
1893 int i;
1894
1895 for (i = 0; i < so->num_outputs; i++)
1896 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
1897 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
1898 sctx->b.streamout.stride_in_dw = shader->so.stride;
1899 }
1900
1901 bool si_update_shaders(struct si_context *sctx)
1902 {
1903 struct pipe_context *ctx = (struct pipe_context*)sctx;
1904 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1905 int r;
1906
1907 /* Update stages before GS. */
1908 if (sctx->tes_shader.cso) {
1909 if (!sctx->tf_ring) {
1910 si_init_tess_factor_ring(sctx);
1911 if (!sctx->tf_ring)
1912 return false;
1913 }
1914
1915 /* VS as LS */
1916 r = si_shader_select(ctx, &sctx->vs_shader);
1917 if (r)
1918 return false;
1919 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1920
1921 if (sctx->tcs_shader.cso) {
1922 r = si_shader_select(ctx, &sctx->tcs_shader);
1923 if (r)
1924 return false;
1925 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1926 } else {
1927 if (!sctx->fixed_func_tcs_shader.cso) {
1928 si_generate_fixed_func_tcs(sctx);
1929 if (!sctx->fixed_func_tcs_shader.cso)
1930 return false;
1931 }
1932
1933 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader);
1934 if (r)
1935 return false;
1936 si_pm4_bind_state(sctx, hs,
1937 sctx->fixed_func_tcs_shader.current->pm4);
1938 }
1939
1940 r = si_shader_select(ctx, &sctx->tes_shader);
1941 if (r)
1942 return false;
1943
1944 if (sctx->gs_shader.cso) {
1945 /* TES as ES */
1946 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1947 } else {
1948 /* TES as VS */
1949 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1950 si_update_so(sctx, sctx->tes_shader.cso);
1951 }
1952 } else if (sctx->gs_shader.cso) {
1953 /* VS as ES */
1954 r = si_shader_select(ctx, &sctx->vs_shader);
1955 if (r)
1956 return false;
1957 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1958 } else {
1959 /* VS as VS */
1960 r = si_shader_select(ctx, &sctx->vs_shader);
1961 if (r)
1962 return false;
1963 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1964 si_update_so(sctx, sctx->vs_shader.cso);
1965 }
1966
1967 /* Update GS. */
1968 if (sctx->gs_shader.cso) {
1969 r = si_shader_select(ctx, &sctx->gs_shader);
1970 if (r)
1971 return false;
1972 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1973 si_pm4_bind_state(sctx, vs, sctx->gs_shader.current->gs_copy_shader->pm4);
1974 si_update_so(sctx, sctx->gs_shader.cso);
1975
1976 if (!si_update_gs_ring_buffers(sctx))
1977 return false;
1978
1979 si_update_gsvs_ring_bindings(sctx);
1980 } else {
1981 si_pm4_bind_state(sctx, gs, NULL);
1982 si_pm4_bind_state(sctx, es, NULL);
1983 }
1984
1985 si_update_vgt_shader_config(sctx);
1986
1987 if (sctx->ps_shader.cso) {
1988 unsigned db_shader_control =
1989 sctx->ps_shader.cso->db_shader_control |
1990 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
1991
1992 r = si_shader_select(ctx, &sctx->ps_shader);
1993 if (r)
1994 return false;
1995 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
1996
1997 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
1998 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
1999 sctx->flatshade != rs->flatshade) {
2000 sctx->sprite_coord_enable = rs->sprite_coord_enable;
2001 sctx->flatshade = rs->flatshade;
2002 si_mark_atom_dirty(sctx, &sctx->spi_map);
2003 }
2004
2005 if (sctx->b.family == CHIP_STONEY && si_pm4_state_changed(sctx, ps))
2006 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2007
2008 if (sctx->ps_db_shader_control != db_shader_control) {
2009 sctx->ps_db_shader_control = db_shader_control;
2010 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2011 }
2012
2013 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.ps.epilog.poly_line_smoothing) {
2014 sctx->smoothing_enabled = sctx->ps_shader.current->key.ps.epilog.poly_line_smoothing;
2015 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2016
2017 if (sctx->b.chip_class == SI)
2018 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2019 }
2020 }
2021
2022 if (si_pm4_state_changed(sctx, ls) ||
2023 si_pm4_state_changed(sctx, hs) ||
2024 si_pm4_state_changed(sctx, es) ||
2025 si_pm4_state_changed(sctx, gs) ||
2026 si_pm4_state_changed(sctx, vs) ||
2027 si_pm4_state_changed(sctx, ps)) {
2028 if (!si_update_spi_tmpring_size(sctx))
2029 return false;
2030 }
2031 return true;
2032 }
2033
2034 void si_init_shader_functions(struct si_context *sctx)
2035 {
2036 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
2037
2038 sctx->b.b.create_vs_state = si_create_shader_selector;
2039 sctx->b.b.create_tcs_state = si_create_shader_selector;
2040 sctx->b.b.create_tes_state = si_create_shader_selector;
2041 sctx->b.b.create_gs_state = si_create_shader_selector;
2042 sctx->b.b.create_fs_state = si_create_shader_selector;
2043
2044 sctx->b.b.bind_vs_state = si_bind_vs_shader;
2045 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
2046 sctx->b.b.bind_tes_state = si_bind_tes_shader;
2047 sctx->b.b.bind_gs_state = si_bind_gs_shader;
2048 sctx->b.b.bind_fs_state = si_bind_ps_shader;
2049
2050 sctx->b.b.delete_vs_state = si_delete_shader_selector;
2051 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
2052 sctx->b.b.delete_tes_state = si_delete_shader_selector;
2053 sctx->b.b.delete_gs_state = si_delete_shader_selector;
2054 sctx->b.b.delete_fs_state = si_delete_shader_selector;
2055 }