2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "radeon/r600_cs.h"
29 #include "compiler/nir/nir_serialize.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "tgsi/tgsi_ureg.h"
32 #include "util/hash_table.h"
33 #include "util/crc32.h"
34 #include "util/u_async_debug.h"
35 #include "util/u_memory.h"
36 #include "util/u_prim.h"
38 #include "util/disk_cache.h"
39 #include "util/mesa-sha1.h"
40 #include "ac_exp_param.h"
41 #include "ac_shader_util.h"
46 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
49 static void *si_get_ir_binary(struct si_shader_selector
*sel
)
56 ir_binary
= sel
->tokens
;
57 ir_size
= tgsi_num_tokens(sel
->tokens
) *
58 sizeof(struct tgsi_token
);
63 nir_serialize(&blob
, sel
->nir
);
64 ir_binary
= blob
.data
;
68 unsigned size
= 4 + ir_size
+ sizeof(sel
->so
);
69 char *result
= (char*)MALLOC(size
);
73 *((uint32_t*)result
) = size
;
74 memcpy(result
+ 4, ir_binary
, ir_size
);
75 memcpy(result
+ 4 + ir_size
, &sel
->so
, sizeof(sel
->so
));
83 /** Copy "data" to "ptr" and return the next dword following copied data. */
84 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
86 /* data may be NULL if size == 0 */
88 memcpy(ptr
, data
, size
);
89 ptr
+= DIV_ROUND_UP(size
, 4);
93 /** Read data from "ptr". Return the next dword following the data. */
94 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
96 memcpy(data
, ptr
, size
);
97 ptr
+= DIV_ROUND_UP(size
, 4);
102 * Write the size as uint followed by the data. Return the next dword
103 * following the copied data.
105 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
108 return write_data(ptr
, data
, size
);
112 * Read the size as uint followed by the data. Return both via parameters.
113 * Return the next dword following the data.
115 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
118 assert(*data
== NULL
);
121 *data
= malloc(*size
);
122 return read_data(ptr
, *data
, *size
);
126 * Return the shader binary in a buffer. The first 4 bytes contain its size
129 static void *si_get_shader_binary(struct si_shader
*shader
)
131 /* There is always a size of data followed by the data itself. */
132 unsigned relocs_size
= shader
->binary
.reloc_count
*
133 sizeof(shader
->binary
.relocs
[0]);
134 unsigned disasm_size
= shader
->binary
.disasm_string
?
135 strlen(shader
->binary
.disasm_string
) + 1 : 0;
136 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
137 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
140 4 + /* CRC32 of the data below */
141 align(sizeof(shader
->config
), 4) +
142 align(sizeof(shader
->info
), 4) +
143 4 + align(shader
->binary
.code_size
, 4) +
144 4 + align(shader
->binary
.rodata_size
, 4) +
145 4 + align(relocs_size
, 4) +
146 4 + align(disasm_size
, 4) +
147 4 + align(llvm_ir_size
, 4);
148 void *buffer
= CALLOC(1, size
);
149 uint32_t *ptr
= (uint32_t*)buffer
;
155 ptr
++; /* CRC32 is calculated at the end. */
157 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
158 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
159 ptr
= write_chunk(ptr
, shader
->binary
.code
, shader
->binary
.code_size
);
160 ptr
= write_chunk(ptr
, shader
->binary
.rodata
, shader
->binary
.rodata_size
);
161 ptr
= write_chunk(ptr
, shader
->binary
.relocs
, relocs_size
);
162 ptr
= write_chunk(ptr
, shader
->binary
.disasm_string
, disasm_size
);
163 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
164 assert((char *)ptr
- (char *)buffer
== size
);
167 ptr
= (uint32_t*)buffer
;
169 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
174 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
176 uint32_t *ptr
= (uint32_t*)binary
;
177 uint32_t size
= *ptr
++;
178 uint32_t crc32
= *ptr
++;
181 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
182 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
186 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
187 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
188 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.code
,
189 &shader
->binary
.code_size
);
190 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.rodata
,
191 &shader
->binary
.rodata_size
);
192 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.relocs
, &chunk_size
);
193 shader
->binary
.reloc_count
= chunk_size
/ sizeof(shader
->binary
.relocs
[0]);
194 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.disasm_string
, &chunk_size
);
195 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
201 * Insert a shader into the cache. It's assumed the shader is not in the cache.
202 * Use si_shader_cache_load_shader before calling this.
204 * Returns false on failure, in which case the ir_binary should be freed.
206 static bool si_shader_cache_insert_shader(struct si_screen
*sscreen
,
208 struct si_shader
*shader
,
209 bool insert_into_disk_cache
)
212 struct hash_entry
*entry
;
213 uint8_t key
[CACHE_KEY_SIZE
];
215 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
217 return false; /* already added */
219 hw_binary
= si_get_shader_binary(shader
);
223 if (_mesa_hash_table_insert(sscreen
->shader_cache
, ir_binary
,
224 hw_binary
) == NULL
) {
229 if (sscreen
->disk_shader_cache
&& insert_into_disk_cache
) {
230 disk_cache_compute_key(sscreen
->disk_shader_cache
, ir_binary
,
231 *((uint32_t *)ir_binary
), key
);
232 disk_cache_put(sscreen
->disk_shader_cache
, key
, hw_binary
,
233 *((uint32_t *) hw_binary
), NULL
);
239 static bool si_shader_cache_load_shader(struct si_screen
*sscreen
,
241 struct si_shader
*shader
)
243 struct hash_entry
*entry
=
244 _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
246 if (sscreen
->disk_shader_cache
) {
247 unsigned char sha1
[CACHE_KEY_SIZE
];
248 size_t tg_size
= *((uint32_t *) ir_binary
);
250 disk_cache_compute_key(sscreen
->disk_shader_cache
,
251 ir_binary
, tg_size
, sha1
);
255 disk_cache_get(sscreen
->disk_shader_cache
,
260 if (binary_size
< sizeof(uint32_t) ||
261 *((uint32_t*)buffer
) != binary_size
) {
262 /* Something has gone wrong discard the item
263 * from the cache and rebuild/link from
266 assert(!"Invalid radeonsi shader disk cache "
269 disk_cache_remove(sscreen
->disk_shader_cache
,
276 if (!si_load_shader_binary(shader
, buffer
)) {
282 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
,
289 if (si_load_shader_binary(shader
, entry
->data
))
294 p_atomic_inc(&sscreen
->num_shader_cache_hits
);
298 static uint32_t si_shader_cache_key_hash(const void *key
)
300 /* The first dword is the key size. */
301 return util_hash_crc32(key
, *(uint32_t*)key
);
304 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
306 uint32_t *keya
= (uint32_t*)a
;
307 uint32_t *keyb
= (uint32_t*)b
;
309 /* The first dword is the key size. */
313 return memcmp(keya
, keyb
, *keya
) == 0;
316 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
318 FREE((void*)entry
->key
);
322 bool si_init_shader_cache(struct si_screen
*sscreen
)
324 (void) mtx_init(&sscreen
->shader_cache_mutex
, mtx_plain
);
325 sscreen
->shader_cache
=
326 _mesa_hash_table_create(NULL
,
327 si_shader_cache_key_hash
,
328 si_shader_cache_key_equals
);
330 return sscreen
->shader_cache
!= NULL
;
333 void si_destroy_shader_cache(struct si_screen
*sscreen
)
335 if (sscreen
->shader_cache
)
336 _mesa_hash_table_destroy(sscreen
->shader_cache
,
337 si_destroy_shader_cache_entry
);
338 mtx_destroy(&sscreen
->shader_cache_mutex
);
343 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
344 struct si_shader_selector
*tes
,
345 struct si_pm4_state
*pm4
)
347 struct tgsi_shader_info
*info
= &tes
->info
;
348 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
349 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
350 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
351 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
352 unsigned type
, partitioning
, topology
, distribution_mode
;
354 switch (tes_prim_mode
) {
355 case PIPE_PRIM_LINES
:
356 type
= V_028B6C_TESS_ISOLINE
;
358 case PIPE_PRIM_TRIANGLES
:
359 type
= V_028B6C_TESS_TRIANGLE
;
361 case PIPE_PRIM_QUADS
:
362 type
= V_028B6C_TESS_QUAD
;
369 switch (tes_spacing
) {
370 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
371 partitioning
= V_028B6C_PART_FRAC_ODD
;
373 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
374 partitioning
= V_028B6C_PART_FRAC_EVEN
;
376 case PIPE_TESS_SPACING_EQUAL
:
377 partitioning
= V_028B6C_PART_INTEGER
;
385 topology
= V_028B6C_OUTPUT_POINT
;
386 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
387 topology
= V_028B6C_OUTPUT_LINE
;
388 else if (tes_vertex_order_cw
)
389 /* for some reason, this must be the other way around */
390 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
392 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
394 if (sscreen
->has_distributed_tess
) {
395 if (sscreen
->info
.family
== CHIP_FIJI
||
396 sscreen
->info
.family
>= CHIP_POLARIS10
)
397 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
399 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
401 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
403 si_pm4_set_reg(pm4
, R_028B6C_VGT_TF_PARAM
,
404 S_028B6C_TYPE(type
) |
405 S_028B6C_PARTITIONING(partitioning
) |
406 S_028B6C_TOPOLOGY(topology
) |
407 S_028B6C_DISTRIBUTION_MODE(distribution_mode
));
410 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
411 * whether the "fractional odd" tessellation spacing is used.
413 * Possible VGT configurations and which state should set the register:
415 * Reg set in | VGT shader configuration | Value
416 * ------------------------------------------------------
418 * VS as ES | ES -> GS -> VS | 30
419 * TES as VS | LS -> HS -> VS | 14 or 30
420 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
422 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
424 static void polaris_set_vgt_vertex_reuse(struct si_screen
*sscreen
,
425 struct si_shader_selector
*sel
,
426 struct si_shader
*shader
,
427 struct si_pm4_state
*pm4
)
429 unsigned type
= sel
->type
;
431 if (sscreen
->info
.family
< CHIP_POLARIS10
)
434 /* VS as VS, or VS as ES: */
435 if ((type
== PIPE_SHADER_VERTEX
&&
437 (!shader
->key
.as_ls
&& !shader
->is_gs_copy_shader
))) ||
438 /* TES as VS, or TES as ES: */
439 type
== PIPE_SHADER_TESS_EVAL
) {
440 unsigned vtx_reuse_depth
= 30;
442 if (type
== PIPE_SHADER_TESS_EVAL
&&
443 sel
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] ==
444 PIPE_TESS_SPACING_FRACTIONAL_ODD
)
445 vtx_reuse_depth
= 14;
447 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
452 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
455 si_pm4_clear_state(shader
->pm4
);
457 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
462 static void si_shader_ls(struct si_screen
*sscreen
, struct si_shader
*shader
)
464 struct si_pm4_state
*pm4
;
465 unsigned vgpr_comp_cnt
;
468 assert(sscreen
->info
.chip_class
<= VI
);
470 pm4
= si_get_shader_pm4_state(shader
);
474 va
= shader
->bo
->gpu_address
;
475 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
477 /* We need at least 2 components for LS.
478 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
479 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
481 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
483 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
484 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, va
>> 40);
486 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
487 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
488 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt
) |
489 S_00B528_DX10_CLAMP(1) |
490 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
491 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(SI_VS_NUM_USER_SGPR
) |
492 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
495 static void si_shader_hs(struct si_screen
*sscreen
, struct si_shader
*shader
)
497 struct si_pm4_state
*pm4
;
499 unsigned ls_vgpr_comp_cnt
= 0;
501 pm4
= si_get_shader_pm4_state(shader
);
505 va
= shader
->bo
->gpu_address
;
506 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
508 if (sscreen
->info
.chip_class
>= GFX9
) {
509 si_pm4_set_reg(pm4
, R_00B410_SPI_SHADER_PGM_LO_LS
, va
>> 8);
510 si_pm4_set_reg(pm4
, R_00B414_SPI_SHADER_PGM_HI_LS
, va
>> 40);
512 /* We need at least 2 components for LS.
513 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
514 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
516 ls_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
518 shader
->config
.rsrc2
=
519 S_00B42C_USER_SGPR(GFX9_TCS_NUM_USER_SGPR
) |
520 S_00B42C_USER_SGPR_MSB(GFX9_TCS_NUM_USER_SGPR
>> 5) |
521 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
523 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
524 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, va
>> 40);
526 shader
->config
.rsrc2
=
527 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR
) |
528 S_00B42C_OC_LDS_EN(1) |
529 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
532 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
533 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
534 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
535 S_00B428_DX10_CLAMP(1) |
536 S_00B428_FLOAT_MODE(shader
->config
.float_mode
) |
537 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt
));
539 if (sscreen
->info
.chip_class
<= VI
) {
540 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
541 shader
->config
.rsrc2
);
545 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
547 struct si_pm4_state
*pm4
;
548 unsigned num_user_sgprs
;
549 unsigned vgpr_comp_cnt
;
553 assert(sscreen
->info
.chip_class
<= VI
);
555 pm4
= si_get_shader_pm4_state(shader
);
559 va
= shader
->bo
->gpu_address
;
560 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
562 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
563 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
564 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
565 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
566 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
567 vgpr_comp_cnt
= shader
->selector
->info
.uses_primid
? 3 : 2;
568 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
570 unreachable("invalid shader selector type");
572 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
574 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
575 shader
->selector
->esgs_itemsize
/ 4);
576 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
577 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
578 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
579 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
580 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
581 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
582 S_00B328_DX10_CLAMP(1) |
583 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
584 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
585 S_00B32C_USER_SGPR(num_user_sgprs
) |
586 S_00B32C_OC_LDS_EN(oc_lds_en
) |
587 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
589 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
590 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
592 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
595 struct gfx9_gs_info
{
596 unsigned es_verts_per_subgroup
;
597 unsigned gs_prims_per_subgroup
;
598 unsigned gs_inst_prims_in_subgroup
;
599 unsigned max_prims_per_subgroup
;
603 static void gfx9_get_gs_info(struct si_shader_selector
*es
,
604 struct si_shader_selector
*gs
,
605 struct gfx9_gs_info
*out
)
607 unsigned gs_num_invocations
= MAX2(gs
->gs_num_invocations
, 1);
608 unsigned input_prim
= gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
609 bool uses_adjacency
= input_prim
>= PIPE_PRIM_LINES_ADJACENCY
&&
610 input_prim
<= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
;
612 /* All these are in dwords: */
613 /* We can't allow using the whole LDS, because GS waves compete with
614 * other shader stages for LDS space. */
615 const unsigned max_lds_size
= 8 * 1024;
616 const unsigned esgs_itemsize
= es
->esgs_itemsize
/ 4;
617 unsigned esgs_lds_size
;
619 /* All these are per subgroup: */
620 const unsigned max_out_prims
= 32 * 1024;
621 const unsigned max_es_verts
= 255;
622 const unsigned ideal_gs_prims
= 64;
623 unsigned max_gs_prims
, gs_prims
;
624 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
626 assert(gs_num_invocations
<= 32); /* GL maximum */
628 if (uses_adjacency
|| gs_num_invocations
> 1)
629 max_gs_prims
= 127 / gs_num_invocations
;
633 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
634 * Make sure we don't go over the maximum value.
636 if (gs
->gs_max_out_vertices
> 0) {
637 max_gs_prims
= MIN2(max_gs_prims
,
639 (gs
->gs_max_out_vertices
* gs_num_invocations
));
641 assert(max_gs_prims
> 0);
643 /* If the primitive has adjacency, halve the number of vertices
644 * that will be reused in multiple primitives.
646 min_es_verts
= gs
->gs_input_verts_per_prim
/ (uses_adjacency
? 2 : 1);
648 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
649 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
651 /* Compute ESGS LDS size based on the worst case number of ES vertices
652 * needed to create the target number of GS prims per subgroup.
654 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
656 /* If total LDS usage is too big, refactor partitions based on ratio
657 * of ESGS item sizes.
659 if (esgs_lds_size
> max_lds_size
) {
660 /* Our target GS Prims Per Subgroup was too large. Calculate
661 * the maximum number of GS Prims Per Subgroup that will fit
662 * into LDS, capped by the maximum that the hardware can support.
664 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
666 assert(gs_prims
> 0);
667 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
670 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
671 assert(esgs_lds_size
<= max_lds_size
);
674 /* Now calculate remaining ESGS information. */
676 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
678 es_verts
= max_es_verts
;
680 /* Vertices for adjacency primitives are not always reused, so restore
681 * it for ES_VERTS_PER_SUBGRP.
683 min_es_verts
= gs
->gs_input_verts_per_prim
;
685 /* For normal primitives, the VGT only checks if they are past the ES
686 * verts per subgroup after allocating a full GS primitive and if they
687 * are, kick off a new subgroup. But if those additional ES verts are
688 * unique (e.g. not reused) we need to make sure there is enough LDS
689 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
691 es_verts
-= min_es_verts
- 1;
693 out
->es_verts_per_subgroup
= es_verts
;
694 out
->gs_prims_per_subgroup
= gs_prims
;
695 out
->gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
696 out
->max_prims_per_subgroup
= out
->gs_inst_prims_in_subgroup
*
697 gs
->gs_max_out_vertices
;
698 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
700 assert(out
->max_prims_per_subgroup
<= max_out_prims
);
703 static void si_shader_gs(struct si_screen
*sscreen
, struct si_shader
*shader
)
705 struct si_shader_selector
*sel
= shader
->selector
;
706 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
707 unsigned gs_num_invocations
= sel
->gs_num_invocations
;
708 struct si_pm4_state
*pm4
;
710 unsigned max_stream
= sel
->max_gs_stream
;
713 pm4
= si_get_shader_pm4_state(shader
);
717 offset
= num_components
[0] * sel
->gs_max_out_vertices
;
718 si_pm4_set_reg(pm4
, R_028A60_VGT_GSVS_RING_OFFSET_1
, offset
);
720 offset
+= num_components
[1] * sel
->gs_max_out_vertices
;
721 si_pm4_set_reg(pm4
, R_028A64_VGT_GSVS_RING_OFFSET_2
, offset
);
723 offset
+= num_components
[2] * sel
->gs_max_out_vertices
;
724 si_pm4_set_reg(pm4
, R_028A68_VGT_GSVS_RING_OFFSET_3
, offset
);
726 offset
+= num_components
[3] * sel
->gs_max_out_vertices
;
727 si_pm4_set_reg(pm4
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
729 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
730 assert(offset
< (1 << 15));
732 si_pm4_set_reg(pm4
, R_028B38_VGT_GS_MAX_VERT_OUT
, sel
->gs_max_out_vertices
);
734 si_pm4_set_reg(pm4
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, num_components
[0]);
735 si_pm4_set_reg(pm4
, R_028B60_VGT_GS_VERT_ITEMSIZE_1
, (max_stream
>= 1) ? num_components
[1] : 0);
736 si_pm4_set_reg(pm4
, R_028B64_VGT_GS_VERT_ITEMSIZE_2
, (max_stream
>= 2) ? num_components
[2] : 0);
737 si_pm4_set_reg(pm4
, R_028B68_VGT_GS_VERT_ITEMSIZE_3
, (max_stream
>= 3) ? num_components
[3] : 0);
739 si_pm4_set_reg(pm4
, R_028B90_VGT_GS_INSTANCE_CNT
,
740 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
741 S_028B90_ENABLE(gs_num_invocations
> 0));
743 va
= shader
->bo
->gpu_address
;
744 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
746 if (sscreen
->info
.chip_class
>= GFX9
) {
747 unsigned input_prim
= sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
748 unsigned es_type
= shader
->key
.part
.gs
.es
->type
;
749 unsigned es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
750 struct gfx9_gs_info gs_info
;
752 if (es_type
== PIPE_SHADER_VERTEX
)
753 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
754 es_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
755 else if (es_type
== PIPE_SHADER_TESS_EVAL
)
756 es_vgpr_comp_cnt
= shader
->key
.part
.gs
.es
->info
.uses_primid
? 3 : 2;
758 unreachable("invalid shader selector type");
760 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
761 * VGPR[0:4] are always loaded.
763 if (sel
->info
.uses_invocationid
)
764 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
765 else if (sel
->info
.uses_primid
)
766 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
767 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
768 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
770 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
772 gfx9_get_gs_info(shader
->key
.part
.gs
.es
, sel
, &gs_info
);
774 si_pm4_set_reg(pm4
, R_00B210_SPI_SHADER_PGM_LO_ES
, va
>> 8);
775 si_pm4_set_reg(pm4
, R_00B214_SPI_SHADER_PGM_HI_ES
, va
>> 40);
777 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
778 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
779 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
780 S_00B228_DX10_CLAMP(1) |
781 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
782 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
));
783 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
784 S_00B22C_USER_SGPR(GFX9_GS_NUM_USER_SGPR
) |
785 S_00B22C_USER_SGPR_MSB(GFX9_GS_NUM_USER_SGPR
>> 5) |
786 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
787 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
788 S_00B22C_LDS_SIZE(gs_info
.lds_size
) |
789 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
791 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
792 S_028A44_ES_VERTS_PER_SUBGRP(gs_info
.es_verts_per_subgroup
) |
793 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info
.gs_prims_per_subgroup
) |
794 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info
.gs_inst_prims_in_subgroup
));
795 si_pm4_set_reg(pm4
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
796 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info
.max_prims_per_subgroup
));
797 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
798 shader
->key
.part
.gs
.es
->esgs_itemsize
/ 4);
800 if (es_type
== PIPE_SHADER_TESS_EVAL
)
801 si_set_tesseval_regs(sscreen
, shader
->key
.part
.gs
.es
, pm4
);
803 polaris_set_vgt_vertex_reuse(sscreen
, shader
->key
.part
.gs
.es
,
806 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
807 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, va
>> 40);
809 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
810 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
811 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
812 S_00B228_DX10_CLAMP(1) |
813 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
814 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
815 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR
) |
816 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
821 * Compute the state for \p shader, which will run as a vertex shader on the
824 * If \p gs is non-NULL, it points to the geometry shader for which this shader
825 * is the copy shader.
827 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
828 struct si_shader_selector
*gs
)
830 const struct tgsi_shader_info
*info
= &shader
->selector
->info
;
831 struct si_pm4_state
*pm4
;
832 unsigned num_user_sgprs
;
833 unsigned nparams
, vgpr_comp_cnt
;
836 unsigned window_space
=
837 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
838 bool enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| info
->uses_primid
;
840 pm4
= si_get_shader_pm4_state(shader
);
844 /* We always write VGT_GS_MODE in the VS state, because every switch
845 * between different shader pipelines involving a different GS or no
846 * GS at all involves a switch of the VS (different GS use different
847 * copy shaders). On the other hand, when the API switches from a GS to
848 * no GS and then back to the same GS used originally, the GS state is
852 unsigned mode
= V_028A40_GS_OFF
;
854 /* PrimID needs GS scenario A. */
856 mode
= V_028A40_GS_SCENARIO_A
;
858 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, S_028A40_MODE(mode
));
859 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, enable_prim_id
);
861 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
,
862 ac_vgt_gs_mode(gs
->gs_max_out_vertices
,
863 sscreen
->info
.chip_class
));
864 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
867 if (sscreen
->info
.chip_class
<= VI
) {
868 /* Reuse needs to be set off if we write oViewport. */
869 si_pm4_set_reg(pm4
, R_028AB4_VGT_REUSE_OFF
,
870 S_028AB4_REUSE_OFF(info
->writes_viewport_index
));
873 va
= shader
->bo
->gpu_address
;
874 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
877 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
878 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
879 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
880 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
881 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
882 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
884 vgpr_comp_cnt
= enable_prim_id
? 2 : (shader
->info
.uses_instanceid
? 1 : 0);
886 if (info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
]) {
887 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
888 info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
890 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
892 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
893 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
894 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
896 unreachable("invalid shader selector type");
898 /* VS is required to export at least one param. */
899 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
900 si_pm4_set_reg(pm4
, R_0286C4_SPI_VS_OUT_CONFIG
,
901 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
903 si_pm4_set_reg(pm4
, R_02870C_SPI_SHADER_POS_FORMAT
,
904 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
905 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
906 V_02870C_SPI_SHADER_4COMP
:
907 V_02870C_SPI_SHADER_NONE
) |
908 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
909 V_02870C_SPI_SHADER_4COMP
:
910 V_02870C_SPI_SHADER_NONE
) |
911 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
912 V_02870C_SPI_SHADER_4COMP
:
913 V_02870C_SPI_SHADER_NONE
));
915 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
917 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
918 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, va
>> 40);
919 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
920 S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
921 S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
922 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
923 S_00B128_DX10_CLAMP(1) |
924 S_00B128_FLOAT_MODE(shader
->config
.float_mode
));
925 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
926 S_00B12C_USER_SGPR(num_user_sgprs
) |
927 S_00B12C_OC_LDS_EN(oc_lds_en
) |
928 S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
929 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
930 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
931 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
932 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
) |
933 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
935 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
936 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
938 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
939 S_028818_VTX_W0_FMT(1) |
940 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
941 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
942 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
944 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
945 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
947 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
950 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
952 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
953 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
954 !!(info
->colors_read
& 0xf0);
955 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
956 (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
958 assert(num_interp
<= 32);
959 return MIN2(num_interp
, 32);
962 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
964 unsigned value
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
965 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
967 /* If the i-th target format is set, all previous target formats must
968 * be non-zero to avoid hangs.
970 for (i
= 0; i
< num_targets
; i
++)
971 if (!(value
& (0xf << (i
* 4))))
972 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
977 static void si_shader_ps(struct si_shader
*shader
)
979 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
980 struct si_pm4_state
*pm4
;
981 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
982 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
984 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
986 /* we need to enable at least one of them, otherwise we hang the GPU */
987 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
988 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
989 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
990 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
991 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
992 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
993 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
994 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
995 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
996 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
997 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
998 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
999 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1000 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
1002 /* Validate interpolation optimization flags (read as implications). */
1003 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1004 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1005 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1006 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1007 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1008 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1009 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
1010 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
1011 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1012 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
1013 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
1014 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1015 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
1016 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1017 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1018 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
1019 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1020 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1022 /* Validate cases when the optimizations are off (read as implications). */
1023 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1024 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1025 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
1026 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1027 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1028 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
1030 pm4
= si_get_shader_pm4_state(shader
);
1034 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1036 * 0 -> Position = pixel center
1037 * 1 -> Position = pixel centroid
1038 * 2 -> Position = at sample position
1040 * From GLSL 4.5 specification, section 7.1:
1041 * "The variable gl_FragCoord is available as an input variable from
1042 * within fragment shaders and it holds the window relative coordinates
1043 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1044 * value can be for any location within the pixel, or one of the
1045 * fragment samples. The use of centroid does not further restrict
1046 * this value to be inside the current primitive."
1048 * Meaning that centroid has no effect and we can return anything within
1049 * the pixel. Thus, return the value at sample position, because that's
1050 * the most accurate one shaders can get.
1052 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1054 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
1055 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
1056 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
1058 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
1059 cb_shader_mask
= ac_get_cb_shader_mask(spi_shader_col_format
);
1061 /* Ensure that some export memory is always allocated, for two reasons:
1063 * 1) Correctness: The hardware ignores the EXEC mask if no export
1064 * memory is allocated, so KILL and alpha test do not work correctly
1066 * 2) Performance: Every shader needs at least a NULL export, even when
1067 * it writes no color/depth output. The NULL export instruction
1068 * stalls without this setting.
1070 * Don't add this to CB_SHADER_MASK.
1072 if (!spi_shader_col_format
&&
1073 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
1074 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
1076 si_pm4_set_reg(pm4
, R_0286CC_SPI_PS_INPUT_ENA
, input_ena
);
1077 si_pm4_set_reg(pm4
, R_0286D0_SPI_PS_INPUT_ADDR
,
1078 shader
->config
.spi_ps_input_addr
);
1080 /* Set interpolation controls. */
1081 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
));
1083 /* Set registers. */
1084 si_pm4_set_reg(pm4
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
1085 si_pm4_set_reg(pm4
, R_0286D8_SPI_PS_IN_CONTROL
, spi_ps_in_control
);
1087 si_pm4_set_reg(pm4
, R_028710_SPI_SHADER_Z_FORMAT
,
1088 ac_get_spi_shader_z_format(info
->writes_z
,
1089 info
->writes_stencil
,
1090 info
->writes_samplemask
));
1092 si_pm4_set_reg(pm4
, R_028714_SPI_SHADER_COL_FORMAT
, spi_shader_col_format
);
1093 si_pm4_set_reg(pm4
, R_02823C_CB_SHADER_MASK
, cb_shader_mask
);
1095 va
= shader
->bo
->gpu_address
;
1096 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1097 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
1098 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, va
>> 40);
1100 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
,
1101 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1102 S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
1103 S_00B028_DX10_CLAMP(1) |
1104 S_00B028_FLOAT_MODE(shader
->config
.float_mode
));
1105 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
1106 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
1107 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
1108 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1111 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
1112 struct si_shader
*shader
)
1114 switch (shader
->selector
->type
) {
1115 case PIPE_SHADER_VERTEX
:
1116 if (shader
->key
.as_ls
)
1117 si_shader_ls(sscreen
, shader
);
1118 else if (shader
->key
.as_es
)
1119 si_shader_es(sscreen
, shader
);
1121 si_shader_vs(sscreen
, shader
, NULL
);
1123 case PIPE_SHADER_TESS_CTRL
:
1124 si_shader_hs(sscreen
, shader
);
1126 case PIPE_SHADER_TESS_EVAL
:
1127 if (shader
->key
.as_es
)
1128 si_shader_es(sscreen
, shader
);
1130 si_shader_vs(sscreen
, shader
, NULL
);
1132 case PIPE_SHADER_GEOMETRY
:
1133 si_shader_gs(sscreen
, shader
);
1135 case PIPE_SHADER_FRAGMENT
:
1136 si_shader_ps(shader
);
1143 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
1145 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1146 if (sctx
->queued
.named
.dsa
)
1147 return sctx
->queued
.named
.dsa
->alpha_func
;
1149 return PIPE_FUNC_ALWAYS
;
1152 static void si_shader_selector_key_vs(struct si_context
*sctx
,
1153 struct si_shader_selector
*vs
,
1154 struct si_shader_key
*key
,
1155 struct si_vs_prolog_bits
*prolog_key
)
1157 if (!sctx
->vertex_elements
)
1160 prolog_key
->instance_divisor_is_one
=
1161 sctx
->vertex_elements
->instance_divisor_is_one
;
1162 prolog_key
->instance_divisor_is_fetched
=
1163 sctx
->vertex_elements
->instance_divisor_is_fetched
;
1165 /* Prefer a monolithic shader to allow scheduling divisions around
1167 if (prolog_key
->instance_divisor_is_fetched
)
1168 key
->opt
.prefer_mono
= 1;
1170 unsigned count
= MIN2(vs
->info
.num_inputs
,
1171 sctx
->vertex_elements
->count
);
1172 memcpy(key
->mono
.vs_fix_fetch
, sctx
->vertex_elements
->fix_fetch
, count
);
1175 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
,
1176 struct si_shader_selector
*vs
,
1177 struct si_shader_key
*key
)
1179 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1181 key
->opt
.clip_disable
=
1182 sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
1183 (vs
->info
.clipdist_writemask
||
1184 vs
->info
.writes_clipvertex
) &&
1185 !vs
->info
.culldist_writemask
;
1187 /* Find out if PS is disabled. */
1188 bool ps_disabled
= true;
1190 const struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1191 bool alpha_to_coverage
= blend
&& blend
->alpha_to_coverage
;
1192 bool ps_modifies_zs
= ps
->info
.uses_kill
||
1193 ps
->info
.writes_z
||
1194 ps
->info
.writes_stencil
||
1195 ps
->info
.writes_samplemask
||
1196 alpha_to_coverage
||
1197 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
1199 unsigned ps_colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
&
1200 sctx
->queued
.named
.blend
->cb_target_mask
;
1201 if (!ps
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
])
1202 ps_colormask
&= ps
->colors_written_4bit
;
1204 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
1207 !ps
->info
.writes_memory
);
1210 /* Find out which VS outputs aren't used by the PS. */
1211 uint64_t outputs_written
= vs
->outputs_written
;
1212 uint64_t inputs_read
= 0;
1214 /* ignore POSITION, PSIZE */
1215 outputs_written
&= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION
, 0) |
1216 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE
, 0))));
1219 inputs_read
= ps
->inputs_read
;
1222 uint64_t linked
= outputs_written
& inputs_read
;
1224 key
->opt
.kill_outputs
= ~linked
& outputs_written
;
1227 /* Compute the key for the hw shader variant */
1228 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
1229 struct si_shader_selector
*sel
,
1230 struct si_shader_key
*key
)
1232 struct si_context
*sctx
= (struct si_context
*)ctx
;
1234 memset(key
, 0, sizeof(*key
));
1236 switch (sel
->type
) {
1237 case PIPE_SHADER_VERTEX
:
1238 si_shader_selector_key_vs(sctx
, sel
, key
, &key
->part
.vs
.prolog
);
1240 if (sctx
->tes_shader
.cso
)
1242 else if (sctx
->gs_shader
.cso
)
1245 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1247 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1248 key
->mono
.u
.vs_export_prim_id
= 1;
1251 case PIPE_SHADER_TESS_CTRL
:
1252 if (sctx
->b
.chip_class
>= GFX9
) {
1253 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1254 key
, &key
->part
.tcs
.ls_prolog
);
1255 key
->part
.tcs
.ls
= sctx
->vs_shader
.cso
;
1257 /* When the LS VGPR fix is needed, monolithic shaders
1259 * - avoid initializing EXEC in both the LS prolog
1260 * and the LS main part when !vs_needs_prolog
1261 * - remove the fixup for unused input VGPRs
1263 key
->part
.tcs
.ls_prolog
.ls_vgpr_fix
= sctx
->ls_vgpr_fix
;
1265 /* The LS output / HS input layout can be communicated
1266 * directly instead of via user SGPRs for merged LS-HS.
1267 * The LS VGPR fix prefers this too.
1269 key
->opt
.prefer_mono
= 1;
1272 key
->part
.tcs
.epilog
.prim_mode
=
1273 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1274 key
->part
.tcs
.epilog
.invoc0_tess_factors_are_def
=
1275 sel
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1276 key
->part
.tcs
.epilog
.tes_reads_tess_factors
=
1277 sctx
->tes_shader
.cso
->info
.reads_tess_factors
;
1279 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
1280 key
->mono
.u
.ff_tcs_inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
1282 case PIPE_SHADER_TESS_EVAL
:
1283 if (sctx
->gs_shader
.cso
)
1286 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1288 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1289 key
->mono
.u
.vs_export_prim_id
= 1;
1292 case PIPE_SHADER_GEOMETRY
:
1293 if (sctx
->b
.chip_class
>= GFX9
) {
1294 if (sctx
->tes_shader
.cso
) {
1295 key
->part
.gs
.es
= sctx
->tes_shader
.cso
;
1297 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1298 key
, &key
->part
.gs
.vs_prolog
);
1299 key
->part
.gs
.es
= sctx
->vs_shader
.cso
;
1302 /* Merged ES-GS can have unbalanced wave usage.
1304 * ES threads are per-vertex, while GS threads are
1305 * per-primitive. So without any amplification, there
1306 * are fewer GS threads than ES threads, which can result
1307 * in empty (no-op) GS waves. With too much amplification,
1308 * there are more GS threads than ES threads, which
1309 * can result in empty (no-op) ES waves.
1311 * Non-monolithic shaders are implemented by setting EXEC
1312 * at the beginning of shader parts, and don't jump to
1313 * the end if EXEC is 0.
1315 * Monolithic shaders use conditional blocks, so they can
1316 * jump and skip empty waves of ES or GS. So set this to
1317 * always use optimized variants, which are monolithic.
1319 key
->opt
.prefer_mono
= 1;
1321 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
1323 case PIPE_SHADER_FRAGMENT
: {
1324 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1325 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1327 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
1328 sel
->info
.colors_written
== 0x1)
1329 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
1332 /* Select the shader color format based on whether
1333 * blending or alpha are needed.
1335 key
->part
.ps
.epilog
.spi_shader_col_format
=
1336 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1337 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
1338 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1339 sctx
->framebuffer
.spi_shader_col_format_blend
) |
1340 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1341 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
1342 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1343 sctx
->framebuffer
.spi_shader_col_format
);
1344 key
->part
.ps
.epilog
.spi_shader_col_format
&= blend
->cb_target_enabled_4bit
;
1346 /* The output for dual source blending should have
1347 * the same format as the first output.
1349 if (blend
->dual_src_blend
)
1350 key
->part
.ps
.epilog
.spi_shader_col_format
|=
1351 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
1353 key
->part
.ps
.epilog
.spi_shader_col_format
= sctx
->framebuffer
.spi_shader_col_format
;
1355 /* If alpha-to-coverage is enabled, we have to export alpha
1356 * even if there is no color buffer.
1358 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) &&
1359 blend
&& blend
->alpha_to_coverage
)
1360 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
1362 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1363 * to the range supported by the type if a channel has less
1364 * than 16 bits and the export format is 16_ABGR.
1366 if (sctx
->b
.chip_class
<= CIK
&& sctx
->b
.family
!= CHIP_HAWAII
) {
1367 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
1368 key
->part
.ps
.epilog
.color_is_int10
= sctx
->framebuffer
.color_is_int10
;
1371 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1372 if (!key
->part
.ps
.epilog
.last_cbuf
) {
1373 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
1374 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
1375 key
->part
.ps
.epilog
.color_is_int10
&= sel
->info
.colors_written
;
1379 bool is_poly
= (sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES
&&
1380 sctx
->current_rast_prim
<= PIPE_PRIM_POLYGON
) ||
1381 sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES_ADJACENCY
;
1382 bool is_line
= !is_poly
&& sctx
->current_rast_prim
!= PIPE_PRIM_POINTS
;
1384 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
1385 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
1387 if (sctx
->queued
.named
.blend
) {
1388 key
->part
.ps
.epilog
.alpha_to_one
= sctx
->queued
.named
.blend
->alpha_to_one
&&
1389 rs
->multisample_enable
;
1392 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
1393 key
->part
.ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
1394 (is_line
&& rs
->line_smooth
)) &&
1395 sctx
->framebuffer
.nr_samples
<= 1;
1396 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
1398 if (sctx
->ps_iter_samples
> 1 &&
1399 sel
->info
.reads_samplemask
) {
1400 key
->part
.ps
.prolog
.samplemask_log_ps_iter
=
1401 util_logbase2(util_next_power_of_two(sctx
->ps_iter_samples
));
1404 if (rs
->force_persample_interp
&&
1405 rs
->multisample_enable
&&
1406 sctx
->framebuffer
.nr_samples
> 1 &&
1407 sctx
->ps_iter_samples
> 1) {
1408 key
->part
.ps
.prolog
.force_persp_sample_interp
=
1409 sel
->info
.uses_persp_center
||
1410 sel
->info
.uses_persp_centroid
;
1412 key
->part
.ps
.prolog
.force_linear_sample_interp
=
1413 sel
->info
.uses_linear_center
||
1414 sel
->info
.uses_linear_centroid
;
1415 } else if (rs
->multisample_enable
&&
1416 sctx
->framebuffer
.nr_samples
> 1) {
1417 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
1418 sel
->info
.uses_persp_center
&&
1419 sel
->info
.uses_persp_centroid
;
1420 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
1421 sel
->info
.uses_linear_center
&&
1422 sel
->info
.uses_linear_centroid
;
1424 /* Make sure SPI doesn't compute more than 1 pair
1425 * of (i,j), which is the optimization here. */
1426 key
->part
.ps
.prolog
.force_persp_center_interp
=
1427 sel
->info
.uses_persp_center
+
1428 sel
->info
.uses_persp_centroid
+
1429 sel
->info
.uses_persp_sample
> 1;
1431 key
->part
.ps
.prolog
.force_linear_center_interp
=
1432 sel
->info
.uses_linear_center
+
1433 sel
->info
.uses_linear_centroid
+
1434 sel
->info
.uses_linear_sample
> 1;
1436 if (sel
->info
.opcode_count
[TGSI_OPCODE_INTERP_SAMPLE
])
1437 key
->mono
.u
.ps
.interpolate_at_sample_force_center
= 1;
1441 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
1448 if (unlikely(sctx
->screen
->debug_flags
& DBG(NO_OPT_VARIANT
)))
1449 memset(&key
->opt
, 0, sizeof(key
->opt
));
1452 static void si_build_shader_variant(struct si_shader
*shader
,
1456 struct si_shader_selector
*sel
= shader
->selector
;
1457 struct si_screen
*sscreen
= sel
->screen
;
1458 LLVMTargetMachineRef tm
;
1459 struct pipe_debug_callback
*debug
= &shader
->compiler_ctx_state
.debug
;
1462 if (thread_index
>= 0) {
1464 assert(thread_index
< ARRAY_SIZE(sscreen
->tm_low_priority
));
1465 tm
= sscreen
->tm_low_priority
[thread_index
];
1467 assert(thread_index
< ARRAY_SIZE(sscreen
->tm
));
1468 tm
= sscreen
->tm
[thread_index
];
1473 assert(!low_priority
);
1474 tm
= shader
->compiler_ctx_state
.tm
;
1477 r
= si_shader_create(sscreen
, tm
, shader
, debug
);
1479 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1481 shader
->compilation_failed
= true;
1485 if (shader
->compiler_ctx_state
.is_debug_context
) {
1486 FILE *f
= open_memstream(&shader
->shader_log
,
1487 &shader
->shader_log_size
);
1489 si_shader_dump(sscreen
, shader
, NULL
, sel
->type
, f
, false);
1494 si_shader_init_pm4_state(sscreen
, shader
);
1497 static void si_build_shader_variant_low_priority(void *job
, int thread_index
)
1499 struct si_shader
*shader
= (struct si_shader
*)job
;
1501 assert(thread_index
>= 0);
1503 si_build_shader_variant(shader
, thread_index
, true);
1506 static const struct si_shader_key zeroed
;
1508 static bool si_check_missing_main_part(struct si_screen
*sscreen
,
1509 struct si_shader_selector
*sel
,
1510 struct si_compiler_ctx_state
*compiler_state
,
1511 struct si_shader_key
*key
)
1513 struct si_shader
**mainp
= si_get_main_shader_part(sel
, key
);
1516 struct si_shader
*main_part
= CALLOC_STRUCT(si_shader
);
1521 /* We can leave the fence as permanently signaled because the
1522 * main part becomes visible globally only after it has been
1524 util_queue_fence_init(&main_part
->ready
);
1526 main_part
->selector
= sel
;
1527 main_part
->key
.as_es
= key
->as_es
;
1528 main_part
->key
.as_ls
= key
->as_ls
;
1530 if (si_compile_tgsi_shader(sscreen
, compiler_state
->tm
,
1532 &compiler_state
->debug
) != 0) {
1541 /* Select the hw shader variant depending on the current state. */
1542 static int si_shader_select_with_key(struct si_screen
*sscreen
,
1543 struct si_shader_ctx_state
*state
,
1544 struct si_compiler_ctx_state
*compiler_state
,
1545 struct si_shader_key
*key
,
1548 struct si_shader_selector
*sel
= state
->cso
;
1549 struct si_shader_selector
*previous_stage_sel
= NULL
;
1550 struct si_shader
*current
= state
->current
;
1551 struct si_shader
*iter
, *shader
= NULL
;
1554 /* Check if we don't need to change anything.
1555 * This path is also used for most shaders that don't need multiple
1556 * variants, it will cost just a computation of the key and this
1558 if (likely(current
&&
1559 memcmp(¤t
->key
, key
, sizeof(*key
)) == 0)) {
1560 if (unlikely(!util_queue_fence_is_signalled(¤t
->ready
))) {
1561 if (current
->is_optimized
) {
1562 memset(&key
->opt
, 0, sizeof(key
->opt
));
1563 goto current_not_ready
;
1566 util_queue_fence_wait(¤t
->ready
);
1569 return current
->compilation_failed
? -1 : 0;
1573 /* This must be done before the mutex is locked, because async GS
1574 * compilation calls this function too, and therefore must enter
1577 * Only wait if we are in a draw call. Don't wait if we are
1578 * in a compiler thread.
1580 if (thread_index
< 0)
1581 util_queue_fence_wait(&sel
->ready
);
1583 mtx_lock(&sel
->mutex
);
1585 /* Find the shader variant. */
1586 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
1587 /* Don't check the "current" shader. We checked it above. */
1588 if (current
!= iter
&&
1589 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
1590 mtx_unlock(&sel
->mutex
);
1592 if (unlikely(!util_queue_fence_is_signalled(&iter
->ready
))) {
1593 /* If it's an optimized shader and its compilation has
1594 * been started but isn't done, use the unoptimized
1595 * shader so as not to cause a stall due to compilation.
1597 if (iter
->is_optimized
) {
1598 memset(&key
->opt
, 0, sizeof(key
->opt
));
1602 util_queue_fence_wait(&iter
->ready
);
1605 if (iter
->compilation_failed
) {
1606 return -1; /* skip the draw call */
1609 state
->current
= iter
;
1614 /* Build a new shader. */
1615 shader
= CALLOC_STRUCT(si_shader
);
1617 mtx_unlock(&sel
->mutex
);
1621 util_queue_fence_init(&shader
->ready
);
1623 shader
->selector
= sel
;
1625 shader
->compiler_ctx_state
= *compiler_state
;
1627 /* If this is a merged shader, get the first shader's selector. */
1628 if (sscreen
->info
.chip_class
>= GFX9
) {
1629 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
1630 previous_stage_sel
= key
->part
.tcs
.ls
;
1631 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
1632 previous_stage_sel
= key
->part
.gs
.es
;
1634 /* We need to wait for the previous shader. */
1635 if (previous_stage_sel
&& thread_index
< 0)
1636 util_queue_fence_wait(&previous_stage_sel
->ready
);
1639 /* Compile the main shader part if it doesn't exist. This can happen
1640 * if the initial guess was wrong. */
1641 bool is_pure_monolithic
=
1642 sscreen
->use_monolithic_shaders
||
1643 memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
1645 if (!is_pure_monolithic
) {
1648 /* Make sure the main shader part is present. This is needed
1649 * for shaders that can be compiled as VS, LS, or ES, and only
1650 * one of them is compiled at creation.
1652 * For merged shaders, check that the starting shader's main
1655 if (previous_stage_sel
) {
1656 struct si_shader_key shader1_key
= zeroed
;
1658 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
1659 shader1_key
.as_ls
= 1;
1660 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
1661 shader1_key
.as_es
= 1;
1665 mtx_lock(&previous_stage_sel
->mutex
);
1666 ok
= si_check_missing_main_part(sscreen
,
1668 compiler_state
, &shader1_key
);
1669 mtx_unlock(&previous_stage_sel
->mutex
);
1671 ok
= si_check_missing_main_part(sscreen
, sel
,
1672 compiler_state
, key
);
1676 mtx_unlock(&sel
->mutex
);
1677 return -ENOMEM
; /* skip the draw call */
1681 /* Keep the reference to the 1st shader of merged shaders, so that
1682 * Gallium can't destroy it before we destroy the 2nd shader.
1684 * Set sctx = NULL, because it's unused if we're not releasing
1685 * the shader, and we don't have any sctx here.
1687 si_shader_selector_reference(NULL
, &shader
->previous_stage_sel
,
1688 previous_stage_sel
);
1690 /* Monolithic-only shaders don't make a distinction between optimized
1691 * and unoptimized. */
1692 shader
->is_monolithic
=
1693 is_pure_monolithic
||
1694 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1696 shader
->is_optimized
=
1697 !is_pure_monolithic
&&
1698 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1700 /* If it's an optimized shader, compile it asynchronously. */
1701 if (shader
->is_optimized
&&
1702 !is_pure_monolithic
&&
1704 /* Compile it asynchronously. */
1705 util_queue_add_job(&sscreen
->shader_compiler_queue_low_priority
,
1706 shader
, &shader
->ready
,
1707 si_build_shader_variant_low_priority
, NULL
);
1709 /* Add only after the ready fence was reset, to guard against a
1710 * race with si_bind_XX_shader. */
1711 if (!sel
->last_variant
) {
1712 sel
->first_variant
= shader
;
1713 sel
->last_variant
= shader
;
1715 sel
->last_variant
->next_variant
= shader
;
1716 sel
->last_variant
= shader
;
1719 /* Use the default (unoptimized) shader for now. */
1720 memset(&key
->opt
, 0, sizeof(key
->opt
));
1721 mtx_unlock(&sel
->mutex
);
1725 /* Reset the fence before adding to the variant list. */
1726 util_queue_fence_reset(&shader
->ready
);
1728 if (!sel
->last_variant
) {
1729 sel
->first_variant
= shader
;
1730 sel
->last_variant
= shader
;
1732 sel
->last_variant
->next_variant
= shader
;
1733 sel
->last_variant
= shader
;
1736 mtx_unlock(&sel
->mutex
);
1738 assert(!shader
->is_optimized
);
1739 si_build_shader_variant(shader
, thread_index
, false);
1741 util_queue_fence_signal(&shader
->ready
);
1743 if (!shader
->compilation_failed
)
1744 state
->current
= shader
;
1746 return shader
->compilation_failed
? -1 : 0;
1749 static int si_shader_select(struct pipe_context
*ctx
,
1750 struct si_shader_ctx_state
*state
,
1751 struct si_compiler_ctx_state
*compiler_state
)
1753 struct si_context
*sctx
= (struct si_context
*)ctx
;
1754 struct si_shader_key key
;
1756 si_shader_selector_key(ctx
, state
->cso
, &key
);
1757 return si_shader_select_with_key(sctx
->screen
, state
, compiler_state
,
1761 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
1763 struct si_shader_key
*key
)
1765 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
1767 switch (info
->processor
) {
1768 case PIPE_SHADER_VERTEX
:
1769 switch (next_shader
) {
1770 case PIPE_SHADER_GEOMETRY
:
1773 case PIPE_SHADER_TESS_CTRL
:
1774 case PIPE_SHADER_TESS_EVAL
:
1778 /* If POSITION isn't written, it can only be a HW VS
1779 * if streamout is used. If streamout isn't used,
1780 * assume that it's a HW LS. (the next shader is TCS)
1781 * This heuristic is needed for separate shader objects.
1783 if (!info
->writes_position
&& !streamout
)
1788 case PIPE_SHADER_TESS_EVAL
:
1789 if (next_shader
== PIPE_SHADER_GEOMETRY
||
1790 !info
->writes_position
)
1797 * Compile the main shader part or the monolithic shader as part of
1798 * si_shader_selector initialization. Since it can be done asynchronously,
1799 * there is no way to report compile failures to applications.
1801 static void si_init_shader_selector_async(void *job
, int thread_index
)
1803 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
1804 struct si_screen
*sscreen
= sel
->screen
;
1805 LLVMTargetMachineRef tm
;
1806 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
1808 assert(!debug
->debug_message
|| debug
->async
);
1809 assert(thread_index
>= 0);
1810 assert(thread_index
< ARRAY_SIZE(sscreen
->tm
));
1811 tm
= sscreen
->tm
[thread_index
];
1813 /* Compile the main shader part for use with a prolog and/or epilog.
1814 * If this fails, the driver will try to compile a monolithic shader
1817 if (!sscreen
->use_monolithic_shaders
) {
1818 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
1819 void *ir_binary
= NULL
;
1822 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
1826 /* We can leave the fence signaled because use of the default
1827 * main part is guarded by the selector's ready fence. */
1828 util_queue_fence_init(&shader
->ready
);
1830 shader
->selector
= sel
;
1831 si_parse_next_shader_property(&sel
->info
,
1832 sel
->so
.num_outputs
!= 0,
1835 if (sel
->tokens
|| sel
->nir
)
1836 ir_binary
= si_get_ir_binary(sel
);
1838 /* Try to load the shader from the shader cache. */
1839 mtx_lock(&sscreen
->shader_cache_mutex
);
1842 si_shader_cache_load_shader(sscreen
, ir_binary
, shader
)) {
1843 mtx_unlock(&sscreen
->shader_cache_mutex
);
1844 si_shader_dump_stats_for_shader_db(shader
, debug
);
1846 mtx_unlock(&sscreen
->shader_cache_mutex
);
1848 /* Compile the shader if it hasn't been loaded from the cache. */
1849 if (si_compile_tgsi_shader(sscreen
, tm
, shader
, false,
1853 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
1858 mtx_lock(&sscreen
->shader_cache_mutex
);
1859 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
, shader
, true))
1861 mtx_unlock(&sscreen
->shader_cache_mutex
);
1865 *si_get_main_shader_part(sel
, &shader
->key
) = shader
;
1867 /* Unset "outputs_written" flags for outputs converted to
1868 * DEFAULT_VAL, so that later inter-shader optimizations don't
1869 * try to eliminate outputs that don't exist in the final
1872 * This is only done if non-monolithic shaders are enabled.
1874 if ((sel
->type
== PIPE_SHADER_VERTEX
||
1875 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
1876 !shader
->key
.as_ls
&&
1877 !shader
->key
.as_es
) {
1880 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
1881 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
1883 if (offset
<= AC_EXP_PARAM_OFFSET_31
)
1886 unsigned name
= sel
->info
.output_semantic_name
[i
];
1887 unsigned index
= sel
->info
.output_semantic_index
[i
];
1891 case TGSI_SEMANTIC_GENERIC
:
1892 /* don't process indices the function can't handle */
1893 if (index
>= SI_MAX_IO_GENERIC
)
1897 id
= si_shader_io_get_unique_index(name
, index
);
1898 sel
->outputs_written
&= ~(1ull << id
);
1900 case TGSI_SEMANTIC_POSITION
: /* ignore these */
1901 case TGSI_SEMANTIC_PSIZE
:
1902 case TGSI_SEMANTIC_CLIPVERTEX
:
1903 case TGSI_SEMANTIC_EDGEFLAG
:
1910 /* The GS copy shader is always pre-compiled. */
1911 if (sel
->type
== PIPE_SHADER_GEOMETRY
) {
1912 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, tm
, sel
, debug
);
1913 if (!sel
->gs_copy_shader
) {
1914 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
1918 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
1922 /* Return descriptor slot usage masks from the given shader info. */
1923 void si_get_active_slot_masks(const struct tgsi_shader_info
*info
,
1924 uint32_t *const_and_shader_buffers
,
1925 uint64_t *samplers_and_images
)
1927 unsigned start
, num_shaderbufs
, num_constbufs
, num_images
, num_samplers
;
1929 num_shaderbufs
= util_last_bit(info
->shader_buffers_declared
);
1930 num_constbufs
= util_last_bit(info
->const_buffers_declared
);
1931 /* two 8-byte images share one 16-byte slot */
1932 num_images
= align(util_last_bit(info
->images_declared
), 2);
1933 num_samplers
= util_last_bit(info
->samplers_declared
);
1935 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
1936 start
= si_get_shaderbuf_slot(num_shaderbufs
- 1);
1937 *const_and_shader_buffers
=
1938 u_bit_consecutive(start
, num_shaderbufs
+ num_constbufs
);
1940 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
1941 start
= si_get_image_slot(num_images
- 1) / 2;
1942 *samplers_and_images
=
1943 u_bit_consecutive64(start
, num_images
/ 2 + num_samplers
);
1946 static void *si_create_shader_selector(struct pipe_context
*ctx
,
1947 const struct pipe_shader_state
*state
)
1949 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
1950 struct si_context
*sctx
= (struct si_context
*)ctx
;
1951 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
1957 pipe_reference_init(&sel
->reference
, 1);
1958 sel
->screen
= sscreen
;
1959 sel
->compiler_ctx_state
.debug
= sctx
->debug
;
1960 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
1962 sel
->so
= state
->stream_output
;
1964 if (state
->type
== PIPE_SHADER_IR_TGSI
) {
1965 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
1971 tgsi_scan_shader(state
->tokens
, &sel
->info
);
1972 tgsi_scan_tess_ctrl(state
->tokens
, &sel
->info
, &sel
->tcs_info
);
1974 assert(state
->type
== PIPE_SHADER_IR_NIR
);
1976 sel
->nir
= state
->ir
.nir
;
1978 si_nir_scan_shader(sel
->nir
, &sel
->info
);
1979 si_nir_scan_tess_ctrl(sel
->nir
, &sel
->info
, &sel
->tcs_info
);
1984 sel
->type
= sel
->info
.processor
;
1985 p_atomic_inc(&sscreen
->num_shaders_created
);
1986 si_get_active_slot_masks(&sel
->info
,
1987 &sel
->active_const_and_shader_buffers
,
1988 &sel
->active_samplers_and_images
);
1990 /* Record which streamout buffers are enabled. */
1991 for (i
= 0; i
< sel
->so
.num_outputs
; i
++) {
1992 sel
->enabled_streamout_buffer_mask
|=
1993 (1 << sel
->so
.output
[i
].output_buffer
) <<
1994 (sel
->so
.output
[i
].stream
* 4);
1997 /* The prolog is a no-op if there are no inputs. */
1998 sel
->vs_needs_prolog
= sel
->type
== PIPE_SHADER_VERTEX
&&
1999 sel
->info
.num_inputs
&&
2000 !sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
2002 sel
->force_correct_derivs_after_kill
=
2003 sel
->type
== PIPE_SHADER_FRAGMENT
&&
2004 sel
->info
.uses_derivatives
&&
2005 sel
->info
.uses_kill
&&
2006 sctx
->screen
->debug_flags
& DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
2008 /* Set which opcode uses which (i,j) pair. */
2009 if (sel
->info
.uses_persp_opcode_interp_centroid
)
2010 sel
->info
.uses_persp_centroid
= true;
2012 if (sel
->info
.uses_linear_opcode_interp_centroid
)
2013 sel
->info
.uses_linear_centroid
= true;
2015 if (sel
->info
.uses_persp_opcode_interp_offset
||
2016 sel
->info
.uses_persp_opcode_interp_sample
)
2017 sel
->info
.uses_persp_center
= true;
2019 if (sel
->info
.uses_linear_opcode_interp_offset
||
2020 sel
->info
.uses_linear_opcode_interp_sample
)
2021 sel
->info
.uses_linear_center
= true;
2023 switch (sel
->type
) {
2024 case PIPE_SHADER_GEOMETRY
:
2025 sel
->gs_output_prim
=
2026 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
2027 sel
->gs_max_out_vertices
=
2028 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
2029 sel
->gs_num_invocations
=
2030 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
2031 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
2032 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
2033 sel
->gs_max_out_vertices
;
2035 sel
->max_gs_stream
= 0;
2036 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
2037 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
2038 sel
->so
.output
[i
].stream
);
2040 sel
->gs_input_verts_per_prim
=
2041 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
2044 case PIPE_SHADER_TESS_CTRL
:
2045 /* Always reserve space for these. */
2046 sel
->patch_outputs_written
|=
2047 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0)) |
2048 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0));
2050 case PIPE_SHADER_VERTEX
:
2051 case PIPE_SHADER_TESS_EVAL
:
2052 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2053 unsigned name
= sel
->info
.output_semantic_name
[i
];
2054 unsigned index
= sel
->info
.output_semantic_index
[i
];
2057 case TGSI_SEMANTIC_TESSINNER
:
2058 case TGSI_SEMANTIC_TESSOUTER
:
2059 case TGSI_SEMANTIC_PATCH
:
2060 sel
->patch_outputs_written
|=
2061 1ull << si_shader_io_get_unique_index_patch(name
, index
);
2064 case TGSI_SEMANTIC_GENERIC
:
2065 /* don't process indices the function can't handle */
2066 if (index
>= SI_MAX_IO_GENERIC
)
2070 sel
->outputs_written
|=
2071 1ull << si_shader_io_get_unique_index(name
, index
);
2073 case TGSI_SEMANTIC_CLIPVERTEX
: /* ignore these */
2074 case TGSI_SEMANTIC_EDGEFLAG
:
2078 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
2080 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2081 * conflicts, i.e. each vertex will start at a different bank.
2083 if (sctx
->b
.chip_class
>= GFX9
)
2084 sel
->esgs_itemsize
+= 4;
2087 case PIPE_SHADER_FRAGMENT
:
2088 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2089 unsigned name
= sel
->info
.input_semantic_name
[i
];
2090 unsigned index
= sel
->info
.input_semantic_index
[i
];
2093 case TGSI_SEMANTIC_GENERIC
:
2094 /* don't process indices the function can't handle */
2095 if (index
>= SI_MAX_IO_GENERIC
)
2100 1ull << si_shader_io_get_unique_index(name
, index
);
2102 case TGSI_SEMANTIC_PCOORD
: /* ignore this */
2107 for (i
= 0; i
< 8; i
++)
2108 if (sel
->info
.colors_written
& (1 << i
))
2109 sel
->colors_written_4bit
|= 0xf << (4 * i
);
2111 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2112 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
2113 int index
= sel
->info
.input_semantic_index
[i
];
2114 sel
->color_attr_index
[index
] = i
;
2120 /* PA_CL_VS_OUT_CNTL */
2122 sel
->info
.writes_psize
|| sel
->info
.writes_edgeflag
||
2123 sel
->info
.writes_layer
|| sel
->info
.writes_viewport_index
;
2124 sel
->pa_cl_vs_out_cntl
=
2125 S_02881C_USE_VTX_POINT_SIZE(sel
->info
.writes_psize
) |
2126 S_02881C_USE_VTX_EDGE_FLAG(sel
->info
.writes_edgeflag
) |
2127 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel
->info
.writes_layer
) |
2128 S_02881C_USE_VTX_VIEWPORT_INDX(sel
->info
.writes_viewport_index
) |
2129 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
2130 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
);
2131 sel
->clipdist_mask
= sel
->info
.writes_clipvertex
?
2132 SIX_BITS
: sel
->info
.clipdist_writemask
;
2133 sel
->culldist_mask
= sel
->info
.culldist_writemask
<<
2134 sel
->info
.num_written_clipdistance
;
2136 /* DB_SHADER_CONTROL */
2137 sel
->db_shader_control
=
2138 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
2139 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
2140 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
2141 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
2143 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
2144 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2145 sel
->db_shader_control
|=
2146 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2148 case TGSI_FS_DEPTH_LAYOUT_LESS
:
2149 sel
->db_shader_control
|=
2150 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2154 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2156 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2157 * --|-----------|------------|------------|--------------------|-------------------|-------------
2158 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2159 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2160 * 2 | false | true | n/a | LateZ | 1 | 0
2161 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2162 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2164 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2165 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2167 * Don't use ReZ without profiling !!!
2169 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2172 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
2174 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
2175 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
2176 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
2177 } else if (sel
->info
.writes_memory
) {
2179 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) |
2180 S_02880C_EXEC_ON_HIER_FAIL(1);
2183 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2186 (void) mtx_init(&sel
->mutex
, mtx_plain
);
2187 util_queue_fence_init(&sel
->ready
);
2189 struct util_async_debug_callback async_debug
;
2191 (sctx
->debug
.debug_message
&& !sctx
->debug
.async
) ||
2193 si_can_dump_shader(sscreen
, sel
->info
.processor
);
2196 u_async_debug_init(&async_debug
);
2197 sel
->compiler_ctx_state
.debug
= async_debug
.base
;
2200 util_queue_add_job(&sscreen
->shader_compiler_queue
, sel
,
2201 &sel
->ready
, si_init_shader_selector_async
,
2205 util_queue_fence_wait(&sel
->ready
);
2206 u_async_debug_drain(&async_debug
, &sctx
->debug
);
2207 u_async_debug_cleanup(&async_debug
);
2213 static void si_update_streamout_state(struct si_context
*sctx
)
2215 struct si_shader_selector
*shader_with_so
= si_get_vs(sctx
)->cso
;
2217 if (!shader_with_so
)
2220 sctx
->streamout
.enabled_stream_buffers_mask
=
2221 shader_with_so
->enabled_streamout_buffer_mask
;
2222 sctx
->streamout
.stride_in_dw
= shader_with_so
->so
.stride
;
2225 static void si_update_clip_regs(struct si_context
*sctx
,
2226 struct si_shader_selector
*old_hw_vs
,
2227 struct si_shader
*old_hw_vs_variant
,
2228 struct si_shader_selector
*next_hw_vs
,
2229 struct si_shader
*next_hw_vs_variant
)
2233 old_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] !=
2234 next_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] ||
2235 old_hw_vs
->pa_cl_vs_out_cntl
!= next_hw_vs
->pa_cl_vs_out_cntl
||
2236 old_hw_vs
->clipdist_mask
!= next_hw_vs
->clipdist_mask
||
2237 old_hw_vs
->culldist_mask
!= next_hw_vs
->culldist_mask
||
2238 !old_hw_vs_variant
||
2239 !next_hw_vs_variant
||
2240 old_hw_vs_variant
->key
.opt
.clip_disable
!=
2241 next_hw_vs_variant
->key
.opt
.clip_disable
))
2242 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
2245 static void si_update_common_shader_state(struct si_context
*sctx
)
2247 sctx
->uses_bindless_samplers
=
2248 si_shader_uses_bindless_samplers(sctx
->vs_shader
.cso
) ||
2249 si_shader_uses_bindless_samplers(sctx
->gs_shader
.cso
) ||
2250 si_shader_uses_bindless_samplers(sctx
->ps_shader
.cso
) ||
2251 si_shader_uses_bindless_samplers(sctx
->tcs_shader
.cso
) ||
2252 si_shader_uses_bindless_samplers(sctx
->tes_shader
.cso
);
2253 sctx
->uses_bindless_images
=
2254 si_shader_uses_bindless_images(sctx
->vs_shader
.cso
) ||
2255 si_shader_uses_bindless_images(sctx
->gs_shader
.cso
) ||
2256 si_shader_uses_bindless_images(sctx
->ps_shader
.cso
) ||
2257 si_shader_uses_bindless_images(sctx
->tcs_shader
.cso
) ||
2258 si_shader_uses_bindless_images(sctx
->tes_shader
.cso
);
2259 sctx
->do_update_shaders
= true;
2262 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
2264 struct si_context
*sctx
= (struct si_context
*)ctx
;
2265 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2266 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2267 struct si_shader_selector
*sel
= state
;
2269 if (sctx
->vs_shader
.cso
== sel
)
2272 sctx
->vs_shader
.cso
= sel
;
2273 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2274 sctx
->num_vs_blit_sgprs
= sel
? sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
] : 0;
2276 si_update_common_shader_state(sctx
);
2277 si_update_vs_viewport_state(sctx
);
2278 si_set_active_descriptors_for_shader(sctx
, sel
);
2279 si_update_streamout_state(sctx
);
2280 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2281 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2284 static void si_update_tess_uses_prim_id(struct si_context
*sctx
)
2286 sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
=
2287 (sctx
->tes_shader
.cso
&&
2288 sctx
->tes_shader
.cso
->info
.uses_primid
) ||
2289 (sctx
->tcs_shader
.cso
&&
2290 sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
2291 (sctx
->gs_shader
.cso
&&
2292 sctx
->gs_shader
.cso
->info
.uses_primid
) ||
2293 (sctx
->ps_shader
.cso
&& !sctx
->gs_shader
.cso
&&
2294 sctx
->ps_shader
.cso
->info
.uses_primid
);
2297 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
2299 struct si_context
*sctx
= (struct si_context
*)ctx
;
2300 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2301 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2302 struct si_shader_selector
*sel
= state
;
2303 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
2305 if (sctx
->gs_shader
.cso
== sel
)
2308 sctx
->gs_shader
.cso
= sel
;
2309 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2310 sctx
->ia_multi_vgt_param_key
.u
.uses_gs
= sel
!= NULL
;
2312 si_update_common_shader_state(sctx
);
2313 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2315 if (enable_changed
) {
2316 si_shader_change_notify(sctx
);
2317 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2318 si_update_tess_uses_prim_id(sctx
);
2320 si_update_vs_viewport_state(sctx
);
2321 si_set_active_descriptors_for_shader(sctx
, sel
);
2322 si_update_streamout_state(sctx
);
2323 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2324 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2327 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
2329 struct si_context
*sctx
= (struct si_context
*)ctx
;
2330 struct si_shader_selector
*sel
= state
;
2331 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
2333 if (sctx
->tcs_shader
.cso
== sel
)
2336 sctx
->tcs_shader
.cso
= sel
;
2337 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2338 si_update_tess_uses_prim_id(sctx
);
2340 si_update_common_shader_state(sctx
);
2343 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
2345 si_set_active_descriptors_for_shader(sctx
, sel
);
2348 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
2350 struct si_context
*sctx
= (struct si_context
*)ctx
;
2351 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2352 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2353 struct si_shader_selector
*sel
= state
;
2354 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
2356 if (sctx
->tes_shader
.cso
== sel
)
2359 sctx
->tes_shader
.cso
= sel
;
2360 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
2361 sctx
->ia_multi_vgt_param_key
.u
.uses_tess
= sel
!= NULL
;
2362 si_update_tess_uses_prim_id(sctx
);
2364 si_update_common_shader_state(sctx
);
2365 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2367 if (enable_changed
) {
2368 si_shader_change_notify(sctx
);
2369 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
2371 si_update_vs_viewport_state(sctx
);
2372 si_set_active_descriptors_for_shader(sctx
, sel
);
2373 si_update_streamout_state(sctx
);
2374 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2375 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2378 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
2380 struct si_context
*sctx
= (struct si_context
*)ctx
;
2381 struct si_shader_selector
*old_sel
= sctx
->ps_shader
.cso
;
2382 struct si_shader_selector
*sel
= state
;
2384 /* skip if supplied shader is one already in use */
2388 sctx
->ps_shader
.cso
= sel
;
2389 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
2391 si_update_common_shader_state(sctx
);
2393 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2394 si_update_tess_uses_prim_id(sctx
);
2397 old_sel
->info
.colors_written
!= sel
->info
.colors_written
)
2398 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
2400 if (sctx
->screen
->has_out_of_order_rast
&&
2402 old_sel
->info
.writes_memory
!= sel
->info
.writes_memory
||
2403 old_sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] !=
2404 sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]))
2405 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2407 si_set_active_descriptors_for_shader(sctx
, sel
);
2410 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
2412 if (shader
->is_optimized
) {
2413 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue_low_priority
,
2417 util_queue_fence_destroy(&shader
->ready
);
2420 switch (shader
->selector
->type
) {
2421 case PIPE_SHADER_VERTEX
:
2422 if (shader
->key
.as_ls
) {
2423 assert(sctx
->b
.chip_class
<= VI
);
2424 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
2425 } else if (shader
->key
.as_es
) {
2426 assert(sctx
->b
.chip_class
<= VI
);
2427 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2429 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2432 case PIPE_SHADER_TESS_CTRL
:
2433 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
2435 case PIPE_SHADER_TESS_EVAL
:
2436 if (shader
->key
.as_es
) {
2437 assert(sctx
->b
.chip_class
<= VI
);
2438 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2440 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2443 case PIPE_SHADER_GEOMETRY
:
2444 if (shader
->is_gs_copy_shader
)
2445 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2447 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
2449 case PIPE_SHADER_FRAGMENT
:
2450 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
2455 si_shader_selector_reference(sctx
, &shader
->previous_stage_sel
, NULL
);
2456 si_shader_destroy(shader
);
2460 void si_destroy_shader_selector(struct si_context
*sctx
,
2461 struct si_shader_selector
*sel
)
2463 struct si_shader
*p
= sel
->first_variant
, *c
;
2464 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
2465 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
2466 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
2467 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
2468 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
2469 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
2472 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue
, &sel
->ready
);
2474 if (current_shader
[sel
->type
]->cso
== sel
) {
2475 current_shader
[sel
->type
]->cso
= NULL
;
2476 current_shader
[sel
->type
]->current
= NULL
;
2480 c
= p
->next_variant
;
2481 si_delete_shader(sctx
, p
);
2485 if (sel
->main_shader_part
)
2486 si_delete_shader(sctx
, sel
->main_shader_part
);
2487 if (sel
->main_shader_part_ls
)
2488 si_delete_shader(sctx
, sel
->main_shader_part_ls
);
2489 if (sel
->main_shader_part_es
)
2490 si_delete_shader(sctx
, sel
->main_shader_part_es
);
2491 if (sel
->gs_copy_shader
)
2492 si_delete_shader(sctx
, sel
->gs_copy_shader
);
2494 util_queue_fence_destroy(&sel
->ready
);
2495 mtx_destroy(&sel
->mutex
);
2497 ralloc_free(sel
->nir
);
2501 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
2503 struct si_context
*sctx
= (struct si_context
*)ctx
;
2504 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
2506 si_shader_selector_reference(sctx
, &sel
, NULL
);
2509 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
2510 struct si_shader
*vs
, unsigned name
,
2511 unsigned index
, unsigned interpolate
)
2513 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
2514 unsigned j
, offset
, ps_input_cntl
= 0;
2516 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2517 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
))
2518 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
2520 if (name
== TGSI_SEMANTIC_PCOORD
||
2521 (name
== TGSI_SEMANTIC_TEXCOORD
&&
2522 sctx
->sprite_coord_enable
& (1 << index
))) {
2523 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
2526 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
2527 if (name
== vsinfo
->output_semantic_name
[j
] &&
2528 index
== vsinfo
->output_semantic_index
[j
]) {
2529 offset
= vs
->info
.vs_output_param_offset
[j
];
2531 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
2532 /* The input is loaded from parameter memory. */
2533 ps_input_cntl
|= S_028644_OFFSET(offset
);
2534 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2535 if (offset
== AC_EXP_PARAM_UNDEFINED
) {
2536 /* This can happen with depth-only rendering. */
2539 /* The input is a DEFAULT_VAL constant. */
2540 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
2541 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
2542 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
2545 ps_input_cntl
= S_028644_OFFSET(0x20) |
2546 S_028644_DEFAULT_VAL(offset
);
2552 if (name
== TGSI_SEMANTIC_PRIMID
)
2553 /* PrimID is written after the last output. */
2554 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
2555 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2556 /* No corresponding output found, load defaults into input.
2557 * Don't set any other bits.
2558 * (FLAT_SHADE=1 completely changes behavior) */
2559 ps_input_cntl
= S_028644_OFFSET(0x20);
2560 /* D3D 9 behaviour. GL is undefined */
2561 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
2562 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
2564 return ps_input_cntl
;
2567 static void si_emit_spi_map(struct si_context
*sctx
, struct r600_atom
*atom
)
2569 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2570 struct si_shader
*ps
= sctx
->ps_shader
.current
;
2571 struct si_shader
*vs
= si_get_vs_state(sctx
);
2572 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
2573 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
2575 if (!ps
|| !ps
->selector
->info
.num_inputs
)
2578 num_interp
= si_get_ps_num_interp(ps
);
2579 assert(num_interp
> 0);
2580 radeon_set_context_reg_seq(cs
, R_028644_SPI_PS_INPUT_CNTL_0
, num_interp
);
2582 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
2583 unsigned name
= psinfo
->input_semantic_name
[i
];
2584 unsigned index
= psinfo
->input_semantic_index
[i
];
2585 unsigned interpolate
= psinfo
->input_interpolate
[i
];
2587 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, name
, index
,
2591 if (name
== TGSI_SEMANTIC_COLOR
) {
2592 assert(index
< ARRAY_SIZE(bcol_interp
));
2593 bcol_interp
[index
] = interpolate
;
2597 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
2598 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
2600 for (i
= 0; i
< 2; i
++) {
2601 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
2604 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, bcol
,
2605 i
, bcol_interp
[i
]));
2609 assert(num_interp
== num_written
);
2613 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2615 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
2617 if (sctx
->init_config_has_vgt_flush
)
2620 /* Done by Vulkan before VGT_FLUSH. */
2621 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2622 si_pm4_cmd_add(sctx
->init_config
,
2623 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2624 si_pm4_cmd_end(sctx
->init_config
, false);
2626 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2627 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2628 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
2629 si_pm4_cmd_end(sctx
->init_config
, false);
2630 sctx
->init_config_has_vgt_flush
= true;
2633 /* Initialize state related to ESGS / GSVS ring buffers */
2634 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
2636 struct si_shader_selector
*es
=
2637 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
2638 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
2639 struct si_pm4_state
*pm4
;
2641 /* Chip constants. */
2642 unsigned num_se
= sctx
->screen
->info
.max_se
;
2643 unsigned wave_size
= 64;
2644 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
2645 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2646 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2648 unsigned gs_vertex_reuse
= (sctx
->b
.chip_class
>= VI
? 32 : 16) * num_se
;
2649 unsigned alignment
= 256 * num_se
;
2650 /* The maximum size is 63.999 MB per SE. */
2651 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
2653 /* Calculate the minimum size. */
2654 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
2655 wave_size
, alignment
);
2657 /* These are recommended sizes, not minimum sizes. */
2658 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
2659 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
2660 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
2661 gs
->max_gsvs_emit_size
;
2663 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
2664 esgs_ring_size
= align(esgs_ring_size
, alignment
);
2665 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
2667 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
2668 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
2670 /* Some rings don't have to be allocated if shaders don't use them.
2671 * (e.g. no varyings between ES and GS or GS and VS)
2673 * GFX9 doesn't have the ESGS ring.
2675 bool update_esgs
= sctx
->b
.chip_class
<= VI
&&
2677 (!sctx
->esgs_ring
||
2678 sctx
->esgs_ring
->width0
< esgs_ring_size
);
2679 bool update_gsvs
= gsvs_ring_size
&&
2680 (!sctx
->gsvs_ring
||
2681 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
2683 if (!update_esgs
&& !update_gsvs
)
2687 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
2689 si_aligned_buffer_create(sctx
->b
.b
.screen
,
2690 R600_RESOURCE_FLAG_UNMAPPABLE
,
2692 esgs_ring_size
, alignment
);
2693 if (!sctx
->esgs_ring
)
2698 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
2700 si_aligned_buffer_create(sctx
->b
.b
.screen
,
2701 R600_RESOURCE_FLAG_UNMAPPABLE
,
2703 gsvs_ring_size
, alignment
);
2704 if (!sctx
->gsvs_ring
)
2708 /* Create the "init_config_gs_rings" state. */
2709 pm4
= CALLOC_STRUCT(si_pm4_state
);
2713 if (sctx
->b
.chip_class
>= CIK
) {
2714 if (sctx
->esgs_ring
) {
2715 assert(sctx
->b
.chip_class
<= VI
);
2716 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
2717 sctx
->esgs_ring
->width0
/ 256);
2719 if (sctx
->gsvs_ring
)
2720 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
2721 sctx
->gsvs_ring
->width0
/ 256);
2723 if (sctx
->esgs_ring
)
2724 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
2725 sctx
->esgs_ring
->width0
/ 256);
2726 if (sctx
->gsvs_ring
)
2727 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
2728 sctx
->gsvs_ring
->width0
/ 256);
2731 /* Set the state. */
2732 if (sctx
->init_config_gs_rings
)
2733 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
2734 sctx
->init_config_gs_rings
= pm4
;
2736 if (!sctx
->init_config_has_vgt_flush
) {
2737 si_init_config_add_vgt_flush(sctx
);
2738 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
2741 /* Flush the context to re-emit both init_config states. */
2742 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
2743 si_context_gfx_flush(sctx
, PIPE_FLUSH_ASYNC
, NULL
);
2745 /* Set ring bindings. */
2746 if (sctx
->esgs_ring
) {
2747 assert(sctx
->b
.chip_class
<= VI
);
2748 si_set_ring_buffer(&sctx
->b
.b
, SI_ES_RING_ESGS
,
2749 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
2750 true, true, 4, 64, 0);
2751 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_ESGS
,
2752 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
2753 false, false, 0, 0, 0);
2755 if (sctx
->gsvs_ring
) {
2756 si_set_ring_buffer(&sctx
->b
.b
, SI_RING_GSVS
,
2757 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
2758 false, false, 0, 0, 0);
2764 static void si_shader_lock(struct si_shader
*shader
)
2766 mtx_lock(&shader
->selector
->mutex
);
2767 if (shader
->previous_stage_sel
) {
2768 assert(shader
->previous_stage_sel
!= shader
->selector
);
2769 mtx_lock(&shader
->previous_stage_sel
->mutex
);
2773 static void si_shader_unlock(struct si_shader
*shader
)
2775 if (shader
->previous_stage_sel
)
2776 mtx_unlock(&shader
->previous_stage_sel
->mutex
);
2777 mtx_unlock(&shader
->selector
->mutex
);
2781 * @returns 1 if \p sel has been updated to use a new scratch buffer
2783 * < 0 if there was a failure
2785 static int si_update_scratch_buffer(struct si_context
*sctx
,
2786 struct si_shader
*shader
)
2788 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
2794 /* This shader doesn't need a scratch buffer */
2795 if (shader
->config
.scratch_bytes_per_wave
== 0)
2798 /* Prevent race conditions when updating:
2799 * - si_shader::scratch_bo
2800 * - si_shader::binary::code
2801 * - si_shader::previous_stage::binary::code.
2803 si_shader_lock(shader
);
2805 /* This shader is already configured to use the current
2806 * scratch buffer. */
2807 if (shader
->scratch_bo
== sctx
->scratch_buffer
) {
2808 si_shader_unlock(shader
);
2812 assert(sctx
->scratch_buffer
);
2814 if (shader
->previous_stage
)
2815 si_shader_apply_scratch_relocs(shader
->previous_stage
, scratch_va
);
2817 si_shader_apply_scratch_relocs(shader
, scratch_va
);
2819 /* Replace the shader bo with a new bo that has the relocs applied. */
2820 r
= si_shader_binary_upload(sctx
->screen
, shader
);
2822 si_shader_unlock(shader
);
2826 /* Update the shader state to use the new shader bo. */
2827 si_shader_init_pm4_state(sctx
->screen
, shader
);
2829 r600_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
2831 si_shader_unlock(shader
);
2835 static unsigned si_get_current_scratch_buffer_size(struct si_context
*sctx
)
2837 return sctx
->scratch_buffer
? sctx
->scratch_buffer
->b
.b
.width0
: 0;
2840 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
2842 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
2845 static struct si_shader
*si_get_tcs_current(struct si_context
*sctx
)
2847 if (!sctx
->tes_shader
.cso
)
2848 return NULL
; /* tessellation disabled */
2850 return sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.current
:
2851 sctx
->fixed_func_tcs_shader
.current
;
2854 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context
*sctx
)
2858 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
2859 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
2860 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
2861 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
2863 if (sctx
->tes_shader
.cso
) {
2864 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
2866 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(tcs
));
2871 static bool si_update_scratch_relocs(struct si_context
*sctx
)
2873 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
2876 /* Update the shaders, so that they are using the latest scratch.
2877 * The scratch buffer may have been changed since these shaders were
2878 * last used, so we still need to try to update them, even if they
2879 * require scratch buffers smaller than the current size.
2881 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
2885 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
2887 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
2891 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
2893 r
= si_update_scratch_buffer(sctx
, tcs
);
2897 si_pm4_bind_state(sctx
, hs
, tcs
->pm4
);
2899 /* VS can be bound as LS, ES, or VS. */
2900 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
2904 if (sctx
->tes_shader
.current
)
2905 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
2906 else if (sctx
->gs_shader
.current
)
2907 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
2909 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
2912 /* TES can be bound as ES or VS. */
2913 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
2917 if (sctx
->gs_shader
.current
)
2918 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
2920 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
2926 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
2928 unsigned current_scratch_buffer_size
=
2929 si_get_current_scratch_buffer_size(sctx
);
2930 unsigned scratch_bytes_per_wave
=
2931 si_get_max_scratch_bytes_per_wave(sctx
);
2932 unsigned scratch_needed_size
= scratch_bytes_per_wave
*
2933 sctx
->scratch_waves
;
2934 unsigned spi_tmpring_size
;
2936 if (scratch_needed_size
> 0) {
2937 if (scratch_needed_size
> current_scratch_buffer_size
) {
2938 /* Create a bigger scratch buffer */
2939 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
2941 sctx
->scratch_buffer
= (struct r600_resource
*)
2942 si_aligned_buffer_create(&sctx
->screen
->b
,
2943 R600_RESOURCE_FLAG_UNMAPPABLE
,
2945 scratch_needed_size
, 256);
2946 if (!sctx
->scratch_buffer
)
2949 si_mark_atom_dirty(sctx
, &sctx
->scratch_state
);
2950 si_context_add_resource_size(&sctx
->b
.b
,
2951 &sctx
->scratch_buffer
->b
.b
);
2954 if (!si_update_scratch_relocs(sctx
))
2958 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
2959 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
2960 "scratch size should already be aligned correctly.");
2962 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
2963 S_0286E8_WAVESIZE(scratch_bytes_per_wave
>> 10);
2964 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
2965 sctx
->spi_tmpring_size
= spi_tmpring_size
;
2966 si_mark_atom_dirty(sctx
, &sctx
->scratch_state
);
2971 static void si_init_tess_factor_ring(struct si_context
*sctx
)
2973 assert(!sctx
->tess_rings
);
2975 /* The address must be aligned to 2^19, because the shader only
2976 * receives the high 13 bits.
2978 sctx
->tess_rings
= si_aligned_buffer_create(sctx
->b
.b
.screen
,
2979 R600_RESOURCE_FLAG_32BIT
,
2981 sctx
->screen
->tess_offchip_ring_size
+
2982 sctx
->screen
->tess_factor_ring_size
,
2984 if (!sctx
->tess_rings
)
2987 si_init_config_add_vgt_flush(sctx
);
2989 si_pm4_add_bo(sctx
->init_config
, r600_resource(sctx
->tess_rings
),
2990 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
2992 uint64_t factor_va
= r600_resource(sctx
->tess_rings
)->gpu_address
+
2993 sctx
->screen
->tess_offchip_ring_size
;
2995 /* Append these registers to the init config state. */
2996 if (sctx
->b
.chip_class
>= CIK
) {
2997 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
2998 S_030938_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
2999 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
3001 if (sctx
->b
.chip_class
>= GFX9
)
3002 si_pm4_set_reg(sctx
->init_config
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3004 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3005 sctx
->screen
->vgt_hs_offchip_param
);
3007 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
3008 S_008988_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3009 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
3011 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3012 sctx
->screen
->vgt_hs_offchip_param
);
3015 /* Flush the context to re-emit the init_config state.
3016 * This is done only once in a lifetime of a context.
3018 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3019 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
3020 si_context_gfx_flush(sctx
, PIPE_FLUSH_ASYNC
, NULL
);
3024 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
3025 * VS passes its outputs to TES directly, so the fixed-function shader only
3026 * has to write TESSOUTER and TESSINNER.
3028 static void si_generate_fixed_func_tcs(struct si_context
*sctx
)
3030 struct ureg_src outer
, inner
;
3031 struct ureg_dst tessouter
, tessinner
;
3032 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_TESS_CTRL
);
3035 return; /* if we get here, we're screwed */
3037 assert(!sctx
->fixed_func_tcs_shader
.cso
);
3039 outer
= ureg_DECL_system_value(ureg
,
3040 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
, 0);
3041 inner
= ureg_DECL_system_value(ureg
,
3042 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
, 0);
3044 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
3045 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
3047 ureg_MOV(ureg
, tessouter
, outer
);
3048 ureg_MOV(ureg
, tessinner
, inner
);
3051 sctx
->fixed_func_tcs_shader
.cso
=
3052 ureg_create_shader_and_destroy(ureg
, &sctx
->b
.b
);
3055 static void si_update_vgt_shader_config(struct si_context
*sctx
)
3057 /* Calculate the index of the config.
3058 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3059 unsigned index
= 2*!!sctx
->tes_shader
.cso
+ !!sctx
->gs_shader
.cso
;
3060 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[index
];
3063 uint32_t stages
= 0;
3065 *pm4
= CALLOC_STRUCT(si_pm4_state
);
3067 if (sctx
->tes_shader
.cso
) {
3068 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3069 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3071 if (sctx
->gs_shader
.cso
)
3072 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3074 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3076 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3077 } else if (sctx
->gs_shader
.cso
) {
3078 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3080 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3083 if (sctx
->b
.chip_class
>= GFX9
)
3084 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3086 si_pm4_set_reg(*pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
3088 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
3091 bool si_update_shaders(struct si_context
*sctx
)
3093 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
3094 struct si_compiler_ctx_state compiler_state
;
3095 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3096 struct si_shader
*old_vs
= si_get_vs_state(sctx
);
3097 bool old_clip_disable
= old_vs
? old_vs
->key
.opt
.clip_disable
: false;
3098 struct si_shader
*old_ps
= sctx
->ps_shader
.current
;
3099 unsigned old_spi_shader_col_format
=
3100 old_ps
? old_ps
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
3103 compiler_state
.tm
= sctx
->tm
;
3104 compiler_state
.debug
= sctx
->debug
;
3105 compiler_state
.is_debug_context
= sctx
->is_debug
;
3107 /* Update stages before GS. */
3108 if (sctx
->tes_shader
.cso
) {
3109 if (!sctx
->tess_rings
) {
3110 si_init_tess_factor_ring(sctx
);
3111 if (!sctx
->tess_rings
)
3116 if (sctx
->b
.chip_class
<= VI
) {
3117 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
3121 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3124 if (sctx
->tcs_shader
.cso
) {
3125 r
= si_shader_select(ctx
, &sctx
->tcs_shader
,
3129 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
3131 if (!sctx
->fixed_func_tcs_shader
.cso
) {
3132 si_generate_fixed_func_tcs(sctx
);
3133 if (!sctx
->fixed_func_tcs_shader
.cso
)
3137 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
,
3141 si_pm4_bind_state(sctx
, hs
,
3142 sctx
->fixed_func_tcs_shader
.current
->pm4
);
3145 if (sctx
->gs_shader
.cso
) {
3147 if (sctx
->b
.chip_class
<= VI
) {
3148 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
3152 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3156 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
3160 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3162 } else if (sctx
->gs_shader
.cso
) {
3163 if (sctx
->b
.chip_class
<= VI
) {
3165 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
3169 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3171 si_pm4_bind_state(sctx
, ls
, NULL
);
3172 si_pm4_bind_state(sctx
, hs
, NULL
);
3176 r
= si_shader_select(ctx
, &sctx
->vs_shader
, &compiler_state
);
3179 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3180 si_pm4_bind_state(sctx
, ls
, NULL
);
3181 si_pm4_bind_state(sctx
, hs
, NULL
);
3185 if (sctx
->gs_shader
.cso
) {
3186 r
= si_shader_select(ctx
, &sctx
->gs_shader
, &compiler_state
);
3189 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3190 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
3192 if (!si_update_gs_ring_buffers(sctx
))
3195 si_pm4_bind_state(sctx
, gs
, NULL
);
3196 if (sctx
->b
.chip_class
<= VI
)
3197 si_pm4_bind_state(sctx
, es
, NULL
);
3200 si_update_vgt_shader_config(sctx
);
3202 if (old_clip_disable
!= si_get_vs_state(sctx
)->key
.opt
.clip_disable
)
3203 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
3205 if (sctx
->ps_shader
.cso
) {
3206 unsigned db_shader_control
;
3208 r
= si_shader_select(ctx
, &sctx
->ps_shader
, &compiler_state
);
3211 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3214 sctx
->ps_shader
.cso
->db_shader_control
|
3215 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
3217 if (si_pm4_state_changed(sctx
, ps
) || si_pm4_state_changed(sctx
, vs
) ||
3218 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
3219 sctx
->flatshade
!= rs
->flatshade
) {
3220 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
3221 sctx
->flatshade
= rs
->flatshade
;
3222 si_mark_atom_dirty(sctx
, &sctx
->spi_map
);
3225 if (sctx
->screen
->rbplus_allowed
&&
3226 si_pm4_state_changed(sctx
, ps
) &&
3228 old_spi_shader_col_format
!=
3229 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
))
3230 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
3232 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
3233 sctx
->ps_db_shader_control
= db_shader_control
;
3234 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
3235 if (sctx
->screen
->dpbb_allowed
)
3236 si_mark_atom_dirty(sctx
, &sctx
->dpbb_state
);
3239 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
3240 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
3241 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
3243 if (sctx
->b
.chip_class
== SI
)
3244 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
3246 if (sctx
->framebuffer
.nr_samples
<= 1)
3247 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
3251 if (si_pm4_state_enabled_and_changed(sctx
, ls
) ||
3252 si_pm4_state_enabled_and_changed(sctx
, hs
) ||
3253 si_pm4_state_enabled_and_changed(sctx
, es
) ||
3254 si_pm4_state_enabled_and_changed(sctx
, gs
) ||
3255 si_pm4_state_enabled_and_changed(sctx
, vs
) ||
3256 si_pm4_state_enabled_and_changed(sctx
, ps
)) {
3257 if (!si_update_spi_tmpring_size(sctx
))
3261 if (sctx
->b
.chip_class
>= CIK
) {
3262 if (si_pm4_state_enabled_and_changed(sctx
, ls
))
3263 sctx
->prefetch_L2_mask
|= SI_PREFETCH_LS
;
3264 else if (!sctx
->queued
.named
.ls
)
3265 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_LS
;
3267 if (si_pm4_state_enabled_and_changed(sctx
, hs
))
3268 sctx
->prefetch_L2_mask
|= SI_PREFETCH_HS
;
3269 else if (!sctx
->queued
.named
.hs
)
3270 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_HS
;
3272 if (si_pm4_state_enabled_and_changed(sctx
, es
))
3273 sctx
->prefetch_L2_mask
|= SI_PREFETCH_ES
;
3274 else if (!sctx
->queued
.named
.es
)
3275 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_ES
;
3277 if (si_pm4_state_enabled_and_changed(sctx
, gs
))
3278 sctx
->prefetch_L2_mask
|= SI_PREFETCH_GS
;
3279 else if (!sctx
->queued
.named
.gs
)
3280 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_GS
;
3282 if (si_pm4_state_enabled_and_changed(sctx
, vs
))
3283 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VS
;
3284 else if (!sctx
->queued
.named
.vs
)
3285 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_VS
;
3287 if (si_pm4_state_enabled_and_changed(sctx
, ps
))
3288 sctx
->prefetch_L2_mask
|= SI_PREFETCH_PS
;
3289 else if (!sctx
->queued
.named
.ps
)
3290 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_PS
;
3293 sctx
->do_update_shaders
= false;
3297 static void si_emit_scratch_state(struct si_context
*sctx
,
3298 struct r600_atom
*atom
)
3300 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
3302 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
3303 sctx
->spi_tmpring_size
);
3305 if (sctx
->scratch_buffer
) {
3306 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
3307 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
3308 RADEON_PRIO_SCRATCH_BUFFER
);
3312 void *si_get_blit_vs(struct si_context
*sctx
, enum blitter_attrib_type type
,
3313 unsigned num_layers
)
3315 struct pipe_context
*pipe
= &sctx
->b
.b
;
3316 unsigned vs_blit_property
;
3320 case UTIL_BLITTER_ATTRIB_NONE
:
3321 vs
= num_layers
> 1 ? &sctx
->vs_blit_pos_layered
:
3323 vs_blit_property
= SI_VS_BLIT_SGPRS_POS
;
3325 case UTIL_BLITTER_ATTRIB_COLOR
:
3326 vs
= num_layers
> 1 ? &sctx
->vs_blit_color_layered
:
3327 &sctx
->vs_blit_color
;
3328 vs_blit_property
= SI_VS_BLIT_SGPRS_POS_COLOR
;
3330 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY
:
3331 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW
:
3332 assert(num_layers
== 1);
3333 vs
= &sctx
->vs_blit_texcoord
;
3334 vs_blit_property
= SI_VS_BLIT_SGPRS_POS_TEXCOORD
;
3343 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_VERTEX
);
3347 /* Tell the shader to load VS inputs from SGPRs: */
3348 ureg_property(ureg
, TGSI_PROPERTY_VS_BLIT_SGPRS
, vs_blit_property
);
3349 ureg_property(ureg
, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
, true);
3351 /* This is just a pass-through shader with 1-3 MOV instructions. */
3353 ureg_DECL_output(ureg
, TGSI_SEMANTIC_POSITION
, 0),
3354 ureg_DECL_vs_input(ureg
, 0));
3356 if (type
!= UTIL_BLITTER_ATTRIB_NONE
) {
3358 ureg_DECL_output(ureg
, TGSI_SEMANTIC_GENERIC
, 0),
3359 ureg_DECL_vs_input(ureg
, 1));
3362 if (num_layers
> 1) {
3363 struct ureg_src instance_id
=
3364 ureg_DECL_system_value(ureg
, TGSI_SEMANTIC_INSTANCEID
, 0);
3365 struct ureg_dst layer
=
3366 ureg_DECL_output(ureg
, TGSI_SEMANTIC_LAYER
, 0);
3368 ureg_MOV(ureg
, ureg_writemask(layer
, TGSI_WRITEMASK_X
),
3369 ureg_scalar(instance_id
, TGSI_SWIZZLE_X
));
3373 *vs
= ureg_create_shader_and_destroy(ureg
, pipe
);
3377 void si_init_shader_functions(struct si_context
*sctx
)
3379 si_init_atom(sctx
, &sctx
->spi_map
, &sctx
->atoms
.s
.spi_map
, si_emit_spi_map
);
3380 si_init_atom(sctx
, &sctx
->scratch_state
, &sctx
->atoms
.s
.scratch_state
,
3381 si_emit_scratch_state
);
3383 sctx
->b
.b
.create_vs_state
= si_create_shader_selector
;
3384 sctx
->b
.b
.create_tcs_state
= si_create_shader_selector
;
3385 sctx
->b
.b
.create_tes_state
= si_create_shader_selector
;
3386 sctx
->b
.b
.create_gs_state
= si_create_shader_selector
;
3387 sctx
->b
.b
.create_fs_state
= si_create_shader_selector
;
3389 sctx
->b
.b
.bind_vs_state
= si_bind_vs_shader
;
3390 sctx
->b
.b
.bind_tcs_state
= si_bind_tcs_shader
;
3391 sctx
->b
.b
.bind_tes_state
= si_bind_tes_shader
;
3392 sctx
->b
.b
.bind_gs_state
= si_bind_gs_shader
;
3393 sctx
->b
.b
.bind_fs_state
= si_bind_ps_shader
;
3395 sctx
->b
.b
.delete_vs_state
= si_delete_shader_selector
;
3396 sctx
->b
.b
.delete_tcs_state
= si_delete_shader_selector
;
3397 sctx
->b
.b
.delete_tes_state
= si_delete_shader_selector
;
3398 sctx
->b
.b
.delete_gs_state
= si_delete_shader_selector
;
3399 sctx
->b
.b
.delete_fs_state
= si_delete_shader_selector
;