2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
31 #include "radeon/r600_cs.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/hash_table.h"
36 #include "util/crc32.h"
37 #include "util/u_memory.h"
38 #include "util/u_prim.h"
40 #include "util/disk_cache.h"
41 #include "util/mesa-sha1.h"
42 #include "ac_exp_param.h"
47 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
50 static void *si_get_tgsi_binary(struct si_shader_selector
*sel
)
52 unsigned tgsi_size
= tgsi_num_tokens(sel
->tokens
) *
53 sizeof(struct tgsi_token
);
54 unsigned size
= 4 + tgsi_size
+ sizeof(sel
->so
);
55 char *result
= (char*)MALLOC(size
);
60 *((uint32_t*)result
) = size
;
61 memcpy(result
+ 4, sel
->tokens
, tgsi_size
);
62 memcpy(result
+ 4 + tgsi_size
, &sel
->so
, sizeof(sel
->so
));
66 /** Copy "data" to "ptr" and return the next dword following copied data. */
67 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
69 /* data may be NULL if size == 0 */
71 memcpy(ptr
, data
, size
);
72 ptr
+= DIV_ROUND_UP(size
, 4);
76 /** Read data from "ptr". Return the next dword following the data. */
77 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
79 memcpy(data
, ptr
, size
);
80 ptr
+= DIV_ROUND_UP(size
, 4);
85 * Write the size as uint followed by the data. Return the next dword
86 * following the copied data.
88 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
91 return write_data(ptr
, data
, size
);
95 * Read the size as uint followed by the data. Return both via parameters.
96 * Return the next dword following the data.
98 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
101 assert(*data
== NULL
);
104 *data
= malloc(*size
);
105 return read_data(ptr
, *data
, *size
);
109 * Return the shader binary in a buffer. The first 4 bytes contain its size
112 static void *si_get_shader_binary(struct si_shader
*shader
)
114 /* There is always a size of data followed by the data itself. */
115 unsigned relocs_size
= shader
->binary
.reloc_count
*
116 sizeof(shader
->binary
.relocs
[0]);
117 unsigned disasm_size
= shader
->binary
.disasm_string
?
118 strlen(shader
->binary
.disasm_string
) + 1 : 0;
119 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
120 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
123 4 + /* CRC32 of the data below */
124 align(sizeof(shader
->config
), 4) +
125 align(sizeof(shader
->info
), 4) +
126 4 + align(shader
->binary
.code_size
, 4) +
127 4 + align(shader
->binary
.rodata_size
, 4) +
128 4 + align(relocs_size
, 4) +
129 4 + align(disasm_size
, 4) +
130 4 + align(llvm_ir_size
, 4);
131 void *buffer
= CALLOC(1, size
);
132 uint32_t *ptr
= (uint32_t*)buffer
;
138 ptr
++; /* CRC32 is calculated at the end. */
140 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
141 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
142 ptr
= write_chunk(ptr
, shader
->binary
.code
, shader
->binary
.code_size
);
143 ptr
= write_chunk(ptr
, shader
->binary
.rodata
, shader
->binary
.rodata_size
);
144 ptr
= write_chunk(ptr
, shader
->binary
.relocs
, relocs_size
);
145 ptr
= write_chunk(ptr
, shader
->binary
.disasm_string
, disasm_size
);
146 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
147 assert((char *)ptr
- (char *)buffer
== size
);
150 ptr
= (uint32_t*)buffer
;
152 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
157 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
159 uint32_t *ptr
= (uint32_t*)binary
;
160 uint32_t size
= *ptr
++;
161 uint32_t crc32
= *ptr
++;
164 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
165 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
169 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
170 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
171 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.code
,
172 &shader
->binary
.code_size
);
173 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.rodata
,
174 &shader
->binary
.rodata_size
);
175 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.relocs
, &chunk_size
);
176 shader
->binary
.reloc_count
= chunk_size
/ sizeof(shader
->binary
.relocs
[0]);
177 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.disasm_string
, &chunk_size
);
178 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
184 * Insert a shader into the cache. It's assumed the shader is not in the cache.
185 * Use si_shader_cache_load_shader before calling this.
187 * Returns false on failure, in which case the tgsi_binary should be freed.
189 static bool si_shader_cache_insert_shader(struct si_screen
*sscreen
,
191 struct si_shader
*shader
,
192 bool insert_into_disk_cache
)
195 struct hash_entry
*entry
;
196 uint8_t key
[CACHE_KEY_SIZE
];
198 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, tgsi_binary
);
200 return false; /* already added */
202 hw_binary
= si_get_shader_binary(shader
);
206 if (_mesa_hash_table_insert(sscreen
->shader_cache
, tgsi_binary
,
207 hw_binary
) == NULL
) {
212 if (sscreen
->b
.disk_shader_cache
&& insert_into_disk_cache
) {
213 disk_cache_compute_key(sscreen
->b
.disk_shader_cache
, tgsi_binary
,
214 *((uint32_t *)tgsi_binary
), key
);
215 disk_cache_put(sscreen
->b
.disk_shader_cache
, key
, hw_binary
,
216 *((uint32_t *) hw_binary
));
222 static bool si_shader_cache_load_shader(struct si_screen
*sscreen
,
224 struct si_shader
*shader
)
226 struct hash_entry
*entry
=
227 _mesa_hash_table_search(sscreen
->shader_cache
, tgsi_binary
);
229 if (sscreen
->b
.disk_shader_cache
) {
230 unsigned char sha1
[CACHE_KEY_SIZE
];
231 size_t tg_size
= *((uint32_t *) tgsi_binary
);
233 disk_cache_compute_key(sscreen
->b
.disk_shader_cache
,
234 tgsi_binary
, tg_size
, sha1
);
238 disk_cache_get(sscreen
->b
.disk_shader_cache
,
243 if (binary_size
< sizeof(uint32_t) ||
244 *((uint32_t*)buffer
) != binary_size
) {
245 /* Something has gone wrong discard the item
246 * from the cache and rebuild/link from
249 assert(!"Invalid radeonsi shader disk cache "
252 disk_cache_remove(sscreen
->b
.disk_shader_cache
,
259 if (!si_load_shader_binary(shader
, buffer
)) {
265 if (!si_shader_cache_insert_shader(sscreen
, tgsi_binary
,
272 if (si_load_shader_binary(shader
, entry
->data
))
277 p_atomic_inc(&sscreen
->b
.num_shader_cache_hits
);
281 static uint32_t si_shader_cache_key_hash(const void *key
)
283 /* The first dword is the key size. */
284 return util_hash_crc32(key
, *(uint32_t*)key
);
287 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
289 uint32_t *keya
= (uint32_t*)a
;
290 uint32_t *keyb
= (uint32_t*)b
;
292 /* The first dword is the key size. */
296 return memcmp(keya
, keyb
, *keya
) == 0;
299 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
301 FREE((void*)entry
->key
);
305 bool si_init_shader_cache(struct si_screen
*sscreen
)
307 (void) mtx_init(&sscreen
->shader_cache_mutex
, mtx_plain
);
308 sscreen
->shader_cache
=
309 _mesa_hash_table_create(NULL
,
310 si_shader_cache_key_hash
,
311 si_shader_cache_key_equals
);
313 return sscreen
->shader_cache
!= NULL
;
316 void si_destroy_shader_cache(struct si_screen
*sscreen
)
318 if (sscreen
->shader_cache
)
319 _mesa_hash_table_destroy(sscreen
->shader_cache
,
320 si_destroy_shader_cache_entry
);
321 mtx_destroy(&sscreen
->shader_cache_mutex
);
326 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
327 struct si_shader_selector
*tes
,
328 struct si_pm4_state
*pm4
)
330 struct tgsi_shader_info
*info
= &tes
->info
;
331 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
332 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
333 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
334 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
335 unsigned type
, partitioning
, topology
, distribution_mode
;
337 switch (tes_prim_mode
) {
338 case PIPE_PRIM_LINES
:
339 type
= V_028B6C_TESS_ISOLINE
;
341 case PIPE_PRIM_TRIANGLES
:
342 type
= V_028B6C_TESS_TRIANGLE
;
344 case PIPE_PRIM_QUADS
:
345 type
= V_028B6C_TESS_QUAD
;
352 switch (tes_spacing
) {
353 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
354 partitioning
= V_028B6C_PART_FRAC_ODD
;
356 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
357 partitioning
= V_028B6C_PART_FRAC_EVEN
;
359 case PIPE_TESS_SPACING_EQUAL
:
360 partitioning
= V_028B6C_PART_INTEGER
;
368 topology
= V_028B6C_OUTPUT_POINT
;
369 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
370 topology
= V_028B6C_OUTPUT_LINE
;
371 else if (tes_vertex_order_cw
)
372 /* for some reason, this must be the other way around */
373 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
375 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
377 if (sscreen
->has_distributed_tess
) {
378 if (sscreen
->b
.family
== CHIP_FIJI
||
379 sscreen
->b
.family
>= CHIP_POLARIS10
)
380 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
382 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
384 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
386 si_pm4_set_reg(pm4
, R_028B6C_VGT_TF_PARAM
,
387 S_028B6C_TYPE(type
) |
388 S_028B6C_PARTITIONING(partitioning
) |
389 S_028B6C_TOPOLOGY(topology
) |
390 S_028B6C_DISTRIBUTION_MODE(distribution_mode
));
393 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
394 * whether the "fractional odd" tessellation spacing is used.
396 * Possible VGT configurations and which state should set the register:
398 * Reg set in | VGT shader configuration | Value
399 * ------------------------------------------------------
401 * VS as ES | ES -> GS -> VS | 30
402 * TES as VS | LS -> HS -> VS | 14 or 30
403 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
405 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
407 static void polaris_set_vgt_vertex_reuse(struct si_screen
*sscreen
,
408 struct si_shader_selector
*sel
,
409 struct si_shader
*shader
,
410 struct si_pm4_state
*pm4
)
412 unsigned type
= sel
->type
;
414 if (sscreen
->b
.family
< CHIP_POLARIS10
)
417 /* VS as VS, or VS as ES: */
418 if ((type
== PIPE_SHADER_VERTEX
&&
420 (!shader
->key
.as_ls
&& !shader
->is_gs_copy_shader
))) ||
421 /* TES as VS, or TES as ES: */
422 type
== PIPE_SHADER_TESS_EVAL
) {
423 unsigned vtx_reuse_depth
= 30;
425 if (type
== PIPE_SHADER_TESS_EVAL
&&
426 sel
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] ==
427 PIPE_TESS_SPACING_FRACTIONAL_ODD
)
428 vtx_reuse_depth
= 14;
430 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
435 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
438 si_pm4_clear_state(shader
->pm4
);
440 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
445 static void si_shader_ls(struct si_screen
*sscreen
, struct si_shader
*shader
)
447 struct si_pm4_state
*pm4
;
448 unsigned vgpr_comp_cnt
;
451 assert(sscreen
->b
.chip_class
<= VI
);
453 pm4
= si_get_shader_pm4_state(shader
);
457 va
= shader
->bo
->gpu_address
;
458 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
460 /* We need at least 2 components for LS.
461 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
462 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
464 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
466 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
467 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, va
>> 40);
469 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
470 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
471 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt
) |
472 S_00B528_DX10_CLAMP(1) |
473 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
474 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(SI_VS_NUM_USER_SGPR
) |
475 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
478 static void si_shader_hs(struct si_screen
*sscreen
, struct si_shader
*shader
)
480 struct si_pm4_state
*pm4
;
482 unsigned ls_vgpr_comp_cnt
= 0;
484 pm4
= si_get_shader_pm4_state(shader
);
488 va
= shader
->bo
->gpu_address
;
489 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
491 if (sscreen
->b
.chip_class
>= GFX9
) {
492 si_pm4_set_reg(pm4
, R_00B410_SPI_SHADER_PGM_LO_LS
, va
>> 8);
493 si_pm4_set_reg(pm4
, R_00B414_SPI_SHADER_PGM_HI_LS
, va
>> 40);
495 /* We need at least 2 components for LS.
496 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
497 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
499 ls_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
501 shader
->config
.rsrc2
=
502 S_00B42C_USER_SGPR(GFX9_TCS_NUM_USER_SGPR
) |
503 S_00B42C_USER_SGPR_MSB(GFX9_TCS_NUM_USER_SGPR
>> 5) |
504 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
506 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
507 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, va
>> 40);
509 shader
->config
.rsrc2
=
510 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR
) |
511 S_00B42C_OC_LDS_EN(1) |
512 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
515 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
516 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
517 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
518 S_00B428_DX10_CLAMP(1) |
519 S_00B428_FLOAT_MODE(shader
->config
.float_mode
) |
520 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt
));
522 if (sscreen
->b
.chip_class
<= VI
) {
523 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
524 shader
->config
.rsrc2
);
528 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
530 struct si_pm4_state
*pm4
;
531 unsigned num_user_sgprs
;
532 unsigned vgpr_comp_cnt
;
536 assert(sscreen
->b
.chip_class
<= VI
);
538 pm4
= si_get_shader_pm4_state(shader
);
542 va
= shader
->bo
->gpu_address
;
543 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
545 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
546 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
547 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
548 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
549 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
550 vgpr_comp_cnt
= shader
->selector
->info
.uses_primid
? 3 : 2;
551 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
553 unreachable("invalid shader selector type");
555 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
557 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
558 shader
->selector
->esgs_itemsize
/ 4);
559 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
560 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
561 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
562 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
563 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
564 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
565 S_00B328_DX10_CLAMP(1) |
566 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
567 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
568 S_00B32C_USER_SGPR(num_user_sgprs
) |
569 S_00B32C_OC_LDS_EN(oc_lds_en
) |
570 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
572 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
573 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
575 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
579 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
582 static uint32_t si_vgt_gs_mode(struct si_shader_selector
*sel
)
584 enum chip_class chip_class
= sel
->screen
->b
.chip_class
;
585 unsigned gs_max_vert_out
= sel
->gs_max_out_vertices
;
588 if (gs_max_vert_out
<= 128) {
589 cut_mode
= V_028A40_GS_CUT_128
;
590 } else if (gs_max_vert_out
<= 256) {
591 cut_mode
= V_028A40_GS_CUT_256
;
592 } else if (gs_max_vert_out
<= 512) {
593 cut_mode
= V_028A40_GS_CUT_512
;
595 assert(gs_max_vert_out
<= 1024);
596 cut_mode
= V_028A40_GS_CUT_1024
;
599 return S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
600 S_028A40_CUT_MODE(cut_mode
)|
601 S_028A40_ES_WRITE_OPTIMIZE(chip_class
<= VI
) |
602 S_028A40_GS_WRITE_OPTIMIZE(1) |
603 S_028A40_ONCHIP(chip_class
>= GFX9
? 1 : 0);
606 struct gfx9_gs_info
{
607 unsigned es_verts_per_subgroup
;
608 unsigned gs_prims_per_subgroup
;
609 unsigned gs_inst_prims_in_subgroup
;
610 unsigned max_prims_per_subgroup
;
614 static void gfx9_get_gs_info(struct si_shader_selector
*es
,
615 struct si_shader_selector
*gs
,
616 struct gfx9_gs_info
*out
)
618 unsigned gs_num_invocations
= MAX2(gs
->gs_num_invocations
, 1);
619 unsigned input_prim
= gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
620 bool uses_adjacency
= input_prim
>= PIPE_PRIM_LINES_ADJACENCY
&&
621 input_prim
<= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
;
623 /* All these are in dwords: */
624 /* We can't allow using the whole LDS, because GS waves compete with
625 * other shader stages for LDS space. */
626 const unsigned max_lds_size
= 8 * 1024;
627 const unsigned esgs_itemsize
= es
->esgs_itemsize
/ 4;
628 unsigned esgs_lds_size
;
630 /* All these are per subgroup: */
631 const unsigned max_out_prims
= 32 * 1024;
632 const unsigned max_es_verts
= 255;
633 const unsigned ideal_gs_prims
= 64;
634 unsigned max_gs_prims
, gs_prims
;
635 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
637 assert(gs_num_invocations
<= 32); /* GL maximum */
639 if (uses_adjacency
|| gs_num_invocations
> 1)
640 max_gs_prims
= 127 / gs_num_invocations
;
644 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
645 * Make sure we don't go over the maximum value.
647 max_gs_prims
= MIN2(max_gs_prims
,
649 (gs
->gs_max_out_vertices
* gs_num_invocations
));
650 assert(max_gs_prims
> 0);
652 /* If the primitive has adjacency, halve the number of vertices
653 * that will be reused in multiple primitives.
655 min_es_verts
= gs
->gs_input_verts_per_prim
/ (uses_adjacency
? 2 : 1);
657 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
658 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
660 /* Compute ESGS LDS size based on the worst case number of ES vertices
661 * needed to create the target number of GS prims per subgroup.
663 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
665 /* If total LDS usage is too big, refactor partitions based on ratio
666 * of ESGS item sizes.
668 if (esgs_lds_size
> max_lds_size
) {
669 /* Our target GS Prims Per Subgroup was too large. Calculate
670 * the maximum number of GS Prims Per Subgroup that will fit
671 * into LDS, capped by the maximum that the hardware can support.
673 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
675 assert(gs_prims
> 0);
676 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
679 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
680 assert(esgs_lds_size
<= max_lds_size
);
683 /* Now calculate remaining ESGS information. */
685 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
687 es_verts
= max_es_verts
;
689 /* Vertices for adjacency primitives are not always reused, so restore
690 * it for ES_VERTS_PER_SUBGRP.
692 min_es_verts
= gs
->gs_input_verts_per_prim
;
694 /* For normal primitives, the VGT only checks if they are past the ES
695 * verts per subgroup after allocating a full GS primitive and if they
696 * are, kick off a new subgroup. But if those additional ES verts are
697 * unique (e.g. not reused) we need to make sure there is enough LDS
698 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
700 es_verts
-= min_es_verts
- 1;
702 out
->es_verts_per_subgroup
= es_verts
;
703 out
->gs_prims_per_subgroup
= gs_prims
;
704 out
->gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
705 out
->max_prims_per_subgroup
= out
->gs_inst_prims_in_subgroup
*
706 gs
->gs_max_out_vertices
;
707 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
709 assert(out
->max_prims_per_subgroup
<= max_out_prims
);
712 static void si_shader_gs(struct si_screen
*sscreen
, struct si_shader
*shader
)
714 struct si_shader_selector
*sel
= shader
->selector
;
715 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
716 unsigned gs_num_invocations
= sel
->gs_num_invocations
;
717 struct si_pm4_state
*pm4
;
719 unsigned max_stream
= sel
->max_gs_stream
;
722 pm4
= si_get_shader_pm4_state(shader
);
726 offset
= num_components
[0] * sel
->gs_max_out_vertices
;
727 si_pm4_set_reg(pm4
, R_028A60_VGT_GSVS_RING_OFFSET_1
, offset
);
729 offset
+= num_components
[1] * sel
->gs_max_out_vertices
;
730 si_pm4_set_reg(pm4
, R_028A64_VGT_GSVS_RING_OFFSET_2
, offset
);
732 offset
+= num_components
[2] * sel
->gs_max_out_vertices
;
733 si_pm4_set_reg(pm4
, R_028A68_VGT_GSVS_RING_OFFSET_3
, offset
);
735 offset
+= num_components
[3] * sel
->gs_max_out_vertices
;
736 si_pm4_set_reg(pm4
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
738 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
739 assert(offset
< (1 << 15));
741 si_pm4_set_reg(pm4
, R_028B38_VGT_GS_MAX_VERT_OUT
, sel
->gs_max_out_vertices
);
743 si_pm4_set_reg(pm4
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, num_components
[0]);
744 si_pm4_set_reg(pm4
, R_028B60_VGT_GS_VERT_ITEMSIZE_1
, (max_stream
>= 1) ? num_components
[1] : 0);
745 si_pm4_set_reg(pm4
, R_028B64_VGT_GS_VERT_ITEMSIZE_2
, (max_stream
>= 2) ? num_components
[2] : 0);
746 si_pm4_set_reg(pm4
, R_028B68_VGT_GS_VERT_ITEMSIZE_3
, (max_stream
>= 3) ? num_components
[3] : 0);
748 si_pm4_set_reg(pm4
, R_028B90_VGT_GS_INSTANCE_CNT
,
749 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
750 S_028B90_ENABLE(gs_num_invocations
> 0));
752 va
= shader
->bo
->gpu_address
;
753 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
755 if (sscreen
->b
.chip_class
>= GFX9
) {
756 unsigned input_prim
= sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
757 unsigned es_type
= shader
->key
.part
.gs
.es
->type
;
758 unsigned es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
759 struct gfx9_gs_info gs_info
;
761 if (es_type
== PIPE_SHADER_VERTEX
)
762 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
763 es_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
764 else if (es_type
== PIPE_SHADER_TESS_EVAL
)
765 es_vgpr_comp_cnt
= shader
->key
.part
.gs
.es
->info
.uses_primid
? 3 : 2;
767 unreachable("invalid shader selector type");
769 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
770 * VGPR[0:4] are always loaded.
772 if (sel
->info
.uses_invocationid
)
773 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
774 else if (sel
->info
.uses_primid
)
775 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
776 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
777 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
779 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
781 gfx9_get_gs_info(shader
->key
.part
.gs
.es
, sel
, &gs_info
);
783 si_pm4_set_reg(pm4
, R_00B210_SPI_SHADER_PGM_LO_ES
, va
>> 8);
784 si_pm4_set_reg(pm4
, R_00B214_SPI_SHADER_PGM_HI_ES
, va
>> 40);
786 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
787 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
788 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
789 S_00B228_DX10_CLAMP(1) |
790 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
791 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
));
792 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
793 S_00B22C_USER_SGPR(GFX9_GS_NUM_USER_SGPR
) |
794 S_00B22C_USER_SGPR_MSB(GFX9_GS_NUM_USER_SGPR
>> 5) |
795 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
796 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
797 S_00B22C_LDS_SIZE(gs_info
.lds_size
) |
798 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
800 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
801 S_028A44_ES_VERTS_PER_SUBGRP(gs_info
.es_verts_per_subgroup
) |
802 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info
.gs_prims_per_subgroup
) |
803 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info
.gs_inst_prims_in_subgroup
));
804 si_pm4_set_reg(pm4
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
805 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info
.max_prims_per_subgroup
));
806 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
807 shader
->key
.part
.gs
.es
->esgs_itemsize
/ 4);
809 if (es_type
== PIPE_SHADER_TESS_EVAL
)
810 si_set_tesseval_regs(sscreen
, shader
->key
.part
.gs
.es
, pm4
);
812 polaris_set_vgt_vertex_reuse(sscreen
, shader
->key
.part
.gs
.es
,
815 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
816 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, va
>> 40);
818 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
819 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
820 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
821 S_00B228_DX10_CLAMP(1) |
822 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
823 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
824 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR
) |
825 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
830 * Compute the state for \p shader, which will run as a vertex shader on the
833 * If \p gs is non-NULL, it points to the geometry shader for which this shader
834 * is the copy shader.
836 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
837 struct si_shader_selector
*gs
)
839 struct si_pm4_state
*pm4
;
840 unsigned num_user_sgprs
;
841 unsigned nparams
, vgpr_comp_cnt
;
844 unsigned window_space
=
845 shader
->selector
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
846 bool enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| shader
->selector
->info
.uses_primid
;
848 pm4
= si_get_shader_pm4_state(shader
);
852 /* We always write VGT_GS_MODE in the VS state, because every switch
853 * between different shader pipelines involving a different GS or no
854 * GS at all involves a switch of the VS (different GS use different
855 * copy shaders). On the other hand, when the API switches from a GS to
856 * no GS and then back to the same GS used originally, the GS state is
862 /* PrimID needs GS scenario A.
863 * GFX9 also needs it when ViewportIndex is enabled.
865 if (enable_prim_id
||
866 (sscreen
->b
.chip_class
>= GFX9
&&
867 shader
->selector
->info
.writes_viewport_index
))
868 mode
= V_028A40_GS_SCENARIO_A
;
870 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, S_028A40_MODE(mode
));
871 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, enable_prim_id
);
873 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, si_vgt_gs_mode(gs
));
874 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
877 va
= shader
->bo
->gpu_address
;
878 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
881 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
882 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
883 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
884 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
885 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
886 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
888 vgpr_comp_cnt
= enable_prim_id
? 2 : (shader
->info
.uses_instanceid
? 1 : 0);
889 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
890 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
891 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
892 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
894 unreachable("invalid shader selector type");
896 /* VS is required to export at least one param. */
897 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
898 si_pm4_set_reg(pm4
, R_0286C4_SPI_VS_OUT_CONFIG
,
899 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
901 si_pm4_set_reg(pm4
, R_02870C_SPI_SHADER_POS_FORMAT
,
902 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
903 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
904 V_02870C_SPI_SHADER_4COMP
:
905 V_02870C_SPI_SHADER_NONE
) |
906 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
907 V_02870C_SPI_SHADER_4COMP
:
908 V_02870C_SPI_SHADER_NONE
) |
909 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
910 V_02870C_SPI_SHADER_4COMP
:
911 V_02870C_SPI_SHADER_NONE
));
913 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
915 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
916 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, va
>> 40);
917 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
918 S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
919 S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
920 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
921 S_00B128_DX10_CLAMP(1) |
922 S_00B128_FLOAT_MODE(shader
->config
.float_mode
));
923 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
924 S_00B12C_USER_SGPR(num_user_sgprs
) |
925 S_00B12C_OC_LDS_EN(oc_lds_en
) |
926 S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
927 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
928 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
929 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
930 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
) |
931 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
933 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
934 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
936 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
937 S_028818_VTX_W0_FMT(1) |
938 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
939 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
940 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
942 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
943 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
945 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
948 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
950 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
951 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
952 !!(info
->colors_read
& 0xf0);
953 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
954 (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
956 assert(num_interp
<= 32);
957 return MIN2(num_interp
, 32);
960 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
962 unsigned value
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
963 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
965 /* If the i-th target format is set, all previous target formats must
966 * be non-zero to avoid hangs.
968 for (i
= 0; i
< num_targets
; i
++)
969 if (!(value
& (0xf << (i
* 4))))
970 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
975 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format
)
977 unsigned i
, cb_shader_mask
= 0;
979 for (i
= 0; i
< 8; i
++) {
980 switch ((spi_shader_col_format
>> (i
* 4)) & 0xf) {
981 case V_028714_SPI_SHADER_ZERO
:
983 case V_028714_SPI_SHADER_32_R
:
984 cb_shader_mask
|= 0x1 << (i
* 4);
986 case V_028714_SPI_SHADER_32_GR
:
987 cb_shader_mask
|= 0x3 << (i
* 4);
989 case V_028714_SPI_SHADER_32_AR
:
990 cb_shader_mask
|= 0x9 << (i
* 4);
992 case V_028714_SPI_SHADER_FP16_ABGR
:
993 case V_028714_SPI_SHADER_UNORM16_ABGR
:
994 case V_028714_SPI_SHADER_SNORM16_ABGR
:
995 case V_028714_SPI_SHADER_UINT16_ABGR
:
996 case V_028714_SPI_SHADER_SINT16_ABGR
:
997 case V_028714_SPI_SHADER_32_ABGR
:
998 cb_shader_mask
|= 0xf << (i
* 4);
1004 return cb_shader_mask
;
1007 static void si_shader_ps(struct si_shader
*shader
)
1009 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1010 struct si_pm4_state
*pm4
;
1011 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
1012 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
1014 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
1016 /* we need to enable at least one of them, otherwise we hang the GPU */
1017 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1018 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1019 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1020 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
1021 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
1022 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1023 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
1024 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
1025 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1026 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
1027 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1028 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1029 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1030 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
1032 /* Validate interpolation optimization flags (read as implications). */
1033 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1034 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1035 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1036 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1037 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1038 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1039 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
1040 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
1041 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1042 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
1043 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
1044 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1045 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
1046 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1047 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1048 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
1049 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1050 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1052 /* Validate cases when the optimizations are off (read as implications). */
1053 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1054 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1055 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
1056 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1057 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1058 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
1060 pm4
= si_get_shader_pm4_state(shader
);
1064 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1066 * 0 -> Position = pixel center
1067 * 1 -> Position = pixel centroid
1068 * 2 -> Position = at sample position
1070 * From GLSL 4.5 specification, section 7.1:
1071 * "The variable gl_FragCoord is available as an input variable from
1072 * within fragment shaders and it holds the window relative coordinates
1073 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1074 * value can be for any location within the pixel, or one of the
1075 * fragment samples. The use of centroid does not further restrict
1076 * this value to be inside the current primitive."
1078 * Meaning that centroid has no effect and we can return anything within
1079 * the pixel. Thus, return the value at sample position, because that's
1080 * the most accurate one shaders can get.
1082 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1084 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
1085 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
1086 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
1088 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
1089 cb_shader_mask
= si_get_cb_shader_mask(spi_shader_col_format
);
1091 /* Ensure that some export memory is always allocated, for two reasons:
1093 * 1) Correctness: The hardware ignores the EXEC mask if no export
1094 * memory is allocated, so KILL and alpha test do not work correctly
1096 * 2) Performance: Every shader needs at least a NULL export, even when
1097 * it writes no color/depth output. The NULL export instruction
1098 * stalls without this setting.
1100 * Don't add this to CB_SHADER_MASK.
1102 if (!spi_shader_col_format
&&
1103 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
1104 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
1106 si_pm4_set_reg(pm4
, R_0286CC_SPI_PS_INPUT_ENA
, input_ena
);
1107 si_pm4_set_reg(pm4
, R_0286D0_SPI_PS_INPUT_ADDR
,
1108 shader
->config
.spi_ps_input_addr
);
1110 /* Set interpolation controls. */
1111 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
));
1113 /* Set registers. */
1114 si_pm4_set_reg(pm4
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
1115 si_pm4_set_reg(pm4
, R_0286D8_SPI_PS_IN_CONTROL
, spi_ps_in_control
);
1117 si_pm4_set_reg(pm4
, R_028710_SPI_SHADER_Z_FORMAT
,
1118 si_get_spi_shader_z_format(info
->writes_z
,
1119 info
->writes_stencil
,
1120 info
->writes_samplemask
));
1122 si_pm4_set_reg(pm4
, R_028714_SPI_SHADER_COL_FORMAT
, spi_shader_col_format
);
1123 si_pm4_set_reg(pm4
, R_02823C_CB_SHADER_MASK
, cb_shader_mask
);
1125 va
= shader
->bo
->gpu_address
;
1126 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1127 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
1128 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, va
>> 40);
1130 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
,
1131 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1132 S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
1133 S_00B028_DX10_CLAMP(1) |
1134 S_00B028_FLOAT_MODE(shader
->config
.float_mode
));
1135 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
1136 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
1137 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
1138 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1141 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
1142 struct si_shader
*shader
)
1144 switch (shader
->selector
->type
) {
1145 case PIPE_SHADER_VERTEX
:
1146 if (shader
->key
.as_ls
)
1147 si_shader_ls(sscreen
, shader
);
1148 else if (shader
->key
.as_es
)
1149 si_shader_es(sscreen
, shader
);
1151 si_shader_vs(sscreen
, shader
, NULL
);
1153 case PIPE_SHADER_TESS_CTRL
:
1154 si_shader_hs(sscreen
, shader
);
1156 case PIPE_SHADER_TESS_EVAL
:
1157 if (shader
->key
.as_es
)
1158 si_shader_es(sscreen
, shader
);
1160 si_shader_vs(sscreen
, shader
, NULL
);
1162 case PIPE_SHADER_GEOMETRY
:
1163 si_shader_gs(sscreen
, shader
);
1165 case PIPE_SHADER_FRAGMENT
:
1166 si_shader_ps(shader
);
1173 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
1175 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1176 if (sctx
->queued
.named
.dsa
)
1177 return sctx
->queued
.named
.dsa
->alpha_func
;
1179 return PIPE_FUNC_ALWAYS
;
1182 static void si_shader_selector_key_vs(struct si_context
*sctx
,
1183 struct si_shader_selector
*vs
,
1184 struct si_shader_key
*key
,
1185 struct si_vs_prolog_bits
*prolog_key
)
1187 if (!sctx
->vertex_elements
)
1190 prolog_key
->instance_divisor_is_one
=
1191 sctx
->vertex_elements
->instance_divisor_is_one
;
1192 prolog_key
->instance_divisor_is_fetched
=
1193 sctx
->vertex_elements
->instance_divisor_is_fetched
;
1195 /* Prefer a monolithic shader to allow scheduling divisions around
1197 if (prolog_key
->instance_divisor_is_fetched
)
1198 key
->opt
.prefer_mono
= 1;
1200 unsigned count
= MIN2(vs
->info
.num_inputs
,
1201 sctx
->vertex_elements
->count
);
1202 memcpy(key
->mono
.vs_fix_fetch
, sctx
->vertex_elements
->fix_fetch
, count
);
1205 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
,
1206 struct si_shader_selector
*vs
,
1207 struct si_shader_key
*key
)
1209 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1211 key
->opt
.clip_disable
=
1212 sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
1213 (vs
->info
.clipdist_writemask
||
1214 vs
->info
.writes_clipvertex
) &&
1215 !vs
->info
.culldist_writemask
;
1217 /* Find out if PS is disabled. */
1218 bool ps_disabled
= true;
1220 bool ps_modifies_zs
= ps
->info
.uses_kill
||
1221 ps
->info
.writes_z
||
1222 ps
->info
.writes_stencil
||
1223 ps
->info
.writes_samplemask
||
1224 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
1226 unsigned ps_colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
&
1227 sctx
->queued
.named
.blend
->cb_target_mask
;
1228 if (!ps
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
])
1229 ps_colormask
&= ps
->colors_written_4bit
;
1231 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
1234 !ps
->info
.writes_memory
);
1237 /* Find out which VS outputs aren't used by the PS. */
1238 uint64_t outputs_written
= vs
->outputs_written
;
1239 uint64_t inputs_read
= 0;
1241 /* ignore POSITION, PSIZE */
1242 outputs_written
&= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION
, 0) |
1243 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE
, 0))));
1246 inputs_read
= ps
->inputs_read
;
1249 uint64_t linked
= outputs_written
& inputs_read
;
1251 key
->opt
.kill_outputs
= ~linked
& outputs_written
;
1254 /* Compute the key for the hw shader variant */
1255 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
1256 struct si_shader_selector
*sel
,
1257 struct si_shader_key
*key
)
1259 struct si_context
*sctx
= (struct si_context
*)ctx
;
1261 memset(key
, 0, sizeof(*key
));
1263 switch (sel
->type
) {
1264 case PIPE_SHADER_VERTEX
:
1265 si_shader_selector_key_vs(sctx
, sel
, key
, &key
->part
.vs
.prolog
);
1267 if (sctx
->tes_shader
.cso
)
1269 else if (sctx
->gs_shader
.cso
)
1272 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1274 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1275 key
->mono
.u
.vs_export_prim_id
= 1;
1278 case PIPE_SHADER_TESS_CTRL
:
1279 if (sctx
->b
.chip_class
>= GFX9
) {
1280 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1281 key
, &key
->part
.tcs
.ls_prolog
);
1282 key
->part
.tcs
.ls
= sctx
->vs_shader
.cso
;
1285 key
->part
.tcs
.epilog
.prim_mode
=
1286 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1287 key
->part
.tcs
.epilog
.tes_reads_tess_factors
=
1288 sctx
->tes_shader
.cso
->info
.reads_tess_factors
;
1290 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
1291 key
->mono
.u
.ff_tcs_inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
1293 case PIPE_SHADER_TESS_EVAL
:
1294 if (sctx
->gs_shader
.cso
)
1297 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1299 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1300 key
->mono
.u
.vs_export_prim_id
= 1;
1303 case PIPE_SHADER_GEOMETRY
:
1304 if (sctx
->b
.chip_class
>= GFX9
) {
1305 if (sctx
->tes_shader
.cso
) {
1306 key
->part
.gs
.es
= sctx
->tes_shader
.cso
;
1308 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1309 key
, &key
->part
.gs
.vs_prolog
);
1310 key
->part
.gs
.es
= sctx
->vs_shader
.cso
;
1313 /* Merged ES-GS can have unbalanced wave usage.
1315 * ES threads are per-vertex, while GS threads are
1316 * per-primitive. So without any amplification, there
1317 * are fewer GS threads than ES threads, which can result
1318 * in empty (no-op) GS waves. With too much amplification,
1319 * there are more GS threads than ES threads, which
1320 * can result in empty (no-op) ES waves.
1322 * Non-monolithic shaders are implemented by setting EXEC
1323 * at the beginning of shader parts, and don't jump to
1324 * the end if EXEC is 0.
1326 * Monolithic shaders use conditional blocks, so they can
1327 * jump and skip empty waves of ES or GS. So set this to
1328 * always use optimized variants, which are monolithic.
1330 key
->opt
.prefer_mono
= 1;
1332 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
1334 case PIPE_SHADER_FRAGMENT
: {
1335 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1336 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1338 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
1339 sel
->info
.colors_written
== 0x1)
1340 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
1343 /* Select the shader color format based on whether
1344 * blending or alpha are needed.
1346 key
->part
.ps
.epilog
.spi_shader_col_format
=
1347 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1348 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
1349 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1350 sctx
->framebuffer
.spi_shader_col_format_blend
) |
1351 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1352 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
1353 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1354 sctx
->framebuffer
.spi_shader_col_format
);
1356 /* The output for dual source blending should have
1357 * the same format as the first output.
1359 if (blend
->dual_src_blend
)
1360 key
->part
.ps
.epilog
.spi_shader_col_format
|=
1361 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
1363 key
->part
.ps
.epilog
.spi_shader_col_format
= sctx
->framebuffer
.spi_shader_col_format
;
1365 /* If alpha-to-coverage is enabled, we have to export alpha
1366 * even if there is no color buffer.
1368 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) &&
1369 blend
&& blend
->alpha_to_coverage
)
1370 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
1372 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1373 * to the range supported by the type if a channel has less
1374 * than 16 bits and the export format is 16_ABGR.
1376 if (sctx
->b
.chip_class
<= CIK
&& sctx
->b
.family
!= CHIP_HAWAII
) {
1377 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
1378 key
->part
.ps
.epilog
.color_is_int10
= sctx
->framebuffer
.color_is_int10
;
1381 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1382 if (!key
->part
.ps
.epilog
.last_cbuf
) {
1383 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
1384 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
1385 key
->part
.ps
.epilog
.color_is_int10
&= sel
->info
.colors_written
;
1389 bool is_poly
= (sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES
&&
1390 sctx
->current_rast_prim
<= PIPE_PRIM_POLYGON
) ||
1391 sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES_ADJACENCY
;
1392 bool is_line
= !is_poly
&& sctx
->current_rast_prim
!= PIPE_PRIM_POINTS
;
1394 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
1395 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
1397 if (sctx
->queued
.named
.blend
) {
1398 key
->part
.ps
.epilog
.alpha_to_one
= sctx
->queued
.named
.blend
->alpha_to_one
&&
1399 rs
->multisample_enable
;
1402 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
1403 key
->part
.ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
1404 (is_line
&& rs
->line_smooth
)) &&
1405 sctx
->framebuffer
.nr_samples
<= 1;
1406 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
1408 if (rs
->force_persample_interp
&&
1409 rs
->multisample_enable
&&
1410 sctx
->framebuffer
.nr_samples
> 1 &&
1411 sctx
->ps_iter_samples
> 1) {
1412 key
->part
.ps
.prolog
.force_persp_sample_interp
=
1413 sel
->info
.uses_persp_center
||
1414 sel
->info
.uses_persp_centroid
;
1416 key
->part
.ps
.prolog
.force_linear_sample_interp
=
1417 sel
->info
.uses_linear_center
||
1418 sel
->info
.uses_linear_centroid
;
1419 } else if (rs
->multisample_enable
&&
1420 sctx
->framebuffer
.nr_samples
> 1) {
1421 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
1422 sel
->info
.uses_persp_center
&&
1423 sel
->info
.uses_persp_centroid
;
1424 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
1425 sel
->info
.uses_linear_center
&&
1426 sel
->info
.uses_linear_centroid
;
1428 /* Make sure SPI doesn't compute more than 1 pair
1429 * of (i,j), which is the optimization here. */
1430 key
->part
.ps
.prolog
.force_persp_center_interp
=
1431 sel
->info
.uses_persp_center
+
1432 sel
->info
.uses_persp_centroid
+
1433 sel
->info
.uses_persp_sample
> 1;
1435 key
->part
.ps
.prolog
.force_linear_center_interp
=
1436 sel
->info
.uses_linear_center
+
1437 sel
->info
.uses_linear_centroid
+
1438 sel
->info
.uses_linear_sample
> 1;
1442 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
1449 if (unlikely(sctx
->screen
->b
.debug_flags
& DBG_NO_OPT_VARIANT
))
1450 memset(&key
->opt
, 0, sizeof(key
->opt
));
1453 static void si_build_shader_variant(struct si_shader
*shader
,
1457 struct si_shader_selector
*sel
= shader
->selector
;
1458 struct si_screen
*sscreen
= sel
->screen
;
1459 LLVMTargetMachineRef tm
;
1460 struct pipe_debug_callback
*debug
= &shader
->compiler_ctx_state
.debug
;
1463 if (thread_index
>= 0) {
1465 assert(thread_index
< ARRAY_SIZE(sscreen
->tm_low_priority
));
1466 tm
= sscreen
->tm_low_priority
[thread_index
];
1468 assert(thread_index
< ARRAY_SIZE(sscreen
->tm
));
1469 tm
= sscreen
->tm
[thread_index
];
1474 assert(!low_priority
);
1475 tm
= shader
->compiler_ctx_state
.tm
;
1478 r
= si_shader_create(sscreen
, tm
, shader
, debug
);
1480 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1482 shader
->compilation_failed
= true;
1486 if (shader
->compiler_ctx_state
.is_debug_context
) {
1487 FILE *f
= open_memstream(&shader
->shader_log
,
1488 &shader
->shader_log_size
);
1490 si_shader_dump(sscreen
, shader
, NULL
, sel
->type
, f
, false);
1495 si_shader_init_pm4_state(sscreen
, shader
);
1498 static void si_build_shader_variant_low_priority(void *job
, int thread_index
)
1500 struct si_shader
*shader
= (struct si_shader
*)job
;
1502 assert(thread_index
>= 0);
1504 si_build_shader_variant(shader
, thread_index
, true);
1507 static const struct si_shader_key zeroed
;
1509 static bool si_check_missing_main_part(struct si_screen
*sscreen
,
1510 struct si_shader_selector
*sel
,
1511 struct si_compiler_ctx_state
*compiler_state
,
1512 struct si_shader_key
*key
)
1514 struct si_shader
**mainp
= si_get_main_shader_part(sel
, key
);
1517 struct si_shader
*main_part
= CALLOC_STRUCT(si_shader
);
1522 main_part
->selector
= sel
;
1523 main_part
->key
.as_es
= key
->as_es
;
1524 main_part
->key
.as_ls
= key
->as_ls
;
1526 if (si_compile_tgsi_shader(sscreen
, compiler_state
->tm
,
1528 &compiler_state
->debug
) != 0) {
1537 static void si_destroy_shader_selector(struct si_context
*sctx
,
1538 struct si_shader_selector
*sel
);
1540 static void si_shader_selector_reference(struct si_context
*sctx
,
1541 struct si_shader_selector
**dst
,
1542 struct si_shader_selector
*src
)
1544 if (pipe_reference(&(*dst
)->reference
, &src
->reference
))
1545 si_destroy_shader_selector(sctx
, *dst
);
1550 /* Select the hw shader variant depending on the current state. */
1551 static int si_shader_select_with_key(struct si_screen
*sscreen
,
1552 struct si_shader_ctx_state
*state
,
1553 struct si_compiler_ctx_state
*compiler_state
,
1554 struct si_shader_key
*key
,
1557 struct si_shader_selector
*sel
= state
->cso
;
1558 struct si_shader_selector
*previous_stage_sel
= NULL
;
1559 struct si_shader
*current
= state
->current
;
1560 struct si_shader
*iter
, *shader
= NULL
;
1563 /* Check if we don't need to change anything.
1564 * This path is also used for most shaders that don't need multiple
1565 * variants, it will cost just a computation of the key and this
1567 if (likely(current
&&
1568 memcmp(¤t
->key
, key
, sizeof(*key
)) == 0 &&
1569 (!current
->is_optimized
||
1570 util_queue_fence_is_signalled(¤t
->optimized_ready
))))
1571 return current
->compilation_failed
? -1 : 0;
1573 /* This must be done before the mutex is locked, because async GS
1574 * compilation calls this function too, and therefore must enter
1577 * Only wait if we are in a draw call. Don't wait if we are
1578 * in a compiler thread.
1580 if (thread_index
< 0)
1581 util_queue_fence_wait(&sel
->ready
);
1583 mtx_lock(&sel
->mutex
);
1585 /* Find the shader variant. */
1586 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
1587 /* Don't check the "current" shader. We checked it above. */
1588 if (current
!= iter
&&
1589 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
1590 /* If it's an optimized shader and its compilation has
1591 * been started but isn't done, use the unoptimized
1592 * shader so as not to cause a stall due to compilation.
1594 if (iter
->is_optimized
&&
1595 !util_queue_fence_is_signalled(&iter
->optimized_ready
)) {
1596 memset(&key
->opt
, 0, sizeof(key
->opt
));
1597 mtx_unlock(&sel
->mutex
);
1601 if (iter
->compilation_failed
) {
1602 mtx_unlock(&sel
->mutex
);
1603 return -1; /* skip the draw call */
1606 state
->current
= iter
;
1607 mtx_unlock(&sel
->mutex
);
1612 /* Build a new shader. */
1613 shader
= CALLOC_STRUCT(si_shader
);
1615 mtx_unlock(&sel
->mutex
);
1618 shader
->selector
= sel
;
1620 shader
->compiler_ctx_state
= *compiler_state
;
1622 /* If this is a merged shader, get the first shader's selector. */
1623 if (sscreen
->b
.chip_class
>= GFX9
) {
1624 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
1625 previous_stage_sel
= key
->part
.tcs
.ls
;
1626 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
1627 previous_stage_sel
= key
->part
.gs
.es
;
1629 /* We need to wait for the previous shader. */
1630 if (previous_stage_sel
&& thread_index
< 0)
1631 util_queue_fence_wait(&previous_stage_sel
->ready
);
1634 /* Compile the main shader part if it doesn't exist. This can happen
1635 * if the initial guess was wrong. */
1636 bool is_pure_monolithic
=
1637 sscreen
->use_monolithic_shaders
||
1638 memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
1640 if (!is_pure_monolithic
) {
1643 /* Make sure the main shader part is present. This is needed
1644 * for shaders that can be compiled as VS, LS, or ES, and only
1645 * one of them is compiled at creation.
1647 * For merged shaders, check that the starting shader's main
1650 if (previous_stage_sel
) {
1651 struct si_shader_key shader1_key
= zeroed
;
1653 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
1654 shader1_key
.as_ls
= 1;
1655 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
1656 shader1_key
.as_es
= 1;
1660 mtx_lock(&previous_stage_sel
->mutex
);
1661 ok
= si_check_missing_main_part(sscreen
,
1663 compiler_state
, &shader1_key
);
1664 mtx_unlock(&previous_stage_sel
->mutex
);
1666 ok
= si_check_missing_main_part(sscreen
, sel
,
1667 compiler_state
, key
);
1671 mtx_unlock(&sel
->mutex
);
1672 return -ENOMEM
; /* skip the draw call */
1676 /* Keep the reference to the 1st shader of merged shaders, so that
1677 * Gallium can't destroy it before we destroy the 2nd shader.
1679 * Set sctx = NULL, because it's unused if we're not releasing
1680 * the shader, and we don't have any sctx here.
1682 si_shader_selector_reference(NULL
, &shader
->previous_stage_sel
,
1683 previous_stage_sel
);
1685 /* Monolithic-only shaders don't make a distinction between optimized
1686 * and unoptimized. */
1687 shader
->is_monolithic
=
1688 is_pure_monolithic
||
1689 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1691 shader
->is_optimized
=
1692 !is_pure_monolithic
&&
1693 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1694 if (shader
->is_optimized
)
1695 util_queue_fence_init(&shader
->optimized_ready
);
1697 if (!sel
->last_variant
) {
1698 sel
->first_variant
= shader
;
1699 sel
->last_variant
= shader
;
1701 sel
->last_variant
->next_variant
= shader
;
1702 sel
->last_variant
= shader
;
1705 /* If it's an optimized shader, compile it asynchronously. */
1706 if (shader
->is_optimized
&&
1707 !is_pure_monolithic
&&
1709 /* Compile it asynchronously. */
1710 util_queue_add_job(&sscreen
->shader_compiler_queue_low_priority
,
1711 shader
, &shader
->optimized_ready
,
1712 si_build_shader_variant_low_priority
, NULL
);
1714 /* Use the default (unoptimized) shader for now. */
1715 memset(&key
->opt
, 0, sizeof(key
->opt
));
1716 mtx_unlock(&sel
->mutex
);
1720 assert(!shader
->is_optimized
);
1721 si_build_shader_variant(shader
, thread_index
, false);
1723 if (!shader
->compilation_failed
)
1724 state
->current
= shader
;
1726 mtx_unlock(&sel
->mutex
);
1727 return shader
->compilation_failed
? -1 : 0;
1730 static int si_shader_select(struct pipe_context
*ctx
,
1731 struct si_shader_ctx_state
*state
,
1732 struct si_compiler_ctx_state
*compiler_state
)
1734 struct si_context
*sctx
= (struct si_context
*)ctx
;
1735 struct si_shader_key key
;
1737 si_shader_selector_key(ctx
, state
->cso
, &key
);
1738 return si_shader_select_with_key(sctx
->screen
, state
, compiler_state
,
1742 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
1743 struct si_shader_key
*key
)
1745 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
1747 switch (info
->processor
) {
1748 case PIPE_SHADER_VERTEX
:
1749 switch (next_shader
) {
1750 case PIPE_SHADER_GEOMETRY
:
1753 case PIPE_SHADER_TESS_CTRL
:
1754 case PIPE_SHADER_TESS_EVAL
:
1758 /* If POSITION isn't written, it can't be a HW VS.
1759 * Assume that it's a HW LS. (the next shader is TCS)
1760 * This heuristic is needed for separate shader objects.
1762 if (!info
->writes_position
)
1767 case PIPE_SHADER_TESS_EVAL
:
1768 if (next_shader
== PIPE_SHADER_GEOMETRY
||
1769 !info
->writes_position
)
1776 * Compile the main shader part or the monolithic shader as part of
1777 * si_shader_selector initialization. Since it can be done asynchronously,
1778 * there is no way to report compile failures to applications.
1780 void si_init_shader_selector_async(void *job
, int thread_index
)
1782 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
1783 struct si_screen
*sscreen
= sel
->screen
;
1784 LLVMTargetMachineRef tm
;
1785 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
1788 if (thread_index
>= 0) {
1789 assert(thread_index
< ARRAY_SIZE(sscreen
->tm
));
1790 tm
= sscreen
->tm
[thread_index
];
1794 tm
= sel
->compiler_ctx_state
.tm
;
1797 /* Compile the main shader part for use with a prolog and/or epilog.
1798 * If this fails, the driver will try to compile a monolithic shader
1801 if (!sscreen
->use_monolithic_shaders
) {
1802 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
1806 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
1810 shader
->selector
= sel
;
1811 si_parse_next_shader_property(&sel
->info
, &shader
->key
);
1813 tgsi_binary
= si_get_tgsi_binary(sel
);
1815 /* Try to load the shader from the shader cache. */
1816 mtx_lock(&sscreen
->shader_cache_mutex
);
1819 si_shader_cache_load_shader(sscreen
, tgsi_binary
, shader
)) {
1820 mtx_unlock(&sscreen
->shader_cache_mutex
);
1822 mtx_unlock(&sscreen
->shader_cache_mutex
);
1824 /* Compile the shader if it hasn't been loaded from the cache. */
1825 if (si_compile_tgsi_shader(sscreen
, tm
, shader
, false,
1829 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
1834 mtx_lock(&sscreen
->shader_cache_mutex
);
1835 if (!si_shader_cache_insert_shader(sscreen
, tgsi_binary
, shader
, true))
1837 mtx_unlock(&sscreen
->shader_cache_mutex
);
1841 *si_get_main_shader_part(sel
, &shader
->key
) = shader
;
1843 /* Unset "outputs_written" flags for outputs converted to
1844 * DEFAULT_VAL, so that later inter-shader optimizations don't
1845 * try to eliminate outputs that don't exist in the final
1848 * This is only done if non-monolithic shaders are enabled.
1850 if ((sel
->type
== PIPE_SHADER_VERTEX
||
1851 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
1852 !shader
->key
.as_ls
&&
1853 !shader
->key
.as_es
) {
1856 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
1857 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
1859 if (offset
<= AC_EXP_PARAM_OFFSET_31
)
1862 unsigned name
= sel
->info
.output_semantic_name
[i
];
1863 unsigned index
= sel
->info
.output_semantic_index
[i
];
1867 case TGSI_SEMANTIC_GENERIC
:
1868 /* don't process indices the function can't handle */
1869 if (index
>= SI_MAX_IO_GENERIC
)
1873 id
= si_shader_io_get_unique_index(name
, index
);
1874 sel
->outputs_written
&= ~(1ull << id
);
1876 case TGSI_SEMANTIC_POSITION
: /* ignore these */
1877 case TGSI_SEMANTIC_PSIZE
:
1878 case TGSI_SEMANTIC_CLIPVERTEX
:
1879 case TGSI_SEMANTIC_EDGEFLAG
:
1886 /* Pre-compilation. */
1887 if (sscreen
->b
.debug_flags
& DBG_PRECOMPILE
) {
1888 struct si_shader_ctx_state state
= {sel
};
1889 struct si_shader_key key
;
1891 memset(&key
, 0, sizeof(key
));
1892 si_parse_next_shader_property(&sel
->info
, &key
);
1894 /* Set reasonable defaults, so that the shader key doesn't
1895 * cause any code to be eliminated.
1897 switch (sel
->type
) {
1898 case PIPE_SHADER_TESS_CTRL
:
1899 key
.part
.tcs
.epilog
.prim_mode
= PIPE_PRIM_TRIANGLES
;
1901 case PIPE_SHADER_FRAGMENT
:
1902 key
.part
.ps
.prolog
.bc_optimize_for_persp
=
1903 sel
->info
.uses_persp_center
&&
1904 sel
->info
.uses_persp_centroid
;
1905 key
.part
.ps
.prolog
.bc_optimize_for_linear
=
1906 sel
->info
.uses_linear_center
&&
1907 sel
->info
.uses_linear_centroid
;
1908 key
.part
.ps
.epilog
.alpha_func
= PIPE_FUNC_ALWAYS
;
1909 for (i
= 0; i
< 8; i
++)
1910 if (sel
->info
.colors_written
& (1 << i
))
1911 key
.part
.ps
.epilog
.spi_shader_col_format
|=
1912 V_028710_SPI_SHADER_FP16_ABGR
<< (i
* 4);
1916 if (si_shader_select_with_key(sscreen
, &state
,
1917 &sel
->compiler_ctx_state
, &key
,
1919 fprintf(stderr
, "radeonsi: can't create a monolithic shader\n");
1922 /* The GS copy shader is always pre-compiled. */
1923 if (sel
->type
== PIPE_SHADER_GEOMETRY
) {
1924 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, tm
, sel
, debug
);
1925 if (!sel
->gs_copy_shader
) {
1926 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
1930 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
1934 /* Return descriptor slot usage masks from the given shader info. */
1935 void si_get_active_slot_masks(const struct tgsi_shader_info
*info
,
1936 uint32_t *const_and_shader_buffers
,
1937 uint64_t *samplers_and_images
)
1939 unsigned start
, num_shaderbufs
, num_constbufs
, num_images
, num_samplers
;
1941 num_shaderbufs
= util_last_bit(info
->shader_buffers_declared
);
1942 num_constbufs
= util_last_bit(info
->const_buffers_declared
);
1943 /* two 8-byte images share one 16-byte slot */
1944 num_images
= align(util_last_bit(info
->images_declared
), 2);
1945 num_samplers
= util_last_bit(info
->samplers_declared
);
1947 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
1948 start
= si_get_shaderbuf_slot(num_shaderbufs
- 1);
1949 *const_and_shader_buffers
=
1950 u_bit_consecutive(start
, num_shaderbufs
+ num_constbufs
);
1952 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
1953 start
= si_get_image_slot(num_images
- 1) / 2;
1954 *samplers_and_images
=
1955 u_bit_consecutive64(start
, num_images
/ 2 + num_samplers
);
1958 static void *si_create_shader_selector(struct pipe_context
*ctx
,
1959 const struct pipe_shader_state
*state
)
1961 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
1962 struct si_context
*sctx
= (struct si_context
*)ctx
;
1963 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
1969 pipe_reference_init(&sel
->reference
, 1);
1970 sel
->screen
= sscreen
;
1971 sel
->compiler_ctx_state
.tm
= sctx
->tm
;
1972 sel
->compiler_ctx_state
.debug
= sctx
->b
.debug
;
1973 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
1974 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
1980 sel
->so
= state
->stream_output
;
1981 tgsi_scan_shader(state
->tokens
, &sel
->info
);
1982 sel
->type
= sel
->info
.processor
;
1983 p_atomic_inc(&sscreen
->b
.num_shaders_created
);
1984 si_get_active_slot_masks(&sel
->info
,
1985 &sel
->active_const_and_shader_buffers
,
1986 &sel
->active_samplers_and_images
);
1988 /* Record which streamout buffers are enabled. */
1989 for (i
= 0; i
< sel
->so
.num_outputs
; i
++) {
1990 sel
->enabled_streamout_buffer_mask
|=
1991 (1 << sel
->so
.output
[i
].output_buffer
) <<
1992 (sel
->so
.output
[i
].stream
* 4);
1995 /* The prolog is a no-op if there are no inputs. */
1996 sel
->vs_needs_prolog
= sel
->type
== PIPE_SHADER_VERTEX
&&
1997 sel
->info
.num_inputs
;
1999 /* Set which opcode uses which (i,j) pair. */
2000 if (sel
->info
.uses_persp_opcode_interp_centroid
)
2001 sel
->info
.uses_persp_centroid
= true;
2003 if (sel
->info
.uses_linear_opcode_interp_centroid
)
2004 sel
->info
.uses_linear_centroid
= true;
2006 if (sel
->info
.uses_persp_opcode_interp_offset
||
2007 sel
->info
.uses_persp_opcode_interp_sample
)
2008 sel
->info
.uses_persp_center
= true;
2010 if (sel
->info
.uses_linear_opcode_interp_offset
||
2011 sel
->info
.uses_linear_opcode_interp_sample
)
2012 sel
->info
.uses_linear_center
= true;
2014 switch (sel
->type
) {
2015 case PIPE_SHADER_GEOMETRY
:
2016 sel
->gs_output_prim
=
2017 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
2018 sel
->gs_max_out_vertices
=
2019 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
2020 sel
->gs_num_invocations
=
2021 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
2022 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
2023 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
2024 sel
->gs_max_out_vertices
;
2026 sel
->max_gs_stream
= 0;
2027 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
2028 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
2029 sel
->so
.output
[i
].stream
);
2031 sel
->gs_input_verts_per_prim
=
2032 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
2035 case PIPE_SHADER_TESS_CTRL
:
2036 /* Always reserve space for these. */
2037 sel
->patch_outputs_written
|=
2038 (1llu << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0)) |
2039 (1llu << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0));
2041 case PIPE_SHADER_VERTEX
:
2042 case PIPE_SHADER_TESS_EVAL
:
2043 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2044 unsigned name
= sel
->info
.output_semantic_name
[i
];
2045 unsigned index
= sel
->info
.output_semantic_index
[i
];
2048 case TGSI_SEMANTIC_TESSINNER
:
2049 case TGSI_SEMANTIC_TESSOUTER
:
2050 case TGSI_SEMANTIC_PATCH
:
2051 sel
->patch_outputs_written
|=
2052 1llu << si_shader_io_get_unique_index_patch(name
, index
);
2055 case TGSI_SEMANTIC_GENERIC
:
2056 /* don't process indices the function can't handle */
2057 if (index
>= SI_MAX_IO_GENERIC
)
2061 sel
->outputs_written
|=
2062 1llu << si_shader_io_get_unique_index(name
, index
);
2064 case TGSI_SEMANTIC_CLIPVERTEX
: /* ignore these */
2065 case TGSI_SEMANTIC_EDGEFLAG
:
2069 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
2071 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2072 * conflicts, i.e. each vertex will start at a different bank.
2074 if (sctx
->b
.chip_class
>= GFX9
)
2075 sel
->esgs_itemsize
+= 4;
2078 case PIPE_SHADER_FRAGMENT
:
2079 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2080 unsigned name
= sel
->info
.input_semantic_name
[i
];
2081 unsigned index
= sel
->info
.input_semantic_index
[i
];
2084 case TGSI_SEMANTIC_GENERIC
:
2085 /* don't process indices the function can't handle */
2086 if (index
>= SI_MAX_IO_GENERIC
)
2091 1llu << si_shader_io_get_unique_index(name
, index
);
2093 case TGSI_SEMANTIC_PCOORD
: /* ignore this */
2098 for (i
= 0; i
< 8; i
++)
2099 if (sel
->info
.colors_written
& (1 << i
))
2100 sel
->colors_written_4bit
|= 0xf << (4 * i
);
2102 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2103 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
2104 int index
= sel
->info
.input_semantic_index
[i
];
2105 sel
->color_attr_index
[index
] = i
;
2111 /* PA_CL_VS_OUT_CNTL */
2113 sel
->info
.writes_psize
|| sel
->info
.writes_edgeflag
||
2114 sel
->info
.writes_layer
|| sel
->info
.writes_viewport_index
;
2115 sel
->pa_cl_vs_out_cntl
=
2116 S_02881C_USE_VTX_POINT_SIZE(sel
->info
.writes_psize
) |
2117 S_02881C_USE_VTX_EDGE_FLAG(sel
->info
.writes_edgeflag
) |
2118 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel
->info
.writes_layer
) |
2119 S_02881C_USE_VTX_VIEWPORT_INDX(sel
->info
.writes_viewport_index
) |
2120 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
2121 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
);
2122 sel
->clipdist_mask
= sel
->info
.writes_clipvertex
?
2123 SIX_BITS
: sel
->info
.clipdist_writemask
;
2124 sel
->culldist_mask
= sel
->info
.culldist_writemask
<<
2125 sel
->info
.num_written_clipdistance
;
2127 /* DB_SHADER_CONTROL */
2128 sel
->db_shader_control
=
2129 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
2130 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
2131 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
2132 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
2134 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
2135 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2136 sel
->db_shader_control
|=
2137 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2139 case TGSI_FS_DEPTH_LAYOUT_LESS
:
2140 sel
->db_shader_control
|=
2141 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2145 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2147 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2148 * --|-----------|------------|------------|--------------------|-------------------|-------------
2149 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2150 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2151 * 2 | false | true | n/a | LateZ | 1 | 0
2152 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2153 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2155 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2156 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2158 * Don't use ReZ without profiling !!!
2160 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2163 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
2165 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
2166 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
2167 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
2168 } else if (sel
->info
.writes_memory
) {
2170 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) |
2171 S_02880C_EXEC_ON_HIER_FAIL(1);
2174 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2177 (void) mtx_init(&sel
->mutex
, mtx_plain
);
2178 util_queue_fence_init(&sel
->ready
);
2180 if ((sctx
->b
.debug
.debug_message
&& !sctx
->b
.debug
.async
) ||
2182 r600_can_dump_shader(&sscreen
->b
, sel
->info
.processor
))
2183 si_init_shader_selector_async(sel
, -1);
2185 util_queue_add_job(&sscreen
->shader_compiler_queue
, sel
,
2186 &sel
->ready
, si_init_shader_selector_async
,
2192 static void si_update_streamout_state(struct si_context
*sctx
)
2194 struct si_shader_selector
*shader_with_so
= si_get_vs(sctx
)->cso
;
2196 if (!shader_with_so
)
2199 sctx
->b
.streamout
.enabled_stream_buffers_mask
=
2200 shader_with_so
->enabled_streamout_buffer_mask
;
2201 sctx
->b
.streamout
.stride_in_dw
= shader_with_so
->so
.stride
;
2204 static void si_update_clip_regs(struct si_context
*sctx
,
2205 struct si_shader_selector
*old_hw_vs
,
2206 struct si_shader
*old_hw_vs_variant
,
2207 struct si_shader_selector
*next_hw_vs
,
2208 struct si_shader
*next_hw_vs_variant
)
2212 old_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] !=
2213 next_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] ||
2214 old_hw_vs
->pa_cl_vs_out_cntl
!= next_hw_vs
->pa_cl_vs_out_cntl
||
2215 old_hw_vs
->clipdist_mask
!= next_hw_vs
->clipdist_mask
||
2216 old_hw_vs
->culldist_mask
!= next_hw_vs
->culldist_mask
||
2217 !old_hw_vs_variant
||
2218 !next_hw_vs_variant
||
2219 old_hw_vs_variant
->key
.opt
.clip_disable
!=
2220 next_hw_vs_variant
->key
.opt
.clip_disable
))
2221 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
2224 static void si_update_common_shader_state(struct si_context
*sctx
)
2226 sctx
->uses_bindless_samplers
=
2227 si_shader_uses_bindless_samplers(sctx
->vs_shader
.cso
) ||
2228 si_shader_uses_bindless_samplers(sctx
->gs_shader
.cso
) ||
2229 si_shader_uses_bindless_samplers(sctx
->ps_shader
.cso
) ||
2230 si_shader_uses_bindless_samplers(sctx
->tcs_shader
.cso
) ||
2231 si_shader_uses_bindless_samplers(sctx
->tes_shader
.cso
);
2232 sctx
->uses_bindless_images
=
2233 si_shader_uses_bindless_images(sctx
->vs_shader
.cso
) ||
2234 si_shader_uses_bindless_images(sctx
->gs_shader
.cso
) ||
2235 si_shader_uses_bindless_images(sctx
->ps_shader
.cso
) ||
2236 si_shader_uses_bindless_images(sctx
->tcs_shader
.cso
) ||
2237 si_shader_uses_bindless_images(sctx
->tes_shader
.cso
);
2238 sctx
->do_update_shaders
= true;
2241 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
2243 struct si_context
*sctx
= (struct si_context
*)ctx
;
2244 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2245 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2246 struct si_shader_selector
*sel
= state
;
2248 if (sctx
->vs_shader
.cso
== sel
)
2251 sctx
->vs_shader
.cso
= sel
;
2252 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2254 si_update_common_shader_state(sctx
);
2255 r600_update_vs_writes_viewport_index(&sctx
->b
, si_get_vs_info(sctx
));
2256 si_set_active_descriptors_for_shader(sctx
, sel
);
2257 si_update_streamout_state(sctx
);
2258 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2259 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2262 static void si_update_tess_uses_prim_id(struct si_context
*sctx
)
2264 sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
=
2265 (sctx
->tes_shader
.cso
&&
2266 sctx
->tes_shader
.cso
->info
.uses_primid
) ||
2267 (sctx
->tcs_shader
.cso
&&
2268 sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
2269 (sctx
->gs_shader
.cso
&&
2270 sctx
->gs_shader
.cso
->info
.uses_primid
) ||
2271 (sctx
->ps_shader
.cso
&& !sctx
->gs_shader
.cso
&&
2272 sctx
->ps_shader
.cso
->info
.uses_primid
);
2275 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
2277 struct si_context
*sctx
= (struct si_context
*)ctx
;
2278 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2279 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2280 struct si_shader_selector
*sel
= state
;
2281 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
2283 if (sctx
->gs_shader
.cso
== sel
)
2286 sctx
->gs_shader
.cso
= sel
;
2287 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2288 sctx
->ia_multi_vgt_param_key
.u
.uses_gs
= sel
!= NULL
;
2290 si_update_common_shader_state(sctx
);
2291 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2293 if (enable_changed
) {
2294 si_shader_change_notify(sctx
);
2295 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2296 si_update_tess_uses_prim_id(sctx
);
2298 r600_update_vs_writes_viewport_index(&sctx
->b
, si_get_vs_info(sctx
));
2299 si_set_active_descriptors_for_shader(sctx
, sel
);
2300 si_update_streamout_state(sctx
);
2301 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2302 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2305 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
2307 struct si_context
*sctx
= (struct si_context
*)ctx
;
2308 struct si_shader_selector
*sel
= state
;
2309 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
2311 if (sctx
->tcs_shader
.cso
== sel
)
2314 sctx
->tcs_shader
.cso
= sel
;
2315 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2316 si_update_tess_uses_prim_id(sctx
);
2318 si_update_common_shader_state(sctx
);
2321 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
2323 si_set_active_descriptors_for_shader(sctx
, sel
);
2326 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
2328 struct si_context
*sctx
= (struct si_context
*)ctx
;
2329 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2330 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2331 struct si_shader_selector
*sel
= state
;
2332 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
2334 if (sctx
->tes_shader
.cso
== sel
)
2337 sctx
->tes_shader
.cso
= sel
;
2338 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
2339 sctx
->ia_multi_vgt_param_key
.u
.uses_tess
= sel
!= NULL
;
2340 si_update_tess_uses_prim_id(sctx
);
2342 si_update_common_shader_state(sctx
);
2343 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2345 if (enable_changed
) {
2346 si_shader_change_notify(sctx
);
2347 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
2349 r600_update_vs_writes_viewport_index(&sctx
->b
, si_get_vs_info(sctx
));
2350 si_set_active_descriptors_for_shader(sctx
, sel
);
2351 si_update_streamout_state(sctx
);
2352 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2353 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2356 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
2358 struct si_context
*sctx
= (struct si_context
*)ctx
;
2359 struct si_shader_selector
*old_sel
= sctx
->ps_shader
.cso
;
2360 struct si_shader_selector
*sel
= state
;
2362 /* skip if supplied shader is one already in use */
2366 sctx
->ps_shader
.cso
= sel
;
2367 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
2369 si_update_common_shader_state(sctx
);
2371 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2372 si_update_tess_uses_prim_id(sctx
);
2375 old_sel
->info
.colors_written
!= sel
->info
.colors_written
)
2376 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
2378 si_set_active_descriptors_for_shader(sctx
, sel
);
2381 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
2383 if (shader
->is_optimized
) {
2384 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue_low_priority
,
2385 &shader
->optimized_ready
);
2386 util_queue_fence_destroy(&shader
->optimized_ready
);
2390 switch (shader
->selector
->type
) {
2391 case PIPE_SHADER_VERTEX
:
2392 if (shader
->key
.as_ls
) {
2393 assert(sctx
->b
.chip_class
<= VI
);
2394 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
2395 } else if (shader
->key
.as_es
) {
2396 assert(sctx
->b
.chip_class
<= VI
);
2397 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2399 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2402 case PIPE_SHADER_TESS_CTRL
:
2403 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
2405 case PIPE_SHADER_TESS_EVAL
:
2406 if (shader
->key
.as_es
) {
2407 assert(sctx
->b
.chip_class
<= VI
);
2408 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2410 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2413 case PIPE_SHADER_GEOMETRY
:
2414 if (shader
->is_gs_copy_shader
)
2415 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2417 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
2419 case PIPE_SHADER_FRAGMENT
:
2420 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
2425 si_shader_selector_reference(sctx
, &shader
->previous_stage_sel
, NULL
);
2426 si_shader_destroy(shader
);
2430 static void si_destroy_shader_selector(struct si_context
*sctx
,
2431 struct si_shader_selector
*sel
)
2433 struct si_shader
*p
= sel
->first_variant
, *c
;
2434 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
2435 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
2436 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
2437 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
2438 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
2439 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
2442 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue
, &sel
->ready
);
2444 if (current_shader
[sel
->type
]->cso
== sel
) {
2445 current_shader
[sel
->type
]->cso
= NULL
;
2446 current_shader
[sel
->type
]->current
= NULL
;
2450 c
= p
->next_variant
;
2451 si_delete_shader(sctx
, p
);
2455 if (sel
->main_shader_part
)
2456 si_delete_shader(sctx
, sel
->main_shader_part
);
2457 if (sel
->main_shader_part_ls
)
2458 si_delete_shader(sctx
, sel
->main_shader_part_ls
);
2459 if (sel
->main_shader_part_es
)
2460 si_delete_shader(sctx
, sel
->main_shader_part_es
);
2461 if (sel
->gs_copy_shader
)
2462 si_delete_shader(sctx
, sel
->gs_copy_shader
);
2464 util_queue_fence_destroy(&sel
->ready
);
2465 mtx_destroy(&sel
->mutex
);
2470 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
2472 struct si_context
*sctx
= (struct si_context
*)ctx
;
2473 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
2475 si_shader_selector_reference(sctx
, &sel
, NULL
);
2478 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
2479 struct si_shader
*vs
, unsigned name
,
2480 unsigned index
, unsigned interpolate
)
2482 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
2483 unsigned j
, offset
, ps_input_cntl
= 0;
2485 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2486 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
))
2487 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
2489 if (name
== TGSI_SEMANTIC_PCOORD
||
2490 (name
== TGSI_SEMANTIC_TEXCOORD
&&
2491 sctx
->sprite_coord_enable
& (1 << index
))) {
2492 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
2495 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
2496 if (name
== vsinfo
->output_semantic_name
[j
] &&
2497 index
== vsinfo
->output_semantic_index
[j
]) {
2498 offset
= vs
->info
.vs_output_param_offset
[j
];
2500 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
2501 /* The input is loaded from parameter memory. */
2502 ps_input_cntl
|= S_028644_OFFSET(offset
);
2503 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2504 if (offset
== AC_EXP_PARAM_UNDEFINED
) {
2505 /* This can happen with depth-only rendering. */
2508 /* The input is a DEFAULT_VAL constant. */
2509 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
2510 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
2511 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
2514 ps_input_cntl
= S_028644_OFFSET(0x20) |
2515 S_028644_DEFAULT_VAL(offset
);
2521 if (name
== TGSI_SEMANTIC_PRIMID
)
2522 /* PrimID is written after the last output. */
2523 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
2524 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2525 /* No corresponding output found, load defaults into input.
2526 * Don't set any other bits.
2527 * (FLAT_SHADE=1 completely changes behavior) */
2528 ps_input_cntl
= S_028644_OFFSET(0x20);
2529 /* D3D 9 behaviour. GL is undefined */
2530 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
2531 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
2533 return ps_input_cntl
;
2536 static void si_emit_spi_map(struct si_context
*sctx
, struct r600_atom
*atom
)
2538 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2539 struct si_shader
*ps
= sctx
->ps_shader
.current
;
2540 struct si_shader
*vs
= si_get_vs_state(sctx
);
2541 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
2542 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
2544 if (!ps
|| !ps
->selector
->info
.num_inputs
)
2547 num_interp
= si_get_ps_num_interp(ps
);
2548 assert(num_interp
> 0);
2549 radeon_set_context_reg_seq(cs
, R_028644_SPI_PS_INPUT_CNTL_0
, num_interp
);
2551 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
2552 unsigned name
= psinfo
->input_semantic_name
[i
];
2553 unsigned index
= psinfo
->input_semantic_index
[i
];
2554 unsigned interpolate
= psinfo
->input_interpolate
[i
];
2556 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, name
, index
,
2560 if (name
== TGSI_SEMANTIC_COLOR
) {
2561 assert(index
< ARRAY_SIZE(bcol_interp
));
2562 bcol_interp
[index
] = interpolate
;
2566 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
2567 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
2569 for (i
= 0; i
< 2; i
++) {
2570 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
2573 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, bcol
,
2574 i
, bcol_interp
[i
]));
2578 assert(num_interp
== num_written
);
2582 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2584 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
2586 if (sctx
->init_config_has_vgt_flush
)
2589 /* Done by Vulkan before VGT_FLUSH. */
2590 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2591 si_pm4_cmd_add(sctx
->init_config
,
2592 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2593 si_pm4_cmd_end(sctx
->init_config
, false);
2595 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2596 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2597 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
2598 si_pm4_cmd_end(sctx
->init_config
, false);
2599 sctx
->init_config_has_vgt_flush
= true;
2602 /* Initialize state related to ESGS / GSVS ring buffers */
2603 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
2605 struct si_shader_selector
*es
=
2606 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
2607 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
2608 struct si_pm4_state
*pm4
;
2610 /* Chip constants. */
2611 unsigned num_se
= sctx
->screen
->b
.info
.max_se
;
2612 unsigned wave_size
= 64;
2613 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
2614 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2615 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2617 unsigned gs_vertex_reuse
= (sctx
->b
.chip_class
>= VI
? 32 : 16) * num_se
;
2618 unsigned alignment
= 256 * num_se
;
2619 /* The maximum size is 63.999 MB per SE. */
2620 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
2622 /* Calculate the minimum size. */
2623 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
2624 wave_size
, alignment
);
2626 /* These are recommended sizes, not minimum sizes. */
2627 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
2628 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
2629 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
2630 gs
->max_gsvs_emit_size
;
2632 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
2633 esgs_ring_size
= align(esgs_ring_size
, alignment
);
2634 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
2636 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
2637 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
2639 /* Some rings don't have to be allocated if shaders don't use them.
2640 * (e.g. no varyings between ES and GS or GS and VS)
2642 * GFX9 doesn't have the ESGS ring.
2644 bool update_esgs
= sctx
->b
.chip_class
<= VI
&&
2646 (!sctx
->esgs_ring
||
2647 sctx
->esgs_ring
->width0
< esgs_ring_size
);
2648 bool update_gsvs
= gsvs_ring_size
&&
2649 (!sctx
->gsvs_ring
||
2650 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
2652 if (!update_esgs
&& !update_gsvs
)
2656 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
2658 r600_aligned_buffer_create(sctx
->b
.b
.screen
,
2659 R600_RESOURCE_FLAG_UNMAPPABLE
,
2661 esgs_ring_size
, alignment
);
2662 if (!sctx
->esgs_ring
)
2667 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
2669 r600_aligned_buffer_create(sctx
->b
.b
.screen
,
2670 R600_RESOURCE_FLAG_UNMAPPABLE
,
2672 gsvs_ring_size
, alignment
);
2673 if (!sctx
->gsvs_ring
)
2677 /* Create the "init_config_gs_rings" state. */
2678 pm4
= CALLOC_STRUCT(si_pm4_state
);
2682 if (sctx
->b
.chip_class
>= CIK
) {
2683 if (sctx
->esgs_ring
) {
2684 assert(sctx
->b
.chip_class
<= VI
);
2685 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
2686 sctx
->esgs_ring
->width0
/ 256);
2688 if (sctx
->gsvs_ring
)
2689 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
2690 sctx
->gsvs_ring
->width0
/ 256);
2692 if (sctx
->esgs_ring
)
2693 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
2694 sctx
->esgs_ring
->width0
/ 256);
2695 if (sctx
->gsvs_ring
)
2696 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
2697 sctx
->gsvs_ring
->width0
/ 256);
2700 /* Set the state. */
2701 if (sctx
->init_config_gs_rings
)
2702 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
2703 sctx
->init_config_gs_rings
= pm4
;
2705 if (!sctx
->init_config_has_vgt_flush
) {
2706 si_init_config_add_vgt_flush(sctx
);
2707 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
2710 /* Flush the context to re-emit both init_config states. */
2711 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
2712 si_context_gfx_flush(sctx
, RADEON_FLUSH_ASYNC
, NULL
);
2714 /* Set ring bindings. */
2715 if (sctx
->esgs_ring
) {
2716 assert(sctx
->b
.chip_class
<= VI
);
2717 si_set_ring_buffer(&sctx
->b
.b
, SI_ES_RING_ESGS
,
2718 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
2719 true, true, 4, 64, 0);
2720 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_ESGS
,
2721 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
2722 false, false, 0, 0, 0);
2724 if (sctx
->gsvs_ring
) {
2725 si_set_ring_buffer(&sctx
->b
.b
, SI_RING_GSVS
,
2726 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
2727 false, false, 0, 0, 0);
2733 static void si_shader_lock(struct si_shader
*shader
)
2735 mtx_lock(&shader
->selector
->mutex
);
2736 if (shader
->previous_stage_sel
) {
2737 assert(shader
->previous_stage_sel
!= shader
->selector
);
2738 mtx_lock(&shader
->previous_stage_sel
->mutex
);
2742 static void si_shader_unlock(struct si_shader
*shader
)
2744 if (shader
->previous_stage_sel
)
2745 mtx_unlock(&shader
->previous_stage_sel
->mutex
);
2746 mtx_unlock(&shader
->selector
->mutex
);
2750 * @returns 1 if \p sel has been updated to use a new scratch buffer
2752 * < 0 if there was a failure
2754 static int si_update_scratch_buffer(struct si_context
*sctx
,
2755 struct si_shader
*shader
)
2757 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
2763 /* This shader doesn't need a scratch buffer */
2764 if (shader
->config
.scratch_bytes_per_wave
== 0)
2767 /* Prevent race conditions when updating:
2768 * - si_shader::scratch_bo
2769 * - si_shader::binary::code
2770 * - si_shader::previous_stage::binary::code.
2772 si_shader_lock(shader
);
2774 /* This shader is already configured to use the current
2775 * scratch buffer. */
2776 if (shader
->scratch_bo
== sctx
->scratch_buffer
) {
2777 si_shader_unlock(shader
);
2781 assert(sctx
->scratch_buffer
);
2783 if (shader
->previous_stage
)
2784 si_shader_apply_scratch_relocs(shader
->previous_stage
, scratch_va
);
2786 si_shader_apply_scratch_relocs(shader
, scratch_va
);
2788 /* Replace the shader bo with a new bo that has the relocs applied. */
2789 r
= si_shader_binary_upload(sctx
->screen
, shader
);
2791 si_shader_unlock(shader
);
2795 /* Update the shader state to use the new shader bo. */
2796 si_shader_init_pm4_state(sctx
->screen
, shader
);
2798 r600_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
2800 si_shader_unlock(shader
);
2804 static unsigned si_get_current_scratch_buffer_size(struct si_context
*sctx
)
2806 return sctx
->scratch_buffer
? sctx
->scratch_buffer
->b
.b
.width0
: 0;
2809 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
2811 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
2814 static struct si_shader
*si_get_tcs_current(struct si_context
*sctx
)
2816 if (!sctx
->tes_shader
.cso
)
2817 return NULL
; /* tessellation disabled */
2819 return sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.current
:
2820 sctx
->fixed_func_tcs_shader
.current
;
2823 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context
*sctx
)
2827 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
2828 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
2829 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
2830 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
2832 if (sctx
->tes_shader
.cso
) {
2833 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
2835 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(tcs
));
2840 static bool si_update_scratch_relocs(struct si_context
*sctx
)
2842 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
2845 /* Update the shaders, so that they are using the latest scratch.
2846 * The scratch buffer may have been changed since these shaders were
2847 * last used, so we still need to try to update them, even if they
2848 * require scratch buffers smaller than the current size.
2850 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
2854 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
2856 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
2860 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
2862 r
= si_update_scratch_buffer(sctx
, tcs
);
2866 si_pm4_bind_state(sctx
, hs
, tcs
->pm4
);
2868 /* VS can be bound as LS, ES, or VS. */
2869 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
2873 if (sctx
->tes_shader
.current
)
2874 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
2875 else if (sctx
->gs_shader
.current
)
2876 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
2878 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
2881 /* TES can be bound as ES or VS. */
2882 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
2886 if (sctx
->gs_shader
.current
)
2887 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
2889 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
2895 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
2897 unsigned current_scratch_buffer_size
=
2898 si_get_current_scratch_buffer_size(sctx
);
2899 unsigned scratch_bytes_per_wave
=
2900 si_get_max_scratch_bytes_per_wave(sctx
);
2901 unsigned scratch_needed_size
= scratch_bytes_per_wave
*
2902 sctx
->scratch_waves
;
2903 unsigned spi_tmpring_size
;
2905 if (scratch_needed_size
> 0) {
2906 if (scratch_needed_size
> current_scratch_buffer_size
) {
2907 /* Create a bigger scratch buffer */
2908 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
2910 sctx
->scratch_buffer
= (struct r600_resource
*)
2911 r600_aligned_buffer_create(&sctx
->screen
->b
.b
,
2912 R600_RESOURCE_FLAG_UNMAPPABLE
,
2914 scratch_needed_size
, 256);
2915 if (!sctx
->scratch_buffer
)
2918 si_mark_atom_dirty(sctx
, &sctx
->scratch_state
);
2919 r600_context_add_resource_size(&sctx
->b
.b
,
2920 &sctx
->scratch_buffer
->b
.b
);
2923 if (!si_update_scratch_relocs(sctx
))
2927 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
2928 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
2929 "scratch size should already be aligned correctly.");
2931 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
2932 S_0286E8_WAVESIZE(scratch_bytes_per_wave
>> 10);
2933 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
2934 sctx
->spi_tmpring_size
= spi_tmpring_size
;
2935 si_mark_atom_dirty(sctx
, &sctx
->scratch_state
);
2940 static void si_init_tess_factor_ring(struct si_context
*sctx
)
2942 bool double_offchip_buffers
= sctx
->b
.chip_class
>= CIK
&&
2943 sctx
->b
.family
!= CHIP_CARRIZO
&&
2944 sctx
->b
.family
!= CHIP_STONEY
;
2945 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
2946 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
2947 sctx
->screen
->b
.info
.max_se
;
2948 unsigned offchip_granularity
;
2950 switch (sctx
->screen
->tess_offchip_block_dw_size
) {
2955 offchip_granularity
= V_03093C_X_8K_DWORDS
;
2958 offchip_granularity
= V_03093C_X_4K_DWORDS
;
2962 switch (sctx
->b
.chip_class
) {
2964 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
2969 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
2976 assert(!sctx
->tf_ring
);
2977 /* Use 64K alignment for both rings, so that we can pass the address
2978 * to shaders as one SGPR containing bits [16:47].
2980 sctx
->tf_ring
= r600_aligned_buffer_create(sctx
->b
.b
.screen
,
2981 R600_RESOURCE_FLAG_UNMAPPABLE
,
2983 32768 * sctx
->screen
->b
.info
.max_se
,
2988 assert(((sctx
->tf_ring
->width0
/ 4) & C_030938_SIZE
) == 0);
2990 sctx
->tess_offchip_ring
=
2991 r600_aligned_buffer_create(sctx
->b
.b
.screen
,
2992 R600_RESOURCE_FLAG_UNMAPPABLE
,
2994 max_offchip_buffers
*
2995 sctx
->screen
->tess_offchip_block_dw_size
* 4,
2997 if (!sctx
->tess_offchip_ring
)
3000 si_init_config_add_vgt_flush(sctx
);
3002 uint64_t offchip_va
= r600_resource(sctx
->tess_offchip_ring
)->gpu_address
;
3003 uint64_t factor_va
= r600_resource(sctx
->tf_ring
)->gpu_address
;
3004 assert((offchip_va
& 0xffff) == 0);
3005 assert((factor_va
& 0xffff) == 0);
3007 si_pm4_add_bo(sctx
->init_config
, r600_resource(sctx
->tess_offchip_ring
),
3008 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
3009 si_pm4_add_bo(sctx
->init_config
, r600_resource(sctx
->tf_ring
),
3010 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
3012 /* Append these registers to the init config state. */
3013 if (sctx
->b
.chip_class
>= CIK
) {
3014 if (sctx
->b
.chip_class
>= VI
)
3015 --max_offchip_buffers
;
3017 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
3018 S_030938_SIZE(sctx
->tf_ring
->width0
/ 4));
3019 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
3021 if (sctx
->b
.chip_class
>= GFX9
)
3022 si_pm4_set_reg(sctx
->init_config
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3024 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3025 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
3026 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
));
3028 assert(offchip_granularity
== V_03093C_X_8K_DWORDS
);
3029 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
3030 S_008988_SIZE(sctx
->tf_ring
->width0
/ 4));
3031 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
3033 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3034 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
));
3037 if (sctx
->b
.chip_class
>= GFX9
) {
3038 si_pm4_set_reg(sctx
->init_config
,
3039 R_00B430_SPI_SHADER_USER_DATA_LS_0
+
3040 GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K
* 4,
3042 si_pm4_set_reg(sctx
->init_config
,
3043 R_00B430_SPI_SHADER_USER_DATA_LS_0
+
3044 GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K
* 4,
3047 si_pm4_set_reg(sctx
->init_config
,
3048 R_00B430_SPI_SHADER_USER_DATA_HS_0
+
3049 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K
* 4,
3051 si_pm4_set_reg(sctx
->init_config
,
3052 R_00B430_SPI_SHADER_USER_DATA_HS_0
+
3053 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K
* 4,
3057 /* Flush the context to re-emit the init_config state.
3058 * This is done only once in a lifetime of a context.
3060 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3061 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
3062 si_context_gfx_flush(sctx
, RADEON_FLUSH_ASYNC
, NULL
);
3066 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
3067 * VS passes its outputs to TES directly, so the fixed-function shader only
3068 * has to write TESSOUTER and TESSINNER.
3070 static void si_generate_fixed_func_tcs(struct si_context
*sctx
)
3072 struct ureg_src outer
, inner
;
3073 struct ureg_dst tessouter
, tessinner
;
3074 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_TESS_CTRL
);
3077 return; /* if we get here, we're screwed */
3079 assert(!sctx
->fixed_func_tcs_shader
.cso
);
3081 outer
= ureg_DECL_system_value(ureg
,
3082 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
, 0);
3083 inner
= ureg_DECL_system_value(ureg
,
3084 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
, 0);
3086 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
3087 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
3089 ureg_MOV(ureg
, tessouter
, outer
);
3090 ureg_MOV(ureg
, tessinner
, inner
);
3093 sctx
->fixed_func_tcs_shader
.cso
=
3094 ureg_create_shader_and_destroy(ureg
, &sctx
->b
.b
);
3097 static void si_update_vgt_shader_config(struct si_context
*sctx
)
3099 /* Calculate the index of the config.
3100 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3101 unsigned index
= 2*!!sctx
->tes_shader
.cso
+ !!sctx
->gs_shader
.cso
;
3102 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[index
];
3105 uint32_t stages
= 0;
3107 *pm4
= CALLOC_STRUCT(si_pm4_state
);
3109 if (sctx
->tes_shader
.cso
) {
3110 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3111 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3113 if (sctx
->gs_shader
.cso
)
3114 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3116 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3118 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3119 } else if (sctx
->gs_shader
.cso
) {
3120 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3122 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3125 if (sctx
->b
.chip_class
>= GFX9
)
3126 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3128 si_pm4_set_reg(*pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
3130 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
3133 bool si_update_shaders(struct si_context
*sctx
)
3135 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
3136 struct si_compiler_ctx_state compiler_state
;
3137 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3138 struct si_shader
*old_vs
= si_get_vs_state(sctx
);
3139 bool old_clip_disable
= old_vs
? old_vs
->key
.opt
.clip_disable
: false;
3140 struct si_shader
*old_ps
= sctx
->ps_shader
.current
;
3141 unsigned old_spi_shader_col_format
=
3142 old_ps
? old_ps
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
3145 compiler_state
.tm
= sctx
->tm
;
3146 compiler_state
.debug
= sctx
->b
.debug
;
3147 compiler_state
.is_debug_context
= sctx
->is_debug
;
3149 /* Update stages before GS. */
3150 if (sctx
->tes_shader
.cso
) {
3151 if (!sctx
->tf_ring
) {
3152 si_init_tess_factor_ring(sctx
);
3158 if (sctx
->b
.chip_class
<= VI
) {
3159 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
3163 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3166 if (sctx
->tcs_shader
.cso
) {
3167 r
= si_shader_select(ctx
, &sctx
->tcs_shader
,
3171 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
3173 if (!sctx
->fixed_func_tcs_shader
.cso
) {
3174 si_generate_fixed_func_tcs(sctx
);
3175 if (!sctx
->fixed_func_tcs_shader
.cso
)
3179 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
,
3183 si_pm4_bind_state(sctx
, hs
,
3184 sctx
->fixed_func_tcs_shader
.current
->pm4
);
3187 if (sctx
->gs_shader
.cso
) {
3189 if (sctx
->b
.chip_class
<= VI
) {
3190 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
3194 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3198 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
3202 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3204 } else if (sctx
->gs_shader
.cso
) {
3205 if (sctx
->b
.chip_class
<= VI
) {
3207 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
3211 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3213 si_pm4_bind_state(sctx
, ls
, NULL
);
3214 si_pm4_bind_state(sctx
, hs
, NULL
);
3218 r
= si_shader_select(ctx
, &sctx
->vs_shader
, &compiler_state
);
3221 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3222 si_pm4_bind_state(sctx
, ls
, NULL
);
3223 si_pm4_bind_state(sctx
, hs
, NULL
);
3227 if (sctx
->gs_shader
.cso
) {
3228 r
= si_shader_select(ctx
, &sctx
->gs_shader
, &compiler_state
);
3231 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3232 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
3234 if (!si_update_gs_ring_buffers(sctx
))
3237 si_pm4_bind_state(sctx
, gs
, NULL
);
3238 if (sctx
->b
.chip_class
<= VI
)
3239 si_pm4_bind_state(sctx
, es
, NULL
);
3242 si_update_vgt_shader_config(sctx
);
3244 if (old_clip_disable
!= si_get_vs_state(sctx
)->key
.opt
.clip_disable
)
3245 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
3247 if (sctx
->ps_shader
.cso
) {
3248 unsigned db_shader_control
;
3250 r
= si_shader_select(ctx
, &sctx
->ps_shader
, &compiler_state
);
3253 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3256 sctx
->ps_shader
.cso
->db_shader_control
|
3257 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
3259 if (si_pm4_state_changed(sctx
, ps
) || si_pm4_state_changed(sctx
, vs
) ||
3260 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
3261 sctx
->flatshade
!= rs
->flatshade
) {
3262 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
3263 sctx
->flatshade
= rs
->flatshade
;
3264 si_mark_atom_dirty(sctx
, &sctx
->spi_map
);
3267 if (sctx
->screen
->b
.rbplus_allowed
&&
3268 si_pm4_state_changed(sctx
, ps
) &&
3270 old_spi_shader_col_format
!=
3271 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
))
3272 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
3274 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
3275 sctx
->ps_db_shader_control
= db_shader_control
;
3276 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
3279 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
3280 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
3281 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
3283 if (sctx
->b
.chip_class
== SI
)
3284 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
3286 if (sctx
->framebuffer
.nr_samples
<= 1)
3287 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
3291 if (si_pm4_state_changed(sctx
, ls
) ||
3292 si_pm4_state_changed(sctx
, hs
) ||
3293 si_pm4_state_changed(sctx
, es
) ||
3294 si_pm4_state_changed(sctx
, gs
) ||
3295 si_pm4_state_changed(sctx
, vs
) ||
3296 si_pm4_state_changed(sctx
, ps
)) {
3297 if (!si_update_spi_tmpring_size(sctx
))
3301 if (sctx
->b
.chip_class
>= CIK
)
3302 si_mark_atom_dirty(sctx
, &sctx
->prefetch_L2
);
3304 sctx
->do_update_shaders
= false;
3308 static void si_emit_scratch_state(struct si_context
*sctx
,
3309 struct r600_atom
*atom
)
3311 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
3313 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
3314 sctx
->spi_tmpring_size
);
3316 if (sctx
->scratch_buffer
) {
3317 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
3318 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
3319 RADEON_PRIO_SCRATCH_BUFFER
);
3323 void si_init_shader_functions(struct si_context
*sctx
)
3325 si_init_atom(sctx
, &sctx
->spi_map
, &sctx
->atoms
.s
.spi_map
, si_emit_spi_map
);
3326 si_init_atom(sctx
, &sctx
->scratch_state
, &sctx
->atoms
.s
.scratch_state
,
3327 si_emit_scratch_state
);
3329 sctx
->b
.b
.create_vs_state
= si_create_shader_selector
;
3330 sctx
->b
.b
.create_tcs_state
= si_create_shader_selector
;
3331 sctx
->b
.b
.create_tes_state
= si_create_shader_selector
;
3332 sctx
->b
.b
.create_gs_state
= si_create_shader_selector
;
3333 sctx
->b
.b
.create_fs_state
= si_create_shader_selector
;
3335 sctx
->b
.b
.bind_vs_state
= si_bind_vs_shader
;
3336 sctx
->b
.b
.bind_tcs_state
= si_bind_tcs_shader
;
3337 sctx
->b
.b
.bind_tes_state
= si_bind_tes_shader
;
3338 sctx
->b
.b
.bind_gs_state
= si_bind_gs_shader
;
3339 sctx
->b
.b
.bind_fs_state
= si_bind_ps_shader
;
3341 sctx
->b
.b
.delete_vs_state
= si_delete_shader_selector
;
3342 sctx
->b
.b
.delete_tcs_state
= si_delete_shader_selector
;
3343 sctx
->b
.b
.delete_tes_state
= si_delete_shader_selector
;
3344 sctx
->b
.b
.delete_gs_state
= si_delete_shader_selector
;
3345 sctx
->b
.b
.delete_fs_state
= si_delete_shader_selector
;