2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
44 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
47 void *si_get_ir_binary(struct si_shader_selector
*sel
)
54 ir_binary
= sel
->tokens
;
55 ir_size
= tgsi_num_tokens(sel
->tokens
) *
56 sizeof(struct tgsi_token
);
61 nir_serialize(&blob
, sel
->nir
);
62 ir_binary
= blob
.data
;
66 unsigned size
= 4 + ir_size
+ sizeof(sel
->so
);
67 char *result
= (char*)MALLOC(size
);
71 *((uint32_t*)result
) = size
;
72 memcpy(result
+ 4, ir_binary
, ir_size
);
73 memcpy(result
+ 4 + ir_size
, &sel
->so
, sizeof(sel
->so
));
81 /** Copy "data" to "ptr" and return the next dword following copied data. */
82 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
84 /* data may be NULL if size == 0 */
86 memcpy(ptr
, data
, size
);
87 ptr
+= DIV_ROUND_UP(size
, 4);
91 /** Read data from "ptr". Return the next dword following the data. */
92 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
94 memcpy(data
, ptr
, size
);
95 ptr
+= DIV_ROUND_UP(size
, 4);
100 * Write the size as uint followed by the data. Return the next dword
101 * following the copied data.
103 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
106 return write_data(ptr
, data
, size
);
110 * Read the size as uint followed by the data. Return both via parameters.
111 * Return the next dword following the data.
113 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
116 assert(*data
== NULL
);
119 *data
= malloc(*size
);
120 return read_data(ptr
, *data
, *size
);
124 * Return the shader binary in a buffer. The first 4 bytes contain its size
127 static void *si_get_shader_binary(struct si_shader
*shader
)
129 /* There is always a size of data followed by the data itself. */
130 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
131 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
133 /* Refuse to allocate overly large buffers and guard against integer
135 if (shader
->binary
.elf_size
> UINT_MAX
/ 4 ||
136 llvm_ir_size
> UINT_MAX
/ 4)
141 4 + /* CRC32 of the data below */
142 align(sizeof(shader
->config
), 4) +
143 align(sizeof(shader
->info
), 4) +
144 4 + align(shader
->binary
.elf_size
, 4) +
145 4 + align(llvm_ir_size
, 4);
146 void *buffer
= CALLOC(1, size
);
147 uint32_t *ptr
= (uint32_t*)buffer
;
153 ptr
++; /* CRC32 is calculated at the end. */
155 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
156 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
157 ptr
= write_chunk(ptr
, shader
->binary
.elf_buffer
, shader
->binary
.elf_size
);
158 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
159 assert((char *)ptr
- (char *)buffer
== size
);
162 ptr
= (uint32_t*)buffer
;
164 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
169 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
171 uint32_t *ptr
= (uint32_t*)binary
;
172 uint32_t size
= *ptr
++;
173 uint32_t crc32
= *ptr
++;
177 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
178 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
182 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
183 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
184 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.elf_buffer
,
186 shader
->binary
.elf_size
= elf_size
;
187 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
193 * Insert a shader into the cache. It's assumed the shader is not in the cache.
194 * Use si_shader_cache_load_shader before calling this.
196 * Returns false on failure, in which case the ir_binary should be freed.
198 bool si_shader_cache_insert_shader(struct si_screen
*sscreen
, void *ir_binary
,
199 struct si_shader
*shader
,
200 bool insert_into_disk_cache
)
203 struct hash_entry
*entry
;
204 uint8_t key
[CACHE_KEY_SIZE
];
206 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
208 return false; /* already added */
210 hw_binary
= si_get_shader_binary(shader
);
214 if (_mesa_hash_table_insert(sscreen
->shader_cache
, ir_binary
,
215 hw_binary
) == NULL
) {
220 if (sscreen
->disk_shader_cache
&& insert_into_disk_cache
) {
221 disk_cache_compute_key(sscreen
->disk_shader_cache
, ir_binary
,
222 *((uint32_t *)ir_binary
), key
);
223 disk_cache_put(sscreen
->disk_shader_cache
, key
, hw_binary
,
224 *((uint32_t *) hw_binary
), NULL
);
230 bool si_shader_cache_load_shader(struct si_screen
*sscreen
, void *ir_binary
,
231 struct si_shader
*shader
)
233 struct hash_entry
*entry
=
234 _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
236 if (sscreen
->disk_shader_cache
) {
237 unsigned char sha1
[CACHE_KEY_SIZE
];
238 size_t tg_size
= *((uint32_t *) ir_binary
);
240 disk_cache_compute_key(sscreen
->disk_shader_cache
,
241 ir_binary
, tg_size
, sha1
);
245 disk_cache_get(sscreen
->disk_shader_cache
,
250 if (binary_size
< sizeof(uint32_t) ||
251 *((uint32_t*)buffer
) != binary_size
) {
252 /* Something has gone wrong discard the item
253 * from the cache and rebuild/link from
256 assert(!"Invalid radeonsi shader disk cache "
259 disk_cache_remove(sscreen
->disk_shader_cache
,
266 if (!si_load_shader_binary(shader
, buffer
)) {
272 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
,
279 if (si_load_shader_binary(shader
, entry
->data
))
284 p_atomic_inc(&sscreen
->num_shader_cache_hits
);
288 static uint32_t si_shader_cache_key_hash(const void *key
)
290 /* The first dword is the key size. */
291 return util_hash_crc32(key
, *(uint32_t*)key
);
294 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
296 uint32_t *keya
= (uint32_t*)a
;
297 uint32_t *keyb
= (uint32_t*)b
;
299 /* The first dword is the key size. */
303 return memcmp(keya
, keyb
, *keya
) == 0;
306 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
308 FREE((void*)entry
->key
);
312 bool si_init_shader_cache(struct si_screen
*sscreen
)
314 (void) mtx_init(&sscreen
->shader_cache_mutex
, mtx_plain
);
315 sscreen
->shader_cache
=
316 _mesa_hash_table_create(NULL
,
317 si_shader_cache_key_hash
,
318 si_shader_cache_key_equals
);
320 return sscreen
->shader_cache
!= NULL
;
323 void si_destroy_shader_cache(struct si_screen
*sscreen
)
325 if (sscreen
->shader_cache
)
326 _mesa_hash_table_destroy(sscreen
->shader_cache
,
327 si_destroy_shader_cache_entry
);
328 mtx_destroy(&sscreen
->shader_cache_mutex
);
333 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
334 const struct si_shader_selector
*tes
,
335 struct si_pm4_state
*pm4
)
337 const struct tgsi_shader_info
*info
= &tes
->info
;
338 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
339 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
340 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
341 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
342 unsigned type
, partitioning
, topology
, distribution_mode
;
344 switch (tes_prim_mode
) {
345 case PIPE_PRIM_LINES
:
346 type
= V_028B6C_TESS_ISOLINE
;
348 case PIPE_PRIM_TRIANGLES
:
349 type
= V_028B6C_TESS_TRIANGLE
;
351 case PIPE_PRIM_QUADS
:
352 type
= V_028B6C_TESS_QUAD
;
359 switch (tes_spacing
) {
360 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
361 partitioning
= V_028B6C_PART_FRAC_ODD
;
363 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
364 partitioning
= V_028B6C_PART_FRAC_EVEN
;
366 case PIPE_TESS_SPACING_EQUAL
:
367 partitioning
= V_028B6C_PART_INTEGER
;
375 topology
= V_028B6C_OUTPUT_POINT
;
376 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
377 topology
= V_028B6C_OUTPUT_LINE
;
378 else if (tes_vertex_order_cw
)
379 /* for some reason, this must be the other way around */
380 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
382 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
384 if (sscreen
->has_distributed_tess
) {
385 if (sscreen
->info
.family
== CHIP_FIJI
||
386 sscreen
->info
.family
>= CHIP_POLARIS10
)
387 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
389 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
391 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
394 pm4
->shader
->vgt_tf_param
= S_028B6C_TYPE(type
) |
395 S_028B6C_PARTITIONING(partitioning
) |
396 S_028B6C_TOPOLOGY(topology
) |
397 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
400 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
401 * whether the "fractional odd" tessellation spacing is used.
403 * Possible VGT configurations and which state should set the register:
405 * Reg set in | VGT shader configuration | Value
406 * ------------------------------------------------------
408 * VS as ES | ES -> GS -> VS | 30
409 * TES as VS | LS -> HS -> VS | 14 or 30
410 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
412 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
414 static void polaris_set_vgt_vertex_reuse(struct si_screen
*sscreen
,
415 struct si_shader_selector
*sel
,
416 struct si_shader
*shader
,
417 struct si_pm4_state
*pm4
)
419 unsigned type
= sel
->type
;
421 if (sscreen
->info
.family
< CHIP_POLARIS10
||
422 sscreen
->info
.chip_class
>= GFX10
)
425 /* VS as VS, or VS as ES: */
426 if ((type
== PIPE_SHADER_VERTEX
&&
428 (!shader
->key
.as_ls
&& !shader
->is_gs_copy_shader
))) ||
429 /* TES as VS, or TES as ES: */
430 type
== PIPE_SHADER_TESS_EVAL
) {
431 unsigned vtx_reuse_depth
= 30;
433 if (type
== PIPE_SHADER_TESS_EVAL
&&
434 sel
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] ==
435 PIPE_TESS_SPACING_FRACTIONAL_ODD
)
436 vtx_reuse_depth
= 14;
439 pm4
->shader
->vgt_vertex_reuse_block_cntl
= vtx_reuse_depth
;
443 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
446 si_pm4_clear_state(shader
->pm4
);
448 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
451 shader
->pm4
->shader
= shader
;
454 fprintf(stderr
, "radeonsi: Failed to create pm4 state.\n");
459 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs
)
461 /* Add the pointer to VBO descriptors. */
462 return num_always_on_user_sgprs
+ 1;
465 static void si_shader_ls(struct si_screen
*sscreen
, struct si_shader
*shader
)
467 struct si_pm4_state
*pm4
;
468 unsigned vgpr_comp_cnt
;
471 assert(sscreen
->info
.chip_class
<= GFX8
);
473 pm4
= si_get_shader_pm4_state(shader
);
477 va
= shader
->bo
->gpu_address
;
478 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
480 /* We need at least 2 components for LS.
481 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
482 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
484 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
486 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
487 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
489 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
490 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
491 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt
) |
492 S_00B528_DX10_CLAMP(1) |
493 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
494 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
)) |
495 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
498 static void si_shader_hs(struct si_screen
*sscreen
, struct si_shader
*shader
)
500 struct si_pm4_state
*pm4
;
502 unsigned ls_vgpr_comp_cnt
= 0;
504 pm4
= si_get_shader_pm4_state(shader
);
508 va
= shader
->bo
->gpu_address
;
509 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
511 if (sscreen
->info
.chip_class
>= GFX9
) {
512 if (sscreen
->info
.chip_class
>= GFX10
) {
513 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
514 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
516 si_pm4_set_reg(pm4
, R_00B410_SPI_SHADER_PGM_LO_LS
, va
>> 8);
517 si_pm4_set_reg(pm4
, R_00B414_SPI_SHADER_PGM_HI_LS
, S_00B414_MEM_BASE(va
>> 40));
520 /* We need at least 2 components for LS.
521 * GFX9 VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
522 * GFX10 VGPR0-3: (VertexID, RelAutoindex, UserVGPR1, InstanceID).
523 * On gfx9, StepRate0 is set to 1 so that VGPR3 doesn't have to
526 ls_vgpr_comp_cnt
= 1;
527 if (shader
->info
.uses_instanceid
) {
528 if (sscreen
->info
.chip_class
>= GFX10
)
529 ls_vgpr_comp_cnt
= 3;
531 ls_vgpr_comp_cnt
= 2;
534 unsigned num_user_sgprs
=
535 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR
);
537 shader
->config
.rsrc2
=
538 S_00B42C_USER_SGPR(num_user_sgprs
) |
539 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
541 if (sscreen
->info
.chip_class
>= GFX10
)
542 shader
->config
.rsrc2
|= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
544 shader
->config
.rsrc2
|= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
546 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
547 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, S_00B424_MEM_BASE(va
>> 40));
549 shader
->config
.rsrc2
=
550 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR
) |
551 S_00B42C_OC_LDS_EN(1) |
552 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
555 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
556 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
557 (sscreen
->info
.chip_class
<= GFX9
?
558 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) : 0) |
559 S_00B428_DX10_CLAMP(1) |
560 S_00B428_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
561 S_00B428_FLOAT_MODE(shader
->config
.float_mode
) |
562 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt
));
564 if (sscreen
->info
.chip_class
<= GFX8
) {
565 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
566 shader
->config
.rsrc2
);
570 static void si_emit_shader_es(struct si_context
*sctx
)
572 struct si_shader
*shader
= sctx
->queued
.named
.es
->shader
;
573 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
578 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
579 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
580 shader
->selector
->esgs_itemsize
/ 4);
582 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
583 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
584 SI_TRACKED_VGT_TF_PARAM
,
585 shader
->vgt_tf_param
);
587 if (shader
->vgt_vertex_reuse_block_cntl
)
588 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
589 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
590 shader
->vgt_vertex_reuse_block_cntl
);
592 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
593 sctx
->context_roll
= true;
596 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
598 struct si_pm4_state
*pm4
;
599 unsigned num_user_sgprs
;
600 unsigned vgpr_comp_cnt
;
604 assert(sscreen
->info
.chip_class
<= GFX8
);
606 pm4
= si_get_shader_pm4_state(shader
);
610 pm4
->atom
.emit
= si_emit_shader_es
;
611 va
= shader
->bo
->gpu_address
;
612 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
614 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
615 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
616 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
617 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
618 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
619 vgpr_comp_cnt
= shader
->selector
->info
.uses_primid
? 3 : 2;
620 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
622 unreachable("invalid shader selector type");
624 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
626 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
627 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
628 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
629 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
630 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
631 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
632 S_00B328_DX10_CLAMP(1) |
633 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
634 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
635 S_00B32C_USER_SGPR(num_user_sgprs
) |
636 S_00B32C_OC_LDS_EN(oc_lds_en
) |
637 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
639 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
640 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
642 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
645 void gfx9_get_gs_info(struct si_shader_selector
*es
,
646 struct si_shader_selector
*gs
,
647 struct gfx9_gs_info
*out
)
649 unsigned gs_num_invocations
= MAX2(gs
->gs_num_invocations
, 1);
650 unsigned input_prim
= gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
651 bool uses_adjacency
= input_prim
>= PIPE_PRIM_LINES_ADJACENCY
&&
652 input_prim
<= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
;
654 /* All these are in dwords: */
655 /* We can't allow using the whole LDS, because GS waves compete with
656 * other shader stages for LDS space. */
657 const unsigned max_lds_size
= 8 * 1024;
658 const unsigned esgs_itemsize
= es
->esgs_itemsize
/ 4;
659 unsigned esgs_lds_size
;
661 /* All these are per subgroup: */
662 const unsigned max_out_prims
= 32 * 1024;
663 const unsigned max_es_verts
= 255;
664 const unsigned ideal_gs_prims
= 64;
665 unsigned max_gs_prims
, gs_prims
;
666 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
668 if (uses_adjacency
|| gs_num_invocations
> 1)
669 max_gs_prims
= 127 / gs_num_invocations
;
673 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
674 * Make sure we don't go over the maximum value.
676 if (gs
->gs_max_out_vertices
> 0) {
677 max_gs_prims
= MIN2(max_gs_prims
,
679 (gs
->gs_max_out_vertices
* gs_num_invocations
));
681 assert(max_gs_prims
> 0);
683 /* If the primitive has adjacency, halve the number of vertices
684 * that will be reused in multiple primitives.
686 min_es_verts
= gs
->gs_input_verts_per_prim
/ (uses_adjacency
? 2 : 1);
688 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
689 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
691 /* Compute ESGS LDS size based on the worst case number of ES vertices
692 * needed to create the target number of GS prims per subgroup.
694 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
696 /* If total LDS usage is too big, refactor partitions based on ratio
697 * of ESGS item sizes.
699 if (esgs_lds_size
> max_lds_size
) {
700 /* Our target GS Prims Per Subgroup was too large. Calculate
701 * the maximum number of GS Prims Per Subgroup that will fit
702 * into LDS, capped by the maximum that the hardware can support.
704 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
706 assert(gs_prims
> 0);
707 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
710 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
711 assert(esgs_lds_size
<= max_lds_size
);
714 /* Now calculate remaining ESGS information. */
716 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
718 es_verts
= max_es_verts
;
720 /* Vertices for adjacency primitives are not always reused, so restore
721 * it for ES_VERTS_PER_SUBGRP.
723 min_es_verts
= gs
->gs_input_verts_per_prim
;
725 /* For normal primitives, the VGT only checks if they are past the ES
726 * verts per subgroup after allocating a full GS primitive and if they
727 * are, kick off a new subgroup. But if those additional ES verts are
728 * unique (e.g. not reused) we need to make sure there is enough LDS
729 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
731 es_verts
-= min_es_verts
- 1;
733 out
->es_verts_per_subgroup
= es_verts
;
734 out
->gs_prims_per_subgroup
= gs_prims
;
735 out
->gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
736 out
->max_prims_per_subgroup
= out
->gs_inst_prims_in_subgroup
*
737 gs
->gs_max_out_vertices
;
738 out
->esgs_ring_size
= 4 * esgs_lds_size
;
740 assert(out
->max_prims_per_subgroup
<= max_out_prims
);
743 static void si_emit_shader_gs(struct si_context
*sctx
)
745 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
746 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
751 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
752 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
753 radeon_opt_set_context_reg3(sctx
, R_028A60_VGT_GSVS_RING_OFFSET_1
,
754 SI_TRACKED_VGT_GSVS_RING_OFFSET_1
,
755 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
,
756 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
,
757 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
);
759 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
760 radeon_opt_set_context_reg(sctx
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
,
761 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE
,
762 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
);
764 /* R_028B38_VGT_GS_MAX_VERT_OUT */
765 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
766 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
767 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
);
769 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
770 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
771 radeon_opt_set_context_reg4(sctx
, R_028B5C_VGT_GS_VERT_ITEMSIZE
,
772 SI_TRACKED_VGT_GS_VERT_ITEMSIZE
,
773 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
,
774 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
,
775 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
,
776 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
);
778 /* R_028B90_VGT_GS_INSTANCE_CNT */
779 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
,
780 SI_TRACKED_VGT_GS_INSTANCE_CNT
,
781 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
);
783 if (sctx
->chip_class
>= GFX9
) {
784 /* R_028A44_VGT_GS_ONCHIP_CNTL */
785 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
786 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
787 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
);
788 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
789 radeon_opt_set_context_reg(sctx
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
790 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
791 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
);
792 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
793 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
794 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
795 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
);
797 if (shader
->key
.part
.gs
.es
->type
== PIPE_SHADER_TESS_EVAL
)
798 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
799 SI_TRACKED_VGT_TF_PARAM
,
800 shader
->vgt_tf_param
);
801 if (shader
->vgt_vertex_reuse_block_cntl
)
802 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
803 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
804 shader
->vgt_vertex_reuse_block_cntl
);
807 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
808 sctx
->context_roll
= true;
811 static void si_shader_gs(struct si_screen
*sscreen
, struct si_shader
*shader
)
813 struct si_shader_selector
*sel
= shader
->selector
;
814 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
815 unsigned gs_num_invocations
= sel
->gs_num_invocations
;
816 struct si_pm4_state
*pm4
;
818 unsigned max_stream
= sel
->max_gs_stream
;
821 pm4
= si_get_shader_pm4_state(shader
);
825 pm4
->atom
.emit
= si_emit_shader_gs
;
827 offset
= num_components
[0] * sel
->gs_max_out_vertices
;
828 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
= offset
;
831 offset
+= num_components
[1] * sel
->gs_max_out_vertices
;
832 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
= offset
;
835 offset
+= num_components
[2] * sel
->gs_max_out_vertices
;
836 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
= offset
;
839 offset
+= num_components
[3] * sel
->gs_max_out_vertices
;
840 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
= offset
;
842 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
843 assert(offset
< (1 << 15));
845 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
= sel
->gs_max_out_vertices
;
847 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
= num_components
[0];
848 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
= (max_stream
>= 1) ? num_components
[1] : 0;
849 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
= (max_stream
>= 2) ? num_components
[2] : 0;
850 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
= (max_stream
>= 3) ? num_components
[3] : 0;
852 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
= S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
853 S_028B90_ENABLE(gs_num_invocations
> 0);
855 va
= shader
->bo
->gpu_address
;
856 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
858 if (sscreen
->info
.chip_class
>= GFX9
) {
859 unsigned input_prim
= sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
860 unsigned es_type
= shader
->key
.part
.gs
.es
->type
;
861 unsigned es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
863 if (es_type
== PIPE_SHADER_VERTEX
)
864 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
865 es_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
866 else if (es_type
== PIPE_SHADER_TESS_EVAL
)
867 es_vgpr_comp_cnt
= shader
->key
.part
.gs
.es
->info
.uses_primid
? 3 : 2;
869 unreachable("invalid shader selector type");
871 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
872 * VGPR[0:4] are always loaded.
874 if (sel
->info
.uses_invocationid
)
875 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
876 else if (sel
->info
.uses_primid
)
877 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
878 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
879 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
881 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
883 unsigned num_user_sgprs
;
884 if (es_type
== PIPE_SHADER_VERTEX
)
885 num_user_sgprs
= si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR
);
887 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
889 if (sscreen
->info
.chip_class
>= GFX10
) {
890 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
891 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
893 si_pm4_set_reg(pm4
, R_00B210_SPI_SHADER_PGM_LO_ES
, va
>> 8);
894 si_pm4_set_reg(pm4
, R_00B214_SPI_SHADER_PGM_HI_ES
, S_00B214_MEM_BASE(va
>> 40));
898 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
899 S_00B228_DX10_CLAMP(1) |
900 S_00B228_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
901 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
902 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
);
904 S_00B22C_USER_SGPR(num_user_sgprs
) |
905 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
906 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
907 S_00B22C_LDS_SIZE(shader
->config
.lds_size
) |
908 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
910 if (sscreen
->info
.chip_class
>= GFX10
) {
911 rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
913 rsrc1
|= S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
914 rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
917 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, rsrc1
);
918 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
, rsrc2
);
920 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
=
921 S_028A44_ES_VERTS_PER_SUBGRP(shader
->gs_info
.es_verts_per_subgroup
) |
922 S_028A44_GS_PRIMS_PER_SUBGRP(shader
->gs_info
.gs_prims_per_subgroup
) |
923 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader
->gs_info
.gs_inst_prims_in_subgroup
);
924 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
=
925 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader
->gs_info
.max_prims_per_subgroup
);
926 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
=
927 shader
->key
.part
.gs
.es
->esgs_itemsize
/ 4;
929 if (es_type
== PIPE_SHADER_TESS_EVAL
)
930 si_set_tesseval_regs(sscreen
, shader
->key
.part
.gs
.es
, pm4
);
932 polaris_set_vgt_vertex_reuse(sscreen
, shader
->key
.part
.gs
.es
,
935 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
936 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, S_00B224_MEM_BASE(va
>> 40));
938 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
939 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
940 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
941 S_00B228_DX10_CLAMP(1) |
942 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
943 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
944 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR
) |
945 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
949 /* Common tail code for NGG primitive shaders. */
950 static void gfx10_emit_shader_ngg_tail(struct si_context
*sctx
,
951 struct si_shader
*shader
,
952 unsigned initial_cdw
)
954 radeon_opt_set_context_reg(sctx
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
955 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP
,
956 shader
->ctx_reg
.ngg
.ge_max_output_per_subgroup
);
957 radeon_opt_set_context_reg(sctx
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
958 SI_TRACKED_GE_NGG_SUBGRP_CNTL
,
959 shader
->ctx_reg
.ngg
.ge_ngg_subgrp_cntl
);
960 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
,
961 SI_TRACKED_VGT_PRIMITIVEID_EN
,
962 shader
->ctx_reg
.ngg
.vgt_primitiveid_en
);
963 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
964 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
965 shader
->ctx_reg
.ngg
.vgt_gs_onchip_cntl
);
966 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
,
967 SI_TRACKED_VGT_GS_INSTANCE_CNT
,
968 shader
->ctx_reg
.ngg
.vgt_gs_instance_cnt
);
969 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
970 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
971 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
);
972 radeon_opt_set_context_reg(sctx
, R_028AB4_VGT_REUSE_OFF
,
973 SI_TRACKED_VGT_REUSE_OFF
,
974 shader
->ctx_reg
.ngg
.vgt_reuse_off
);
975 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
,
976 SI_TRACKED_SPI_VS_OUT_CONFIG
,
977 shader
->ctx_reg
.ngg
.spi_vs_out_config
);
978 radeon_opt_set_context_reg2(sctx
, R_028708_SPI_SHADER_IDX_FORMAT
,
979 SI_TRACKED_SPI_SHADER_IDX_FORMAT
,
980 shader
->ctx_reg
.ngg
.spi_shader_idx_format
,
981 shader
->ctx_reg
.ngg
.spi_shader_pos_format
);
982 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
,
983 SI_TRACKED_PA_CL_VTE_CNTL
,
984 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
);
985 radeon_opt_set_context_reg(sctx
, R_028838_PA_CL_NGG_CNTL
,
986 SI_TRACKED_PA_CL_NGG_CNTL
,
987 shader
->ctx_reg
.ngg
.pa_cl_ngg_cntl
);
989 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
990 sctx
->context_roll
= true;
992 if (shader
->ge_cntl
!= sctx
->last_multi_vgt_param
) {
993 radeon_set_uconfig_reg(sctx
->gfx_cs
, R_03096C_GE_CNTL
, shader
->ge_cntl
);
994 sctx
->last_multi_vgt_param
= shader
->ge_cntl
;
998 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context
*sctx
)
1000 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1001 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1006 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1009 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context
*sctx
)
1011 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1012 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1017 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1018 SI_TRACKED_VGT_TF_PARAM
,
1019 shader
->vgt_tf_param
);
1021 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1024 static void gfx10_emit_shader_ngg_notess_gs(struct si_context
*sctx
)
1026 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1027 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1032 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
1033 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
1034 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
);
1036 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1039 static void gfx10_emit_shader_ngg_tess_gs(struct si_context
*sctx
)
1041 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1042 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1047 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
1048 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
1049 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
);
1050 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1051 SI_TRACKED_VGT_TF_PARAM
,
1052 shader
->vgt_tf_param
);
1054 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1057 unsigned si_get_input_prim(const struct si_shader_selector
*gs
)
1059 if (gs
->type
== PIPE_SHADER_GEOMETRY
)
1060 return gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
1062 if (gs
->type
== PIPE_SHADER_TESS_EVAL
) {
1063 if (gs
->info
.properties
[TGSI_PROPERTY_TES_POINT_MODE
])
1064 return PIPE_PRIM_POINTS
;
1065 if (gs
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] == PIPE_PRIM_LINES
)
1066 return PIPE_PRIM_LINES
;
1067 return PIPE_PRIM_TRIANGLES
;
1070 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1071 return PIPE_PRIM_TRIANGLES
;
1075 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1078 static void gfx10_shader_ngg(struct si_screen
*sscreen
, struct si_shader
*shader
)
1080 const struct si_shader_selector
*gs_sel
= shader
->selector
;
1081 const struct tgsi_shader_info
*gs_info
= &gs_sel
->info
;
1082 enum pipe_shader_type gs_type
= shader
->selector
->type
;
1083 const struct si_shader_selector
*es_sel
=
1084 shader
->previous_stage_sel
? shader
->previous_stage_sel
: shader
->selector
;
1085 const struct tgsi_shader_info
*es_info
= &es_sel
->info
;
1086 enum pipe_shader_type es_type
= es_sel
->type
;
1087 unsigned num_user_sgprs
;
1088 unsigned nparams
, es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
1090 unsigned window_space
=
1091 gs_info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
1092 bool es_enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| es_info
->uses_primid
;
1093 unsigned gs_num_invocations
= MAX2(gs_sel
->gs_num_invocations
, 1);
1094 unsigned input_prim
= si_get_input_prim(gs_sel
);
1095 bool break_wave_at_eoi
= false;
1096 struct si_pm4_state
*pm4
= si_get_shader_pm4_state(shader
);
1100 if (es_type
== PIPE_SHADER_TESS_EVAL
) {
1101 pm4
->atom
.emit
= gs_type
== PIPE_SHADER_GEOMETRY
? gfx10_emit_shader_ngg_tess_gs
1102 : gfx10_emit_shader_ngg_tess_nogs
;
1104 pm4
->atom
.emit
= gs_type
== PIPE_SHADER_GEOMETRY
? gfx10_emit_shader_ngg_notess_gs
1105 : gfx10_emit_shader_ngg_notess_nogs
;
1108 va
= shader
->bo
->gpu_address
;
1109 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1111 if (es_type
== PIPE_SHADER_VERTEX
) {
1112 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
1113 es_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 3 : 0;
1115 if (es_info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
]) {
1116 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
1117 es_info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
1119 num_user_sgprs
= si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR
);
1122 assert(es_type
== PIPE_SHADER_TESS_EVAL
);
1123 es_vgpr_comp_cnt
= es_enable_prim_id
? 3 : 2;
1124 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
1126 if (es_enable_prim_id
|| gs_info
->uses_primid
)
1127 break_wave_at_eoi
= true;
1130 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1131 * VGPR[0:4] are always loaded.
1133 * Vertex shaders always need to load VGPR3, because they need to
1134 * pass edge flags for decomposed primitives (such as quads) to the PA
1135 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1137 if (gs_info
->uses_invocationid
|| gs_type
== PIPE_SHADER_VERTEX
)
1138 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID, edge flags. */
1139 else if (gs_info
->uses_primid
)
1140 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
1141 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
1142 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
1144 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
1146 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
1147 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
1148 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
1149 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1150 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
1151 S_00B228_DX10_CLAMP(1) |
1152 S_00B228_MEM_ORDERED(1) |
1153 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
));
1154 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
1155 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0) |
1156 S_00B22C_USER_SGPR(num_user_sgprs
) |
1157 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
1158 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5) |
1159 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
1160 S_00B22C_LDS_SIZE(shader
->config
.lds_size
));
1162 /* TODO: Use NO_PC_EXPORT when applicable. */
1163 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1164 shader
->ctx_reg
.ngg
.spi_vs_out_config
=
1165 S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
1167 shader
->ctx_reg
.ngg
.spi_shader_idx_format
=
1168 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
);
1169 shader
->ctx_reg
.ngg
.spi_shader_pos_format
=
1170 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1171 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
1172 V_02870C_SPI_SHADER_4COMP
:
1173 V_02870C_SPI_SHADER_NONE
) |
1174 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
1175 V_02870C_SPI_SHADER_4COMP
:
1176 V_02870C_SPI_SHADER_NONE
) |
1177 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
1178 V_02870C_SPI_SHADER_4COMP
:
1179 V_02870C_SPI_SHADER_NONE
);
1181 shader
->ctx_reg
.ngg
.vgt_primitiveid_en
=
1182 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
1183 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id
);
1185 if (gs_type
== PIPE_SHADER_GEOMETRY
) {
1186 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
= es_sel
->esgs_itemsize
/ 4;
1187 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
= gs_sel
->gs_max_out_vertices
;
1189 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
= 1;
1192 if (es_type
== PIPE_SHADER_TESS_EVAL
)
1193 si_set_tesseval_regs(sscreen
, es_sel
, pm4
);
1195 shader
->ctx_reg
.ngg
.vgt_gs_onchip_cntl
=
1196 S_028A44_ES_VERTS_PER_SUBGRP(shader
->ngg
.hw_max_esverts
) |
1197 S_028A44_GS_PRIMS_PER_SUBGRP(shader
->ngg
.max_gsprims
) |
1198 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader
->ngg
.max_gsprims
* gs_num_invocations
);
1199 shader
->ctx_reg
.ngg
.ge_max_output_per_subgroup
=
1200 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader
->ngg
.max_out_verts
);
1201 shader
->ctx_reg
.ngg
.ge_ngg_subgrp_cntl
=
1202 S_028B4C_PRIM_AMP_FACTOR(shader
->ngg
.prim_amp_factor
) |
1203 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1204 shader
->ctx_reg
.ngg
.vgt_gs_instance_cnt
=
1205 S_028B90_CNT(gs_num_invocations
) |
1206 S_028B90_ENABLE(gs_num_invocations
> 1) |
1207 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1208 shader
->ngg
.max_vert_out_per_gs_instance
);
1210 /* User edge flags are set by the pos exports. If user edge flags are
1211 * not used, we must use hw-generated edge flags and pass them via
1212 * the prim export to prevent drawing lines on internal edges of
1213 * decomposed primitives (such as quads) with polygon mode = lines.
1215 * TODO: We should combine hw-generated edge flags with user edge
1216 * flags in the shader.
1218 shader
->ctx_reg
.ngg
.pa_cl_ngg_cntl
=
1219 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type
== PIPE_SHADER_VERTEX
&&
1220 !gs_info
->writes_edgeflag
);
1223 S_03096C_PRIM_GRP_SIZE(shader
->ngg
.max_gsprims
) |
1224 S_03096C_VERT_GRP_SIZE(shader
->ngg
.hw_max_esverts
) |
1225 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
1228 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
=
1229 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1231 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
=
1232 S_028818_VTX_W0_FMT(1) |
1233 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1234 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1235 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1238 shader
->ctx_reg
.ngg
.vgt_reuse_off
=
1239 S_028AB4_REUSE_OFF(sscreen
->info
.family
== CHIP_NAVI10
&&
1240 sscreen
->info
.chip_external_rev
== 0x1 &&
1241 es_type
== PIPE_SHADER_TESS_EVAL
);
1244 static void si_emit_shader_vs(struct si_context
*sctx
)
1246 struct si_shader
*shader
= sctx
->queued
.named
.vs
->shader
;
1247 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1252 radeon_opt_set_context_reg(sctx
, R_028A40_VGT_GS_MODE
,
1253 SI_TRACKED_VGT_GS_MODE
,
1254 shader
->ctx_reg
.vs
.vgt_gs_mode
);
1255 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
,
1256 SI_TRACKED_VGT_PRIMITIVEID_EN
,
1257 shader
->ctx_reg
.vs
.vgt_primitiveid_en
);
1259 if (sctx
->chip_class
<= GFX8
) {
1260 radeon_opt_set_context_reg(sctx
, R_028AB4_VGT_REUSE_OFF
,
1261 SI_TRACKED_VGT_REUSE_OFF
,
1262 shader
->ctx_reg
.vs
.vgt_reuse_off
);
1265 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
,
1266 SI_TRACKED_SPI_VS_OUT_CONFIG
,
1267 shader
->ctx_reg
.vs
.spi_vs_out_config
);
1269 radeon_opt_set_context_reg(sctx
, R_02870C_SPI_SHADER_POS_FORMAT
,
1270 SI_TRACKED_SPI_SHADER_POS_FORMAT
,
1271 shader
->ctx_reg
.vs
.spi_shader_pos_format
);
1273 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
,
1274 SI_TRACKED_PA_CL_VTE_CNTL
,
1275 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
);
1277 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
1278 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1279 SI_TRACKED_VGT_TF_PARAM
,
1280 shader
->vgt_tf_param
);
1282 if (shader
->vgt_vertex_reuse_block_cntl
)
1283 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1284 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1285 shader
->vgt_vertex_reuse_block_cntl
);
1287 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1288 sctx
->context_roll
= true;
1292 * Compute the state for \p shader, which will run as a vertex shader on the
1295 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1296 * is the copy shader.
1298 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
1299 struct si_shader_selector
*gs
)
1301 const struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1302 struct si_pm4_state
*pm4
;
1303 unsigned num_user_sgprs
, vgpr_comp_cnt
;
1305 unsigned nparams
, oc_lds_en
;
1306 unsigned window_space
=
1307 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
1308 bool enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| info
->uses_primid
;
1310 pm4
= si_get_shader_pm4_state(shader
);
1314 pm4
->atom
.emit
= si_emit_shader_vs
;
1316 /* We always write VGT_GS_MODE in the VS state, because every switch
1317 * between different shader pipelines involving a different GS or no
1318 * GS at all involves a switch of the VS (different GS use different
1319 * copy shaders). On the other hand, when the API switches from a GS to
1320 * no GS and then back to the same GS used originally, the GS state is
1324 unsigned mode
= V_028A40_GS_OFF
;
1326 /* PrimID needs GS scenario A. */
1328 mode
= V_028A40_GS_SCENARIO_A
;
1330 shader
->ctx_reg
.vs
.vgt_gs_mode
= S_028A40_MODE(mode
);
1331 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= enable_prim_id
;
1333 shader
->ctx_reg
.vs
.vgt_gs_mode
= ac_vgt_gs_mode(gs
->gs_max_out_vertices
,
1334 sscreen
->info
.chip_class
);
1335 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= 0;
1338 if (sscreen
->info
.chip_class
<= GFX8
) {
1339 /* Reuse needs to be set off if we write oViewport. */
1340 shader
->ctx_reg
.vs
.vgt_reuse_off
=
1341 S_028AB4_REUSE_OFF(info
->writes_viewport_index
);
1344 va
= shader
->bo
->gpu_address
;
1345 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1348 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
1349 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
1350 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
1351 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1352 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1353 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1355 vgpr_comp_cnt
= enable_prim_id
? 2 : (shader
->info
.uses_instanceid
? 1 : 0);
1357 if (info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
]) {
1358 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
1359 info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
1361 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
1363 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
1364 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
1365 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
1367 unreachable("invalid shader selector type");
1369 /* VS is required to export at least one param. */
1370 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1371 shader
->ctx_reg
.vs
.spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
1373 shader
->ctx_reg
.vs
.spi_shader_pos_format
=
1374 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1375 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
1376 V_02870C_SPI_SHADER_4COMP
:
1377 V_02870C_SPI_SHADER_NONE
) |
1378 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
1379 V_02870C_SPI_SHADER_4COMP
:
1380 V_02870C_SPI_SHADER_NONE
) |
1381 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
1382 V_02870C_SPI_SHADER_4COMP
:
1383 V_02870C_SPI_SHADER_NONE
);
1385 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
1387 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
1388 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, S_00B124_MEM_BASE(va
>> 40));
1390 uint32_t rsrc1
= S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1391 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
1392 S_00B128_DX10_CLAMP(1) |
1393 S_00B128_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
1394 S_00B128_FLOAT_MODE(shader
->config
.float_mode
);
1395 uint32_t rsrc2
= S_00B12C_USER_SGPR(num_user_sgprs
) |
1396 S_00B12C_OC_LDS_EN(oc_lds_en
) |
1397 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
1399 if (sscreen
->info
.chip_class
<= GFX9
) {
1400 rsrc1
|= S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
1401 rsrc2
|= S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
1402 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
1403 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
1404 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
1405 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
);
1408 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
, rsrc1
);
1409 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
, rsrc2
);
1412 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1413 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1415 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1416 S_028818_VTX_W0_FMT(1) |
1417 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1418 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1419 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1421 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
1422 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
1424 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
1427 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
1429 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
1430 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
1431 !!(info
->colors_read
& 0xf0);
1432 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
1433 (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
1435 assert(num_interp
<= 32);
1436 return MIN2(num_interp
, 32);
1439 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
1441 unsigned value
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
1442 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
1444 /* If the i-th target format is set, all previous target formats must
1445 * be non-zero to avoid hangs.
1447 for (i
= 0; i
< num_targets
; i
++)
1448 if (!(value
& (0xf << (i
* 4))))
1449 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
1454 static void si_emit_shader_ps(struct si_context
*sctx
)
1456 struct si_shader
*shader
= sctx
->queued
.named
.ps
->shader
;
1457 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1462 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1463 radeon_opt_set_context_reg2(sctx
, R_0286CC_SPI_PS_INPUT_ENA
,
1464 SI_TRACKED_SPI_PS_INPUT_ENA
,
1465 shader
->ctx_reg
.ps
.spi_ps_input_ena
,
1466 shader
->ctx_reg
.ps
.spi_ps_input_addr
);
1468 radeon_opt_set_context_reg(sctx
, R_0286E0_SPI_BARYC_CNTL
,
1469 SI_TRACKED_SPI_BARYC_CNTL
,
1470 shader
->ctx_reg
.ps
.spi_baryc_cntl
);
1471 radeon_opt_set_context_reg(sctx
, R_0286D8_SPI_PS_IN_CONTROL
,
1472 SI_TRACKED_SPI_PS_IN_CONTROL
,
1473 shader
->ctx_reg
.ps
.spi_ps_in_control
);
1475 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1476 radeon_opt_set_context_reg2(sctx
, R_028710_SPI_SHADER_Z_FORMAT
,
1477 SI_TRACKED_SPI_SHADER_Z_FORMAT
,
1478 shader
->ctx_reg
.ps
.spi_shader_z_format
,
1479 shader
->ctx_reg
.ps
.spi_shader_col_format
);
1481 radeon_opt_set_context_reg(sctx
, R_02823C_CB_SHADER_MASK
,
1482 SI_TRACKED_CB_SHADER_MASK
,
1483 shader
->ctx_reg
.ps
.cb_shader_mask
);
1485 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1486 sctx
->context_roll
= true;
1489 static void si_shader_ps(struct si_screen
*sscreen
, struct si_shader
*shader
)
1491 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1492 struct si_pm4_state
*pm4
;
1493 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
1494 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
1496 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
1498 /* we need to enable at least one of them, otherwise we hang the GPU */
1499 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1500 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1501 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1502 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
1503 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
1504 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1505 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
1506 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
1507 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1508 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
1509 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1510 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1511 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1512 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
1514 /* Validate interpolation optimization flags (read as implications). */
1515 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1516 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1517 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1518 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1519 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1520 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1521 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
1522 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
1523 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1524 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
1525 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
1526 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1527 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
1528 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1529 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1530 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
1531 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1532 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1534 /* Validate cases when the optimizations are off (read as implications). */
1535 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1536 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1537 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
1538 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1539 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1540 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
1542 pm4
= si_get_shader_pm4_state(shader
);
1546 pm4
->atom
.emit
= si_emit_shader_ps
;
1548 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1550 * 0 -> Position = pixel center
1551 * 1 -> Position = pixel centroid
1552 * 2 -> Position = at sample position
1554 * From GLSL 4.5 specification, section 7.1:
1555 * "The variable gl_FragCoord is available as an input variable from
1556 * within fragment shaders and it holds the window relative coordinates
1557 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1558 * value can be for any location within the pixel, or one of the
1559 * fragment samples. The use of centroid does not further restrict
1560 * this value to be inside the current primitive."
1562 * Meaning that centroid has no effect and we can return anything within
1563 * the pixel. Thus, return the value at sample position, because that's
1564 * the most accurate one shaders can get.
1566 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1568 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
1569 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
1570 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
1572 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
1573 cb_shader_mask
= ac_get_cb_shader_mask(spi_shader_col_format
);
1575 /* Ensure that some export memory is always allocated, for two reasons:
1577 * 1) Correctness: The hardware ignores the EXEC mask if no export
1578 * memory is allocated, so KILL and alpha test do not work correctly
1580 * 2) Performance: Every shader needs at least a NULL export, even when
1581 * it writes no color/depth output. The NULL export instruction
1582 * stalls without this setting.
1584 * Don't add this to CB_SHADER_MASK.
1586 if (!spi_shader_col_format
&&
1587 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
1588 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
1590 shader
->ctx_reg
.ps
.spi_ps_input_ena
= input_ena
;
1591 shader
->ctx_reg
.ps
.spi_ps_input_addr
= shader
->config
.spi_ps_input_addr
;
1593 /* Set interpolation controls. */
1594 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
));
1596 shader
->ctx_reg
.ps
.spi_baryc_cntl
= spi_baryc_cntl
;
1597 shader
->ctx_reg
.ps
.spi_ps_in_control
= spi_ps_in_control
;
1598 shader
->ctx_reg
.ps
.spi_shader_z_format
=
1599 ac_get_spi_shader_z_format(info
->writes_z
,
1600 info
->writes_stencil
,
1601 info
->writes_samplemask
);
1602 shader
->ctx_reg
.ps
.spi_shader_col_format
= spi_shader_col_format
;
1603 shader
->ctx_reg
.ps
.cb_shader_mask
= cb_shader_mask
;
1605 va
= shader
->bo
->gpu_address
;
1606 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1607 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
1608 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, S_00B024_MEM_BASE(va
>> 40));
1611 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1612 S_00B028_DX10_CLAMP(1) |
1613 S_00B028_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
1614 S_00B028_FLOAT_MODE(shader
->config
.float_mode
);
1616 if (sscreen
->info
.chip_class
< GFX10
) {
1617 rsrc1
|= S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
1620 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
, rsrc1
);
1621 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
1622 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
1623 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
1624 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1627 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
1628 struct si_shader
*shader
)
1630 switch (shader
->selector
->type
) {
1631 case PIPE_SHADER_VERTEX
:
1632 if (shader
->key
.as_ls
)
1633 si_shader_ls(sscreen
, shader
);
1634 else if (shader
->key
.as_es
)
1635 si_shader_es(sscreen
, shader
);
1636 else if (shader
->key
.as_ngg
)
1637 gfx10_shader_ngg(sscreen
, shader
);
1639 si_shader_vs(sscreen
, shader
, NULL
);
1641 case PIPE_SHADER_TESS_CTRL
:
1642 si_shader_hs(sscreen
, shader
);
1644 case PIPE_SHADER_TESS_EVAL
:
1645 if (shader
->key
.as_es
)
1646 si_shader_es(sscreen
, shader
);
1647 else if (shader
->key
.as_ngg
)
1648 gfx10_shader_ngg(sscreen
, shader
);
1650 si_shader_vs(sscreen
, shader
, NULL
);
1652 case PIPE_SHADER_GEOMETRY
:
1653 if (shader
->key
.as_ngg
)
1654 gfx10_shader_ngg(sscreen
, shader
);
1656 si_shader_gs(sscreen
, shader
);
1658 case PIPE_SHADER_FRAGMENT
:
1659 si_shader_ps(sscreen
, shader
);
1666 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
1668 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1669 if (sctx
->queued
.named
.dsa
)
1670 return sctx
->queued
.named
.dsa
->alpha_func
;
1672 return PIPE_FUNC_ALWAYS
;
1675 void si_shader_selector_key_vs(struct si_context
*sctx
,
1676 struct si_shader_selector
*vs
,
1677 struct si_shader_key
*key
,
1678 struct si_vs_prolog_bits
*prolog_key
)
1680 if (!sctx
->vertex_elements
||
1681 vs
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
])
1684 struct si_vertex_elements
*elts
= sctx
->vertex_elements
;
1686 prolog_key
->instance_divisor_is_one
= elts
->instance_divisor_is_one
;
1687 prolog_key
->instance_divisor_is_fetched
= elts
->instance_divisor_is_fetched
;
1688 prolog_key
->unpack_instance_id_from_vertex_id
=
1689 sctx
->prim_discard_cs_instancing
;
1691 /* Prefer a monolithic shader to allow scheduling divisions around
1693 if (prolog_key
->instance_divisor_is_fetched
)
1694 key
->opt
.prefer_mono
= 1;
1696 unsigned count
= MIN2(vs
->info
.num_inputs
, elts
->count
);
1697 unsigned count_mask
= (1 << count
) - 1;
1698 unsigned fix
= elts
->fix_fetch_always
& count_mask
;
1699 unsigned opencode
= elts
->fix_fetch_opencode
& count_mask
;
1701 if (sctx
->vertex_buffer_unaligned
& elts
->vb_alignment_check_mask
) {
1702 uint32_t mask
= elts
->fix_fetch_unaligned
& count_mask
;
1704 unsigned i
= u_bit_scan(&mask
);
1705 unsigned log_hw_load_size
= 1 + ((elts
->hw_load_is_dword
>> i
) & 1);
1706 unsigned vbidx
= elts
->vertex_buffer_index
[i
];
1707 struct pipe_vertex_buffer
*vb
= &sctx
->vertex_buffer
[vbidx
];
1708 unsigned align_mask
= (1 << log_hw_load_size
) - 1;
1709 if (vb
->buffer_offset
& align_mask
||
1710 vb
->stride
& align_mask
) {
1718 unsigned i
= u_bit_scan(&fix
);
1719 key
->mono
.vs_fix_fetch
[i
].bits
= elts
->fix_fetch
[i
];
1721 key
->mono
.vs_fetch_opencode
= opencode
;
1724 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
,
1725 struct si_shader_selector
*vs
,
1726 struct si_shader_key
*key
)
1728 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1730 key
->opt
.clip_disable
=
1731 sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
1732 (vs
->info
.clipdist_writemask
||
1733 vs
->info
.writes_clipvertex
) &&
1734 !vs
->info
.culldist_writemask
;
1736 /* Find out if PS is disabled. */
1737 bool ps_disabled
= true;
1739 const struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1740 bool alpha_to_coverage
= blend
&& blend
->alpha_to_coverage
;
1741 bool ps_modifies_zs
= ps
->info
.uses_kill
||
1742 ps
->info
.writes_z
||
1743 ps
->info
.writes_stencil
||
1744 ps
->info
.writes_samplemask
||
1745 alpha_to_coverage
||
1746 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
1747 unsigned ps_colormask
= si_get_total_colormask(sctx
);
1749 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
1752 !ps
->info
.writes_memory
);
1755 /* Find out which VS outputs aren't used by the PS. */
1756 uint64_t outputs_written
= vs
->outputs_written_before_ps
;
1757 uint64_t inputs_read
= 0;
1759 /* Ignore outputs that are not passed from VS to PS. */
1760 outputs_written
&= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION
, 0, true)) |
1761 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE
, 0, true)) |
1762 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX
, 0, true)));
1765 inputs_read
= ps
->inputs_read
;
1768 uint64_t linked
= outputs_written
& inputs_read
;
1770 key
->opt
.kill_outputs
= ~linked
& outputs_written
;
1773 /* Compute the key for the hw shader variant */
1774 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
1775 struct si_shader_selector
*sel
,
1776 union si_vgt_stages_key stages_key
,
1777 struct si_shader_key
*key
)
1779 struct si_context
*sctx
= (struct si_context
*)ctx
;
1781 memset(key
, 0, sizeof(*key
));
1783 switch (sel
->type
) {
1784 case PIPE_SHADER_VERTEX
:
1785 si_shader_selector_key_vs(sctx
, sel
, key
, &key
->part
.vs
.prolog
);
1787 if (sctx
->tes_shader
.cso
)
1789 else if (sctx
->gs_shader
.cso
)
1792 key
->as_ngg
= stages_key
.u
.ngg
;
1793 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1795 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1796 key
->mono
.u
.vs_export_prim_id
= 1;
1799 case PIPE_SHADER_TESS_CTRL
:
1800 if (sctx
->chip_class
>= GFX9
) {
1801 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1802 key
, &key
->part
.tcs
.ls_prolog
);
1803 key
->part
.tcs
.ls
= sctx
->vs_shader
.cso
;
1805 /* When the LS VGPR fix is needed, monolithic shaders
1807 * - avoid initializing EXEC in both the LS prolog
1808 * and the LS main part when !vs_needs_prolog
1809 * - remove the fixup for unused input VGPRs
1811 key
->part
.tcs
.ls_prolog
.ls_vgpr_fix
= sctx
->ls_vgpr_fix
;
1813 /* The LS output / HS input layout can be communicated
1814 * directly instead of via user SGPRs for merged LS-HS.
1815 * The LS VGPR fix prefers this too.
1817 key
->opt
.prefer_mono
= 1;
1820 key
->part
.tcs
.epilog
.prim_mode
=
1821 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1822 key
->part
.tcs
.epilog
.invoc0_tess_factors_are_def
=
1823 sel
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1824 key
->part
.tcs
.epilog
.tes_reads_tess_factors
=
1825 sctx
->tes_shader
.cso
->info
.reads_tess_factors
;
1827 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
1828 key
->mono
.u
.ff_tcs_inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
1830 case PIPE_SHADER_TESS_EVAL
:
1831 if (sctx
->gs_shader
.cso
)
1834 key
->as_ngg
= stages_key
.u
.ngg
;
1835 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1837 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1838 key
->mono
.u
.vs_export_prim_id
= 1;
1841 case PIPE_SHADER_GEOMETRY
:
1842 if (sctx
->chip_class
>= GFX9
) {
1843 if (sctx
->tes_shader
.cso
) {
1844 key
->part
.gs
.es
= sctx
->tes_shader
.cso
;
1846 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1847 key
, &key
->part
.gs
.vs_prolog
);
1848 key
->part
.gs
.es
= sctx
->vs_shader
.cso
;
1849 key
->part
.gs
.prolog
.gfx9_prev_is_vs
= 1;
1852 key
->as_ngg
= stages_key
.u
.ngg
;
1854 /* Merged ES-GS can have unbalanced wave usage.
1856 * ES threads are per-vertex, while GS threads are
1857 * per-primitive. So without any amplification, there
1858 * are fewer GS threads than ES threads, which can result
1859 * in empty (no-op) GS waves. With too much amplification,
1860 * there are more GS threads than ES threads, which
1861 * can result in empty (no-op) ES waves.
1863 * Non-monolithic shaders are implemented by setting EXEC
1864 * at the beginning of shader parts, and don't jump to
1865 * the end if EXEC is 0.
1867 * Monolithic shaders use conditional blocks, so they can
1868 * jump and skip empty waves of ES or GS. So set this to
1869 * always use optimized variants, which are monolithic.
1871 key
->opt
.prefer_mono
= 1;
1873 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
1875 case PIPE_SHADER_FRAGMENT
: {
1876 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1877 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1879 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
1880 sel
->info
.colors_written
== 0x1)
1881 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
1884 /* Select the shader color format based on whether
1885 * blending or alpha are needed.
1887 key
->part
.ps
.epilog
.spi_shader_col_format
=
1888 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1889 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
1890 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1891 sctx
->framebuffer
.spi_shader_col_format_blend
) |
1892 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1893 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
1894 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1895 sctx
->framebuffer
.spi_shader_col_format
);
1896 key
->part
.ps
.epilog
.spi_shader_col_format
&= blend
->cb_target_enabled_4bit
;
1898 /* The output for dual source blending should have
1899 * the same format as the first output.
1901 if (blend
->dual_src_blend
)
1902 key
->part
.ps
.epilog
.spi_shader_col_format
|=
1903 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
1905 key
->part
.ps
.epilog
.spi_shader_col_format
= sctx
->framebuffer
.spi_shader_col_format
;
1907 /* If alpha-to-coverage is enabled, we have to export alpha
1908 * even if there is no color buffer.
1910 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) &&
1911 blend
&& blend
->alpha_to_coverage
)
1912 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
1914 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1915 * to the range supported by the type if a channel has less
1916 * than 16 bits and the export format is 16_ABGR.
1918 if (sctx
->chip_class
<= GFX7
&& sctx
->family
!= CHIP_HAWAII
) {
1919 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
1920 key
->part
.ps
.epilog
.color_is_int10
= sctx
->framebuffer
.color_is_int10
;
1923 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1924 if (!key
->part
.ps
.epilog
.last_cbuf
) {
1925 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
1926 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
1927 key
->part
.ps
.epilog
.color_is_int10
&= sel
->info
.colors_written
;
1930 bool is_poly
= !util_prim_is_points_or_lines(sctx
->current_rast_prim
);
1931 bool is_line
= util_prim_is_lines(sctx
->current_rast_prim
);
1933 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
1934 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
1936 if (sctx
->queued
.named
.blend
) {
1937 key
->part
.ps
.epilog
.alpha_to_one
= sctx
->queued
.named
.blend
->alpha_to_one
&&
1938 rs
->multisample_enable
;
1941 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
1942 key
->part
.ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
1943 (is_line
&& rs
->line_smooth
)) &&
1944 sctx
->framebuffer
.nr_samples
<= 1;
1945 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
1947 if (sctx
->ps_iter_samples
> 1 &&
1948 sel
->info
.reads_samplemask
) {
1949 key
->part
.ps
.prolog
.samplemask_log_ps_iter
=
1950 util_logbase2(sctx
->ps_iter_samples
);
1953 if (rs
->force_persample_interp
&&
1954 rs
->multisample_enable
&&
1955 sctx
->framebuffer
.nr_samples
> 1 &&
1956 sctx
->ps_iter_samples
> 1) {
1957 key
->part
.ps
.prolog
.force_persp_sample_interp
=
1958 sel
->info
.uses_persp_center
||
1959 sel
->info
.uses_persp_centroid
;
1961 key
->part
.ps
.prolog
.force_linear_sample_interp
=
1962 sel
->info
.uses_linear_center
||
1963 sel
->info
.uses_linear_centroid
;
1964 } else if (rs
->multisample_enable
&&
1965 sctx
->framebuffer
.nr_samples
> 1) {
1966 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
1967 sel
->info
.uses_persp_center
&&
1968 sel
->info
.uses_persp_centroid
;
1969 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
1970 sel
->info
.uses_linear_center
&&
1971 sel
->info
.uses_linear_centroid
;
1973 /* Make sure SPI doesn't compute more than 1 pair
1974 * of (i,j), which is the optimization here. */
1975 key
->part
.ps
.prolog
.force_persp_center_interp
=
1976 sel
->info
.uses_persp_center
+
1977 sel
->info
.uses_persp_centroid
+
1978 sel
->info
.uses_persp_sample
> 1;
1980 key
->part
.ps
.prolog
.force_linear_center_interp
=
1981 sel
->info
.uses_linear_center
+
1982 sel
->info
.uses_linear_centroid
+
1983 sel
->info
.uses_linear_sample
> 1;
1985 if (sel
->info
.opcode_count
[TGSI_OPCODE_INTERP_SAMPLE
])
1986 key
->mono
.u
.ps
.interpolate_at_sample_force_center
= 1;
1989 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
1991 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1992 if (sctx
->ps_uses_fbfetch
&& !sctx
->blitter
->running
) {
1993 struct pipe_surface
*cb0
= sctx
->framebuffer
.state
.cbufs
[0];
1994 struct pipe_resource
*tex
= cb0
->texture
;
1996 /* 1D textures are allocated and used as 2D on GFX9. */
1997 key
->mono
.u
.ps
.fbfetch_msaa
= sctx
->framebuffer
.nr_samples
> 1;
1998 key
->mono
.u
.ps
.fbfetch_is_1D
= sctx
->chip_class
!= GFX9
&&
1999 (tex
->target
== PIPE_TEXTURE_1D
||
2000 tex
->target
== PIPE_TEXTURE_1D_ARRAY
);
2001 key
->mono
.u
.ps
.fbfetch_layered
= tex
->target
== PIPE_TEXTURE_1D_ARRAY
||
2002 tex
->target
== PIPE_TEXTURE_2D_ARRAY
||
2003 tex
->target
== PIPE_TEXTURE_CUBE
||
2004 tex
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
2005 tex
->target
== PIPE_TEXTURE_3D
;
2013 if (unlikely(sctx
->screen
->debug_flags
& DBG(NO_OPT_VARIANT
)))
2014 memset(&key
->opt
, 0, sizeof(key
->opt
));
2017 static void si_build_shader_variant(struct si_shader
*shader
,
2021 struct si_shader_selector
*sel
= shader
->selector
;
2022 struct si_screen
*sscreen
= sel
->screen
;
2023 struct ac_llvm_compiler
*compiler
;
2024 struct pipe_debug_callback
*debug
= &shader
->compiler_ctx_state
.debug
;
2026 if (thread_index
>= 0) {
2028 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler_lowp
));
2029 compiler
= &sscreen
->compiler_lowp
[thread_index
];
2031 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
2032 compiler
= &sscreen
->compiler
[thread_index
];
2037 assert(!low_priority
);
2038 compiler
= shader
->compiler_ctx_state
.compiler
;
2041 if (unlikely(!si_shader_create(sscreen
, compiler
, shader
, debug
))) {
2042 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2044 shader
->compilation_failed
= true;
2048 if (shader
->compiler_ctx_state
.is_debug_context
) {
2049 FILE *f
= open_memstream(&shader
->shader_log
,
2050 &shader
->shader_log_size
);
2052 si_shader_dump(sscreen
, shader
, NULL
, sel
->type
, f
, false);
2057 si_shader_init_pm4_state(sscreen
, shader
);
2060 static void si_build_shader_variant_low_priority(void *job
, int thread_index
)
2062 struct si_shader
*shader
= (struct si_shader
*)job
;
2064 assert(thread_index
>= 0);
2066 si_build_shader_variant(shader
, thread_index
, true);
2069 static const struct si_shader_key zeroed
;
2071 static bool si_check_missing_main_part(struct si_screen
*sscreen
,
2072 struct si_shader_selector
*sel
,
2073 struct si_compiler_ctx_state
*compiler_state
,
2074 struct si_shader_key
*key
)
2076 struct si_shader
**mainp
= si_get_main_shader_part(sel
, key
);
2079 struct si_shader
*main_part
= CALLOC_STRUCT(si_shader
);
2084 /* We can leave the fence as permanently signaled because the
2085 * main part becomes visible globally only after it has been
2087 util_queue_fence_init(&main_part
->ready
);
2089 main_part
->selector
= sel
;
2090 main_part
->key
.as_es
= key
->as_es
;
2091 main_part
->key
.as_ls
= key
->as_ls
;
2092 main_part
->key
.as_ngg
= key
->as_ngg
;
2093 main_part
->is_monolithic
= false;
2095 if (si_compile_tgsi_shader(sscreen
, compiler_state
->compiler
,
2096 main_part
, &compiler_state
->debug
) != 0) {
2106 * Select a shader variant according to the shader key.
2108 * \param optimized_or_none If the key describes an optimized shader variant and
2109 * the compilation isn't finished, don't select any
2110 * shader and return an error.
2112 int si_shader_select_with_key(struct si_screen
*sscreen
,
2113 struct si_shader_ctx_state
*state
,
2114 struct si_compiler_ctx_state
*compiler_state
,
2115 struct si_shader_key
*key
,
2117 bool optimized_or_none
)
2119 struct si_shader_selector
*sel
= state
->cso
;
2120 struct si_shader_selector
*previous_stage_sel
= NULL
;
2121 struct si_shader
*current
= state
->current
;
2122 struct si_shader
*iter
, *shader
= NULL
;
2125 /* Check if we don't need to change anything.
2126 * This path is also used for most shaders that don't need multiple
2127 * variants, it will cost just a computation of the key and this
2129 if (likely(current
&&
2130 memcmp(¤t
->key
, key
, sizeof(*key
)) == 0)) {
2131 if (unlikely(!util_queue_fence_is_signalled(¤t
->ready
))) {
2132 if (current
->is_optimized
) {
2133 if (optimized_or_none
)
2136 memset(&key
->opt
, 0, sizeof(key
->opt
));
2137 goto current_not_ready
;
2140 util_queue_fence_wait(¤t
->ready
);
2143 return current
->compilation_failed
? -1 : 0;
2147 /* This must be done before the mutex is locked, because async GS
2148 * compilation calls this function too, and therefore must enter
2151 * Only wait if we are in a draw call. Don't wait if we are
2152 * in a compiler thread.
2154 if (thread_index
< 0)
2155 util_queue_fence_wait(&sel
->ready
);
2157 mtx_lock(&sel
->mutex
);
2159 /* Find the shader variant. */
2160 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
2161 /* Don't check the "current" shader. We checked it above. */
2162 if (current
!= iter
&&
2163 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
2164 mtx_unlock(&sel
->mutex
);
2166 if (unlikely(!util_queue_fence_is_signalled(&iter
->ready
))) {
2167 /* If it's an optimized shader and its compilation has
2168 * been started but isn't done, use the unoptimized
2169 * shader so as not to cause a stall due to compilation.
2171 if (iter
->is_optimized
) {
2172 if (optimized_or_none
)
2174 memset(&key
->opt
, 0, sizeof(key
->opt
));
2178 util_queue_fence_wait(&iter
->ready
);
2181 if (iter
->compilation_failed
) {
2182 return -1; /* skip the draw call */
2185 state
->current
= iter
;
2190 /* Build a new shader. */
2191 shader
= CALLOC_STRUCT(si_shader
);
2193 mtx_unlock(&sel
->mutex
);
2197 util_queue_fence_init(&shader
->ready
);
2199 shader
->selector
= sel
;
2201 shader
->compiler_ctx_state
= *compiler_state
;
2203 /* If this is a merged shader, get the first shader's selector. */
2204 if (sscreen
->info
.chip_class
>= GFX9
) {
2205 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
2206 previous_stage_sel
= key
->part
.tcs
.ls
;
2207 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
2208 previous_stage_sel
= key
->part
.gs
.es
;
2210 /* We need to wait for the previous shader. */
2211 if (previous_stage_sel
&& thread_index
< 0)
2212 util_queue_fence_wait(&previous_stage_sel
->ready
);
2215 bool is_pure_monolithic
=
2216 sscreen
->use_monolithic_shaders
||
2217 memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
2219 /* Compile the main shader part if it doesn't exist. This can happen
2220 * if the initial guess was wrong.
2222 * The prim discard CS doesn't need the main shader part.
2224 if (!is_pure_monolithic
&&
2225 !key
->opt
.vs_as_prim_discard_cs
) {
2228 /* Make sure the main shader part is present. This is needed
2229 * for shaders that can be compiled as VS, LS, or ES, and only
2230 * one of them is compiled at creation.
2232 * It is also needed for GS, which can be compiled as non-NGG
2235 * For merged shaders, check that the starting shader's main
2238 if (previous_stage_sel
) {
2239 struct si_shader_key shader1_key
= zeroed
;
2241 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
2242 shader1_key
.as_ls
= 1;
2243 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
2244 shader1_key
.as_es
= 1;
2248 mtx_lock(&previous_stage_sel
->mutex
);
2249 ok
= si_check_missing_main_part(sscreen
,
2251 compiler_state
, &shader1_key
);
2252 mtx_unlock(&previous_stage_sel
->mutex
);
2256 ok
= si_check_missing_main_part(sscreen
, sel
,
2257 compiler_state
, key
);
2262 mtx_unlock(&sel
->mutex
);
2263 return -ENOMEM
; /* skip the draw call */
2267 /* Keep the reference to the 1st shader of merged shaders, so that
2268 * Gallium can't destroy it before we destroy the 2nd shader.
2270 * Set sctx = NULL, because it's unused if we're not releasing
2271 * the shader, and we don't have any sctx here.
2273 si_shader_selector_reference(NULL
, &shader
->previous_stage_sel
,
2274 previous_stage_sel
);
2276 /* Monolithic-only shaders don't make a distinction between optimized
2277 * and unoptimized. */
2278 shader
->is_monolithic
=
2279 is_pure_monolithic
||
2280 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
2282 /* The prim discard CS is always optimized. */
2283 shader
->is_optimized
=
2284 (!is_pure_monolithic
|| key
->opt
.vs_as_prim_discard_cs
) &&
2285 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
2287 /* If it's an optimized shader, compile it asynchronously. */
2288 if (shader
->is_optimized
&& thread_index
< 0) {
2289 /* Compile it asynchronously. */
2290 util_queue_add_job(&sscreen
->shader_compiler_queue_low_priority
,
2291 shader
, &shader
->ready
,
2292 si_build_shader_variant_low_priority
, NULL
);
2294 /* Add only after the ready fence was reset, to guard against a
2295 * race with si_bind_XX_shader. */
2296 if (!sel
->last_variant
) {
2297 sel
->first_variant
= shader
;
2298 sel
->last_variant
= shader
;
2300 sel
->last_variant
->next_variant
= shader
;
2301 sel
->last_variant
= shader
;
2304 /* Use the default (unoptimized) shader for now. */
2305 memset(&key
->opt
, 0, sizeof(key
->opt
));
2306 mtx_unlock(&sel
->mutex
);
2308 if (sscreen
->options
.sync_compile
)
2309 util_queue_fence_wait(&shader
->ready
);
2311 if (optimized_or_none
)
2316 /* Reset the fence before adding to the variant list. */
2317 util_queue_fence_reset(&shader
->ready
);
2319 if (!sel
->last_variant
) {
2320 sel
->first_variant
= shader
;
2321 sel
->last_variant
= shader
;
2323 sel
->last_variant
->next_variant
= shader
;
2324 sel
->last_variant
= shader
;
2327 mtx_unlock(&sel
->mutex
);
2329 assert(!shader
->is_optimized
);
2330 si_build_shader_variant(shader
, thread_index
, false);
2332 util_queue_fence_signal(&shader
->ready
);
2334 if (!shader
->compilation_failed
)
2335 state
->current
= shader
;
2337 return shader
->compilation_failed
? -1 : 0;
2340 static int si_shader_select(struct pipe_context
*ctx
,
2341 struct si_shader_ctx_state
*state
,
2342 union si_vgt_stages_key stages_key
,
2343 struct si_compiler_ctx_state
*compiler_state
)
2345 struct si_context
*sctx
= (struct si_context
*)ctx
;
2346 struct si_shader_key key
;
2348 si_shader_selector_key(ctx
, state
->cso
, stages_key
, &key
);
2349 return si_shader_select_with_key(sctx
->screen
, state
, compiler_state
,
2353 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
2355 struct si_shader_key
*key
)
2357 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
2359 switch (info
->processor
) {
2360 case PIPE_SHADER_VERTEX
:
2361 switch (next_shader
) {
2362 case PIPE_SHADER_GEOMETRY
:
2365 case PIPE_SHADER_TESS_CTRL
:
2366 case PIPE_SHADER_TESS_EVAL
:
2370 /* If POSITION isn't written, it can only be a HW VS
2371 * if streamout is used. If streamout isn't used,
2372 * assume that it's a HW LS. (the next shader is TCS)
2373 * This heuristic is needed for separate shader objects.
2375 if (!info
->writes_position
&& !streamout
)
2380 case PIPE_SHADER_TESS_EVAL
:
2381 if (next_shader
== PIPE_SHADER_GEOMETRY
||
2382 !info
->writes_position
)
2389 * Compile the main shader part or the monolithic shader as part of
2390 * si_shader_selector initialization. Since it can be done asynchronously,
2391 * there is no way to report compile failures to applications.
2393 static void si_init_shader_selector_async(void *job
, int thread_index
)
2395 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
2396 struct si_screen
*sscreen
= sel
->screen
;
2397 struct ac_llvm_compiler
*compiler
;
2398 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
2400 assert(!debug
->debug_message
|| debug
->async
);
2401 assert(thread_index
>= 0);
2402 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
2403 compiler
= &sscreen
->compiler
[thread_index
];
2408 /* Compile the main shader part for use with a prolog and/or epilog.
2409 * If this fails, the driver will try to compile a monolithic shader
2412 if (!sscreen
->use_monolithic_shaders
) {
2413 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
2414 void *ir_binary
= NULL
;
2417 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
2421 /* We can leave the fence signaled because use of the default
2422 * main part is guarded by the selector's ready fence. */
2423 util_queue_fence_init(&shader
->ready
);
2425 shader
->selector
= sel
;
2426 shader
->is_monolithic
= false;
2427 si_parse_next_shader_property(&sel
->info
,
2428 sel
->so
.num_outputs
!= 0,
2430 if (sscreen
->info
.chip_class
>= GFX10
&&
2431 !sscreen
->options
.disable_ngg
&&
2432 (((sel
->type
== PIPE_SHADER_VERTEX
||
2433 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
2434 !shader
->key
.as_ls
&& !shader
->key
.as_es
) ||
2435 sel
->type
== PIPE_SHADER_GEOMETRY
))
2436 shader
->key
.as_ngg
= 1;
2438 if (sel
->tokens
|| sel
->nir
)
2439 ir_binary
= si_get_ir_binary(sel
);
2441 /* Try to load the shader from the shader cache. */
2442 mtx_lock(&sscreen
->shader_cache_mutex
);
2445 si_shader_cache_load_shader(sscreen
, ir_binary
, shader
)) {
2446 mtx_unlock(&sscreen
->shader_cache_mutex
);
2447 si_shader_dump_stats_for_shader_db(sscreen
, shader
, debug
);
2449 mtx_unlock(&sscreen
->shader_cache_mutex
);
2451 /* Compile the shader if it hasn't been loaded from the cache. */
2452 if (si_compile_tgsi_shader(sscreen
, compiler
, shader
,
2456 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
2461 mtx_lock(&sscreen
->shader_cache_mutex
);
2462 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
, shader
, true))
2464 mtx_unlock(&sscreen
->shader_cache_mutex
);
2468 *si_get_main_shader_part(sel
, &shader
->key
) = shader
;
2470 /* Unset "outputs_written" flags for outputs converted to
2471 * DEFAULT_VAL, so that later inter-shader optimizations don't
2472 * try to eliminate outputs that don't exist in the final
2475 * This is only done if non-monolithic shaders are enabled.
2477 if ((sel
->type
== PIPE_SHADER_VERTEX
||
2478 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
2479 !shader
->key
.as_ls
&&
2480 !shader
->key
.as_es
) {
2483 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2484 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
2486 if (offset
<= AC_EXP_PARAM_OFFSET_31
)
2489 unsigned name
= sel
->info
.output_semantic_name
[i
];
2490 unsigned index
= sel
->info
.output_semantic_index
[i
];
2494 case TGSI_SEMANTIC_GENERIC
:
2495 /* don't process indices the function can't handle */
2496 if (index
>= SI_MAX_IO_GENERIC
)
2500 id
= si_shader_io_get_unique_index(name
, index
, true);
2501 sel
->outputs_written_before_ps
&= ~(1ull << id
);
2503 case TGSI_SEMANTIC_POSITION
: /* ignore these */
2504 case TGSI_SEMANTIC_PSIZE
:
2505 case TGSI_SEMANTIC_CLIPVERTEX
:
2506 case TGSI_SEMANTIC_EDGEFLAG
:
2513 /* The GS copy shader is always pre-compiled.
2515 * TODO-GFX10: We could compile the GS copy shader on demand, since it
2516 * is only used in the (rare) non-NGG case.
2518 if (sel
->type
== PIPE_SHADER_GEOMETRY
) {
2519 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, compiler
, sel
, debug
);
2520 if (!sel
->gs_copy_shader
) {
2521 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
2525 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
2529 void si_schedule_initial_compile(struct si_context
*sctx
, unsigned processor
,
2530 struct util_queue_fence
*ready_fence
,
2531 struct si_compiler_ctx_state
*compiler_ctx_state
,
2532 void *job
, util_queue_execute_func execute
)
2534 util_queue_fence_init(ready_fence
);
2536 struct util_async_debug_callback async_debug
;
2538 (sctx
->debug
.debug_message
&& !sctx
->debug
.async
) ||
2540 si_can_dump_shader(sctx
->screen
, processor
);
2543 u_async_debug_init(&async_debug
);
2544 compiler_ctx_state
->debug
= async_debug
.base
;
2547 util_queue_add_job(&sctx
->screen
->shader_compiler_queue
, job
,
2548 ready_fence
, execute
, NULL
);
2551 util_queue_fence_wait(ready_fence
);
2552 u_async_debug_drain(&async_debug
, &sctx
->debug
);
2553 u_async_debug_cleanup(&async_debug
);
2556 if (sctx
->screen
->options
.sync_compile
)
2557 util_queue_fence_wait(ready_fence
);
2560 /* Return descriptor slot usage masks from the given shader info. */
2561 void si_get_active_slot_masks(const struct tgsi_shader_info
*info
,
2562 uint32_t *const_and_shader_buffers
,
2563 uint64_t *samplers_and_images
)
2565 unsigned start
, num_shaderbufs
, num_constbufs
, num_images
, num_samplers
;
2567 num_shaderbufs
= util_last_bit(info
->shader_buffers_declared
);
2568 num_constbufs
= util_last_bit(info
->const_buffers_declared
);
2569 /* two 8-byte images share one 16-byte slot */
2570 num_images
= align(util_last_bit(info
->images_declared
), 2);
2571 num_samplers
= util_last_bit(info
->samplers_declared
);
2573 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2574 start
= si_get_shaderbuf_slot(num_shaderbufs
- 1);
2575 *const_and_shader_buffers
=
2576 u_bit_consecutive(start
, num_shaderbufs
+ num_constbufs
);
2578 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2579 start
= si_get_image_slot(num_images
- 1) / 2;
2580 *samplers_and_images
=
2581 u_bit_consecutive64(start
, num_images
/ 2 + num_samplers
);
2584 static void *si_create_shader_selector(struct pipe_context
*ctx
,
2585 const struct pipe_shader_state
*state
)
2587 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
2588 struct si_context
*sctx
= (struct si_context
*)ctx
;
2589 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
2595 pipe_reference_init(&sel
->reference
, 1);
2596 sel
->screen
= sscreen
;
2597 sel
->compiler_ctx_state
.debug
= sctx
->debug
;
2598 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
2600 sel
->so
= state
->stream_output
;
2602 if (state
->type
== PIPE_SHADER_IR_TGSI
) {
2603 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
2609 tgsi_scan_shader(state
->tokens
, &sel
->info
);
2610 tgsi_scan_tess_ctrl(state
->tokens
, &sel
->info
, &sel
->tcs_info
);
2612 assert(state
->type
== PIPE_SHADER_IR_NIR
);
2614 sel
->nir
= state
->ir
.nir
;
2616 si_nir_opts(sel
->nir
);
2617 si_nir_scan_shader(sel
->nir
, &sel
->info
);
2618 si_nir_scan_tess_ctrl(sel
->nir
, &sel
->tcs_info
);
2621 sel
->type
= sel
->info
.processor
;
2622 p_atomic_inc(&sscreen
->num_shaders_created
);
2623 si_get_active_slot_masks(&sel
->info
,
2624 &sel
->active_const_and_shader_buffers
,
2625 &sel
->active_samplers_and_images
);
2627 /* Record which streamout buffers are enabled. */
2628 for (i
= 0; i
< sel
->so
.num_outputs
; i
++) {
2629 sel
->enabled_streamout_buffer_mask
|=
2630 (1 << sel
->so
.output
[i
].output_buffer
) <<
2631 (sel
->so
.output
[i
].stream
* 4);
2634 /* The prolog is a no-op if there are no inputs. */
2635 sel
->vs_needs_prolog
= sel
->type
== PIPE_SHADER_VERTEX
&&
2636 sel
->info
.num_inputs
&&
2637 !sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
2639 sel
->force_correct_derivs_after_kill
=
2640 sel
->type
== PIPE_SHADER_FRAGMENT
&&
2641 sel
->info
.uses_derivatives
&&
2642 sel
->info
.uses_kill
&&
2643 sctx
->screen
->debug_flags
& DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
2645 sel
->prim_discard_cs_allowed
=
2646 sel
->type
== PIPE_SHADER_VERTEX
&&
2647 !sel
->info
.uses_bindless_images
&&
2648 !sel
->info
.uses_bindless_samplers
&&
2649 !sel
->info
.writes_memory
&&
2650 !sel
->info
.writes_viewport_index
&&
2651 !sel
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] &&
2652 !sel
->so
.num_outputs
;
2654 /* Set which opcode uses which (i,j) pair. */
2655 if (sel
->info
.uses_persp_opcode_interp_centroid
)
2656 sel
->info
.uses_persp_centroid
= true;
2658 if (sel
->info
.uses_linear_opcode_interp_centroid
)
2659 sel
->info
.uses_linear_centroid
= true;
2661 if (sel
->info
.uses_persp_opcode_interp_offset
||
2662 sel
->info
.uses_persp_opcode_interp_sample
)
2663 sel
->info
.uses_persp_center
= true;
2665 if (sel
->info
.uses_linear_opcode_interp_offset
||
2666 sel
->info
.uses_linear_opcode_interp_sample
)
2667 sel
->info
.uses_linear_center
= true;
2669 switch (sel
->type
) {
2670 case PIPE_SHADER_GEOMETRY
:
2671 sel
->gs_output_prim
=
2672 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
2673 sel
->gs_max_out_vertices
=
2674 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
2675 sel
->gs_num_invocations
=
2676 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
2677 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
2678 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
2679 sel
->gs_max_out_vertices
;
2681 sel
->max_gs_stream
= 0;
2682 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
2683 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
2684 sel
->so
.output
[i
].stream
);
2686 sel
->gs_input_verts_per_prim
=
2687 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
2690 case PIPE_SHADER_TESS_CTRL
:
2691 /* Always reserve space for these. */
2692 sel
->patch_outputs_written
|=
2693 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0)) |
2694 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0));
2696 case PIPE_SHADER_VERTEX
:
2697 case PIPE_SHADER_TESS_EVAL
:
2698 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2699 unsigned name
= sel
->info
.output_semantic_name
[i
];
2700 unsigned index
= sel
->info
.output_semantic_index
[i
];
2703 case TGSI_SEMANTIC_TESSINNER
:
2704 case TGSI_SEMANTIC_TESSOUTER
:
2705 case TGSI_SEMANTIC_PATCH
:
2706 sel
->patch_outputs_written
|=
2707 1ull << si_shader_io_get_unique_index_patch(name
, index
);
2710 case TGSI_SEMANTIC_GENERIC
:
2711 /* don't process indices the function can't handle */
2712 if (index
>= SI_MAX_IO_GENERIC
)
2716 sel
->outputs_written
|=
2717 1ull << si_shader_io_get_unique_index(name
, index
, false);
2718 sel
->outputs_written_before_ps
|=
2719 1ull << si_shader_io_get_unique_index(name
, index
, true);
2721 case TGSI_SEMANTIC_EDGEFLAG
:
2725 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
2726 sel
->lshs_vertex_stride
= sel
->esgs_itemsize
;
2728 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2729 * will start on a different bank. (except for the maximum 32*16).
2731 if (sel
->lshs_vertex_stride
< 32*16)
2732 sel
->lshs_vertex_stride
+= 4;
2734 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2735 * conflicts, i.e. each vertex will start at a different bank.
2737 if (sctx
->chip_class
>= GFX9
)
2738 sel
->esgs_itemsize
+= 4;
2740 assert(((sel
->esgs_itemsize
/ 4) & C_028AAC_ITEMSIZE
) == 0);
2743 case PIPE_SHADER_FRAGMENT
:
2744 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2745 unsigned name
= sel
->info
.input_semantic_name
[i
];
2746 unsigned index
= sel
->info
.input_semantic_index
[i
];
2749 case TGSI_SEMANTIC_GENERIC
:
2750 /* don't process indices the function can't handle */
2751 if (index
>= SI_MAX_IO_GENERIC
)
2756 1ull << si_shader_io_get_unique_index(name
, index
, true);
2758 case TGSI_SEMANTIC_PCOORD
: /* ignore this */
2763 for (i
= 0; i
< 8; i
++)
2764 if (sel
->info
.colors_written
& (1 << i
))
2765 sel
->colors_written_4bit
|= 0xf << (4 * i
);
2767 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2768 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
2769 int index
= sel
->info
.input_semantic_index
[i
];
2770 sel
->color_attr_index
[index
] = i
;
2776 /* PA_CL_VS_OUT_CNTL */
2778 sel
->info
.writes_psize
|| sel
->info
.writes_edgeflag
||
2779 sel
->info
.writes_layer
|| sel
->info
.writes_viewport_index
;
2780 sel
->pa_cl_vs_out_cntl
=
2781 S_02881C_USE_VTX_POINT_SIZE(sel
->info
.writes_psize
) |
2782 S_02881C_USE_VTX_EDGE_FLAG(sel
->info
.writes_edgeflag
) |
2783 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel
->info
.writes_layer
) |
2784 S_02881C_USE_VTX_VIEWPORT_INDX(sel
->info
.writes_viewport_index
) |
2785 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
2786 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
);
2787 sel
->clipdist_mask
= sel
->info
.writes_clipvertex
?
2788 SIX_BITS
: sel
->info
.clipdist_writemask
;
2789 sel
->culldist_mask
= sel
->info
.culldist_writemask
<<
2790 sel
->info
.num_written_clipdistance
;
2792 /* DB_SHADER_CONTROL */
2793 sel
->db_shader_control
=
2794 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
2795 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
2796 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
2797 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
2799 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
2800 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2801 sel
->db_shader_control
|=
2802 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2804 case TGSI_FS_DEPTH_LAYOUT_LESS
:
2805 sel
->db_shader_control
|=
2806 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2810 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2812 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2813 * --|-----------|------------|------------|--------------------|-------------------|-------------
2814 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2815 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2816 * 2 | false | true | n/a | LateZ | 1 | 0
2817 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2818 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2820 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2821 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2823 * Don't use ReZ without profiling !!!
2825 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2828 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
2830 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
2831 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
2832 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
2833 } else if (sel
->info
.writes_memory
) {
2835 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) |
2836 S_02880C_EXEC_ON_HIER_FAIL(1);
2839 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2842 (void) mtx_init(&sel
->mutex
, mtx_plain
);
2844 si_schedule_initial_compile(sctx
, sel
->info
.processor
, &sel
->ready
,
2845 &sel
->compiler_ctx_state
, sel
,
2846 si_init_shader_selector_async
);
2850 static void si_update_streamout_state(struct si_context
*sctx
)
2852 struct si_shader_selector
*shader_with_so
= si_get_vs(sctx
)->cso
;
2854 if (!shader_with_so
)
2857 sctx
->streamout
.enabled_stream_buffers_mask
=
2858 shader_with_so
->enabled_streamout_buffer_mask
;
2859 sctx
->streamout
.stride_in_dw
= shader_with_so
->so
.stride
;
2862 static void si_update_clip_regs(struct si_context
*sctx
,
2863 struct si_shader_selector
*old_hw_vs
,
2864 struct si_shader
*old_hw_vs_variant
,
2865 struct si_shader_selector
*next_hw_vs
,
2866 struct si_shader
*next_hw_vs_variant
)
2870 old_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] !=
2871 next_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] ||
2872 old_hw_vs
->pa_cl_vs_out_cntl
!= next_hw_vs
->pa_cl_vs_out_cntl
||
2873 old_hw_vs
->clipdist_mask
!= next_hw_vs
->clipdist_mask
||
2874 old_hw_vs
->culldist_mask
!= next_hw_vs
->culldist_mask
||
2875 !old_hw_vs_variant
||
2876 !next_hw_vs_variant
||
2877 old_hw_vs_variant
->key
.opt
.clip_disable
!=
2878 next_hw_vs_variant
->key
.opt
.clip_disable
))
2879 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
2882 static void si_update_common_shader_state(struct si_context
*sctx
)
2884 sctx
->uses_bindless_samplers
=
2885 si_shader_uses_bindless_samplers(sctx
->vs_shader
.cso
) ||
2886 si_shader_uses_bindless_samplers(sctx
->gs_shader
.cso
) ||
2887 si_shader_uses_bindless_samplers(sctx
->ps_shader
.cso
) ||
2888 si_shader_uses_bindless_samplers(sctx
->tcs_shader
.cso
) ||
2889 si_shader_uses_bindless_samplers(sctx
->tes_shader
.cso
);
2890 sctx
->uses_bindless_images
=
2891 si_shader_uses_bindless_images(sctx
->vs_shader
.cso
) ||
2892 si_shader_uses_bindless_images(sctx
->gs_shader
.cso
) ||
2893 si_shader_uses_bindless_images(sctx
->ps_shader
.cso
) ||
2894 si_shader_uses_bindless_images(sctx
->tcs_shader
.cso
) ||
2895 si_shader_uses_bindless_images(sctx
->tes_shader
.cso
);
2896 sctx
->do_update_shaders
= true;
2899 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
2901 struct si_context
*sctx
= (struct si_context
*)ctx
;
2902 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2903 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2904 struct si_shader_selector
*sel
= state
;
2906 if (sctx
->vs_shader
.cso
== sel
)
2909 sctx
->vs_shader
.cso
= sel
;
2910 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2911 sctx
->num_vs_blit_sgprs
= sel
? sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
] : 0;
2913 si_update_common_shader_state(sctx
);
2914 si_update_vs_viewport_state(sctx
);
2915 si_set_active_descriptors_for_shader(sctx
, sel
);
2916 si_update_streamout_state(sctx
);
2917 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2918 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2921 static void si_update_tess_uses_prim_id(struct si_context
*sctx
)
2923 sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
=
2924 (sctx
->tes_shader
.cso
&&
2925 sctx
->tes_shader
.cso
->info
.uses_primid
) ||
2926 (sctx
->tcs_shader
.cso
&&
2927 sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
2928 (sctx
->gs_shader
.cso
&&
2929 sctx
->gs_shader
.cso
->info
.uses_primid
) ||
2930 (sctx
->ps_shader
.cso
&& !sctx
->gs_shader
.cso
&&
2931 sctx
->ps_shader
.cso
->info
.uses_primid
);
2934 static bool si_update_ngg(struct si_context
*sctx
)
2936 if (sctx
->chip_class
<= GFX9
||
2937 sctx
->screen
->options
.disable_ngg
)
2940 bool new_ngg
= true;
2942 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2943 if (sctx
->gs_shader
.cso
&& sctx
->tes_shader
.cso
&&
2944 sctx
->gs_shader
.cso
->gs_num_invocations
* sctx
->gs_shader
.cso
->gs_max_out_vertices
> 256)
2947 if (new_ngg
!= sctx
->ngg
) {
2948 sctx
->ngg
= new_ngg
;
2949 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2955 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
2957 struct si_context
*sctx
= (struct si_context
*)ctx
;
2958 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2959 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2960 struct si_shader_selector
*sel
= state
;
2961 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
2964 if (sctx
->gs_shader
.cso
== sel
)
2967 sctx
->gs_shader
.cso
= sel
;
2968 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2969 sctx
->ia_multi_vgt_param_key
.u
.uses_gs
= sel
!= NULL
;
2971 si_update_common_shader_state(sctx
);
2972 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2974 ngg_changed
= si_update_ngg(sctx
);
2975 if (ngg_changed
|| enable_changed
)
2976 si_shader_change_notify(sctx
);
2977 if (enable_changed
) {
2978 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2979 si_update_tess_uses_prim_id(sctx
);
2981 si_update_vs_viewport_state(sctx
);
2982 si_set_active_descriptors_for_shader(sctx
, sel
);
2983 si_update_streamout_state(sctx
);
2984 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2985 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2988 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
2990 struct si_context
*sctx
= (struct si_context
*)ctx
;
2991 struct si_shader_selector
*sel
= state
;
2992 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
2994 if (sctx
->tcs_shader
.cso
== sel
)
2997 sctx
->tcs_shader
.cso
= sel
;
2998 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2999 si_update_tess_uses_prim_id(sctx
);
3001 si_update_common_shader_state(sctx
);
3004 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
3006 si_set_active_descriptors_for_shader(sctx
, sel
);
3009 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
3011 struct si_context
*sctx
= (struct si_context
*)ctx
;
3012 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
3013 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
3014 struct si_shader_selector
*sel
= state
;
3015 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
3017 if (sctx
->tes_shader
.cso
== sel
)
3020 sctx
->tes_shader
.cso
= sel
;
3021 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
3022 sctx
->ia_multi_vgt_param_key
.u
.uses_tess
= sel
!= NULL
;
3023 si_update_tess_uses_prim_id(sctx
);
3025 si_update_common_shader_state(sctx
);
3026 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
3028 if (enable_changed
) {
3029 si_update_ngg(sctx
);
3030 si_shader_change_notify(sctx
);
3031 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
3033 si_update_vs_viewport_state(sctx
);
3034 si_set_active_descriptors_for_shader(sctx
, sel
);
3035 si_update_streamout_state(sctx
);
3036 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
3037 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
3040 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
3042 struct si_context
*sctx
= (struct si_context
*)ctx
;
3043 struct si_shader_selector
*old_sel
= sctx
->ps_shader
.cso
;
3044 struct si_shader_selector
*sel
= state
;
3046 /* skip if supplied shader is one already in use */
3050 sctx
->ps_shader
.cso
= sel
;
3051 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
3053 si_update_common_shader_state(sctx
);
3055 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
3056 si_update_tess_uses_prim_id(sctx
);
3059 old_sel
->info
.colors_written
!= sel
->info
.colors_written
)
3060 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3062 if (sctx
->screen
->has_out_of_order_rast
&&
3064 old_sel
->info
.writes_memory
!= sel
->info
.writes_memory
||
3065 old_sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] !=
3066 sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]))
3067 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3069 si_set_active_descriptors_for_shader(sctx
, sel
);
3070 si_update_ps_colorbuf0_slot(sctx
);
3073 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
3075 if (shader
->is_optimized
) {
3076 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue_low_priority
,
3080 util_queue_fence_destroy(&shader
->ready
);
3083 /* If destroyed shaders were not unbound, the next compiled
3084 * shader variant could get the same pointer address and so
3085 * binding it to the same shader stage would be considered
3086 * a no-op, causing random behavior.
3088 switch (shader
->selector
->type
) {
3089 case PIPE_SHADER_VERTEX
:
3090 if (shader
->key
.as_ls
) {
3091 assert(sctx
->chip_class
<= GFX8
);
3092 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
3093 } else if (shader
->key
.as_es
) {
3094 assert(sctx
->chip_class
<= GFX8
);
3095 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
3096 } else if (shader
->key
.as_ngg
) {
3097 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3099 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3102 case PIPE_SHADER_TESS_CTRL
:
3103 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
3105 case PIPE_SHADER_TESS_EVAL
:
3106 if (shader
->key
.as_es
) {
3107 assert(sctx
->chip_class
<= GFX8
);
3108 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
3109 } else if (shader
->key
.as_ngg
) {
3110 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3112 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3115 case PIPE_SHADER_GEOMETRY
:
3116 if (shader
->is_gs_copy_shader
)
3117 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3119 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3121 case PIPE_SHADER_FRAGMENT
:
3122 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
3127 si_shader_selector_reference(sctx
, &shader
->previous_stage_sel
, NULL
);
3128 si_shader_destroy(shader
);
3132 void si_destroy_shader_selector(struct si_context
*sctx
,
3133 struct si_shader_selector
*sel
)
3135 struct si_shader
*p
= sel
->first_variant
, *c
;
3136 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
3137 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
3138 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
3139 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
3140 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
3141 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
3144 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue
, &sel
->ready
);
3146 if (current_shader
[sel
->type
]->cso
== sel
) {
3147 current_shader
[sel
->type
]->cso
= NULL
;
3148 current_shader
[sel
->type
]->current
= NULL
;
3152 c
= p
->next_variant
;
3153 si_delete_shader(sctx
, p
);
3157 if (sel
->main_shader_part
)
3158 si_delete_shader(sctx
, sel
->main_shader_part
);
3159 if (sel
->main_shader_part_ls
)
3160 si_delete_shader(sctx
, sel
->main_shader_part_ls
);
3161 if (sel
->main_shader_part_es
)
3162 si_delete_shader(sctx
, sel
->main_shader_part_es
);
3163 if (sel
->main_shader_part_ngg
)
3164 si_delete_shader(sctx
, sel
->main_shader_part_ngg
);
3165 if (sel
->gs_copy_shader
)
3166 si_delete_shader(sctx
, sel
->gs_copy_shader
);
3168 util_queue_fence_destroy(&sel
->ready
);
3169 mtx_destroy(&sel
->mutex
);
3171 ralloc_free(sel
->nir
);
3175 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
3177 struct si_context
*sctx
= (struct si_context
*)ctx
;
3178 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
3180 si_shader_selector_reference(sctx
, &sel
, NULL
);
3183 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
3184 struct si_shader
*vs
, unsigned name
,
3185 unsigned index
, unsigned interpolate
)
3187 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
3188 unsigned j
, offset
, ps_input_cntl
= 0;
3190 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
3191 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
) ||
3192 name
== TGSI_SEMANTIC_PRIMID
)
3193 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
3195 if (name
== TGSI_SEMANTIC_PCOORD
||
3196 (name
== TGSI_SEMANTIC_TEXCOORD
&&
3197 sctx
->sprite_coord_enable
& (1 << index
))) {
3198 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
3201 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
3202 if (name
== vsinfo
->output_semantic_name
[j
] &&
3203 index
== vsinfo
->output_semantic_index
[j
]) {
3204 offset
= vs
->info
.vs_output_param_offset
[j
];
3206 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
3207 /* The input is loaded from parameter memory. */
3208 ps_input_cntl
|= S_028644_OFFSET(offset
);
3209 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
3210 if (offset
== AC_EXP_PARAM_UNDEFINED
) {
3211 /* This can happen with depth-only rendering. */
3214 /* The input is a DEFAULT_VAL constant. */
3215 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
3216 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
3217 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
3220 ps_input_cntl
= S_028644_OFFSET(0x20) |
3221 S_028644_DEFAULT_VAL(offset
);
3227 if (j
== vsinfo
->num_outputs
&& name
== TGSI_SEMANTIC_PRIMID
)
3228 /* PrimID is written after the last output when HW VS is used. */
3229 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
3230 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
3231 /* No corresponding output found, load defaults into input.
3232 * Don't set any other bits.
3233 * (FLAT_SHADE=1 completely changes behavior) */
3234 ps_input_cntl
= S_028644_OFFSET(0x20);
3235 /* D3D 9 behaviour. GL is undefined */
3236 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
3237 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
3239 return ps_input_cntl
;
3242 static void si_emit_spi_map(struct si_context
*sctx
)
3244 struct si_shader
*ps
= sctx
->ps_shader
.current
;
3245 struct si_shader
*vs
= si_get_vs_state(sctx
);
3246 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
3247 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
3248 unsigned spi_ps_input_cntl
[32];
3250 if (!ps
|| !ps
->selector
->info
.num_inputs
)
3253 num_interp
= si_get_ps_num_interp(ps
);
3254 assert(num_interp
> 0);
3256 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
3257 unsigned name
= psinfo
->input_semantic_name
[i
];
3258 unsigned index
= psinfo
->input_semantic_index
[i
];
3259 unsigned interpolate
= psinfo
->input_interpolate
[i
];
3261 spi_ps_input_cntl
[num_written
++] = si_get_ps_input_cntl(sctx
, vs
, name
,
3262 index
, interpolate
);
3264 if (name
== TGSI_SEMANTIC_COLOR
) {
3265 assert(index
< ARRAY_SIZE(bcol_interp
));
3266 bcol_interp
[index
] = interpolate
;
3270 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
3271 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
3273 for (i
= 0; i
< 2; i
++) {
3274 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
3277 spi_ps_input_cntl
[num_written
++] =
3278 si_get_ps_input_cntl(sctx
, vs
, bcol
, i
, bcol_interp
[i
]);
3282 assert(num_interp
== num_written
);
3284 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3285 /* Dota 2: Only ~16% of SPI map updates set different values. */
3286 /* Talos: Only ~9% of SPI map updates set different values. */
3287 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
3288 radeon_opt_set_context_regn(sctx
, R_028644_SPI_PS_INPUT_CNTL_0
,
3290 sctx
->tracked_regs
.spi_ps_input_cntl
, num_interp
);
3292 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
3293 sctx
->context_roll
= true;
3297 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3299 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
3301 if (sctx
->init_config_has_vgt_flush
)
3304 /* Done by Vulkan before VGT_FLUSH. */
3305 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
3306 si_pm4_cmd_add(sctx
->init_config
,
3307 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3308 si_pm4_cmd_end(sctx
->init_config
, false);
3310 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3311 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
3312 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
3313 si_pm4_cmd_end(sctx
->init_config
, false);
3314 sctx
->init_config_has_vgt_flush
= true;
3317 /* Initialize state related to ESGS / GSVS ring buffers */
3318 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
3320 struct si_shader_selector
*es
=
3321 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
3322 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
3323 struct si_pm4_state
*pm4
;
3325 /* Chip constants. */
3326 unsigned num_se
= sctx
->screen
->info
.max_se
;
3327 unsigned wave_size
= 64;
3328 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
3329 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3330 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3332 unsigned gs_vertex_reuse
= (sctx
->chip_class
>= GFX8
? 32 : 16) * num_se
;
3333 unsigned alignment
= 256 * num_se
;
3334 /* The maximum size is 63.999 MB per SE. */
3335 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
3337 /* Calculate the minimum size. */
3338 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
3339 wave_size
, alignment
);
3341 /* These are recommended sizes, not minimum sizes. */
3342 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
3343 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
3344 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
3345 gs
->max_gsvs_emit_size
;
3347 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
3348 esgs_ring_size
= align(esgs_ring_size
, alignment
);
3349 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
3351 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
3352 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
3354 /* Some rings don't have to be allocated if shaders don't use them.
3355 * (e.g. no varyings between ES and GS or GS and VS)
3357 * GFX9 doesn't have the ESGS ring.
3359 bool update_esgs
= sctx
->chip_class
<= GFX8
&&
3361 (!sctx
->esgs_ring
||
3362 sctx
->esgs_ring
->width0
< esgs_ring_size
);
3363 bool update_gsvs
= gsvs_ring_size
&&
3364 (!sctx
->gsvs_ring
||
3365 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
3367 if (!update_esgs
&& !update_gsvs
)
3371 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
3373 pipe_aligned_buffer_create(sctx
->b
.screen
,
3374 SI_RESOURCE_FLAG_UNMAPPABLE
,
3376 esgs_ring_size
, alignment
);
3377 if (!sctx
->esgs_ring
)
3382 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
3384 pipe_aligned_buffer_create(sctx
->b
.screen
,
3385 SI_RESOURCE_FLAG_UNMAPPABLE
,
3387 gsvs_ring_size
, alignment
);
3388 if (!sctx
->gsvs_ring
)
3392 /* Create the "init_config_gs_rings" state. */
3393 pm4
= CALLOC_STRUCT(si_pm4_state
);
3397 if (sctx
->chip_class
>= GFX7
) {
3398 if (sctx
->esgs_ring
) {
3399 assert(sctx
->chip_class
<= GFX8
);
3400 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
3401 sctx
->esgs_ring
->width0
/ 256);
3403 if (sctx
->gsvs_ring
)
3404 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
3405 sctx
->gsvs_ring
->width0
/ 256);
3407 if (sctx
->esgs_ring
)
3408 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
3409 sctx
->esgs_ring
->width0
/ 256);
3410 if (sctx
->gsvs_ring
)
3411 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
3412 sctx
->gsvs_ring
->width0
/ 256);
3415 /* Set the state. */
3416 if (sctx
->init_config_gs_rings
)
3417 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
3418 sctx
->init_config_gs_rings
= pm4
;
3420 if (!sctx
->init_config_has_vgt_flush
) {
3421 si_init_config_add_vgt_flush(sctx
);
3422 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3425 /* Flush the context to re-emit both init_config states. */
3426 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3427 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3429 /* Set ring bindings. */
3430 if (sctx
->esgs_ring
) {
3431 assert(sctx
->chip_class
<= GFX8
);
3432 si_set_ring_buffer(sctx
, SI_ES_RING_ESGS
,
3433 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
3434 true, true, 4, 64, 0);
3435 si_set_ring_buffer(sctx
, SI_GS_RING_ESGS
,
3436 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
3437 false, false, 0, 0, 0);
3439 if (sctx
->gsvs_ring
) {
3440 si_set_ring_buffer(sctx
, SI_RING_GSVS
,
3441 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
3442 false, false, 0, 0, 0);
3448 static void si_shader_lock(struct si_shader
*shader
)
3450 mtx_lock(&shader
->selector
->mutex
);
3451 if (shader
->previous_stage_sel
) {
3452 assert(shader
->previous_stage_sel
!= shader
->selector
);
3453 mtx_lock(&shader
->previous_stage_sel
->mutex
);
3457 static void si_shader_unlock(struct si_shader
*shader
)
3459 if (shader
->previous_stage_sel
)
3460 mtx_unlock(&shader
->previous_stage_sel
->mutex
);
3461 mtx_unlock(&shader
->selector
->mutex
);
3465 * @returns 1 if \p sel has been updated to use a new scratch buffer
3467 * < 0 if there was a failure
3469 static int si_update_scratch_buffer(struct si_context
*sctx
,
3470 struct si_shader
*shader
)
3472 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
3477 /* This shader doesn't need a scratch buffer */
3478 if (shader
->config
.scratch_bytes_per_wave
== 0)
3481 /* Prevent race conditions when updating:
3482 * - si_shader::scratch_bo
3483 * - si_shader::binary::code
3484 * - si_shader::previous_stage::binary::code.
3486 si_shader_lock(shader
);
3488 /* This shader is already configured to use the current
3489 * scratch buffer. */
3490 if (shader
->scratch_bo
== sctx
->scratch_buffer
) {
3491 si_shader_unlock(shader
);
3495 assert(sctx
->scratch_buffer
);
3497 /* Replace the shader bo with a new bo that has the relocs applied. */
3498 if (!si_shader_binary_upload(sctx
->screen
, shader
, scratch_va
)) {
3499 si_shader_unlock(shader
);
3503 /* Update the shader state to use the new shader bo. */
3504 si_shader_init_pm4_state(sctx
->screen
, shader
);
3506 si_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
3508 si_shader_unlock(shader
);
3512 static unsigned si_get_current_scratch_buffer_size(struct si_context
*sctx
)
3514 return sctx
->scratch_buffer
? sctx
->scratch_buffer
->b
.b
.width0
: 0;
3517 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
3519 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
3522 static struct si_shader
*si_get_tcs_current(struct si_context
*sctx
)
3524 if (!sctx
->tes_shader
.cso
)
3525 return NULL
; /* tessellation disabled */
3527 return sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.current
:
3528 sctx
->fixed_func_tcs_shader
.current
;
3531 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context
*sctx
)
3535 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
3536 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
3537 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
3538 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
3540 if (sctx
->tes_shader
.cso
) {
3541 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
3543 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(tcs
));
3548 static bool si_update_scratch_relocs(struct si_context
*sctx
)
3550 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
3553 /* Update the shaders, so that they are using the latest scratch.
3554 * The scratch buffer may have been changed since these shaders were
3555 * last used, so we still need to try to update them, even if they
3556 * require scratch buffers smaller than the current size.
3558 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
3562 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3564 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
3568 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3570 r
= si_update_scratch_buffer(sctx
, tcs
);
3574 si_pm4_bind_state(sctx
, hs
, tcs
->pm4
);
3576 /* VS can be bound as LS, ES, or VS. */
3577 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
3581 if (sctx
->vs_shader
.current
->key
.as_ls
)
3582 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3583 else if (sctx
->vs_shader
.current
->key
.as_es
)
3584 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3585 else if (sctx
->vs_shader
.current
->key
.as_ngg
)
3586 si_pm4_bind_state(sctx
, gs
, sctx
->vs_shader
.current
->pm4
);
3588 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3591 /* TES can be bound as ES or VS. */
3592 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
3596 if (sctx
->tes_shader
.current
->key
.as_es
)
3597 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3598 else if (sctx
->tes_shader
.current
->key
.as_ngg
)
3599 si_pm4_bind_state(sctx
, gs
, sctx
->tes_shader
.current
->pm4
);
3601 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3607 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
3609 unsigned current_scratch_buffer_size
=
3610 si_get_current_scratch_buffer_size(sctx
);
3611 unsigned scratch_bytes_per_wave
=
3612 si_get_max_scratch_bytes_per_wave(sctx
);
3613 unsigned scratch_needed_size
= scratch_bytes_per_wave
*
3614 sctx
->scratch_waves
;
3615 unsigned spi_tmpring_size
;
3617 if (scratch_needed_size
> 0) {
3618 if (scratch_needed_size
> current_scratch_buffer_size
) {
3619 /* Create a bigger scratch buffer */
3620 si_resource_reference(&sctx
->scratch_buffer
, NULL
);
3622 sctx
->scratch_buffer
=
3623 si_aligned_buffer_create(&sctx
->screen
->b
,
3624 SI_RESOURCE_FLAG_UNMAPPABLE
,
3626 scratch_needed_size
, 256);
3627 if (!sctx
->scratch_buffer
)
3630 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3631 si_context_add_resource_size(sctx
,
3632 &sctx
->scratch_buffer
->b
.b
);
3635 if (!si_update_scratch_relocs(sctx
))
3639 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3640 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
3641 "scratch size should already be aligned correctly.");
3643 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
3644 S_0286E8_WAVESIZE(scratch_bytes_per_wave
>> 10);
3645 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
3646 sctx
->spi_tmpring_size
= spi_tmpring_size
;
3647 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3652 static void si_init_tess_factor_ring(struct si_context
*sctx
)
3654 assert(!sctx
->tess_rings
);
3656 /* The address must be aligned to 2^19, because the shader only
3657 * receives the high 13 bits.
3659 sctx
->tess_rings
= pipe_aligned_buffer_create(sctx
->b
.screen
,
3660 SI_RESOURCE_FLAG_32BIT
,
3662 sctx
->screen
->tess_offchip_ring_size
+
3663 sctx
->screen
->tess_factor_ring_size
,
3665 if (!sctx
->tess_rings
)
3668 si_init_config_add_vgt_flush(sctx
);
3670 si_pm4_add_bo(sctx
->init_config
, si_resource(sctx
->tess_rings
),
3671 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
3673 uint64_t factor_va
= si_resource(sctx
->tess_rings
)->gpu_address
+
3674 sctx
->screen
->tess_offchip_ring_size
;
3676 /* Append these registers to the init config state. */
3677 if (sctx
->chip_class
>= GFX7
) {
3678 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
3679 S_030938_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3680 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
3682 if (sctx
->chip_class
>= GFX10
)
3683 si_pm4_set_reg(sctx
->init_config
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
3684 S_030984_BASE_HI(factor_va
>> 40));
3685 else if (sctx
->chip_class
== GFX9
)
3686 si_pm4_set_reg(sctx
->init_config
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3687 S_030944_BASE_HI(factor_va
>> 40));
3688 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3689 sctx
->screen
->vgt_hs_offchip_param
);
3691 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
3692 S_008988_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3693 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
3695 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3696 sctx
->screen
->vgt_hs_offchip_param
);
3699 /* Flush the context to re-emit the init_config state.
3700 * This is done only once in a lifetime of a context.
3702 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3703 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3704 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3707 static struct si_pm4_state
*si_build_vgt_shader_config(struct si_screen
*screen
,
3708 union si_vgt_stages_key key
)
3710 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
3711 uint32_t stages
= 0;
3714 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3715 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3718 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3721 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
3723 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3724 } else if (key
.u
.gs
) {
3725 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3727 } else if (key
.u
.ngg
) {
3728 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
3732 stages
|= S_028B54_PRIMGEN_EN(1);
3733 if (key
.u
.streamout
)
3734 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
3735 } else if (key
.u
.gs
)
3736 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3738 if (screen
->info
.chip_class
>= GFX9
)
3739 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3741 si_pm4_set_reg(pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
3745 static void si_update_vgt_shader_config(struct si_context
*sctx
,
3746 union si_vgt_stages_key key
)
3748 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[key
.index
];
3750 if (unlikely(!*pm4
))
3751 *pm4
= si_build_vgt_shader_config(sctx
->screen
, key
);
3752 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
3755 bool si_update_shaders(struct si_context
*sctx
)
3757 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
3758 struct si_compiler_ctx_state compiler_state
;
3759 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3760 struct si_shader
*old_vs
= si_get_vs_state(sctx
);
3761 bool old_clip_disable
= old_vs
? old_vs
->key
.opt
.clip_disable
: false;
3762 struct si_shader
*old_ps
= sctx
->ps_shader
.current
;
3763 union si_vgt_stages_key key
;
3764 unsigned old_spi_shader_col_format
=
3765 old_ps
? old_ps
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
3768 compiler_state
.compiler
= &sctx
->compiler
;
3769 compiler_state
.debug
= sctx
->debug
;
3770 compiler_state
.is_debug_context
= sctx
->is_debug
;
3774 if (sctx
->tes_shader
.cso
)
3776 if (sctx
->gs_shader
.cso
)
3779 if (sctx
->chip_class
>= GFX10
) {
3780 key
.u
.ngg
= sctx
->ngg
;
3782 if (sctx
->gs_shader
.cso
)
3783 key
.u
.streamout
= !!sctx
->gs_shader
.cso
->so
.num_outputs
;
3784 else if (sctx
->tes_shader
.cso
)
3785 key
.u
.streamout
= !!sctx
->tes_shader
.cso
->so
.num_outputs
;
3787 key
.u
.streamout
= !!sctx
->vs_shader
.cso
->so
.num_outputs
;
3790 /* Update TCS and TES. */
3791 if (sctx
->tes_shader
.cso
) {
3792 if (!sctx
->tess_rings
) {
3793 si_init_tess_factor_ring(sctx
);
3794 if (!sctx
->tess_rings
)
3798 if (sctx
->tcs_shader
.cso
) {
3799 r
= si_shader_select(ctx
, &sctx
->tcs_shader
, key
,
3803 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
3805 if (!sctx
->fixed_func_tcs_shader
.cso
) {
3806 sctx
->fixed_func_tcs_shader
.cso
=
3807 si_create_fixed_func_tcs(sctx
);
3808 if (!sctx
->fixed_func_tcs_shader
.cso
)
3812 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
,
3813 key
, &compiler_state
);
3816 si_pm4_bind_state(sctx
, hs
,
3817 sctx
->fixed_func_tcs_shader
.current
->pm4
);
3820 if (!sctx
->gs_shader
.cso
|| sctx
->chip_class
<= GFX8
) {
3821 r
= si_shader_select(ctx
, &sctx
->tes_shader
, key
, &compiler_state
);
3825 if (sctx
->gs_shader
.cso
) {
3827 assert(sctx
->chip_class
<= GFX8
);
3828 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3829 } else if (key
.u
.ngg
) {
3830 si_pm4_bind_state(sctx
, gs
, sctx
->tes_shader
.current
->pm4
);
3832 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3836 if (sctx
->chip_class
<= GFX8
)
3837 si_pm4_bind_state(sctx
, ls
, NULL
);
3838 si_pm4_bind_state(sctx
, hs
, NULL
);
3842 if (sctx
->gs_shader
.cso
) {
3843 r
= si_shader_select(ctx
, &sctx
->gs_shader
, key
, &compiler_state
);
3846 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3848 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
3850 if (!si_update_gs_ring_buffers(sctx
))
3853 si_pm4_bind_state(sctx
, vs
, NULL
);
3857 si_pm4_bind_state(sctx
, gs
, NULL
);
3858 if (sctx
->chip_class
<= GFX8
)
3859 si_pm4_bind_state(sctx
, es
, NULL
);
3864 if ((!key
.u
.tess
&& !key
.u
.gs
) || sctx
->chip_class
<= GFX8
) {
3865 r
= si_shader_select(ctx
, &sctx
->vs_shader
, key
, &compiler_state
);
3869 if (!key
.u
.tess
&& !key
.u
.gs
) {
3871 si_pm4_bind_state(sctx
, gs
, sctx
->vs_shader
.current
->pm4
);
3872 si_pm4_bind_state(sctx
, vs
, NULL
);
3874 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3876 } else if (sctx
->tes_shader
.cso
) {
3877 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3879 assert(sctx
->gs_shader
.cso
);
3880 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3884 si_update_vgt_shader_config(sctx
, key
);
3886 if (old_clip_disable
!= si_get_vs_state(sctx
)->key
.opt
.clip_disable
)
3887 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
3889 if (sctx
->ps_shader
.cso
) {
3890 unsigned db_shader_control
;
3892 r
= si_shader_select(ctx
, &sctx
->ps_shader
, key
, &compiler_state
);
3895 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3898 sctx
->ps_shader
.cso
->db_shader_control
|
3899 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
3901 if (si_pm4_state_changed(sctx
, ps
) ||
3902 si_pm4_state_changed(sctx
, vs
) ||
3903 (key
.u
.ngg
&& si_pm4_state_changed(sctx
, gs
)) ||
3904 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
3905 sctx
->flatshade
!= rs
->flatshade
) {
3906 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
3907 sctx
->flatshade
= rs
->flatshade
;
3908 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.spi_map
);
3911 if (sctx
->screen
->rbplus_allowed
&&
3912 si_pm4_state_changed(sctx
, ps
) &&
3914 old_spi_shader_col_format
!=
3915 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
))
3916 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3918 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
3919 sctx
->ps_db_shader_control
= db_shader_control
;
3920 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3921 if (sctx
->screen
->dpbb_allowed
)
3922 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3925 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
3926 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
3927 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3929 if (sctx
->chip_class
== GFX6
)
3930 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3932 if (sctx
->framebuffer
.nr_samples
<= 1)
3933 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
3937 if (si_pm4_state_enabled_and_changed(sctx
, ls
) ||
3938 si_pm4_state_enabled_and_changed(sctx
, hs
) ||
3939 si_pm4_state_enabled_and_changed(sctx
, es
) ||
3940 si_pm4_state_enabled_and_changed(sctx
, gs
) ||
3941 si_pm4_state_enabled_and_changed(sctx
, vs
) ||
3942 si_pm4_state_enabled_and_changed(sctx
, ps
)) {
3943 if (!si_update_spi_tmpring_size(sctx
))
3947 if (sctx
->chip_class
>= GFX7
) {
3948 if (si_pm4_state_enabled_and_changed(sctx
, ls
))
3949 sctx
->prefetch_L2_mask
|= SI_PREFETCH_LS
;
3950 else if (!sctx
->queued
.named
.ls
)
3951 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_LS
;
3953 if (si_pm4_state_enabled_and_changed(sctx
, hs
))
3954 sctx
->prefetch_L2_mask
|= SI_PREFETCH_HS
;
3955 else if (!sctx
->queued
.named
.hs
)
3956 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_HS
;
3958 if (si_pm4_state_enabled_and_changed(sctx
, es
))
3959 sctx
->prefetch_L2_mask
|= SI_PREFETCH_ES
;
3960 else if (!sctx
->queued
.named
.es
)
3961 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_ES
;
3963 if (si_pm4_state_enabled_and_changed(sctx
, gs
))
3964 sctx
->prefetch_L2_mask
|= SI_PREFETCH_GS
;
3965 else if (!sctx
->queued
.named
.gs
)
3966 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_GS
;
3968 if (si_pm4_state_enabled_and_changed(sctx
, vs
))
3969 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VS
;
3970 else if (!sctx
->queued
.named
.vs
)
3971 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_VS
;
3973 if (si_pm4_state_enabled_and_changed(sctx
, ps
))
3974 sctx
->prefetch_L2_mask
|= SI_PREFETCH_PS
;
3975 else if (!sctx
->queued
.named
.ps
)
3976 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_PS
;
3979 sctx
->do_update_shaders
= false;
3983 static void si_emit_scratch_state(struct si_context
*sctx
)
3985 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3987 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
3988 sctx
->spi_tmpring_size
);
3990 if (sctx
->scratch_buffer
) {
3991 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3992 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
3993 RADEON_PRIO_SCRATCH_BUFFER
);
3997 void si_init_shader_functions(struct si_context
*sctx
)
3999 sctx
->atoms
.s
.spi_map
.emit
= si_emit_spi_map
;
4000 sctx
->atoms
.s
.scratch_state
.emit
= si_emit_scratch_state
;
4002 sctx
->b
.create_vs_state
= si_create_shader_selector
;
4003 sctx
->b
.create_tcs_state
= si_create_shader_selector
;
4004 sctx
->b
.create_tes_state
= si_create_shader_selector
;
4005 sctx
->b
.create_gs_state
= si_create_shader_selector
;
4006 sctx
->b
.create_fs_state
= si_create_shader_selector
;
4008 sctx
->b
.bind_vs_state
= si_bind_vs_shader
;
4009 sctx
->b
.bind_tcs_state
= si_bind_tcs_shader
;
4010 sctx
->b
.bind_tes_state
= si_bind_tes_shader
;
4011 sctx
->b
.bind_gs_state
= si_bind_gs_shader
;
4012 sctx
->b
.bind_fs_state
= si_bind_ps_shader
;
4014 sctx
->b
.delete_vs_state
= si_delete_shader_selector
;
4015 sctx
->b
.delete_tcs_state
= si_delete_shader_selector
;
4016 sctx
->b
.delete_tes_state
= si_delete_shader_selector
;
4017 sctx
->b
.delete_gs_state
= si_delete_shader_selector
;
4018 sctx
->b
.delete_fs_state
= si_delete_shader_selector
;