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[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
45 * size as integer.
46 */
47 void *si_get_ir_binary(struct si_shader_selector *sel)
48 {
49 struct blob blob;
50 unsigned ir_size;
51 void *ir_binary;
52
53 if (sel->tokens) {
54 ir_binary = sel->tokens;
55 ir_size = tgsi_num_tokens(sel->tokens) *
56 sizeof(struct tgsi_token);
57 } else {
58 assert(sel->nir);
59
60 blob_init(&blob);
61 nir_serialize(&blob, sel->nir);
62 ir_binary = blob.data;
63 ir_size = blob.size;
64 }
65
66 unsigned size = 4 + ir_size + sizeof(sel->so);
67 char *result = (char*)MALLOC(size);
68 if (!result)
69 return NULL;
70
71 *((uint32_t*)result) = size;
72 memcpy(result + 4, ir_binary, ir_size);
73 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
74
75 if (sel->nir)
76 blob_finish(&blob);
77
78 return result;
79 }
80
81 /** Copy "data" to "ptr" and return the next dword following copied data. */
82 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
83 {
84 /* data may be NULL if size == 0 */
85 if (size)
86 memcpy(ptr, data, size);
87 ptr += DIV_ROUND_UP(size, 4);
88 return ptr;
89 }
90
91 /** Read data from "ptr". Return the next dword following the data. */
92 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
93 {
94 memcpy(data, ptr, size);
95 ptr += DIV_ROUND_UP(size, 4);
96 return ptr;
97 }
98
99 /**
100 * Write the size as uint followed by the data. Return the next dword
101 * following the copied data.
102 */
103 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
104 {
105 *ptr++ = size;
106 return write_data(ptr, data, size);
107 }
108
109 /**
110 * Read the size as uint followed by the data. Return both via parameters.
111 * Return the next dword following the data.
112 */
113 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
114 {
115 *size = *ptr++;
116 assert(*data == NULL);
117 if (!*size)
118 return ptr;
119 *data = malloc(*size);
120 return read_data(ptr, *data, *size);
121 }
122
123 /**
124 * Return the shader binary in a buffer. The first 4 bytes contain its size
125 * as integer.
126 */
127 static void *si_get_shader_binary(struct si_shader *shader)
128 {
129 /* There is always a size of data followed by the data itself. */
130 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
131 strlen(shader->binary.llvm_ir_string) + 1 : 0;
132
133 /* Refuse to allocate overly large buffers and guard against integer
134 * overflow. */
135 if (shader->binary.elf_size > UINT_MAX / 4 ||
136 llvm_ir_size > UINT_MAX / 4)
137 return NULL;
138
139 unsigned size =
140 4 + /* total size */
141 4 + /* CRC32 of the data below */
142 align(sizeof(shader->config), 4) +
143 align(sizeof(shader->info), 4) +
144 4 + align(shader->binary.elf_size, 4) +
145 4 + align(llvm_ir_size, 4);
146 void *buffer = CALLOC(1, size);
147 uint32_t *ptr = (uint32_t*)buffer;
148
149 if (!buffer)
150 return NULL;
151
152 *ptr++ = size;
153 ptr++; /* CRC32 is calculated at the end. */
154
155 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
156 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
157 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
158 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
159 assert((char *)ptr - (char *)buffer == size);
160
161 /* Compute CRC32. */
162 ptr = (uint32_t*)buffer;
163 ptr++;
164 *ptr = util_hash_crc32(ptr + 1, size - 8);
165
166 return buffer;
167 }
168
169 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
170 {
171 uint32_t *ptr = (uint32_t*)binary;
172 uint32_t size = *ptr++;
173 uint32_t crc32 = *ptr++;
174 unsigned chunk_size;
175 unsigned elf_size;
176
177 if (util_hash_crc32(ptr, size - 8) != crc32) {
178 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
179 return false;
180 }
181
182 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
183 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
184 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
185 &elf_size);
186 shader->binary.elf_size = elf_size;
187 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
188
189 return true;
190 }
191
192 /**
193 * Insert a shader into the cache. It's assumed the shader is not in the cache.
194 * Use si_shader_cache_load_shader before calling this.
195 *
196 * Returns false on failure, in which case the ir_binary should be freed.
197 */
198 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
199 struct si_shader *shader,
200 bool insert_into_disk_cache)
201 {
202 void *hw_binary;
203 struct hash_entry *entry;
204 uint8_t key[CACHE_KEY_SIZE];
205
206 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
207 if (entry)
208 return false; /* already added */
209
210 hw_binary = si_get_shader_binary(shader);
211 if (!hw_binary)
212 return false;
213
214 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
215 hw_binary) == NULL) {
216 FREE(hw_binary);
217 return false;
218 }
219
220 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
221 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
222 *((uint32_t *)ir_binary), key);
223 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
224 *((uint32_t *) hw_binary), NULL);
225 }
226
227 return true;
228 }
229
230 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
231 struct si_shader *shader)
232 {
233 struct hash_entry *entry =
234 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
235 if (!entry) {
236 if (sscreen->disk_shader_cache) {
237 unsigned char sha1[CACHE_KEY_SIZE];
238 size_t tg_size = *((uint32_t *) ir_binary);
239
240 disk_cache_compute_key(sscreen->disk_shader_cache,
241 ir_binary, tg_size, sha1);
242
243 size_t binary_size;
244 uint8_t *buffer =
245 disk_cache_get(sscreen->disk_shader_cache,
246 sha1, &binary_size);
247 if (!buffer)
248 return false;
249
250 if (binary_size < sizeof(uint32_t) ||
251 *((uint32_t*)buffer) != binary_size) {
252 /* Something has gone wrong discard the item
253 * from the cache and rebuild/link from
254 * source.
255 */
256 assert(!"Invalid radeonsi shader disk cache "
257 "item!");
258
259 disk_cache_remove(sscreen->disk_shader_cache,
260 sha1);
261 free(buffer);
262
263 return false;
264 }
265
266 if (!si_load_shader_binary(shader, buffer)) {
267 free(buffer);
268 return false;
269 }
270 free(buffer);
271
272 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
273 shader, false))
274 FREE(ir_binary);
275 } else {
276 return false;
277 }
278 } else {
279 if (si_load_shader_binary(shader, entry->data))
280 FREE(ir_binary);
281 else
282 return false;
283 }
284 p_atomic_inc(&sscreen->num_shader_cache_hits);
285 return true;
286 }
287
288 static uint32_t si_shader_cache_key_hash(const void *key)
289 {
290 /* The first dword is the key size. */
291 return util_hash_crc32(key, *(uint32_t*)key);
292 }
293
294 static bool si_shader_cache_key_equals(const void *a, const void *b)
295 {
296 uint32_t *keya = (uint32_t*)a;
297 uint32_t *keyb = (uint32_t*)b;
298
299 /* The first dword is the key size. */
300 if (*keya != *keyb)
301 return false;
302
303 return memcmp(keya, keyb, *keya) == 0;
304 }
305
306 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
307 {
308 FREE((void*)entry->key);
309 FREE(entry->data);
310 }
311
312 bool si_init_shader_cache(struct si_screen *sscreen)
313 {
314 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
315 sscreen->shader_cache =
316 _mesa_hash_table_create(NULL,
317 si_shader_cache_key_hash,
318 si_shader_cache_key_equals);
319
320 return sscreen->shader_cache != NULL;
321 }
322
323 void si_destroy_shader_cache(struct si_screen *sscreen)
324 {
325 if (sscreen->shader_cache)
326 _mesa_hash_table_destroy(sscreen->shader_cache,
327 si_destroy_shader_cache_entry);
328 mtx_destroy(&sscreen->shader_cache_mutex);
329 }
330
331 /* SHADER STATES */
332
333 static void si_set_tesseval_regs(struct si_screen *sscreen,
334 const struct si_shader_selector *tes,
335 struct si_pm4_state *pm4)
336 {
337 const struct tgsi_shader_info *info = &tes->info;
338 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
339 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
340 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
341 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
342 unsigned type, partitioning, topology, distribution_mode;
343
344 switch (tes_prim_mode) {
345 case PIPE_PRIM_LINES:
346 type = V_028B6C_TESS_ISOLINE;
347 break;
348 case PIPE_PRIM_TRIANGLES:
349 type = V_028B6C_TESS_TRIANGLE;
350 break;
351 case PIPE_PRIM_QUADS:
352 type = V_028B6C_TESS_QUAD;
353 break;
354 default:
355 assert(0);
356 return;
357 }
358
359 switch (tes_spacing) {
360 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
361 partitioning = V_028B6C_PART_FRAC_ODD;
362 break;
363 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
364 partitioning = V_028B6C_PART_FRAC_EVEN;
365 break;
366 case PIPE_TESS_SPACING_EQUAL:
367 partitioning = V_028B6C_PART_INTEGER;
368 break;
369 default:
370 assert(0);
371 return;
372 }
373
374 if (tes_point_mode)
375 topology = V_028B6C_OUTPUT_POINT;
376 else if (tes_prim_mode == PIPE_PRIM_LINES)
377 topology = V_028B6C_OUTPUT_LINE;
378 else if (tes_vertex_order_cw)
379 /* for some reason, this must be the other way around */
380 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
381 else
382 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
383
384 if (sscreen->has_distributed_tess) {
385 if (sscreen->info.family == CHIP_FIJI ||
386 sscreen->info.family >= CHIP_POLARIS10)
387 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
388 else
389 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
390 } else
391 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
392
393 assert(pm4->shader);
394 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
395 S_028B6C_PARTITIONING(partitioning) |
396 S_028B6C_TOPOLOGY(topology) |
397 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
398 }
399
400 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
401 * whether the "fractional odd" tessellation spacing is used.
402 *
403 * Possible VGT configurations and which state should set the register:
404 *
405 * Reg set in | VGT shader configuration | Value
406 * ------------------------------------------------------
407 * VS as VS | VS | 30
408 * VS as ES | ES -> GS -> VS | 30
409 * TES as VS | LS -> HS -> VS | 14 or 30
410 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
411 *
412 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
413 */
414 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
415 struct si_shader_selector *sel,
416 struct si_shader *shader,
417 struct si_pm4_state *pm4)
418 {
419 unsigned type = sel->type;
420
421 if (sscreen->info.family < CHIP_POLARIS10)
422 return;
423
424 /* VS as VS, or VS as ES: */
425 if ((type == PIPE_SHADER_VERTEX &&
426 (!shader ||
427 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
428 /* TES as VS, or TES as ES: */
429 type == PIPE_SHADER_TESS_EVAL) {
430 unsigned vtx_reuse_depth = 30;
431
432 if (type == PIPE_SHADER_TESS_EVAL &&
433 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
434 PIPE_TESS_SPACING_FRACTIONAL_ODD)
435 vtx_reuse_depth = 14;
436
437 assert(pm4->shader);
438 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
439 }
440 }
441
442 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
443 {
444 if (shader->pm4)
445 si_pm4_clear_state(shader->pm4);
446 else
447 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
448
449 if (shader->pm4) {
450 shader->pm4->shader = shader;
451 return shader->pm4;
452 } else {
453 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
454 return NULL;
455 }
456 }
457
458 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
459 {
460 /* Add the pointer to VBO descriptors. */
461 return num_always_on_user_sgprs + 1;
462 }
463
464 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
465 {
466 struct si_pm4_state *pm4;
467 unsigned vgpr_comp_cnt;
468 uint64_t va;
469
470 assert(sscreen->info.chip_class <= GFX8);
471
472 pm4 = si_get_shader_pm4_state(shader);
473 if (!pm4)
474 return;
475
476 va = shader->bo->gpu_address;
477 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
478
479 /* We need at least 2 components for LS.
480 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
481 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
482 */
483 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
484
485 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
486 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
487
488 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
489 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
490 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
491 S_00B528_DX10_CLAMP(1) |
492 S_00B528_FLOAT_MODE(shader->config.float_mode);
493 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
494 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
495 }
496
497 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
498 {
499 struct si_pm4_state *pm4;
500 uint64_t va;
501 unsigned ls_vgpr_comp_cnt = 0;
502
503 pm4 = si_get_shader_pm4_state(shader);
504 if (!pm4)
505 return;
506
507 va = shader->bo->gpu_address;
508 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
509
510 if (sscreen->info.chip_class >= GFX9) {
511 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
512 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
513
514 /* We need at least 2 components for LS.
515 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
516 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
517 */
518 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
519
520 unsigned num_user_sgprs =
521 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
522
523 shader->config.rsrc2 =
524 S_00B42C_USER_SGPR(num_user_sgprs) |
525 S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5) |
526 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
527 } else {
528 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
529 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
530
531 shader->config.rsrc2 =
532 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
533 S_00B42C_OC_LDS_EN(1) |
534 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
535 }
536
537 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
538 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
539 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
540 S_00B428_DX10_CLAMP(1) |
541 S_00B428_FLOAT_MODE(shader->config.float_mode) |
542 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
543
544 if (sscreen->info.chip_class <= GFX8) {
545 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
546 shader->config.rsrc2);
547 }
548 }
549
550 static void si_emit_shader_es(struct si_context *sctx)
551 {
552 struct si_shader *shader = sctx->queued.named.es->shader;
553 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
554
555 if (!shader)
556 return;
557
558 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
559 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
560 shader->selector->esgs_itemsize / 4);
561
562 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
563 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
564 SI_TRACKED_VGT_TF_PARAM,
565 shader->vgt_tf_param);
566
567 if (shader->vgt_vertex_reuse_block_cntl)
568 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
569 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
570 shader->vgt_vertex_reuse_block_cntl);
571
572 if (initial_cdw != sctx->gfx_cs->current.cdw)
573 sctx->context_roll = true;
574 }
575
576 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
577 {
578 struct si_pm4_state *pm4;
579 unsigned num_user_sgprs;
580 unsigned vgpr_comp_cnt;
581 uint64_t va;
582 unsigned oc_lds_en;
583
584 assert(sscreen->info.chip_class <= GFX8);
585
586 pm4 = si_get_shader_pm4_state(shader);
587 if (!pm4)
588 return;
589
590 pm4->atom.emit = si_emit_shader_es;
591 va = shader->bo->gpu_address;
592 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
593
594 if (shader->selector->type == PIPE_SHADER_VERTEX) {
595 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
596 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
597 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
598 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
599 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
600 num_user_sgprs = SI_TES_NUM_USER_SGPR;
601 } else
602 unreachable("invalid shader selector type");
603
604 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
605
606 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
607 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
608 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
609 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
610 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
611 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
612 S_00B328_DX10_CLAMP(1) |
613 S_00B328_FLOAT_MODE(shader->config.float_mode));
614 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
615 S_00B32C_USER_SGPR(num_user_sgprs) |
616 S_00B32C_OC_LDS_EN(oc_lds_en) |
617 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
618
619 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
620 si_set_tesseval_regs(sscreen, shader->selector, pm4);
621
622 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
623 }
624
625 void gfx9_get_gs_info(struct si_shader_selector *es,
626 struct si_shader_selector *gs,
627 struct gfx9_gs_info *out)
628 {
629 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
630 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
631 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
632 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
633
634 /* All these are in dwords: */
635 /* We can't allow using the whole LDS, because GS waves compete with
636 * other shader stages for LDS space. */
637 const unsigned max_lds_size = 8 * 1024;
638 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
639 unsigned esgs_lds_size;
640
641 /* All these are per subgroup: */
642 const unsigned max_out_prims = 32 * 1024;
643 const unsigned max_es_verts = 255;
644 const unsigned ideal_gs_prims = 64;
645 unsigned max_gs_prims, gs_prims;
646 unsigned min_es_verts, es_verts, worst_case_es_verts;
647
648 if (uses_adjacency || gs_num_invocations > 1)
649 max_gs_prims = 127 / gs_num_invocations;
650 else
651 max_gs_prims = 255;
652
653 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
654 * Make sure we don't go over the maximum value.
655 */
656 if (gs->gs_max_out_vertices > 0) {
657 max_gs_prims = MIN2(max_gs_prims,
658 max_out_prims /
659 (gs->gs_max_out_vertices * gs_num_invocations));
660 }
661 assert(max_gs_prims > 0);
662
663 /* If the primitive has adjacency, halve the number of vertices
664 * that will be reused in multiple primitives.
665 */
666 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
667
668 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
669 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
670
671 /* Compute ESGS LDS size based on the worst case number of ES vertices
672 * needed to create the target number of GS prims per subgroup.
673 */
674 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
675
676 /* If total LDS usage is too big, refactor partitions based on ratio
677 * of ESGS item sizes.
678 */
679 if (esgs_lds_size > max_lds_size) {
680 /* Our target GS Prims Per Subgroup was too large. Calculate
681 * the maximum number of GS Prims Per Subgroup that will fit
682 * into LDS, capped by the maximum that the hardware can support.
683 */
684 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
685 max_gs_prims);
686 assert(gs_prims > 0);
687 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
688 max_es_verts);
689
690 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
691 assert(esgs_lds_size <= max_lds_size);
692 }
693
694 /* Now calculate remaining ESGS information. */
695 if (esgs_lds_size)
696 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
697 else
698 es_verts = max_es_verts;
699
700 /* Vertices for adjacency primitives are not always reused, so restore
701 * it for ES_VERTS_PER_SUBGRP.
702 */
703 min_es_verts = gs->gs_input_verts_per_prim;
704
705 /* For normal primitives, the VGT only checks if they are past the ES
706 * verts per subgroup after allocating a full GS primitive and if they
707 * are, kick off a new subgroup. But if those additional ES verts are
708 * unique (e.g. not reused) we need to make sure there is enough LDS
709 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
710 */
711 es_verts -= min_es_verts - 1;
712
713 out->es_verts_per_subgroup = es_verts;
714 out->gs_prims_per_subgroup = gs_prims;
715 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
716 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
717 gs->gs_max_out_vertices;
718 out->esgs_ring_size = 4 * esgs_lds_size;
719
720 assert(out->max_prims_per_subgroup <= max_out_prims);
721 }
722
723 static void si_emit_shader_gs(struct si_context *sctx)
724 {
725 struct si_shader *shader = sctx->queued.named.gs->shader;
726 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
727
728 if (!shader)
729 return;
730
731 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
732 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
733 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
734 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
735 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
736 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
737 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
738
739 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
740 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
741 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
742 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
743
744 /* R_028B38_VGT_GS_MAX_VERT_OUT */
745 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
746 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
747 shader->ctx_reg.gs.vgt_gs_max_vert_out);
748
749 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
750 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
751 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
752 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
753 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
754 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
755 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
756 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
757
758 /* R_028B90_VGT_GS_INSTANCE_CNT */
759 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
760 SI_TRACKED_VGT_GS_INSTANCE_CNT,
761 shader->ctx_reg.gs.vgt_gs_instance_cnt);
762
763 if (sctx->chip_class >= GFX9) {
764 /* R_028A44_VGT_GS_ONCHIP_CNTL */
765 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
766 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
767 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
768 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
769 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
770 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
771 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
772 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
773 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
774 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
775 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
776
777 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
778 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
779 SI_TRACKED_VGT_TF_PARAM,
780 shader->vgt_tf_param);
781 if (shader->vgt_vertex_reuse_block_cntl)
782 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
783 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
784 shader->vgt_vertex_reuse_block_cntl);
785 }
786
787 if (initial_cdw != sctx->gfx_cs->current.cdw)
788 sctx->context_roll = true;
789 }
790
791 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
792 {
793 struct si_shader_selector *sel = shader->selector;
794 const ubyte *num_components = sel->info.num_stream_output_components;
795 unsigned gs_num_invocations = sel->gs_num_invocations;
796 struct si_pm4_state *pm4;
797 uint64_t va;
798 unsigned max_stream = sel->max_gs_stream;
799 unsigned offset;
800
801 pm4 = si_get_shader_pm4_state(shader);
802 if (!pm4)
803 return;
804
805 pm4->atom.emit = si_emit_shader_gs;
806
807 offset = num_components[0] * sel->gs_max_out_vertices;
808 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
809
810 if (max_stream >= 1)
811 offset += num_components[1] * sel->gs_max_out_vertices;
812 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
813
814 if (max_stream >= 2)
815 offset += num_components[2] * sel->gs_max_out_vertices;
816 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
817
818 if (max_stream >= 3)
819 offset += num_components[3] * sel->gs_max_out_vertices;
820 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
821
822 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
823 assert(offset < (1 << 15));
824
825 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
826
827 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
828 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
829 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
830 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
831
832 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
833 S_028B90_ENABLE(gs_num_invocations > 0);
834
835 va = shader->bo->gpu_address;
836 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
837
838 if (sscreen->info.chip_class >= GFX9) {
839 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
840 unsigned es_type = shader->key.part.gs.es->type;
841 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
842
843 if (es_type == PIPE_SHADER_VERTEX)
844 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
845 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
846 else if (es_type == PIPE_SHADER_TESS_EVAL)
847 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
848 else
849 unreachable("invalid shader selector type");
850
851 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
852 * VGPR[0:4] are always loaded.
853 */
854 if (sel->info.uses_invocationid)
855 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
856 else if (sel->info.uses_primid)
857 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
858 else if (input_prim >= PIPE_PRIM_TRIANGLES)
859 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
860 else
861 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
862
863 unsigned num_user_sgprs;
864 if (es_type == PIPE_SHADER_VERTEX)
865 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
866 else
867 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
868
869 if (sscreen->info.chip_class >= GFX10) {
870 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
871 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
872 } else {
873 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
874 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
875 }
876
877 uint32_t rsrc1 =
878 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
879 S_00B228_DX10_CLAMP(1) |
880 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
881 S_00B228_FLOAT_MODE(shader->config.float_mode) |
882 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
883 uint32_t rsrc2 =
884 S_00B22C_USER_SGPR(num_user_sgprs) |
885 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
886 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
887 S_00B22C_LDS_SIZE(shader->config.lds_size) |
888 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
889
890 if (sscreen->info.chip_class >= GFX10) {
891 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
892 } else {
893 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
894 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
895 }
896
897 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
898 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
899
900 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
901 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
902 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
903 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
904 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
905 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
906 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
907 shader->key.part.gs.es->esgs_itemsize / 4;
908
909 if (es_type == PIPE_SHADER_TESS_EVAL)
910 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
911
912 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
913 NULL, pm4);
914 } else {
915 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
916 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
917
918 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
919 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
920 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
921 S_00B228_DX10_CLAMP(1) |
922 S_00B228_FLOAT_MODE(shader->config.float_mode));
923 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
924 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
925 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
926 }
927 }
928
929 /* Common tail code for NGG primitive shaders. */
930 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
931 struct si_shader *shader,
932 unsigned initial_cdw)
933 {
934 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
935 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
936 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
937 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
938 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
939 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
940 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
941 SI_TRACKED_VGT_PRIMITIVEID_EN,
942 shader->ctx_reg.ngg.vgt_primitiveid_en);
943 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
944 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
945 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
946 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
947 SI_TRACKED_VGT_GS_INSTANCE_CNT,
948 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
949 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
950 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
951 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
952 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
953 SI_TRACKED_VGT_REUSE_OFF,
954 shader->ctx_reg.ngg.vgt_reuse_off);
955 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
956 SI_TRACKED_SPI_VS_OUT_CONFIG,
957 shader->ctx_reg.ngg.spi_vs_out_config);
958 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
959 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
960 shader->ctx_reg.ngg.spi_shader_idx_format,
961 shader->ctx_reg.ngg.spi_shader_pos_format);
962 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
963 SI_TRACKED_PA_CL_VTE_CNTL,
964 shader->ctx_reg.ngg.pa_cl_vte_cntl);
965
966 if (initial_cdw != sctx->gfx_cs->current.cdw)
967 sctx->context_roll = true;
968
969 if (shader->ge_cntl != sctx->last_multi_vgt_param) {
970 radeon_set_uconfig_reg(sctx->gfx_cs, R_03096C_GE_CNTL, shader->ge_cntl);
971 sctx->last_multi_vgt_param = shader->ge_cntl;
972 }
973 }
974
975 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
976 {
977 struct si_shader *shader = sctx->queued.named.gs->shader;
978 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
979
980 if (!shader)
981 return;
982
983 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
984 }
985
986 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
987 {
988 struct si_shader *shader = sctx->queued.named.gs->shader;
989 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
990
991 if (!shader)
992 return;
993
994 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
995 SI_TRACKED_VGT_TF_PARAM,
996 shader->vgt_tf_param);
997
998 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
999 }
1000
1001 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1002 {
1003 struct si_shader *shader = sctx->queued.named.gs->shader;
1004 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1005
1006 if (!shader)
1007 return;
1008
1009 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1010 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1011 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1012
1013 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1014 }
1015
1016 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1017 {
1018 struct si_shader *shader = sctx->queued.named.gs->shader;
1019 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1020
1021 if (!shader)
1022 return;
1023
1024 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1025 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1026 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1027 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1028 SI_TRACKED_VGT_TF_PARAM,
1029 shader->vgt_tf_param);
1030
1031 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1032 }
1033
1034 /**
1035 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1036 * in NGG mode.
1037 */
1038 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1039 {
1040 const struct si_shader_selector *gs_sel = shader->selector;
1041 const struct tgsi_shader_info *gs_info = &gs_sel->info;
1042 enum pipe_shader_type gs_type = shader->selector->type;
1043 const struct si_shader_selector *es_sel =
1044 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1045 const struct tgsi_shader_info *es_info = &es_sel->info;
1046 enum pipe_shader_type es_type = es_sel->type;
1047 unsigned num_user_sgprs;
1048 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1049 uint64_t va;
1050 unsigned window_space =
1051 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1052 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1053 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1054 unsigned input_prim =
1055 gs_type == PIPE_SHADER_GEOMETRY ?
1056 gs_info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] :
1057 PIPE_PRIM_TRIANGLES; /* TODO: Optimize when primtype is known */
1058 bool break_wave_at_eoi = false;
1059 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1060 if (!pm4)
1061 return;
1062
1063 if (es_type == PIPE_SHADER_TESS_EVAL) {
1064 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1065 : gfx10_emit_shader_ngg_tess_nogs;
1066 } else {
1067 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1068 : gfx10_emit_shader_ngg_notess_nogs;
1069 }
1070
1071 va = shader->bo->gpu_address;
1072 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1073
1074 if (es_type == PIPE_SHADER_VERTEX) {
1075 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
1076 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
1077
1078 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1079 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1080 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1081 } else {
1082 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
1083 }
1084 } else {
1085 assert(es_type == PIPE_SHADER_TESS_EVAL);
1086 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1087 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1088
1089 if (es_enable_prim_id || gs_info->uses_primid)
1090 break_wave_at_eoi = true;
1091 }
1092
1093 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1094 * VGPR[0:4] are always loaded.
1095 */
1096 if (gs_info->uses_invocationid)
1097 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
1098 else if (gs_info->uses_primid)
1099 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1100 else if (input_prim >= PIPE_PRIM_TRIANGLES)
1101 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1102 else
1103 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1104
1105 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1106 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1107 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1108 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
1109 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1110 S_00B228_DX10_CLAMP(1) |
1111 S_00B228_MEM_ORDERED(1) |
1112 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1113 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1114 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1115 S_00B22C_USER_SGPR(num_user_sgprs) |
1116 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1117 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1118 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1119 S_00B22C_LDS_SIZE(shader->config.lds_size));
1120
1121 /* TODO: Use NO_PC_EXPORT when applicable. */
1122 nparams = MAX2(shader->info.nr_param_exports, 1);
1123 shader->ctx_reg.ngg.spi_vs_out_config =
1124 S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1125
1126 shader->ctx_reg.ngg.spi_shader_idx_format =
1127 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1128 shader->ctx_reg.ngg.spi_shader_pos_format =
1129 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1130 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1131 V_02870C_SPI_SHADER_4COMP :
1132 V_02870C_SPI_SHADER_NONE) |
1133 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1134 V_02870C_SPI_SHADER_4COMP :
1135 V_02870C_SPI_SHADER_NONE) |
1136 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1137 V_02870C_SPI_SHADER_4COMP :
1138 V_02870C_SPI_SHADER_NONE);
1139
1140 shader->ctx_reg.ngg.vgt_primitiveid_en =
1141 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1142 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id);
1143
1144 if (gs_type == PIPE_SHADER_GEOMETRY) {
1145 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1146 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1147 } else {
1148 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1149 }
1150
1151 if (es_type == PIPE_SHADER_TESS_EVAL)
1152 si_set_tesseval_regs(sscreen, es_sel, pm4);
1153
1154 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1155 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1156 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1157 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1158 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1159 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1160 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1161 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1162 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1163 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1164 S_028B90_CNT(gs_num_invocations) |
1165 S_028B90_ENABLE(gs_num_invocations > 1) |
1166 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1167 shader->ngg.max_vert_out_per_gs_instance);
1168
1169 shader->ge_cntl =
1170 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1171 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts) |
1172 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1173
1174 if (window_space) {
1175 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1176 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1177 } else {
1178 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1179 S_028818_VTX_W0_FMT(1) |
1180 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1181 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1182 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1183 }
1184
1185 shader->ctx_reg.ngg.vgt_reuse_off =
1186 S_028AB4_REUSE_OFF(sscreen->info.family == CHIP_NAVI10 &&
1187 sscreen->info.chip_external_rev == 0x1 &&
1188 es_type == PIPE_SHADER_TESS_EVAL);
1189 }
1190
1191 static void si_emit_shader_vs(struct si_context *sctx)
1192 {
1193 struct si_shader *shader = sctx->queued.named.vs->shader;
1194 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1195
1196 if (!shader)
1197 return;
1198
1199 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1200 SI_TRACKED_VGT_GS_MODE,
1201 shader->ctx_reg.vs.vgt_gs_mode);
1202 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1203 SI_TRACKED_VGT_PRIMITIVEID_EN,
1204 shader->ctx_reg.vs.vgt_primitiveid_en);
1205
1206 if (sctx->chip_class <= GFX8) {
1207 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1208 SI_TRACKED_VGT_REUSE_OFF,
1209 shader->ctx_reg.vs.vgt_reuse_off);
1210 }
1211
1212 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1213 SI_TRACKED_SPI_VS_OUT_CONFIG,
1214 shader->ctx_reg.vs.spi_vs_out_config);
1215
1216 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1217 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1218 shader->ctx_reg.vs.spi_shader_pos_format);
1219
1220 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1221 SI_TRACKED_PA_CL_VTE_CNTL,
1222 shader->ctx_reg.vs.pa_cl_vte_cntl);
1223
1224 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1225 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1226 SI_TRACKED_VGT_TF_PARAM,
1227 shader->vgt_tf_param);
1228
1229 if (shader->vgt_vertex_reuse_block_cntl)
1230 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1231 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1232 shader->vgt_vertex_reuse_block_cntl);
1233
1234 if (initial_cdw != sctx->gfx_cs->current.cdw)
1235 sctx->context_roll = true;
1236 }
1237
1238 /**
1239 * Compute the state for \p shader, which will run as a vertex shader on the
1240 * hardware.
1241 *
1242 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1243 * is the copy shader.
1244 */
1245 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1246 struct si_shader_selector *gs)
1247 {
1248 const struct tgsi_shader_info *info = &shader->selector->info;
1249 struct si_pm4_state *pm4;
1250 unsigned num_user_sgprs, vgpr_comp_cnt;
1251 uint64_t va;
1252 unsigned nparams, oc_lds_en;
1253 unsigned window_space =
1254 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1255 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1256
1257 pm4 = si_get_shader_pm4_state(shader);
1258 if (!pm4)
1259 return;
1260
1261 pm4->atom.emit = si_emit_shader_vs;
1262
1263 /* We always write VGT_GS_MODE in the VS state, because every switch
1264 * between different shader pipelines involving a different GS or no
1265 * GS at all involves a switch of the VS (different GS use different
1266 * copy shaders). On the other hand, when the API switches from a GS to
1267 * no GS and then back to the same GS used originally, the GS state is
1268 * not sent again.
1269 */
1270 if (!gs) {
1271 unsigned mode = V_028A40_GS_OFF;
1272
1273 /* PrimID needs GS scenario A. */
1274 if (enable_prim_id)
1275 mode = V_028A40_GS_SCENARIO_A;
1276
1277 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1278 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1279 } else {
1280 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1281 sscreen->info.chip_class);
1282 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1283 }
1284
1285 if (sscreen->info.chip_class <= GFX8) {
1286 /* Reuse needs to be set off if we write oViewport. */
1287 shader->ctx_reg.vs.vgt_reuse_off =
1288 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1289 }
1290
1291 va = shader->bo->gpu_address;
1292 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1293
1294 if (gs) {
1295 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1296 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1297 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1298 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1299 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1300 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1301 */
1302 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
1303
1304 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1305 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1306 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1307 } else {
1308 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1309 }
1310 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1311 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1312 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1313 } else
1314 unreachable("invalid shader selector type");
1315
1316 /* VS is required to export at least one param. */
1317 nparams = MAX2(shader->info.nr_param_exports, 1);
1318 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1319
1320 shader->ctx_reg.vs.spi_shader_pos_format =
1321 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1322 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1323 V_02870C_SPI_SHADER_4COMP :
1324 V_02870C_SPI_SHADER_NONE) |
1325 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1326 V_02870C_SPI_SHADER_4COMP :
1327 V_02870C_SPI_SHADER_NONE) |
1328 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1329 V_02870C_SPI_SHADER_4COMP :
1330 V_02870C_SPI_SHADER_NONE);
1331
1332 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1333
1334 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1335 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1336 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
1337 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
1338 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
1339 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1340 S_00B128_DX10_CLAMP(1) |
1341 S_00B128_FLOAT_MODE(shader->config.float_mode));
1342 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
1343 S_00B12C_USER_SGPR(num_user_sgprs) |
1344 S_00B12C_OC_LDS_EN(oc_lds_en) |
1345 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1346 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1347 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1348 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1349 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
1350 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1351
1352 if (window_space)
1353 shader->ctx_reg.vs.pa_cl_vte_cntl =
1354 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1355 else
1356 shader->ctx_reg.vs.pa_cl_vte_cntl =
1357 S_028818_VTX_W0_FMT(1) |
1358 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1359 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1360 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1361
1362 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1363 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1364
1365 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1366 }
1367
1368 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1369 {
1370 struct tgsi_shader_info *info = &ps->selector->info;
1371 unsigned num_colors = !!(info->colors_read & 0x0f) +
1372 !!(info->colors_read & 0xf0);
1373 unsigned num_interp = ps->selector->info.num_inputs +
1374 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1375
1376 assert(num_interp <= 32);
1377 return MIN2(num_interp, 32);
1378 }
1379
1380 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1381 {
1382 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1383 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1384
1385 /* If the i-th target format is set, all previous target formats must
1386 * be non-zero to avoid hangs.
1387 */
1388 for (i = 0; i < num_targets; i++)
1389 if (!(value & (0xf << (i * 4))))
1390 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1391
1392 return value;
1393 }
1394
1395 static void si_emit_shader_ps(struct si_context *sctx)
1396 {
1397 struct si_shader *shader = sctx->queued.named.ps->shader;
1398 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1399
1400 if (!shader)
1401 return;
1402
1403 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1404 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1405 SI_TRACKED_SPI_PS_INPUT_ENA,
1406 shader->ctx_reg.ps.spi_ps_input_ena,
1407 shader->ctx_reg.ps.spi_ps_input_addr);
1408
1409 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1410 SI_TRACKED_SPI_BARYC_CNTL,
1411 shader->ctx_reg.ps.spi_baryc_cntl);
1412 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1413 SI_TRACKED_SPI_PS_IN_CONTROL,
1414 shader->ctx_reg.ps.spi_ps_in_control);
1415
1416 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1417 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1418 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1419 shader->ctx_reg.ps.spi_shader_z_format,
1420 shader->ctx_reg.ps.spi_shader_col_format);
1421
1422 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1423 SI_TRACKED_CB_SHADER_MASK,
1424 shader->ctx_reg.ps.cb_shader_mask);
1425
1426 if (initial_cdw != sctx->gfx_cs->current.cdw)
1427 sctx->context_roll = true;
1428 }
1429
1430 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1431 {
1432 struct tgsi_shader_info *info = &shader->selector->info;
1433 struct si_pm4_state *pm4;
1434 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1435 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1436 uint64_t va;
1437 unsigned input_ena = shader->config.spi_ps_input_ena;
1438
1439 /* we need to enable at least one of them, otherwise we hang the GPU */
1440 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1441 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1442 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1443 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1444 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1445 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1446 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1447 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1448 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1449 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1450 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1451 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1452 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1453 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1454
1455 /* Validate interpolation optimization flags (read as implications). */
1456 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1457 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1458 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1459 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1460 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1461 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1462 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1463 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1464 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1465 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1466 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1467 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1468 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1469 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1470 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1471 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1472 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1473 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1474
1475 /* Validate cases when the optimizations are off (read as implications). */
1476 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1477 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1478 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1479 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1480 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1481 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1482
1483 pm4 = si_get_shader_pm4_state(shader);
1484 if (!pm4)
1485 return;
1486
1487 pm4->atom.emit = si_emit_shader_ps;
1488
1489 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1490 * Possible vaules:
1491 * 0 -> Position = pixel center
1492 * 1 -> Position = pixel centroid
1493 * 2 -> Position = at sample position
1494 *
1495 * From GLSL 4.5 specification, section 7.1:
1496 * "The variable gl_FragCoord is available as an input variable from
1497 * within fragment shaders and it holds the window relative coordinates
1498 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1499 * value can be for any location within the pixel, or one of the
1500 * fragment samples. The use of centroid does not further restrict
1501 * this value to be inside the current primitive."
1502 *
1503 * Meaning that centroid has no effect and we can return anything within
1504 * the pixel. Thus, return the value at sample position, because that's
1505 * the most accurate one shaders can get.
1506 */
1507 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1508
1509 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1510 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1511 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1512
1513 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1514 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1515
1516 /* Ensure that some export memory is always allocated, for two reasons:
1517 *
1518 * 1) Correctness: The hardware ignores the EXEC mask if no export
1519 * memory is allocated, so KILL and alpha test do not work correctly
1520 * without this.
1521 * 2) Performance: Every shader needs at least a NULL export, even when
1522 * it writes no color/depth output. The NULL export instruction
1523 * stalls without this setting.
1524 *
1525 * Don't add this to CB_SHADER_MASK.
1526 */
1527 if (!spi_shader_col_format &&
1528 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1529 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1530
1531 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1532 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1533
1534 /* Set interpolation controls. */
1535 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1536
1537 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1538 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1539 shader->ctx_reg.ps.spi_shader_z_format =
1540 ac_get_spi_shader_z_format(info->writes_z,
1541 info->writes_stencil,
1542 info->writes_samplemask);
1543 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1544 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1545
1546 va = shader->bo->gpu_address;
1547 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1548 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1549 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1550
1551 uint32_t rsrc1 =
1552 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1553 S_00B028_DX10_CLAMP(1) |
1554 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1555 S_00B028_FLOAT_MODE(shader->config.float_mode);
1556
1557 if (sscreen->info.chip_class < GFX10) {
1558 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1559 }
1560
1561 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1562 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1563 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1564 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1565 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1566 }
1567
1568 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1569 struct si_shader *shader)
1570 {
1571 switch (shader->selector->type) {
1572 case PIPE_SHADER_VERTEX:
1573 if (shader->key.as_ls)
1574 si_shader_ls(sscreen, shader);
1575 else if (shader->key.as_es)
1576 si_shader_es(sscreen, shader);
1577 else if (shader->key.as_ngg)
1578 gfx10_shader_ngg(sscreen, shader);
1579 else
1580 si_shader_vs(sscreen, shader, NULL);
1581 break;
1582 case PIPE_SHADER_TESS_CTRL:
1583 si_shader_hs(sscreen, shader);
1584 break;
1585 case PIPE_SHADER_TESS_EVAL:
1586 if (shader->key.as_es)
1587 si_shader_es(sscreen, shader);
1588 else if (shader->key.as_ngg)
1589 gfx10_shader_ngg(sscreen, shader);
1590 else
1591 si_shader_vs(sscreen, shader, NULL);
1592 break;
1593 case PIPE_SHADER_GEOMETRY:
1594 if (shader->key.as_ngg)
1595 gfx10_shader_ngg(sscreen, shader);
1596 else
1597 si_shader_gs(sscreen, shader);
1598 break;
1599 case PIPE_SHADER_FRAGMENT:
1600 si_shader_ps(sscreen, shader);
1601 break;
1602 default:
1603 assert(0);
1604 }
1605 }
1606
1607 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1608 {
1609 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1610 if (sctx->queued.named.dsa)
1611 return sctx->queued.named.dsa->alpha_func;
1612
1613 return PIPE_FUNC_ALWAYS;
1614 }
1615
1616 void si_shader_selector_key_vs(struct si_context *sctx,
1617 struct si_shader_selector *vs,
1618 struct si_shader_key *key,
1619 struct si_vs_prolog_bits *prolog_key)
1620 {
1621 if (!sctx->vertex_elements ||
1622 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS])
1623 return;
1624
1625 struct si_vertex_elements *elts = sctx->vertex_elements;
1626
1627 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1628 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1629 prolog_key->unpack_instance_id_from_vertex_id =
1630 sctx->prim_discard_cs_instancing;
1631
1632 /* Prefer a monolithic shader to allow scheduling divisions around
1633 * VBO loads. */
1634 if (prolog_key->instance_divisor_is_fetched)
1635 key->opt.prefer_mono = 1;
1636
1637 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1638 unsigned count_mask = (1 << count) - 1;
1639 unsigned fix = elts->fix_fetch_always & count_mask;
1640 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1641
1642 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1643 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1644 while (mask) {
1645 unsigned i = u_bit_scan(&mask);
1646 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1647 unsigned vbidx = elts->vertex_buffer_index[i];
1648 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1649 unsigned align_mask = (1 << log_hw_load_size) - 1;
1650 if (vb->buffer_offset & align_mask ||
1651 vb->stride & align_mask) {
1652 fix |= 1 << i;
1653 opencode |= 1 << i;
1654 }
1655 }
1656 }
1657
1658 while (fix) {
1659 unsigned i = u_bit_scan(&fix);
1660 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1661 }
1662 key->mono.vs_fetch_opencode = opencode;
1663 }
1664
1665 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1666 struct si_shader_selector *vs,
1667 struct si_shader_key *key)
1668 {
1669 struct si_shader_selector *ps = sctx->ps_shader.cso;
1670
1671 key->opt.clip_disable =
1672 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1673 (vs->info.clipdist_writemask ||
1674 vs->info.writes_clipvertex) &&
1675 !vs->info.culldist_writemask;
1676
1677 /* Find out if PS is disabled. */
1678 bool ps_disabled = true;
1679 if (ps) {
1680 const struct si_state_blend *blend = sctx->queued.named.blend;
1681 bool alpha_to_coverage = blend && blend->alpha_to_coverage;
1682 bool ps_modifies_zs = ps->info.uses_kill ||
1683 ps->info.writes_z ||
1684 ps->info.writes_stencil ||
1685 ps->info.writes_samplemask ||
1686 alpha_to_coverage ||
1687 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1688 unsigned ps_colormask = si_get_total_colormask(sctx);
1689
1690 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1691 (!ps_colormask &&
1692 !ps_modifies_zs &&
1693 !ps->info.writes_memory);
1694 }
1695
1696 /* Find out which VS outputs aren't used by the PS. */
1697 uint64_t outputs_written = vs->outputs_written_before_ps;
1698 uint64_t inputs_read = 0;
1699
1700 /* Ignore outputs that are not passed from VS to PS. */
1701 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1702 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1703 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1704
1705 if (!ps_disabled) {
1706 inputs_read = ps->inputs_read;
1707 }
1708
1709 uint64_t linked = outputs_written & inputs_read;
1710
1711 key->opt.kill_outputs = ~linked & outputs_written;
1712 }
1713
1714 /* Compute the key for the hw shader variant */
1715 static inline void si_shader_selector_key(struct pipe_context *ctx,
1716 struct si_shader_selector *sel,
1717 union si_vgt_stages_key stages_key,
1718 struct si_shader_key *key)
1719 {
1720 struct si_context *sctx = (struct si_context *)ctx;
1721
1722 memset(key, 0, sizeof(*key));
1723
1724 switch (sel->type) {
1725 case PIPE_SHADER_VERTEX:
1726 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1727
1728 if (sctx->tes_shader.cso)
1729 key->as_ls = 1;
1730 else if (sctx->gs_shader.cso)
1731 key->as_es = 1;
1732 else {
1733 key->as_ngg = stages_key.u.ngg;
1734 si_shader_selector_key_hw_vs(sctx, sel, key);
1735
1736 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1737 key->mono.u.vs_export_prim_id = 1;
1738 }
1739 break;
1740 case PIPE_SHADER_TESS_CTRL:
1741 if (sctx->chip_class >= GFX9) {
1742 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1743 key, &key->part.tcs.ls_prolog);
1744 key->part.tcs.ls = sctx->vs_shader.cso;
1745
1746 /* When the LS VGPR fix is needed, monolithic shaders
1747 * can:
1748 * - avoid initializing EXEC in both the LS prolog
1749 * and the LS main part when !vs_needs_prolog
1750 * - remove the fixup for unused input VGPRs
1751 */
1752 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1753
1754 /* The LS output / HS input layout can be communicated
1755 * directly instead of via user SGPRs for merged LS-HS.
1756 * The LS VGPR fix prefers this too.
1757 */
1758 key->opt.prefer_mono = 1;
1759 }
1760
1761 key->part.tcs.epilog.prim_mode =
1762 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1763 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1764 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1765 key->part.tcs.epilog.tes_reads_tess_factors =
1766 sctx->tes_shader.cso->info.reads_tess_factors;
1767
1768 if (sel == sctx->fixed_func_tcs_shader.cso)
1769 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1770 break;
1771 case PIPE_SHADER_TESS_EVAL:
1772 if (sctx->gs_shader.cso)
1773 key->as_es = 1;
1774 else {
1775 key->as_ngg = stages_key.u.ngg;
1776 si_shader_selector_key_hw_vs(sctx, sel, key);
1777
1778 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1779 key->mono.u.vs_export_prim_id = 1;
1780 }
1781 break;
1782 case PIPE_SHADER_GEOMETRY:
1783 if (sctx->chip_class >= GFX9) {
1784 if (sctx->tes_shader.cso) {
1785 key->part.gs.es = sctx->tes_shader.cso;
1786 } else {
1787 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1788 key, &key->part.gs.vs_prolog);
1789 key->part.gs.es = sctx->vs_shader.cso;
1790 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1791 }
1792
1793 key->as_ngg = stages_key.u.ngg;
1794
1795 /* Merged ES-GS can have unbalanced wave usage.
1796 *
1797 * ES threads are per-vertex, while GS threads are
1798 * per-primitive. So without any amplification, there
1799 * are fewer GS threads than ES threads, which can result
1800 * in empty (no-op) GS waves. With too much amplification,
1801 * there are more GS threads than ES threads, which
1802 * can result in empty (no-op) ES waves.
1803 *
1804 * Non-monolithic shaders are implemented by setting EXEC
1805 * at the beginning of shader parts, and don't jump to
1806 * the end if EXEC is 0.
1807 *
1808 * Monolithic shaders use conditional blocks, so they can
1809 * jump and skip empty waves of ES or GS. So set this to
1810 * always use optimized variants, which are monolithic.
1811 */
1812 key->opt.prefer_mono = 1;
1813 }
1814 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1815 break;
1816 case PIPE_SHADER_FRAGMENT: {
1817 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1818 struct si_state_blend *blend = sctx->queued.named.blend;
1819
1820 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1821 sel->info.colors_written == 0x1)
1822 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1823
1824 if (blend) {
1825 /* Select the shader color format based on whether
1826 * blending or alpha are needed.
1827 */
1828 key->part.ps.epilog.spi_shader_col_format =
1829 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1830 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1831 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1832 sctx->framebuffer.spi_shader_col_format_blend) |
1833 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1834 sctx->framebuffer.spi_shader_col_format_alpha) |
1835 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1836 sctx->framebuffer.spi_shader_col_format);
1837 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1838
1839 /* The output for dual source blending should have
1840 * the same format as the first output.
1841 */
1842 if (blend->dual_src_blend)
1843 key->part.ps.epilog.spi_shader_col_format |=
1844 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1845 } else
1846 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1847
1848 /* If alpha-to-coverage is enabled, we have to export alpha
1849 * even if there is no color buffer.
1850 */
1851 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1852 blend && blend->alpha_to_coverage)
1853 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1854
1855 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1856 * to the range supported by the type if a channel has less
1857 * than 16 bits and the export format is 16_ABGR.
1858 */
1859 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1860 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1861 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1862 }
1863
1864 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1865 if (!key->part.ps.epilog.last_cbuf) {
1866 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1867 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1868 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1869 }
1870
1871 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1872 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1873
1874 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1875 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1876
1877 if (sctx->queued.named.blend) {
1878 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1879 rs->multisample_enable;
1880 }
1881
1882 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1883 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1884 (is_line && rs->line_smooth)) &&
1885 sctx->framebuffer.nr_samples <= 1;
1886 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1887
1888 if (sctx->ps_iter_samples > 1 &&
1889 sel->info.reads_samplemask) {
1890 key->part.ps.prolog.samplemask_log_ps_iter =
1891 util_logbase2(sctx->ps_iter_samples);
1892 }
1893
1894 if (rs->force_persample_interp &&
1895 rs->multisample_enable &&
1896 sctx->framebuffer.nr_samples > 1 &&
1897 sctx->ps_iter_samples > 1) {
1898 key->part.ps.prolog.force_persp_sample_interp =
1899 sel->info.uses_persp_center ||
1900 sel->info.uses_persp_centroid;
1901
1902 key->part.ps.prolog.force_linear_sample_interp =
1903 sel->info.uses_linear_center ||
1904 sel->info.uses_linear_centroid;
1905 } else if (rs->multisample_enable &&
1906 sctx->framebuffer.nr_samples > 1) {
1907 key->part.ps.prolog.bc_optimize_for_persp =
1908 sel->info.uses_persp_center &&
1909 sel->info.uses_persp_centroid;
1910 key->part.ps.prolog.bc_optimize_for_linear =
1911 sel->info.uses_linear_center &&
1912 sel->info.uses_linear_centroid;
1913 } else {
1914 /* Make sure SPI doesn't compute more than 1 pair
1915 * of (i,j), which is the optimization here. */
1916 key->part.ps.prolog.force_persp_center_interp =
1917 sel->info.uses_persp_center +
1918 sel->info.uses_persp_centroid +
1919 sel->info.uses_persp_sample > 1;
1920
1921 key->part.ps.prolog.force_linear_center_interp =
1922 sel->info.uses_linear_center +
1923 sel->info.uses_linear_centroid +
1924 sel->info.uses_linear_sample > 1;
1925
1926 if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
1927 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1928 }
1929
1930 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1931
1932 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1933 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
1934 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
1935 struct pipe_resource *tex = cb0->texture;
1936
1937 /* 1D textures are allocated and used as 2D on GFX9. */
1938 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
1939 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
1940 (tex->target == PIPE_TEXTURE_1D ||
1941 tex->target == PIPE_TEXTURE_1D_ARRAY);
1942 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
1943 tex->target == PIPE_TEXTURE_2D_ARRAY ||
1944 tex->target == PIPE_TEXTURE_CUBE ||
1945 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
1946 tex->target == PIPE_TEXTURE_3D;
1947 }
1948 break;
1949 }
1950 default:
1951 assert(0);
1952 }
1953
1954 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
1955 memset(&key->opt, 0, sizeof(key->opt));
1956 }
1957
1958 static void si_build_shader_variant(struct si_shader *shader,
1959 int thread_index,
1960 bool low_priority)
1961 {
1962 struct si_shader_selector *sel = shader->selector;
1963 struct si_screen *sscreen = sel->screen;
1964 struct ac_llvm_compiler *compiler;
1965 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1966
1967 if (thread_index >= 0) {
1968 if (low_priority) {
1969 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
1970 compiler = &sscreen->compiler_lowp[thread_index];
1971 } else {
1972 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
1973 compiler = &sscreen->compiler[thread_index];
1974 }
1975 if (!debug->async)
1976 debug = NULL;
1977 } else {
1978 assert(!low_priority);
1979 compiler = shader->compiler_ctx_state.compiler;
1980 }
1981
1982 if (unlikely(!si_shader_create(sscreen, compiler, shader, debug))) {
1983 PRINT_ERR("Failed to build shader variant (type=%u)\n",
1984 sel->type);
1985 shader->compilation_failed = true;
1986 return;
1987 }
1988
1989 if (shader->compiler_ctx_state.is_debug_context) {
1990 FILE *f = open_memstream(&shader->shader_log,
1991 &shader->shader_log_size);
1992 if (f) {
1993 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1994 fclose(f);
1995 }
1996 }
1997
1998 si_shader_init_pm4_state(sscreen, shader);
1999 }
2000
2001 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2002 {
2003 struct si_shader *shader = (struct si_shader *)job;
2004
2005 assert(thread_index >= 0);
2006
2007 si_build_shader_variant(shader, thread_index, true);
2008 }
2009
2010 static const struct si_shader_key zeroed;
2011
2012 static bool si_check_missing_main_part(struct si_screen *sscreen,
2013 struct si_shader_selector *sel,
2014 struct si_compiler_ctx_state *compiler_state,
2015 struct si_shader_key *key)
2016 {
2017 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2018
2019 if (!*mainp) {
2020 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2021
2022 if (!main_part)
2023 return false;
2024
2025 /* We can leave the fence as permanently signaled because the
2026 * main part becomes visible globally only after it has been
2027 * compiled. */
2028 util_queue_fence_init(&main_part->ready);
2029
2030 main_part->selector = sel;
2031 main_part->key.as_es = key->as_es;
2032 main_part->key.as_ls = key->as_ls;
2033 main_part->key.as_ngg = key->as_ngg;
2034 main_part->is_monolithic = false;
2035
2036 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
2037 main_part, &compiler_state->debug) != 0) {
2038 FREE(main_part);
2039 return false;
2040 }
2041 *mainp = main_part;
2042 }
2043 return true;
2044 }
2045
2046 /**
2047 * Select a shader variant according to the shader key.
2048 *
2049 * \param optimized_or_none If the key describes an optimized shader variant and
2050 * the compilation isn't finished, don't select any
2051 * shader and return an error.
2052 */
2053 int si_shader_select_with_key(struct si_screen *sscreen,
2054 struct si_shader_ctx_state *state,
2055 struct si_compiler_ctx_state *compiler_state,
2056 struct si_shader_key *key,
2057 int thread_index,
2058 bool optimized_or_none)
2059 {
2060 struct si_shader_selector *sel = state->cso;
2061 struct si_shader_selector *previous_stage_sel = NULL;
2062 struct si_shader *current = state->current;
2063 struct si_shader *iter, *shader = NULL;
2064
2065 again:
2066 /* Check if we don't need to change anything.
2067 * This path is also used for most shaders that don't need multiple
2068 * variants, it will cost just a computation of the key and this
2069 * test. */
2070 if (likely(current &&
2071 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2072 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2073 if (current->is_optimized) {
2074 if (optimized_or_none)
2075 return -1;
2076
2077 memset(&key->opt, 0, sizeof(key->opt));
2078 goto current_not_ready;
2079 }
2080
2081 util_queue_fence_wait(&current->ready);
2082 }
2083
2084 return current->compilation_failed ? -1 : 0;
2085 }
2086 current_not_ready:
2087
2088 /* This must be done before the mutex is locked, because async GS
2089 * compilation calls this function too, and therefore must enter
2090 * the mutex first.
2091 *
2092 * Only wait if we are in a draw call. Don't wait if we are
2093 * in a compiler thread.
2094 */
2095 if (thread_index < 0)
2096 util_queue_fence_wait(&sel->ready);
2097
2098 mtx_lock(&sel->mutex);
2099
2100 /* Find the shader variant. */
2101 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2102 /* Don't check the "current" shader. We checked it above. */
2103 if (current != iter &&
2104 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2105 mtx_unlock(&sel->mutex);
2106
2107 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2108 /* If it's an optimized shader and its compilation has
2109 * been started but isn't done, use the unoptimized
2110 * shader so as not to cause a stall due to compilation.
2111 */
2112 if (iter->is_optimized) {
2113 if (optimized_or_none)
2114 return -1;
2115 memset(&key->opt, 0, sizeof(key->opt));
2116 goto again;
2117 }
2118
2119 util_queue_fence_wait(&iter->ready);
2120 }
2121
2122 if (iter->compilation_failed) {
2123 return -1; /* skip the draw call */
2124 }
2125
2126 state->current = iter;
2127 return 0;
2128 }
2129 }
2130
2131 /* Build a new shader. */
2132 shader = CALLOC_STRUCT(si_shader);
2133 if (!shader) {
2134 mtx_unlock(&sel->mutex);
2135 return -ENOMEM;
2136 }
2137
2138 util_queue_fence_init(&shader->ready);
2139
2140 shader->selector = sel;
2141 shader->key = *key;
2142 shader->compiler_ctx_state = *compiler_state;
2143
2144 /* If this is a merged shader, get the first shader's selector. */
2145 if (sscreen->info.chip_class >= GFX9) {
2146 if (sel->type == PIPE_SHADER_TESS_CTRL)
2147 previous_stage_sel = key->part.tcs.ls;
2148 else if (sel->type == PIPE_SHADER_GEOMETRY)
2149 previous_stage_sel = key->part.gs.es;
2150
2151 /* We need to wait for the previous shader. */
2152 if (previous_stage_sel && thread_index < 0)
2153 util_queue_fence_wait(&previous_stage_sel->ready);
2154 }
2155
2156 bool is_pure_monolithic =
2157 sscreen->use_monolithic_shaders ||
2158 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2159
2160 /* Compile the main shader part if it doesn't exist. This can happen
2161 * if the initial guess was wrong.
2162 *
2163 * The prim discard CS doesn't need the main shader part.
2164 */
2165 if (!is_pure_monolithic &&
2166 !key->opt.vs_as_prim_discard_cs) {
2167 bool ok = true;
2168
2169 /* Make sure the main shader part is present. This is needed
2170 * for shaders that can be compiled as VS, LS, or ES, and only
2171 * one of them is compiled at creation.
2172 *
2173 * It is also needed for GS, which can be compiled as non-NGG
2174 * and NGG.
2175 *
2176 * For merged shaders, check that the starting shader's main
2177 * part is present.
2178 */
2179 if (previous_stage_sel) {
2180 struct si_shader_key shader1_key = zeroed;
2181
2182 if (sel->type == PIPE_SHADER_TESS_CTRL)
2183 shader1_key.as_ls = 1;
2184 else if (sel->type == PIPE_SHADER_GEOMETRY)
2185 shader1_key.as_es = 1;
2186 else
2187 assert(0);
2188
2189 mtx_lock(&previous_stage_sel->mutex);
2190 ok = si_check_missing_main_part(sscreen,
2191 previous_stage_sel,
2192 compiler_state, &shader1_key);
2193 mtx_unlock(&previous_stage_sel->mutex);
2194 }
2195
2196 if (ok) {
2197 ok = si_check_missing_main_part(sscreen, sel,
2198 compiler_state, key);
2199 }
2200
2201 if (!ok) {
2202 FREE(shader);
2203 mtx_unlock(&sel->mutex);
2204 return -ENOMEM; /* skip the draw call */
2205 }
2206 }
2207
2208 /* Keep the reference to the 1st shader of merged shaders, so that
2209 * Gallium can't destroy it before we destroy the 2nd shader.
2210 *
2211 * Set sctx = NULL, because it's unused if we're not releasing
2212 * the shader, and we don't have any sctx here.
2213 */
2214 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2215 previous_stage_sel);
2216
2217 /* Monolithic-only shaders don't make a distinction between optimized
2218 * and unoptimized. */
2219 shader->is_monolithic =
2220 is_pure_monolithic ||
2221 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2222
2223 /* The prim discard CS is always optimized. */
2224 shader->is_optimized =
2225 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2226 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2227
2228 /* If it's an optimized shader, compile it asynchronously. */
2229 if (shader->is_optimized && thread_index < 0) {
2230 /* Compile it asynchronously. */
2231 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2232 shader, &shader->ready,
2233 si_build_shader_variant_low_priority, NULL);
2234
2235 /* Add only after the ready fence was reset, to guard against a
2236 * race with si_bind_XX_shader. */
2237 if (!sel->last_variant) {
2238 sel->first_variant = shader;
2239 sel->last_variant = shader;
2240 } else {
2241 sel->last_variant->next_variant = shader;
2242 sel->last_variant = shader;
2243 }
2244
2245 /* Use the default (unoptimized) shader for now. */
2246 memset(&key->opt, 0, sizeof(key->opt));
2247 mtx_unlock(&sel->mutex);
2248
2249 if (sscreen->options.sync_compile)
2250 util_queue_fence_wait(&shader->ready);
2251
2252 if (optimized_or_none)
2253 return -1;
2254 goto again;
2255 }
2256
2257 /* Reset the fence before adding to the variant list. */
2258 util_queue_fence_reset(&shader->ready);
2259
2260 if (!sel->last_variant) {
2261 sel->first_variant = shader;
2262 sel->last_variant = shader;
2263 } else {
2264 sel->last_variant->next_variant = shader;
2265 sel->last_variant = shader;
2266 }
2267
2268 mtx_unlock(&sel->mutex);
2269
2270 assert(!shader->is_optimized);
2271 si_build_shader_variant(shader, thread_index, false);
2272
2273 util_queue_fence_signal(&shader->ready);
2274
2275 if (!shader->compilation_failed)
2276 state->current = shader;
2277
2278 return shader->compilation_failed ? -1 : 0;
2279 }
2280
2281 static int si_shader_select(struct pipe_context *ctx,
2282 struct si_shader_ctx_state *state,
2283 union si_vgt_stages_key stages_key,
2284 struct si_compiler_ctx_state *compiler_state)
2285 {
2286 struct si_context *sctx = (struct si_context *)ctx;
2287 struct si_shader_key key;
2288
2289 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2290 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2291 &key, -1, false);
2292 }
2293
2294 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
2295 bool streamout,
2296 struct si_shader_key *key)
2297 {
2298 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2299
2300 switch (info->processor) {
2301 case PIPE_SHADER_VERTEX:
2302 switch (next_shader) {
2303 case PIPE_SHADER_GEOMETRY:
2304 key->as_es = 1;
2305 break;
2306 case PIPE_SHADER_TESS_CTRL:
2307 case PIPE_SHADER_TESS_EVAL:
2308 key->as_ls = 1;
2309 break;
2310 default:
2311 /* If POSITION isn't written, it can only be a HW VS
2312 * if streamout is used. If streamout isn't used,
2313 * assume that it's a HW LS. (the next shader is TCS)
2314 * This heuristic is needed for separate shader objects.
2315 */
2316 if (!info->writes_position && !streamout)
2317 key->as_ls = 1;
2318 }
2319 break;
2320
2321 case PIPE_SHADER_TESS_EVAL:
2322 if (next_shader == PIPE_SHADER_GEOMETRY ||
2323 !info->writes_position)
2324 key->as_es = 1;
2325 break;
2326 }
2327 }
2328
2329 /**
2330 * Compile the main shader part or the monolithic shader as part of
2331 * si_shader_selector initialization. Since it can be done asynchronously,
2332 * there is no way to report compile failures to applications.
2333 */
2334 static void si_init_shader_selector_async(void *job, int thread_index)
2335 {
2336 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2337 struct si_screen *sscreen = sel->screen;
2338 struct ac_llvm_compiler *compiler;
2339 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2340
2341 assert(!debug->debug_message || debug->async);
2342 assert(thread_index >= 0);
2343 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2344 compiler = &sscreen->compiler[thread_index];
2345
2346 if (sel->nir)
2347 si_lower_nir(sel);
2348
2349 /* Compile the main shader part for use with a prolog and/or epilog.
2350 * If this fails, the driver will try to compile a monolithic shader
2351 * on demand.
2352 */
2353 if (!sscreen->use_monolithic_shaders) {
2354 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2355 void *ir_binary = NULL;
2356
2357 if (!shader) {
2358 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2359 return;
2360 }
2361
2362 /* We can leave the fence signaled because use of the default
2363 * main part is guarded by the selector's ready fence. */
2364 util_queue_fence_init(&shader->ready);
2365
2366 shader->selector = sel;
2367 shader->is_monolithic = false;
2368 si_parse_next_shader_property(&sel->info,
2369 sel->so.num_outputs != 0,
2370 &shader->key);
2371 if (sscreen->info.chip_class >= GFX10 &&
2372 !sscreen->options.disable_ngg &&
2373 (((sel->type == PIPE_SHADER_VERTEX ||
2374 sel->type == PIPE_SHADER_TESS_EVAL) &&
2375 !shader->key.as_ls && !shader->key.as_es) ||
2376 sel->type == PIPE_SHADER_GEOMETRY))
2377 shader->key.as_ngg = 1;
2378
2379 if (sel->tokens || sel->nir)
2380 ir_binary = si_get_ir_binary(sel);
2381
2382 /* Try to load the shader from the shader cache. */
2383 mtx_lock(&sscreen->shader_cache_mutex);
2384
2385 if (ir_binary &&
2386 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
2387 mtx_unlock(&sscreen->shader_cache_mutex);
2388 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2389 } else {
2390 mtx_unlock(&sscreen->shader_cache_mutex);
2391
2392 /* Compile the shader if it hasn't been loaded from the cache. */
2393 if (si_compile_tgsi_shader(sscreen, compiler, shader,
2394 debug) != 0) {
2395 FREE(shader);
2396 FREE(ir_binary);
2397 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2398 return;
2399 }
2400
2401 if (ir_binary) {
2402 mtx_lock(&sscreen->shader_cache_mutex);
2403 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
2404 FREE(ir_binary);
2405 mtx_unlock(&sscreen->shader_cache_mutex);
2406 }
2407 }
2408
2409 *si_get_main_shader_part(sel, &shader->key) = shader;
2410
2411 /* Unset "outputs_written" flags for outputs converted to
2412 * DEFAULT_VAL, so that later inter-shader optimizations don't
2413 * try to eliminate outputs that don't exist in the final
2414 * shader.
2415 *
2416 * This is only done if non-monolithic shaders are enabled.
2417 */
2418 if ((sel->type == PIPE_SHADER_VERTEX ||
2419 sel->type == PIPE_SHADER_TESS_EVAL) &&
2420 !shader->key.as_ls &&
2421 !shader->key.as_es) {
2422 unsigned i;
2423
2424 for (i = 0; i < sel->info.num_outputs; i++) {
2425 unsigned offset = shader->info.vs_output_param_offset[i];
2426
2427 if (offset <= AC_EXP_PARAM_OFFSET_31)
2428 continue;
2429
2430 unsigned name = sel->info.output_semantic_name[i];
2431 unsigned index = sel->info.output_semantic_index[i];
2432 unsigned id;
2433
2434 switch (name) {
2435 case TGSI_SEMANTIC_GENERIC:
2436 /* don't process indices the function can't handle */
2437 if (index >= SI_MAX_IO_GENERIC)
2438 break;
2439 /* fall through */
2440 default:
2441 id = si_shader_io_get_unique_index(name, index, true);
2442 sel->outputs_written_before_ps &= ~(1ull << id);
2443 break;
2444 case TGSI_SEMANTIC_POSITION: /* ignore these */
2445 case TGSI_SEMANTIC_PSIZE:
2446 case TGSI_SEMANTIC_CLIPVERTEX:
2447 case TGSI_SEMANTIC_EDGEFLAG:
2448 break;
2449 }
2450 }
2451 }
2452 }
2453
2454 /* The GS copy shader is always pre-compiled.
2455 *
2456 * TODO-GFX10: We could compile the GS copy shader on demand, since it
2457 * is only used in the (rare) non-NGG case.
2458 */
2459 if (sel->type == PIPE_SHADER_GEOMETRY) {
2460 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2461 if (!sel->gs_copy_shader) {
2462 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2463 return;
2464 }
2465
2466 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2467 }
2468 }
2469
2470 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2471 struct util_queue_fence *ready_fence,
2472 struct si_compiler_ctx_state *compiler_ctx_state,
2473 void *job, util_queue_execute_func execute)
2474 {
2475 util_queue_fence_init(ready_fence);
2476
2477 struct util_async_debug_callback async_debug;
2478 bool debug =
2479 (sctx->debug.debug_message && !sctx->debug.async) ||
2480 sctx->is_debug ||
2481 si_can_dump_shader(sctx->screen, processor);
2482
2483 if (debug) {
2484 u_async_debug_init(&async_debug);
2485 compiler_ctx_state->debug = async_debug.base;
2486 }
2487
2488 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2489 ready_fence, execute, NULL);
2490
2491 if (debug) {
2492 util_queue_fence_wait(ready_fence);
2493 u_async_debug_drain(&async_debug, &sctx->debug);
2494 u_async_debug_cleanup(&async_debug);
2495 }
2496
2497 if (sctx->screen->options.sync_compile)
2498 util_queue_fence_wait(ready_fence);
2499 }
2500
2501 /* Return descriptor slot usage masks from the given shader info. */
2502 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2503 uint32_t *const_and_shader_buffers,
2504 uint64_t *samplers_and_images)
2505 {
2506 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2507
2508 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2509 num_constbufs = util_last_bit(info->const_buffers_declared);
2510 /* two 8-byte images share one 16-byte slot */
2511 num_images = align(util_last_bit(info->images_declared), 2);
2512 num_samplers = util_last_bit(info->samplers_declared);
2513
2514 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2515 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2516 *const_and_shader_buffers =
2517 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2518
2519 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2520 start = si_get_image_slot(num_images - 1) / 2;
2521 *samplers_and_images =
2522 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2523 }
2524
2525 static void *si_create_shader_selector(struct pipe_context *ctx,
2526 const struct pipe_shader_state *state)
2527 {
2528 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2529 struct si_context *sctx = (struct si_context*)ctx;
2530 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2531 int i;
2532
2533 if (!sel)
2534 return NULL;
2535
2536 pipe_reference_init(&sel->reference, 1);
2537 sel->screen = sscreen;
2538 sel->compiler_ctx_state.debug = sctx->debug;
2539 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2540
2541 sel->so = state->stream_output;
2542
2543 if (state->type == PIPE_SHADER_IR_TGSI) {
2544 sel->tokens = tgsi_dup_tokens(state->tokens);
2545 if (!sel->tokens) {
2546 FREE(sel);
2547 return NULL;
2548 }
2549
2550 tgsi_scan_shader(state->tokens, &sel->info);
2551 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2552 } else {
2553 assert(state->type == PIPE_SHADER_IR_NIR);
2554
2555 sel->nir = state->ir.nir;
2556
2557 si_nir_opts(sel->nir);
2558 si_nir_scan_shader(sel->nir, &sel->info);
2559 si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
2560 }
2561
2562 sel->type = sel->info.processor;
2563 p_atomic_inc(&sscreen->num_shaders_created);
2564 si_get_active_slot_masks(&sel->info,
2565 &sel->active_const_and_shader_buffers,
2566 &sel->active_samplers_and_images);
2567
2568 /* Record which streamout buffers are enabled. */
2569 for (i = 0; i < sel->so.num_outputs; i++) {
2570 sel->enabled_streamout_buffer_mask |=
2571 (1 << sel->so.output[i].output_buffer) <<
2572 (sel->so.output[i].stream * 4);
2573 }
2574
2575 /* The prolog is a no-op if there are no inputs. */
2576 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2577 sel->info.num_inputs &&
2578 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2579
2580 sel->force_correct_derivs_after_kill =
2581 sel->type == PIPE_SHADER_FRAGMENT &&
2582 sel->info.uses_derivatives &&
2583 sel->info.uses_kill &&
2584 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2585
2586 sel->prim_discard_cs_allowed =
2587 sel->type == PIPE_SHADER_VERTEX &&
2588 !sel->info.uses_bindless_images &&
2589 !sel->info.uses_bindless_samplers &&
2590 !sel->info.writes_memory &&
2591 !sel->info.writes_viewport_index &&
2592 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2593 !sel->so.num_outputs;
2594
2595 /* Set which opcode uses which (i,j) pair. */
2596 if (sel->info.uses_persp_opcode_interp_centroid)
2597 sel->info.uses_persp_centroid = true;
2598
2599 if (sel->info.uses_linear_opcode_interp_centroid)
2600 sel->info.uses_linear_centroid = true;
2601
2602 if (sel->info.uses_persp_opcode_interp_offset ||
2603 sel->info.uses_persp_opcode_interp_sample)
2604 sel->info.uses_persp_center = true;
2605
2606 if (sel->info.uses_linear_opcode_interp_offset ||
2607 sel->info.uses_linear_opcode_interp_sample)
2608 sel->info.uses_linear_center = true;
2609
2610 switch (sel->type) {
2611 case PIPE_SHADER_GEOMETRY:
2612 sel->gs_output_prim =
2613 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2614 sel->gs_max_out_vertices =
2615 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2616 sel->gs_num_invocations =
2617 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2618 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2619 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2620 sel->gs_max_out_vertices;
2621
2622 sel->max_gs_stream = 0;
2623 for (i = 0; i < sel->so.num_outputs; i++)
2624 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2625 sel->so.output[i].stream);
2626
2627 sel->gs_input_verts_per_prim =
2628 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2629 break;
2630
2631 case PIPE_SHADER_TESS_CTRL:
2632 /* Always reserve space for these. */
2633 sel->patch_outputs_written |=
2634 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2635 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2636 /* fall through */
2637 case PIPE_SHADER_VERTEX:
2638 case PIPE_SHADER_TESS_EVAL:
2639 for (i = 0; i < sel->info.num_outputs; i++) {
2640 unsigned name = sel->info.output_semantic_name[i];
2641 unsigned index = sel->info.output_semantic_index[i];
2642
2643 switch (name) {
2644 case TGSI_SEMANTIC_TESSINNER:
2645 case TGSI_SEMANTIC_TESSOUTER:
2646 case TGSI_SEMANTIC_PATCH:
2647 sel->patch_outputs_written |=
2648 1ull << si_shader_io_get_unique_index_patch(name, index);
2649 break;
2650
2651 case TGSI_SEMANTIC_GENERIC:
2652 /* don't process indices the function can't handle */
2653 if (index >= SI_MAX_IO_GENERIC)
2654 break;
2655 /* fall through */
2656 default:
2657 sel->outputs_written |=
2658 1ull << si_shader_io_get_unique_index(name, index, false);
2659 sel->outputs_written_before_ps |=
2660 1ull << si_shader_io_get_unique_index(name, index, true);
2661 break;
2662 case TGSI_SEMANTIC_EDGEFLAG:
2663 break;
2664 }
2665 }
2666 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2667 sel->lshs_vertex_stride = sel->esgs_itemsize;
2668
2669 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2670 * will start on a different bank. (except for the maximum 32*16).
2671 */
2672 if (sel->lshs_vertex_stride < 32*16)
2673 sel->lshs_vertex_stride += 4;
2674
2675 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2676 * conflicts, i.e. each vertex will start at a different bank.
2677 */
2678 if (sctx->chip_class >= GFX9)
2679 sel->esgs_itemsize += 4;
2680
2681 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2682 break;
2683
2684 case PIPE_SHADER_FRAGMENT:
2685 for (i = 0; i < sel->info.num_inputs; i++) {
2686 unsigned name = sel->info.input_semantic_name[i];
2687 unsigned index = sel->info.input_semantic_index[i];
2688
2689 switch (name) {
2690 case TGSI_SEMANTIC_GENERIC:
2691 /* don't process indices the function can't handle */
2692 if (index >= SI_MAX_IO_GENERIC)
2693 break;
2694 /* fall through */
2695 default:
2696 sel->inputs_read |=
2697 1ull << si_shader_io_get_unique_index(name, index, true);
2698 break;
2699 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2700 break;
2701 }
2702 }
2703
2704 for (i = 0; i < 8; i++)
2705 if (sel->info.colors_written & (1 << i))
2706 sel->colors_written_4bit |= 0xf << (4 * i);
2707
2708 for (i = 0; i < sel->info.num_inputs; i++) {
2709 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2710 int index = sel->info.input_semantic_index[i];
2711 sel->color_attr_index[index] = i;
2712 }
2713 }
2714 break;
2715 }
2716
2717 /* PA_CL_VS_OUT_CNTL */
2718 bool misc_vec_ena =
2719 sel->info.writes_psize || sel->info.writes_edgeflag ||
2720 sel->info.writes_layer || sel->info.writes_viewport_index;
2721 sel->pa_cl_vs_out_cntl =
2722 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2723 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2724 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2725 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2726 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2727 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2728 sel->clipdist_mask = sel->info.writes_clipvertex ?
2729 SIX_BITS : sel->info.clipdist_writemask;
2730 sel->culldist_mask = sel->info.culldist_writemask <<
2731 sel->info.num_written_clipdistance;
2732
2733 /* DB_SHADER_CONTROL */
2734 sel->db_shader_control =
2735 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2736 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2737 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2738 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2739
2740 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2741 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2742 sel->db_shader_control |=
2743 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2744 break;
2745 case TGSI_FS_DEPTH_LAYOUT_LESS:
2746 sel->db_shader_control |=
2747 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2748 break;
2749 }
2750
2751 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2752 *
2753 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2754 * --|-----------|------------|------------|--------------------|-------------------|-------------
2755 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2756 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2757 * 2 | false | true | n/a | LateZ | 1 | 0
2758 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2759 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2760 *
2761 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2762 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2763 *
2764 * Don't use ReZ without profiling !!!
2765 *
2766 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2767 * shaders.
2768 */
2769 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2770 /* Cases 3, 4. */
2771 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2772 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2773 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2774 } else if (sel->info.writes_memory) {
2775 /* Case 2. */
2776 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2777 S_02880C_EXEC_ON_HIER_FAIL(1);
2778 } else {
2779 /* Case 1. */
2780 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2781 }
2782
2783 (void) mtx_init(&sel->mutex, mtx_plain);
2784
2785 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2786 &sel->compiler_ctx_state, sel,
2787 si_init_shader_selector_async);
2788 return sel;
2789 }
2790
2791 static void si_update_streamout_state(struct si_context *sctx)
2792 {
2793 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2794
2795 if (!shader_with_so)
2796 return;
2797
2798 sctx->streamout.enabled_stream_buffers_mask =
2799 shader_with_so->enabled_streamout_buffer_mask;
2800 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2801 }
2802
2803 static void si_update_clip_regs(struct si_context *sctx,
2804 struct si_shader_selector *old_hw_vs,
2805 struct si_shader *old_hw_vs_variant,
2806 struct si_shader_selector *next_hw_vs,
2807 struct si_shader *next_hw_vs_variant)
2808 {
2809 if (next_hw_vs &&
2810 (!old_hw_vs ||
2811 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2812 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2813 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2814 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2815 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2816 !old_hw_vs_variant ||
2817 !next_hw_vs_variant ||
2818 old_hw_vs_variant->key.opt.clip_disable !=
2819 next_hw_vs_variant->key.opt.clip_disable))
2820 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2821 }
2822
2823 static void si_update_common_shader_state(struct si_context *sctx)
2824 {
2825 sctx->uses_bindless_samplers =
2826 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2827 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2828 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2829 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2830 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2831 sctx->uses_bindless_images =
2832 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2833 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2834 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2835 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2836 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2837 sctx->do_update_shaders = true;
2838 }
2839
2840 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2841 {
2842 struct si_context *sctx = (struct si_context *)ctx;
2843 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2844 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2845 struct si_shader_selector *sel = state;
2846
2847 if (sctx->vs_shader.cso == sel)
2848 return;
2849
2850 sctx->vs_shader.cso = sel;
2851 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2852 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2853
2854 si_update_common_shader_state(sctx);
2855 si_update_vs_viewport_state(sctx);
2856 si_set_active_descriptors_for_shader(sctx, sel);
2857 si_update_streamout_state(sctx);
2858 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2859 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2860 }
2861
2862 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2863 {
2864 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2865 (sctx->tes_shader.cso &&
2866 sctx->tes_shader.cso->info.uses_primid) ||
2867 (sctx->tcs_shader.cso &&
2868 sctx->tcs_shader.cso->info.uses_primid) ||
2869 (sctx->gs_shader.cso &&
2870 sctx->gs_shader.cso->info.uses_primid) ||
2871 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2872 sctx->ps_shader.cso->info.uses_primid);
2873 }
2874
2875 static bool si_update_ngg(struct si_context *sctx)
2876 {
2877 if (sctx->chip_class <= GFX9 ||
2878 sctx->screen->options.disable_ngg)
2879 return false;
2880
2881 bool new_ngg = true;
2882
2883 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2884 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
2885 sctx->gs_shader.cso->gs_num_invocations * sctx->gs_shader.cso->gs_max_out_vertices > 256)
2886 new_ngg = false;
2887
2888 if (new_ngg != sctx->ngg) {
2889 sctx->ngg = new_ngg;
2890 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2891 return true;
2892 }
2893 return false;
2894 }
2895
2896 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2897 {
2898 struct si_context *sctx = (struct si_context *)ctx;
2899 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2900 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2901 struct si_shader_selector *sel = state;
2902 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2903 bool ngg_changed;
2904
2905 if (sctx->gs_shader.cso == sel)
2906 return;
2907
2908 sctx->gs_shader.cso = sel;
2909 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2910 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2911
2912 si_update_common_shader_state(sctx);
2913 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2914
2915 ngg_changed = si_update_ngg(sctx);
2916 if (ngg_changed || enable_changed)
2917 si_shader_change_notify(sctx);
2918 if (enable_changed) {
2919 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2920 si_update_tess_uses_prim_id(sctx);
2921 }
2922 si_update_vs_viewport_state(sctx);
2923 si_set_active_descriptors_for_shader(sctx, sel);
2924 si_update_streamout_state(sctx);
2925 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2926 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2927 }
2928
2929 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2930 {
2931 struct si_context *sctx = (struct si_context *)ctx;
2932 struct si_shader_selector *sel = state;
2933 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2934
2935 if (sctx->tcs_shader.cso == sel)
2936 return;
2937
2938 sctx->tcs_shader.cso = sel;
2939 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
2940 si_update_tess_uses_prim_id(sctx);
2941
2942 si_update_common_shader_state(sctx);
2943
2944 if (enable_changed)
2945 sctx->last_tcs = NULL; /* invalidate derived tess state */
2946
2947 si_set_active_descriptors_for_shader(sctx, sel);
2948 }
2949
2950 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
2951 {
2952 struct si_context *sctx = (struct si_context *)ctx;
2953 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2954 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2955 struct si_shader_selector *sel = state;
2956 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
2957
2958 if (sctx->tes_shader.cso == sel)
2959 return;
2960
2961 sctx->tes_shader.cso = sel;
2962 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
2963 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
2964 si_update_tess_uses_prim_id(sctx);
2965
2966 si_update_common_shader_state(sctx);
2967 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2968
2969 if (enable_changed) {
2970 si_update_ngg(sctx);
2971 si_shader_change_notify(sctx);
2972 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
2973 }
2974 si_update_vs_viewport_state(sctx);
2975 si_set_active_descriptors_for_shader(sctx, sel);
2976 si_update_streamout_state(sctx);
2977 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2978 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2979 }
2980
2981 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2982 {
2983 struct si_context *sctx = (struct si_context *)ctx;
2984 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
2985 struct si_shader_selector *sel = state;
2986
2987 /* skip if supplied shader is one already in use */
2988 if (old_sel == sel)
2989 return;
2990
2991 sctx->ps_shader.cso = sel;
2992 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
2993
2994 si_update_common_shader_state(sctx);
2995 if (sel) {
2996 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2997 si_update_tess_uses_prim_id(sctx);
2998
2999 if (!old_sel ||
3000 old_sel->info.colors_written != sel->info.colors_written)
3001 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3002
3003 if (sctx->screen->has_out_of_order_rast &&
3004 (!old_sel ||
3005 old_sel->info.writes_memory != sel->info.writes_memory ||
3006 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3007 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3008 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3009 }
3010 si_set_active_descriptors_for_shader(sctx, sel);
3011 si_update_ps_colorbuf0_slot(sctx);
3012 }
3013
3014 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3015 {
3016 if (shader->is_optimized) {
3017 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3018 &shader->ready);
3019 }
3020
3021 util_queue_fence_destroy(&shader->ready);
3022
3023 if (shader->pm4) {
3024 switch (shader->selector->type) {
3025 case PIPE_SHADER_VERTEX:
3026 if (shader->key.as_ls) {
3027 assert(sctx->chip_class <= GFX8);
3028 si_pm4_delete_state(sctx, ls, shader->pm4);
3029 } else if (shader->key.as_es) {
3030 assert(sctx->chip_class <= GFX8);
3031 si_pm4_delete_state(sctx, es, shader->pm4);
3032 } else {
3033 si_pm4_delete_state(sctx, vs, shader->pm4);
3034 }
3035 break;
3036 case PIPE_SHADER_TESS_CTRL:
3037 si_pm4_delete_state(sctx, hs, shader->pm4);
3038 break;
3039 case PIPE_SHADER_TESS_EVAL:
3040 if (shader->key.as_es) {
3041 assert(sctx->chip_class <= GFX8);
3042 si_pm4_delete_state(sctx, es, shader->pm4);
3043 } else {
3044 si_pm4_delete_state(sctx, vs, shader->pm4);
3045 }
3046 break;
3047 case PIPE_SHADER_GEOMETRY:
3048 if (shader->is_gs_copy_shader)
3049 si_pm4_delete_state(sctx, vs, shader->pm4);
3050 else
3051 si_pm4_delete_state(sctx, gs, shader->pm4);
3052 break;
3053 case PIPE_SHADER_FRAGMENT:
3054 si_pm4_delete_state(sctx, ps, shader->pm4);
3055 break;
3056 }
3057 }
3058
3059 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3060 si_shader_destroy(shader);
3061 free(shader);
3062 }
3063
3064 void si_destroy_shader_selector(struct si_context *sctx,
3065 struct si_shader_selector *sel)
3066 {
3067 struct si_shader *p = sel->first_variant, *c;
3068 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3069 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3070 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3071 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3072 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3073 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3074 };
3075
3076 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3077
3078 if (current_shader[sel->type]->cso == sel) {
3079 current_shader[sel->type]->cso = NULL;
3080 current_shader[sel->type]->current = NULL;
3081 }
3082
3083 while (p) {
3084 c = p->next_variant;
3085 si_delete_shader(sctx, p);
3086 p = c;
3087 }
3088
3089 if (sel->main_shader_part)
3090 si_delete_shader(sctx, sel->main_shader_part);
3091 if (sel->main_shader_part_ls)
3092 si_delete_shader(sctx, sel->main_shader_part_ls);
3093 if (sel->main_shader_part_es)
3094 si_delete_shader(sctx, sel->main_shader_part_es);
3095 if (sel->main_shader_part_ngg)
3096 si_delete_shader(sctx, sel->main_shader_part_ngg);
3097 if (sel->gs_copy_shader)
3098 si_delete_shader(sctx, sel->gs_copy_shader);
3099
3100 util_queue_fence_destroy(&sel->ready);
3101 mtx_destroy(&sel->mutex);
3102 free(sel->tokens);
3103 ralloc_free(sel->nir);
3104 free(sel);
3105 }
3106
3107 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3108 {
3109 struct si_context *sctx = (struct si_context *)ctx;
3110 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3111
3112 si_shader_selector_reference(sctx, &sel, NULL);
3113 }
3114
3115 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3116 struct si_shader *vs, unsigned name,
3117 unsigned index, unsigned interpolate)
3118 {
3119 struct tgsi_shader_info *vsinfo = &vs->selector->info;
3120 unsigned j, offset, ps_input_cntl = 0;
3121
3122 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3123 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3124 name == TGSI_SEMANTIC_PRIMID)
3125 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3126
3127 if (name == TGSI_SEMANTIC_PCOORD ||
3128 (name == TGSI_SEMANTIC_TEXCOORD &&
3129 sctx->sprite_coord_enable & (1 << index))) {
3130 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3131 }
3132
3133 for (j = 0; j < vsinfo->num_outputs; j++) {
3134 if (name == vsinfo->output_semantic_name[j] &&
3135 index == vsinfo->output_semantic_index[j]) {
3136 offset = vs->info.vs_output_param_offset[j];
3137
3138 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3139 /* The input is loaded from parameter memory. */
3140 ps_input_cntl |= S_028644_OFFSET(offset);
3141 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3142 if (offset == AC_EXP_PARAM_UNDEFINED) {
3143 /* This can happen with depth-only rendering. */
3144 offset = 0;
3145 } else {
3146 /* The input is a DEFAULT_VAL constant. */
3147 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3148 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3149 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3150 }
3151
3152 ps_input_cntl = S_028644_OFFSET(0x20) |
3153 S_028644_DEFAULT_VAL(offset);
3154 }
3155 break;
3156 }
3157 }
3158
3159 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3160 /* PrimID is written after the last output when HW VS is used. */
3161 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3162 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3163 /* No corresponding output found, load defaults into input.
3164 * Don't set any other bits.
3165 * (FLAT_SHADE=1 completely changes behavior) */
3166 ps_input_cntl = S_028644_OFFSET(0x20);
3167 /* D3D 9 behaviour. GL is undefined */
3168 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3169 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3170 }
3171 return ps_input_cntl;
3172 }
3173
3174 static void si_emit_spi_map(struct si_context *sctx)
3175 {
3176 struct si_shader *ps = sctx->ps_shader.current;
3177 struct si_shader *vs = si_get_vs_state(sctx);
3178 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3179 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3180 unsigned spi_ps_input_cntl[32];
3181
3182 if (!ps || !ps->selector->info.num_inputs)
3183 return;
3184
3185 num_interp = si_get_ps_num_interp(ps);
3186 assert(num_interp > 0);
3187
3188 for (i = 0; i < psinfo->num_inputs; i++) {
3189 unsigned name = psinfo->input_semantic_name[i];
3190 unsigned index = psinfo->input_semantic_index[i];
3191 unsigned interpolate = psinfo->input_interpolate[i];
3192
3193 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3194 index, interpolate);
3195
3196 if (name == TGSI_SEMANTIC_COLOR) {
3197 assert(index < ARRAY_SIZE(bcol_interp));
3198 bcol_interp[index] = interpolate;
3199 }
3200 }
3201
3202 if (ps->key.part.ps.prolog.color_two_side) {
3203 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3204
3205 for (i = 0; i < 2; i++) {
3206 if (!(psinfo->colors_read & (0xf << (i * 4))))
3207 continue;
3208
3209 spi_ps_input_cntl[num_written++] =
3210 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3211
3212 }
3213 }
3214 assert(num_interp == num_written);
3215
3216 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3217 /* Dota 2: Only ~16% of SPI map updates set different values. */
3218 /* Talos: Only ~9% of SPI map updates set different values. */
3219 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3220 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3221 spi_ps_input_cntl,
3222 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3223
3224 if (initial_cdw != sctx->gfx_cs->current.cdw)
3225 sctx->context_roll = true;
3226 }
3227
3228 /**
3229 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3230 */
3231 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3232 {
3233 if (sctx->init_config_has_vgt_flush)
3234 return;
3235
3236 /* Done by Vulkan before VGT_FLUSH. */
3237 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3238 si_pm4_cmd_add(sctx->init_config,
3239 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3240 si_pm4_cmd_end(sctx->init_config, false);
3241
3242 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3243 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3244 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3245 si_pm4_cmd_end(sctx->init_config, false);
3246 sctx->init_config_has_vgt_flush = true;
3247 }
3248
3249 /* Initialize state related to ESGS / GSVS ring buffers */
3250 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3251 {
3252 struct si_shader_selector *es =
3253 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3254 struct si_shader_selector *gs = sctx->gs_shader.cso;
3255 struct si_pm4_state *pm4;
3256
3257 /* Chip constants. */
3258 unsigned num_se = sctx->screen->info.max_se;
3259 unsigned wave_size = 64;
3260 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3261 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3262 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3263 */
3264 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3265 unsigned alignment = 256 * num_se;
3266 /* The maximum size is 63.999 MB per SE. */
3267 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3268
3269 /* Calculate the minimum size. */
3270 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3271 wave_size, alignment);
3272
3273 /* These are recommended sizes, not minimum sizes. */
3274 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3275 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3276 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3277 gs->max_gsvs_emit_size;
3278
3279 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3280 esgs_ring_size = align(esgs_ring_size, alignment);
3281 gsvs_ring_size = align(gsvs_ring_size, alignment);
3282
3283 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3284 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3285
3286 /* Some rings don't have to be allocated if shaders don't use them.
3287 * (e.g. no varyings between ES and GS or GS and VS)
3288 *
3289 * GFX9 doesn't have the ESGS ring.
3290 */
3291 bool update_esgs = sctx->chip_class <= GFX8 &&
3292 esgs_ring_size &&
3293 (!sctx->esgs_ring ||
3294 sctx->esgs_ring->width0 < esgs_ring_size);
3295 bool update_gsvs = gsvs_ring_size &&
3296 (!sctx->gsvs_ring ||
3297 sctx->gsvs_ring->width0 < gsvs_ring_size);
3298
3299 if (!update_esgs && !update_gsvs)
3300 return true;
3301
3302 if (update_esgs) {
3303 pipe_resource_reference(&sctx->esgs_ring, NULL);
3304 sctx->esgs_ring =
3305 pipe_aligned_buffer_create(sctx->b.screen,
3306 SI_RESOURCE_FLAG_UNMAPPABLE,
3307 PIPE_USAGE_DEFAULT,
3308 esgs_ring_size, alignment);
3309 if (!sctx->esgs_ring)
3310 return false;
3311 }
3312
3313 if (update_gsvs) {
3314 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3315 sctx->gsvs_ring =
3316 pipe_aligned_buffer_create(sctx->b.screen,
3317 SI_RESOURCE_FLAG_UNMAPPABLE,
3318 PIPE_USAGE_DEFAULT,
3319 gsvs_ring_size, alignment);
3320 if (!sctx->gsvs_ring)
3321 return false;
3322 }
3323
3324 /* Create the "init_config_gs_rings" state. */
3325 pm4 = CALLOC_STRUCT(si_pm4_state);
3326 if (!pm4)
3327 return false;
3328
3329 if (sctx->chip_class >= GFX7) {
3330 if (sctx->esgs_ring) {
3331 assert(sctx->chip_class <= GFX8);
3332 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3333 sctx->esgs_ring->width0 / 256);
3334 }
3335 if (sctx->gsvs_ring)
3336 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3337 sctx->gsvs_ring->width0 / 256);
3338 } else {
3339 if (sctx->esgs_ring)
3340 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3341 sctx->esgs_ring->width0 / 256);
3342 if (sctx->gsvs_ring)
3343 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3344 sctx->gsvs_ring->width0 / 256);
3345 }
3346
3347 /* Set the state. */
3348 if (sctx->init_config_gs_rings)
3349 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3350 sctx->init_config_gs_rings = pm4;
3351
3352 if (!sctx->init_config_has_vgt_flush) {
3353 si_init_config_add_vgt_flush(sctx);
3354 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3355 }
3356
3357 /* Flush the context to re-emit both init_config states. */
3358 sctx->initial_gfx_cs_size = 0; /* force flush */
3359 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3360
3361 /* Set ring bindings. */
3362 if (sctx->esgs_ring) {
3363 assert(sctx->chip_class <= GFX8);
3364 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3365 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3366 true, true, 4, 64, 0);
3367 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3368 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3369 false, false, 0, 0, 0);
3370 }
3371 if (sctx->gsvs_ring) {
3372 si_set_ring_buffer(sctx, SI_RING_GSVS,
3373 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3374 false, false, 0, 0, 0);
3375 }
3376
3377 return true;
3378 }
3379
3380 static void si_shader_lock(struct si_shader *shader)
3381 {
3382 mtx_lock(&shader->selector->mutex);
3383 if (shader->previous_stage_sel) {
3384 assert(shader->previous_stage_sel != shader->selector);
3385 mtx_lock(&shader->previous_stage_sel->mutex);
3386 }
3387 }
3388
3389 static void si_shader_unlock(struct si_shader *shader)
3390 {
3391 if (shader->previous_stage_sel)
3392 mtx_unlock(&shader->previous_stage_sel->mutex);
3393 mtx_unlock(&shader->selector->mutex);
3394 }
3395
3396 /**
3397 * @returns 1 if \p sel has been updated to use a new scratch buffer
3398 * 0 if not
3399 * < 0 if there was a failure
3400 */
3401 static int si_update_scratch_buffer(struct si_context *sctx,
3402 struct si_shader *shader)
3403 {
3404 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3405
3406 if (!shader)
3407 return 0;
3408
3409 /* This shader doesn't need a scratch buffer */
3410 if (shader->config.scratch_bytes_per_wave == 0)
3411 return 0;
3412
3413 /* Prevent race conditions when updating:
3414 * - si_shader::scratch_bo
3415 * - si_shader::binary::code
3416 * - si_shader::previous_stage::binary::code.
3417 */
3418 si_shader_lock(shader);
3419
3420 /* This shader is already configured to use the current
3421 * scratch buffer. */
3422 if (shader->scratch_bo == sctx->scratch_buffer) {
3423 si_shader_unlock(shader);
3424 return 0;
3425 }
3426
3427 assert(sctx->scratch_buffer);
3428
3429 /* Replace the shader bo with a new bo that has the relocs applied. */
3430 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3431 si_shader_unlock(shader);
3432 return -1;
3433 }
3434
3435 /* Update the shader state to use the new shader bo. */
3436 si_shader_init_pm4_state(sctx->screen, shader);
3437
3438 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3439
3440 si_shader_unlock(shader);
3441 return 1;
3442 }
3443
3444 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
3445 {
3446 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
3447 }
3448
3449 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3450 {
3451 return shader ? shader->config.scratch_bytes_per_wave : 0;
3452 }
3453
3454 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3455 {
3456 if (!sctx->tes_shader.cso)
3457 return NULL; /* tessellation disabled */
3458
3459 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3460 sctx->fixed_func_tcs_shader.current;
3461 }
3462
3463 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
3464 {
3465 unsigned bytes = 0;
3466
3467 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3468 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3469 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3470 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3471
3472 if (sctx->tes_shader.cso) {
3473 struct si_shader *tcs = si_get_tcs_current(sctx);
3474
3475 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
3476 }
3477 return bytes;
3478 }
3479
3480 static bool si_update_scratch_relocs(struct si_context *sctx)
3481 {
3482 struct si_shader *tcs = si_get_tcs_current(sctx);
3483 int r;
3484
3485 /* Update the shaders, so that they are using the latest scratch.
3486 * The scratch buffer may have been changed since these shaders were
3487 * last used, so we still need to try to update them, even if they
3488 * require scratch buffers smaller than the current size.
3489 */
3490 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3491 if (r < 0)
3492 return false;
3493 if (r == 1)
3494 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3495
3496 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3497 if (r < 0)
3498 return false;
3499 if (r == 1)
3500 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3501
3502 r = si_update_scratch_buffer(sctx, tcs);
3503 if (r < 0)
3504 return false;
3505 if (r == 1)
3506 si_pm4_bind_state(sctx, hs, tcs->pm4);
3507
3508 /* VS can be bound as LS, ES, or VS. */
3509 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3510 if (r < 0)
3511 return false;
3512 if (r == 1) {
3513 if (sctx->vs_shader.current->key.as_ls)
3514 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3515 else if (sctx->vs_shader.current->key.as_es)
3516 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3517 else if (sctx->vs_shader.current->key.as_ngg)
3518 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3519 else
3520 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3521 }
3522
3523 /* TES can be bound as ES or VS. */
3524 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3525 if (r < 0)
3526 return false;
3527 if (r == 1) {
3528 if (sctx->tes_shader.current->key.as_es)
3529 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3530 else if (sctx->tes_shader.current->key.as_ngg)
3531 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3532 else
3533 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3534 }
3535
3536 return true;
3537 }
3538
3539 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3540 {
3541 unsigned current_scratch_buffer_size =
3542 si_get_current_scratch_buffer_size(sctx);
3543 unsigned scratch_bytes_per_wave =
3544 si_get_max_scratch_bytes_per_wave(sctx);
3545 unsigned scratch_needed_size = scratch_bytes_per_wave *
3546 sctx->scratch_waves;
3547 unsigned spi_tmpring_size;
3548
3549 if (scratch_needed_size > 0) {
3550 if (scratch_needed_size > current_scratch_buffer_size) {
3551 /* Create a bigger scratch buffer */
3552 si_resource_reference(&sctx->scratch_buffer, NULL);
3553
3554 sctx->scratch_buffer =
3555 si_aligned_buffer_create(&sctx->screen->b,
3556 SI_RESOURCE_FLAG_UNMAPPABLE,
3557 PIPE_USAGE_DEFAULT,
3558 scratch_needed_size, 256);
3559 if (!sctx->scratch_buffer)
3560 return false;
3561
3562 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3563 si_context_add_resource_size(sctx,
3564 &sctx->scratch_buffer->b.b);
3565 }
3566
3567 if (!si_update_scratch_relocs(sctx))
3568 return false;
3569 }
3570
3571 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3572 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3573 "scratch size should already be aligned correctly.");
3574
3575 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3576 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3577 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3578 sctx->spi_tmpring_size = spi_tmpring_size;
3579 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3580 }
3581 return true;
3582 }
3583
3584 static void si_init_tess_factor_ring(struct si_context *sctx)
3585 {
3586 assert(!sctx->tess_rings);
3587
3588 /* The address must be aligned to 2^19, because the shader only
3589 * receives the high 13 bits.
3590 */
3591 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3592 SI_RESOURCE_FLAG_32BIT,
3593 PIPE_USAGE_DEFAULT,
3594 sctx->screen->tess_offchip_ring_size +
3595 sctx->screen->tess_factor_ring_size,
3596 1 << 19);
3597 if (!sctx->tess_rings)
3598 return;
3599
3600 si_init_config_add_vgt_flush(sctx);
3601
3602 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3603 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3604
3605 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3606 sctx->screen->tess_offchip_ring_size;
3607
3608 /* Append these registers to the init config state. */
3609 if (sctx->chip_class >= GFX7) {
3610 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3611 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3612 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3613 factor_va >> 8);
3614 if (sctx->chip_class >= GFX9)
3615 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3616 S_030944_BASE_HI(factor_va >> 40));
3617 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3618 sctx->screen->vgt_hs_offchip_param);
3619 } else {
3620 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3621 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3622 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3623 factor_va >> 8);
3624 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3625 sctx->screen->vgt_hs_offchip_param);
3626 }
3627
3628 /* Flush the context to re-emit the init_config state.
3629 * This is done only once in a lifetime of a context.
3630 */
3631 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3632 sctx->initial_gfx_cs_size = 0; /* force flush */
3633 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3634 }
3635
3636 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3637 union si_vgt_stages_key key)
3638 {
3639 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3640 uint32_t stages = 0;
3641
3642 if (key.u.tess) {
3643 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3644 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3645
3646 if (key.u.gs)
3647 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3648 S_028B54_GS_EN(1);
3649 else if (key.u.ngg)
3650 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3651 else
3652 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3653 } else if (key.u.gs) {
3654 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3655 S_028B54_GS_EN(1);
3656 } else if (key.u.ngg) {
3657 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3658 }
3659
3660 if (key.u.ngg) {
3661 stages |= S_028B54_PRIMGEN_EN(1);
3662 if (key.u.streamout)
3663 stages |= S_028B54_NGG_WAVE_ID_EN(1);
3664 } else if (key.u.gs)
3665 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3666
3667 if (screen->info.chip_class >= GFX9)
3668 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3669
3670 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3671 return pm4;
3672 }
3673
3674 static void si_update_vgt_shader_config(struct si_context *sctx,
3675 union si_vgt_stages_key key)
3676 {
3677 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3678
3679 if (unlikely(!*pm4))
3680 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3681 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3682 }
3683
3684 bool si_update_shaders(struct si_context *sctx)
3685 {
3686 struct pipe_context *ctx = (struct pipe_context*)sctx;
3687 struct si_compiler_ctx_state compiler_state;
3688 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3689 struct si_shader *old_vs = si_get_vs_state(sctx);
3690 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3691 struct si_shader *old_ps = sctx->ps_shader.current;
3692 union si_vgt_stages_key key;
3693 unsigned old_spi_shader_col_format =
3694 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3695 int r;
3696
3697 compiler_state.compiler = &sctx->compiler;
3698 compiler_state.debug = sctx->debug;
3699 compiler_state.is_debug_context = sctx->is_debug;
3700
3701 key.index = 0;
3702
3703 if (sctx->tes_shader.cso)
3704 key.u.tess = 1;
3705 if (sctx->gs_shader.cso)
3706 key.u.gs = 1;
3707
3708 if (sctx->chip_class >= GFX10) {
3709 key.u.ngg = sctx->ngg;
3710
3711 if (sctx->gs_shader.cso)
3712 key.u.streamout = !!sctx->gs_shader.cso->so.num_outputs;
3713 else if (sctx->tes_shader.cso)
3714 key.u.streamout = !!sctx->tes_shader.cso->so.num_outputs;
3715 else
3716 key.u.streamout = !!sctx->vs_shader.cso->so.num_outputs;
3717 }
3718
3719 /* Update TCS and TES. */
3720 if (sctx->tes_shader.cso) {
3721 if (!sctx->tess_rings) {
3722 si_init_tess_factor_ring(sctx);
3723 if (!sctx->tess_rings)
3724 return false;
3725 }
3726
3727 if (sctx->tcs_shader.cso) {
3728 r = si_shader_select(ctx, &sctx->tcs_shader, key,
3729 &compiler_state);
3730 if (r)
3731 return false;
3732 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3733 } else {
3734 if (!sctx->fixed_func_tcs_shader.cso) {
3735 sctx->fixed_func_tcs_shader.cso =
3736 si_create_fixed_func_tcs(sctx);
3737 if (!sctx->fixed_func_tcs_shader.cso)
3738 return false;
3739 }
3740
3741 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3742 key, &compiler_state);
3743 if (r)
3744 return false;
3745 si_pm4_bind_state(sctx, hs,
3746 sctx->fixed_func_tcs_shader.current->pm4);
3747 }
3748
3749 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3750 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3751 if (r)
3752 return false;
3753
3754 if (sctx->gs_shader.cso) {
3755 /* TES as ES */
3756 assert(sctx->chip_class <= GFX8);
3757 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3758 } else if (key.u.ngg) {
3759 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3760 } else {
3761 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3762 }
3763 }
3764 } else {
3765 if (sctx->chip_class <= GFX8)
3766 si_pm4_bind_state(sctx, ls, NULL);
3767 si_pm4_bind_state(sctx, hs, NULL);
3768 }
3769
3770 /* Update GS. */
3771 if (sctx->gs_shader.cso) {
3772 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
3773 if (r)
3774 return false;
3775 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3776 if (!key.u.ngg) {
3777 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3778
3779 if (!si_update_gs_ring_buffers(sctx))
3780 return false;
3781 } else {
3782 si_pm4_bind_state(sctx, vs, NULL);
3783 }
3784 } else {
3785 if (!key.u.ngg) {
3786 si_pm4_bind_state(sctx, gs, NULL);
3787 if (sctx->chip_class <= GFX8)
3788 si_pm4_bind_state(sctx, es, NULL);
3789 }
3790 }
3791
3792 /* Update VS. */
3793 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
3794 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
3795 if (r)
3796 return false;
3797
3798 if (!key.u.tess && !key.u.gs) {
3799 if (key.u.ngg) {
3800 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3801 si_pm4_bind_state(sctx, vs, NULL);
3802 } else {
3803 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3804 }
3805 } else if (sctx->tes_shader.cso) {
3806 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3807 } else {
3808 assert(sctx->gs_shader.cso);
3809 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3810 }
3811 }
3812
3813 si_update_vgt_shader_config(sctx, key);
3814
3815 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3816 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3817
3818 if (sctx->ps_shader.cso) {
3819 unsigned db_shader_control;
3820
3821 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
3822 if (r)
3823 return false;
3824 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3825
3826 db_shader_control =
3827 sctx->ps_shader.cso->db_shader_control |
3828 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3829
3830 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3831 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3832 sctx->flatshade != rs->flatshade) {
3833 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3834 sctx->flatshade = rs->flatshade;
3835 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3836 }
3837
3838 if (sctx->screen->rbplus_allowed &&
3839 si_pm4_state_changed(sctx, ps) &&
3840 (!old_ps ||
3841 old_spi_shader_col_format !=
3842 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3843 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3844
3845 if (sctx->ps_db_shader_control != db_shader_control) {
3846 sctx->ps_db_shader_control = db_shader_control;
3847 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3848 if (sctx->screen->dpbb_allowed)
3849 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3850 }
3851
3852 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3853 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3854 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3855
3856 if (sctx->chip_class == GFX6)
3857 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3858
3859 if (sctx->framebuffer.nr_samples <= 1)
3860 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3861 }
3862 }
3863
3864 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3865 si_pm4_state_enabled_and_changed(sctx, hs) ||
3866 si_pm4_state_enabled_and_changed(sctx, es) ||
3867 si_pm4_state_enabled_and_changed(sctx, gs) ||
3868 si_pm4_state_enabled_and_changed(sctx, vs) ||
3869 si_pm4_state_enabled_and_changed(sctx, ps)) {
3870 if (!si_update_spi_tmpring_size(sctx))
3871 return false;
3872 }
3873
3874 if (sctx->chip_class >= GFX7) {
3875 if (si_pm4_state_enabled_and_changed(sctx, ls))
3876 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3877 else if (!sctx->queued.named.ls)
3878 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3879
3880 if (si_pm4_state_enabled_and_changed(sctx, hs))
3881 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3882 else if (!sctx->queued.named.hs)
3883 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3884
3885 if (si_pm4_state_enabled_and_changed(sctx, es))
3886 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
3887 else if (!sctx->queued.named.es)
3888 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
3889
3890 if (si_pm4_state_enabled_and_changed(sctx, gs))
3891 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
3892 else if (!sctx->queued.named.gs)
3893 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
3894
3895 if (si_pm4_state_enabled_and_changed(sctx, vs))
3896 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
3897 else if (!sctx->queued.named.vs)
3898 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
3899
3900 if (si_pm4_state_enabled_and_changed(sctx, ps))
3901 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
3902 else if (!sctx->queued.named.ps)
3903 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
3904 }
3905
3906 sctx->do_update_shaders = false;
3907 return true;
3908 }
3909
3910 static void si_emit_scratch_state(struct si_context *sctx)
3911 {
3912 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3913
3914 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3915 sctx->spi_tmpring_size);
3916
3917 if (sctx->scratch_buffer) {
3918 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3919 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3920 RADEON_PRIO_SCRATCH_BUFFER);
3921 }
3922 }
3923
3924 void si_init_shader_functions(struct si_context *sctx)
3925 {
3926 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
3927 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
3928
3929 sctx->b.create_vs_state = si_create_shader_selector;
3930 sctx->b.create_tcs_state = si_create_shader_selector;
3931 sctx->b.create_tes_state = si_create_shader_selector;
3932 sctx->b.create_gs_state = si_create_shader_selector;
3933 sctx->b.create_fs_state = si_create_shader_selector;
3934
3935 sctx->b.bind_vs_state = si_bind_vs_shader;
3936 sctx->b.bind_tcs_state = si_bind_tcs_shader;
3937 sctx->b.bind_tes_state = si_bind_tes_shader;
3938 sctx->b.bind_gs_state = si_bind_gs_shader;
3939 sctx->b.bind_fs_state = si_bind_ps_shader;
3940
3941 sctx->b.delete_vs_state = si_delete_shader_selector;
3942 sctx->b.delete_tcs_state = si_delete_shader_selector;
3943 sctx->b.delete_tes_state = si_delete_shader_selector;
3944 sctx->b.delete_gs_state = si_delete_shader_selector;
3945 sctx->b.delete_fs_state = si_delete_shader_selector;
3946 }