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radeonsi/gfx10: NGG geometry shader PM4 and upload
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
45 * size as integer.
46 */
47 void *si_get_ir_binary(struct si_shader_selector *sel)
48 {
49 struct blob blob;
50 unsigned ir_size;
51 void *ir_binary;
52
53 if (sel->tokens) {
54 ir_binary = sel->tokens;
55 ir_size = tgsi_num_tokens(sel->tokens) *
56 sizeof(struct tgsi_token);
57 } else {
58 assert(sel->nir);
59
60 blob_init(&blob);
61 nir_serialize(&blob, sel->nir);
62 ir_binary = blob.data;
63 ir_size = blob.size;
64 }
65
66 unsigned size = 4 + ir_size + sizeof(sel->so);
67 char *result = (char*)MALLOC(size);
68 if (!result)
69 return NULL;
70
71 *((uint32_t*)result) = size;
72 memcpy(result + 4, ir_binary, ir_size);
73 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
74
75 if (sel->nir)
76 blob_finish(&blob);
77
78 return result;
79 }
80
81 /** Copy "data" to "ptr" and return the next dword following copied data. */
82 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
83 {
84 /* data may be NULL if size == 0 */
85 if (size)
86 memcpy(ptr, data, size);
87 ptr += DIV_ROUND_UP(size, 4);
88 return ptr;
89 }
90
91 /** Read data from "ptr". Return the next dword following the data. */
92 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
93 {
94 memcpy(data, ptr, size);
95 ptr += DIV_ROUND_UP(size, 4);
96 return ptr;
97 }
98
99 /**
100 * Write the size as uint followed by the data. Return the next dword
101 * following the copied data.
102 */
103 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
104 {
105 *ptr++ = size;
106 return write_data(ptr, data, size);
107 }
108
109 /**
110 * Read the size as uint followed by the data. Return both via parameters.
111 * Return the next dword following the data.
112 */
113 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
114 {
115 *size = *ptr++;
116 assert(*data == NULL);
117 if (!*size)
118 return ptr;
119 *data = malloc(*size);
120 return read_data(ptr, *data, *size);
121 }
122
123 /**
124 * Return the shader binary in a buffer. The first 4 bytes contain its size
125 * as integer.
126 */
127 static void *si_get_shader_binary(struct si_shader *shader)
128 {
129 /* There is always a size of data followed by the data itself. */
130 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
131 strlen(shader->binary.llvm_ir_string) + 1 : 0;
132
133 /* Refuse to allocate overly large buffers and guard against integer
134 * overflow. */
135 if (shader->binary.elf_size > UINT_MAX / 4 ||
136 llvm_ir_size > UINT_MAX / 4)
137 return NULL;
138
139 unsigned size =
140 4 + /* total size */
141 4 + /* CRC32 of the data below */
142 align(sizeof(shader->config), 4) +
143 align(sizeof(shader->info), 4) +
144 4 + align(shader->binary.elf_size, 4) +
145 4 + align(llvm_ir_size, 4);
146 void *buffer = CALLOC(1, size);
147 uint32_t *ptr = (uint32_t*)buffer;
148
149 if (!buffer)
150 return NULL;
151
152 *ptr++ = size;
153 ptr++; /* CRC32 is calculated at the end. */
154
155 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
156 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
157 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
158 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
159 assert((char *)ptr - (char *)buffer == size);
160
161 /* Compute CRC32. */
162 ptr = (uint32_t*)buffer;
163 ptr++;
164 *ptr = util_hash_crc32(ptr + 1, size - 8);
165
166 return buffer;
167 }
168
169 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
170 {
171 uint32_t *ptr = (uint32_t*)binary;
172 uint32_t size = *ptr++;
173 uint32_t crc32 = *ptr++;
174 unsigned chunk_size;
175 unsigned elf_size;
176
177 if (util_hash_crc32(ptr, size - 8) != crc32) {
178 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
179 return false;
180 }
181
182 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
183 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
184 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
185 &elf_size);
186 shader->binary.elf_size = elf_size;
187 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
188
189 return true;
190 }
191
192 /**
193 * Insert a shader into the cache. It's assumed the shader is not in the cache.
194 * Use si_shader_cache_load_shader before calling this.
195 *
196 * Returns false on failure, in which case the ir_binary should be freed.
197 */
198 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
199 struct si_shader *shader,
200 bool insert_into_disk_cache)
201 {
202 void *hw_binary;
203 struct hash_entry *entry;
204 uint8_t key[CACHE_KEY_SIZE];
205
206 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
207 if (entry)
208 return false; /* already added */
209
210 hw_binary = si_get_shader_binary(shader);
211 if (!hw_binary)
212 return false;
213
214 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
215 hw_binary) == NULL) {
216 FREE(hw_binary);
217 return false;
218 }
219
220 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
221 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
222 *((uint32_t *)ir_binary), key);
223 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
224 *((uint32_t *) hw_binary), NULL);
225 }
226
227 return true;
228 }
229
230 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
231 struct si_shader *shader)
232 {
233 struct hash_entry *entry =
234 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
235 if (!entry) {
236 if (sscreen->disk_shader_cache) {
237 unsigned char sha1[CACHE_KEY_SIZE];
238 size_t tg_size = *((uint32_t *) ir_binary);
239
240 disk_cache_compute_key(sscreen->disk_shader_cache,
241 ir_binary, tg_size, sha1);
242
243 size_t binary_size;
244 uint8_t *buffer =
245 disk_cache_get(sscreen->disk_shader_cache,
246 sha1, &binary_size);
247 if (!buffer)
248 return false;
249
250 if (binary_size < sizeof(uint32_t) ||
251 *((uint32_t*)buffer) != binary_size) {
252 /* Something has gone wrong discard the item
253 * from the cache and rebuild/link from
254 * source.
255 */
256 assert(!"Invalid radeonsi shader disk cache "
257 "item!");
258
259 disk_cache_remove(sscreen->disk_shader_cache,
260 sha1);
261 free(buffer);
262
263 return false;
264 }
265
266 if (!si_load_shader_binary(shader, buffer)) {
267 free(buffer);
268 return false;
269 }
270 free(buffer);
271
272 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
273 shader, false))
274 FREE(ir_binary);
275 } else {
276 return false;
277 }
278 } else {
279 if (si_load_shader_binary(shader, entry->data))
280 FREE(ir_binary);
281 else
282 return false;
283 }
284 p_atomic_inc(&sscreen->num_shader_cache_hits);
285 return true;
286 }
287
288 static uint32_t si_shader_cache_key_hash(const void *key)
289 {
290 /* The first dword is the key size. */
291 return util_hash_crc32(key, *(uint32_t*)key);
292 }
293
294 static bool si_shader_cache_key_equals(const void *a, const void *b)
295 {
296 uint32_t *keya = (uint32_t*)a;
297 uint32_t *keyb = (uint32_t*)b;
298
299 /* The first dword is the key size. */
300 if (*keya != *keyb)
301 return false;
302
303 return memcmp(keya, keyb, *keya) == 0;
304 }
305
306 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
307 {
308 FREE((void*)entry->key);
309 FREE(entry->data);
310 }
311
312 bool si_init_shader_cache(struct si_screen *sscreen)
313 {
314 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
315 sscreen->shader_cache =
316 _mesa_hash_table_create(NULL,
317 si_shader_cache_key_hash,
318 si_shader_cache_key_equals);
319
320 return sscreen->shader_cache != NULL;
321 }
322
323 void si_destroy_shader_cache(struct si_screen *sscreen)
324 {
325 if (sscreen->shader_cache)
326 _mesa_hash_table_destroy(sscreen->shader_cache,
327 si_destroy_shader_cache_entry);
328 mtx_destroy(&sscreen->shader_cache_mutex);
329 }
330
331 /* SHADER STATES */
332
333 static void si_set_tesseval_regs(struct si_screen *sscreen,
334 const struct si_shader_selector *tes,
335 struct si_pm4_state *pm4)
336 {
337 const struct tgsi_shader_info *info = &tes->info;
338 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
339 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
340 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
341 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
342 unsigned type, partitioning, topology, distribution_mode;
343
344 switch (tes_prim_mode) {
345 case PIPE_PRIM_LINES:
346 type = V_028B6C_TESS_ISOLINE;
347 break;
348 case PIPE_PRIM_TRIANGLES:
349 type = V_028B6C_TESS_TRIANGLE;
350 break;
351 case PIPE_PRIM_QUADS:
352 type = V_028B6C_TESS_QUAD;
353 break;
354 default:
355 assert(0);
356 return;
357 }
358
359 switch (tes_spacing) {
360 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
361 partitioning = V_028B6C_PART_FRAC_ODD;
362 break;
363 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
364 partitioning = V_028B6C_PART_FRAC_EVEN;
365 break;
366 case PIPE_TESS_SPACING_EQUAL:
367 partitioning = V_028B6C_PART_INTEGER;
368 break;
369 default:
370 assert(0);
371 return;
372 }
373
374 if (tes_point_mode)
375 topology = V_028B6C_OUTPUT_POINT;
376 else if (tes_prim_mode == PIPE_PRIM_LINES)
377 topology = V_028B6C_OUTPUT_LINE;
378 else if (tes_vertex_order_cw)
379 /* for some reason, this must be the other way around */
380 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
381 else
382 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
383
384 if (sscreen->has_distributed_tess) {
385 if (sscreen->info.family == CHIP_FIJI ||
386 sscreen->info.family >= CHIP_POLARIS10)
387 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
388 else
389 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
390 } else
391 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
392
393 assert(pm4->shader);
394 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
395 S_028B6C_PARTITIONING(partitioning) |
396 S_028B6C_TOPOLOGY(topology) |
397 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
398 }
399
400 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
401 * whether the "fractional odd" tessellation spacing is used.
402 *
403 * Possible VGT configurations and which state should set the register:
404 *
405 * Reg set in | VGT shader configuration | Value
406 * ------------------------------------------------------
407 * VS as VS | VS | 30
408 * VS as ES | ES -> GS -> VS | 30
409 * TES as VS | LS -> HS -> VS | 14 or 30
410 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
411 *
412 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
413 */
414 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
415 struct si_shader_selector *sel,
416 struct si_shader *shader,
417 struct si_pm4_state *pm4)
418 {
419 unsigned type = sel->type;
420
421 if (sscreen->info.family < CHIP_POLARIS10)
422 return;
423
424 /* VS as VS, or VS as ES: */
425 if ((type == PIPE_SHADER_VERTEX &&
426 (!shader ||
427 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
428 /* TES as VS, or TES as ES: */
429 type == PIPE_SHADER_TESS_EVAL) {
430 unsigned vtx_reuse_depth = 30;
431
432 if (type == PIPE_SHADER_TESS_EVAL &&
433 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
434 PIPE_TESS_SPACING_FRACTIONAL_ODD)
435 vtx_reuse_depth = 14;
436
437 assert(pm4->shader);
438 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
439 }
440 }
441
442 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
443 {
444 if (shader->pm4)
445 si_pm4_clear_state(shader->pm4);
446 else
447 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
448
449 if (shader->pm4) {
450 shader->pm4->shader = shader;
451 return shader->pm4;
452 } else {
453 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
454 return NULL;
455 }
456 }
457
458 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
459 {
460 /* Add the pointer to VBO descriptors. */
461 return num_always_on_user_sgprs + 1;
462 }
463
464 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
465 {
466 struct si_pm4_state *pm4;
467 unsigned vgpr_comp_cnt;
468 uint64_t va;
469
470 assert(sscreen->info.chip_class <= GFX8);
471
472 pm4 = si_get_shader_pm4_state(shader);
473 if (!pm4)
474 return;
475
476 va = shader->bo->gpu_address;
477 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
478
479 /* We need at least 2 components for LS.
480 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
481 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
482 */
483 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
484
485 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
486 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
487
488 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
489 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
490 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
491 S_00B528_DX10_CLAMP(1) |
492 S_00B528_FLOAT_MODE(shader->config.float_mode);
493 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
494 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
495 }
496
497 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
498 {
499 struct si_pm4_state *pm4;
500 uint64_t va;
501 unsigned ls_vgpr_comp_cnt = 0;
502
503 pm4 = si_get_shader_pm4_state(shader);
504 if (!pm4)
505 return;
506
507 va = shader->bo->gpu_address;
508 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
509
510 if (sscreen->info.chip_class >= GFX9) {
511 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
512 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
513
514 /* We need at least 2 components for LS.
515 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
516 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
517 */
518 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
519
520 unsigned num_user_sgprs =
521 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
522
523 shader->config.rsrc2 =
524 S_00B42C_USER_SGPR(num_user_sgprs) |
525 S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5) |
526 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
527 } else {
528 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
529 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
530
531 shader->config.rsrc2 =
532 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
533 S_00B42C_OC_LDS_EN(1) |
534 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
535 }
536
537 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
538 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
539 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
540 S_00B428_DX10_CLAMP(1) |
541 S_00B428_FLOAT_MODE(shader->config.float_mode) |
542 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
543
544 if (sscreen->info.chip_class <= GFX8) {
545 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
546 shader->config.rsrc2);
547 }
548 }
549
550 static void si_emit_shader_es(struct si_context *sctx)
551 {
552 struct si_shader *shader = sctx->queued.named.es->shader;
553 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
554
555 if (!shader)
556 return;
557
558 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
559 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
560 shader->selector->esgs_itemsize / 4);
561
562 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
563 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
564 SI_TRACKED_VGT_TF_PARAM,
565 shader->vgt_tf_param);
566
567 if (shader->vgt_vertex_reuse_block_cntl)
568 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
569 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
570 shader->vgt_vertex_reuse_block_cntl);
571
572 if (initial_cdw != sctx->gfx_cs->current.cdw)
573 sctx->context_roll = true;
574 }
575
576 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
577 {
578 struct si_pm4_state *pm4;
579 unsigned num_user_sgprs;
580 unsigned vgpr_comp_cnt;
581 uint64_t va;
582 unsigned oc_lds_en;
583
584 assert(sscreen->info.chip_class <= GFX8);
585
586 pm4 = si_get_shader_pm4_state(shader);
587 if (!pm4)
588 return;
589
590 pm4->atom.emit = si_emit_shader_es;
591 va = shader->bo->gpu_address;
592 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
593
594 if (shader->selector->type == PIPE_SHADER_VERTEX) {
595 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
596 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
597 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
598 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
599 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
600 num_user_sgprs = SI_TES_NUM_USER_SGPR;
601 } else
602 unreachable("invalid shader selector type");
603
604 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
605
606 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
607 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
608 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
609 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
610 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
611 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
612 S_00B328_DX10_CLAMP(1) |
613 S_00B328_FLOAT_MODE(shader->config.float_mode));
614 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
615 S_00B32C_USER_SGPR(num_user_sgprs) |
616 S_00B32C_OC_LDS_EN(oc_lds_en) |
617 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
618
619 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
620 si_set_tesseval_regs(sscreen, shader->selector, pm4);
621
622 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
623 }
624
625 static unsigned si_conv_prim_to_gs_out(unsigned mode)
626 {
627 static const int prim_conv[] = {
628 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
629 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
630 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
631 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
632 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
633 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
634 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
635 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
636 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
637 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
638 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
639 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
640 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
641 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
642 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
643 };
644 assert(mode < ARRAY_SIZE(prim_conv));
645
646 return prim_conv[mode];
647 }
648
649 void gfx9_get_gs_info(struct si_shader_selector *es,
650 struct si_shader_selector *gs,
651 struct gfx9_gs_info *out)
652 {
653 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
654 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
655 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
656 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
657
658 /* All these are in dwords: */
659 /* We can't allow using the whole LDS, because GS waves compete with
660 * other shader stages for LDS space. */
661 const unsigned max_lds_size = 8 * 1024;
662 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
663 unsigned esgs_lds_size;
664
665 /* All these are per subgroup: */
666 const unsigned max_out_prims = 32 * 1024;
667 const unsigned max_es_verts = 255;
668 const unsigned ideal_gs_prims = 64;
669 unsigned max_gs_prims, gs_prims;
670 unsigned min_es_verts, es_verts, worst_case_es_verts;
671
672 if (uses_adjacency || gs_num_invocations > 1)
673 max_gs_prims = 127 / gs_num_invocations;
674 else
675 max_gs_prims = 255;
676
677 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
678 * Make sure we don't go over the maximum value.
679 */
680 if (gs->gs_max_out_vertices > 0) {
681 max_gs_prims = MIN2(max_gs_prims,
682 max_out_prims /
683 (gs->gs_max_out_vertices * gs_num_invocations));
684 }
685 assert(max_gs_prims > 0);
686
687 /* If the primitive has adjacency, halve the number of vertices
688 * that will be reused in multiple primitives.
689 */
690 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
691
692 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
693 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
694
695 /* Compute ESGS LDS size based on the worst case number of ES vertices
696 * needed to create the target number of GS prims per subgroup.
697 */
698 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
699
700 /* If total LDS usage is too big, refactor partitions based on ratio
701 * of ESGS item sizes.
702 */
703 if (esgs_lds_size > max_lds_size) {
704 /* Our target GS Prims Per Subgroup was too large. Calculate
705 * the maximum number of GS Prims Per Subgroup that will fit
706 * into LDS, capped by the maximum that the hardware can support.
707 */
708 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
709 max_gs_prims);
710 assert(gs_prims > 0);
711 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
712 max_es_verts);
713
714 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
715 assert(esgs_lds_size <= max_lds_size);
716 }
717
718 /* Now calculate remaining ESGS information. */
719 if (esgs_lds_size)
720 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
721 else
722 es_verts = max_es_verts;
723
724 /* Vertices for adjacency primitives are not always reused, so restore
725 * it for ES_VERTS_PER_SUBGRP.
726 */
727 min_es_verts = gs->gs_input_verts_per_prim;
728
729 /* For normal primitives, the VGT only checks if they are past the ES
730 * verts per subgroup after allocating a full GS primitive and if they
731 * are, kick off a new subgroup. But if those additional ES verts are
732 * unique (e.g. not reused) we need to make sure there is enough LDS
733 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
734 */
735 es_verts -= min_es_verts - 1;
736
737 out->es_verts_per_subgroup = es_verts;
738 out->gs_prims_per_subgroup = gs_prims;
739 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
740 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
741 gs->gs_max_out_vertices;
742 out->esgs_ring_size = 4 * esgs_lds_size;
743
744 assert(out->max_prims_per_subgroup <= max_out_prims);
745 }
746
747 static void si_emit_shader_gs(struct si_context *sctx)
748 {
749 struct si_shader *shader = sctx->queued.named.gs->shader;
750 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
751
752 if (!shader)
753 return;
754
755 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
756 * R_028A68_VGT_GSVS_RING_OFFSET_3, R_028A6C_VGT_GS_OUT_PRIM_TYPE */
757 radeon_opt_set_context_reg4(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
758 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
759 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
760 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
761 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3,
762 shader->ctx_reg.gs.vgt_gs_out_prim_type);
763
764
765 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
766 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
767 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
768 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
769
770 /* R_028B38_VGT_GS_MAX_VERT_OUT */
771 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
772 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
773 shader->ctx_reg.gs.vgt_gs_max_vert_out);
774
775 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
776 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
777 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
778 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
779 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
780 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
781 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
782 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
783
784 /* R_028B90_VGT_GS_INSTANCE_CNT */
785 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
786 SI_TRACKED_VGT_GS_INSTANCE_CNT,
787 shader->ctx_reg.gs.vgt_gs_instance_cnt);
788
789 if (sctx->chip_class >= GFX9) {
790 /* R_028A44_VGT_GS_ONCHIP_CNTL */
791 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
792 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
793 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
794 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
795 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
796 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
797 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
798 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
799 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
800 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
801 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
802
803 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
804 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
805 SI_TRACKED_VGT_TF_PARAM,
806 shader->vgt_tf_param);
807 if (shader->vgt_vertex_reuse_block_cntl)
808 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
809 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
810 shader->vgt_vertex_reuse_block_cntl);
811 }
812
813 if (initial_cdw != sctx->gfx_cs->current.cdw)
814 sctx->context_roll = true;
815 }
816
817 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
818 {
819 struct si_shader_selector *sel = shader->selector;
820 const ubyte *num_components = sel->info.num_stream_output_components;
821 unsigned gs_num_invocations = sel->gs_num_invocations;
822 struct si_pm4_state *pm4;
823 uint64_t va;
824 unsigned max_stream = sel->max_gs_stream;
825 unsigned offset;
826
827 pm4 = si_get_shader_pm4_state(shader);
828 if (!pm4)
829 return;
830
831 pm4->atom.emit = si_emit_shader_gs;
832
833 offset = num_components[0] * sel->gs_max_out_vertices;
834 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
835
836 if (max_stream >= 1)
837 offset += num_components[1] * sel->gs_max_out_vertices;
838 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
839
840 if (max_stream >= 2)
841 offset += num_components[2] * sel->gs_max_out_vertices;
842 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
843
844 shader->ctx_reg.gs.vgt_gs_out_prim_type =
845 si_conv_prim_to_gs_out(sel->gs_output_prim);
846
847 if (max_stream >= 3)
848 offset += num_components[3] * sel->gs_max_out_vertices;
849 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
850
851 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
852 assert(offset < (1 << 15));
853
854 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
855
856 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
857 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
858 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
859 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
860
861 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
862 S_028B90_ENABLE(gs_num_invocations > 0);
863
864 va = shader->bo->gpu_address;
865 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
866
867 if (sscreen->info.chip_class >= GFX9) {
868 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
869 unsigned es_type = shader->key.part.gs.es->type;
870 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
871
872 if (es_type == PIPE_SHADER_VERTEX)
873 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
874 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
875 else if (es_type == PIPE_SHADER_TESS_EVAL)
876 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
877 else
878 unreachable("invalid shader selector type");
879
880 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
881 * VGPR[0:4] are always loaded.
882 */
883 if (sel->info.uses_invocationid)
884 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
885 else if (sel->info.uses_primid)
886 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
887 else if (input_prim >= PIPE_PRIM_TRIANGLES)
888 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
889 else
890 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
891
892 unsigned num_user_sgprs;
893 if (es_type == PIPE_SHADER_VERTEX)
894 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
895 else
896 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
897
898 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
899 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
900
901 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
902 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
903 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
904 S_00B228_DX10_CLAMP(1) |
905 S_00B228_FLOAT_MODE(shader->config.float_mode) |
906 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
907 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
908 S_00B22C_USER_SGPR(num_user_sgprs) |
909 S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5) |
910 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
911 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
912 S_00B22C_LDS_SIZE(shader->config.lds_size) |
913 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
914
915 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
916 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
917 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
918 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
919 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
920 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
921 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
922 shader->key.part.gs.es->esgs_itemsize / 4;
923
924 if (es_type == PIPE_SHADER_TESS_EVAL)
925 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
926
927 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
928 NULL, pm4);
929 } else {
930 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
931 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
932
933 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
934 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
935 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
936 S_00B228_DX10_CLAMP(1) |
937 S_00B228_FLOAT_MODE(shader->config.float_mode));
938 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
939 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
940 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
941 }
942 }
943
944 /* Common tail code for NGG primitive shaders. */
945 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
946 struct si_shader *shader,
947 unsigned initial_cdw)
948 {
949 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
950 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
951 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
952 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
953 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
954 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
955 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
956 SI_TRACKED_VGT_PRIMITIVEID_EN,
957 shader->ctx_reg.ngg.vgt_primitiveid_en);
958 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
959 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
960 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
961 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
962 SI_TRACKED_VGT_GS_INSTANCE_CNT,
963 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
964 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
965 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
966 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
967 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
968 SI_TRACKED_VGT_REUSE_OFF,
969 shader->ctx_reg.ngg.vgt_reuse_off);
970 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
971 SI_TRACKED_SPI_VS_OUT_CONFIG,
972 shader->ctx_reg.ngg.spi_vs_out_config);
973 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
974 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
975 shader->ctx_reg.ngg.spi_shader_idx_format,
976 shader->ctx_reg.ngg.spi_shader_pos_format);
977 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
978 SI_TRACKED_PA_CL_VTE_CNTL,
979 shader->ctx_reg.ngg.pa_cl_vte_cntl);
980
981 if (initial_cdw != sctx->gfx_cs->current.cdw)
982 sctx->context_roll = true;
983
984 if (shader->ge_cntl != sctx->last_multi_vgt_param) {
985 radeon_set_uconfig_reg(sctx->gfx_cs, R_03096C_GE_CNTL, shader->ge_cntl);
986 sctx->last_multi_vgt_param = shader->ge_cntl;
987 }
988 }
989
990 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
991 {
992 struct si_shader *shader = sctx->queued.named.gs->shader;
993 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
994
995 if (!shader)
996 return;
997
998 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
999 }
1000
1001 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1002 {
1003 struct si_shader *shader = sctx->queued.named.gs->shader;
1004 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1005
1006 if (!shader)
1007 return;
1008
1009 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1010 SI_TRACKED_VGT_TF_PARAM,
1011 shader->vgt_tf_param);
1012
1013 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1014 }
1015
1016 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1017 {
1018 struct si_shader *shader = sctx->queued.named.gs->shader;
1019 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1020
1021 if (!shader)
1022 return;
1023
1024 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1025 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1026 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1027
1028 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1029 }
1030
1031 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1032 {
1033 struct si_shader *shader = sctx->queued.named.gs->shader;
1034 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1035
1036 if (!shader)
1037 return;
1038
1039 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1040 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1041 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1042 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1043 SI_TRACKED_VGT_TF_PARAM,
1044 shader->vgt_tf_param);
1045
1046 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1047 }
1048
1049 /**
1050 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1051 * in NGG mode.
1052 */
1053 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1054 {
1055 const struct si_shader_selector *gs_sel = shader->selector;
1056 const struct tgsi_shader_info *gs_info = &gs_sel->info;
1057 enum pipe_shader_type gs_type = shader->selector->type;
1058 const struct si_shader_selector *es_sel =
1059 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1060 const struct tgsi_shader_info *es_info = &es_sel->info;
1061 enum pipe_shader_type es_type = es_sel->type;
1062 unsigned num_user_sgprs;
1063 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1064 uint64_t va;
1065 unsigned window_space =
1066 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1067 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1068 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1069 unsigned input_prim =
1070 gs_type == PIPE_SHADER_GEOMETRY ?
1071 gs_info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] :
1072 PIPE_PRIM_TRIANGLES; /* TODO: Optimize when primtype is known */
1073 bool break_wave_at_eoi = false;
1074 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1075 if (!pm4)
1076 return;
1077
1078 if (es_type == PIPE_SHADER_TESS_EVAL) {
1079 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1080 : gfx10_emit_shader_ngg_tess_nogs;
1081 } else {
1082 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1083 : gfx10_emit_shader_ngg_notess_nogs;
1084 }
1085
1086 va = shader->bo->gpu_address;
1087 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1088
1089 if (es_type == PIPE_SHADER_VERTEX) {
1090 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
1091 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
1092
1093 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1094 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1095 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1096 } else {
1097 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
1098 }
1099 } else {
1100 assert(es_type == PIPE_SHADER_TESS_EVAL);
1101 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1102 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1103
1104 if (es_enable_prim_id || gs_info->uses_primid)
1105 break_wave_at_eoi = true;
1106 }
1107
1108 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1109 * VGPR[0:4] are always loaded.
1110 */
1111 if (gs_info->uses_invocationid)
1112 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
1113 else if (gs_info->uses_primid)
1114 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1115 else if (input_prim >= PIPE_PRIM_TRIANGLES)
1116 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1117 else
1118 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1119
1120 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1121 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1122 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1123 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
1124 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1125 S_00B228_DX10_CLAMP(1) |
1126 S_00B228_MEM_ORDERED(1) |
1127 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1128 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1129 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1130 S_00B22C_USER_SGPR(num_user_sgprs) |
1131 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1132 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1133 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1134 S_00B22C_LDS_SIZE(shader->config.lds_size));
1135
1136 /* TODO: Use NO_PC_EXPORT when applicable. */
1137 nparams = MAX2(shader->info.nr_param_exports, 1);
1138 shader->ctx_reg.ngg.spi_vs_out_config =
1139 S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1140
1141 shader->ctx_reg.ngg.spi_shader_idx_format =
1142 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1143 shader->ctx_reg.ngg.spi_shader_pos_format =
1144 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1145 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1146 V_02870C_SPI_SHADER_4COMP :
1147 V_02870C_SPI_SHADER_NONE) |
1148 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1149 V_02870C_SPI_SHADER_4COMP :
1150 V_02870C_SPI_SHADER_NONE) |
1151 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1152 V_02870C_SPI_SHADER_4COMP :
1153 V_02870C_SPI_SHADER_NONE);
1154
1155 shader->ctx_reg.ngg.vgt_primitiveid_en =
1156 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1157 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id);
1158
1159 if (gs_type == PIPE_SHADER_GEOMETRY) {
1160 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1161 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1162 } else {
1163 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1164 }
1165
1166 if (es_type == PIPE_SHADER_TESS_EVAL)
1167 si_set_tesseval_regs(sscreen, es_sel, pm4);
1168
1169 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1170 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1171 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1172 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1173 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1174 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1175 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1176 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1177 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1178 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1179 S_028B90_CNT(gs_num_invocations) |
1180 S_028B90_ENABLE(gs_num_invocations > 1) |
1181 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1182 shader->ngg.max_vert_out_per_gs_instance);
1183
1184 shader->ge_cntl =
1185 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1186 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts) |
1187 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1188
1189 if (window_space) {
1190 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1191 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1192 } else {
1193 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1194 S_028818_VTX_W0_FMT(1) |
1195 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1196 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1197 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1198 }
1199
1200 shader->ctx_reg.ngg.vgt_reuse_off =
1201 S_028AB4_REUSE_OFF(sscreen->info.family == CHIP_NAVI10 &&
1202 sscreen->info.chip_external_rev == 0x1 &&
1203 es_type == PIPE_SHADER_TESS_EVAL);
1204 }
1205
1206 static void si_emit_shader_vs(struct si_context *sctx)
1207 {
1208 struct si_shader *shader = sctx->queued.named.vs->shader;
1209 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1210
1211 if (!shader)
1212 return;
1213
1214 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1215 SI_TRACKED_VGT_GS_MODE,
1216 shader->ctx_reg.vs.vgt_gs_mode);
1217 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1218 SI_TRACKED_VGT_PRIMITIVEID_EN,
1219 shader->ctx_reg.vs.vgt_primitiveid_en);
1220
1221 if (sctx->chip_class <= GFX8) {
1222 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1223 SI_TRACKED_VGT_REUSE_OFF,
1224 shader->ctx_reg.vs.vgt_reuse_off);
1225 }
1226
1227 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1228 SI_TRACKED_SPI_VS_OUT_CONFIG,
1229 shader->ctx_reg.vs.spi_vs_out_config);
1230
1231 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1232 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1233 shader->ctx_reg.vs.spi_shader_pos_format);
1234
1235 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1236 SI_TRACKED_PA_CL_VTE_CNTL,
1237 shader->ctx_reg.vs.pa_cl_vte_cntl);
1238
1239 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1240 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1241 SI_TRACKED_VGT_TF_PARAM,
1242 shader->vgt_tf_param);
1243
1244 if (shader->vgt_vertex_reuse_block_cntl)
1245 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1246 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1247 shader->vgt_vertex_reuse_block_cntl);
1248
1249 if (initial_cdw != sctx->gfx_cs->current.cdw)
1250 sctx->context_roll = true;
1251 }
1252
1253 /**
1254 * Compute the state for \p shader, which will run as a vertex shader on the
1255 * hardware.
1256 *
1257 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1258 * is the copy shader.
1259 */
1260 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1261 struct si_shader_selector *gs)
1262 {
1263 const struct tgsi_shader_info *info = &shader->selector->info;
1264 struct si_pm4_state *pm4;
1265 unsigned num_user_sgprs, vgpr_comp_cnt;
1266 uint64_t va;
1267 unsigned nparams, oc_lds_en;
1268 unsigned window_space =
1269 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1270 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1271
1272 pm4 = si_get_shader_pm4_state(shader);
1273 if (!pm4)
1274 return;
1275
1276 pm4->atom.emit = si_emit_shader_vs;
1277
1278 /* We always write VGT_GS_MODE in the VS state, because every switch
1279 * between different shader pipelines involving a different GS or no
1280 * GS at all involves a switch of the VS (different GS use different
1281 * copy shaders). On the other hand, when the API switches from a GS to
1282 * no GS and then back to the same GS used originally, the GS state is
1283 * not sent again.
1284 */
1285 if (!gs) {
1286 unsigned mode = V_028A40_GS_OFF;
1287
1288 /* PrimID needs GS scenario A. */
1289 if (enable_prim_id)
1290 mode = V_028A40_GS_SCENARIO_A;
1291
1292 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1293 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1294 } else {
1295 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1296 sscreen->info.chip_class);
1297 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1298 }
1299
1300 if (sscreen->info.chip_class <= GFX8) {
1301 /* Reuse needs to be set off if we write oViewport. */
1302 shader->ctx_reg.vs.vgt_reuse_off =
1303 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1304 }
1305
1306 va = shader->bo->gpu_address;
1307 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1308
1309 if (gs) {
1310 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1311 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1312 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1313 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1314 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1315 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1316 */
1317 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
1318
1319 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1320 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1321 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1322 } else {
1323 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1324 }
1325 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1326 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1327 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1328 } else
1329 unreachable("invalid shader selector type");
1330
1331 /* VS is required to export at least one param. */
1332 nparams = MAX2(shader->info.nr_param_exports, 1);
1333 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1334
1335 shader->ctx_reg.vs.spi_shader_pos_format =
1336 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1337 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1338 V_02870C_SPI_SHADER_4COMP :
1339 V_02870C_SPI_SHADER_NONE) |
1340 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1341 V_02870C_SPI_SHADER_4COMP :
1342 V_02870C_SPI_SHADER_NONE) |
1343 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1344 V_02870C_SPI_SHADER_4COMP :
1345 V_02870C_SPI_SHADER_NONE);
1346
1347 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1348
1349 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1350 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1351 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
1352 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
1353 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
1354 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1355 S_00B128_DX10_CLAMP(1) |
1356 S_00B128_FLOAT_MODE(shader->config.float_mode));
1357 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
1358 S_00B12C_USER_SGPR(num_user_sgprs) |
1359 S_00B12C_OC_LDS_EN(oc_lds_en) |
1360 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1361 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1362 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1363 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1364 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
1365 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1366
1367 if (window_space)
1368 shader->ctx_reg.vs.pa_cl_vte_cntl =
1369 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1370 else
1371 shader->ctx_reg.vs.pa_cl_vte_cntl =
1372 S_028818_VTX_W0_FMT(1) |
1373 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1374 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1375 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1376
1377 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1378 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1379
1380 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1381 }
1382
1383 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1384 {
1385 struct tgsi_shader_info *info = &ps->selector->info;
1386 unsigned num_colors = !!(info->colors_read & 0x0f) +
1387 !!(info->colors_read & 0xf0);
1388 unsigned num_interp = ps->selector->info.num_inputs +
1389 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1390
1391 assert(num_interp <= 32);
1392 return MIN2(num_interp, 32);
1393 }
1394
1395 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1396 {
1397 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1398 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1399
1400 /* If the i-th target format is set, all previous target formats must
1401 * be non-zero to avoid hangs.
1402 */
1403 for (i = 0; i < num_targets; i++)
1404 if (!(value & (0xf << (i * 4))))
1405 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1406
1407 return value;
1408 }
1409
1410 static void si_emit_shader_ps(struct si_context *sctx)
1411 {
1412 struct si_shader *shader = sctx->queued.named.ps->shader;
1413 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1414
1415 if (!shader)
1416 return;
1417
1418 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1419 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1420 SI_TRACKED_SPI_PS_INPUT_ENA,
1421 shader->ctx_reg.ps.spi_ps_input_ena,
1422 shader->ctx_reg.ps.spi_ps_input_addr);
1423
1424 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1425 SI_TRACKED_SPI_BARYC_CNTL,
1426 shader->ctx_reg.ps.spi_baryc_cntl);
1427 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1428 SI_TRACKED_SPI_PS_IN_CONTROL,
1429 shader->ctx_reg.ps.spi_ps_in_control);
1430
1431 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1432 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1433 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1434 shader->ctx_reg.ps.spi_shader_z_format,
1435 shader->ctx_reg.ps.spi_shader_col_format);
1436
1437 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1438 SI_TRACKED_CB_SHADER_MASK,
1439 shader->ctx_reg.ps.cb_shader_mask);
1440
1441 if (initial_cdw != sctx->gfx_cs->current.cdw)
1442 sctx->context_roll = true;
1443 }
1444
1445 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1446 {
1447 struct tgsi_shader_info *info = &shader->selector->info;
1448 struct si_pm4_state *pm4;
1449 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1450 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1451 uint64_t va;
1452 unsigned input_ena = shader->config.spi_ps_input_ena;
1453
1454 /* we need to enable at least one of them, otherwise we hang the GPU */
1455 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1456 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1457 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1458 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1459 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1460 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1461 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1462 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1463 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1464 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1465 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1466 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1467 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1468 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1469
1470 /* Validate interpolation optimization flags (read as implications). */
1471 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1472 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1473 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1474 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1475 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1476 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1477 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1478 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1479 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1480 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1481 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1482 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1483 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1484 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1485 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1486 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1487 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1488 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1489
1490 /* Validate cases when the optimizations are off (read as implications). */
1491 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1492 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1493 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1494 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1495 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1496 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1497
1498 pm4 = si_get_shader_pm4_state(shader);
1499 if (!pm4)
1500 return;
1501
1502 pm4->atom.emit = si_emit_shader_ps;
1503
1504 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1505 * Possible vaules:
1506 * 0 -> Position = pixel center
1507 * 1 -> Position = pixel centroid
1508 * 2 -> Position = at sample position
1509 *
1510 * From GLSL 4.5 specification, section 7.1:
1511 * "The variable gl_FragCoord is available as an input variable from
1512 * within fragment shaders and it holds the window relative coordinates
1513 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1514 * value can be for any location within the pixel, or one of the
1515 * fragment samples. The use of centroid does not further restrict
1516 * this value to be inside the current primitive."
1517 *
1518 * Meaning that centroid has no effect and we can return anything within
1519 * the pixel. Thus, return the value at sample position, because that's
1520 * the most accurate one shaders can get.
1521 */
1522 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1523
1524 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1525 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1526 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1527
1528 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1529 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1530
1531 /* Ensure that some export memory is always allocated, for two reasons:
1532 *
1533 * 1) Correctness: The hardware ignores the EXEC mask if no export
1534 * memory is allocated, so KILL and alpha test do not work correctly
1535 * without this.
1536 * 2) Performance: Every shader needs at least a NULL export, even when
1537 * it writes no color/depth output. The NULL export instruction
1538 * stalls without this setting.
1539 *
1540 * Don't add this to CB_SHADER_MASK.
1541 */
1542 if (!spi_shader_col_format &&
1543 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1544 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1545
1546 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1547 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1548
1549 /* Set interpolation controls. */
1550 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1551
1552 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1553 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1554 shader->ctx_reg.ps.spi_shader_z_format =
1555 ac_get_spi_shader_z_format(info->writes_z,
1556 info->writes_stencil,
1557 info->writes_samplemask);
1558 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1559 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1560
1561 va = shader->bo->gpu_address;
1562 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1563 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1564 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1565
1566 uint32_t rsrc1 =
1567 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1568 S_00B028_DX10_CLAMP(1) |
1569 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1570 S_00B028_FLOAT_MODE(shader->config.float_mode);
1571
1572 if (sscreen->info.chip_class < GFX10) {
1573 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1574 }
1575
1576 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1577 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1578 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1579 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1580 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1581 }
1582
1583 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1584 struct si_shader *shader)
1585 {
1586 switch (shader->selector->type) {
1587 case PIPE_SHADER_VERTEX:
1588 if (shader->key.as_ls)
1589 si_shader_ls(sscreen, shader);
1590 else if (shader->key.as_es)
1591 si_shader_es(sscreen, shader);
1592 else if (shader->key.as_ngg)
1593 gfx10_shader_ngg(sscreen, shader);
1594 else
1595 si_shader_vs(sscreen, shader, NULL);
1596 break;
1597 case PIPE_SHADER_TESS_CTRL:
1598 si_shader_hs(sscreen, shader);
1599 break;
1600 case PIPE_SHADER_TESS_EVAL:
1601 if (shader->key.as_es)
1602 si_shader_es(sscreen, shader);
1603 else if (shader->key.as_ngg)
1604 gfx10_shader_ngg(sscreen, shader);
1605 else
1606 si_shader_vs(sscreen, shader, NULL);
1607 break;
1608 case PIPE_SHADER_GEOMETRY:
1609 if (shader->key.as_ngg)
1610 gfx10_shader_ngg(sscreen, shader);
1611 else
1612 si_shader_gs(sscreen, shader);
1613 break;
1614 case PIPE_SHADER_FRAGMENT:
1615 si_shader_ps(sscreen, shader);
1616 break;
1617 default:
1618 assert(0);
1619 }
1620 }
1621
1622 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1623 {
1624 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1625 if (sctx->queued.named.dsa)
1626 return sctx->queued.named.dsa->alpha_func;
1627
1628 return PIPE_FUNC_ALWAYS;
1629 }
1630
1631 void si_shader_selector_key_vs(struct si_context *sctx,
1632 struct si_shader_selector *vs,
1633 struct si_shader_key *key,
1634 struct si_vs_prolog_bits *prolog_key)
1635 {
1636 if (!sctx->vertex_elements ||
1637 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS])
1638 return;
1639
1640 struct si_vertex_elements *elts = sctx->vertex_elements;
1641
1642 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1643 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1644 prolog_key->unpack_instance_id_from_vertex_id =
1645 sctx->prim_discard_cs_instancing;
1646
1647 /* Prefer a monolithic shader to allow scheduling divisions around
1648 * VBO loads. */
1649 if (prolog_key->instance_divisor_is_fetched)
1650 key->opt.prefer_mono = 1;
1651
1652 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1653 unsigned count_mask = (1 << count) - 1;
1654 unsigned fix = elts->fix_fetch_always & count_mask;
1655 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1656
1657 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1658 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1659 while (mask) {
1660 unsigned i = u_bit_scan(&mask);
1661 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1662 unsigned vbidx = elts->vertex_buffer_index[i];
1663 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1664 unsigned align_mask = (1 << log_hw_load_size) - 1;
1665 if (vb->buffer_offset & align_mask ||
1666 vb->stride & align_mask) {
1667 fix |= 1 << i;
1668 opencode |= 1 << i;
1669 }
1670 }
1671 }
1672
1673 while (fix) {
1674 unsigned i = u_bit_scan(&fix);
1675 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1676 }
1677 key->mono.vs_fetch_opencode = opencode;
1678 }
1679
1680 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1681 struct si_shader_selector *vs,
1682 struct si_shader_key *key)
1683 {
1684 struct si_shader_selector *ps = sctx->ps_shader.cso;
1685
1686 key->opt.clip_disable =
1687 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1688 (vs->info.clipdist_writemask ||
1689 vs->info.writes_clipvertex) &&
1690 !vs->info.culldist_writemask;
1691
1692 /* Find out if PS is disabled. */
1693 bool ps_disabled = true;
1694 if (ps) {
1695 const struct si_state_blend *blend = sctx->queued.named.blend;
1696 bool alpha_to_coverage = blend && blend->alpha_to_coverage;
1697 bool ps_modifies_zs = ps->info.uses_kill ||
1698 ps->info.writes_z ||
1699 ps->info.writes_stencil ||
1700 ps->info.writes_samplemask ||
1701 alpha_to_coverage ||
1702 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1703 unsigned ps_colormask = si_get_total_colormask(sctx);
1704
1705 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1706 (!ps_colormask &&
1707 !ps_modifies_zs &&
1708 !ps->info.writes_memory);
1709 }
1710
1711 /* Find out which VS outputs aren't used by the PS. */
1712 uint64_t outputs_written = vs->outputs_written_before_ps;
1713 uint64_t inputs_read = 0;
1714
1715 /* Ignore outputs that are not passed from VS to PS. */
1716 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1717 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1718 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1719
1720 if (!ps_disabled) {
1721 inputs_read = ps->inputs_read;
1722 }
1723
1724 uint64_t linked = outputs_written & inputs_read;
1725
1726 key->opt.kill_outputs = ~linked & outputs_written;
1727 }
1728
1729 /* Compute the key for the hw shader variant */
1730 static inline void si_shader_selector_key(struct pipe_context *ctx,
1731 struct si_shader_selector *sel,
1732 union si_vgt_stages_key stages_key,
1733 struct si_shader_key *key)
1734 {
1735 struct si_context *sctx = (struct si_context *)ctx;
1736
1737 memset(key, 0, sizeof(*key));
1738
1739 switch (sel->type) {
1740 case PIPE_SHADER_VERTEX:
1741 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1742
1743 if (sctx->tes_shader.cso)
1744 key->as_ls = 1;
1745 else if (sctx->gs_shader.cso)
1746 key->as_es = 1;
1747 else {
1748 key->as_ngg = stages_key.u.ngg;
1749 si_shader_selector_key_hw_vs(sctx, sel, key);
1750
1751 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1752 key->mono.u.vs_export_prim_id = 1;
1753 }
1754 break;
1755 case PIPE_SHADER_TESS_CTRL:
1756 if (sctx->chip_class >= GFX9) {
1757 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1758 key, &key->part.tcs.ls_prolog);
1759 key->part.tcs.ls = sctx->vs_shader.cso;
1760
1761 /* When the LS VGPR fix is needed, monolithic shaders
1762 * can:
1763 * - avoid initializing EXEC in both the LS prolog
1764 * and the LS main part when !vs_needs_prolog
1765 * - remove the fixup for unused input VGPRs
1766 */
1767 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1768
1769 /* The LS output / HS input layout can be communicated
1770 * directly instead of via user SGPRs for merged LS-HS.
1771 * The LS VGPR fix prefers this too.
1772 */
1773 key->opt.prefer_mono = 1;
1774 }
1775
1776 key->part.tcs.epilog.prim_mode =
1777 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1778 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1779 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1780 key->part.tcs.epilog.tes_reads_tess_factors =
1781 sctx->tes_shader.cso->info.reads_tess_factors;
1782
1783 if (sel == sctx->fixed_func_tcs_shader.cso)
1784 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1785 break;
1786 case PIPE_SHADER_TESS_EVAL:
1787 if (sctx->gs_shader.cso)
1788 key->as_es = 1;
1789 else {
1790 key->as_ngg = stages_key.u.ngg;
1791 si_shader_selector_key_hw_vs(sctx, sel, key);
1792
1793 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1794 key->mono.u.vs_export_prim_id = 1;
1795 }
1796 break;
1797 case PIPE_SHADER_GEOMETRY:
1798 if (sctx->chip_class >= GFX9) {
1799 if (sctx->tes_shader.cso) {
1800 key->part.gs.es = sctx->tes_shader.cso;
1801 } else {
1802 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1803 key, &key->part.gs.vs_prolog);
1804 key->part.gs.es = sctx->vs_shader.cso;
1805 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1806 }
1807
1808 key->as_ngg = stages_key.u.ngg;
1809
1810 /* Merged ES-GS can have unbalanced wave usage.
1811 *
1812 * ES threads are per-vertex, while GS threads are
1813 * per-primitive. So without any amplification, there
1814 * are fewer GS threads than ES threads, which can result
1815 * in empty (no-op) GS waves. With too much amplification,
1816 * there are more GS threads than ES threads, which
1817 * can result in empty (no-op) ES waves.
1818 *
1819 * Non-monolithic shaders are implemented by setting EXEC
1820 * at the beginning of shader parts, and don't jump to
1821 * the end if EXEC is 0.
1822 *
1823 * Monolithic shaders use conditional blocks, so they can
1824 * jump and skip empty waves of ES or GS. So set this to
1825 * always use optimized variants, which are monolithic.
1826 */
1827 key->opt.prefer_mono = 1;
1828 }
1829 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1830 break;
1831 case PIPE_SHADER_FRAGMENT: {
1832 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1833 struct si_state_blend *blend = sctx->queued.named.blend;
1834
1835 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1836 sel->info.colors_written == 0x1)
1837 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1838
1839 if (blend) {
1840 /* Select the shader color format based on whether
1841 * blending or alpha are needed.
1842 */
1843 key->part.ps.epilog.spi_shader_col_format =
1844 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1845 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1846 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1847 sctx->framebuffer.spi_shader_col_format_blend) |
1848 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1849 sctx->framebuffer.spi_shader_col_format_alpha) |
1850 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1851 sctx->framebuffer.spi_shader_col_format);
1852 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1853
1854 /* The output for dual source blending should have
1855 * the same format as the first output.
1856 */
1857 if (blend->dual_src_blend)
1858 key->part.ps.epilog.spi_shader_col_format |=
1859 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1860 } else
1861 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1862
1863 /* If alpha-to-coverage is enabled, we have to export alpha
1864 * even if there is no color buffer.
1865 */
1866 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1867 blend && blend->alpha_to_coverage)
1868 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1869
1870 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1871 * to the range supported by the type if a channel has less
1872 * than 16 bits and the export format is 16_ABGR.
1873 */
1874 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1875 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1876 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1877 }
1878
1879 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1880 if (!key->part.ps.epilog.last_cbuf) {
1881 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1882 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1883 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1884 }
1885
1886 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1887 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1888
1889 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1890 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1891
1892 if (sctx->queued.named.blend) {
1893 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1894 rs->multisample_enable;
1895 }
1896
1897 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1898 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1899 (is_line && rs->line_smooth)) &&
1900 sctx->framebuffer.nr_samples <= 1;
1901 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1902
1903 if (sctx->ps_iter_samples > 1 &&
1904 sel->info.reads_samplemask) {
1905 key->part.ps.prolog.samplemask_log_ps_iter =
1906 util_logbase2(sctx->ps_iter_samples);
1907 }
1908
1909 if (rs->force_persample_interp &&
1910 rs->multisample_enable &&
1911 sctx->framebuffer.nr_samples > 1 &&
1912 sctx->ps_iter_samples > 1) {
1913 key->part.ps.prolog.force_persp_sample_interp =
1914 sel->info.uses_persp_center ||
1915 sel->info.uses_persp_centroid;
1916
1917 key->part.ps.prolog.force_linear_sample_interp =
1918 sel->info.uses_linear_center ||
1919 sel->info.uses_linear_centroid;
1920 } else if (rs->multisample_enable &&
1921 sctx->framebuffer.nr_samples > 1) {
1922 key->part.ps.prolog.bc_optimize_for_persp =
1923 sel->info.uses_persp_center &&
1924 sel->info.uses_persp_centroid;
1925 key->part.ps.prolog.bc_optimize_for_linear =
1926 sel->info.uses_linear_center &&
1927 sel->info.uses_linear_centroid;
1928 } else {
1929 /* Make sure SPI doesn't compute more than 1 pair
1930 * of (i,j), which is the optimization here. */
1931 key->part.ps.prolog.force_persp_center_interp =
1932 sel->info.uses_persp_center +
1933 sel->info.uses_persp_centroid +
1934 sel->info.uses_persp_sample > 1;
1935
1936 key->part.ps.prolog.force_linear_center_interp =
1937 sel->info.uses_linear_center +
1938 sel->info.uses_linear_centroid +
1939 sel->info.uses_linear_sample > 1;
1940
1941 if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
1942 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1943 }
1944
1945 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1946
1947 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1948 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
1949 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
1950 struct pipe_resource *tex = cb0->texture;
1951
1952 /* 1D textures are allocated and used as 2D on GFX9. */
1953 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
1954 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
1955 (tex->target == PIPE_TEXTURE_1D ||
1956 tex->target == PIPE_TEXTURE_1D_ARRAY);
1957 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
1958 tex->target == PIPE_TEXTURE_2D_ARRAY ||
1959 tex->target == PIPE_TEXTURE_CUBE ||
1960 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
1961 tex->target == PIPE_TEXTURE_3D;
1962 }
1963 break;
1964 }
1965 default:
1966 assert(0);
1967 }
1968
1969 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
1970 memset(&key->opt, 0, sizeof(key->opt));
1971 }
1972
1973 static void si_build_shader_variant(struct si_shader *shader,
1974 int thread_index,
1975 bool low_priority)
1976 {
1977 struct si_shader_selector *sel = shader->selector;
1978 struct si_screen *sscreen = sel->screen;
1979 struct ac_llvm_compiler *compiler;
1980 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1981
1982 if (thread_index >= 0) {
1983 if (low_priority) {
1984 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
1985 compiler = &sscreen->compiler_lowp[thread_index];
1986 } else {
1987 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
1988 compiler = &sscreen->compiler[thread_index];
1989 }
1990 if (!debug->async)
1991 debug = NULL;
1992 } else {
1993 assert(!low_priority);
1994 compiler = shader->compiler_ctx_state.compiler;
1995 }
1996
1997 if (unlikely(!si_shader_create(sscreen, compiler, shader, debug))) {
1998 PRINT_ERR("Failed to build shader variant (type=%u)\n",
1999 sel->type);
2000 shader->compilation_failed = true;
2001 return;
2002 }
2003
2004 if (shader->compiler_ctx_state.is_debug_context) {
2005 FILE *f = open_memstream(&shader->shader_log,
2006 &shader->shader_log_size);
2007 if (f) {
2008 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
2009 fclose(f);
2010 }
2011 }
2012
2013 si_shader_init_pm4_state(sscreen, shader);
2014 }
2015
2016 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2017 {
2018 struct si_shader *shader = (struct si_shader *)job;
2019
2020 assert(thread_index >= 0);
2021
2022 si_build_shader_variant(shader, thread_index, true);
2023 }
2024
2025 static const struct si_shader_key zeroed;
2026
2027 static bool si_check_missing_main_part(struct si_screen *sscreen,
2028 struct si_shader_selector *sel,
2029 struct si_compiler_ctx_state *compiler_state,
2030 struct si_shader_key *key)
2031 {
2032 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2033
2034 if (!*mainp) {
2035 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2036
2037 if (!main_part)
2038 return false;
2039
2040 /* We can leave the fence as permanently signaled because the
2041 * main part becomes visible globally only after it has been
2042 * compiled. */
2043 util_queue_fence_init(&main_part->ready);
2044
2045 main_part->selector = sel;
2046 main_part->key.as_es = key->as_es;
2047 main_part->key.as_ls = key->as_ls;
2048 main_part->key.as_ngg = key->as_ngg;
2049 main_part->is_monolithic = false;
2050
2051 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
2052 main_part, &compiler_state->debug) != 0) {
2053 FREE(main_part);
2054 return false;
2055 }
2056 *mainp = main_part;
2057 }
2058 return true;
2059 }
2060
2061 /**
2062 * Select a shader variant according to the shader key.
2063 *
2064 * \param optimized_or_none If the key describes an optimized shader variant and
2065 * the compilation isn't finished, don't select any
2066 * shader and return an error.
2067 */
2068 int si_shader_select_with_key(struct si_screen *sscreen,
2069 struct si_shader_ctx_state *state,
2070 struct si_compiler_ctx_state *compiler_state,
2071 struct si_shader_key *key,
2072 int thread_index,
2073 bool optimized_or_none)
2074 {
2075 struct si_shader_selector *sel = state->cso;
2076 struct si_shader_selector *previous_stage_sel = NULL;
2077 struct si_shader *current = state->current;
2078 struct si_shader *iter, *shader = NULL;
2079
2080 again:
2081 /* Check if we don't need to change anything.
2082 * This path is also used for most shaders that don't need multiple
2083 * variants, it will cost just a computation of the key and this
2084 * test. */
2085 if (likely(current &&
2086 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2087 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2088 if (current->is_optimized) {
2089 if (optimized_or_none)
2090 return -1;
2091
2092 memset(&key->opt, 0, sizeof(key->opt));
2093 goto current_not_ready;
2094 }
2095
2096 util_queue_fence_wait(&current->ready);
2097 }
2098
2099 return current->compilation_failed ? -1 : 0;
2100 }
2101 current_not_ready:
2102
2103 /* This must be done before the mutex is locked, because async GS
2104 * compilation calls this function too, and therefore must enter
2105 * the mutex first.
2106 *
2107 * Only wait if we are in a draw call. Don't wait if we are
2108 * in a compiler thread.
2109 */
2110 if (thread_index < 0)
2111 util_queue_fence_wait(&sel->ready);
2112
2113 mtx_lock(&sel->mutex);
2114
2115 /* Find the shader variant. */
2116 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2117 /* Don't check the "current" shader. We checked it above. */
2118 if (current != iter &&
2119 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2120 mtx_unlock(&sel->mutex);
2121
2122 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2123 /* If it's an optimized shader and its compilation has
2124 * been started but isn't done, use the unoptimized
2125 * shader so as not to cause a stall due to compilation.
2126 */
2127 if (iter->is_optimized) {
2128 if (optimized_or_none)
2129 return -1;
2130 memset(&key->opt, 0, sizeof(key->opt));
2131 goto again;
2132 }
2133
2134 util_queue_fence_wait(&iter->ready);
2135 }
2136
2137 if (iter->compilation_failed) {
2138 return -1; /* skip the draw call */
2139 }
2140
2141 state->current = iter;
2142 return 0;
2143 }
2144 }
2145
2146 /* Build a new shader. */
2147 shader = CALLOC_STRUCT(si_shader);
2148 if (!shader) {
2149 mtx_unlock(&sel->mutex);
2150 return -ENOMEM;
2151 }
2152
2153 util_queue_fence_init(&shader->ready);
2154
2155 shader->selector = sel;
2156 shader->key = *key;
2157 shader->compiler_ctx_state = *compiler_state;
2158
2159 /* If this is a merged shader, get the first shader's selector. */
2160 if (sscreen->info.chip_class >= GFX9) {
2161 if (sel->type == PIPE_SHADER_TESS_CTRL)
2162 previous_stage_sel = key->part.tcs.ls;
2163 else if (sel->type == PIPE_SHADER_GEOMETRY)
2164 previous_stage_sel = key->part.gs.es;
2165
2166 /* We need to wait for the previous shader. */
2167 if (previous_stage_sel && thread_index < 0)
2168 util_queue_fence_wait(&previous_stage_sel->ready);
2169 }
2170
2171 bool is_pure_monolithic =
2172 sscreen->use_monolithic_shaders ||
2173 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2174
2175 /* Compile the main shader part if it doesn't exist. This can happen
2176 * if the initial guess was wrong.
2177 *
2178 * The prim discard CS doesn't need the main shader part.
2179 */
2180 if (!is_pure_monolithic &&
2181 !key->opt.vs_as_prim_discard_cs) {
2182 bool ok = true;
2183
2184 /* Make sure the main shader part is present. This is needed
2185 * for shaders that can be compiled as VS, LS, or ES, and only
2186 * one of them is compiled at creation.
2187 *
2188 * It is also needed for GS, which can be compiled as non-NGG
2189 * and NGG.
2190 *
2191 * For merged shaders, check that the starting shader's main
2192 * part is present.
2193 */
2194 if (previous_stage_sel) {
2195 struct si_shader_key shader1_key = zeroed;
2196
2197 if (sel->type == PIPE_SHADER_TESS_CTRL)
2198 shader1_key.as_ls = 1;
2199 else if (sel->type == PIPE_SHADER_GEOMETRY)
2200 shader1_key.as_es = 1;
2201 else
2202 assert(0);
2203
2204 mtx_lock(&previous_stage_sel->mutex);
2205 ok = si_check_missing_main_part(sscreen,
2206 previous_stage_sel,
2207 compiler_state, &shader1_key);
2208 mtx_unlock(&previous_stage_sel->mutex);
2209 }
2210
2211 if (ok) {
2212 ok = si_check_missing_main_part(sscreen, sel,
2213 compiler_state, key);
2214 }
2215
2216 if (!ok) {
2217 FREE(shader);
2218 mtx_unlock(&sel->mutex);
2219 return -ENOMEM; /* skip the draw call */
2220 }
2221 }
2222
2223 /* Keep the reference to the 1st shader of merged shaders, so that
2224 * Gallium can't destroy it before we destroy the 2nd shader.
2225 *
2226 * Set sctx = NULL, because it's unused if we're not releasing
2227 * the shader, and we don't have any sctx here.
2228 */
2229 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2230 previous_stage_sel);
2231
2232 /* Monolithic-only shaders don't make a distinction between optimized
2233 * and unoptimized. */
2234 shader->is_monolithic =
2235 is_pure_monolithic ||
2236 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2237
2238 /* The prim discard CS is always optimized. */
2239 shader->is_optimized =
2240 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2241 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2242
2243 /* If it's an optimized shader, compile it asynchronously. */
2244 if (shader->is_optimized && thread_index < 0) {
2245 /* Compile it asynchronously. */
2246 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2247 shader, &shader->ready,
2248 si_build_shader_variant_low_priority, NULL);
2249
2250 /* Add only after the ready fence was reset, to guard against a
2251 * race with si_bind_XX_shader. */
2252 if (!sel->last_variant) {
2253 sel->first_variant = shader;
2254 sel->last_variant = shader;
2255 } else {
2256 sel->last_variant->next_variant = shader;
2257 sel->last_variant = shader;
2258 }
2259
2260 /* Use the default (unoptimized) shader for now. */
2261 memset(&key->opt, 0, sizeof(key->opt));
2262 mtx_unlock(&sel->mutex);
2263
2264 if (sscreen->options.sync_compile)
2265 util_queue_fence_wait(&shader->ready);
2266
2267 if (optimized_or_none)
2268 return -1;
2269 goto again;
2270 }
2271
2272 /* Reset the fence before adding to the variant list. */
2273 util_queue_fence_reset(&shader->ready);
2274
2275 if (!sel->last_variant) {
2276 sel->first_variant = shader;
2277 sel->last_variant = shader;
2278 } else {
2279 sel->last_variant->next_variant = shader;
2280 sel->last_variant = shader;
2281 }
2282
2283 mtx_unlock(&sel->mutex);
2284
2285 assert(!shader->is_optimized);
2286 si_build_shader_variant(shader, thread_index, false);
2287
2288 util_queue_fence_signal(&shader->ready);
2289
2290 if (!shader->compilation_failed)
2291 state->current = shader;
2292
2293 return shader->compilation_failed ? -1 : 0;
2294 }
2295
2296 static int si_shader_select(struct pipe_context *ctx,
2297 struct si_shader_ctx_state *state,
2298 union si_vgt_stages_key stages_key,
2299 struct si_compiler_ctx_state *compiler_state)
2300 {
2301 struct si_context *sctx = (struct si_context *)ctx;
2302 struct si_shader_key key;
2303
2304 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2305 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2306 &key, -1, false);
2307 }
2308
2309 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
2310 bool streamout,
2311 struct si_shader_key *key)
2312 {
2313 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2314
2315 switch (info->processor) {
2316 case PIPE_SHADER_VERTEX:
2317 switch (next_shader) {
2318 case PIPE_SHADER_GEOMETRY:
2319 key->as_es = 1;
2320 break;
2321 case PIPE_SHADER_TESS_CTRL:
2322 case PIPE_SHADER_TESS_EVAL:
2323 key->as_ls = 1;
2324 break;
2325 default:
2326 /* If POSITION isn't written, it can only be a HW VS
2327 * if streamout is used. If streamout isn't used,
2328 * assume that it's a HW LS. (the next shader is TCS)
2329 * This heuristic is needed for separate shader objects.
2330 */
2331 if (!info->writes_position && !streamout)
2332 key->as_ls = 1;
2333 }
2334 break;
2335
2336 case PIPE_SHADER_TESS_EVAL:
2337 if (next_shader == PIPE_SHADER_GEOMETRY ||
2338 !info->writes_position)
2339 key->as_es = 1;
2340 break;
2341 }
2342 }
2343
2344 /**
2345 * Compile the main shader part or the monolithic shader as part of
2346 * si_shader_selector initialization. Since it can be done asynchronously,
2347 * there is no way to report compile failures to applications.
2348 */
2349 static void si_init_shader_selector_async(void *job, int thread_index)
2350 {
2351 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2352 struct si_screen *sscreen = sel->screen;
2353 struct ac_llvm_compiler *compiler;
2354 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2355
2356 assert(!debug->debug_message || debug->async);
2357 assert(thread_index >= 0);
2358 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2359 compiler = &sscreen->compiler[thread_index];
2360
2361 if (sel->nir)
2362 si_lower_nir(sel);
2363
2364 /* Compile the main shader part for use with a prolog and/or epilog.
2365 * If this fails, the driver will try to compile a monolithic shader
2366 * on demand.
2367 */
2368 if (!sscreen->use_monolithic_shaders) {
2369 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2370 void *ir_binary = NULL;
2371
2372 if (!shader) {
2373 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2374 return;
2375 }
2376
2377 /* We can leave the fence signaled because use of the default
2378 * main part is guarded by the selector's ready fence. */
2379 util_queue_fence_init(&shader->ready);
2380
2381 shader->selector = sel;
2382 shader->is_monolithic = false;
2383 si_parse_next_shader_property(&sel->info,
2384 sel->so.num_outputs != 0,
2385 &shader->key);
2386 if (sscreen->info.chip_class >= GFX10 &&
2387 !sscreen->options.disable_ngg &&
2388 (((sel->type == PIPE_SHADER_VERTEX ||
2389 sel->type == PIPE_SHADER_TESS_EVAL) &&
2390 !shader->key.as_ls && !shader->key.as_es) ||
2391 sel->type == PIPE_SHADER_GEOMETRY))
2392 shader->key.as_ngg = 1;
2393
2394 if (sel->tokens || sel->nir)
2395 ir_binary = si_get_ir_binary(sel);
2396
2397 /* Try to load the shader from the shader cache. */
2398 mtx_lock(&sscreen->shader_cache_mutex);
2399
2400 if (ir_binary &&
2401 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
2402 mtx_unlock(&sscreen->shader_cache_mutex);
2403 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2404 } else {
2405 mtx_unlock(&sscreen->shader_cache_mutex);
2406
2407 /* Compile the shader if it hasn't been loaded from the cache. */
2408 if (si_compile_tgsi_shader(sscreen, compiler, shader,
2409 debug) != 0) {
2410 FREE(shader);
2411 FREE(ir_binary);
2412 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2413 return;
2414 }
2415
2416 if (ir_binary) {
2417 mtx_lock(&sscreen->shader_cache_mutex);
2418 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
2419 FREE(ir_binary);
2420 mtx_unlock(&sscreen->shader_cache_mutex);
2421 }
2422 }
2423
2424 *si_get_main_shader_part(sel, &shader->key) = shader;
2425
2426 /* Unset "outputs_written" flags for outputs converted to
2427 * DEFAULT_VAL, so that later inter-shader optimizations don't
2428 * try to eliminate outputs that don't exist in the final
2429 * shader.
2430 *
2431 * This is only done if non-monolithic shaders are enabled.
2432 */
2433 if ((sel->type == PIPE_SHADER_VERTEX ||
2434 sel->type == PIPE_SHADER_TESS_EVAL) &&
2435 !shader->key.as_ls &&
2436 !shader->key.as_es) {
2437 unsigned i;
2438
2439 for (i = 0; i < sel->info.num_outputs; i++) {
2440 unsigned offset = shader->info.vs_output_param_offset[i];
2441
2442 if (offset <= AC_EXP_PARAM_OFFSET_31)
2443 continue;
2444
2445 unsigned name = sel->info.output_semantic_name[i];
2446 unsigned index = sel->info.output_semantic_index[i];
2447 unsigned id;
2448
2449 switch (name) {
2450 case TGSI_SEMANTIC_GENERIC:
2451 /* don't process indices the function can't handle */
2452 if (index >= SI_MAX_IO_GENERIC)
2453 break;
2454 /* fall through */
2455 default:
2456 id = si_shader_io_get_unique_index(name, index, true);
2457 sel->outputs_written_before_ps &= ~(1ull << id);
2458 break;
2459 case TGSI_SEMANTIC_POSITION: /* ignore these */
2460 case TGSI_SEMANTIC_PSIZE:
2461 case TGSI_SEMANTIC_CLIPVERTEX:
2462 case TGSI_SEMANTIC_EDGEFLAG:
2463 break;
2464 }
2465 }
2466 }
2467 }
2468
2469 /* The GS copy shader is always pre-compiled.
2470 *
2471 * TODO-GFX10: We could compile the GS copy shader on demand, since it
2472 * is only used in the (rare) non-NGG case.
2473 */
2474 if (sel->type == PIPE_SHADER_GEOMETRY) {
2475 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2476 if (!sel->gs_copy_shader) {
2477 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2478 return;
2479 }
2480
2481 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2482 }
2483 }
2484
2485 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2486 struct util_queue_fence *ready_fence,
2487 struct si_compiler_ctx_state *compiler_ctx_state,
2488 void *job, util_queue_execute_func execute)
2489 {
2490 util_queue_fence_init(ready_fence);
2491
2492 struct util_async_debug_callback async_debug;
2493 bool debug =
2494 (sctx->debug.debug_message && !sctx->debug.async) ||
2495 sctx->is_debug ||
2496 si_can_dump_shader(sctx->screen, processor);
2497
2498 if (debug) {
2499 u_async_debug_init(&async_debug);
2500 compiler_ctx_state->debug = async_debug.base;
2501 }
2502
2503 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2504 ready_fence, execute, NULL);
2505
2506 if (debug) {
2507 util_queue_fence_wait(ready_fence);
2508 u_async_debug_drain(&async_debug, &sctx->debug);
2509 u_async_debug_cleanup(&async_debug);
2510 }
2511
2512 if (sctx->screen->options.sync_compile)
2513 util_queue_fence_wait(ready_fence);
2514 }
2515
2516 /* Return descriptor slot usage masks from the given shader info. */
2517 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2518 uint32_t *const_and_shader_buffers,
2519 uint64_t *samplers_and_images)
2520 {
2521 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2522
2523 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2524 num_constbufs = util_last_bit(info->const_buffers_declared);
2525 /* two 8-byte images share one 16-byte slot */
2526 num_images = align(util_last_bit(info->images_declared), 2);
2527 num_samplers = util_last_bit(info->samplers_declared);
2528
2529 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2530 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2531 *const_and_shader_buffers =
2532 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2533
2534 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2535 start = si_get_image_slot(num_images - 1) / 2;
2536 *samplers_and_images =
2537 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2538 }
2539
2540 static void *si_create_shader_selector(struct pipe_context *ctx,
2541 const struct pipe_shader_state *state)
2542 {
2543 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2544 struct si_context *sctx = (struct si_context*)ctx;
2545 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2546 int i;
2547
2548 if (!sel)
2549 return NULL;
2550
2551 pipe_reference_init(&sel->reference, 1);
2552 sel->screen = sscreen;
2553 sel->compiler_ctx_state.debug = sctx->debug;
2554 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2555
2556 sel->so = state->stream_output;
2557
2558 if (state->type == PIPE_SHADER_IR_TGSI) {
2559 sel->tokens = tgsi_dup_tokens(state->tokens);
2560 if (!sel->tokens) {
2561 FREE(sel);
2562 return NULL;
2563 }
2564
2565 tgsi_scan_shader(state->tokens, &sel->info);
2566 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2567 } else {
2568 assert(state->type == PIPE_SHADER_IR_NIR);
2569
2570 sel->nir = state->ir.nir;
2571
2572 si_nir_opts(sel->nir);
2573 si_nir_scan_shader(sel->nir, &sel->info);
2574 si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
2575 }
2576
2577 sel->type = sel->info.processor;
2578 p_atomic_inc(&sscreen->num_shaders_created);
2579 si_get_active_slot_masks(&sel->info,
2580 &sel->active_const_and_shader_buffers,
2581 &sel->active_samplers_and_images);
2582
2583 /* Record which streamout buffers are enabled. */
2584 for (i = 0; i < sel->so.num_outputs; i++) {
2585 sel->enabled_streamout_buffer_mask |=
2586 (1 << sel->so.output[i].output_buffer) <<
2587 (sel->so.output[i].stream * 4);
2588 }
2589
2590 /* The prolog is a no-op if there are no inputs. */
2591 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2592 sel->info.num_inputs &&
2593 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2594
2595 sel->force_correct_derivs_after_kill =
2596 sel->type == PIPE_SHADER_FRAGMENT &&
2597 sel->info.uses_derivatives &&
2598 sel->info.uses_kill &&
2599 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2600
2601 sel->prim_discard_cs_allowed =
2602 sel->type == PIPE_SHADER_VERTEX &&
2603 !sel->info.uses_bindless_images &&
2604 !sel->info.uses_bindless_samplers &&
2605 !sel->info.writes_memory &&
2606 !sel->info.writes_viewport_index &&
2607 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2608 !sel->so.num_outputs;
2609
2610 /* Set which opcode uses which (i,j) pair. */
2611 if (sel->info.uses_persp_opcode_interp_centroid)
2612 sel->info.uses_persp_centroid = true;
2613
2614 if (sel->info.uses_linear_opcode_interp_centroid)
2615 sel->info.uses_linear_centroid = true;
2616
2617 if (sel->info.uses_persp_opcode_interp_offset ||
2618 sel->info.uses_persp_opcode_interp_sample)
2619 sel->info.uses_persp_center = true;
2620
2621 if (sel->info.uses_linear_opcode_interp_offset ||
2622 sel->info.uses_linear_opcode_interp_sample)
2623 sel->info.uses_linear_center = true;
2624
2625 switch (sel->type) {
2626 case PIPE_SHADER_GEOMETRY:
2627 sel->gs_output_prim =
2628 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2629 sel->gs_max_out_vertices =
2630 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2631 sel->gs_num_invocations =
2632 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2633 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2634 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2635 sel->gs_max_out_vertices;
2636
2637 sel->max_gs_stream = 0;
2638 for (i = 0; i < sel->so.num_outputs; i++)
2639 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2640 sel->so.output[i].stream);
2641
2642 sel->gs_input_verts_per_prim =
2643 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2644 break;
2645
2646 case PIPE_SHADER_TESS_CTRL:
2647 /* Always reserve space for these. */
2648 sel->patch_outputs_written |=
2649 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2650 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2651 /* fall through */
2652 case PIPE_SHADER_VERTEX:
2653 case PIPE_SHADER_TESS_EVAL:
2654 for (i = 0; i < sel->info.num_outputs; i++) {
2655 unsigned name = sel->info.output_semantic_name[i];
2656 unsigned index = sel->info.output_semantic_index[i];
2657
2658 switch (name) {
2659 case TGSI_SEMANTIC_TESSINNER:
2660 case TGSI_SEMANTIC_TESSOUTER:
2661 case TGSI_SEMANTIC_PATCH:
2662 sel->patch_outputs_written |=
2663 1ull << si_shader_io_get_unique_index_patch(name, index);
2664 break;
2665
2666 case TGSI_SEMANTIC_GENERIC:
2667 /* don't process indices the function can't handle */
2668 if (index >= SI_MAX_IO_GENERIC)
2669 break;
2670 /* fall through */
2671 default:
2672 sel->outputs_written |=
2673 1ull << si_shader_io_get_unique_index(name, index, false);
2674 sel->outputs_written_before_ps |=
2675 1ull << si_shader_io_get_unique_index(name, index, true);
2676 break;
2677 case TGSI_SEMANTIC_EDGEFLAG:
2678 break;
2679 }
2680 }
2681 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2682 sel->lshs_vertex_stride = sel->esgs_itemsize;
2683
2684 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2685 * will start on a different bank. (except for the maximum 32*16).
2686 */
2687 if (sel->lshs_vertex_stride < 32*16)
2688 sel->lshs_vertex_stride += 4;
2689
2690 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2691 * conflicts, i.e. each vertex will start at a different bank.
2692 */
2693 if (sctx->chip_class >= GFX9)
2694 sel->esgs_itemsize += 4;
2695
2696 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2697 break;
2698
2699 case PIPE_SHADER_FRAGMENT:
2700 for (i = 0; i < sel->info.num_inputs; i++) {
2701 unsigned name = sel->info.input_semantic_name[i];
2702 unsigned index = sel->info.input_semantic_index[i];
2703
2704 switch (name) {
2705 case TGSI_SEMANTIC_GENERIC:
2706 /* don't process indices the function can't handle */
2707 if (index >= SI_MAX_IO_GENERIC)
2708 break;
2709 /* fall through */
2710 default:
2711 sel->inputs_read |=
2712 1ull << si_shader_io_get_unique_index(name, index, true);
2713 break;
2714 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2715 break;
2716 }
2717 }
2718
2719 for (i = 0; i < 8; i++)
2720 if (sel->info.colors_written & (1 << i))
2721 sel->colors_written_4bit |= 0xf << (4 * i);
2722
2723 for (i = 0; i < sel->info.num_inputs; i++) {
2724 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2725 int index = sel->info.input_semantic_index[i];
2726 sel->color_attr_index[index] = i;
2727 }
2728 }
2729 break;
2730 }
2731
2732 /* PA_CL_VS_OUT_CNTL */
2733 bool misc_vec_ena =
2734 sel->info.writes_psize || sel->info.writes_edgeflag ||
2735 sel->info.writes_layer || sel->info.writes_viewport_index;
2736 sel->pa_cl_vs_out_cntl =
2737 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2738 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2739 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2740 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2741 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2742 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2743 sel->clipdist_mask = sel->info.writes_clipvertex ?
2744 SIX_BITS : sel->info.clipdist_writemask;
2745 sel->culldist_mask = sel->info.culldist_writemask <<
2746 sel->info.num_written_clipdistance;
2747
2748 /* DB_SHADER_CONTROL */
2749 sel->db_shader_control =
2750 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2751 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2752 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2753 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2754
2755 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2756 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2757 sel->db_shader_control |=
2758 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2759 break;
2760 case TGSI_FS_DEPTH_LAYOUT_LESS:
2761 sel->db_shader_control |=
2762 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2763 break;
2764 }
2765
2766 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2767 *
2768 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2769 * --|-----------|------------|------------|--------------------|-------------------|-------------
2770 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2771 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2772 * 2 | false | true | n/a | LateZ | 1 | 0
2773 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2774 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2775 *
2776 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2777 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2778 *
2779 * Don't use ReZ without profiling !!!
2780 *
2781 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2782 * shaders.
2783 */
2784 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2785 /* Cases 3, 4. */
2786 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2787 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2788 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2789 } else if (sel->info.writes_memory) {
2790 /* Case 2. */
2791 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2792 S_02880C_EXEC_ON_HIER_FAIL(1);
2793 } else {
2794 /* Case 1. */
2795 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2796 }
2797
2798 (void) mtx_init(&sel->mutex, mtx_plain);
2799
2800 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2801 &sel->compiler_ctx_state, sel,
2802 si_init_shader_selector_async);
2803 return sel;
2804 }
2805
2806 static void si_update_streamout_state(struct si_context *sctx)
2807 {
2808 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2809
2810 if (!shader_with_so)
2811 return;
2812
2813 sctx->streamout.enabled_stream_buffers_mask =
2814 shader_with_so->enabled_streamout_buffer_mask;
2815 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2816 }
2817
2818 static void si_update_clip_regs(struct si_context *sctx,
2819 struct si_shader_selector *old_hw_vs,
2820 struct si_shader *old_hw_vs_variant,
2821 struct si_shader_selector *next_hw_vs,
2822 struct si_shader *next_hw_vs_variant)
2823 {
2824 if (next_hw_vs &&
2825 (!old_hw_vs ||
2826 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2827 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2828 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2829 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2830 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2831 !old_hw_vs_variant ||
2832 !next_hw_vs_variant ||
2833 old_hw_vs_variant->key.opt.clip_disable !=
2834 next_hw_vs_variant->key.opt.clip_disable))
2835 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2836 }
2837
2838 static void si_update_common_shader_state(struct si_context *sctx)
2839 {
2840 sctx->uses_bindless_samplers =
2841 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2842 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2843 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2844 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2845 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2846 sctx->uses_bindless_images =
2847 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2848 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2849 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2850 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2851 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2852 sctx->do_update_shaders = true;
2853 }
2854
2855 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2856 {
2857 struct si_context *sctx = (struct si_context *)ctx;
2858 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2859 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2860 struct si_shader_selector *sel = state;
2861
2862 if (sctx->vs_shader.cso == sel)
2863 return;
2864
2865 sctx->vs_shader.cso = sel;
2866 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2867 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2868
2869 si_update_common_shader_state(sctx);
2870 si_update_vs_viewport_state(sctx);
2871 si_set_active_descriptors_for_shader(sctx, sel);
2872 si_update_streamout_state(sctx);
2873 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2874 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2875 }
2876
2877 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2878 {
2879 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2880 (sctx->tes_shader.cso &&
2881 sctx->tes_shader.cso->info.uses_primid) ||
2882 (sctx->tcs_shader.cso &&
2883 sctx->tcs_shader.cso->info.uses_primid) ||
2884 (sctx->gs_shader.cso &&
2885 sctx->gs_shader.cso->info.uses_primid) ||
2886 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2887 sctx->ps_shader.cso->info.uses_primid);
2888 }
2889
2890 static bool si_update_ngg(struct si_context *sctx)
2891 {
2892 if (sctx->chip_class <= GFX9 ||
2893 sctx->screen->options.disable_ngg)
2894 return false;
2895
2896 bool new_ngg = true;
2897
2898 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2899 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
2900 sctx->gs_shader.cso->gs_num_invocations * sctx->gs_shader.cso->gs_max_out_vertices > 256)
2901 new_ngg = false;
2902
2903 if (new_ngg != sctx->ngg) {
2904 sctx->ngg = new_ngg;
2905 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2906 return true;
2907 }
2908 return false;
2909 }
2910
2911 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2912 {
2913 struct si_context *sctx = (struct si_context *)ctx;
2914 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2915 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2916 struct si_shader_selector *sel = state;
2917 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2918 bool ngg_changed;
2919
2920 if (sctx->gs_shader.cso == sel)
2921 return;
2922
2923 sctx->gs_shader.cso = sel;
2924 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2925 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2926
2927 si_update_common_shader_state(sctx);
2928 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2929
2930 ngg_changed = si_update_ngg(sctx);
2931 if (ngg_changed || enable_changed)
2932 si_shader_change_notify(sctx);
2933 if (enable_changed) {
2934 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2935 si_update_tess_uses_prim_id(sctx);
2936 }
2937 si_update_vs_viewport_state(sctx);
2938 si_set_active_descriptors_for_shader(sctx, sel);
2939 si_update_streamout_state(sctx);
2940 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2941 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2942 }
2943
2944 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2945 {
2946 struct si_context *sctx = (struct si_context *)ctx;
2947 struct si_shader_selector *sel = state;
2948 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2949
2950 if (sctx->tcs_shader.cso == sel)
2951 return;
2952
2953 sctx->tcs_shader.cso = sel;
2954 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
2955 si_update_tess_uses_prim_id(sctx);
2956
2957 si_update_common_shader_state(sctx);
2958
2959 if (enable_changed)
2960 sctx->last_tcs = NULL; /* invalidate derived tess state */
2961
2962 si_set_active_descriptors_for_shader(sctx, sel);
2963 }
2964
2965 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
2966 {
2967 struct si_context *sctx = (struct si_context *)ctx;
2968 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2969 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2970 struct si_shader_selector *sel = state;
2971 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
2972
2973 if (sctx->tes_shader.cso == sel)
2974 return;
2975
2976 sctx->tes_shader.cso = sel;
2977 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
2978 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
2979 si_update_tess_uses_prim_id(sctx);
2980
2981 si_update_common_shader_state(sctx);
2982 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2983
2984 if (enable_changed) {
2985 si_update_ngg(sctx);
2986 si_shader_change_notify(sctx);
2987 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
2988 }
2989 si_update_vs_viewport_state(sctx);
2990 si_set_active_descriptors_for_shader(sctx, sel);
2991 si_update_streamout_state(sctx);
2992 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2993 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2994 }
2995
2996 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2997 {
2998 struct si_context *sctx = (struct si_context *)ctx;
2999 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3000 struct si_shader_selector *sel = state;
3001
3002 /* skip if supplied shader is one already in use */
3003 if (old_sel == sel)
3004 return;
3005
3006 sctx->ps_shader.cso = sel;
3007 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3008
3009 si_update_common_shader_state(sctx);
3010 if (sel) {
3011 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3012 si_update_tess_uses_prim_id(sctx);
3013
3014 if (!old_sel ||
3015 old_sel->info.colors_written != sel->info.colors_written)
3016 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3017
3018 if (sctx->screen->has_out_of_order_rast &&
3019 (!old_sel ||
3020 old_sel->info.writes_memory != sel->info.writes_memory ||
3021 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3022 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3023 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3024 }
3025 si_set_active_descriptors_for_shader(sctx, sel);
3026 si_update_ps_colorbuf0_slot(sctx);
3027 }
3028
3029 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3030 {
3031 if (shader->is_optimized) {
3032 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3033 &shader->ready);
3034 }
3035
3036 util_queue_fence_destroy(&shader->ready);
3037
3038 if (shader->pm4) {
3039 switch (shader->selector->type) {
3040 case PIPE_SHADER_VERTEX:
3041 if (shader->key.as_ls) {
3042 assert(sctx->chip_class <= GFX8);
3043 si_pm4_delete_state(sctx, ls, shader->pm4);
3044 } else if (shader->key.as_es) {
3045 assert(sctx->chip_class <= GFX8);
3046 si_pm4_delete_state(sctx, es, shader->pm4);
3047 } else {
3048 si_pm4_delete_state(sctx, vs, shader->pm4);
3049 }
3050 break;
3051 case PIPE_SHADER_TESS_CTRL:
3052 si_pm4_delete_state(sctx, hs, shader->pm4);
3053 break;
3054 case PIPE_SHADER_TESS_EVAL:
3055 if (shader->key.as_es) {
3056 assert(sctx->chip_class <= GFX8);
3057 si_pm4_delete_state(sctx, es, shader->pm4);
3058 } else {
3059 si_pm4_delete_state(sctx, vs, shader->pm4);
3060 }
3061 break;
3062 case PIPE_SHADER_GEOMETRY:
3063 if (shader->is_gs_copy_shader)
3064 si_pm4_delete_state(sctx, vs, shader->pm4);
3065 else
3066 si_pm4_delete_state(sctx, gs, shader->pm4);
3067 break;
3068 case PIPE_SHADER_FRAGMENT:
3069 si_pm4_delete_state(sctx, ps, shader->pm4);
3070 break;
3071 }
3072 }
3073
3074 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3075 si_shader_destroy(shader);
3076 free(shader);
3077 }
3078
3079 void si_destroy_shader_selector(struct si_context *sctx,
3080 struct si_shader_selector *sel)
3081 {
3082 struct si_shader *p = sel->first_variant, *c;
3083 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3084 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3085 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3086 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3087 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3088 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3089 };
3090
3091 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3092
3093 if (current_shader[sel->type]->cso == sel) {
3094 current_shader[sel->type]->cso = NULL;
3095 current_shader[sel->type]->current = NULL;
3096 }
3097
3098 while (p) {
3099 c = p->next_variant;
3100 si_delete_shader(sctx, p);
3101 p = c;
3102 }
3103
3104 if (sel->main_shader_part)
3105 si_delete_shader(sctx, sel->main_shader_part);
3106 if (sel->main_shader_part_ls)
3107 si_delete_shader(sctx, sel->main_shader_part_ls);
3108 if (sel->main_shader_part_es)
3109 si_delete_shader(sctx, sel->main_shader_part_es);
3110 if (sel->main_shader_part_ngg)
3111 si_delete_shader(sctx, sel->main_shader_part_ngg);
3112 if (sel->gs_copy_shader)
3113 si_delete_shader(sctx, sel->gs_copy_shader);
3114
3115 util_queue_fence_destroy(&sel->ready);
3116 mtx_destroy(&sel->mutex);
3117 free(sel->tokens);
3118 ralloc_free(sel->nir);
3119 free(sel);
3120 }
3121
3122 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3123 {
3124 struct si_context *sctx = (struct si_context *)ctx;
3125 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3126
3127 si_shader_selector_reference(sctx, &sel, NULL);
3128 }
3129
3130 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3131 struct si_shader *vs, unsigned name,
3132 unsigned index, unsigned interpolate)
3133 {
3134 struct tgsi_shader_info *vsinfo = &vs->selector->info;
3135 unsigned j, offset, ps_input_cntl = 0;
3136
3137 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3138 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3139 name == TGSI_SEMANTIC_PRIMID)
3140 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3141
3142 if (name == TGSI_SEMANTIC_PCOORD ||
3143 (name == TGSI_SEMANTIC_TEXCOORD &&
3144 sctx->sprite_coord_enable & (1 << index))) {
3145 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3146 }
3147
3148 for (j = 0; j < vsinfo->num_outputs; j++) {
3149 if (name == vsinfo->output_semantic_name[j] &&
3150 index == vsinfo->output_semantic_index[j]) {
3151 offset = vs->info.vs_output_param_offset[j];
3152
3153 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3154 /* The input is loaded from parameter memory. */
3155 ps_input_cntl |= S_028644_OFFSET(offset);
3156 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3157 if (offset == AC_EXP_PARAM_UNDEFINED) {
3158 /* This can happen with depth-only rendering. */
3159 offset = 0;
3160 } else {
3161 /* The input is a DEFAULT_VAL constant. */
3162 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3163 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3164 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3165 }
3166
3167 ps_input_cntl = S_028644_OFFSET(0x20) |
3168 S_028644_DEFAULT_VAL(offset);
3169 }
3170 break;
3171 }
3172 }
3173
3174 if (name == TGSI_SEMANTIC_PRIMID)
3175 /* PrimID is written after the last output. */
3176 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3177 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3178 /* No corresponding output found, load defaults into input.
3179 * Don't set any other bits.
3180 * (FLAT_SHADE=1 completely changes behavior) */
3181 ps_input_cntl = S_028644_OFFSET(0x20);
3182 /* D3D 9 behaviour. GL is undefined */
3183 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3184 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3185 }
3186 return ps_input_cntl;
3187 }
3188
3189 static void si_emit_spi_map(struct si_context *sctx)
3190 {
3191 struct si_shader *ps = sctx->ps_shader.current;
3192 struct si_shader *vs = si_get_vs_state(sctx);
3193 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3194 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3195 unsigned spi_ps_input_cntl[32];
3196
3197 if (!ps || !ps->selector->info.num_inputs)
3198 return;
3199
3200 num_interp = si_get_ps_num_interp(ps);
3201 assert(num_interp > 0);
3202
3203 for (i = 0; i < psinfo->num_inputs; i++) {
3204 unsigned name = psinfo->input_semantic_name[i];
3205 unsigned index = psinfo->input_semantic_index[i];
3206 unsigned interpolate = psinfo->input_interpolate[i];
3207
3208 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3209 index, interpolate);
3210
3211 if (name == TGSI_SEMANTIC_COLOR) {
3212 assert(index < ARRAY_SIZE(bcol_interp));
3213 bcol_interp[index] = interpolate;
3214 }
3215 }
3216
3217 if (ps->key.part.ps.prolog.color_two_side) {
3218 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3219
3220 for (i = 0; i < 2; i++) {
3221 if (!(psinfo->colors_read & (0xf << (i * 4))))
3222 continue;
3223
3224 spi_ps_input_cntl[num_written++] =
3225 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3226
3227 }
3228 }
3229 assert(num_interp == num_written);
3230
3231 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3232 /* Dota 2: Only ~16% of SPI map updates set different values. */
3233 /* Talos: Only ~9% of SPI map updates set different values. */
3234 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3235 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3236 spi_ps_input_cntl,
3237 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3238
3239 if (initial_cdw != sctx->gfx_cs->current.cdw)
3240 sctx->context_roll = true;
3241 }
3242
3243 /**
3244 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3245 */
3246 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3247 {
3248 if (sctx->init_config_has_vgt_flush)
3249 return;
3250
3251 /* Done by Vulkan before VGT_FLUSH. */
3252 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3253 si_pm4_cmd_add(sctx->init_config,
3254 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3255 si_pm4_cmd_end(sctx->init_config, false);
3256
3257 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3258 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3259 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3260 si_pm4_cmd_end(sctx->init_config, false);
3261 sctx->init_config_has_vgt_flush = true;
3262 }
3263
3264 /* Initialize state related to ESGS / GSVS ring buffers */
3265 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3266 {
3267 struct si_shader_selector *es =
3268 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3269 struct si_shader_selector *gs = sctx->gs_shader.cso;
3270 struct si_pm4_state *pm4;
3271
3272 /* Chip constants. */
3273 unsigned num_se = sctx->screen->info.max_se;
3274 unsigned wave_size = 64;
3275 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3276 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3277 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3278 */
3279 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3280 unsigned alignment = 256 * num_se;
3281 /* The maximum size is 63.999 MB per SE. */
3282 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3283
3284 /* Calculate the minimum size. */
3285 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3286 wave_size, alignment);
3287
3288 /* These are recommended sizes, not minimum sizes. */
3289 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3290 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3291 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3292 gs->max_gsvs_emit_size;
3293
3294 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3295 esgs_ring_size = align(esgs_ring_size, alignment);
3296 gsvs_ring_size = align(gsvs_ring_size, alignment);
3297
3298 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3299 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3300
3301 /* Some rings don't have to be allocated if shaders don't use them.
3302 * (e.g. no varyings between ES and GS or GS and VS)
3303 *
3304 * GFX9 doesn't have the ESGS ring.
3305 */
3306 bool update_esgs = sctx->chip_class <= GFX8 &&
3307 esgs_ring_size &&
3308 (!sctx->esgs_ring ||
3309 sctx->esgs_ring->width0 < esgs_ring_size);
3310 bool update_gsvs = gsvs_ring_size &&
3311 (!sctx->gsvs_ring ||
3312 sctx->gsvs_ring->width0 < gsvs_ring_size);
3313
3314 if (!update_esgs && !update_gsvs)
3315 return true;
3316
3317 if (update_esgs) {
3318 pipe_resource_reference(&sctx->esgs_ring, NULL);
3319 sctx->esgs_ring =
3320 pipe_aligned_buffer_create(sctx->b.screen,
3321 SI_RESOURCE_FLAG_UNMAPPABLE,
3322 PIPE_USAGE_DEFAULT,
3323 esgs_ring_size, alignment);
3324 if (!sctx->esgs_ring)
3325 return false;
3326 }
3327
3328 if (update_gsvs) {
3329 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3330 sctx->gsvs_ring =
3331 pipe_aligned_buffer_create(sctx->b.screen,
3332 SI_RESOURCE_FLAG_UNMAPPABLE,
3333 PIPE_USAGE_DEFAULT,
3334 gsvs_ring_size, alignment);
3335 if (!sctx->gsvs_ring)
3336 return false;
3337 }
3338
3339 /* Create the "init_config_gs_rings" state. */
3340 pm4 = CALLOC_STRUCT(si_pm4_state);
3341 if (!pm4)
3342 return false;
3343
3344 if (sctx->chip_class >= GFX7) {
3345 if (sctx->esgs_ring) {
3346 assert(sctx->chip_class <= GFX8);
3347 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3348 sctx->esgs_ring->width0 / 256);
3349 }
3350 if (sctx->gsvs_ring)
3351 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3352 sctx->gsvs_ring->width0 / 256);
3353 } else {
3354 if (sctx->esgs_ring)
3355 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3356 sctx->esgs_ring->width0 / 256);
3357 if (sctx->gsvs_ring)
3358 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3359 sctx->gsvs_ring->width0 / 256);
3360 }
3361
3362 /* Set the state. */
3363 if (sctx->init_config_gs_rings)
3364 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3365 sctx->init_config_gs_rings = pm4;
3366
3367 if (!sctx->init_config_has_vgt_flush) {
3368 si_init_config_add_vgt_flush(sctx);
3369 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3370 }
3371
3372 /* Flush the context to re-emit both init_config states. */
3373 sctx->initial_gfx_cs_size = 0; /* force flush */
3374 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3375
3376 /* Set ring bindings. */
3377 if (sctx->esgs_ring) {
3378 assert(sctx->chip_class <= GFX8);
3379 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3380 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3381 true, true, 4, 64, 0);
3382 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3383 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3384 false, false, 0, 0, 0);
3385 }
3386 if (sctx->gsvs_ring) {
3387 si_set_ring_buffer(sctx, SI_RING_GSVS,
3388 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3389 false, false, 0, 0, 0);
3390 }
3391
3392 return true;
3393 }
3394
3395 static void si_shader_lock(struct si_shader *shader)
3396 {
3397 mtx_lock(&shader->selector->mutex);
3398 if (shader->previous_stage_sel) {
3399 assert(shader->previous_stage_sel != shader->selector);
3400 mtx_lock(&shader->previous_stage_sel->mutex);
3401 }
3402 }
3403
3404 static void si_shader_unlock(struct si_shader *shader)
3405 {
3406 if (shader->previous_stage_sel)
3407 mtx_unlock(&shader->previous_stage_sel->mutex);
3408 mtx_unlock(&shader->selector->mutex);
3409 }
3410
3411 /**
3412 * @returns 1 if \p sel has been updated to use a new scratch buffer
3413 * 0 if not
3414 * < 0 if there was a failure
3415 */
3416 static int si_update_scratch_buffer(struct si_context *sctx,
3417 struct si_shader *shader)
3418 {
3419 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3420
3421 if (!shader)
3422 return 0;
3423
3424 /* This shader doesn't need a scratch buffer */
3425 if (shader->config.scratch_bytes_per_wave == 0)
3426 return 0;
3427
3428 /* Prevent race conditions when updating:
3429 * - si_shader::scratch_bo
3430 * - si_shader::binary::code
3431 * - si_shader::previous_stage::binary::code.
3432 */
3433 si_shader_lock(shader);
3434
3435 /* This shader is already configured to use the current
3436 * scratch buffer. */
3437 if (shader->scratch_bo == sctx->scratch_buffer) {
3438 si_shader_unlock(shader);
3439 return 0;
3440 }
3441
3442 assert(sctx->scratch_buffer);
3443
3444 /* Replace the shader bo with a new bo that has the relocs applied. */
3445 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3446 si_shader_unlock(shader);
3447 return -1;
3448 }
3449
3450 /* Update the shader state to use the new shader bo. */
3451 si_shader_init_pm4_state(sctx->screen, shader);
3452
3453 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3454
3455 si_shader_unlock(shader);
3456 return 1;
3457 }
3458
3459 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
3460 {
3461 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
3462 }
3463
3464 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3465 {
3466 return shader ? shader->config.scratch_bytes_per_wave : 0;
3467 }
3468
3469 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3470 {
3471 if (!sctx->tes_shader.cso)
3472 return NULL; /* tessellation disabled */
3473
3474 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3475 sctx->fixed_func_tcs_shader.current;
3476 }
3477
3478 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
3479 {
3480 unsigned bytes = 0;
3481
3482 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3483 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3484 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3485 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3486
3487 if (sctx->tes_shader.cso) {
3488 struct si_shader *tcs = si_get_tcs_current(sctx);
3489
3490 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
3491 }
3492 return bytes;
3493 }
3494
3495 static bool si_update_scratch_relocs(struct si_context *sctx)
3496 {
3497 struct si_shader *tcs = si_get_tcs_current(sctx);
3498 int r;
3499
3500 /* Update the shaders, so that they are using the latest scratch.
3501 * The scratch buffer may have been changed since these shaders were
3502 * last used, so we still need to try to update them, even if they
3503 * require scratch buffers smaller than the current size.
3504 */
3505 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3506 if (r < 0)
3507 return false;
3508 if (r == 1)
3509 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3510
3511 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3512 if (r < 0)
3513 return false;
3514 if (r == 1)
3515 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3516
3517 r = si_update_scratch_buffer(sctx, tcs);
3518 if (r < 0)
3519 return false;
3520 if (r == 1)
3521 si_pm4_bind_state(sctx, hs, tcs->pm4);
3522
3523 /* VS can be bound as LS, ES, or VS. */
3524 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3525 if (r < 0)
3526 return false;
3527 if (r == 1) {
3528 if (sctx->tes_shader.current)
3529 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3530 else if (sctx->gs_shader.current)
3531 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3532 else
3533 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3534 }
3535
3536 /* TES can be bound as ES or VS. */
3537 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3538 if (r < 0)
3539 return false;
3540 if (r == 1) {
3541 if (sctx->gs_shader.current)
3542 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3543 else
3544 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3545 }
3546
3547 return true;
3548 }
3549
3550 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3551 {
3552 unsigned current_scratch_buffer_size =
3553 si_get_current_scratch_buffer_size(sctx);
3554 unsigned scratch_bytes_per_wave =
3555 si_get_max_scratch_bytes_per_wave(sctx);
3556 unsigned scratch_needed_size = scratch_bytes_per_wave *
3557 sctx->scratch_waves;
3558 unsigned spi_tmpring_size;
3559
3560 if (scratch_needed_size > 0) {
3561 if (scratch_needed_size > current_scratch_buffer_size) {
3562 /* Create a bigger scratch buffer */
3563 si_resource_reference(&sctx->scratch_buffer, NULL);
3564
3565 sctx->scratch_buffer =
3566 si_aligned_buffer_create(&sctx->screen->b,
3567 SI_RESOURCE_FLAG_UNMAPPABLE,
3568 PIPE_USAGE_DEFAULT,
3569 scratch_needed_size, 256);
3570 if (!sctx->scratch_buffer)
3571 return false;
3572
3573 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3574 si_context_add_resource_size(sctx,
3575 &sctx->scratch_buffer->b.b);
3576 }
3577
3578 if (!si_update_scratch_relocs(sctx))
3579 return false;
3580 }
3581
3582 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3583 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3584 "scratch size should already be aligned correctly.");
3585
3586 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3587 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3588 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3589 sctx->spi_tmpring_size = spi_tmpring_size;
3590 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3591 }
3592 return true;
3593 }
3594
3595 static void si_init_tess_factor_ring(struct si_context *sctx)
3596 {
3597 assert(!sctx->tess_rings);
3598
3599 /* The address must be aligned to 2^19, because the shader only
3600 * receives the high 13 bits.
3601 */
3602 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3603 SI_RESOURCE_FLAG_32BIT,
3604 PIPE_USAGE_DEFAULT,
3605 sctx->screen->tess_offchip_ring_size +
3606 sctx->screen->tess_factor_ring_size,
3607 1 << 19);
3608 if (!sctx->tess_rings)
3609 return;
3610
3611 si_init_config_add_vgt_flush(sctx);
3612
3613 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3614 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3615
3616 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3617 sctx->screen->tess_offchip_ring_size;
3618
3619 /* Append these registers to the init config state. */
3620 if (sctx->chip_class >= GFX7) {
3621 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3622 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3623 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3624 factor_va >> 8);
3625 if (sctx->chip_class >= GFX9)
3626 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3627 S_030944_BASE_HI(factor_va >> 40));
3628 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3629 sctx->screen->vgt_hs_offchip_param);
3630 } else {
3631 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3632 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3633 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3634 factor_va >> 8);
3635 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3636 sctx->screen->vgt_hs_offchip_param);
3637 }
3638
3639 /* Flush the context to re-emit the init_config state.
3640 * This is done only once in a lifetime of a context.
3641 */
3642 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3643 sctx->initial_gfx_cs_size = 0; /* force flush */
3644 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3645 }
3646
3647 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3648 union si_vgt_stages_key key)
3649 {
3650 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3651 uint32_t stages = 0;
3652
3653 if (key.u.tess) {
3654 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3655 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3656
3657 if (key.u.gs)
3658 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3659 S_028B54_GS_EN(1);
3660 else if (key.u.ngg)
3661 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3662 else
3663 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3664 } else if (key.u.gs) {
3665 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3666 S_028B54_GS_EN(1);
3667 } else if (key.u.ngg) {
3668 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3669 }
3670
3671 if (key.u.ngg) {
3672 stages |= S_028B54_PRIMGEN_EN(1);
3673 if (key.u.streamout)
3674 stages |= S_028B54_NGG_WAVE_ID_EN(1);
3675 } else if (key.u.gs)
3676 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3677
3678 if (screen->info.chip_class >= GFX9)
3679 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3680
3681 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3682 return pm4;
3683 }
3684
3685 static void si_update_vgt_shader_config(struct si_context *sctx,
3686 union si_vgt_stages_key key)
3687 {
3688 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3689
3690 if (unlikely(!*pm4))
3691 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3692 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3693 }
3694
3695 bool si_update_shaders(struct si_context *sctx)
3696 {
3697 struct pipe_context *ctx = (struct pipe_context*)sctx;
3698 struct si_compiler_ctx_state compiler_state;
3699 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3700 struct si_shader *old_vs = si_get_vs_state(sctx);
3701 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3702 struct si_shader *old_ps = sctx->ps_shader.current;
3703 union si_vgt_stages_key key;
3704 unsigned old_spi_shader_col_format =
3705 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3706 int r;
3707
3708 compiler_state.compiler = &sctx->compiler;
3709 compiler_state.debug = sctx->debug;
3710 compiler_state.is_debug_context = sctx->is_debug;
3711
3712 key.index = 0;
3713
3714 if (sctx->tes_shader.cso)
3715 key.u.tess = 1;
3716 if (sctx->gs_shader.cso)
3717 key.u.gs = 1;
3718
3719 if (sctx->chip_class >= GFX10) {
3720 key.u.ngg = sctx->ngg;
3721
3722 if (sctx->gs_shader.cso)
3723 key.u.streamout = !!sctx->gs_shader.cso->so.num_outputs;
3724 else if (sctx->tes_shader.cso)
3725 key.u.streamout = !!sctx->tes_shader.cso->so.num_outputs;
3726 else
3727 key.u.streamout = !!sctx->vs_shader.cso->so.num_outputs;
3728 }
3729
3730 /* Update TCS and TES. */
3731 if (sctx->tes_shader.cso) {
3732 if (!sctx->tess_rings) {
3733 si_init_tess_factor_ring(sctx);
3734 if (!sctx->tess_rings)
3735 return false;
3736 }
3737
3738 if (sctx->tcs_shader.cso) {
3739 r = si_shader_select(ctx, &sctx->tcs_shader, key,
3740 &compiler_state);
3741 if (r)
3742 return false;
3743 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3744 } else {
3745 if (!sctx->fixed_func_tcs_shader.cso) {
3746 sctx->fixed_func_tcs_shader.cso =
3747 si_create_fixed_func_tcs(sctx);
3748 if (!sctx->fixed_func_tcs_shader.cso)
3749 return false;
3750 }
3751
3752 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3753 key, &compiler_state);
3754 if (r)
3755 return false;
3756 si_pm4_bind_state(sctx, hs,
3757 sctx->fixed_func_tcs_shader.current->pm4);
3758 }
3759
3760 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3761 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3762 if (r)
3763 return false;
3764
3765 if (sctx->gs_shader.cso) {
3766 /* TES as ES */
3767 assert(sctx->chip_class <= GFX8);
3768 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3769 } else if (key.u.ngg) {
3770 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3771 } else {
3772 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3773 }
3774 }
3775 } else {
3776 if (sctx->chip_class <= GFX8)
3777 si_pm4_bind_state(sctx, ls, NULL);
3778 si_pm4_bind_state(sctx, hs, NULL);
3779 }
3780
3781 /* Update GS. */
3782 if (sctx->gs_shader.cso) {
3783 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
3784 if (r)
3785 return false;
3786 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3787 if (!key.u.ngg) {
3788 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3789
3790 if (!si_update_gs_ring_buffers(sctx))
3791 return false;
3792 } else {
3793 si_pm4_bind_state(sctx, vs, NULL);
3794 }
3795 } else {
3796 if (!key.u.ngg) {
3797 si_pm4_bind_state(sctx, gs, NULL);
3798 if (sctx->chip_class <= GFX8)
3799 si_pm4_bind_state(sctx, es, NULL);
3800 }
3801 }
3802
3803 /* Update VS. */
3804 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
3805 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
3806 if (r)
3807 return false;
3808
3809 if (!key.u.tess && !key.u.gs) {
3810 if (key.u.ngg) {
3811 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3812 si_pm4_bind_state(sctx, vs, NULL);
3813 } else {
3814 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3815 }
3816 } else if (sctx->tes_shader.cso) {
3817 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3818 } else {
3819 assert(sctx->gs_shader.cso);
3820 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3821 }
3822 }
3823
3824 si_update_vgt_shader_config(sctx, key);
3825
3826 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3827 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3828
3829 if (sctx->ps_shader.cso) {
3830 unsigned db_shader_control;
3831
3832 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
3833 if (r)
3834 return false;
3835 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3836
3837 db_shader_control =
3838 sctx->ps_shader.cso->db_shader_control |
3839 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3840
3841 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3842 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3843 sctx->flatshade != rs->flatshade) {
3844 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3845 sctx->flatshade = rs->flatshade;
3846 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3847 }
3848
3849 if (sctx->screen->rbplus_allowed &&
3850 si_pm4_state_changed(sctx, ps) &&
3851 (!old_ps ||
3852 old_spi_shader_col_format !=
3853 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3854 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3855
3856 if (sctx->ps_db_shader_control != db_shader_control) {
3857 sctx->ps_db_shader_control = db_shader_control;
3858 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3859 if (sctx->screen->dpbb_allowed)
3860 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3861 }
3862
3863 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3864 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3865 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3866
3867 if (sctx->chip_class == GFX6)
3868 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3869
3870 if (sctx->framebuffer.nr_samples <= 1)
3871 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3872 }
3873 }
3874
3875 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3876 si_pm4_state_enabled_and_changed(sctx, hs) ||
3877 si_pm4_state_enabled_and_changed(sctx, es) ||
3878 si_pm4_state_enabled_and_changed(sctx, gs) ||
3879 si_pm4_state_enabled_and_changed(sctx, vs) ||
3880 si_pm4_state_enabled_and_changed(sctx, ps)) {
3881 if (!si_update_spi_tmpring_size(sctx))
3882 return false;
3883 }
3884
3885 if (sctx->chip_class >= GFX7) {
3886 if (si_pm4_state_enabled_and_changed(sctx, ls))
3887 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3888 else if (!sctx->queued.named.ls)
3889 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3890
3891 if (si_pm4_state_enabled_and_changed(sctx, hs))
3892 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3893 else if (!sctx->queued.named.hs)
3894 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3895
3896 if (si_pm4_state_enabled_and_changed(sctx, es))
3897 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
3898 else if (!sctx->queued.named.es)
3899 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
3900
3901 if (si_pm4_state_enabled_and_changed(sctx, gs))
3902 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
3903 else if (!sctx->queued.named.gs)
3904 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
3905
3906 if (si_pm4_state_enabled_and_changed(sctx, vs))
3907 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
3908 else if (!sctx->queued.named.vs)
3909 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
3910
3911 if (si_pm4_state_enabled_and_changed(sctx, ps))
3912 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
3913 else if (!sctx->queued.named.ps)
3914 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
3915 }
3916
3917 sctx->do_update_shaders = false;
3918 return true;
3919 }
3920
3921 static void si_emit_scratch_state(struct si_context *sctx)
3922 {
3923 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3924
3925 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3926 sctx->spi_tmpring_size);
3927
3928 if (sctx->scratch_buffer) {
3929 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3930 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3931 RADEON_PRIO_SCRATCH_BUFFER);
3932 }
3933 }
3934
3935 void si_init_shader_functions(struct si_context *sctx)
3936 {
3937 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
3938 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
3939
3940 sctx->b.create_vs_state = si_create_shader_selector;
3941 sctx->b.create_tcs_state = si_create_shader_selector;
3942 sctx->b.create_tes_state = si_create_shader_selector;
3943 sctx->b.create_gs_state = si_create_shader_selector;
3944 sctx->b.create_fs_state = si_create_shader_selector;
3945
3946 sctx->b.bind_vs_state = si_bind_vs_shader;
3947 sctx->b.bind_tcs_state = si_bind_tcs_shader;
3948 sctx->b.bind_tes_state = si_bind_tes_shader;
3949 sctx->b.bind_gs_state = si_bind_gs_shader;
3950 sctx->b.bind_fs_state = si_bind_ps_shader;
3951
3952 sctx->b.delete_vs_state = si_delete_shader_selector;
3953 sctx->b.delete_tcs_state = si_delete_shader_selector;
3954 sctx->b.delete_tes_state = si_delete_shader_selector;
3955 sctx->b.delete_gs_state = si_delete_shader_selector;
3956 sctx->b.delete_fs_state = si_delete_shader_selector;
3957 }