2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
31 #include "radeon/r600_cs.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/hash_table.h"
36 #include "util/crc32.h"
37 #include "util/u_memory.h"
38 #include "util/u_prim.h"
40 #include "util/disk_cache.h"
41 #include "util/mesa-sha1.h"
42 #include "ac_exp_param.h"
47 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
50 static void *si_get_tgsi_binary(struct si_shader_selector
*sel
)
52 unsigned tgsi_size
= tgsi_num_tokens(sel
->tokens
) *
53 sizeof(struct tgsi_token
);
54 unsigned size
= 4 + tgsi_size
+ sizeof(sel
->so
);
55 char *result
= (char*)MALLOC(size
);
60 *((uint32_t*)result
) = size
;
61 memcpy(result
+ 4, sel
->tokens
, tgsi_size
);
62 memcpy(result
+ 4 + tgsi_size
, &sel
->so
, sizeof(sel
->so
));
66 /** Copy "data" to "ptr" and return the next dword following copied data. */
67 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
69 /* data may be NULL if size == 0 */
71 memcpy(ptr
, data
, size
);
72 ptr
+= DIV_ROUND_UP(size
, 4);
76 /** Read data from "ptr". Return the next dword following the data. */
77 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
79 memcpy(data
, ptr
, size
);
80 ptr
+= DIV_ROUND_UP(size
, 4);
85 * Write the size as uint followed by the data. Return the next dword
86 * following the copied data.
88 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
91 return write_data(ptr
, data
, size
);
95 * Read the size as uint followed by the data. Return both via parameters.
96 * Return the next dword following the data.
98 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
101 assert(*data
== NULL
);
104 *data
= malloc(*size
);
105 return read_data(ptr
, *data
, *size
);
109 * Return the shader binary in a buffer. The first 4 bytes contain its size
112 static void *si_get_shader_binary(struct si_shader
*shader
)
114 /* There is always a size of data followed by the data itself. */
115 unsigned relocs_size
= shader
->binary
.reloc_count
*
116 sizeof(shader
->binary
.relocs
[0]);
117 unsigned disasm_size
= shader
->binary
.disasm_string
?
118 strlen(shader
->binary
.disasm_string
) + 1 : 0;
119 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
120 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
123 4 + /* CRC32 of the data below */
124 align(sizeof(shader
->config
), 4) +
125 align(sizeof(shader
->info
), 4) +
126 4 + align(shader
->binary
.code_size
, 4) +
127 4 + align(shader
->binary
.rodata_size
, 4) +
128 4 + align(relocs_size
, 4) +
129 4 + align(disasm_size
, 4) +
130 4 + align(llvm_ir_size
, 4);
131 void *buffer
= CALLOC(1, size
);
132 uint32_t *ptr
= (uint32_t*)buffer
;
138 ptr
++; /* CRC32 is calculated at the end. */
140 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
141 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
142 ptr
= write_chunk(ptr
, shader
->binary
.code
, shader
->binary
.code_size
);
143 ptr
= write_chunk(ptr
, shader
->binary
.rodata
, shader
->binary
.rodata_size
);
144 ptr
= write_chunk(ptr
, shader
->binary
.relocs
, relocs_size
);
145 ptr
= write_chunk(ptr
, shader
->binary
.disasm_string
, disasm_size
);
146 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
147 assert((char *)ptr
- (char *)buffer
== size
);
150 ptr
= (uint32_t*)buffer
;
152 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
157 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
159 uint32_t *ptr
= (uint32_t*)binary
;
160 uint32_t size
= *ptr
++;
161 uint32_t crc32
= *ptr
++;
164 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
165 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
169 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
170 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
171 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.code
,
172 &shader
->binary
.code_size
);
173 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.rodata
,
174 &shader
->binary
.rodata_size
);
175 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.relocs
, &chunk_size
);
176 shader
->binary
.reloc_count
= chunk_size
/ sizeof(shader
->binary
.relocs
[0]);
177 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.disasm_string
, &chunk_size
);
178 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
184 * Insert a shader into the cache. It's assumed the shader is not in the cache.
185 * Use si_shader_cache_load_shader before calling this.
187 * Returns false on failure, in which case the tgsi_binary should be freed.
189 static bool si_shader_cache_insert_shader(struct si_screen
*sscreen
,
191 struct si_shader
*shader
,
192 bool insert_into_disk_cache
)
195 struct hash_entry
*entry
;
196 uint8_t key
[CACHE_KEY_SIZE
];
198 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, tgsi_binary
);
200 return false; /* already added */
202 hw_binary
= si_get_shader_binary(shader
);
206 if (_mesa_hash_table_insert(sscreen
->shader_cache
, tgsi_binary
,
207 hw_binary
) == NULL
) {
212 if (sscreen
->b
.disk_shader_cache
&& insert_into_disk_cache
) {
213 disk_cache_compute_key(sscreen
->b
.disk_shader_cache
, tgsi_binary
,
214 *((uint32_t *)tgsi_binary
), key
);
215 disk_cache_put(sscreen
->b
.disk_shader_cache
, key
, hw_binary
,
216 *((uint32_t *) hw_binary
));
222 static bool si_shader_cache_load_shader(struct si_screen
*sscreen
,
224 struct si_shader
*shader
)
226 struct hash_entry
*entry
=
227 _mesa_hash_table_search(sscreen
->shader_cache
, tgsi_binary
);
229 if (sscreen
->b
.disk_shader_cache
) {
230 unsigned char sha1
[CACHE_KEY_SIZE
];
231 size_t tg_size
= *((uint32_t *) tgsi_binary
);
233 disk_cache_compute_key(sscreen
->b
.disk_shader_cache
,
234 tgsi_binary
, tg_size
, sha1
);
238 disk_cache_get(sscreen
->b
.disk_shader_cache
,
243 if (binary_size
< sizeof(uint32_t) ||
244 *((uint32_t*)buffer
) != binary_size
) {
245 /* Something has gone wrong discard the item
246 * from the cache and rebuild/link from
249 assert(!"Invalid radeonsi shader disk cache "
252 disk_cache_remove(sscreen
->b
.disk_shader_cache
,
259 if (!si_load_shader_binary(shader
, buffer
)) {
265 if (!si_shader_cache_insert_shader(sscreen
, tgsi_binary
,
272 if (si_load_shader_binary(shader
, entry
->data
))
277 p_atomic_inc(&sscreen
->b
.num_shader_cache_hits
);
281 static uint32_t si_shader_cache_key_hash(const void *key
)
283 /* The first dword is the key size. */
284 return util_hash_crc32(key
, *(uint32_t*)key
);
287 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
289 uint32_t *keya
= (uint32_t*)a
;
290 uint32_t *keyb
= (uint32_t*)b
;
292 /* The first dword is the key size. */
296 return memcmp(keya
, keyb
, *keya
) == 0;
299 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
301 FREE((void*)entry
->key
);
305 bool si_init_shader_cache(struct si_screen
*sscreen
)
307 (void) mtx_init(&sscreen
->shader_cache_mutex
, mtx_plain
);
308 sscreen
->shader_cache
=
309 _mesa_hash_table_create(NULL
,
310 si_shader_cache_key_hash
,
311 si_shader_cache_key_equals
);
313 return sscreen
->shader_cache
!= NULL
;
316 void si_destroy_shader_cache(struct si_screen
*sscreen
)
318 if (sscreen
->shader_cache
)
319 _mesa_hash_table_destroy(sscreen
->shader_cache
,
320 si_destroy_shader_cache_entry
);
321 mtx_destroy(&sscreen
->shader_cache_mutex
);
326 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
327 struct si_shader_selector
*tes
,
328 struct si_pm4_state
*pm4
)
330 struct tgsi_shader_info
*info
= &tes
->info
;
331 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
332 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
333 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
334 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
335 unsigned type
, partitioning
, topology
, distribution_mode
;
337 switch (tes_prim_mode
) {
338 case PIPE_PRIM_LINES
:
339 type
= V_028B6C_TESS_ISOLINE
;
341 case PIPE_PRIM_TRIANGLES
:
342 type
= V_028B6C_TESS_TRIANGLE
;
344 case PIPE_PRIM_QUADS
:
345 type
= V_028B6C_TESS_QUAD
;
352 switch (tes_spacing
) {
353 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
354 partitioning
= V_028B6C_PART_FRAC_ODD
;
356 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
357 partitioning
= V_028B6C_PART_FRAC_EVEN
;
359 case PIPE_TESS_SPACING_EQUAL
:
360 partitioning
= V_028B6C_PART_INTEGER
;
368 topology
= V_028B6C_OUTPUT_POINT
;
369 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
370 topology
= V_028B6C_OUTPUT_LINE
;
371 else if (tes_vertex_order_cw
)
372 /* for some reason, this must be the other way around */
373 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
375 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
377 if (sscreen
->has_distributed_tess
) {
378 if (sscreen
->b
.family
== CHIP_FIJI
||
379 sscreen
->b
.family
>= CHIP_POLARIS10
)
380 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
382 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
384 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
386 si_pm4_set_reg(pm4
, R_028B6C_VGT_TF_PARAM
,
387 S_028B6C_TYPE(type
) |
388 S_028B6C_PARTITIONING(partitioning
) |
389 S_028B6C_TOPOLOGY(topology
) |
390 S_028B6C_DISTRIBUTION_MODE(distribution_mode
));
393 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
394 * whether the "fractional odd" tessellation spacing is used.
396 * Possible VGT configurations and which state should set the register:
398 * Reg set in | VGT shader configuration | Value
399 * ------------------------------------------------------
401 * VS as ES | ES -> GS -> VS | 30
402 * TES as VS | LS -> HS -> VS | 14 or 30
403 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
405 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
407 static void polaris_set_vgt_vertex_reuse(struct si_screen
*sscreen
,
408 struct si_shader_selector
*sel
,
409 struct si_shader
*shader
,
410 struct si_pm4_state
*pm4
)
412 unsigned type
= sel
->type
;
414 if (sscreen
->b
.family
< CHIP_POLARIS10
)
417 /* VS as VS, or VS as ES: */
418 if ((type
== PIPE_SHADER_VERTEX
&&
420 (!shader
->key
.as_ls
&& !shader
->is_gs_copy_shader
))) ||
421 /* TES as VS, or TES as ES: */
422 type
== PIPE_SHADER_TESS_EVAL
) {
423 unsigned vtx_reuse_depth
= 30;
425 if (type
== PIPE_SHADER_TESS_EVAL
&&
426 sel
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] ==
427 PIPE_TESS_SPACING_FRACTIONAL_ODD
)
428 vtx_reuse_depth
= 14;
430 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
435 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
438 si_pm4_clear_state(shader
->pm4
);
440 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
445 static void si_shader_ls(struct si_screen
*sscreen
, struct si_shader
*shader
)
447 struct si_pm4_state
*pm4
;
448 unsigned vgpr_comp_cnt
;
451 assert(sscreen
->b
.chip_class
<= VI
);
453 pm4
= si_get_shader_pm4_state(shader
);
457 va
= shader
->bo
->gpu_address
;
458 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
460 /* We need at least 2 components for LS.
461 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
462 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
464 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
466 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
467 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, va
>> 40);
469 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
470 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
471 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt
) |
472 S_00B528_DX10_CLAMP(1) |
473 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
474 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(SI_VS_NUM_USER_SGPR
) |
475 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
478 static void si_shader_hs(struct si_screen
*sscreen
, struct si_shader
*shader
)
480 struct si_pm4_state
*pm4
;
482 unsigned ls_vgpr_comp_cnt
= 0;
484 pm4
= si_get_shader_pm4_state(shader
);
488 va
= shader
->bo
->gpu_address
;
489 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
491 if (sscreen
->b
.chip_class
>= GFX9
) {
492 si_pm4_set_reg(pm4
, R_00B410_SPI_SHADER_PGM_LO_LS
, va
>> 8);
493 si_pm4_set_reg(pm4
, R_00B414_SPI_SHADER_PGM_HI_LS
, va
>> 40);
495 /* We need at least 2 components for LS.
496 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
497 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
499 ls_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
501 shader
->config
.rsrc2
=
502 S_00B42C_USER_SGPR(GFX9_TCS_NUM_USER_SGPR
) |
503 S_00B42C_USER_SGPR_MSB(GFX9_TCS_NUM_USER_SGPR
>> 5) |
504 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
506 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
507 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, va
>> 40);
509 shader
->config
.rsrc2
=
510 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR
) |
511 S_00B42C_OC_LDS_EN(1) |
512 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
515 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
516 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
517 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
518 S_00B428_DX10_CLAMP(1) |
519 S_00B428_FLOAT_MODE(shader
->config
.float_mode
) |
520 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt
));
522 if (sscreen
->b
.chip_class
<= VI
) {
523 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
524 shader
->config
.rsrc2
);
528 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
530 struct si_pm4_state
*pm4
;
531 unsigned num_user_sgprs
;
532 unsigned vgpr_comp_cnt
;
536 assert(sscreen
->b
.chip_class
<= VI
);
538 pm4
= si_get_shader_pm4_state(shader
);
542 va
= shader
->bo
->gpu_address
;
543 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
545 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
546 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
547 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
548 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
549 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
550 vgpr_comp_cnt
= shader
->selector
->info
.uses_primid
? 3 : 2;
551 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
553 unreachable("invalid shader selector type");
555 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
557 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
558 shader
->selector
->esgs_itemsize
/ 4);
559 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
560 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
561 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
562 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
563 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
564 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
565 S_00B328_DX10_CLAMP(1) |
566 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
567 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
568 S_00B32C_USER_SGPR(num_user_sgprs
) |
569 S_00B32C_OC_LDS_EN(oc_lds_en
) |
570 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
572 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
573 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
575 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
579 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
582 static uint32_t si_vgt_gs_mode(struct si_shader_selector
*sel
)
584 enum chip_class chip_class
= sel
->screen
->b
.chip_class
;
585 unsigned gs_max_vert_out
= sel
->gs_max_out_vertices
;
588 if (gs_max_vert_out
<= 128) {
589 cut_mode
= V_028A40_GS_CUT_128
;
590 } else if (gs_max_vert_out
<= 256) {
591 cut_mode
= V_028A40_GS_CUT_256
;
592 } else if (gs_max_vert_out
<= 512) {
593 cut_mode
= V_028A40_GS_CUT_512
;
595 assert(gs_max_vert_out
<= 1024);
596 cut_mode
= V_028A40_GS_CUT_1024
;
599 return S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
600 S_028A40_CUT_MODE(cut_mode
)|
601 S_028A40_ES_WRITE_OPTIMIZE(chip_class
<= VI
) |
602 S_028A40_GS_WRITE_OPTIMIZE(1) |
603 S_028A40_ONCHIP(chip_class
>= GFX9
? 1 : 0);
606 struct gfx9_gs_info
{
607 unsigned es_verts_per_subgroup
;
608 unsigned gs_prims_per_subgroup
;
609 unsigned gs_inst_prims_in_subgroup
;
610 unsigned max_prims_per_subgroup
;
614 static void gfx9_get_gs_info(struct si_shader_selector
*es
,
615 struct si_shader_selector
*gs
,
616 struct gfx9_gs_info
*out
)
618 unsigned gs_num_invocations
= MAX2(gs
->gs_num_invocations
, 1);
619 unsigned input_prim
= gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
620 bool uses_adjacency
= input_prim
>= PIPE_PRIM_LINES_ADJACENCY
&&
621 input_prim
<= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
;
623 /* All these are in dwords: */
624 /* We can't allow using the whole LDS, because GS waves compete with
625 * other shader stages for LDS space. */
626 const unsigned max_lds_size
= 8 * 1024;
627 const unsigned esgs_itemsize
= es
->esgs_itemsize
/ 4;
628 unsigned esgs_lds_size
;
630 /* All these are per subgroup: */
631 const unsigned max_out_prims
= 32 * 1024;
632 const unsigned max_es_verts
= 255;
633 const unsigned ideal_gs_prims
= 64;
634 unsigned max_gs_prims
, gs_prims
;
635 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
637 assert(gs_num_invocations
<= 32); /* GL maximum */
639 if (uses_adjacency
|| gs_num_invocations
> 1)
640 max_gs_prims
= 127 / gs_num_invocations
;
644 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
645 * Make sure we don't go over the maximum value.
647 max_gs_prims
= MIN2(max_gs_prims
,
649 (gs
->gs_max_out_vertices
* gs_num_invocations
));
650 assert(max_gs_prims
> 0);
652 /* If the primitive has adjacency, halve the number of vertices
653 * that will be reused in multiple primitives.
655 min_es_verts
= gs
->gs_input_verts_per_prim
/ (uses_adjacency
? 2 : 1);
657 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
658 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
660 /* Compute ESGS LDS size based on the worst case number of ES vertices
661 * needed to create the target number of GS prims per subgroup.
663 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
665 /* If total LDS usage is too big, refactor partitions based on ratio
666 * of ESGS item sizes.
668 if (esgs_lds_size
> max_lds_size
) {
669 /* Our target GS Prims Per Subgroup was too large. Calculate
670 * the maximum number of GS Prims Per Subgroup that will fit
671 * into LDS, capped by the maximum that the hardware can support.
673 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
675 assert(gs_prims
> 0);
676 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
679 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
680 assert(esgs_lds_size
<= max_lds_size
);
683 /* Now calculate remaining ESGS information. */
685 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
687 es_verts
= max_es_verts
;
689 /* Vertices for adjacency primitives are not always reused, so restore
690 * it for ES_VERTS_PER_SUBGRP.
692 min_es_verts
= gs
->gs_input_verts_per_prim
;
694 /* For normal primitives, the VGT only checks if they are past the ES
695 * verts per subgroup after allocating a full GS primitive and if they
696 * are, kick off a new subgroup. But if those additional ES verts are
697 * unique (e.g. not reused) we need to make sure there is enough LDS
698 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
700 es_verts
-= min_es_verts
- 1;
702 out
->es_verts_per_subgroup
= es_verts
;
703 out
->gs_prims_per_subgroup
= gs_prims
;
704 out
->gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
705 out
->max_prims_per_subgroup
= out
->gs_inst_prims_in_subgroup
*
706 gs
->gs_max_out_vertices
;
707 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
709 assert(out
->max_prims_per_subgroup
<= max_out_prims
);
712 static void si_shader_gs(struct si_screen
*sscreen
, struct si_shader
*shader
)
714 struct si_shader_selector
*sel
= shader
->selector
;
715 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
716 unsigned gs_num_invocations
= sel
->gs_num_invocations
;
717 struct si_pm4_state
*pm4
;
719 unsigned max_stream
= sel
->max_gs_stream
;
722 pm4
= si_get_shader_pm4_state(shader
);
726 offset
= num_components
[0] * sel
->gs_max_out_vertices
;
727 si_pm4_set_reg(pm4
, R_028A60_VGT_GSVS_RING_OFFSET_1
, offset
);
729 offset
+= num_components
[1] * sel
->gs_max_out_vertices
;
730 si_pm4_set_reg(pm4
, R_028A64_VGT_GSVS_RING_OFFSET_2
, offset
);
732 offset
+= num_components
[2] * sel
->gs_max_out_vertices
;
733 si_pm4_set_reg(pm4
, R_028A68_VGT_GSVS_RING_OFFSET_3
, offset
);
735 offset
+= num_components
[3] * sel
->gs_max_out_vertices
;
736 si_pm4_set_reg(pm4
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
738 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
739 assert(offset
< (1 << 15));
741 si_pm4_set_reg(pm4
, R_028B38_VGT_GS_MAX_VERT_OUT
, sel
->gs_max_out_vertices
);
743 si_pm4_set_reg(pm4
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, num_components
[0]);
744 si_pm4_set_reg(pm4
, R_028B60_VGT_GS_VERT_ITEMSIZE_1
, (max_stream
>= 1) ? num_components
[1] : 0);
745 si_pm4_set_reg(pm4
, R_028B64_VGT_GS_VERT_ITEMSIZE_2
, (max_stream
>= 2) ? num_components
[2] : 0);
746 si_pm4_set_reg(pm4
, R_028B68_VGT_GS_VERT_ITEMSIZE_3
, (max_stream
>= 3) ? num_components
[3] : 0);
748 si_pm4_set_reg(pm4
, R_028B90_VGT_GS_INSTANCE_CNT
,
749 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
750 S_028B90_ENABLE(gs_num_invocations
> 0));
752 va
= shader
->bo
->gpu_address
;
753 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
755 if (sscreen
->b
.chip_class
>= GFX9
) {
756 unsigned input_prim
= sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
757 unsigned es_type
= shader
->key
.part
.gs
.es
->type
;
758 unsigned es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
759 struct gfx9_gs_info gs_info
;
761 if (es_type
== PIPE_SHADER_VERTEX
)
762 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
763 es_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
764 else if (es_type
== PIPE_SHADER_TESS_EVAL
)
765 es_vgpr_comp_cnt
= shader
->key
.part
.gs
.es
->info
.uses_primid
? 3 : 2;
767 unreachable("invalid shader selector type");
769 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
770 * VGPR[0:4] are always loaded.
772 if (sel
->info
.uses_invocationid
)
773 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
774 else if (sel
->info
.uses_primid
)
775 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
776 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
777 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
779 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
781 gfx9_get_gs_info(shader
->key
.part
.gs
.es
, sel
, &gs_info
);
783 si_pm4_set_reg(pm4
, R_00B210_SPI_SHADER_PGM_LO_ES
, va
>> 8);
784 si_pm4_set_reg(pm4
, R_00B214_SPI_SHADER_PGM_HI_ES
, va
>> 40);
786 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
787 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
788 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
789 S_00B228_DX10_CLAMP(1) |
790 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
791 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
));
792 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
793 S_00B22C_USER_SGPR(GFX9_GS_NUM_USER_SGPR
) |
794 S_00B22C_USER_SGPR_MSB(GFX9_GS_NUM_USER_SGPR
>> 5) |
795 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
796 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
797 S_00B22C_LDS_SIZE(gs_info
.lds_size
) |
798 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
800 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
801 S_028A44_ES_VERTS_PER_SUBGRP(gs_info
.es_verts_per_subgroup
) |
802 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info
.gs_prims_per_subgroup
) |
803 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info
.gs_inst_prims_in_subgroup
));
804 si_pm4_set_reg(pm4
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
805 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info
.max_prims_per_subgroup
));
806 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
807 shader
->key
.part
.gs
.es
->esgs_itemsize
/ 4);
809 if (es_type
== PIPE_SHADER_TESS_EVAL
)
810 si_set_tesseval_regs(sscreen
, shader
->key
.part
.gs
.es
, pm4
);
812 polaris_set_vgt_vertex_reuse(sscreen
, shader
->key
.part
.gs
.es
,
815 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
816 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, va
>> 40);
818 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
819 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
820 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
821 S_00B228_DX10_CLAMP(1) |
822 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
823 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
824 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR
) |
825 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
830 * Compute the state for \p shader, which will run as a vertex shader on the
833 * If \p gs is non-NULL, it points to the geometry shader for which this shader
834 * is the copy shader.
836 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
837 struct si_shader_selector
*gs
)
839 struct si_pm4_state
*pm4
;
840 unsigned num_user_sgprs
;
841 unsigned nparams
, vgpr_comp_cnt
;
844 unsigned window_space
=
845 shader
->selector
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
846 bool enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| shader
->selector
->info
.uses_primid
;
848 pm4
= si_get_shader_pm4_state(shader
);
852 /* We always write VGT_GS_MODE in the VS state, because every switch
853 * between different shader pipelines involving a different GS or no
854 * GS at all involves a switch of the VS (different GS use different
855 * copy shaders). On the other hand, when the API switches from a GS to
856 * no GS and then back to the same GS used originally, the GS state is
862 /* PrimID needs GS scenario A.
863 * GFX9 also needs it when ViewportIndex is enabled.
865 if (enable_prim_id
||
866 (sscreen
->b
.chip_class
>= GFX9
&&
867 shader
->selector
->info
.writes_viewport_index
))
868 mode
= V_028A40_GS_SCENARIO_A
;
870 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, S_028A40_MODE(mode
));
871 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, enable_prim_id
);
873 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, si_vgt_gs_mode(gs
));
874 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
877 va
= shader
->bo
->gpu_address
;
878 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
881 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
882 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
883 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
884 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
885 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
886 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
888 vgpr_comp_cnt
= enable_prim_id
? 2 : (shader
->info
.uses_instanceid
? 1 : 0);
889 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
890 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
891 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
892 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
894 unreachable("invalid shader selector type");
896 /* VS is required to export at least one param. */
897 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
898 si_pm4_set_reg(pm4
, R_0286C4_SPI_VS_OUT_CONFIG
,
899 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
901 si_pm4_set_reg(pm4
, R_02870C_SPI_SHADER_POS_FORMAT
,
902 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
903 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
904 V_02870C_SPI_SHADER_4COMP
:
905 V_02870C_SPI_SHADER_NONE
) |
906 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
907 V_02870C_SPI_SHADER_4COMP
:
908 V_02870C_SPI_SHADER_NONE
) |
909 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
910 V_02870C_SPI_SHADER_4COMP
:
911 V_02870C_SPI_SHADER_NONE
));
913 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
915 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
916 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, va
>> 40);
917 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
918 S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
919 S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
920 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
921 S_00B128_DX10_CLAMP(1) |
922 S_00B128_FLOAT_MODE(shader
->config
.float_mode
));
923 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
924 S_00B12C_USER_SGPR(num_user_sgprs
) |
925 S_00B12C_OC_LDS_EN(oc_lds_en
) |
926 S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
927 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
928 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
929 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
930 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
) |
931 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
933 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
934 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
936 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
937 S_028818_VTX_W0_FMT(1) |
938 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
939 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
940 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
942 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
943 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
945 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
948 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
950 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
951 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
952 !!(info
->colors_read
& 0xf0);
953 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
954 (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
956 assert(num_interp
<= 32);
957 return MIN2(num_interp
, 32);
960 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
962 unsigned value
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
963 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
965 /* If the i-th target format is set, all previous target formats must
966 * be non-zero to avoid hangs.
968 for (i
= 0; i
< num_targets
; i
++)
969 if (!(value
& (0xf << (i
* 4))))
970 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
975 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format
)
977 unsigned i
, cb_shader_mask
= 0;
979 for (i
= 0; i
< 8; i
++) {
980 switch ((spi_shader_col_format
>> (i
* 4)) & 0xf) {
981 case V_028714_SPI_SHADER_ZERO
:
983 case V_028714_SPI_SHADER_32_R
:
984 cb_shader_mask
|= 0x1 << (i
* 4);
986 case V_028714_SPI_SHADER_32_GR
:
987 cb_shader_mask
|= 0x3 << (i
* 4);
989 case V_028714_SPI_SHADER_32_AR
:
990 cb_shader_mask
|= 0x9 << (i
* 4);
992 case V_028714_SPI_SHADER_FP16_ABGR
:
993 case V_028714_SPI_SHADER_UNORM16_ABGR
:
994 case V_028714_SPI_SHADER_SNORM16_ABGR
:
995 case V_028714_SPI_SHADER_UINT16_ABGR
:
996 case V_028714_SPI_SHADER_SINT16_ABGR
:
997 case V_028714_SPI_SHADER_32_ABGR
:
998 cb_shader_mask
|= 0xf << (i
* 4);
1004 return cb_shader_mask
;
1007 static void si_shader_ps(struct si_shader
*shader
)
1009 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1010 struct si_pm4_state
*pm4
;
1011 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
1012 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
1014 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
1016 /* we need to enable at least one of them, otherwise we hang the GPU */
1017 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1018 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1019 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1020 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
1021 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
1022 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1023 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
1024 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
1025 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1026 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
1027 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1028 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1029 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1030 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
1032 /* Validate interpolation optimization flags (read as implications). */
1033 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1034 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1035 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1036 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1037 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1038 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1039 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
1040 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
1041 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1042 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
1043 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
1044 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1045 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
1046 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1047 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1048 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
1049 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1050 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1052 /* Validate cases when the optimizations are off (read as implications). */
1053 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1054 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1055 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
1056 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1057 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1058 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
1060 pm4
= si_get_shader_pm4_state(shader
);
1064 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1066 * 0 -> Position = pixel center
1067 * 1 -> Position = pixel centroid
1068 * 2 -> Position = at sample position
1070 * From GLSL 4.5 specification, section 7.1:
1071 * "The variable gl_FragCoord is available as an input variable from
1072 * within fragment shaders and it holds the window relative coordinates
1073 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1074 * value can be for any location within the pixel, or one of the
1075 * fragment samples. The use of centroid does not further restrict
1076 * this value to be inside the current primitive."
1078 * Meaning that centroid has no effect and we can return anything within
1079 * the pixel. Thus, return the value at sample position, because that's
1080 * the most accurate one shaders can get.
1082 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1084 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
1085 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
1086 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
1088 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
1089 cb_shader_mask
= si_get_cb_shader_mask(spi_shader_col_format
);
1091 /* Ensure that some export memory is always allocated, for two reasons:
1093 * 1) Correctness: The hardware ignores the EXEC mask if no export
1094 * memory is allocated, so KILL and alpha test do not work correctly
1096 * 2) Performance: Every shader needs at least a NULL export, even when
1097 * it writes no color/depth output. The NULL export instruction
1098 * stalls without this setting.
1100 * Don't add this to CB_SHADER_MASK.
1102 if (!spi_shader_col_format
&&
1103 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
1104 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
1106 si_pm4_set_reg(pm4
, R_0286CC_SPI_PS_INPUT_ENA
, input_ena
);
1107 si_pm4_set_reg(pm4
, R_0286D0_SPI_PS_INPUT_ADDR
,
1108 shader
->config
.spi_ps_input_addr
);
1110 /* Set interpolation controls. */
1111 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
));
1113 /* Set registers. */
1114 si_pm4_set_reg(pm4
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
1115 si_pm4_set_reg(pm4
, R_0286D8_SPI_PS_IN_CONTROL
, spi_ps_in_control
);
1117 si_pm4_set_reg(pm4
, R_028710_SPI_SHADER_Z_FORMAT
,
1118 si_get_spi_shader_z_format(info
->writes_z
,
1119 info
->writes_stencil
,
1120 info
->writes_samplemask
));
1122 si_pm4_set_reg(pm4
, R_028714_SPI_SHADER_COL_FORMAT
, spi_shader_col_format
);
1123 si_pm4_set_reg(pm4
, R_02823C_CB_SHADER_MASK
, cb_shader_mask
);
1125 va
= shader
->bo
->gpu_address
;
1126 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1127 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
1128 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, va
>> 40);
1130 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
,
1131 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1132 S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
1133 S_00B028_DX10_CLAMP(1) |
1134 S_00B028_FLOAT_MODE(shader
->config
.float_mode
));
1135 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
1136 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
1137 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
1138 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1141 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
1142 struct si_shader
*shader
)
1144 switch (shader
->selector
->type
) {
1145 case PIPE_SHADER_VERTEX
:
1146 if (shader
->key
.as_ls
)
1147 si_shader_ls(sscreen
, shader
);
1148 else if (shader
->key
.as_es
)
1149 si_shader_es(sscreen
, shader
);
1151 si_shader_vs(sscreen
, shader
, NULL
);
1153 case PIPE_SHADER_TESS_CTRL
:
1154 si_shader_hs(sscreen
, shader
);
1156 case PIPE_SHADER_TESS_EVAL
:
1157 if (shader
->key
.as_es
)
1158 si_shader_es(sscreen
, shader
);
1160 si_shader_vs(sscreen
, shader
, NULL
);
1162 case PIPE_SHADER_GEOMETRY
:
1163 si_shader_gs(sscreen
, shader
);
1165 case PIPE_SHADER_FRAGMENT
:
1166 si_shader_ps(shader
);
1173 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
1175 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1176 if (sctx
->queued
.named
.dsa
)
1177 return sctx
->queued
.named
.dsa
->alpha_func
;
1179 return PIPE_FUNC_ALWAYS
;
1182 static void si_shader_selector_key_vs(struct si_context
*sctx
,
1183 struct si_shader_selector
*vs
,
1184 struct si_shader_key
*key
,
1185 struct si_vs_prolog_bits
*prolog_key
)
1187 if (!sctx
->vertex_elements
)
1190 unsigned count
= MIN2(vs
->info
.num_inputs
,
1191 sctx
->vertex_elements
->count
);
1192 for (unsigned i
= 0; i
< count
; ++i
) {
1193 prolog_key
->instance_divisors
[i
] =
1194 sctx
->vertex_elements
->elements
[i
].instance_divisor
;
1197 memcpy(key
->mono
.vs_fix_fetch
, sctx
->vertex_elements
->fix_fetch
, count
);
1200 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
,
1201 struct si_shader_selector
*vs
,
1202 struct si_shader_key
*key
)
1204 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1206 key
->opt
.hw_vs
.clip_disable
=
1207 sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
1208 (vs
->info
.clipdist_writemask
||
1209 vs
->info
.writes_clipvertex
) &&
1210 !vs
->info
.culldist_writemask
;
1212 /* Find out if PS is disabled. */
1213 bool ps_disabled
= true;
1215 bool ps_modifies_zs
= ps
->info
.uses_kill
||
1216 ps
->info
.writes_z
||
1217 ps
->info
.writes_stencil
||
1218 ps
->info
.writes_samplemask
||
1219 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
1221 unsigned ps_colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
&
1222 sctx
->queued
.named
.blend
->cb_target_mask
;
1223 if (!ps
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
])
1224 ps_colormask
&= ps
->colors_written_4bit
;
1226 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
1229 !ps
->info
.writes_memory
);
1232 /* Find out which VS outputs aren't used by the PS. */
1233 uint64_t outputs_written
= vs
->outputs_written
;
1234 uint64_t inputs_read
= 0;
1236 /* ignore POSITION, PSIZE */
1237 outputs_written
&= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION
, 0) |
1238 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE
, 0))));
1241 inputs_read
= ps
->inputs_read
;
1244 uint64_t linked
= outputs_written
& inputs_read
;
1246 key
->opt
.hw_vs
.kill_outputs
= ~linked
& outputs_written
;
1249 /* Compute the key for the hw shader variant */
1250 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
1251 struct si_shader_selector
*sel
,
1252 struct si_shader_key
*key
)
1254 struct si_context
*sctx
= (struct si_context
*)ctx
;
1256 memset(key
, 0, sizeof(*key
));
1258 switch (sel
->type
) {
1259 case PIPE_SHADER_VERTEX
:
1260 si_shader_selector_key_vs(sctx
, sel
, key
, &key
->part
.vs
.prolog
);
1262 if (sctx
->tes_shader
.cso
)
1264 else if (sctx
->gs_shader
.cso
)
1267 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1269 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1270 key
->mono
.u
.vs_export_prim_id
= 1;
1273 case PIPE_SHADER_TESS_CTRL
:
1274 if (sctx
->b
.chip_class
>= GFX9
) {
1275 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1276 key
, &key
->part
.tcs
.ls_prolog
);
1277 key
->part
.tcs
.ls
= sctx
->vs_shader
.cso
;
1280 key
->part
.tcs
.epilog
.prim_mode
=
1281 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1282 key
->part
.tcs
.epilog
.tes_reads_tess_factors
=
1283 sctx
->tes_shader
.cso
->info
.reads_tess_factors
;
1285 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
1286 key
->mono
.u
.ff_tcs_inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
1288 case PIPE_SHADER_TESS_EVAL
:
1289 if (sctx
->gs_shader
.cso
)
1292 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1294 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1295 key
->mono
.u
.vs_export_prim_id
= 1;
1298 case PIPE_SHADER_GEOMETRY
:
1299 if (sctx
->b
.chip_class
>= GFX9
) {
1300 if (sctx
->tes_shader
.cso
) {
1301 key
->part
.gs
.es
= sctx
->tes_shader
.cso
;
1303 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1304 key
, &key
->part
.gs
.vs_prolog
);
1305 key
->part
.gs
.es
= sctx
->vs_shader
.cso
;
1308 /* Merged ES-GS can have unbalanced wave usage.
1310 * ES threads are per-vertex, while GS threads are
1311 * per-primitive. So without any amplification, there
1312 * are fewer GS threads than ES threads, which can result
1313 * in empty (no-op) GS waves. With too much amplification,
1314 * there are more GS threads than ES threads, which
1315 * can result in empty (no-op) ES waves.
1317 * Non-monolithic shaders are implemented by setting EXEC
1318 * at the beginning of shader parts, and don't jump to
1319 * the end if EXEC is 0.
1321 * Monolithic shaders use conditional blocks, so they can
1322 * jump and skip empty waves of ES or GS. So set this to
1323 * always use optimized variants, which are monolithic.
1325 key
->opt
.prefer_mono
= 1;
1327 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
1329 case PIPE_SHADER_FRAGMENT
: {
1330 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1331 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1333 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
1334 sel
->info
.colors_written
== 0x1)
1335 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
1338 /* Select the shader color format based on whether
1339 * blending or alpha are needed.
1341 key
->part
.ps
.epilog
.spi_shader_col_format
=
1342 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1343 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
1344 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1345 sctx
->framebuffer
.spi_shader_col_format_blend
) |
1346 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1347 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
1348 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1349 sctx
->framebuffer
.spi_shader_col_format
);
1351 /* The output for dual source blending should have
1352 * the same format as the first output.
1354 if (blend
->dual_src_blend
)
1355 key
->part
.ps
.epilog
.spi_shader_col_format
|=
1356 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
1358 key
->part
.ps
.epilog
.spi_shader_col_format
= sctx
->framebuffer
.spi_shader_col_format
;
1360 /* If alpha-to-coverage is enabled, we have to export alpha
1361 * even if there is no color buffer.
1363 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) &&
1364 blend
&& blend
->alpha_to_coverage
)
1365 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
1367 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1368 * to the range supported by the type if a channel has less
1369 * than 16 bits and the export format is 16_ABGR.
1371 if (sctx
->b
.chip_class
<= CIK
&& sctx
->b
.family
!= CHIP_HAWAII
) {
1372 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
1373 key
->part
.ps
.epilog
.color_is_int10
= sctx
->framebuffer
.color_is_int10
;
1376 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1377 if (!key
->part
.ps
.epilog
.last_cbuf
) {
1378 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
1379 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
1380 key
->part
.ps
.epilog
.color_is_int10
&= sel
->info
.colors_written
;
1384 bool is_poly
= (sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES
&&
1385 sctx
->current_rast_prim
<= PIPE_PRIM_POLYGON
) ||
1386 sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES_ADJACENCY
;
1387 bool is_line
= !is_poly
&& sctx
->current_rast_prim
!= PIPE_PRIM_POINTS
;
1389 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
1390 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
1392 if (sctx
->queued
.named
.blend
) {
1393 key
->part
.ps
.epilog
.alpha_to_one
= sctx
->queued
.named
.blend
->alpha_to_one
&&
1394 rs
->multisample_enable
;
1397 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
1398 key
->part
.ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
1399 (is_line
&& rs
->line_smooth
)) &&
1400 sctx
->framebuffer
.nr_samples
<= 1;
1401 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
1403 if (rs
->force_persample_interp
&&
1404 rs
->multisample_enable
&&
1405 sctx
->framebuffer
.nr_samples
> 1 &&
1406 sctx
->ps_iter_samples
> 1) {
1407 key
->part
.ps
.prolog
.force_persp_sample_interp
=
1408 sel
->info
.uses_persp_center
||
1409 sel
->info
.uses_persp_centroid
;
1411 key
->part
.ps
.prolog
.force_linear_sample_interp
=
1412 sel
->info
.uses_linear_center
||
1413 sel
->info
.uses_linear_centroid
;
1414 } else if (rs
->multisample_enable
&&
1415 sctx
->framebuffer
.nr_samples
> 1) {
1416 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
1417 sel
->info
.uses_persp_center
&&
1418 sel
->info
.uses_persp_centroid
;
1419 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
1420 sel
->info
.uses_linear_center
&&
1421 sel
->info
.uses_linear_centroid
;
1423 /* Make sure SPI doesn't compute more than 1 pair
1424 * of (i,j), which is the optimization here. */
1425 key
->part
.ps
.prolog
.force_persp_center_interp
=
1426 sel
->info
.uses_persp_center
+
1427 sel
->info
.uses_persp_centroid
+
1428 sel
->info
.uses_persp_sample
> 1;
1430 key
->part
.ps
.prolog
.force_linear_center_interp
=
1431 sel
->info
.uses_linear_center
+
1432 sel
->info
.uses_linear_centroid
+
1433 sel
->info
.uses_linear_sample
> 1;
1437 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
1444 if (unlikely(sctx
->screen
->b
.debug_flags
& DBG_NO_OPT_VARIANT
))
1445 memset(&key
->opt
, 0, sizeof(key
->opt
));
1448 static void si_build_shader_variant(void *job
, int thread_index
)
1450 struct si_shader
*shader
= (struct si_shader
*)job
;
1451 struct si_shader_selector
*sel
= shader
->selector
;
1452 struct si_screen
*sscreen
= sel
->screen
;
1453 LLVMTargetMachineRef tm
;
1454 struct pipe_debug_callback
*debug
= &shader
->compiler_ctx_state
.debug
;
1457 if (thread_index
>= 0) {
1458 assert(thread_index
< ARRAY_SIZE(sscreen
->tm_low_priority
));
1459 tm
= sscreen
->tm_low_priority
[thread_index
];
1463 tm
= shader
->compiler_ctx_state
.tm
;
1466 r
= si_shader_create(sscreen
, tm
, shader
, debug
);
1468 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1470 shader
->compilation_failed
= true;
1474 if (shader
->compiler_ctx_state
.is_debug_context
) {
1475 FILE *f
= open_memstream(&shader
->shader_log
,
1476 &shader
->shader_log_size
);
1478 si_shader_dump(sscreen
, shader
, NULL
, sel
->type
, f
, false);
1483 si_shader_init_pm4_state(sscreen
, shader
);
1486 static const struct si_shader_key zeroed
;
1488 static bool si_check_missing_main_part(struct si_screen
*sscreen
,
1489 struct si_shader_selector
*sel
,
1490 struct si_compiler_ctx_state
*compiler_state
,
1491 struct si_shader_key
*key
)
1493 struct si_shader
**mainp
= si_get_main_shader_part(sel
, key
);
1496 struct si_shader
*main_part
= CALLOC_STRUCT(si_shader
);
1501 main_part
->selector
= sel
;
1502 main_part
->key
.as_es
= key
->as_es
;
1503 main_part
->key
.as_ls
= key
->as_ls
;
1505 if (si_compile_tgsi_shader(sscreen
, compiler_state
->tm
,
1507 &compiler_state
->debug
) != 0) {
1516 static void si_destroy_shader_selector(struct si_context
*sctx
,
1517 struct si_shader_selector
*sel
);
1519 static void si_shader_selector_reference(struct si_context
*sctx
,
1520 struct si_shader_selector
**dst
,
1521 struct si_shader_selector
*src
)
1523 if (pipe_reference(&(*dst
)->reference
, &src
->reference
))
1524 si_destroy_shader_selector(sctx
, *dst
);
1529 /* Select the hw shader variant depending on the current state. */
1530 static int si_shader_select_with_key(struct si_screen
*sscreen
,
1531 struct si_shader_ctx_state
*state
,
1532 struct si_compiler_ctx_state
*compiler_state
,
1533 struct si_shader_key
*key
,
1536 struct si_shader_selector
*sel
= state
->cso
;
1537 struct si_shader_selector
*previous_stage_sel
= NULL
;
1538 struct si_shader
*current
= state
->current
;
1539 struct si_shader
*iter
, *shader
= NULL
;
1542 /* Check if we don't need to change anything.
1543 * This path is also used for most shaders that don't need multiple
1544 * variants, it will cost just a computation of the key and this
1546 if (likely(current
&&
1547 memcmp(¤t
->key
, key
, sizeof(*key
)) == 0 &&
1548 (!current
->is_optimized
||
1549 util_queue_fence_is_signalled(¤t
->optimized_ready
))))
1550 return current
->compilation_failed
? -1 : 0;
1552 /* This must be done before the mutex is locked, because async GS
1553 * compilation calls this function too, and therefore must enter
1556 * Only wait if we are in a draw call. Don't wait if we are
1557 * in a compiler thread.
1559 if (thread_index
< 0)
1560 util_queue_fence_wait(&sel
->ready
);
1562 mtx_lock(&sel
->mutex
);
1564 /* Find the shader variant. */
1565 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
1566 /* Don't check the "current" shader. We checked it above. */
1567 if (current
!= iter
&&
1568 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
1569 /* If it's an optimized shader and its compilation has
1570 * been started but isn't done, use the unoptimized
1571 * shader so as not to cause a stall due to compilation.
1573 if (iter
->is_optimized
&&
1574 !util_queue_fence_is_signalled(&iter
->optimized_ready
)) {
1575 memset(&key
->opt
, 0, sizeof(key
->opt
));
1576 mtx_unlock(&sel
->mutex
);
1580 if (iter
->compilation_failed
) {
1581 mtx_unlock(&sel
->mutex
);
1582 return -1; /* skip the draw call */
1585 state
->current
= iter
;
1586 mtx_unlock(&sel
->mutex
);
1591 /* Build a new shader. */
1592 shader
= CALLOC_STRUCT(si_shader
);
1594 mtx_unlock(&sel
->mutex
);
1597 shader
->selector
= sel
;
1599 shader
->compiler_ctx_state
= *compiler_state
;
1601 /* If this is a merged shader, get the first shader's selector. */
1602 if (sscreen
->b
.chip_class
>= GFX9
) {
1603 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
1604 previous_stage_sel
= key
->part
.tcs
.ls
;
1605 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
1606 previous_stage_sel
= key
->part
.gs
.es
;
1608 /* We need to wait for the previous shader. */
1609 if (previous_stage_sel
&& thread_index
< 0)
1610 util_queue_fence_wait(&previous_stage_sel
->ready
);
1613 /* Compile the main shader part if it doesn't exist. This can happen
1614 * if the initial guess was wrong. */
1615 bool is_pure_monolithic
=
1616 sscreen
->use_monolithic_shaders
||
1617 memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
1619 if (!is_pure_monolithic
) {
1622 /* Make sure the main shader part is present. This is needed
1623 * for shaders that can be compiled as VS, LS, or ES, and only
1624 * one of them is compiled at creation.
1626 * For merged shaders, check that the starting shader's main
1629 if (previous_stage_sel
) {
1630 struct si_shader_key shader1_key
= zeroed
;
1632 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
1633 shader1_key
.as_ls
= 1;
1634 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
1635 shader1_key
.as_es
= 1;
1639 mtx_lock(&previous_stage_sel
->mutex
);
1640 ok
= si_check_missing_main_part(sscreen
,
1642 compiler_state
, &shader1_key
);
1643 mtx_unlock(&previous_stage_sel
->mutex
);
1645 ok
= si_check_missing_main_part(sscreen
, sel
,
1646 compiler_state
, key
);
1650 mtx_unlock(&sel
->mutex
);
1651 return -ENOMEM
; /* skip the draw call */
1655 /* Keep the reference to the 1st shader of merged shaders, so that
1656 * Gallium can't destroy it before we destroy the 2nd shader.
1658 * Set sctx = NULL, because it's unused if we're not releasing
1659 * the shader, and we don't have any sctx here.
1661 si_shader_selector_reference(NULL
, &shader
->previous_stage_sel
,
1662 previous_stage_sel
);
1664 /* Monolithic-only shaders don't make a distinction between optimized
1665 * and unoptimized. */
1666 shader
->is_monolithic
=
1667 is_pure_monolithic
||
1668 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1670 shader
->is_optimized
=
1671 !is_pure_monolithic
&&
1672 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1673 if (shader
->is_optimized
)
1674 util_queue_fence_init(&shader
->optimized_ready
);
1676 if (!sel
->last_variant
) {
1677 sel
->first_variant
= shader
;
1678 sel
->last_variant
= shader
;
1680 sel
->last_variant
->next_variant
= shader
;
1681 sel
->last_variant
= shader
;
1684 /* If it's an optimized shader, compile it asynchronously. */
1685 if (shader
->is_optimized
&&
1686 !is_pure_monolithic
&&
1688 /* Compile it asynchronously. */
1689 util_queue_add_job(&sscreen
->shader_compiler_queue_low_priority
,
1690 shader
, &shader
->optimized_ready
,
1691 si_build_shader_variant
, NULL
);
1693 /* Use the default (unoptimized) shader for now. */
1694 memset(&key
->opt
, 0, sizeof(key
->opt
));
1695 mtx_unlock(&sel
->mutex
);
1699 assert(!shader
->is_optimized
);
1700 si_build_shader_variant(shader
, thread_index
);
1702 if (!shader
->compilation_failed
)
1703 state
->current
= shader
;
1705 mtx_unlock(&sel
->mutex
);
1706 return shader
->compilation_failed
? -1 : 0;
1709 static int si_shader_select(struct pipe_context
*ctx
,
1710 struct si_shader_ctx_state
*state
,
1711 struct si_compiler_ctx_state
*compiler_state
)
1713 struct si_context
*sctx
= (struct si_context
*)ctx
;
1714 struct si_shader_key key
;
1716 si_shader_selector_key(ctx
, state
->cso
, &key
);
1717 return si_shader_select_with_key(sctx
->screen
, state
, compiler_state
,
1721 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
1722 struct si_shader_key
*key
)
1724 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
1726 switch (info
->processor
) {
1727 case PIPE_SHADER_VERTEX
:
1728 switch (next_shader
) {
1729 case PIPE_SHADER_GEOMETRY
:
1732 case PIPE_SHADER_TESS_CTRL
:
1733 case PIPE_SHADER_TESS_EVAL
:
1737 /* If POSITION isn't written, it can't be a HW VS.
1738 * Assume that it's a HW LS. (the next shader is TCS)
1739 * This heuristic is needed for separate shader objects.
1741 if (!info
->writes_position
)
1746 case PIPE_SHADER_TESS_EVAL
:
1747 if (next_shader
== PIPE_SHADER_GEOMETRY
||
1748 !info
->writes_position
)
1755 * Compile the main shader part or the monolithic shader as part of
1756 * si_shader_selector initialization. Since it can be done asynchronously,
1757 * there is no way to report compile failures to applications.
1759 void si_init_shader_selector_async(void *job
, int thread_index
)
1761 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
1762 struct si_screen
*sscreen
= sel
->screen
;
1763 LLVMTargetMachineRef tm
;
1764 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
1767 if (thread_index
>= 0) {
1768 assert(thread_index
< ARRAY_SIZE(sscreen
->tm
));
1769 tm
= sscreen
->tm
[thread_index
];
1773 tm
= sel
->compiler_ctx_state
.tm
;
1776 /* Compile the main shader part for use with a prolog and/or epilog.
1777 * If this fails, the driver will try to compile a monolithic shader
1780 if (!sscreen
->use_monolithic_shaders
) {
1781 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
1785 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
1789 shader
->selector
= sel
;
1790 si_parse_next_shader_property(&sel
->info
, &shader
->key
);
1792 tgsi_binary
= si_get_tgsi_binary(sel
);
1794 /* Try to load the shader from the shader cache. */
1795 mtx_lock(&sscreen
->shader_cache_mutex
);
1798 si_shader_cache_load_shader(sscreen
, tgsi_binary
, shader
)) {
1799 mtx_unlock(&sscreen
->shader_cache_mutex
);
1801 mtx_unlock(&sscreen
->shader_cache_mutex
);
1803 /* Compile the shader if it hasn't been loaded from the cache. */
1804 if (si_compile_tgsi_shader(sscreen
, tm
, shader
, false,
1808 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
1813 mtx_lock(&sscreen
->shader_cache_mutex
);
1814 if (!si_shader_cache_insert_shader(sscreen
, tgsi_binary
, shader
, true))
1816 mtx_unlock(&sscreen
->shader_cache_mutex
);
1820 *si_get_main_shader_part(sel
, &shader
->key
) = shader
;
1822 /* Unset "outputs_written" flags for outputs converted to
1823 * DEFAULT_VAL, so that later inter-shader optimizations don't
1824 * try to eliminate outputs that don't exist in the final
1827 * This is only done if non-monolithic shaders are enabled.
1829 if ((sel
->type
== PIPE_SHADER_VERTEX
||
1830 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
1831 !shader
->key
.as_ls
&&
1832 !shader
->key
.as_es
) {
1835 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
1836 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
1838 if (offset
<= AC_EXP_PARAM_OFFSET_31
)
1841 unsigned name
= sel
->info
.output_semantic_name
[i
];
1842 unsigned index
= sel
->info
.output_semantic_index
[i
];
1846 case TGSI_SEMANTIC_GENERIC
:
1847 /* don't process indices the function can't handle */
1848 if (index
>= SI_MAX_IO_GENERIC
)
1852 id
= si_shader_io_get_unique_index(name
, index
);
1853 sel
->outputs_written
&= ~(1ull << id
);
1855 case TGSI_SEMANTIC_POSITION
: /* ignore these */
1856 case TGSI_SEMANTIC_PSIZE
:
1857 case TGSI_SEMANTIC_CLIPVERTEX
:
1858 case TGSI_SEMANTIC_EDGEFLAG
:
1865 /* Pre-compilation. */
1866 if (sscreen
->b
.debug_flags
& DBG_PRECOMPILE
) {
1867 struct si_shader_ctx_state state
= {sel
};
1868 struct si_shader_key key
;
1870 memset(&key
, 0, sizeof(key
));
1871 si_parse_next_shader_property(&sel
->info
, &key
);
1873 /* Set reasonable defaults, so that the shader key doesn't
1874 * cause any code to be eliminated.
1876 switch (sel
->type
) {
1877 case PIPE_SHADER_TESS_CTRL
:
1878 key
.part
.tcs
.epilog
.prim_mode
= PIPE_PRIM_TRIANGLES
;
1880 case PIPE_SHADER_FRAGMENT
:
1881 key
.part
.ps
.prolog
.bc_optimize_for_persp
=
1882 sel
->info
.uses_persp_center
&&
1883 sel
->info
.uses_persp_centroid
;
1884 key
.part
.ps
.prolog
.bc_optimize_for_linear
=
1885 sel
->info
.uses_linear_center
&&
1886 sel
->info
.uses_linear_centroid
;
1887 key
.part
.ps
.epilog
.alpha_func
= PIPE_FUNC_ALWAYS
;
1888 for (i
= 0; i
< 8; i
++)
1889 if (sel
->info
.colors_written
& (1 << i
))
1890 key
.part
.ps
.epilog
.spi_shader_col_format
|=
1891 V_028710_SPI_SHADER_FP16_ABGR
<< (i
* 4);
1895 if (si_shader_select_with_key(sscreen
, &state
,
1896 &sel
->compiler_ctx_state
, &key
,
1898 fprintf(stderr
, "radeonsi: can't create a monolithic shader\n");
1901 /* The GS copy shader is always pre-compiled. */
1902 if (sel
->type
== PIPE_SHADER_GEOMETRY
) {
1903 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, tm
, sel
, debug
);
1904 if (!sel
->gs_copy_shader
) {
1905 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
1909 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
1913 /* Return descriptor slot usage masks from the given shader info. */
1914 void si_get_active_slot_masks(const struct tgsi_shader_info
*info
,
1915 uint32_t *const_and_shader_buffers
,
1916 uint64_t *samplers_and_images
)
1918 unsigned start
, num_shaderbufs
, num_constbufs
, num_images
, num_samplers
;
1920 num_shaderbufs
= util_last_bit(info
->shader_buffers_declared
);
1921 num_constbufs
= util_last_bit(info
->const_buffers_declared
);
1922 /* two 8-byte images share one 16-byte slot */
1923 num_images
= align(util_last_bit(info
->images_declared
), 2);
1924 num_samplers
= util_last_bit(info
->samplers_declared
);
1926 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
1927 start
= si_get_shaderbuf_slot(num_shaderbufs
- 1);
1928 *const_and_shader_buffers
=
1929 u_bit_consecutive(start
, num_shaderbufs
+ num_constbufs
);
1931 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
1932 start
= si_get_image_slot(num_images
- 1) / 2;
1933 *samplers_and_images
=
1934 u_bit_consecutive64(start
, num_images
/ 2 + num_samplers
);
1937 static void *si_create_shader_selector(struct pipe_context
*ctx
,
1938 const struct pipe_shader_state
*state
)
1940 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
1941 struct si_context
*sctx
= (struct si_context
*)ctx
;
1942 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
1948 pipe_reference_init(&sel
->reference
, 1);
1949 sel
->screen
= sscreen
;
1950 sel
->compiler_ctx_state
.tm
= sctx
->tm
;
1951 sel
->compiler_ctx_state
.debug
= sctx
->b
.debug
;
1952 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
1953 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
1959 sel
->so
= state
->stream_output
;
1960 tgsi_scan_shader(state
->tokens
, &sel
->info
);
1961 sel
->type
= sel
->info
.processor
;
1962 p_atomic_inc(&sscreen
->b
.num_shaders_created
);
1963 si_get_active_slot_masks(&sel
->info
,
1964 &sel
->active_const_and_shader_buffers
,
1965 &sel
->active_samplers_and_images
);
1967 /* Record which streamout buffers are enabled. */
1968 for (i
= 0; i
< sel
->so
.num_outputs
; i
++) {
1969 sel
->enabled_streamout_buffer_mask
|=
1970 (1 << sel
->so
.output
[i
].output_buffer
) <<
1971 (sel
->so
.output
[i
].stream
* 4);
1974 /* The prolog is a no-op if there are no inputs. */
1975 sel
->vs_needs_prolog
= sel
->type
== PIPE_SHADER_VERTEX
&&
1976 sel
->info
.num_inputs
;
1978 /* Set which opcode uses which (i,j) pair. */
1979 if (sel
->info
.uses_persp_opcode_interp_centroid
)
1980 sel
->info
.uses_persp_centroid
= true;
1982 if (sel
->info
.uses_linear_opcode_interp_centroid
)
1983 sel
->info
.uses_linear_centroid
= true;
1985 if (sel
->info
.uses_persp_opcode_interp_offset
||
1986 sel
->info
.uses_persp_opcode_interp_sample
)
1987 sel
->info
.uses_persp_center
= true;
1989 if (sel
->info
.uses_linear_opcode_interp_offset
||
1990 sel
->info
.uses_linear_opcode_interp_sample
)
1991 sel
->info
.uses_linear_center
= true;
1993 switch (sel
->type
) {
1994 case PIPE_SHADER_GEOMETRY
:
1995 sel
->gs_output_prim
=
1996 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
1997 sel
->gs_max_out_vertices
=
1998 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
1999 sel
->gs_num_invocations
=
2000 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
2001 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
2002 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
2003 sel
->gs_max_out_vertices
;
2005 sel
->max_gs_stream
= 0;
2006 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
2007 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
2008 sel
->so
.output
[i
].stream
);
2010 sel
->gs_input_verts_per_prim
=
2011 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
2014 case PIPE_SHADER_TESS_CTRL
:
2015 /* Always reserve space for these. */
2016 sel
->patch_outputs_written
|=
2017 (1llu << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0)) |
2018 (1llu << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0));
2020 case PIPE_SHADER_VERTEX
:
2021 case PIPE_SHADER_TESS_EVAL
:
2022 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2023 unsigned name
= sel
->info
.output_semantic_name
[i
];
2024 unsigned index
= sel
->info
.output_semantic_index
[i
];
2027 case TGSI_SEMANTIC_TESSINNER
:
2028 case TGSI_SEMANTIC_TESSOUTER
:
2029 case TGSI_SEMANTIC_PATCH
:
2030 sel
->patch_outputs_written
|=
2031 1llu << si_shader_io_get_unique_index_patch(name
, index
);
2034 case TGSI_SEMANTIC_GENERIC
:
2035 /* don't process indices the function can't handle */
2036 if (index
>= SI_MAX_IO_GENERIC
)
2040 sel
->outputs_written
|=
2041 1llu << si_shader_io_get_unique_index(name
, index
);
2043 case TGSI_SEMANTIC_CLIPVERTEX
: /* ignore these */
2044 case TGSI_SEMANTIC_EDGEFLAG
:
2048 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
2050 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2051 * conflicts, i.e. each vertex will start at a different bank.
2053 if (sctx
->b
.chip_class
>= GFX9
)
2054 sel
->esgs_itemsize
+= 4;
2057 case PIPE_SHADER_FRAGMENT
:
2058 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2059 unsigned name
= sel
->info
.input_semantic_name
[i
];
2060 unsigned index
= sel
->info
.input_semantic_index
[i
];
2063 case TGSI_SEMANTIC_GENERIC
:
2064 /* don't process indices the function can't handle */
2065 if (index
>= SI_MAX_IO_GENERIC
)
2070 1llu << si_shader_io_get_unique_index(name
, index
);
2072 case TGSI_SEMANTIC_PCOORD
: /* ignore this */
2077 for (i
= 0; i
< 8; i
++)
2078 if (sel
->info
.colors_written
& (1 << i
))
2079 sel
->colors_written_4bit
|= 0xf << (4 * i
);
2081 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2082 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
2083 int index
= sel
->info
.input_semantic_index
[i
];
2084 sel
->color_attr_index
[index
] = i
;
2090 /* PA_CL_VS_OUT_CNTL */
2092 sel
->info
.writes_psize
|| sel
->info
.writes_edgeflag
||
2093 sel
->info
.writes_layer
|| sel
->info
.writes_viewport_index
;
2094 sel
->pa_cl_vs_out_cntl
=
2095 S_02881C_USE_VTX_POINT_SIZE(sel
->info
.writes_psize
) |
2096 S_02881C_USE_VTX_EDGE_FLAG(sel
->info
.writes_edgeflag
) |
2097 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel
->info
.writes_layer
) |
2098 S_02881C_USE_VTX_VIEWPORT_INDX(sel
->info
.writes_viewport_index
) |
2099 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
2100 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
);
2101 sel
->clipdist_mask
= sel
->info
.writes_clipvertex
?
2102 SIX_BITS
: sel
->info
.clipdist_writemask
;
2103 sel
->culldist_mask
= sel
->info
.culldist_writemask
<<
2104 sel
->info
.num_written_clipdistance
;
2106 /* DB_SHADER_CONTROL */
2107 sel
->db_shader_control
=
2108 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
2109 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
2110 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
2111 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
2113 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
2114 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2115 sel
->db_shader_control
|=
2116 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2118 case TGSI_FS_DEPTH_LAYOUT_LESS
:
2119 sel
->db_shader_control
|=
2120 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2124 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2126 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2127 * --|-----------|------------|------------|--------------------|-------------------|-------------
2128 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2129 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2130 * 2 | false | true | n/a | LateZ | 1 | 0
2131 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2132 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2134 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2135 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2137 * Don't use ReZ without profiling !!!
2139 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2142 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
2144 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
2145 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
2146 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
2147 } else if (sel
->info
.writes_memory
) {
2149 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) |
2150 S_02880C_EXEC_ON_HIER_FAIL(1);
2153 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2156 (void) mtx_init(&sel
->mutex
, mtx_plain
);
2157 util_queue_fence_init(&sel
->ready
);
2159 if ((sctx
->b
.debug
.debug_message
&& !sctx
->b
.debug
.async
) ||
2161 r600_can_dump_shader(&sscreen
->b
, sel
->info
.processor
))
2162 si_init_shader_selector_async(sel
, -1);
2164 util_queue_add_job(&sscreen
->shader_compiler_queue
, sel
,
2165 &sel
->ready
, si_init_shader_selector_async
,
2171 static void si_update_streamout_state(struct si_context
*sctx
)
2173 struct si_shader_selector
*shader_with_so
= si_get_vs(sctx
)->cso
;
2175 if (!shader_with_so
)
2178 sctx
->b
.streamout
.enabled_stream_buffers_mask
=
2179 shader_with_so
->enabled_streamout_buffer_mask
;
2180 sctx
->b
.streamout
.stride_in_dw
= shader_with_so
->so
.stride
;
2183 static void si_update_clip_regs(struct si_context
*sctx
,
2184 struct si_shader_selector
*old_hw_vs
,
2185 struct si_shader
*old_hw_vs_variant
,
2186 struct si_shader_selector
*next_hw_vs
,
2187 struct si_shader
*next_hw_vs_variant
)
2191 old_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] !=
2192 next_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] ||
2193 old_hw_vs
->pa_cl_vs_out_cntl
!= next_hw_vs
->pa_cl_vs_out_cntl
||
2194 old_hw_vs
->clipdist_mask
!= next_hw_vs
->clipdist_mask
||
2195 old_hw_vs
->culldist_mask
!= next_hw_vs
->culldist_mask
||
2196 !old_hw_vs_variant
||
2197 !next_hw_vs_variant
||
2198 old_hw_vs_variant
->key
.opt
.hw_vs
.clip_disable
!=
2199 next_hw_vs_variant
->key
.opt
.hw_vs
.clip_disable
))
2200 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
2203 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
2205 struct si_context
*sctx
= (struct si_context
*)ctx
;
2206 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2207 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2208 struct si_shader_selector
*sel
= state
;
2210 if (sctx
->vs_shader
.cso
== sel
)
2213 sctx
->vs_shader
.cso
= sel
;
2214 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2215 sctx
->do_update_shaders
= true;
2216 r600_update_vs_writes_viewport_index(&sctx
->b
, si_get_vs_info(sctx
));
2217 si_set_active_descriptors_for_shader(sctx
, sel
);
2218 si_update_streamout_state(sctx
);
2219 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2220 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2223 static void si_update_tess_uses_prim_id(struct si_context
*sctx
)
2225 sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
=
2226 (sctx
->tes_shader
.cso
&&
2227 sctx
->tes_shader
.cso
->info
.uses_primid
) ||
2228 (sctx
->tcs_shader
.cso
&&
2229 sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
2230 (sctx
->gs_shader
.cso
&&
2231 sctx
->gs_shader
.cso
->info
.uses_primid
) ||
2232 (sctx
->ps_shader
.cso
&& !sctx
->gs_shader
.cso
&&
2233 sctx
->ps_shader
.cso
->info
.uses_primid
);
2236 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
2238 struct si_context
*sctx
= (struct si_context
*)ctx
;
2239 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2240 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2241 struct si_shader_selector
*sel
= state
;
2242 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
2244 if (sctx
->gs_shader
.cso
== sel
)
2247 sctx
->gs_shader
.cso
= sel
;
2248 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2249 sctx
->ia_multi_vgt_param_key
.u
.uses_gs
= sel
!= NULL
;
2250 sctx
->do_update_shaders
= true;
2251 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2253 if (enable_changed
) {
2254 si_shader_change_notify(sctx
);
2255 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2256 si_update_tess_uses_prim_id(sctx
);
2258 r600_update_vs_writes_viewport_index(&sctx
->b
, si_get_vs_info(sctx
));
2259 si_set_active_descriptors_for_shader(sctx
, sel
);
2260 si_update_streamout_state(sctx
);
2261 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2262 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2265 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
2267 struct si_context
*sctx
= (struct si_context
*)ctx
;
2268 struct si_shader_selector
*sel
= state
;
2269 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
2271 if (sctx
->tcs_shader
.cso
== sel
)
2274 sctx
->tcs_shader
.cso
= sel
;
2275 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2276 si_update_tess_uses_prim_id(sctx
);
2277 sctx
->do_update_shaders
= true;
2280 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
2282 si_set_active_descriptors_for_shader(sctx
, sel
);
2285 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
2287 struct si_context
*sctx
= (struct si_context
*)ctx
;
2288 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2289 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2290 struct si_shader_selector
*sel
= state
;
2291 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
2293 if (sctx
->tes_shader
.cso
== sel
)
2296 sctx
->tes_shader
.cso
= sel
;
2297 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
2298 sctx
->ia_multi_vgt_param_key
.u
.uses_tess
= sel
!= NULL
;
2299 si_update_tess_uses_prim_id(sctx
);
2300 sctx
->do_update_shaders
= true;
2301 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2303 if (enable_changed
) {
2304 si_shader_change_notify(sctx
);
2305 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
2307 r600_update_vs_writes_viewport_index(&sctx
->b
, si_get_vs_info(sctx
));
2308 si_set_active_descriptors_for_shader(sctx
, sel
);
2309 si_update_streamout_state(sctx
);
2310 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2311 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2314 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
2316 struct si_context
*sctx
= (struct si_context
*)ctx
;
2317 struct si_shader_selector
*sel
= state
;
2319 /* skip if supplied shader is one already in use */
2320 if (sctx
->ps_shader
.cso
== sel
)
2323 sctx
->ps_shader
.cso
= sel
;
2324 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
2325 sctx
->do_update_shaders
= true;
2326 if (sel
&& sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2327 si_update_tess_uses_prim_id(sctx
);
2328 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
2329 si_set_active_descriptors_for_shader(sctx
, sel
);
2332 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
2334 if (shader
->is_optimized
) {
2335 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue_low_priority
,
2336 &shader
->optimized_ready
);
2337 util_queue_fence_destroy(&shader
->optimized_ready
);
2341 switch (shader
->selector
->type
) {
2342 case PIPE_SHADER_VERTEX
:
2343 if (shader
->key
.as_ls
) {
2344 assert(sctx
->b
.chip_class
<= VI
);
2345 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
2346 } else if (shader
->key
.as_es
) {
2347 assert(sctx
->b
.chip_class
<= VI
);
2348 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2350 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2353 case PIPE_SHADER_TESS_CTRL
:
2354 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
2356 case PIPE_SHADER_TESS_EVAL
:
2357 if (shader
->key
.as_es
) {
2358 assert(sctx
->b
.chip_class
<= VI
);
2359 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2361 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2364 case PIPE_SHADER_GEOMETRY
:
2365 if (shader
->is_gs_copy_shader
)
2366 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2368 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
2370 case PIPE_SHADER_FRAGMENT
:
2371 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
2376 si_shader_selector_reference(sctx
, &shader
->previous_stage_sel
, NULL
);
2377 si_shader_destroy(shader
);
2381 static void si_destroy_shader_selector(struct si_context
*sctx
,
2382 struct si_shader_selector
*sel
)
2384 struct si_shader
*p
= sel
->first_variant
, *c
;
2385 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
2386 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
2387 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
2388 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
2389 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
2390 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
2393 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue
, &sel
->ready
);
2395 if (current_shader
[sel
->type
]->cso
== sel
) {
2396 current_shader
[sel
->type
]->cso
= NULL
;
2397 current_shader
[sel
->type
]->current
= NULL
;
2401 c
= p
->next_variant
;
2402 si_delete_shader(sctx
, p
);
2406 if (sel
->main_shader_part
)
2407 si_delete_shader(sctx
, sel
->main_shader_part
);
2408 if (sel
->main_shader_part_ls
)
2409 si_delete_shader(sctx
, sel
->main_shader_part_ls
);
2410 if (sel
->main_shader_part_es
)
2411 si_delete_shader(sctx
, sel
->main_shader_part_es
);
2412 if (sel
->gs_copy_shader
)
2413 si_delete_shader(sctx
, sel
->gs_copy_shader
);
2415 util_queue_fence_destroy(&sel
->ready
);
2416 mtx_destroy(&sel
->mutex
);
2421 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
2423 struct si_context
*sctx
= (struct si_context
*)ctx
;
2424 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
2426 si_shader_selector_reference(sctx
, &sel
, NULL
);
2429 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
2430 struct si_shader
*vs
, unsigned name
,
2431 unsigned index
, unsigned interpolate
)
2433 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
2434 unsigned j
, offset
, ps_input_cntl
= 0;
2436 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2437 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
))
2438 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
2440 if (name
== TGSI_SEMANTIC_PCOORD
||
2441 (name
== TGSI_SEMANTIC_TEXCOORD
&&
2442 sctx
->sprite_coord_enable
& (1 << index
))) {
2443 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
2446 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
2447 if (name
== vsinfo
->output_semantic_name
[j
] &&
2448 index
== vsinfo
->output_semantic_index
[j
]) {
2449 offset
= vs
->info
.vs_output_param_offset
[j
];
2451 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
2452 /* The input is loaded from parameter memory. */
2453 ps_input_cntl
|= S_028644_OFFSET(offset
);
2454 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2455 if (offset
== AC_EXP_PARAM_UNDEFINED
) {
2456 /* This can happen with depth-only rendering. */
2459 /* The input is a DEFAULT_VAL constant. */
2460 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
2461 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
2462 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
2465 ps_input_cntl
= S_028644_OFFSET(0x20) |
2466 S_028644_DEFAULT_VAL(offset
);
2472 if (name
== TGSI_SEMANTIC_PRIMID
)
2473 /* PrimID is written after the last output. */
2474 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
2475 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2476 /* No corresponding output found, load defaults into input.
2477 * Don't set any other bits.
2478 * (FLAT_SHADE=1 completely changes behavior) */
2479 ps_input_cntl
= S_028644_OFFSET(0x20);
2480 /* D3D 9 behaviour. GL is undefined */
2481 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
2482 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
2484 return ps_input_cntl
;
2487 static void si_emit_spi_map(struct si_context
*sctx
, struct r600_atom
*atom
)
2489 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2490 struct si_shader
*ps
= sctx
->ps_shader
.current
;
2491 struct si_shader
*vs
= si_get_vs_state(sctx
);
2492 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
2493 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
2495 if (!ps
|| !ps
->selector
->info
.num_inputs
)
2498 num_interp
= si_get_ps_num_interp(ps
);
2499 assert(num_interp
> 0);
2500 radeon_set_context_reg_seq(cs
, R_028644_SPI_PS_INPUT_CNTL_0
, num_interp
);
2502 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
2503 unsigned name
= psinfo
->input_semantic_name
[i
];
2504 unsigned index
= psinfo
->input_semantic_index
[i
];
2505 unsigned interpolate
= psinfo
->input_interpolate
[i
];
2507 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, name
, index
,
2511 if (name
== TGSI_SEMANTIC_COLOR
) {
2512 assert(index
< ARRAY_SIZE(bcol_interp
));
2513 bcol_interp
[index
] = interpolate
;
2517 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
2518 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
2520 for (i
= 0; i
< 2; i
++) {
2521 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
2524 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, bcol
,
2525 i
, bcol_interp
[i
]));
2529 assert(num_interp
== num_written
);
2533 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2535 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
2537 if (sctx
->init_config_has_vgt_flush
)
2540 /* Done by Vulkan before VGT_FLUSH. */
2541 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2542 si_pm4_cmd_add(sctx
->init_config
,
2543 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2544 si_pm4_cmd_end(sctx
->init_config
, false);
2546 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2547 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2548 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
2549 si_pm4_cmd_end(sctx
->init_config
, false);
2550 sctx
->init_config_has_vgt_flush
= true;
2553 /* Initialize state related to ESGS / GSVS ring buffers */
2554 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
2556 struct si_shader_selector
*es
=
2557 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
2558 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
2559 struct si_pm4_state
*pm4
;
2561 /* Chip constants. */
2562 unsigned num_se
= sctx
->screen
->b
.info
.max_se
;
2563 unsigned wave_size
= 64;
2564 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
2565 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2566 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2568 unsigned gs_vertex_reuse
= (sctx
->b
.chip_class
>= VI
? 32 : 16) * num_se
;
2569 unsigned alignment
= 256 * num_se
;
2570 /* The maximum size is 63.999 MB per SE. */
2571 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
2573 /* Calculate the minimum size. */
2574 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
2575 wave_size
, alignment
);
2577 /* These are recommended sizes, not minimum sizes. */
2578 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
2579 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
2580 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
2581 gs
->max_gsvs_emit_size
;
2583 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
2584 esgs_ring_size
= align(esgs_ring_size
, alignment
);
2585 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
2587 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
2588 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
2590 /* Some rings don't have to be allocated if shaders don't use them.
2591 * (e.g. no varyings between ES and GS or GS and VS)
2593 * GFX9 doesn't have the ESGS ring.
2595 bool update_esgs
= sctx
->b
.chip_class
<= VI
&&
2597 (!sctx
->esgs_ring
||
2598 sctx
->esgs_ring
->width0
< esgs_ring_size
);
2599 bool update_gsvs
= gsvs_ring_size
&&
2600 (!sctx
->gsvs_ring
||
2601 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
2603 if (!update_esgs
&& !update_gsvs
)
2607 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
2609 r600_aligned_buffer_create(sctx
->b
.b
.screen
,
2610 R600_RESOURCE_FLAG_UNMAPPABLE
,
2612 esgs_ring_size
, alignment
);
2613 if (!sctx
->esgs_ring
)
2618 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
2620 r600_aligned_buffer_create(sctx
->b
.b
.screen
,
2621 R600_RESOURCE_FLAG_UNMAPPABLE
,
2623 gsvs_ring_size
, alignment
);
2624 if (!sctx
->gsvs_ring
)
2628 /* Create the "init_config_gs_rings" state. */
2629 pm4
= CALLOC_STRUCT(si_pm4_state
);
2633 if (sctx
->b
.chip_class
>= CIK
) {
2634 if (sctx
->esgs_ring
) {
2635 assert(sctx
->b
.chip_class
<= VI
);
2636 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
2637 sctx
->esgs_ring
->width0
/ 256);
2639 if (sctx
->gsvs_ring
)
2640 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
2641 sctx
->gsvs_ring
->width0
/ 256);
2643 if (sctx
->esgs_ring
)
2644 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
2645 sctx
->esgs_ring
->width0
/ 256);
2646 if (sctx
->gsvs_ring
)
2647 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
2648 sctx
->gsvs_ring
->width0
/ 256);
2651 /* Set the state. */
2652 if (sctx
->init_config_gs_rings
)
2653 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
2654 sctx
->init_config_gs_rings
= pm4
;
2656 if (!sctx
->init_config_has_vgt_flush
) {
2657 si_init_config_add_vgt_flush(sctx
);
2658 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
2661 /* Flush the context to re-emit both init_config states. */
2662 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
2663 si_context_gfx_flush(sctx
, RADEON_FLUSH_ASYNC
, NULL
);
2665 /* Set ring bindings. */
2666 if (sctx
->esgs_ring
) {
2667 assert(sctx
->b
.chip_class
<= VI
);
2668 si_set_ring_buffer(&sctx
->b
.b
, SI_ES_RING_ESGS
,
2669 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
2670 true, true, 4, 64, 0);
2671 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_ESGS
,
2672 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
2673 false, false, 0, 0, 0);
2675 if (sctx
->gsvs_ring
) {
2676 si_set_ring_buffer(&sctx
->b
.b
, SI_RING_GSVS
,
2677 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
2678 false, false, 0, 0, 0);
2684 static void si_shader_lock(struct si_shader
*shader
)
2686 mtx_lock(&shader
->selector
->mutex
);
2687 if (shader
->previous_stage_sel
) {
2688 assert(shader
->previous_stage_sel
!= shader
->selector
);
2689 mtx_lock(&shader
->previous_stage_sel
->mutex
);
2693 static void si_shader_unlock(struct si_shader
*shader
)
2695 if (shader
->previous_stage_sel
)
2696 mtx_unlock(&shader
->previous_stage_sel
->mutex
);
2697 mtx_unlock(&shader
->selector
->mutex
);
2701 * @returns 1 if \p sel has been updated to use a new scratch buffer
2703 * < 0 if there was a failure
2705 static int si_update_scratch_buffer(struct si_context
*sctx
,
2706 struct si_shader
*shader
)
2708 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
2714 /* This shader doesn't need a scratch buffer */
2715 if (shader
->config
.scratch_bytes_per_wave
== 0)
2718 /* Prevent race conditions when updating:
2719 * - si_shader::scratch_bo
2720 * - si_shader::binary::code
2721 * - si_shader::previous_stage::binary::code.
2723 si_shader_lock(shader
);
2725 /* This shader is already configured to use the current
2726 * scratch buffer. */
2727 if (shader
->scratch_bo
== sctx
->scratch_buffer
) {
2728 si_shader_unlock(shader
);
2732 assert(sctx
->scratch_buffer
);
2734 if (shader
->previous_stage
)
2735 si_shader_apply_scratch_relocs(shader
->previous_stage
, scratch_va
);
2737 si_shader_apply_scratch_relocs(shader
, scratch_va
);
2739 /* Replace the shader bo with a new bo that has the relocs applied. */
2740 r
= si_shader_binary_upload(sctx
->screen
, shader
);
2742 si_shader_unlock(shader
);
2746 /* Update the shader state to use the new shader bo. */
2747 si_shader_init_pm4_state(sctx
->screen
, shader
);
2749 r600_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
2751 si_shader_unlock(shader
);
2755 static unsigned si_get_current_scratch_buffer_size(struct si_context
*sctx
)
2757 return sctx
->scratch_buffer
? sctx
->scratch_buffer
->b
.b
.width0
: 0;
2760 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
2762 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
2765 static struct si_shader
*si_get_tcs_current(struct si_context
*sctx
)
2767 if (!sctx
->tes_shader
.cso
)
2768 return NULL
; /* tessellation disabled */
2770 return sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.current
:
2771 sctx
->fixed_func_tcs_shader
.current
;
2774 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context
*sctx
)
2778 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
2779 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
2780 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
2781 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
2783 if (sctx
->tes_shader
.cso
) {
2784 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
2786 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(tcs
));
2791 static bool si_update_scratch_relocs(struct si_context
*sctx
)
2793 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
2796 /* Update the shaders, so that they are using the latest scratch.
2797 * The scratch buffer may have been changed since these shaders were
2798 * last used, so we still need to try to update them, even if they
2799 * require scratch buffers smaller than the current size.
2801 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
2805 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
2807 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
2811 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
2813 r
= si_update_scratch_buffer(sctx
, tcs
);
2817 si_pm4_bind_state(sctx
, hs
, tcs
->pm4
);
2819 /* VS can be bound as LS, ES, or VS. */
2820 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
2824 if (sctx
->tes_shader
.current
)
2825 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
2826 else if (sctx
->gs_shader
.current
)
2827 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
2829 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
2832 /* TES can be bound as ES or VS. */
2833 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
2837 if (sctx
->gs_shader
.current
)
2838 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
2840 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
2846 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
2848 unsigned current_scratch_buffer_size
=
2849 si_get_current_scratch_buffer_size(sctx
);
2850 unsigned scratch_bytes_per_wave
=
2851 si_get_max_scratch_bytes_per_wave(sctx
);
2852 unsigned scratch_needed_size
= scratch_bytes_per_wave
*
2853 sctx
->scratch_waves
;
2854 unsigned spi_tmpring_size
;
2856 if (scratch_needed_size
> 0) {
2857 if (scratch_needed_size
> current_scratch_buffer_size
) {
2858 /* Create a bigger scratch buffer */
2859 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
2861 sctx
->scratch_buffer
= (struct r600_resource
*)
2862 r600_aligned_buffer_create(&sctx
->screen
->b
.b
,
2863 R600_RESOURCE_FLAG_UNMAPPABLE
,
2865 scratch_needed_size
, 256);
2866 if (!sctx
->scratch_buffer
)
2869 si_mark_atom_dirty(sctx
, &sctx
->scratch_state
);
2870 r600_context_add_resource_size(&sctx
->b
.b
,
2871 &sctx
->scratch_buffer
->b
.b
);
2874 if (!si_update_scratch_relocs(sctx
))
2878 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
2879 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
2880 "scratch size should already be aligned correctly.");
2882 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
2883 S_0286E8_WAVESIZE(scratch_bytes_per_wave
>> 10);
2884 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
2885 sctx
->spi_tmpring_size
= spi_tmpring_size
;
2886 si_mark_atom_dirty(sctx
, &sctx
->scratch_state
);
2891 static void si_init_tess_factor_ring(struct si_context
*sctx
)
2893 bool double_offchip_buffers
= sctx
->b
.chip_class
>= CIK
&&
2894 sctx
->b
.family
!= CHIP_CARRIZO
&&
2895 sctx
->b
.family
!= CHIP_STONEY
;
2896 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
2897 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
2898 sctx
->screen
->b
.info
.max_se
;
2899 unsigned offchip_granularity
;
2901 switch (sctx
->screen
->tess_offchip_block_dw_size
) {
2906 offchip_granularity
= V_03093C_X_8K_DWORDS
;
2909 offchip_granularity
= V_03093C_X_4K_DWORDS
;
2913 switch (sctx
->b
.chip_class
) {
2915 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
2920 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
2927 assert(!sctx
->tf_ring
);
2928 /* Use 64K alignment for both rings, so that we can pass the address
2929 * to shaders as one SGPR containing bits [16:47].
2931 sctx
->tf_ring
= r600_aligned_buffer_create(sctx
->b
.b
.screen
,
2932 R600_RESOURCE_FLAG_UNMAPPABLE
,
2934 32768 * sctx
->screen
->b
.info
.max_se
,
2939 assert(((sctx
->tf_ring
->width0
/ 4) & C_030938_SIZE
) == 0);
2941 sctx
->tess_offchip_ring
=
2942 r600_aligned_buffer_create(sctx
->b
.b
.screen
,
2943 R600_RESOURCE_FLAG_UNMAPPABLE
,
2945 max_offchip_buffers
*
2946 sctx
->screen
->tess_offchip_block_dw_size
* 4,
2948 if (!sctx
->tess_offchip_ring
)
2951 si_init_config_add_vgt_flush(sctx
);
2953 uint64_t offchip_va
= r600_resource(sctx
->tess_offchip_ring
)->gpu_address
;
2954 uint64_t factor_va
= r600_resource(sctx
->tf_ring
)->gpu_address
;
2955 assert((offchip_va
& 0xffff) == 0);
2956 assert((factor_va
& 0xffff) == 0);
2958 si_pm4_add_bo(sctx
->init_config
, r600_resource(sctx
->tess_offchip_ring
),
2959 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
2960 si_pm4_add_bo(sctx
->init_config
, r600_resource(sctx
->tf_ring
),
2961 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
2963 /* Append these registers to the init config state. */
2964 if (sctx
->b
.chip_class
>= CIK
) {
2965 if (sctx
->b
.chip_class
>= VI
)
2966 --max_offchip_buffers
;
2968 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
2969 S_030938_SIZE(sctx
->tf_ring
->width0
/ 4));
2970 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
2972 if (sctx
->b
.chip_class
>= GFX9
)
2973 si_pm4_set_reg(sctx
->init_config
, R_030944_VGT_TF_MEMORY_BASE_HI
,
2975 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
2976 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
2977 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
));
2979 assert(offchip_granularity
== V_03093C_X_8K_DWORDS
);
2980 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
2981 S_008988_SIZE(sctx
->tf_ring
->width0
/ 4));
2982 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
2984 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
2985 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
));
2988 if (sctx
->b
.chip_class
>= GFX9
) {
2989 si_pm4_set_reg(sctx
->init_config
,
2990 R_00B430_SPI_SHADER_USER_DATA_LS_0
+
2991 GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K
* 4,
2993 si_pm4_set_reg(sctx
->init_config
,
2994 R_00B430_SPI_SHADER_USER_DATA_LS_0
+
2995 GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K
* 4,
2998 si_pm4_set_reg(sctx
->init_config
,
2999 R_00B430_SPI_SHADER_USER_DATA_HS_0
+
3000 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K
* 4,
3002 si_pm4_set_reg(sctx
->init_config
,
3003 R_00B430_SPI_SHADER_USER_DATA_HS_0
+
3004 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K
* 4,
3008 /* Flush the context to re-emit the init_config state.
3009 * This is done only once in a lifetime of a context.
3011 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3012 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
3013 si_context_gfx_flush(sctx
, RADEON_FLUSH_ASYNC
, NULL
);
3017 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
3018 * VS passes its outputs to TES directly, so the fixed-function shader only
3019 * has to write TESSOUTER and TESSINNER.
3021 static void si_generate_fixed_func_tcs(struct si_context
*sctx
)
3023 struct ureg_src outer
, inner
;
3024 struct ureg_dst tessouter
, tessinner
;
3025 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_TESS_CTRL
);
3028 return; /* if we get here, we're screwed */
3030 assert(!sctx
->fixed_func_tcs_shader
.cso
);
3032 outer
= ureg_DECL_system_value(ureg
,
3033 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
, 0);
3034 inner
= ureg_DECL_system_value(ureg
,
3035 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
, 0);
3037 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
3038 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
3040 ureg_MOV(ureg
, tessouter
, outer
);
3041 ureg_MOV(ureg
, tessinner
, inner
);
3044 sctx
->fixed_func_tcs_shader
.cso
=
3045 ureg_create_shader_and_destroy(ureg
, &sctx
->b
.b
);
3048 static void si_update_vgt_shader_config(struct si_context
*sctx
)
3050 /* Calculate the index of the config.
3051 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3052 unsigned index
= 2*!!sctx
->tes_shader
.cso
+ !!sctx
->gs_shader
.cso
;
3053 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[index
];
3056 uint32_t stages
= 0;
3058 *pm4
= CALLOC_STRUCT(si_pm4_state
);
3060 if (sctx
->tes_shader
.cso
) {
3061 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3062 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3064 if (sctx
->gs_shader
.cso
)
3065 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3067 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3069 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3070 } else if (sctx
->gs_shader
.cso
) {
3071 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3073 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3076 if (sctx
->b
.chip_class
>= GFX9
)
3077 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3079 si_pm4_set_reg(*pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
3081 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
3084 bool si_update_shaders(struct si_context
*sctx
)
3086 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
3087 struct si_compiler_ctx_state compiler_state
;
3088 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3089 struct si_shader
*old_vs
= si_get_vs_state(sctx
);
3090 bool old_clip_disable
= old_vs
? old_vs
->key
.opt
.hw_vs
.clip_disable
: false;
3093 compiler_state
.tm
= sctx
->tm
;
3094 compiler_state
.debug
= sctx
->b
.debug
;
3095 compiler_state
.is_debug_context
= sctx
->is_debug
;
3097 /* Update stages before GS. */
3098 if (sctx
->tes_shader
.cso
) {
3099 if (!sctx
->tf_ring
) {
3100 si_init_tess_factor_ring(sctx
);
3106 if (sctx
->b
.chip_class
<= VI
) {
3107 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
3111 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3114 if (sctx
->tcs_shader
.cso
) {
3115 r
= si_shader_select(ctx
, &sctx
->tcs_shader
,
3119 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
3121 if (!sctx
->fixed_func_tcs_shader
.cso
) {
3122 si_generate_fixed_func_tcs(sctx
);
3123 if (!sctx
->fixed_func_tcs_shader
.cso
)
3127 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
,
3131 si_pm4_bind_state(sctx
, hs
,
3132 sctx
->fixed_func_tcs_shader
.current
->pm4
);
3135 if (sctx
->gs_shader
.cso
) {
3137 if (sctx
->b
.chip_class
<= VI
) {
3138 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
3142 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3146 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
3150 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3152 } else if (sctx
->gs_shader
.cso
) {
3153 if (sctx
->b
.chip_class
<= VI
) {
3155 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
3159 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3161 si_pm4_bind_state(sctx
, ls
, NULL
);
3162 si_pm4_bind_state(sctx
, hs
, NULL
);
3166 r
= si_shader_select(ctx
, &sctx
->vs_shader
, &compiler_state
);
3169 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3170 si_pm4_bind_state(sctx
, ls
, NULL
);
3171 si_pm4_bind_state(sctx
, hs
, NULL
);
3175 if (sctx
->gs_shader
.cso
) {
3176 r
= si_shader_select(ctx
, &sctx
->gs_shader
, &compiler_state
);
3179 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3180 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
3182 if (!si_update_gs_ring_buffers(sctx
))
3185 si_pm4_bind_state(sctx
, gs
, NULL
);
3186 if (sctx
->b
.chip_class
<= VI
)
3187 si_pm4_bind_state(sctx
, es
, NULL
);
3190 si_update_vgt_shader_config(sctx
);
3192 if (old_clip_disable
!= si_get_vs_state(sctx
)->key
.opt
.hw_vs
.clip_disable
)
3193 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
3195 if (sctx
->ps_shader
.cso
) {
3196 unsigned db_shader_control
;
3198 r
= si_shader_select(ctx
, &sctx
->ps_shader
, &compiler_state
);
3201 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3204 sctx
->ps_shader
.cso
->db_shader_control
|
3205 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
3207 if (si_pm4_state_changed(sctx
, ps
) || si_pm4_state_changed(sctx
, vs
) ||
3208 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
3209 sctx
->flatshade
!= rs
->flatshade
) {
3210 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
3211 sctx
->flatshade
= rs
->flatshade
;
3212 si_mark_atom_dirty(sctx
, &sctx
->spi_map
);
3215 if (sctx
->screen
->b
.rbplus_allowed
&& si_pm4_state_changed(sctx
, ps
))
3216 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
3218 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
3219 sctx
->ps_db_shader_control
= db_shader_control
;
3220 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
3223 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
3224 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
3225 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
3227 if (sctx
->b
.chip_class
== SI
)
3228 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
3230 if (sctx
->framebuffer
.nr_samples
<= 1)
3231 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
3235 if (si_pm4_state_changed(sctx
, ls
) ||
3236 si_pm4_state_changed(sctx
, hs
) ||
3237 si_pm4_state_changed(sctx
, es
) ||
3238 si_pm4_state_changed(sctx
, gs
) ||
3239 si_pm4_state_changed(sctx
, vs
) ||
3240 si_pm4_state_changed(sctx
, ps
)) {
3241 if (!si_update_spi_tmpring_size(sctx
))
3245 if (sctx
->b
.chip_class
>= CIK
)
3246 si_mark_atom_dirty(sctx
, &sctx
->prefetch_L2
);
3248 sctx
->do_update_shaders
= false;
3252 static void si_emit_scratch_state(struct si_context
*sctx
,
3253 struct r600_atom
*atom
)
3255 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
3257 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
3258 sctx
->spi_tmpring_size
);
3260 if (sctx
->scratch_buffer
) {
3261 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
3262 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
3263 RADEON_PRIO_SCRATCH_BUFFER
);
3267 void si_init_shader_functions(struct si_context
*sctx
)
3269 si_init_atom(sctx
, &sctx
->spi_map
, &sctx
->atoms
.s
.spi_map
, si_emit_spi_map
);
3270 si_init_atom(sctx
, &sctx
->scratch_state
, &sctx
->atoms
.s
.scratch_state
,
3271 si_emit_scratch_state
);
3273 sctx
->b
.b
.create_vs_state
= si_create_shader_selector
;
3274 sctx
->b
.b
.create_tcs_state
= si_create_shader_selector
;
3275 sctx
->b
.b
.create_tes_state
= si_create_shader_selector
;
3276 sctx
->b
.b
.create_gs_state
= si_create_shader_selector
;
3277 sctx
->b
.b
.create_fs_state
= si_create_shader_selector
;
3279 sctx
->b
.b
.bind_vs_state
= si_bind_vs_shader
;
3280 sctx
->b
.b
.bind_tcs_state
= si_bind_tcs_shader
;
3281 sctx
->b
.b
.bind_tes_state
= si_bind_tes_shader
;
3282 sctx
->b
.b
.bind_gs_state
= si_bind_gs_shader
;
3283 sctx
->b
.b
.bind_fs_state
= si_bind_ps_shader
;
3285 sctx
->b
.b
.delete_vs_state
= si_delete_shader_selector
;
3286 sctx
->b
.b
.delete_tcs_state
= si_delete_shader_selector
;
3287 sctx
->b
.b
.delete_tes_state
= si_delete_shader_selector
;
3288 sctx
->b
.b
.delete_gs_state
= si_delete_shader_selector
;
3289 sctx
->b
.b
.delete_fs_state
= si_delete_shader_selector
;