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svga: change svga_hw_view_state::dirty to boolean
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "si_shader.h"
30 #include "sid.h"
31 #include "radeon/r600_cs.h"
32
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/u_memory.h"
36 #include "util/u_prim.h"
37 #include "util/u_simple_shaders.h"
38
39 static void si_set_tesseval_regs(struct si_shader *shader,
40 struct si_pm4_state *pm4)
41 {
42 struct tgsi_shader_info *info = &shader->selector->info;
43 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
44 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
45 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
46 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
47 unsigned type, partitioning, topology;
48
49 switch (tes_prim_mode) {
50 case PIPE_PRIM_LINES:
51 type = V_028B6C_TESS_ISOLINE;
52 break;
53 case PIPE_PRIM_TRIANGLES:
54 type = V_028B6C_TESS_TRIANGLE;
55 break;
56 case PIPE_PRIM_QUADS:
57 type = V_028B6C_TESS_QUAD;
58 break;
59 default:
60 assert(0);
61 return;
62 }
63
64 switch (tes_spacing) {
65 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
66 partitioning = V_028B6C_PART_FRAC_ODD;
67 break;
68 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
69 partitioning = V_028B6C_PART_FRAC_EVEN;
70 break;
71 case PIPE_TESS_SPACING_EQUAL:
72 partitioning = V_028B6C_PART_INTEGER;
73 break;
74 default:
75 assert(0);
76 return;
77 }
78
79 if (tes_point_mode)
80 topology = V_028B6C_OUTPUT_POINT;
81 else if (tes_prim_mode == PIPE_PRIM_LINES)
82 topology = V_028B6C_OUTPUT_LINE;
83 else if (tes_vertex_order_cw)
84 /* for some reason, this must be the other way around */
85 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
86 else
87 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
88
89 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
90 S_028B6C_TYPE(type) |
91 S_028B6C_PARTITIONING(partitioning) |
92 S_028B6C_TOPOLOGY(topology));
93 }
94
95 static void si_shader_ls(struct si_shader *shader)
96 {
97 struct si_pm4_state *pm4;
98 unsigned num_sgprs, num_user_sgprs;
99 unsigned vgpr_comp_cnt;
100 uint64_t va;
101
102 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
103 if (!pm4)
104 return;
105
106 va = shader->bo->gpu_address;
107 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
108
109 /* We need at least 2 components for LS.
110 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
111 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 1;
112
113 num_user_sgprs = SI_LS_NUM_USER_SGPR;
114 num_sgprs = shader->num_sgprs;
115 if (num_user_sgprs > num_sgprs) {
116 /* Last 2 reserved SGPRs are used for VCC */
117 num_sgprs = num_user_sgprs + 2;
118 }
119 assert(num_sgprs <= 104);
120
121 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
122 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
123
124 shader->rsrc1 = S_00B528_VGPRS((shader->num_vgprs - 1) / 4) |
125 S_00B528_SGPRS((num_sgprs - 1) / 8) |
126 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
127 S_00B528_DX10_CLAMP(shader->dx10_clamp_mode);
128 shader->rsrc2 = S_00B52C_USER_SGPR(num_user_sgprs) |
129 S_00B52C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0);
130 }
131
132 static void si_shader_hs(struct si_shader *shader)
133 {
134 struct si_pm4_state *pm4;
135 unsigned num_sgprs, num_user_sgprs;
136 uint64_t va;
137
138 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
139 if (!pm4)
140 return;
141
142 va = shader->bo->gpu_address;
143 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
144
145 num_user_sgprs = SI_TCS_NUM_USER_SGPR;
146 num_sgprs = shader->num_sgprs;
147 /* One SGPR after user SGPRs is pre-loaded with tessellation factor
148 * buffer offset. */
149 if ((num_user_sgprs + 1) > num_sgprs) {
150 /* Last 2 reserved SGPRs are used for VCC */
151 num_sgprs = num_user_sgprs + 1 + 2;
152 }
153 assert(num_sgprs <= 104);
154
155 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
156 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
157 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
158 S_00B428_VGPRS((shader->num_vgprs - 1) / 4) |
159 S_00B428_SGPRS((num_sgprs - 1) / 8) |
160 S_00B428_DX10_CLAMP(shader->dx10_clamp_mode));
161 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
162 S_00B42C_USER_SGPR(num_user_sgprs) |
163 S_00B42C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
164 }
165
166 static void si_shader_es(struct si_shader *shader)
167 {
168 struct si_pm4_state *pm4;
169 unsigned num_sgprs, num_user_sgprs;
170 unsigned vgpr_comp_cnt;
171 uint64_t va;
172
173 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
174
175 if (!pm4)
176 return;
177
178 va = shader->bo->gpu_address;
179 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
180
181 if (shader->selector->type == PIPE_SHADER_VERTEX) {
182 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
183 num_user_sgprs = SI_ES_NUM_USER_SGPR;
184 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
185 vgpr_comp_cnt = 3; /* all components are needed for TES */
186 num_user_sgprs = SI_TES_NUM_USER_SGPR;
187 } else
188 unreachable("invalid shader selector type");
189
190 num_sgprs = shader->num_sgprs;
191 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
192 if ((num_user_sgprs + 1) > num_sgprs) {
193 /* Last 2 reserved SGPRs are used for VCC */
194 num_sgprs = num_user_sgprs + 1 + 2;
195 }
196 assert(num_sgprs <= 104);
197
198 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
199 shader->selector->esgs_itemsize / 4);
200 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
201 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
202 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
203 S_00B328_VGPRS((shader->num_vgprs - 1) / 4) |
204 S_00B328_SGPRS((num_sgprs - 1) / 8) |
205 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
206 S_00B328_DX10_CLAMP(shader->dx10_clamp_mode));
207 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
208 S_00B32C_USER_SGPR(num_user_sgprs) |
209 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
210
211 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
212 si_set_tesseval_regs(shader, pm4);
213 }
214
215 static void si_shader_gs(struct si_shader *shader)
216 {
217 unsigned gs_vert_itemsize = shader->selector->gsvs_vertex_size;
218 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
219 unsigned gsvs_itemsize = shader->selector->max_gsvs_emit_size >> 2;
220 unsigned gs_num_invocations = shader->selector->gs_num_invocations;
221 unsigned cut_mode;
222 struct si_pm4_state *pm4;
223 unsigned num_sgprs, num_user_sgprs;
224 uint64_t va;
225 unsigned max_stream = shader->selector->max_gs_stream;
226
227 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
228 assert(gsvs_itemsize < (1 << 15));
229
230 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
231
232 if (!pm4)
233 return;
234
235 if (gs_max_vert_out <= 128) {
236 cut_mode = V_028A40_GS_CUT_128;
237 } else if (gs_max_vert_out <= 256) {
238 cut_mode = V_028A40_GS_CUT_256;
239 } else if (gs_max_vert_out <= 512) {
240 cut_mode = V_028A40_GS_CUT_512;
241 } else {
242 assert(gs_max_vert_out <= 1024);
243 cut_mode = V_028A40_GS_CUT_1024;
244 }
245
246 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
247 S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
248 S_028A40_CUT_MODE(cut_mode)|
249 S_028A40_ES_WRITE_OPTIMIZE(1) |
250 S_028A40_GS_WRITE_OPTIMIZE(1));
251
252 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
253 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize * ((max_stream >= 2) ? 2 : 1));
254 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize * ((max_stream >= 3) ? 3 : 1));
255
256 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize * (max_stream + 1));
257
258 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, gs_max_vert_out);
259
260 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize >> 2);
261 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? gs_vert_itemsize >> 2 : 0);
262 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? gs_vert_itemsize >> 2 : 0);
263 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? gs_vert_itemsize >> 2 : 0);
264
265 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
266 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
267 S_028B90_ENABLE(gs_num_invocations > 0));
268
269 va = shader->bo->gpu_address;
270 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
271 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
272 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
273
274 num_user_sgprs = SI_GS_NUM_USER_SGPR;
275 num_sgprs = shader->num_sgprs;
276 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
277 if ((num_user_sgprs + 2) > num_sgprs) {
278 /* Last 2 reserved SGPRs are used for VCC */
279 num_sgprs = num_user_sgprs + 2 + 2;
280 }
281 assert(num_sgprs <= 104);
282
283 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
284 S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
285 S_00B228_SGPRS((num_sgprs - 1) / 8) |
286 S_00B228_DX10_CLAMP(shader->dx10_clamp_mode));
287 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
288 S_00B22C_USER_SGPR(num_user_sgprs) |
289 S_00B22C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
290 }
291
292 static void si_shader_vs(struct si_shader *shader)
293 {
294 struct si_pm4_state *pm4;
295 unsigned num_sgprs, num_user_sgprs;
296 unsigned nparams, vgpr_comp_cnt;
297 uint64_t va;
298 unsigned window_space =
299 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
300 bool enable_prim_id = si_vs_exports_prim_id(shader);
301
302 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
303
304 if (!pm4)
305 return;
306
307 /* If this is the GS copy shader, the GS state writes this register.
308 * Otherwise, the VS state writes it.
309 */
310 if (!shader->is_gs_copy_shader) {
311 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
312 S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
313 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
314 } else
315 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
316
317 va = shader->bo->gpu_address;
318 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
319
320 if (shader->is_gs_copy_shader) {
321 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
322 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
323 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
324 vgpr_comp_cnt = shader->uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
325 num_user_sgprs = SI_VS_NUM_USER_SGPR;
326 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
327 vgpr_comp_cnt = 3; /* all components are needed for TES */
328 num_user_sgprs = SI_TES_NUM_USER_SGPR;
329 } else
330 unreachable("invalid shader selector type");
331
332 num_sgprs = shader->num_sgprs;
333 if (num_user_sgprs > num_sgprs) {
334 /* Last 2 reserved SGPRs are used for VCC */
335 num_sgprs = num_user_sgprs + 2;
336 }
337 assert(num_sgprs <= 104);
338
339 /* VS is required to export at least one param. */
340 nparams = MAX2(shader->nr_param_exports, 1);
341 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
342 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
343
344 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
345 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
346 S_02870C_POS1_EXPORT_FORMAT(shader->nr_pos_exports > 1 ?
347 V_02870C_SPI_SHADER_4COMP :
348 V_02870C_SPI_SHADER_NONE) |
349 S_02870C_POS2_EXPORT_FORMAT(shader->nr_pos_exports > 2 ?
350 V_02870C_SPI_SHADER_4COMP :
351 V_02870C_SPI_SHADER_NONE) |
352 S_02870C_POS3_EXPORT_FORMAT(shader->nr_pos_exports > 3 ?
353 V_02870C_SPI_SHADER_4COMP :
354 V_02870C_SPI_SHADER_NONE));
355
356 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
357 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
358 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
359 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
360 S_00B128_SGPRS((num_sgprs - 1) / 8) |
361 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
362 S_00B128_DX10_CLAMP(shader->dx10_clamp_mode));
363 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
364 S_00B12C_USER_SGPR(num_user_sgprs) |
365 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
366 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
367 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
368 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
369 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
370 S_00B12C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
371 if (window_space)
372 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
373 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
374 else
375 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
376 S_028818_VTX_W0_FMT(1) |
377 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
378 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
379 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
380
381 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
382 si_set_tesseval_regs(shader, pm4);
383 }
384
385 static void si_shader_ps(struct si_shader *shader)
386 {
387 struct tgsi_shader_info *info = &shader->selector->info;
388 struct si_pm4_state *pm4;
389 unsigned i, spi_ps_in_control;
390 unsigned num_sgprs, num_user_sgprs;
391 unsigned spi_baryc_cntl = 0;
392 uint64_t va;
393 bool has_centroid;
394
395 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
396
397 if (!pm4)
398 return;
399
400 for (i = 0; i < info->num_inputs; i++) {
401 switch (info->input_semantic_name[i]) {
402 case TGSI_SEMANTIC_POSITION:
403 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
404 * Possible vaules:
405 * 0 -> Position = pixel center (default)
406 * 1 -> Position = pixel centroid
407 * 2 -> Position = at sample position
408 */
409 switch (info->input_interpolate_loc[i]) {
410 case TGSI_INTERPOLATE_LOC_CENTROID:
411 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
412 break;
413 case TGSI_INTERPOLATE_LOC_SAMPLE:
414 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
415 break;
416 }
417
418 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
419 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
420 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
421 break;
422 }
423 }
424
425 has_centroid = G_0286CC_PERSP_CENTROID_ENA(shader->spi_ps_input_ena) ||
426 G_0286CC_LINEAR_CENTROID_ENA(shader->spi_ps_input_ena);
427
428 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->nparam) |
429 S_0286D8_BC_OPTIMIZE_DISABLE(has_centroid);
430
431 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
432 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
433
434 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
435 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
436 shader->spi_shader_col_format);
437 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
438
439 va = shader->bo->gpu_address;
440 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
441 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
442 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
443
444 num_user_sgprs = SI_PS_NUM_USER_SGPR;
445 num_sgprs = shader->num_sgprs;
446 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
447 if ((num_user_sgprs + 1) > num_sgprs) {
448 /* Last 2 reserved SGPRs are used for VCC */
449 num_sgprs = num_user_sgprs + 1 + 2;
450 }
451 assert(num_sgprs <= 104);
452
453 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
454 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
455 S_00B028_SGPRS((num_sgprs - 1) / 8) |
456 S_00B028_DX10_CLAMP(shader->dx10_clamp_mode));
457 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
458 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
459 S_00B02C_USER_SGPR(num_user_sgprs) |
460 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
461 }
462
463 static void si_shader_init_pm4_state(struct si_shader *shader)
464 {
465
466 if (shader->pm4)
467 si_pm4_free_state_simple(shader->pm4);
468
469 switch (shader->selector->type) {
470 case PIPE_SHADER_VERTEX:
471 if (shader->key.vs.as_ls)
472 si_shader_ls(shader);
473 else if (shader->key.vs.as_es)
474 si_shader_es(shader);
475 else
476 si_shader_vs(shader);
477 break;
478 case PIPE_SHADER_TESS_CTRL:
479 si_shader_hs(shader);
480 break;
481 case PIPE_SHADER_TESS_EVAL:
482 if (shader->key.tes.as_es)
483 si_shader_es(shader);
484 else
485 si_shader_vs(shader);
486 break;
487 case PIPE_SHADER_GEOMETRY:
488 si_shader_gs(shader);
489 si_shader_vs(shader->gs_copy_shader);
490 break;
491 case PIPE_SHADER_FRAGMENT:
492 si_shader_ps(shader);
493 break;
494 default:
495 assert(0);
496 }
497 }
498
499 /* Compute the key for the hw shader variant */
500 static inline void si_shader_selector_key(struct pipe_context *ctx,
501 struct si_shader_selector *sel,
502 union si_shader_key *key)
503 {
504 struct si_context *sctx = (struct si_context *)ctx;
505 unsigned i;
506
507 memset(key, 0, sizeof(*key));
508
509 switch (sel->type) {
510 case PIPE_SHADER_VERTEX:
511 if (sctx->vertex_elements)
512 for (i = 0; i < sctx->vertex_elements->count; ++i)
513 key->vs.instance_divisors[i] =
514 sctx->vertex_elements->elements[i].instance_divisor;
515
516 if (sctx->tes_shader.cso)
517 key->vs.as_ls = 1;
518 else if (sctx->gs_shader.cso)
519 key->vs.as_es = 1;
520
521 if (!sctx->gs_shader.cso && sctx->ps_shader.cso &&
522 sctx->ps_shader.cso->info.uses_primid)
523 key->vs.export_prim_id = 1;
524 break;
525 case PIPE_SHADER_TESS_CTRL:
526 key->tcs.prim_mode =
527 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
528 break;
529 case PIPE_SHADER_TESS_EVAL:
530 if (sctx->gs_shader.cso)
531 key->tes.as_es = 1;
532 else if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
533 key->tes.export_prim_id = 1;
534 break;
535 case PIPE_SHADER_GEOMETRY:
536 break;
537 case PIPE_SHADER_FRAGMENT: {
538 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
539
540 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
541 key->ps.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
542 key->ps.export_16bpc = sctx->framebuffer.export_16bpc;
543
544 if (rs) {
545 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
546 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
547 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
548 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
549
550 key->ps.color_two_side = rs->two_side;
551
552 if (sctx->queued.named.blend) {
553 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
554 rs->multisample_enable &&
555 !sctx->framebuffer.cb0_is_integer;
556 }
557
558 key->ps.poly_stipple = rs->poly_stipple_enable && is_poly;
559 key->ps.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
560 (is_line && rs->line_smooth)) &&
561 sctx->framebuffer.nr_samples <= 1;
562 key->ps.clamp_color = rs->clamp_fragment_color;
563 }
564
565 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
566 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
567 if (sctx->queued.named.dsa &&
568 !sctx->framebuffer.cb0_is_integer)
569 key->ps.alpha_func = sctx->queued.named.dsa->alpha_func;
570 break;
571 }
572 default:
573 assert(0);
574 }
575 }
576
577 /* Select the hw shader variant depending on the current state. */
578 static int si_shader_select(struct pipe_context *ctx,
579 struct si_shader_ctx_state *state)
580 {
581 struct si_context *sctx = (struct si_context *)ctx;
582 struct si_shader_selector *sel = state->cso;
583 struct si_shader *current = state->current;
584 union si_shader_key key;
585 struct si_shader *iter, *shader = NULL;
586 int r;
587
588 si_shader_selector_key(ctx, sel, &key);
589
590 /* Check if we don't need to change anything.
591 * This path is also used for most shaders that don't need multiple
592 * variants, it will cost just a computation of the key and this
593 * test. */
594 if (likely(current && memcmp(&current->key, &key, sizeof(key)) == 0))
595 return 0;
596
597 pipe_mutex_lock(sel->mutex);
598
599 /* Find the shader variant. */
600 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
601 /* Don't check the "current" shader. We checked it above. */
602 if (current != iter &&
603 memcmp(&iter->key, &key, sizeof(key)) == 0) {
604 state->current = iter;
605 pipe_mutex_unlock(sel->mutex);
606 return 0;
607 }
608 }
609
610 /* Build a new shader. */
611 shader = CALLOC_STRUCT(si_shader);
612 if (!shader) {
613 pipe_mutex_unlock(sel->mutex);
614 return -ENOMEM;
615 }
616 shader->selector = sel;
617 shader->key = key;
618
619 r = si_shader_create(sctx->screen, sctx->tm, shader, &sctx->b.debug);
620 if (unlikely(r)) {
621 R600_ERR("Failed to build shader variant (type=%u) %d\n",
622 sel->type, r);
623 FREE(shader);
624 pipe_mutex_unlock(sel->mutex);
625 return r;
626 }
627 si_shader_init_pm4_state(shader);
628
629 if (!sel->last_variant) {
630 sel->first_variant = shader;
631 sel->last_variant = shader;
632 } else {
633 sel->last_variant->next_variant = shader;
634 sel->last_variant = shader;
635 }
636 state->current = shader;
637 pipe_mutex_unlock(sel->mutex);
638 return 0;
639 }
640
641 static void *si_create_shader_selector(struct pipe_context *ctx,
642 const struct pipe_shader_state *state)
643 {
644 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
645 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
646 int i;
647
648 if (!sel)
649 return NULL;
650
651 sel->tokens = tgsi_dup_tokens(state->tokens);
652 if (!sel->tokens) {
653 FREE(sel);
654 return NULL;
655 }
656
657 sel->so = state->stream_output;
658 tgsi_scan_shader(state->tokens, &sel->info);
659 sel->type = util_pipe_shader_from_tgsi_processor(sel->info.processor);
660 p_atomic_inc(&sscreen->b.num_shaders_created);
661
662 /* First set which opcode uses which (i,j) pair. */
663 if (sel->info.uses_persp_opcode_interp_centroid)
664 sel->info.uses_persp_centroid = true;
665
666 if (sel->info.uses_linear_opcode_interp_centroid)
667 sel->info.uses_linear_centroid = true;
668
669 if (sel->info.uses_persp_opcode_interp_offset ||
670 sel->info.uses_persp_opcode_interp_sample)
671 sel->info.uses_persp_center = true;
672
673 if (sel->info.uses_linear_opcode_interp_offset ||
674 sel->info.uses_linear_opcode_interp_sample)
675 sel->info.uses_linear_center = true;
676
677 /* Determine if the shader has to use a conditional assignment when
678 * emulating force_persample_interp.
679 */
680 sel->forces_persample_interp_for_persp =
681 sel->info.uses_persp_center +
682 sel->info.uses_persp_centroid +
683 sel->info.uses_persp_sample >= 2;
684
685 sel->forces_persample_interp_for_linear =
686 sel->info.uses_linear_center +
687 sel->info.uses_linear_centroid +
688 sel->info.uses_linear_sample >= 2;
689
690 switch (sel->type) {
691 case PIPE_SHADER_GEOMETRY:
692 sel->gs_output_prim =
693 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
694 sel->gs_max_out_vertices =
695 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
696 sel->gs_num_invocations =
697 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
698 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
699 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
700 sel->gs_max_out_vertices;
701
702 sel->max_gs_stream = 0;
703 for (i = 0; i < sel->so.num_outputs; i++)
704 sel->max_gs_stream = MAX2(sel->max_gs_stream,
705 sel->so.output[i].stream);
706
707 sel->gs_input_verts_per_prim =
708 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
709 break;
710
711 case PIPE_SHADER_VERTEX:
712 case PIPE_SHADER_TESS_CTRL:
713 case PIPE_SHADER_TESS_EVAL:
714 for (i = 0; i < sel->info.num_outputs; i++) {
715 unsigned name = sel->info.output_semantic_name[i];
716 unsigned index = sel->info.output_semantic_index[i];
717
718 switch (name) {
719 case TGSI_SEMANTIC_TESSINNER:
720 case TGSI_SEMANTIC_TESSOUTER:
721 case TGSI_SEMANTIC_PATCH:
722 sel->patch_outputs_written |=
723 1llu << si_shader_io_get_unique_index(name, index);
724 break;
725 default:
726 sel->outputs_written |=
727 1llu << si_shader_io_get_unique_index(name, index);
728 }
729 }
730 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
731 break;
732 }
733
734 if (sscreen->b.debug_flags & DBG_PRECOMPILE) {
735 struct si_shader_ctx_state state = {sel};
736
737 if (si_shader_select(ctx, &state)) {
738 fprintf(stderr, "radeonsi: can't create a shader\n");
739 tgsi_free_tokens(sel->tokens);
740 FREE(sel);
741 return NULL;
742 }
743 }
744
745 pipe_mutex_init(sel->mutex);
746 return sel;
747 }
748
749 /**
750 * Normally, we only emit 1 viewport and 1 scissor if no shader is using
751 * the VIEWPORT_INDEX output, and emitting the other viewports and scissors
752 * is delayed. When a shader with VIEWPORT_INDEX appears, this should be
753 * called to emit the rest.
754 */
755 static void si_update_viewports_and_scissors(struct si_context *sctx)
756 {
757 struct tgsi_shader_info *info = si_get_vs_info(sctx);
758
759 if (!info || !info->writes_viewport_index)
760 return;
761
762 if (sctx->scissors.dirty_mask)
763 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
764 if (sctx->viewports.dirty_mask)
765 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
766 }
767
768 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
769 {
770 struct si_context *sctx = (struct si_context *)ctx;
771 struct si_shader_selector *sel = state;
772
773 if (sctx->vs_shader.cso == sel)
774 return;
775
776 sctx->vs_shader.cso = sel;
777 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
778 si_mark_atom_dirty(sctx, &sctx->clip_regs);
779 si_update_viewports_and_scissors(sctx);
780 }
781
782 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
783 {
784 struct si_context *sctx = (struct si_context *)ctx;
785 struct si_shader_selector *sel = state;
786 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
787
788 if (sctx->gs_shader.cso == sel)
789 return;
790
791 sctx->gs_shader.cso = sel;
792 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
793 si_mark_atom_dirty(sctx, &sctx->clip_regs);
794 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
795
796 if (enable_changed)
797 si_shader_change_notify(sctx);
798 si_update_viewports_and_scissors(sctx);
799 }
800
801 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
802 {
803 struct si_context *sctx = (struct si_context *)ctx;
804 struct si_shader_selector *sel = state;
805 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
806
807 if (sctx->tcs_shader.cso == sel)
808 return;
809
810 sctx->tcs_shader.cso = sel;
811 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
812
813 if (enable_changed)
814 sctx->last_tcs = NULL; /* invalidate derived tess state */
815 }
816
817 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
818 {
819 struct si_context *sctx = (struct si_context *)ctx;
820 struct si_shader_selector *sel = state;
821 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
822
823 if (sctx->tes_shader.cso == sel)
824 return;
825
826 sctx->tes_shader.cso = sel;
827 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
828 si_mark_atom_dirty(sctx, &sctx->clip_regs);
829 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
830
831 if (enable_changed) {
832 si_shader_change_notify(sctx);
833 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
834 }
835 si_update_viewports_and_scissors(sctx);
836 }
837
838 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
839 {
840 struct si_context *sctx = (struct si_context *)ctx;
841 struct si_shader_selector *sel = state;
842
843 /* skip if supplied shader is one already in use */
844 if (sctx->ps_shader.cso == sel)
845 return;
846
847 sctx->ps_shader.cso = sel;
848 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
849 si_mark_atom_dirty(sctx, &sctx->cb_target_mask);
850 }
851
852 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
853 {
854 struct si_context *sctx = (struct si_context *)ctx;
855 struct si_shader_selector *sel = (struct si_shader_selector *)state;
856 struct si_shader *p = sel->first_variant, *c;
857 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
858 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
859 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
860 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
861 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
862 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
863 };
864
865 if (current_shader[sel->type]->cso == sel) {
866 current_shader[sel->type]->cso = NULL;
867 current_shader[sel->type]->current = NULL;
868 }
869
870 while (p) {
871 c = p->next_variant;
872 switch (sel->type) {
873 case PIPE_SHADER_VERTEX:
874 if (p->key.vs.as_ls)
875 si_pm4_delete_state(sctx, ls, p->pm4);
876 else if (p->key.vs.as_es)
877 si_pm4_delete_state(sctx, es, p->pm4);
878 else
879 si_pm4_delete_state(sctx, vs, p->pm4);
880 break;
881 case PIPE_SHADER_TESS_CTRL:
882 si_pm4_delete_state(sctx, hs, p->pm4);
883 break;
884 case PIPE_SHADER_TESS_EVAL:
885 if (p->key.tes.as_es)
886 si_pm4_delete_state(sctx, es, p->pm4);
887 else
888 si_pm4_delete_state(sctx, vs, p->pm4);
889 break;
890 case PIPE_SHADER_GEOMETRY:
891 si_pm4_delete_state(sctx, gs, p->pm4);
892 si_pm4_delete_state(sctx, vs, p->gs_copy_shader->pm4);
893 break;
894 case PIPE_SHADER_FRAGMENT:
895 si_pm4_delete_state(sctx, ps, p->pm4);
896 break;
897 }
898
899 si_shader_destroy(p);
900 free(p);
901 p = c;
902 }
903
904 pipe_mutex_destroy(sel->mutex);
905 free(sel->tokens);
906 free(sel);
907 }
908
909 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
910 {
911 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
912 struct si_shader *ps = sctx->ps_shader.current;
913 struct si_shader *vs = si_get_vs_state(sctx);
914 struct tgsi_shader_info *psinfo;
915 struct tgsi_shader_info *vsinfo = &vs->selector->info;
916 unsigned i, j, tmp, num_written = 0;
917
918 if (!ps || !ps->nparam)
919 return;
920
921 psinfo = &ps->selector->info;
922
923 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, ps->nparam);
924
925 for (i = 0; i < psinfo->num_inputs; i++) {
926 unsigned name = psinfo->input_semantic_name[i];
927 unsigned index = psinfo->input_semantic_index[i];
928 unsigned interpolate = psinfo->input_interpolate[i];
929 unsigned param_offset = ps->ps_input_param_offset[i];
930
931 if (name == TGSI_SEMANTIC_POSITION ||
932 name == TGSI_SEMANTIC_FACE)
933 /* Read from preloaded VGPRs, not parameters */
934 continue;
935
936 bcolor:
937 tmp = 0;
938
939 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
940 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
941 tmp |= S_028644_FLAT_SHADE(1);
942
943 if (name == TGSI_SEMANTIC_PCOORD ||
944 (name == TGSI_SEMANTIC_TEXCOORD &&
945 sctx->sprite_coord_enable & (1 << index))) {
946 tmp |= S_028644_PT_SPRITE_TEX(1);
947 }
948
949 for (j = 0; j < vsinfo->num_outputs; j++) {
950 if (name == vsinfo->output_semantic_name[j] &&
951 index == vsinfo->output_semantic_index[j]) {
952 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[j]);
953 break;
954 }
955 }
956
957 if (name == TGSI_SEMANTIC_PRIMID)
958 /* PrimID is written after the last output. */
959 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[vsinfo->num_outputs]);
960 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(tmp)) {
961 /* No corresponding output found, load defaults into input.
962 * Don't set any other bits.
963 * (FLAT_SHADE=1 completely changes behavior) */
964 tmp = S_028644_OFFSET(0x20);
965 }
966
967 assert(param_offset == num_written);
968 radeon_emit(cs, tmp);
969 num_written++;
970
971 if (name == TGSI_SEMANTIC_COLOR &&
972 ps->key.ps.color_two_side) {
973 name = TGSI_SEMANTIC_BCOLOR;
974 param_offset++;
975 goto bcolor;
976 }
977 }
978 assert(ps->nparam == num_written);
979 }
980
981 static void si_emit_spi_ps_input(struct si_context *sctx, struct r600_atom *atom)
982 {
983 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
984 struct si_shader *ps = sctx->ps_shader.current;
985 unsigned input_ena;
986
987 if (!ps)
988 return;
989
990 input_ena = ps->spi_ps_input_ena;
991
992 /* we need to enable at least one of them, otherwise we hang the GPU */
993 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
994 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
995 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
996 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
997 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
998 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
999 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1000 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1001
1002 if (sctx->force_persample_interp) {
1003 unsigned num_persp = G_0286CC_PERSP_SAMPLE_ENA(input_ena) +
1004 G_0286CC_PERSP_CENTER_ENA(input_ena) +
1005 G_0286CC_PERSP_CENTROID_ENA(input_ena);
1006 unsigned num_linear = G_0286CC_LINEAR_SAMPLE_ENA(input_ena) +
1007 G_0286CC_LINEAR_CENTER_ENA(input_ena) +
1008 G_0286CC_LINEAR_CENTROID_ENA(input_ena);
1009
1010 /* If only one set of (i,j) coordinates is used, we can disable
1011 * CENTER/CENTROID, enable SAMPLE and it will load SAMPLE coordinates
1012 * where CENTER/CENTROID are expected, effectively forcing per-sample
1013 * interpolation.
1014 */
1015 if (num_persp == 1) {
1016 input_ena &= C_0286CC_PERSP_CENTER_ENA;
1017 input_ena &= C_0286CC_PERSP_CENTROID_ENA;
1018 input_ena |= G_0286CC_PERSP_SAMPLE_ENA(1);
1019 }
1020 if (num_linear == 1) {
1021 input_ena &= C_0286CC_LINEAR_CENTER_ENA;
1022 input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
1023 input_ena |= G_0286CC_LINEAR_SAMPLE_ENA(1);
1024 }
1025
1026 /* If at least 2 sets of coordinates are used, we can't use this
1027 * trick and have to select SAMPLE using a conditional assignment
1028 * in the shader with "force_persample_interp" being a shader constant.
1029 */
1030 }
1031
1032 radeon_set_context_reg_seq(cs, R_0286CC_SPI_PS_INPUT_ENA, 2);
1033 radeon_emit(cs, input_ena);
1034 radeon_emit(cs, input_ena);
1035
1036 if (ps->selector->forces_persample_interp_for_persp ||
1037 ps->selector->forces_persample_interp_for_linear)
1038 radeon_set_sh_reg(cs, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1039 SI_SGPR_PS_STATE_BITS * 4,
1040 sctx->force_persample_interp);
1041 }
1042
1043 /**
1044 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
1045 */
1046 static void si_init_config_add_vgt_flush(struct si_context *sctx)
1047 {
1048 if (sctx->init_config_has_vgt_flush)
1049 return;
1050
1051 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
1052 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
1053 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1054 si_pm4_cmd_end(sctx->init_config, false);
1055 sctx->init_config_has_vgt_flush = true;
1056 }
1057
1058 /* Initialize state related to ESGS / GSVS ring buffers */
1059 static bool si_update_gs_ring_buffers(struct si_context *sctx)
1060 {
1061 struct si_shader_selector *es =
1062 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
1063 struct si_shader_selector *gs = sctx->gs_shader.cso;
1064 struct si_pm4_state *pm4;
1065
1066 /* Chip constants. */
1067 unsigned num_se = sctx->screen->b.info.max_se;
1068 unsigned wave_size = 64;
1069 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1070 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1071 unsigned alignment = 256 * num_se;
1072 /* The maximum size is 63.999 MB per SE. */
1073 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1074
1075 /* Calculate the minimum size. */
1076 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
1077 wave_size, alignment);
1078
1079 /* These are recommended sizes, not minimum sizes. */
1080 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1081 es->esgs_itemsize * gs->gs_input_verts_per_prim;
1082 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1083 gs->max_gsvs_emit_size * (gs->max_gs_stream + 1);
1084
1085 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1086 esgs_ring_size = align(esgs_ring_size, alignment);
1087 gsvs_ring_size = align(gsvs_ring_size, alignment);
1088
1089 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1090 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1091
1092 /* Some rings don't have to be allocated if shaders don't use them.
1093 * (e.g. no varyings between ES and GS or GS and VS)
1094 */
1095 bool update_esgs = esgs_ring_size &&
1096 (!sctx->esgs_ring ||
1097 sctx->esgs_ring->width0 < esgs_ring_size);
1098 bool update_gsvs = gsvs_ring_size &&
1099 (!sctx->gsvs_ring ||
1100 sctx->gsvs_ring->width0 < gsvs_ring_size);
1101
1102 if (!update_esgs && !update_gsvs)
1103 return true;
1104
1105 if (update_esgs) {
1106 pipe_resource_reference(&sctx->esgs_ring, NULL);
1107 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1108 PIPE_USAGE_DEFAULT,
1109 esgs_ring_size);
1110 if (!sctx->esgs_ring)
1111 return false;
1112 }
1113
1114 if (update_gsvs) {
1115 pipe_resource_reference(&sctx->gsvs_ring, NULL);
1116 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1117 PIPE_USAGE_DEFAULT,
1118 gsvs_ring_size);
1119 if (!sctx->gsvs_ring)
1120 return false;
1121 }
1122
1123 /* Create the "init_config_gs_rings" state. */
1124 pm4 = CALLOC_STRUCT(si_pm4_state);
1125 if (!pm4)
1126 return false;
1127
1128 if (sctx->b.chip_class >= CIK) {
1129 if (sctx->esgs_ring)
1130 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
1131 sctx->esgs_ring->width0 / 256);
1132 if (sctx->gsvs_ring)
1133 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
1134 sctx->gsvs_ring->width0 / 256);
1135 } else {
1136 if (sctx->esgs_ring)
1137 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
1138 sctx->esgs_ring->width0 / 256);
1139 if (sctx->gsvs_ring)
1140 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
1141 sctx->gsvs_ring->width0 / 256);
1142 }
1143
1144 /* Set the state. */
1145 if (sctx->init_config_gs_rings)
1146 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
1147 sctx->init_config_gs_rings = pm4;
1148
1149 if (!sctx->init_config_has_vgt_flush) {
1150 si_init_config_add_vgt_flush(sctx);
1151 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1152 }
1153
1154 /* Flush the context to re-emit both init_config states. */
1155 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1156 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1157
1158 /* Set ring bindings. */
1159 if (sctx->esgs_ring) {
1160 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
1161 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1162 true, true, 4, 64, 0);
1163 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
1164 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1165 false, false, 0, 0, 0);
1166 }
1167 if (sctx->gsvs_ring)
1168 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
1169 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
1170 false, false, 0, 0, 0);
1171 return true;
1172 }
1173
1174 static void si_update_gsvs_ring_bindings(struct si_context *sctx)
1175 {
1176 unsigned gsvs_itemsize = sctx->gs_shader.cso->max_gsvs_emit_size;
1177 uint64_t offset;
1178
1179 if (!sctx->gsvs_ring || gsvs_itemsize == sctx->last_gsvs_itemsize)
1180 return;
1181
1182 sctx->last_gsvs_itemsize = gsvs_itemsize;
1183
1184 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
1185 sctx->gsvs_ring, gsvs_itemsize,
1186 64, true, true, 4, 16, 0);
1187
1188 offset = gsvs_itemsize * 64;
1189 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_1,
1190 sctx->gsvs_ring, gsvs_itemsize,
1191 64, true, true, 4, 16, offset);
1192
1193 offset = (gsvs_itemsize * 2) * 64;
1194 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_2,
1195 sctx->gsvs_ring, gsvs_itemsize,
1196 64, true, true, 4, 16, offset);
1197
1198 offset = (gsvs_itemsize * 3) * 64;
1199 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_3,
1200 sctx->gsvs_ring, gsvs_itemsize,
1201 64, true, true, 4, 16, offset);
1202 }
1203
1204 /**
1205 * @returns 1 if \p sel has been updated to use a new scratch buffer
1206 * 0 if not
1207 * < 0 if there was a failure
1208 */
1209 static int si_update_scratch_buffer(struct si_context *sctx,
1210 struct si_shader *shader)
1211 {
1212 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
1213 int r;
1214
1215 if (!shader)
1216 return 0;
1217
1218 /* This shader doesn't need a scratch buffer */
1219 if (shader->scratch_bytes_per_wave == 0)
1220 return 0;
1221
1222 /* This shader is already configured to use the current
1223 * scratch buffer. */
1224 if (shader->scratch_bo == sctx->scratch_buffer)
1225 return 0;
1226
1227 assert(sctx->scratch_buffer);
1228
1229 si_shader_apply_scratch_relocs(sctx, shader, scratch_va);
1230
1231 /* Replace the shader bo with a new bo that has the relocs applied. */
1232 r = si_shader_binary_upload(sctx->screen, shader);
1233 if (r)
1234 return r;
1235
1236 /* Update the shader state to use the new shader bo. */
1237 si_shader_init_pm4_state(shader);
1238
1239 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
1240
1241 return 1;
1242 }
1243
1244 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
1245 {
1246 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
1247 }
1248
1249 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
1250 {
1251 return shader ? shader->scratch_bytes_per_wave : 0;
1252 }
1253
1254 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
1255 {
1256 unsigned bytes = 0;
1257
1258 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
1259 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
1260 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
1261 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tcs_shader.current));
1262 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
1263 return bytes;
1264 }
1265
1266 static bool si_update_spi_tmpring_size(struct si_context *sctx)
1267 {
1268 unsigned current_scratch_buffer_size =
1269 si_get_current_scratch_buffer_size(sctx);
1270 unsigned scratch_bytes_per_wave =
1271 si_get_max_scratch_bytes_per_wave(sctx);
1272 unsigned scratch_needed_size = scratch_bytes_per_wave *
1273 sctx->scratch_waves;
1274 int r;
1275
1276 if (scratch_needed_size > 0) {
1277 if (scratch_needed_size > current_scratch_buffer_size) {
1278 /* Create a bigger scratch buffer */
1279 pipe_resource_reference(
1280 (struct pipe_resource**)&sctx->scratch_buffer,
1281 NULL);
1282
1283 sctx->scratch_buffer =
1284 si_resource_create_custom(&sctx->screen->b.b,
1285 PIPE_USAGE_DEFAULT, scratch_needed_size);
1286 if (!sctx->scratch_buffer)
1287 return false;
1288 sctx->emit_scratch_reloc = true;
1289 }
1290
1291 /* Update the shaders, so they are using the latest scratch. The
1292 * scratch buffer may have been changed since these shaders were
1293 * last used, so we still need to try to update them, even if
1294 * they require scratch buffers smaller than the current size.
1295 */
1296 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
1297 if (r < 0)
1298 return false;
1299 if (r == 1)
1300 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
1301
1302 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
1303 if (r < 0)
1304 return false;
1305 if (r == 1)
1306 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1307
1308 r = si_update_scratch_buffer(sctx, sctx->tcs_shader.current);
1309 if (r < 0)
1310 return false;
1311 if (r == 1)
1312 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1313
1314 /* VS can be bound as LS, ES, or VS. */
1315 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
1316 if (r < 0)
1317 return false;
1318 if (r == 1) {
1319 if (sctx->tes_shader.current)
1320 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1321 else if (sctx->gs_shader.current)
1322 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1323 else
1324 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1325 }
1326
1327 /* TES can be bound as ES or VS. */
1328 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
1329 if (r < 0)
1330 return false;
1331 if (r == 1) {
1332 if (sctx->gs_shader.current)
1333 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1334 else
1335 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1336 }
1337 }
1338
1339 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
1340 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
1341 "scratch size should already be aligned correctly.");
1342
1343 sctx->spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
1344 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
1345 return true;
1346 }
1347
1348 static void si_init_tess_factor_ring(struct si_context *sctx)
1349 {
1350 assert(!sctx->tf_ring);
1351
1352 sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1353 PIPE_USAGE_DEFAULT,
1354 32768 * sctx->screen->b.info.max_se);
1355 if (!sctx->tf_ring)
1356 return;
1357
1358 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
1359
1360 si_init_config_add_vgt_flush(sctx);
1361
1362 /* Append these registers to the init config state. */
1363 if (sctx->b.chip_class >= CIK) {
1364 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
1365 S_030938_SIZE(sctx->tf_ring->width0 / 4));
1366 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
1367 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1368 } else {
1369 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
1370 S_008988_SIZE(sctx->tf_ring->width0 / 4));
1371 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
1372 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1373 }
1374
1375 /* Flush the context to re-emit the init_config state.
1376 * This is done only once in a lifetime of a context.
1377 */
1378 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1379 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1380 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1381
1382 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_TESS_CTRL,
1383 SI_RING_TESS_FACTOR, sctx->tf_ring, 0,
1384 sctx->tf_ring->width0, false, false, 0, 0, 0);
1385 }
1386
1387 /**
1388 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
1389 * VS passes its outputs to TES directly, so the fixed-function shader only
1390 * has to write TESSOUTER and TESSINNER.
1391 */
1392 static void si_generate_fixed_func_tcs(struct si_context *sctx)
1393 {
1394 struct ureg_src const0, const1;
1395 struct ureg_dst tessouter, tessinner;
1396 struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
1397
1398 if (!ureg)
1399 return; /* if we get here, we're screwed */
1400
1401 assert(!sctx->fixed_func_tcs_shader.cso);
1402
1403 ureg_DECL_constant2D(ureg, 0, 1, SI_DRIVER_STATE_CONST_BUF);
1404 const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 0),
1405 SI_DRIVER_STATE_CONST_BUF);
1406 const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 1),
1407 SI_DRIVER_STATE_CONST_BUF);
1408
1409 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1410 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1411
1412 ureg_MOV(ureg, tessouter, const0);
1413 ureg_MOV(ureg, tessinner, const1);
1414 ureg_END(ureg);
1415
1416 sctx->fixed_func_tcs_shader.cso =
1417 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
1418 }
1419
1420 static void si_update_vgt_shader_config(struct si_context *sctx)
1421 {
1422 /* Calculate the index of the config.
1423 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
1424 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
1425 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
1426
1427 if (!*pm4) {
1428 uint32_t stages = 0;
1429
1430 *pm4 = CALLOC_STRUCT(si_pm4_state);
1431
1432 if (sctx->tes_shader.cso) {
1433 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
1434 S_028B54_HS_EN(1);
1435
1436 if (sctx->gs_shader.cso)
1437 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
1438 S_028B54_GS_EN(1) |
1439 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1440 else
1441 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
1442 } else if (sctx->gs_shader.cso) {
1443 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1444 S_028B54_GS_EN(1) |
1445 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1446 }
1447
1448 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
1449 }
1450 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
1451 }
1452
1453 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
1454 {
1455 struct pipe_stream_output_info *so = &shader->so;
1456 uint32_t enabled_stream_buffers_mask = 0;
1457 int i;
1458
1459 for (i = 0; i < so->num_outputs; i++)
1460 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
1461 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
1462 sctx->b.streamout.stride_in_dw = shader->so.stride;
1463 }
1464
1465 bool si_update_shaders(struct si_context *sctx)
1466 {
1467 struct pipe_context *ctx = (struct pipe_context*)sctx;
1468 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1469 int r;
1470
1471 /* Update stages before GS. */
1472 if (sctx->tes_shader.cso) {
1473 if (!sctx->tf_ring) {
1474 si_init_tess_factor_ring(sctx);
1475 if (!sctx->tf_ring)
1476 return false;
1477 }
1478
1479 /* VS as LS */
1480 r = si_shader_select(ctx, &sctx->vs_shader);
1481 if (r)
1482 return false;
1483 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1484
1485 if (sctx->tcs_shader.cso) {
1486 r = si_shader_select(ctx, &sctx->tcs_shader);
1487 if (r)
1488 return false;
1489 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1490 } else {
1491 if (!sctx->fixed_func_tcs_shader.cso) {
1492 si_generate_fixed_func_tcs(sctx);
1493 if (!sctx->fixed_func_tcs_shader.cso)
1494 return false;
1495 }
1496
1497 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader);
1498 if (r)
1499 return false;
1500 si_pm4_bind_state(sctx, hs,
1501 sctx->fixed_func_tcs_shader.current->pm4);
1502 }
1503
1504 r = si_shader_select(ctx, &sctx->tes_shader);
1505 if (r)
1506 return false;
1507
1508 if (sctx->gs_shader.cso) {
1509 /* TES as ES */
1510 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1511 } else {
1512 /* TES as VS */
1513 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1514 si_update_so(sctx, sctx->tes_shader.cso);
1515 }
1516 } else if (sctx->gs_shader.cso) {
1517 /* VS as ES */
1518 r = si_shader_select(ctx, &sctx->vs_shader);
1519 if (r)
1520 return false;
1521 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1522 } else {
1523 /* VS as VS */
1524 r = si_shader_select(ctx, &sctx->vs_shader);
1525 if (r)
1526 return false;
1527 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1528 si_update_so(sctx, sctx->vs_shader.cso);
1529 }
1530
1531 /* Update GS. */
1532 if (sctx->gs_shader.cso) {
1533 r = si_shader_select(ctx, &sctx->gs_shader);
1534 if (r)
1535 return false;
1536 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1537 si_pm4_bind_state(sctx, vs, sctx->gs_shader.current->gs_copy_shader->pm4);
1538 si_update_so(sctx, sctx->gs_shader.cso);
1539
1540 if (!si_update_gs_ring_buffers(sctx))
1541 return false;
1542
1543 si_update_gsvs_ring_bindings(sctx);
1544 } else {
1545 si_pm4_bind_state(sctx, gs, NULL);
1546 si_pm4_bind_state(sctx, es, NULL);
1547 }
1548
1549 si_update_vgt_shader_config(sctx);
1550
1551 if (sctx->ps_shader.cso) {
1552 r = si_shader_select(ctx, &sctx->ps_shader);
1553 if (r)
1554 return false;
1555 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
1556
1557 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
1558 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
1559 sctx->flatshade != rs->flatshade) {
1560 sctx->sprite_coord_enable = rs->sprite_coord_enable;
1561 sctx->flatshade = rs->flatshade;
1562 si_mark_atom_dirty(sctx, &sctx->spi_map);
1563 }
1564
1565 if (si_pm4_state_changed(sctx, ps) ||
1566 sctx->force_persample_interp != rs->force_persample_interp) {
1567 sctx->force_persample_interp = rs->force_persample_interp;
1568 si_mark_atom_dirty(sctx, &sctx->spi_ps_input);
1569 }
1570
1571 if (sctx->ps_db_shader_control != sctx->ps_shader.current->db_shader_control) {
1572 sctx->ps_db_shader_control = sctx->ps_shader.current->db_shader_control;
1573 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1574 }
1575
1576 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.ps.poly_line_smoothing) {
1577 sctx->smoothing_enabled = sctx->ps_shader.current->key.ps.poly_line_smoothing;
1578 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1579
1580 if (sctx->b.chip_class == SI)
1581 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1582 }
1583 }
1584
1585 if (si_pm4_state_changed(sctx, ls) ||
1586 si_pm4_state_changed(sctx, hs) ||
1587 si_pm4_state_changed(sctx, es) ||
1588 si_pm4_state_changed(sctx, gs) ||
1589 si_pm4_state_changed(sctx, vs) ||
1590 si_pm4_state_changed(sctx, ps)) {
1591 if (!si_update_spi_tmpring_size(sctx))
1592 return false;
1593 }
1594 return true;
1595 }
1596
1597 void si_init_shader_functions(struct si_context *sctx)
1598 {
1599 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
1600 si_init_atom(sctx, &sctx->spi_ps_input, &sctx->atoms.s.spi_ps_input, si_emit_spi_ps_input);
1601
1602 sctx->b.b.create_vs_state = si_create_shader_selector;
1603 sctx->b.b.create_tcs_state = si_create_shader_selector;
1604 sctx->b.b.create_tes_state = si_create_shader_selector;
1605 sctx->b.b.create_gs_state = si_create_shader_selector;
1606 sctx->b.b.create_fs_state = si_create_shader_selector;
1607
1608 sctx->b.b.bind_vs_state = si_bind_vs_shader;
1609 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
1610 sctx->b.b.bind_tes_state = si_bind_tes_shader;
1611 sctx->b.b.bind_gs_state = si_bind_gs_shader;
1612 sctx->b.b.bind_fs_state = si_bind_ps_shader;
1613
1614 sctx->b.b.delete_vs_state = si_delete_shader_selector;
1615 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
1616 sctx->b.b.delete_tes_state = si_delete_shader_selector;
1617 sctx->b.b.delete_gs_state = si_delete_shader_selector;
1618 sctx->b.b.delete_fs_state = si_delete_shader_selector;
1619 }