2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "util/hash_table.h"
32 #include "util/crc32.h"
33 #include "util/u_async_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
37 #include "util/disk_cache.h"
38 #include "util/mesa-sha1.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
45 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
48 void *si_get_ir_binary(struct si_shader_selector
*sel
, bool ngg
, bool es
)
55 ir_binary
= sel
->tokens
;
56 ir_size
= tgsi_num_tokens(sel
->tokens
) *
57 sizeof(struct tgsi_token
);
62 nir_serialize(&blob
, sel
->nir
);
63 ir_binary
= blob
.data
;
67 /* These settings affect the compilation, but they are not derived
68 * from the input shader IR.
70 unsigned shader_variant_flags
= 0;
73 shader_variant_flags
|= 1 << 0;
75 shader_variant_flags
|= 1 << 1;
76 if (si_get_wave_size(sel
->screen
, sel
->type
, ngg
, es
) == 32)
77 shader_variant_flags
|= 1 << 2;
78 if (sel
->force_correct_derivs_after_kill
)
79 shader_variant_flags
|= 1 << 3;
81 unsigned size
= 4 + 4 + ir_size
+ sizeof(sel
->so
);
82 char *result
= (char*)MALLOC(size
);
86 ((uint32_t*)result
)[0] = size
;
87 ((uint32_t*)result
)[1] = shader_variant_flags
;
88 memcpy(result
+ 8, ir_binary
, ir_size
);
89 memcpy(result
+ 8 + ir_size
, &sel
->so
, sizeof(sel
->so
));
97 /** Copy "data" to "ptr" and return the next dword following copied data. */
98 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
100 /* data may be NULL if size == 0 */
102 memcpy(ptr
, data
, size
);
103 ptr
+= DIV_ROUND_UP(size
, 4);
107 /** Read data from "ptr". Return the next dword following the data. */
108 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
110 memcpy(data
, ptr
, size
);
111 ptr
+= DIV_ROUND_UP(size
, 4);
116 * Write the size as uint followed by the data. Return the next dword
117 * following the copied data.
119 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
122 return write_data(ptr
, data
, size
);
126 * Read the size as uint followed by the data. Return both via parameters.
127 * Return the next dword following the data.
129 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
132 assert(*data
== NULL
);
135 *data
= malloc(*size
);
136 return read_data(ptr
, *data
, *size
);
140 * Return the shader binary in a buffer. The first 4 bytes contain its size
143 static void *si_get_shader_binary(struct si_shader
*shader
)
145 /* There is always a size of data followed by the data itself. */
146 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
147 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
149 /* Refuse to allocate overly large buffers and guard against integer
151 if (shader
->binary
.elf_size
> UINT_MAX
/ 4 ||
152 llvm_ir_size
> UINT_MAX
/ 4)
157 4 + /* CRC32 of the data below */
158 align(sizeof(shader
->config
), 4) +
159 align(sizeof(shader
->info
), 4) +
160 4 + align(shader
->binary
.elf_size
, 4) +
161 4 + align(llvm_ir_size
, 4);
162 void *buffer
= CALLOC(1, size
);
163 uint32_t *ptr
= (uint32_t*)buffer
;
169 ptr
++; /* CRC32 is calculated at the end. */
171 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
172 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
173 ptr
= write_chunk(ptr
, shader
->binary
.elf_buffer
, shader
->binary
.elf_size
);
174 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
175 assert((char *)ptr
- (char *)buffer
== size
);
178 ptr
= (uint32_t*)buffer
;
180 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
185 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
187 uint32_t *ptr
= (uint32_t*)binary
;
188 uint32_t size
= *ptr
++;
189 uint32_t crc32
= *ptr
++;
193 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
194 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
198 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
199 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
200 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.elf_buffer
,
202 shader
->binary
.elf_size
= elf_size
;
203 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
209 * Insert a shader into the cache. It's assumed the shader is not in the cache.
210 * Use si_shader_cache_load_shader before calling this.
212 * Returns false on failure, in which case the ir_binary should be freed.
214 bool si_shader_cache_insert_shader(struct si_screen
*sscreen
, void *ir_binary
,
215 struct si_shader
*shader
,
216 bool insert_into_disk_cache
)
219 struct hash_entry
*entry
;
220 uint8_t key
[CACHE_KEY_SIZE
];
222 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
224 return false; /* already added */
226 hw_binary
= si_get_shader_binary(shader
);
230 if (_mesa_hash_table_insert(sscreen
->shader_cache
, ir_binary
,
231 hw_binary
) == NULL
) {
236 if (sscreen
->disk_shader_cache
&& insert_into_disk_cache
) {
237 disk_cache_compute_key(sscreen
->disk_shader_cache
, ir_binary
,
238 *((uint32_t *)ir_binary
), key
);
239 disk_cache_put(sscreen
->disk_shader_cache
, key
, hw_binary
,
240 *((uint32_t *) hw_binary
), NULL
);
246 bool si_shader_cache_load_shader(struct si_screen
*sscreen
, void *ir_binary
,
247 struct si_shader
*shader
)
249 struct hash_entry
*entry
=
250 _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
252 if (sscreen
->disk_shader_cache
) {
253 unsigned char sha1
[CACHE_KEY_SIZE
];
254 size_t tg_size
= *((uint32_t *) ir_binary
);
256 disk_cache_compute_key(sscreen
->disk_shader_cache
,
257 ir_binary
, tg_size
, sha1
);
261 disk_cache_get(sscreen
->disk_shader_cache
,
266 if (binary_size
< sizeof(uint32_t) ||
267 *((uint32_t*)buffer
) != binary_size
) {
268 /* Something has gone wrong discard the item
269 * from the cache and rebuild/link from
272 assert(!"Invalid radeonsi shader disk cache "
275 disk_cache_remove(sscreen
->disk_shader_cache
,
282 if (!si_load_shader_binary(shader
, buffer
)) {
288 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
,
295 if (si_load_shader_binary(shader
, entry
->data
))
300 p_atomic_inc(&sscreen
->num_shader_cache_hits
);
304 static uint32_t si_shader_cache_key_hash(const void *key
)
306 /* The first dword is the key size. */
307 return util_hash_crc32(key
, *(uint32_t*)key
);
310 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
312 uint32_t *keya
= (uint32_t*)a
;
313 uint32_t *keyb
= (uint32_t*)b
;
315 /* The first dword is the key size. */
319 return memcmp(keya
, keyb
, *keya
) == 0;
322 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
324 FREE((void*)entry
->key
);
328 bool si_init_shader_cache(struct si_screen
*sscreen
)
330 (void) mtx_init(&sscreen
->shader_cache_mutex
, mtx_plain
);
331 sscreen
->shader_cache
=
332 _mesa_hash_table_create(NULL
,
333 si_shader_cache_key_hash
,
334 si_shader_cache_key_equals
);
336 return sscreen
->shader_cache
!= NULL
;
339 void si_destroy_shader_cache(struct si_screen
*sscreen
)
341 if (sscreen
->shader_cache
)
342 _mesa_hash_table_destroy(sscreen
->shader_cache
,
343 si_destroy_shader_cache_entry
);
344 mtx_destroy(&sscreen
->shader_cache_mutex
);
349 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
350 const struct si_shader_selector
*tes
,
351 struct si_pm4_state
*pm4
)
353 const struct tgsi_shader_info
*info
= &tes
->info
;
354 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
355 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
356 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
357 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
358 unsigned type
, partitioning
, topology
, distribution_mode
;
360 switch (tes_prim_mode
) {
361 case PIPE_PRIM_LINES
:
362 type
= V_028B6C_TESS_ISOLINE
;
364 case PIPE_PRIM_TRIANGLES
:
365 type
= V_028B6C_TESS_TRIANGLE
;
367 case PIPE_PRIM_QUADS
:
368 type
= V_028B6C_TESS_QUAD
;
375 switch (tes_spacing
) {
376 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
377 partitioning
= V_028B6C_PART_FRAC_ODD
;
379 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
380 partitioning
= V_028B6C_PART_FRAC_EVEN
;
382 case PIPE_TESS_SPACING_EQUAL
:
383 partitioning
= V_028B6C_PART_INTEGER
;
391 topology
= V_028B6C_OUTPUT_POINT
;
392 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
393 topology
= V_028B6C_OUTPUT_LINE
;
394 else if (tes_vertex_order_cw
)
395 /* for some reason, this must be the other way around */
396 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
398 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
400 if (sscreen
->info
.has_distributed_tess
) {
401 if (sscreen
->info
.family
== CHIP_FIJI
||
402 sscreen
->info
.family
>= CHIP_POLARIS10
)
403 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
405 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
407 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
410 pm4
->shader
->vgt_tf_param
= S_028B6C_TYPE(type
) |
411 S_028B6C_PARTITIONING(partitioning
) |
412 S_028B6C_TOPOLOGY(topology
) |
413 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
416 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
417 * whether the "fractional odd" tessellation spacing is used.
419 * Possible VGT configurations and which state should set the register:
421 * Reg set in | VGT shader configuration | Value
422 * ------------------------------------------------------
424 * VS as ES | ES -> GS -> VS | 30
425 * TES as VS | LS -> HS -> VS | 14 or 30
426 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
428 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
430 static void polaris_set_vgt_vertex_reuse(struct si_screen
*sscreen
,
431 struct si_shader_selector
*sel
,
432 struct si_shader
*shader
,
433 struct si_pm4_state
*pm4
)
435 unsigned type
= sel
->type
;
437 if (sscreen
->info
.family
< CHIP_POLARIS10
||
438 sscreen
->info
.chip_class
>= GFX10
)
441 /* VS as VS, or VS as ES: */
442 if ((type
== PIPE_SHADER_VERTEX
&&
444 (!shader
->key
.as_ls
&& !shader
->is_gs_copy_shader
))) ||
445 /* TES as VS, or TES as ES: */
446 type
== PIPE_SHADER_TESS_EVAL
) {
447 unsigned vtx_reuse_depth
= 30;
449 if (type
== PIPE_SHADER_TESS_EVAL
&&
450 sel
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] ==
451 PIPE_TESS_SPACING_FRACTIONAL_ODD
)
452 vtx_reuse_depth
= 14;
455 pm4
->shader
->vgt_vertex_reuse_block_cntl
= vtx_reuse_depth
;
459 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
462 si_pm4_clear_state(shader
->pm4
);
464 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
467 shader
->pm4
->shader
= shader
;
470 fprintf(stderr
, "radeonsi: Failed to create pm4 state.\n");
475 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs
)
477 /* Add the pointer to VBO descriptors. */
478 return num_always_on_user_sgprs
+ 1;
481 static void si_shader_ls(struct si_screen
*sscreen
, struct si_shader
*shader
)
483 struct si_pm4_state
*pm4
;
484 unsigned vgpr_comp_cnt
;
487 assert(sscreen
->info
.chip_class
<= GFX8
);
489 pm4
= si_get_shader_pm4_state(shader
);
493 va
= shader
->bo
->gpu_address
;
494 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
496 /* We need at least 2 components for LS.
497 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
498 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
500 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
502 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
503 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
505 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
506 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
507 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt
) |
508 S_00B528_DX10_CLAMP(1) |
509 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
510 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
)) |
511 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
514 static void si_shader_hs(struct si_screen
*sscreen
, struct si_shader
*shader
)
516 struct si_pm4_state
*pm4
;
518 unsigned ls_vgpr_comp_cnt
= 0;
520 pm4
= si_get_shader_pm4_state(shader
);
524 va
= shader
->bo
->gpu_address
;
525 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
527 if (sscreen
->info
.chip_class
>= GFX9
) {
528 if (sscreen
->info
.chip_class
>= GFX10
) {
529 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
530 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
532 si_pm4_set_reg(pm4
, R_00B410_SPI_SHADER_PGM_LO_LS
, va
>> 8);
533 si_pm4_set_reg(pm4
, R_00B414_SPI_SHADER_PGM_HI_LS
, S_00B414_MEM_BASE(va
>> 40));
536 /* We need at least 2 components for LS.
537 * GFX9 VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
538 * GFX10 VGPR0-3: (VertexID, RelAutoindex, UserVGPR1, InstanceID).
539 * On gfx9, StepRate0 is set to 1 so that VGPR3 doesn't have to
542 ls_vgpr_comp_cnt
= 1;
543 if (shader
->info
.uses_instanceid
) {
544 if (sscreen
->info
.chip_class
>= GFX10
)
545 ls_vgpr_comp_cnt
= 3;
547 ls_vgpr_comp_cnt
= 2;
550 unsigned num_user_sgprs
=
551 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR
);
553 shader
->config
.rsrc2
=
554 S_00B42C_USER_SGPR(num_user_sgprs
) |
555 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
557 if (sscreen
->info
.chip_class
>= GFX10
)
558 shader
->config
.rsrc2
|= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
560 shader
->config
.rsrc2
|= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
562 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
563 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, S_00B424_MEM_BASE(va
>> 40));
565 shader
->config
.rsrc2
=
566 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR
) |
567 S_00B42C_OC_LDS_EN(1) |
568 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
571 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
572 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) /
573 (sscreen
->ge_wave_size
== 32 ? 8 : 4)) |
574 (sscreen
->info
.chip_class
<= GFX9
?
575 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) : 0) |
576 S_00B428_DX10_CLAMP(1) |
577 S_00B428_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
578 S_00B428_WGP_MODE(sscreen
->info
.chip_class
>= GFX10
) |
579 S_00B428_FLOAT_MODE(shader
->config
.float_mode
) |
580 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt
));
582 if (sscreen
->info
.chip_class
<= GFX8
) {
583 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
584 shader
->config
.rsrc2
);
588 static void si_emit_shader_es(struct si_context
*sctx
)
590 struct si_shader
*shader
= sctx
->queued
.named
.es
->shader
;
591 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
596 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
597 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
598 shader
->selector
->esgs_itemsize
/ 4);
600 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
601 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
602 SI_TRACKED_VGT_TF_PARAM
,
603 shader
->vgt_tf_param
);
605 if (shader
->vgt_vertex_reuse_block_cntl
)
606 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
607 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
608 shader
->vgt_vertex_reuse_block_cntl
);
610 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
611 sctx
->context_roll
= true;
614 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
616 struct si_pm4_state
*pm4
;
617 unsigned num_user_sgprs
;
618 unsigned vgpr_comp_cnt
;
622 assert(sscreen
->info
.chip_class
<= GFX8
);
624 pm4
= si_get_shader_pm4_state(shader
);
628 pm4
->atom
.emit
= si_emit_shader_es
;
629 va
= shader
->bo
->gpu_address
;
630 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
632 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
633 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
634 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
635 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
636 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
637 vgpr_comp_cnt
= shader
->selector
->info
.uses_primid
? 3 : 2;
638 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
640 unreachable("invalid shader selector type");
642 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
644 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
645 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
646 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
647 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
648 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
649 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
650 S_00B328_DX10_CLAMP(1) |
651 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
652 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
653 S_00B32C_USER_SGPR(num_user_sgprs
) |
654 S_00B32C_OC_LDS_EN(oc_lds_en
) |
655 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
657 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
658 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
660 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
663 void gfx9_get_gs_info(struct si_shader_selector
*es
,
664 struct si_shader_selector
*gs
,
665 struct gfx9_gs_info
*out
)
667 unsigned gs_num_invocations
= MAX2(gs
->gs_num_invocations
, 1);
668 unsigned input_prim
= gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
669 bool uses_adjacency
= input_prim
>= PIPE_PRIM_LINES_ADJACENCY
&&
670 input_prim
<= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
;
672 /* All these are in dwords: */
673 /* We can't allow using the whole LDS, because GS waves compete with
674 * other shader stages for LDS space. */
675 const unsigned max_lds_size
= 8 * 1024;
676 const unsigned esgs_itemsize
= es
->esgs_itemsize
/ 4;
677 unsigned esgs_lds_size
;
679 /* All these are per subgroup: */
680 const unsigned max_out_prims
= 32 * 1024;
681 const unsigned max_es_verts
= 255;
682 const unsigned ideal_gs_prims
= 64;
683 unsigned max_gs_prims
, gs_prims
;
684 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
686 if (uses_adjacency
|| gs_num_invocations
> 1)
687 max_gs_prims
= 127 / gs_num_invocations
;
691 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
692 * Make sure we don't go over the maximum value.
694 if (gs
->gs_max_out_vertices
> 0) {
695 max_gs_prims
= MIN2(max_gs_prims
,
697 (gs
->gs_max_out_vertices
* gs_num_invocations
));
699 assert(max_gs_prims
> 0);
701 /* If the primitive has adjacency, halve the number of vertices
702 * that will be reused in multiple primitives.
704 min_es_verts
= gs
->gs_input_verts_per_prim
/ (uses_adjacency
? 2 : 1);
706 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
707 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
709 /* Compute ESGS LDS size based on the worst case number of ES vertices
710 * needed to create the target number of GS prims per subgroup.
712 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
714 /* If total LDS usage is too big, refactor partitions based on ratio
715 * of ESGS item sizes.
717 if (esgs_lds_size
> max_lds_size
) {
718 /* Our target GS Prims Per Subgroup was too large. Calculate
719 * the maximum number of GS Prims Per Subgroup that will fit
720 * into LDS, capped by the maximum that the hardware can support.
722 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
724 assert(gs_prims
> 0);
725 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
728 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
729 assert(esgs_lds_size
<= max_lds_size
);
732 /* Now calculate remaining ESGS information. */
734 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
736 es_verts
= max_es_verts
;
738 /* Vertices for adjacency primitives are not always reused, so restore
739 * it for ES_VERTS_PER_SUBGRP.
741 min_es_verts
= gs
->gs_input_verts_per_prim
;
743 /* For normal primitives, the VGT only checks if they are past the ES
744 * verts per subgroup after allocating a full GS primitive and if they
745 * are, kick off a new subgroup. But if those additional ES verts are
746 * unique (e.g. not reused) we need to make sure there is enough LDS
747 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
749 es_verts
-= min_es_verts
- 1;
751 out
->es_verts_per_subgroup
= es_verts
;
752 out
->gs_prims_per_subgroup
= gs_prims
;
753 out
->gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
754 out
->max_prims_per_subgroup
= out
->gs_inst_prims_in_subgroup
*
755 gs
->gs_max_out_vertices
;
756 out
->esgs_ring_size
= 4 * esgs_lds_size
;
758 assert(out
->max_prims_per_subgroup
<= max_out_prims
);
761 static void si_emit_shader_gs(struct si_context
*sctx
)
763 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
764 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
769 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
770 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
771 radeon_opt_set_context_reg3(sctx
, R_028A60_VGT_GSVS_RING_OFFSET_1
,
772 SI_TRACKED_VGT_GSVS_RING_OFFSET_1
,
773 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
,
774 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
,
775 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
);
777 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
778 radeon_opt_set_context_reg(sctx
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
,
779 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE
,
780 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
);
782 /* R_028B38_VGT_GS_MAX_VERT_OUT */
783 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
784 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
785 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
);
787 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
788 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
789 radeon_opt_set_context_reg4(sctx
, R_028B5C_VGT_GS_VERT_ITEMSIZE
,
790 SI_TRACKED_VGT_GS_VERT_ITEMSIZE
,
791 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
,
792 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
,
793 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
,
794 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
);
796 /* R_028B90_VGT_GS_INSTANCE_CNT */
797 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
,
798 SI_TRACKED_VGT_GS_INSTANCE_CNT
,
799 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
);
801 if (sctx
->chip_class
>= GFX9
) {
802 /* R_028A44_VGT_GS_ONCHIP_CNTL */
803 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
804 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
805 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
);
806 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
807 radeon_opt_set_context_reg(sctx
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
808 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
809 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
);
810 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
811 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
812 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
813 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
);
815 if (shader
->key
.part
.gs
.es
->type
== PIPE_SHADER_TESS_EVAL
)
816 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
817 SI_TRACKED_VGT_TF_PARAM
,
818 shader
->vgt_tf_param
);
819 if (shader
->vgt_vertex_reuse_block_cntl
)
820 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
821 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
822 shader
->vgt_vertex_reuse_block_cntl
);
825 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
826 sctx
->context_roll
= true;
829 static void si_shader_gs(struct si_screen
*sscreen
, struct si_shader
*shader
)
831 struct si_shader_selector
*sel
= shader
->selector
;
832 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
833 unsigned gs_num_invocations
= sel
->gs_num_invocations
;
834 struct si_pm4_state
*pm4
;
836 unsigned max_stream
= sel
->max_gs_stream
;
839 pm4
= si_get_shader_pm4_state(shader
);
843 pm4
->atom
.emit
= si_emit_shader_gs
;
845 offset
= num_components
[0] * sel
->gs_max_out_vertices
;
846 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
= offset
;
849 offset
+= num_components
[1] * sel
->gs_max_out_vertices
;
850 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
= offset
;
853 offset
+= num_components
[2] * sel
->gs_max_out_vertices
;
854 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
= offset
;
857 offset
+= num_components
[3] * sel
->gs_max_out_vertices
;
858 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
= offset
;
860 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
861 assert(offset
< (1 << 15));
863 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
= sel
->gs_max_out_vertices
;
865 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
= num_components
[0];
866 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
= (max_stream
>= 1) ? num_components
[1] : 0;
867 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
= (max_stream
>= 2) ? num_components
[2] : 0;
868 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
= (max_stream
>= 3) ? num_components
[3] : 0;
870 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
= S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
871 S_028B90_ENABLE(gs_num_invocations
> 0);
873 va
= shader
->bo
->gpu_address
;
874 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
876 if (sscreen
->info
.chip_class
>= GFX9
) {
877 unsigned input_prim
= sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
878 unsigned es_type
= shader
->key
.part
.gs
.es
->type
;
879 unsigned es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
881 if (es_type
== PIPE_SHADER_VERTEX
)
882 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
883 es_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
884 else if (es_type
== PIPE_SHADER_TESS_EVAL
)
885 es_vgpr_comp_cnt
= shader
->key
.part
.gs
.es
->info
.uses_primid
? 3 : 2;
887 unreachable("invalid shader selector type");
889 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
890 * VGPR[0:4] are always loaded.
892 if (sel
->info
.uses_invocationid
)
893 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
894 else if (sel
->info
.uses_primid
)
895 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
896 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
897 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
899 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
901 unsigned num_user_sgprs
;
902 if (es_type
== PIPE_SHADER_VERTEX
)
903 num_user_sgprs
= si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR
);
905 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
907 if (sscreen
->info
.chip_class
>= GFX10
) {
908 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
909 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
911 si_pm4_set_reg(pm4
, R_00B210_SPI_SHADER_PGM_LO_ES
, va
>> 8);
912 si_pm4_set_reg(pm4
, R_00B214_SPI_SHADER_PGM_HI_ES
, S_00B214_MEM_BASE(va
>> 40));
916 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
917 S_00B228_DX10_CLAMP(1) |
918 S_00B228_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
919 S_00B228_WGP_MODE(sscreen
->info
.chip_class
>= GFX10
) |
920 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
921 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
);
923 S_00B22C_USER_SGPR(num_user_sgprs
) |
924 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
925 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
926 S_00B22C_LDS_SIZE(shader
->config
.lds_size
) |
927 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
929 if (sscreen
->info
.chip_class
>= GFX10
) {
930 rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
932 rsrc1
|= S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
933 rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
936 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, rsrc1
);
937 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
, rsrc2
);
939 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
=
940 S_028A44_ES_VERTS_PER_SUBGRP(shader
->gs_info
.es_verts_per_subgroup
) |
941 S_028A44_GS_PRIMS_PER_SUBGRP(shader
->gs_info
.gs_prims_per_subgroup
) |
942 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader
->gs_info
.gs_inst_prims_in_subgroup
);
943 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
=
944 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader
->gs_info
.max_prims_per_subgroup
);
945 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
=
946 shader
->key
.part
.gs
.es
->esgs_itemsize
/ 4;
948 if (es_type
== PIPE_SHADER_TESS_EVAL
)
949 si_set_tesseval_regs(sscreen
, shader
->key
.part
.gs
.es
, pm4
);
951 polaris_set_vgt_vertex_reuse(sscreen
, shader
->key
.part
.gs
.es
,
954 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
955 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, S_00B224_MEM_BASE(va
>> 40));
957 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
958 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
959 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
960 S_00B228_DX10_CLAMP(1) |
961 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
962 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
963 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR
) |
964 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
968 /* Common tail code for NGG primitive shaders. */
969 static void gfx10_emit_shader_ngg_tail(struct si_context
*sctx
,
970 struct si_shader
*shader
,
971 unsigned initial_cdw
)
973 radeon_opt_set_context_reg(sctx
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
974 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP
,
975 shader
->ctx_reg
.ngg
.ge_max_output_per_subgroup
);
976 radeon_opt_set_context_reg(sctx
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
977 SI_TRACKED_GE_NGG_SUBGRP_CNTL
,
978 shader
->ctx_reg
.ngg
.ge_ngg_subgrp_cntl
);
979 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
,
980 SI_TRACKED_VGT_PRIMITIVEID_EN
,
981 shader
->ctx_reg
.ngg
.vgt_primitiveid_en
);
982 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
983 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
984 shader
->ctx_reg
.ngg
.vgt_gs_onchip_cntl
);
985 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
,
986 SI_TRACKED_VGT_GS_INSTANCE_CNT
,
987 shader
->ctx_reg
.ngg
.vgt_gs_instance_cnt
);
988 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
989 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
990 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
);
991 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
,
992 SI_TRACKED_SPI_VS_OUT_CONFIG
,
993 shader
->ctx_reg
.ngg
.spi_vs_out_config
);
994 radeon_opt_set_context_reg2(sctx
, R_028708_SPI_SHADER_IDX_FORMAT
,
995 SI_TRACKED_SPI_SHADER_IDX_FORMAT
,
996 shader
->ctx_reg
.ngg
.spi_shader_idx_format
,
997 shader
->ctx_reg
.ngg
.spi_shader_pos_format
);
998 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
,
999 SI_TRACKED_PA_CL_VTE_CNTL
,
1000 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
);
1001 radeon_opt_set_context_reg(sctx
, R_028838_PA_CL_NGG_CNTL
,
1002 SI_TRACKED_PA_CL_NGG_CNTL
,
1003 shader
->ctx_reg
.ngg
.pa_cl_ngg_cntl
);
1005 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1006 sctx
->context_roll
= true;
1009 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context
*sctx
)
1011 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1012 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1017 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1020 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context
*sctx
)
1022 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1023 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1028 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1029 SI_TRACKED_VGT_TF_PARAM
,
1030 shader
->vgt_tf_param
);
1032 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1035 static void gfx10_emit_shader_ngg_notess_gs(struct si_context
*sctx
)
1037 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1038 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1043 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
1044 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
1045 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
);
1047 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1050 static void gfx10_emit_shader_ngg_tess_gs(struct si_context
*sctx
)
1052 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1053 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1058 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
1059 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
1060 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
);
1061 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1062 SI_TRACKED_VGT_TF_PARAM
,
1063 shader
->vgt_tf_param
);
1065 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1068 unsigned si_get_input_prim(const struct si_shader_selector
*gs
)
1070 if (gs
->type
== PIPE_SHADER_GEOMETRY
)
1071 return gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
1073 if (gs
->type
== PIPE_SHADER_TESS_EVAL
) {
1074 if (gs
->info
.properties
[TGSI_PROPERTY_TES_POINT_MODE
])
1075 return PIPE_PRIM_POINTS
;
1076 if (gs
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] == PIPE_PRIM_LINES
)
1077 return PIPE_PRIM_LINES
;
1078 return PIPE_PRIM_TRIANGLES
;
1081 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1082 return PIPE_PRIM_TRIANGLES
; /* worst case for all callers */
1086 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1089 static void gfx10_shader_ngg(struct si_screen
*sscreen
, struct si_shader
*shader
)
1091 const struct si_shader_selector
*gs_sel
= shader
->selector
;
1092 const struct tgsi_shader_info
*gs_info
= &gs_sel
->info
;
1093 enum pipe_shader_type gs_type
= shader
->selector
->type
;
1094 const struct si_shader_selector
*es_sel
=
1095 shader
->previous_stage_sel
? shader
->previous_stage_sel
: shader
->selector
;
1096 const struct tgsi_shader_info
*es_info
= &es_sel
->info
;
1097 enum pipe_shader_type es_type
= es_sel
->type
;
1098 unsigned num_user_sgprs
;
1099 unsigned nparams
, es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
1101 unsigned window_space
=
1102 gs_info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
1103 bool es_enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| es_info
->uses_primid
;
1104 unsigned gs_num_invocations
= MAX2(gs_sel
->gs_num_invocations
, 1);
1105 unsigned input_prim
= si_get_input_prim(gs_sel
);
1106 bool break_wave_at_eoi
= false;
1107 struct si_pm4_state
*pm4
= si_get_shader_pm4_state(shader
);
1111 if (es_type
== PIPE_SHADER_TESS_EVAL
) {
1112 pm4
->atom
.emit
= gs_type
== PIPE_SHADER_GEOMETRY
? gfx10_emit_shader_ngg_tess_gs
1113 : gfx10_emit_shader_ngg_tess_nogs
;
1115 pm4
->atom
.emit
= gs_type
== PIPE_SHADER_GEOMETRY
? gfx10_emit_shader_ngg_notess_gs
1116 : gfx10_emit_shader_ngg_notess_nogs
;
1119 va
= shader
->bo
->gpu_address
;
1120 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1122 if (es_type
== PIPE_SHADER_VERTEX
) {
1123 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
1124 es_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 3 : 0;
1126 if (es_info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
]) {
1127 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
1128 es_info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
];
1130 num_user_sgprs
= si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR
);
1133 assert(es_type
== PIPE_SHADER_TESS_EVAL
);
1134 es_vgpr_comp_cnt
= es_enable_prim_id
? 3 : 2;
1135 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
1137 if (es_enable_prim_id
|| gs_info
->uses_primid
)
1138 break_wave_at_eoi
= true;
1141 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1142 * VGPR[0:4] are always loaded.
1144 * Vertex shaders always need to load VGPR3, because they need to
1145 * pass edge flags for decomposed primitives (such as quads) to the PA
1146 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1148 if (gs_info
->uses_invocationid
|| gs_type
== PIPE_SHADER_VERTEX
)
1149 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID, edge flags. */
1150 else if (gs_info
->uses_primid
)
1151 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
1152 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
1153 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
1155 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
1157 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
1158 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
1159 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
1160 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) /
1161 (sscreen
->ge_wave_size
== 32 ? 8 : 4)) |
1162 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
1163 S_00B228_DX10_CLAMP(1) |
1164 S_00B228_MEM_ORDERED(1) |
1165 S_00B228_WGP_MODE(1) |
1166 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
));
1167 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
1168 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0) |
1169 S_00B22C_USER_SGPR(num_user_sgprs
) |
1170 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
1171 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5) |
1172 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
1173 S_00B22C_LDS_SIZE(shader
->config
.lds_size
));
1175 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1176 shader
->ctx_reg
.ngg
.spi_vs_out_config
=
1177 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
1178 S_0286C4_NO_PC_EXPORT(shader
->info
.nr_param_exports
== 0);
1180 shader
->ctx_reg
.ngg
.spi_shader_idx_format
=
1181 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
);
1182 shader
->ctx_reg
.ngg
.spi_shader_pos_format
=
1183 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1184 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
1185 V_02870C_SPI_SHADER_4COMP
:
1186 V_02870C_SPI_SHADER_NONE
) |
1187 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
1188 V_02870C_SPI_SHADER_4COMP
:
1189 V_02870C_SPI_SHADER_NONE
) |
1190 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
1191 V_02870C_SPI_SHADER_4COMP
:
1192 V_02870C_SPI_SHADER_NONE
);
1194 shader
->ctx_reg
.ngg
.vgt_primitiveid_en
=
1195 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
1196 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id
);
1198 if (gs_type
== PIPE_SHADER_GEOMETRY
) {
1199 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
= es_sel
->esgs_itemsize
/ 4;
1200 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
= gs_sel
->gs_max_out_vertices
;
1202 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
= 1;
1205 if (es_type
== PIPE_SHADER_TESS_EVAL
)
1206 si_set_tesseval_regs(sscreen
, es_sel
, pm4
);
1208 shader
->ctx_reg
.ngg
.vgt_gs_onchip_cntl
=
1209 S_028A44_ES_VERTS_PER_SUBGRP(shader
->ngg
.hw_max_esverts
) |
1210 S_028A44_GS_PRIMS_PER_SUBGRP(shader
->ngg
.max_gsprims
) |
1211 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader
->ngg
.max_gsprims
* gs_num_invocations
);
1212 shader
->ctx_reg
.ngg
.ge_max_output_per_subgroup
=
1213 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader
->ngg
.max_out_verts
);
1214 shader
->ctx_reg
.ngg
.ge_ngg_subgrp_cntl
=
1215 S_028B4C_PRIM_AMP_FACTOR(shader
->ngg
.prim_amp_factor
) |
1216 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1217 shader
->ctx_reg
.ngg
.vgt_gs_instance_cnt
=
1218 S_028B90_CNT(gs_num_invocations
) |
1219 S_028B90_ENABLE(gs_num_invocations
> 1) |
1220 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1221 shader
->ngg
.max_vert_out_per_gs_instance
);
1223 /* Always output hw-generated edge flags and pass them via the prim
1224 * export to prevent drawing lines on internal edges of decomposed
1225 * primitives (such as quads) with polygon mode = lines. Only VS needs
1228 shader
->ctx_reg
.ngg
.pa_cl_ngg_cntl
=
1229 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type
== PIPE_SHADER_VERTEX
);
1232 S_03096C_PRIM_GRP_SIZE(shader
->ngg
.max_gsprims
) |
1233 S_03096C_VERT_GRP_SIZE(shader
->ngg
.hw_max_esverts
) |
1234 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
1236 /* Bug workaround for a possible hang with non-tessellation cases.
1237 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1239 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1241 if ((sscreen
->info
.family
== CHIP_NAVI10
||
1242 sscreen
->info
.family
== CHIP_NAVI12
||
1243 sscreen
->info
.family
== CHIP_NAVI14
) &&
1244 (es_type
== PIPE_SHADER_VERTEX
|| gs_type
== PIPE_SHADER_VERTEX
) && /* = no tess */
1245 shader
->ngg
.hw_max_esverts
!= 256) {
1246 shader
->ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
1248 if (shader
->ngg
.hw_max_esverts
> 5) {
1250 S_03096C_VERT_GRP_SIZE(shader
->ngg
.hw_max_esverts
- 5);
1255 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
=
1256 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1258 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
=
1259 S_028818_VTX_W0_FMT(1) |
1260 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1261 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1262 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1266 static void si_emit_shader_vs(struct si_context
*sctx
)
1268 struct si_shader
*shader
= sctx
->queued
.named
.vs
->shader
;
1269 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1274 radeon_opt_set_context_reg(sctx
, R_028A40_VGT_GS_MODE
,
1275 SI_TRACKED_VGT_GS_MODE
,
1276 shader
->ctx_reg
.vs
.vgt_gs_mode
);
1277 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
,
1278 SI_TRACKED_VGT_PRIMITIVEID_EN
,
1279 shader
->ctx_reg
.vs
.vgt_primitiveid_en
);
1281 if (sctx
->chip_class
<= GFX8
) {
1282 radeon_opt_set_context_reg(sctx
, R_028AB4_VGT_REUSE_OFF
,
1283 SI_TRACKED_VGT_REUSE_OFF
,
1284 shader
->ctx_reg
.vs
.vgt_reuse_off
);
1287 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
,
1288 SI_TRACKED_SPI_VS_OUT_CONFIG
,
1289 shader
->ctx_reg
.vs
.spi_vs_out_config
);
1291 radeon_opt_set_context_reg(sctx
, R_02870C_SPI_SHADER_POS_FORMAT
,
1292 SI_TRACKED_SPI_SHADER_POS_FORMAT
,
1293 shader
->ctx_reg
.vs
.spi_shader_pos_format
);
1295 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
,
1296 SI_TRACKED_PA_CL_VTE_CNTL
,
1297 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
);
1299 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
1300 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1301 SI_TRACKED_VGT_TF_PARAM
,
1302 shader
->vgt_tf_param
);
1304 if (shader
->vgt_vertex_reuse_block_cntl
)
1305 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1306 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1307 shader
->vgt_vertex_reuse_block_cntl
);
1309 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1310 sctx
->context_roll
= true;
1314 * Compute the state for \p shader, which will run as a vertex shader on the
1317 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1318 * is the copy shader.
1320 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
1321 struct si_shader_selector
*gs
)
1323 const struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1324 struct si_pm4_state
*pm4
;
1325 unsigned num_user_sgprs
, vgpr_comp_cnt
;
1327 unsigned nparams
, oc_lds_en
;
1328 unsigned window_space
=
1329 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
1330 bool enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| info
->uses_primid
;
1332 pm4
= si_get_shader_pm4_state(shader
);
1336 pm4
->atom
.emit
= si_emit_shader_vs
;
1338 /* We always write VGT_GS_MODE in the VS state, because every switch
1339 * between different shader pipelines involving a different GS or no
1340 * GS at all involves a switch of the VS (different GS use different
1341 * copy shaders). On the other hand, when the API switches from a GS to
1342 * no GS and then back to the same GS used originally, the GS state is
1346 unsigned mode
= V_028A40_GS_OFF
;
1348 /* PrimID needs GS scenario A. */
1350 mode
= V_028A40_GS_SCENARIO_A
;
1352 shader
->ctx_reg
.vs
.vgt_gs_mode
= S_028A40_MODE(mode
);
1353 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= enable_prim_id
;
1355 shader
->ctx_reg
.vs
.vgt_gs_mode
= ac_vgt_gs_mode(gs
->gs_max_out_vertices
,
1356 sscreen
->info
.chip_class
);
1357 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= 0;
1360 if (sscreen
->info
.chip_class
<= GFX8
) {
1361 /* Reuse needs to be set off if we write oViewport. */
1362 shader
->ctx_reg
.vs
.vgt_reuse_off
=
1363 S_028AB4_REUSE_OFF(info
->writes_viewport_index
);
1366 va
= shader
->bo
->gpu_address
;
1367 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1370 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
1371 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
1372 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
1373 if (sscreen
->info
.chip_class
>= GFX10
) {
1374 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 3 : (enable_prim_id
? 2 : 0);
1376 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1377 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1378 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1380 vgpr_comp_cnt
= enable_prim_id
? 2 : (shader
->info
.uses_instanceid
? 1 : 0);
1383 if (info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
]) {
1384 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
1385 info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
];
1387 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
1389 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
1390 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
1391 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
1393 unreachable("invalid shader selector type");
1395 /* VS is required to export at least one param. */
1396 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1397 shader
->ctx_reg
.vs
.spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
1399 if (sscreen
->info
.chip_class
>= GFX10
) {
1400 shader
->ctx_reg
.vs
.spi_vs_out_config
|=
1401 S_0286C4_NO_PC_EXPORT(shader
->info
.nr_param_exports
== 0);
1404 shader
->ctx_reg
.vs
.spi_shader_pos_format
=
1405 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1406 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
1407 V_02870C_SPI_SHADER_4COMP
:
1408 V_02870C_SPI_SHADER_NONE
) |
1409 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
1410 V_02870C_SPI_SHADER_4COMP
:
1411 V_02870C_SPI_SHADER_NONE
) |
1412 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
1413 V_02870C_SPI_SHADER_4COMP
:
1414 V_02870C_SPI_SHADER_NONE
);
1416 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
1418 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
1419 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, S_00B124_MEM_BASE(va
>> 40));
1421 uint32_t rsrc1
= S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) /
1422 (sscreen
->ge_wave_size
== 32 ? 8 : 4)) |
1423 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
1424 S_00B128_DX10_CLAMP(1) |
1425 S_00B128_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
1426 S_00B128_FLOAT_MODE(shader
->config
.float_mode
);
1427 uint32_t rsrc2
= S_00B12C_USER_SGPR(num_user_sgprs
) |
1428 S_00B12C_OC_LDS_EN(oc_lds_en
) |
1429 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
1431 if (sscreen
->info
.chip_class
<= GFX9
)
1432 rsrc1
|= S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
1434 if (!sscreen
->use_ngg_streamout
) {
1435 rsrc2
|= S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
1436 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
1437 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
1438 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
1439 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
);
1442 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
, rsrc1
);
1443 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
, rsrc2
);
1446 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1447 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1449 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1450 S_028818_VTX_W0_FMT(1) |
1451 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1452 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1453 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1455 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
1456 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
1458 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
1461 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
1463 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
1464 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
1465 !!(info
->colors_read
& 0xf0);
1466 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
1467 (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
1469 assert(num_interp
<= 32);
1470 return MIN2(num_interp
, 32);
1473 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
1475 unsigned value
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
1476 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
1478 /* If the i-th target format is set, all previous target formats must
1479 * be non-zero to avoid hangs.
1481 for (i
= 0; i
< num_targets
; i
++)
1482 if (!(value
& (0xf << (i
* 4))))
1483 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
1488 static void si_emit_shader_ps(struct si_context
*sctx
)
1490 struct si_shader
*shader
= sctx
->queued
.named
.ps
->shader
;
1491 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1496 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1497 radeon_opt_set_context_reg2(sctx
, R_0286CC_SPI_PS_INPUT_ENA
,
1498 SI_TRACKED_SPI_PS_INPUT_ENA
,
1499 shader
->ctx_reg
.ps
.spi_ps_input_ena
,
1500 shader
->ctx_reg
.ps
.spi_ps_input_addr
);
1502 radeon_opt_set_context_reg(sctx
, R_0286E0_SPI_BARYC_CNTL
,
1503 SI_TRACKED_SPI_BARYC_CNTL
,
1504 shader
->ctx_reg
.ps
.spi_baryc_cntl
);
1505 radeon_opt_set_context_reg(sctx
, R_0286D8_SPI_PS_IN_CONTROL
,
1506 SI_TRACKED_SPI_PS_IN_CONTROL
,
1507 shader
->ctx_reg
.ps
.spi_ps_in_control
);
1509 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1510 radeon_opt_set_context_reg2(sctx
, R_028710_SPI_SHADER_Z_FORMAT
,
1511 SI_TRACKED_SPI_SHADER_Z_FORMAT
,
1512 shader
->ctx_reg
.ps
.spi_shader_z_format
,
1513 shader
->ctx_reg
.ps
.spi_shader_col_format
);
1515 radeon_opt_set_context_reg(sctx
, R_02823C_CB_SHADER_MASK
,
1516 SI_TRACKED_CB_SHADER_MASK
,
1517 shader
->ctx_reg
.ps
.cb_shader_mask
);
1519 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1520 sctx
->context_roll
= true;
1523 static void si_shader_ps(struct si_screen
*sscreen
, struct si_shader
*shader
)
1525 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1526 struct si_pm4_state
*pm4
;
1527 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
1528 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
1530 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
1532 /* we need to enable at least one of them, otherwise we hang the GPU */
1533 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1534 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1535 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1536 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
1537 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
1538 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1539 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
1540 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
1541 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1542 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
1543 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1544 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1545 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1546 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
1548 /* Validate interpolation optimization flags (read as implications). */
1549 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1550 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1551 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1552 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1553 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1554 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1555 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
1556 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
1557 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1558 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
1559 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
1560 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1561 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
1562 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1563 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1564 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
1565 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1566 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1568 /* Validate cases when the optimizations are off (read as implications). */
1569 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1570 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1571 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
1572 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1573 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1574 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
1576 pm4
= si_get_shader_pm4_state(shader
);
1580 pm4
->atom
.emit
= si_emit_shader_ps
;
1582 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1584 * 0 -> Position = pixel center
1585 * 1 -> Position = pixel centroid
1586 * 2 -> Position = at sample position
1588 * From GLSL 4.5 specification, section 7.1:
1589 * "The variable gl_FragCoord is available as an input variable from
1590 * within fragment shaders and it holds the window relative coordinates
1591 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1592 * value can be for any location within the pixel, or one of the
1593 * fragment samples. The use of centroid does not further restrict
1594 * this value to be inside the current primitive."
1596 * Meaning that centroid has no effect and we can return anything within
1597 * the pixel. Thus, return the value at sample position, because that's
1598 * the most accurate one shaders can get.
1600 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1602 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
1603 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
1604 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
1606 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
1607 cb_shader_mask
= ac_get_cb_shader_mask(spi_shader_col_format
);
1609 /* Ensure that some export memory is always allocated, for two reasons:
1611 * 1) Correctness: The hardware ignores the EXEC mask if no export
1612 * memory is allocated, so KILL and alpha test do not work correctly
1614 * 2) Performance: Every shader needs at least a NULL export, even when
1615 * it writes no color/depth output. The NULL export instruction
1616 * stalls without this setting.
1618 * Don't add this to CB_SHADER_MASK.
1620 * GFX10 supports pixel shaders without exports by setting both
1621 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1622 * instructions if any are present.
1624 if ((sscreen
->info
.chip_class
<= GFX9
||
1626 shader
->key
.part
.ps
.epilog
.alpha_func
!= PIPE_FUNC_ALWAYS
) &&
1627 !spi_shader_col_format
&&
1628 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
1629 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
1631 shader
->ctx_reg
.ps
.spi_ps_input_ena
= input_ena
;
1632 shader
->ctx_reg
.ps
.spi_ps_input_addr
= shader
->config
.spi_ps_input_addr
;
1634 /* Set interpolation controls. */
1635 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
)) |
1636 S_0286D8_PS_W32_EN(sscreen
->ps_wave_size
== 32);
1638 shader
->ctx_reg
.ps
.spi_baryc_cntl
= spi_baryc_cntl
;
1639 shader
->ctx_reg
.ps
.spi_ps_in_control
= spi_ps_in_control
;
1640 shader
->ctx_reg
.ps
.spi_shader_z_format
=
1641 ac_get_spi_shader_z_format(info
->writes_z
,
1642 info
->writes_stencil
,
1643 info
->writes_samplemask
);
1644 shader
->ctx_reg
.ps
.spi_shader_col_format
= spi_shader_col_format
;
1645 shader
->ctx_reg
.ps
.cb_shader_mask
= cb_shader_mask
;
1647 va
= shader
->bo
->gpu_address
;
1648 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1649 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
1650 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, S_00B024_MEM_BASE(va
>> 40));
1653 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) /
1654 (sscreen
->ps_wave_size
== 32 ? 8 : 4)) |
1655 S_00B028_DX10_CLAMP(1) |
1656 S_00B028_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
1657 S_00B028_FLOAT_MODE(shader
->config
.float_mode
);
1659 if (sscreen
->info
.chip_class
< GFX10
) {
1660 rsrc1
|= S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
1663 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
, rsrc1
);
1664 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
1665 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
1666 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
1667 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1670 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
1671 struct si_shader
*shader
)
1673 switch (shader
->selector
->type
) {
1674 case PIPE_SHADER_VERTEX
:
1675 if (shader
->key
.as_ls
)
1676 si_shader_ls(sscreen
, shader
);
1677 else if (shader
->key
.as_es
)
1678 si_shader_es(sscreen
, shader
);
1679 else if (shader
->key
.as_ngg
)
1680 gfx10_shader_ngg(sscreen
, shader
);
1682 si_shader_vs(sscreen
, shader
, NULL
);
1684 case PIPE_SHADER_TESS_CTRL
:
1685 si_shader_hs(sscreen
, shader
);
1687 case PIPE_SHADER_TESS_EVAL
:
1688 if (shader
->key
.as_es
)
1689 si_shader_es(sscreen
, shader
);
1690 else if (shader
->key
.as_ngg
)
1691 gfx10_shader_ngg(sscreen
, shader
);
1693 si_shader_vs(sscreen
, shader
, NULL
);
1695 case PIPE_SHADER_GEOMETRY
:
1696 if (shader
->key
.as_ngg
)
1697 gfx10_shader_ngg(sscreen
, shader
);
1699 si_shader_gs(sscreen
, shader
);
1701 case PIPE_SHADER_FRAGMENT
:
1702 si_shader_ps(sscreen
, shader
);
1709 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
1711 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1712 return sctx
->queued
.named
.dsa
->alpha_func
;
1715 void si_shader_selector_key_vs(struct si_context
*sctx
,
1716 struct si_shader_selector
*vs
,
1717 struct si_shader_key
*key
,
1718 struct si_vs_prolog_bits
*prolog_key
)
1720 if (!sctx
->vertex_elements
||
1721 vs
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
])
1724 struct si_vertex_elements
*elts
= sctx
->vertex_elements
;
1726 prolog_key
->instance_divisor_is_one
= elts
->instance_divisor_is_one
;
1727 prolog_key
->instance_divisor_is_fetched
= elts
->instance_divisor_is_fetched
;
1728 prolog_key
->unpack_instance_id_from_vertex_id
=
1729 sctx
->prim_discard_cs_instancing
;
1731 /* Prefer a monolithic shader to allow scheduling divisions around
1733 if (prolog_key
->instance_divisor_is_fetched
)
1734 key
->opt
.prefer_mono
= 1;
1736 unsigned count
= MIN2(vs
->info
.num_inputs
, elts
->count
);
1737 unsigned count_mask
= (1 << count
) - 1;
1738 unsigned fix
= elts
->fix_fetch_always
& count_mask
;
1739 unsigned opencode
= elts
->fix_fetch_opencode
& count_mask
;
1741 if (sctx
->vertex_buffer_unaligned
& elts
->vb_alignment_check_mask
) {
1742 uint32_t mask
= elts
->fix_fetch_unaligned
& count_mask
;
1744 unsigned i
= u_bit_scan(&mask
);
1745 unsigned log_hw_load_size
= 1 + ((elts
->hw_load_is_dword
>> i
) & 1);
1746 unsigned vbidx
= elts
->vertex_buffer_index
[i
];
1747 struct pipe_vertex_buffer
*vb
= &sctx
->vertex_buffer
[vbidx
];
1748 unsigned align_mask
= (1 << log_hw_load_size
) - 1;
1749 if (vb
->buffer_offset
& align_mask
||
1750 vb
->stride
& align_mask
) {
1758 unsigned i
= u_bit_scan(&fix
);
1759 key
->mono
.vs_fix_fetch
[i
].bits
= elts
->fix_fetch
[i
];
1761 key
->mono
.vs_fetch_opencode
= opencode
;
1764 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
,
1765 struct si_shader_selector
*vs
,
1766 struct si_shader_key
*key
)
1768 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1770 key
->opt
.clip_disable
=
1771 sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
1772 (vs
->info
.clipdist_writemask
||
1773 vs
->info
.writes_clipvertex
) &&
1774 !vs
->info
.culldist_writemask
;
1776 /* Find out if PS is disabled. */
1777 bool ps_disabled
= true;
1779 bool ps_modifies_zs
= ps
->info
.uses_kill
||
1780 ps
->info
.writes_z
||
1781 ps
->info
.writes_stencil
||
1782 ps
->info
.writes_samplemask
||
1783 sctx
->queued
.named
.blend
->alpha_to_coverage
||
1784 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
1785 unsigned ps_colormask
= si_get_total_colormask(sctx
);
1787 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
1790 !ps
->info
.writes_memory
);
1793 /* Find out which VS outputs aren't used by the PS. */
1794 uint64_t outputs_written
= vs
->outputs_written_before_ps
;
1795 uint64_t inputs_read
= 0;
1797 /* Ignore outputs that are not passed from VS to PS. */
1798 outputs_written
&= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION
, 0, true)) |
1799 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE
, 0, true)) |
1800 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX
, 0, true)));
1803 inputs_read
= ps
->inputs_read
;
1806 uint64_t linked
= outputs_written
& inputs_read
;
1808 key
->opt
.kill_outputs
= ~linked
& outputs_written
;
1811 /* Compute the key for the hw shader variant */
1812 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
1813 struct si_shader_selector
*sel
,
1814 union si_vgt_stages_key stages_key
,
1815 struct si_shader_key
*key
)
1817 struct si_context
*sctx
= (struct si_context
*)ctx
;
1819 memset(key
, 0, sizeof(*key
));
1821 switch (sel
->type
) {
1822 case PIPE_SHADER_VERTEX
:
1823 si_shader_selector_key_vs(sctx
, sel
, key
, &key
->part
.vs
.prolog
);
1825 if (sctx
->tes_shader
.cso
)
1827 else if (sctx
->gs_shader
.cso
)
1830 key
->as_ngg
= stages_key
.u
.ngg
;
1831 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1833 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1834 key
->mono
.u
.vs_export_prim_id
= 1;
1837 case PIPE_SHADER_TESS_CTRL
:
1838 if (sctx
->chip_class
>= GFX9
) {
1839 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1840 key
, &key
->part
.tcs
.ls_prolog
);
1841 key
->part
.tcs
.ls
= sctx
->vs_shader
.cso
;
1843 /* When the LS VGPR fix is needed, monolithic shaders
1845 * - avoid initializing EXEC in both the LS prolog
1846 * and the LS main part when !vs_needs_prolog
1847 * - remove the fixup for unused input VGPRs
1849 key
->part
.tcs
.ls_prolog
.ls_vgpr_fix
= sctx
->ls_vgpr_fix
;
1851 /* The LS output / HS input layout can be communicated
1852 * directly instead of via user SGPRs for merged LS-HS.
1853 * The LS VGPR fix prefers this too.
1855 key
->opt
.prefer_mono
= 1;
1858 key
->part
.tcs
.epilog
.prim_mode
=
1859 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1860 key
->part
.tcs
.epilog
.invoc0_tess_factors_are_def
=
1861 sel
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1862 key
->part
.tcs
.epilog
.tes_reads_tess_factors
=
1863 sctx
->tes_shader
.cso
->info
.reads_tess_factors
;
1865 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
1866 key
->mono
.u
.ff_tcs_inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
1868 case PIPE_SHADER_TESS_EVAL
:
1869 key
->as_ngg
= stages_key
.u
.ngg
;
1871 if (sctx
->gs_shader
.cso
)
1874 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1876 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1877 key
->mono
.u
.vs_export_prim_id
= 1;
1880 case PIPE_SHADER_GEOMETRY
:
1881 if (sctx
->chip_class
>= GFX9
) {
1882 if (sctx
->tes_shader
.cso
) {
1883 key
->part
.gs
.es
= sctx
->tes_shader
.cso
;
1885 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1886 key
, &key
->part
.gs
.vs_prolog
);
1887 key
->part
.gs
.es
= sctx
->vs_shader
.cso
;
1888 key
->part
.gs
.prolog
.gfx9_prev_is_vs
= 1;
1891 key
->as_ngg
= stages_key
.u
.ngg
;
1893 /* Merged ES-GS can have unbalanced wave usage.
1895 * ES threads are per-vertex, while GS threads are
1896 * per-primitive. So without any amplification, there
1897 * are fewer GS threads than ES threads, which can result
1898 * in empty (no-op) GS waves. With too much amplification,
1899 * there are more GS threads than ES threads, which
1900 * can result in empty (no-op) ES waves.
1902 * Non-monolithic shaders are implemented by setting EXEC
1903 * at the beginning of shader parts, and don't jump to
1904 * the end if EXEC is 0.
1906 * Monolithic shaders use conditional blocks, so they can
1907 * jump and skip empty waves of ES or GS. So set this to
1908 * always use optimized variants, which are monolithic.
1910 key
->opt
.prefer_mono
= 1;
1912 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
1914 case PIPE_SHADER_FRAGMENT
: {
1915 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1916 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1918 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
1919 sel
->info
.colors_written
== 0x1)
1920 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
1922 /* Select the shader color format based on whether
1923 * blending or alpha are needed.
1925 key
->part
.ps
.epilog
.spi_shader_col_format
=
1926 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1927 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
1928 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1929 sctx
->framebuffer
.spi_shader_col_format_blend
) |
1930 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1931 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
1932 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1933 sctx
->framebuffer
.spi_shader_col_format
);
1934 key
->part
.ps
.epilog
.spi_shader_col_format
&= blend
->cb_target_enabled_4bit
;
1936 /* The output for dual source blending should have
1937 * the same format as the first output.
1939 if (blend
->dual_src_blend
) {
1940 key
->part
.ps
.epilog
.spi_shader_col_format
|=
1941 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
1944 /* If alpha-to-coverage is enabled, we have to export alpha
1945 * even if there is no color buffer.
1947 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) &&
1948 blend
->alpha_to_coverage
)
1949 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
1951 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1952 * to the range supported by the type if a channel has less
1953 * than 16 bits and the export format is 16_ABGR.
1955 if (sctx
->chip_class
<= GFX7
&& sctx
->family
!= CHIP_HAWAII
) {
1956 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
1957 key
->part
.ps
.epilog
.color_is_int10
= sctx
->framebuffer
.color_is_int10
;
1960 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1961 if (!key
->part
.ps
.epilog
.last_cbuf
) {
1962 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
1963 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
1964 key
->part
.ps
.epilog
.color_is_int10
&= sel
->info
.colors_written
;
1967 bool is_poly
= !util_prim_is_points_or_lines(sctx
->current_rast_prim
);
1968 bool is_line
= util_prim_is_lines(sctx
->current_rast_prim
);
1970 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
1971 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
1973 key
->part
.ps
.epilog
.alpha_to_one
= blend
->alpha_to_one
&&
1974 rs
->multisample_enable
;
1976 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
1977 key
->part
.ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
1978 (is_line
&& rs
->line_smooth
)) &&
1979 sctx
->framebuffer
.nr_samples
<= 1;
1980 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
1982 if (sctx
->ps_iter_samples
> 1 &&
1983 sel
->info
.reads_samplemask
) {
1984 key
->part
.ps
.prolog
.samplemask_log_ps_iter
=
1985 util_logbase2(sctx
->ps_iter_samples
);
1988 if (rs
->force_persample_interp
&&
1989 rs
->multisample_enable
&&
1990 sctx
->framebuffer
.nr_samples
> 1 &&
1991 sctx
->ps_iter_samples
> 1) {
1992 key
->part
.ps
.prolog
.force_persp_sample_interp
=
1993 sel
->info
.uses_persp_center
||
1994 sel
->info
.uses_persp_centroid
;
1996 key
->part
.ps
.prolog
.force_linear_sample_interp
=
1997 sel
->info
.uses_linear_center
||
1998 sel
->info
.uses_linear_centroid
;
1999 } else if (rs
->multisample_enable
&&
2000 sctx
->framebuffer
.nr_samples
> 1) {
2001 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
2002 sel
->info
.uses_persp_center
&&
2003 sel
->info
.uses_persp_centroid
;
2004 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
2005 sel
->info
.uses_linear_center
&&
2006 sel
->info
.uses_linear_centroid
;
2008 /* Make sure SPI doesn't compute more than 1 pair
2009 * of (i,j), which is the optimization here. */
2010 key
->part
.ps
.prolog
.force_persp_center_interp
=
2011 sel
->info
.uses_persp_center
+
2012 sel
->info
.uses_persp_centroid
+
2013 sel
->info
.uses_persp_sample
> 1;
2015 key
->part
.ps
.prolog
.force_linear_center_interp
=
2016 sel
->info
.uses_linear_center
+
2017 sel
->info
.uses_linear_centroid
+
2018 sel
->info
.uses_linear_sample
> 1;
2020 if (sel
->info
.uses_persp_opcode_interp_sample
||
2021 sel
->info
.uses_linear_opcode_interp_sample
)
2022 key
->mono
.u
.ps
.interpolate_at_sample_force_center
= 1;
2025 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
2027 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2028 if (sctx
->ps_uses_fbfetch
&& !sctx
->blitter
->running
) {
2029 struct pipe_surface
*cb0
= sctx
->framebuffer
.state
.cbufs
[0];
2030 struct pipe_resource
*tex
= cb0
->texture
;
2032 /* 1D textures are allocated and used as 2D on GFX9. */
2033 key
->mono
.u
.ps
.fbfetch_msaa
= sctx
->framebuffer
.nr_samples
> 1;
2034 key
->mono
.u
.ps
.fbfetch_is_1D
= sctx
->chip_class
!= GFX9
&&
2035 (tex
->target
== PIPE_TEXTURE_1D
||
2036 tex
->target
== PIPE_TEXTURE_1D_ARRAY
);
2037 key
->mono
.u
.ps
.fbfetch_layered
= tex
->target
== PIPE_TEXTURE_1D_ARRAY
||
2038 tex
->target
== PIPE_TEXTURE_2D_ARRAY
||
2039 tex
->target
== PIPE_TEXTURE_CUBE
||
2040 tex
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
2041 tex
->target
== PIPE_TEXTURE_3D
;
2049 if (unlikely(sctx
->screen
->debug_flags
& DBG(NO_OPT_VARIANT
)))
2050 memset(&key
->opt
, 0, sizeof(key
->opt
));
2053 static void si_build_shader_variant(struct si_shader
*shader
,
2057 struct si_shader_selector
*sel
= shader
->selector
;
2058 struct si_screen
*sscreen
= sel
->screen
;
2059 struct ac_llvm_compiler
*compiler
;
2060 struct pipe_debug_callback
*debug
= &shader
->compiler_ctx_state
.debug
;
2062 if (thread_index
>= 0) {
2064 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler_lowp
));
2065 compiler
= &sscreen
->compiler_lowp
[thread_index
];
2067 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
2068 compiler
= &sscreen
->compiler
[thread_index
];
2073 assert(!low_priority
);
2074 compiler
= shader
->compiler_ctx_state
.compiler
;
2077 if (unlikely(!si_shader_create(sscreen
, compiler
, shader
, debug
))) {
2078 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2080 shader
->compilation_failed
= true;
2084 if (shader
->compiler_ctx_state
.is_debug_context
) {
2085 FILE *f
= open_memstream(&shader
->shader_log
,
2086 &shader
->shader_log_size
);
2088 si_shader_dump(sscreen
, shader
, NULL
, f
, false);
2093 si_shader_init_pm4_state(sscreen
, shader
);
2096 static void si_build_shader_variant_low_priority(void *job
, int thread_index
)
2098 struct si_shader
*shader
= (struct si_shader
*)job
;
2100 assert(thread_index
>= 0);
2102 si_build_shader_variant(shader
, thread_index
, true);
2105 static const struct si_shader_key zeroed
;
2107 static bool si_check_missing_main_part(struct si_screen
*sscreen
,
2108 struct si_shader_selector
*sel
,
2109 struct si_compiler_ctx_state
*compiler_state
,
2110 struct si_shader_key
*key
)
2112 struct si_shader
**mainp
= si_get_main_shader_part(sel
, key
);
2115 struct si_shader
*main_part
= CALLOC_STRUCT(si_shader
);
2120 /* We can leave the fence as permanently signaled because the
2121 * main part becomes visible globally only after it has been
2123 util_queue_fence_init(&main_part
->ready
);
2125 main_part
->selector
= sel
;
2126 main_part
->key
.as_es
= key
->as_es
;
2127 main_part
->key
.as_ls
= key
->as_ls
;
2128 main_part
->key
.as_ngg
= key
->as_ngg
;
2129 main_part
->is_monolithic
= false;
2131 if (si_compile_tgsi_shader(sscreen
, compiler_state
->compiler
,
2132 main_part
, &compiler_state
->debug
) != 0) {
2142 * Select a shader variant according to the shader key.
2144 * \param optimized_or_none If the key describes an optimized shader variant and
2145 * the compilation isn't finished, don't select any
2146 * shader and return an error.
2148 int si_shader_select_with_key(struct si_screen
*sscreen
,
2149 struct si_shader_ctx_state
*state
,
2150 struct si_compiler_ctx_state
*compiler_state
,
2151 struct si_shader_key
*key
,
2153 bool optimized_or_none
)
2155 struct si_shader_selector
*sel
= state
->cso
;
2156 struct si_shader_selector
*previous_stage_sel
= NULL
;
2157 struct si_shader
*current
= state
->current
;
2158 struct si_shader
*iter
, *shader
= NULL
;
2161 /* Check if we don't need to change anything.
2162 * This path is also used for most shaders that don't need multiple
2163 * variants, it will cost just a computation of the key and this
2165 if (likely(current
&&
2166 memcmp(¤t
->key
, key
, sizeof(*key
)) == 0)) {
2167 if (unlikely(!util_queue_fence_is_signalled(¤t
->ready
))) {
2168 if (current
->is_optimized
) {
2169 if (optimized_or_none
)
2172 memset(&key
->opt
, 0, sizeof(key
->opt
));
2173 goto current_not_ready
;
2176 util_queue_fence_wait(¤t
->ready
);
2179 return current
->compilation_failed
? -1 : 0;
2183 /* This must be done before the mutex is locked, because async GS
2184 * compilation calls this function too, and therefore must enter
2187 * Only wait if we are in a draw call. Don't wait if we are
2188 * in a compiler thread.
2190 if (thread_index
< 0)
2191 util_queue_fence_wait(&sel
->ready
);
2193 mtx_lock(&sel
->mutex
);
2195 /* Find the shader variant. */
2196 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
2197 /* Don't check the "current" shader. We checked it above. */
2198 if (current
!= iter
&&
2199 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
2200 mtx_unlock(&sel
->mutex
);
2202 if (unlikely(!util_queue_fence_is_signalled(&iter
->ready
))) {
2203 /* If it's an optimized shader and its compilation has
2204 * been started but isn't done, use the unoptimized
2205 * shader so as not to cause a stall due to compilation.
2207 if (iter
->is_optimized
) {
2208 if (optimized_or_none
)
2210 memset(&key
->opt
, 0, sizeof(key
->opt
));
2214 util_queue_fence_wait(&iter
->ready
);
2217 if (iter
->compilation_failed
) {
2218 return -1; /* skip the draw call */
2221 state
->current
= iter
;
2226 /* Build a new shader. */
2227 shader
= CALLOC_STRUCT(si_shader
);
2229 mtx_unlock(&sel
->mutex
);
2233 util_queue_fence_init(&shader
->ready
);
2235 shader
->selector
= sel
;
2237 shader
->compiler_ctx_state
= *compiler_state
;
2239 /* If this is a merged shader, get the first shader's selector. */
2240 if (sscreen
->info
.chip_class
>= GFX9
) {
2241 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
2242 previous_stage_sel
= key
->part
.tcs
.ls
;
2243 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
2244 previous_stage_sel
= key
->part
.gs
.es
;
2246 /* We need to wait for the previous shader. */
2247 if (previous_stage_sel
&& thread_index
< 0)
2248 util_queue_fence_wait(&previous_stage_sel
->ready
);
2251 bool is_pure_monolithic
=
2252 sscreen
->use_monolithic_shaders
||
2253 memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
2255 /* Compile the main shader part if it doesn't exist. This can happen
2256 * if the initial guess was wrong.
2258 * The prim discard CS doesn't need the main shader part.
2260 if (!is_pure_monolithic
&&
2261 !key
->opt
.vs_as_prim_discard_cs
) {
2264 /* Make sure the main shader part is present. This is needed
2265 * for shaders that can be compiled as VS, LS, or ES, and only
2266 * one of them is compiled at creation.
2268 * It is also needed for GS, which can be compiled as non-NGG
2271 * For merged shaders, check that the starting shader's main
2274 if (previous_stage_sel
) {
2275 struct si_shader_key shader1_key
= zeroed
;
2277 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
2278 shader1_key
.as_ls
= 1;
2279 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
2280 shader1_key
.as_es
= 1;
2284 if (sel
->type
== PIPE_SHADER_GEOMETRY
&&
2285 previous_stage_sel
->type
== PIPE_SHADER_TESS_EVAL
)
2286 shader1_key
.as_ngg
= key
->as_ngg
;
2288 mtx_lock(&previous_stage_sel
->mutex
);
2289 ok
= si_check_missing_main_part(sscreen
,
2291 compiler_state
, &shader1_key
);
2292 mtx_unlock(&previous_stage_sel
->mutex
);
2296 ok
= si_check_missing_main_part(sscreen
, sel
,
2297 compiler_state
, key
);
2302 mtx_unlock(&sel
->mutex
);
2303 return -ENOMEM
; /* skip the draw call */
2307 /* Keep the reference to the 1st shader of merged shaders, so that
2308 * Gallium can't destroy it before we destroy the 2nd shader.
2310 * Set sctx = NULL, because it's unused if we're not releasing
2311 * the shader, and we don't have any sctx here.
2313 si_shader_selector_reference(NULL
, &shader
->previous_stage_sel
,
2314 previous_stage_sel
);
2316 /* Monolithic-only shaders don't make a distinction between optimized
2317 * and unoptimized. */
2318 shader
->is_monolithic
=
2319 is_pure_monolithic
||
2320 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
2322 /* The prim discard CS is always optimized. */
2323 shader
->is_optimized
=
2324 (!is_pure_monolithic
|| key
->opt
.vs_as_prim_discard_cs
) &&
2325 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
2327 /* If it's an optimized shader, compile it asynchronously. */
2328 if (shader
->is_optimized
&& thread_index
< 0) {
2329 /* Compile it asynchronously. */
2330 util_queue_add_job(&sscreen
->shader_compiler_queue_low_priority
,
2331 shader
, &shader
->ready
,
2332 si_build_shader_variant_low_priority
, NULL
);
2334 /* Add only after the ready fence was reset, to guard against a
2335 * race with si_bind_XX_shader. */
2336 if (!sel
->last_variant
) {
2337 sel
->first_variant
= shader
;
2338 sel
->last_variant
= shader
;
2340 sel
->last_variant
->next_variant
= shader
;
2341 sel
->last_variant
= shader
;
2344 /* Use the default (unoptimized) shader for now. */
2345 memset(&key
->opt
, 0, sizeof(key
->opt
));
2346 mtx_unlock(&sel
->mutex
);
2348 if (sscreen
->options
.sync_compile
)
2349 util_queue_fence_wait(&shader
->ready
);
2351 if (optimized_or_none
)
2356 /* Reset the fence before adding to the variant list. */
2357 util_queue_fence_reset(&shader
->ready
);
2359 if (!sel
->last_variant
) {
2360 sel
->first_variant
= shader
;
2361 sel
->last_variant
= shader
;
2363 sel
->last_variant
->next_variant
= shader
;
2364 sel
->last_variant
= shader
;
2367 mtx_unlock(&sel
->mutex
);
2369 assert(!shader
->is_optimized
);
2370 si_build_shader_variant(shader
, thread_index
, false);
2372 util_queue_fence_signal(&shader
->ready
);
2374 if (!shader
->compilation_failed
)
2375 state
->current
= shader
;
2377 return shader
->compilation_failed
? -1 : 0;
2380 static int si_shader_select(struct pipe_context
*ctx
,
2381 struct si_shader_ctx_state
*state
,
2382 union si_vgt_stages_key stages_key
,
2383 struct si_compiler_ctx_state
*compiler_state
)
2385 struct si_context
*sctx
= (struct si_context
*)ctx
;
2386 struct si_shader_key key
;
2388 si_shader_selector_key(ctx
, state
->cso
, stages_key
, &key
);
2389 return si_shader_select_with_key(sctx
->screen
, state
, compiler_state
,
2393 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
2395 struct si_shader_key
*key
)
2397 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
2399 switch (info
->processor
) {
2400 case PIPE_SHADER_VERTEX
:
2401 switch (next_shader
) {
2402 case PIPE_SHADER_GEOMETRY
:
2405 case PIPE_SHADER_TESS_CTRL
:
2406 case PIPE_SHADER_TESS_EVAL
:
2410 /* If POSITION isn't written, it can only be a HW VS
2411 * if streamout is used. If streamout isn't used,
2412 * assume that it's a HW LS. (the next shader is TCS)
2413 * This heuristic is needed for separate shader objects.
2415 if (!info
->writes_position
&& !streamout
)
2420 case PIPE_SHADER_TESS_EVAL
:
2421 if (next_shader
== PIPE_SHADER_GEOMETRY
||
2422 !info
->writes_position
)
2429 * Compile the main shader part or the monolithic shader as part of
2430 * si_shader_selector initialization. Since it can be done asynchronously,
2431 * there is no way to report compile failures to applications.
2433 static void si_init_shader_selector_async(void *job
, int thread_index
)
2435 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
2436 struct si_screen
*sscreen
= sel
->screen
;
2437 struct ac_llvm_compiler
*compiler
;
2438 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
2440 assert(!debug
->debug_message
|| debug
->async
);
2441 assert(thread_index
>= 0);
2442 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
2443 compiler
= &sscreen
->compiler
[thread_index
];
2448 /* Compile the main shader part for use with a prolog and/or epilog.
2449 * If this fails, the driver will try to compile a monolithic shader
2452 if (!sscreen
->use_monolithic_shaders
) {
2453 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
2454 void *ir_binary
= NULL
;
2457 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
2461 /* We can leave the fence signaled because use of the default
2462 * main part is guarded by the selector's ready fence. */
2463 util_queue_fence_init(&shader
->ready
);
2465 shader
->selector
= sel
;
2466 shader
->is_monolithic
= false;
2467 si_parse_next_shader_property(&sel
->info
,
2468 sel
->so
.num_outputs
!= 0,
2471 if (sscreen
->use_ngg
&&
2472 (!sel
->so
.num_outputs
|| sscreen
->use_ngg_streamout
) &&
2473 ((sel
->type
== PIPE_SHADER_VERTEX
&&
2474 !shader
->key
.as_ls
&& !shader
->key
.as_es
) ||
2475 sel
->type
== PIPE_SHADER_TESS_EVAL
||
2476 sel
->type
== PIPE_SHADER_GEOMETRY
))
2477 shader
->key
.as_ngg
= 1;
2479 if (sel
->tokens
|| sel
->nir
) {
2480 ir_binary
= si_get_ir_binary(sel
, shader
->key
.as_ngg
,
2484 /* Try to load the shader from the shader cache. */
2485 mtx_lock(&sscreen
->shader_cache_mutex
);
2488 si_shader_cache_load_shader(sscreen
, ir_binary
, shader
)) {
2489 mtx_unlock(&sscreen
->shader_cache_mutex
);
2490 si_shader_dump_stats_for_shader_db(sscreen
, shader
, debug
);
2492 mtx_unlock(&sscreen
->shader_cache_mutex
);
2494 /* Compile the shader if it hasn't been loaded from the cache. */
2495 if (si_compile_tgsi_shader(sscreen
, compiler
, shader
,
2499 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
2504 mtx_lock(&sscreen
->shader_cache_mutex
);
2505 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
, shader
, true))
2507 mtx_unlock(&sscreen
->shader_cache_mutex
);
2511 *si_get_main_shader_part(sel
, &shader
->key
) = shader
;
2513 /* Unset "outputs_written" flags for outputs converted to
2514 * DEFAULT_VAL, so that later inter-shader optimizations don't
2515 * try to eliminate outputs that don't exist in the final
2518 * This is only done if non-monolithic shaders are enabled.
2520 if ((sel
->type
== PIPE_SHADER_VERTEX
||
2521 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
2522 !shader
->key
.as_ls
&&
2523 !shader
->key
.as_es
) {
2526 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2527 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
2529 if (offset
<= AC_EXP_PARAM_OFFSET_31
)
2532 unsigned name
= sel
->info
.output_semantic_name
[i
];
2533 unsigned index
= sel
->info
.output_semantic_index
[i
];
2537 case TGSI_SEMANTIC_GENERIC
:
2538 /* don't process indices the function can't handle */
2539 if (index
>= SI_MAX_IO_GENERIC
)
2543 id
= si_shader_io_get_unique_index(name
, index
, true);
2544 sel
->outputs_written_before_ps
&= ~(1ull << id
);
2546 case TGSI_SEMANTIC_POSITION
: /* ignore these */
2547 case TGSI_SEMANTIC_PSIZE
:
2548 case TGSI_SEMANTIC_CLIPVERTEX
:
2549 case TGSI_SEMANTIC_EDGEFLAG
:
2556 /* The GS copy shader is always pre-compiled. */
2557 if (sel
->type
== PIPE_SHADER_GEOMETRY
&&
2558 (!sscreen
->use_ngg
|| sel
->tess_turns_off_ngg
)) {
2559 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, compiler
, sel
, debug
);
2560 if (!sel
->gs_copy_shader
) {
2561 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
2565 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
2569 void si_schedule_initial_compile(struct si_context
*sctx
, unsigned processor
,
2570 struct util_queue_fence
*ready_fence
,
2571 struct si_compiler_ctx_state
*compiler_ctx_state
,
2572 void *job
, util_queue_execute_func execute
)
2574 util_queue_fence_init(ready_fence
);
2576 struct util_async_debug_callback async_debug
;
2578 (sctx
->debug
.debug_message
&& !sctx
->debug
.async
) ||
2580 si_can_dump_shader(sctx
->screen
, processor
);
2583 u_async_debug_init(&async_debug
);
2584 compiler_ctx_state
->debug
= async_debug
.base
;
2587 util_queue_add_job(&sctx
->screen
->shader_compiler_queue
, job
,
2588 ready_fence
, execute
, NULL
);
2591 util_queue_fence_wait(ready_fence
);
2592 u_async_debug_drain(&async_debug
, &sctx
->debug
);
2593 u_async_debug_cleanup(&async_debug
);
2596 if (sctx
->screen
->options
.sync_compile
)
2597 util_queue_fence_wait(ready_fence
);
2600 /* Return descriptor slot usage masks from the given shader info. */
2601 void si_get_active_slot_masks(const struct tgsi_shader_info
*info
,
2602 uint32_t *const_and_shader_buffers
,
2603 uint64_t *samplers_and_images
)
2605 unsigned start
, num_shaderbufs
, num_constbufs
, num_images
, num_samplers
;
2607 num_shaderbufs
= util_last_bit(info
->shader_buffers_declared
);
2608 num_constbufs
= util_last_bit(info
->const_buffers_declared
);
2609 /* two 8-byte images share one 16-byte slot */
2610 num_images
= align(util_last_bit(info
->images_declared
), 2);
2611 num_samplers
= util_last_bit(info
->samplers_declared
);
2613 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2614 start
= si_get_shaderbuf_slot(num_shaderbufs
- 1);
2615 *const_and_shader_buffers
=
2616 u_bit_consecutive(start
, num_shaderbufs
+ num_constbufs
);
2618 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2619 start
= si_get_image_slot(num_images
- 1) / 2;
2620 *samplers_and_images
=
2621 u_bit_consecutive64(start
, num_images
/ 2 + num_samplers
);
2624 static void *si_create_shader_selector(struct pipe_context
*ctx
,
2625 const struct pipe_shader_state
*state
)
2627 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
2628 struct si_context
*sctx
= (struct si_context
*)ctx
;
2629 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
2635 pipe_reference_init(&sel
->reference
, 1);
2636 sel
->screen
= sscreen
;
2637 sel
->compiler_ctx_state
.debug
= sctx
->debug
;
2638 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
2640 sel
->so
= state
->stream_output
;
2642 if (state
->type
== PIPE_SHADER_IR_TGSI
&&
2643 !sscreen
->options
.enable_nir
) {
2644 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
2650 tgsi_scan_shader(state
->tokens
, &sel
->info
);
2651 tgsi_scan_tess_ctrl(state
->tokens
, &sel
->info
, &sel
->tcs_info
);
2653 /* Fixup for TGSI: Set which opcode uses which (i,j) pair. */
2654 if (sel
->info
.uses_persp_opcode_interp_centroid
)
2655 sel
->info
.uses_persp_centroid
= true;
2657 if (sel
->info
.uses_linear_opcode_interp_centroid
)
2658 sel
->info
.uses_linear_centroid
= true;
2660 if (sel
->info
.uses_persp_opcode_interp_offset
||
2661 sel
->info
.uses_persp_opcode_interp_sample
)
2662 sel
->info
.uses_persp_center
= true;
2664 if (sel
->info
.uses_linear_opcode_interp_offset
||
2665 sel
->info
.uses_linear_opcode_interp_sample
)
2666 sel
->info
.uses_linear_center
= true;
2668 if (state
->type
== PIPE_SHADER_IR_TGSI
) {
2669 sel
->nir
= tgsi_to_nir(state
->tokens
, ctx
->screen
);
2671 assert(state
->type
== PIPE_SHADER_IR_NIR
);
2672 sel
->nir
= state
->ir
.nir
;
2675 si_nir_lower_ps_inputs(sel
->nir
);
2676 si_nir_opts(sel
->nir
);
2677 si_nir_scan_shader(sel
->nir
, &sel
->info
);
2678 si_nir_scan_tess_ctrl(sel
->nir
, &sel
->tcs_info
);
2681 sel
->type
= sel
->info
.processor
;
2682 p_atomic_inc(&sscreen
->num_shaders_created
);
2683 si_get_active_slot_masks(&sel
->info
,
2684 &sel
->active_const_and_shader_buffers
,
2685 &sel
->active_samplers_and_images
);
2687 /* Record which streamout buffers are enabled. */
2688 for (i
= 0; i
< sel
->so
.num_outputs
; i
++) {
2689 sel
->enabled_streamout_buffer_mask
|=
2690 (1 << sel
->so
.output
[i
].output_buffer
) <<
2691 (sel
->so
.output
[i
].stream
* 4);
2694 /* The prolog is a no-op if there are no inputs. */
2695 sel
->vs_needs_prolog
= sel
->type
== PIPE_SHADER_VERTEX
&&
2696 sel
->info
.num_inputs
&&
2697 !sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
];
2699 sel
->force_correct_derivs_after_kill
=
2700 sel
->type
== PIPE_SHADER_FRAGMENT
&&
2701 sel
->info
.uses_derivatives
&&
2702 sel
->info
.uses_kill
&&
2703 sctx
->screen
->debug_flags
& DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
2705 sel
->prim_discard_cs_allowed
=
2706 sel
->type
== PIPE_SHADER_VERTEX
&&
2707 !sel
->info
.uses_bindless_images
&&
2708 !sel
->info
.uses_bindless_samplers
&&
2709 !sel
->info
.writes_memory
&&
2710 !sel
->info
.writes_viewport_index
&&
2711 !sel
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] &&
2712 !sel
->so
.num_outputs
;
2714 if (sel
->type
== PIPE_SHADER_VERTEX
&&
2715 sel
->info
.writes_edgeflag
) {
2716 if (sscreen
->info
.chip_class
>= GFX10
)
2717 sel
->ngg_writes_edgeflag
= true;
2719 sel
->pos_writes_edgeflag
= true;
2722 switch (sel
->type
) {
2723 case PIPE_SHADER_GEOMETRY
:
2724 sel
->gs_output_prim
=
2725 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
2727 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2728 sel
->rast_prim
= sel
->gs_output_prim
;
2729 if (util_rast_prim_is_triangles(sel
->rast_prim
))
2730 sel
->rast_prim
= PIPE_PRIM_TRIANGLES
;
2732 sel
->gs_max_out_vertices
=
2733 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
2734 sel
->gs_num_invocations
=
2735 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
2736 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
2737 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
2738 sel
->gs_max_out_vertices
;
2740 sel
->max_gs_stream
= 0;
2741 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
2742 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
2743 sel
->so
.output
[i
].stream
);
2745 sel
->gs_input_verts_per_prim
=
2746 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
2748 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2749 sel
->tess_turns_off_ngg
=
2750 (sscreen
->info
.family
== CHIP_NAVI10
||
2751 sscreen
->info
.family
== CHIP_NAVI12
||
2752 sscreen
->info
.family
== CHIP_NAVI14
) &&
2753 sel
->gs_num_invocations
* sel
->gs_max_out_vertices
> 256;
2756 case PIPE_SHADER_TESS_CTRL
:
2757 /* Always reserve space for these. */
2758 sel
->patch_outputs_written
|=
2759 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0)) |
2760 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0));
2762 case PIPE_SHADER_VERTEX
:
2763 case PIPE_SHADER_TESS_EVAL
:
2764 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2765 unsigned name
= sel
->info
.output_semantic_name
[i
];
2766 unsigned index
= sel
->info
.output_semantic_index
[i
];
2769 case TGSI_SEMANTIC_TESSINNER
:
2770 case TGSI_SEMANTIC_TESSOUTER
:
2771 case TGSI_SEMANTIC_PATCH
:
2772 sel
->patch_outputs_written
|=
2773 1ull << si_shader_io_get_unique_index_patch(name
, index
);
2776 case TGSI_SEMANTIC_GENERIC
:
2777 /* don't process indices the function can't handle */
2778 if (index
>= SI_MAX_IO_GENERIC
)
2782 sel
->outputs_written
|=
2783 1ull << si_shader_io_get_unique_index(name
, index
, false);
2784 sel
->outputs_written_before_ps
|=
2785 1ull << si_shader_io_get_unique_index(name
, index
, true);
2787 case TGSI_SEMANTIC_EDGEFLAG
:
2791 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
2792 sel
->lshs_vertex_stride
= sel
->esgs_itemsize
;
2794 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2795 * will start on a different bank. (except for the maximum 32*16).
2797 if (sel
->lshs_vertex_stride
< 32*16)
2798 sel
->lshs_vertex_stride
+= 4;
2800 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2801 * conflicts, i.e. each vertex will start at a different bank.
2803 if (sctx
->chip_class
>= GFX9
)
2804 sel
->esgs_itemsize
+= 4;
2806 assert(((sel
->esgs_itemsize
/ 4) & C_028AAC_ITEMSIZE
) == 0);
2809 if (sel
->info
.properties
[TGSI_PROPERTY_TES_POINT_MODE
])
2810 sel
->rast_prim
= PIPE_PRIM_POINTS
;
2811 else if (sel
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] == PIPE_PRIM_LINES
)
2812 sel
->rast_prim
= PIPE_PRIM_LINE_STRIP
;
2814 sel
->rast_prim
= PIPE_PRIM_TRIANGLES
;
2817 case PIPE_SHADER_FRAGMENT
:
2818 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2819 unsigned name
= sel
->info
.input_semantic_name
[i
];
2820 unsigned index
= sel
->info
.input_semantic_index
[i
];
2823 case TGSI_SEMANTIC_GENERIC
:
2824 /* don't process indices the function can't handle */
2825 if (index
>= SI_MAX_IO_GENERIC
)
2830 1ull << si_shader_io_get_unique_index(name
, index
, true);
2832 case TGSI_SEMANTIC_PCOORD
: /* ignore this */
2837 for (i
= 0; i
< 8; i
++)
2838 if (sel
->info
.colors_written
& (1 << i
))
2839 sel
->colors_written_4bit
|= 0xf << (4 * i
);
2841 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2842 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
2843 int index
= sel
->info
.input_semantic_index
[i
];
2844 sel
->color_attr_index
[index
] = i
;
2851 /* PA_CL_VS_OUT_CNTL */
2853 sel
->info
.writes_psize
|| sel
->pos_writes_edgeflag
||
2854 sel
->info
.writes_layer
|| sel
->info
.writes_viewport_index
;
2855 sel
->pa_cl_vs_out_cntl
=
2856 S_02881C_USE_VTX_POINT_SIZE(sel
->info
.writes_psize
) |
2857 S_02881C_USE_VTX_EDGE_FLAG(sel
->pos_writes_edgeflag
) |
2858 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel
->info
.writes_layer
) |
2859 S_02881C_USE_VTX_VIEWPORT_INDX(sel
->info
.writes_viewport_index
) |
2860 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
2861 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
);
2862 sel
->clipdist_mask
= sel
->info
.writes_clipvertex
?
2863 SIX_BITS
: sel
->info
.clipdist_writemask
;
2864 sel
->culldist_mask
= sel
->info
.culldist_writemask
<<
2865 sel
->info
.num_written_clipdistance
;
2867 /* DB_SHADER_CONTROL */
2868 sel
->db_shader_control
=
2869 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
2870 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
2871 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
2872 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
2874 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
2875 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2876 sel
->db_shader_control
|=
2877 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2879 case TGSI_FS_DEPTH_LAYOUT_LESS
:
2880 sel
->db_shader_control
|=
2881 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2885 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2887 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2888 * --|-----------|------------|------------|--------------------|-------------------|-------------
2889 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2890 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2891 * 2 | false | true | n/a | LateZ | 1 | 0
2892 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2893 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2895 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2896 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2898 * Don't use ReZ without profiling !!!
2900 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2903 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
2905 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
2906 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
2907 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
2908 } else if (sel
->info
.writes_memory
) {
2910 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) |
2911 S_02880C_EXEC_ON_HIER_FAIL(1);
2914 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2917 if (sel
->info
.properties
[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
])
2918 sel
->db_shader_control
|= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2920 (void) mtx_init(&sel
->mutex
, mtx_plain
);
2922 si_schedule_initial_compile(sctx
, sel
->info
.processor
, &sel
->ready
,
2923 &sel
->compiler_ctx_state
, sel
,
2924 si_init_shader_selector_async
);
2928 static void si_update_streamout_state(struct si_context
*sctx
)
2930 struct si_shader_selector
*shader_with_so
= si_get_vs(sctx
)->cso
;
2932 if (!shader_with_so
)
2935 sctx
->streamout
.enabled_stream_buffers_mask
=
2936 shader_with_so
->enabled_streamout_buffer_mask
;
2937 sctx
->streamout
.stride_in_dw
= shader_with_so
->so
.stride
;
2940 static void si_update_clip_regs(struct si_context
*sctx
,
2941 struct si_shader_selector
*old_hw_vs
,
2942 struct si_shader
*old_hw_vs_variant
,
2943 struct si_shader_selector
*next_hw_vs
,
2944 struct si_shader
*next_hw_vs_variant
)
2948 old_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] !=
2949 next_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] ||
2950 old_hw_vs
->pa_cl_vs_out_cntl
!= next_hw_vs
->pa_cl_vs_out_cntl
||
2951 old_hw_vs
->clipdist_mask
!= next_hw_vs
->clipdist_mask
||
2952 old_hw_vs
->culldist_mask
!= next_hw_vs
->culldist_mask
||
2953 !old_hw_vs_variant
||
2954 !next_hw_vs_variant
||
2955 old_hw_vs_variant
->key
.opt
.clip_disable
!=
2956 next_hw_vs_variant
->key
.opt
.clip_disable
))
2957 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
2960 static void si_update_common_shader_state(struct si_context
*sctx
)
2962 sctx
->uses_bindless_samplers
=
2963 si_shader_uses_bindless_samplers(sctx
->vs_shader
.cso
) ||
2964 si_shader_uses_bindless_samplers(sctx
->gs_shader
.cso
) ||
2965 si_shader_uses_bindless_samplers(sctx
->ps_shader
.cso
) ||
2966 si_shader_uses_bindless_samplers(sctx
->tcs_shader
.cso
) ||
2967 si_shader_uses_bindless_samplers(sctx
->tes_shader
.cso
);
2968 sctx
->uses_bindless_images
=
2969 si_shader_uses_bindless_images(sctx
->vs_shader
.cso
) ||
2970 si_shader_uses_bindless_images(sctx
->gs_shader
.cso
) ||
2971 si_shader_uses_bindless_images(sctx
->ps_shader
.cso
) ||
2972 si_shader_uses_bindless_images(sctx
->tcs_shader
.cso
) ||
2973 si_shader_uses_bindless_images(sctx
->tes_shader
.cso
);
2974 sctx
->do_update_shaders
= true;
2977 static bool si_update_ngg(struct si_context
*sctx
);
2979 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
2981 struct si_context
*sctx
= (struct si_context
*)ctx
;
2982 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2983 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2984 struct si_shader_selector
*sel
= state
;
2986 if (sctx
->vs_shader
.cso
== sel
)
2989 sctx
->vs_shader
.cso
= sel
;
2990 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2991 sctx
->num_vs_blit_sgprs
= sel
? sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
] : 0;
2993 if (si_update_ngg(sctx
))
2994 si_shader_change_notify(sctx
);
2996 si_update_common_shader_state(sctx
);
2997 si_update_vs_viewport_state(sctx
);
2998 si_set_active_descriptors_for_shader(sctx
, sel
);
2999 si_update_streamout_state(sctx
);
3000 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
3001 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
3004 static void si_update_tess_uses_prim_id(struct si_context
*sctx
)
3006 sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
=
3007 (sctx
->tes_shader
.cso
&&
3008 sctx
->tes_shader
.cso
->info
.uses_primid
) ||
3009 (sctx
->tcs_shader
.cso
&&
3010 sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
3011 (sctx
->gs_shader
.cso
&&
3012 sctx
->gs_shader
.cso
->info
.uses_primid
) ||
3013 (sctx
->ps_shader
.cso
&& !sctx
->gs_shader
.cso
&&
3014 sctx
->ps_shader
.cso
->info
.uses_primid
);
3017 static bool si_update_ngg(struct si_context
*sctx
)
3019 if (!sctx
->screen
->use_ngg
) {
3024 bool new_ngg
= true;
3026 if (sctx
->gs_shader
.cso
&& sctx
->tes_shader
.cso
&&
3027 sctx
->gs_shader
.cso
->tess_turns_off_ngg
) {
3029 } else if (!sctx
->screen
->use_ngg_streamout
) {
3030 struct si_shader_selector
*last
= si_get_vs(sctx
)->cso
;
3032 if (last
&& last
->so
.num_outputs
)
3036 if (new_ngg
!= sctx
->ngg
) {
3037 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
3038 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
3041 if ((sctx
->family
== CHIP_NAVI10
||
3042 sctx
->family
== CHIP_NAVI12
||
3043 sctx
->family
== CHIP_NAVI14
) &&
3045 sctx
->flags
|= SI_CONTEXT_VGT_FLUSH
;
3047 sctx
->ngg
= new_ngg
;
3048 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
3054 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
3056 struct si_context
*sctx
= (struct si_context
*)ctx
;
3057 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
3058 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
3059 struct si_shader_selector
*sel
= state
;
3060 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
3063 if (sctx
->gs_shader
.cso
== sel
)
3066 sctx
->gs_shader
.cso
= sel
;
3067 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
3068 sctx
->ia_multi_vgt_param_key
.u
.uses_gs
= sel
!= NULL
;
3070 si_update_common_shader_state(sctx
);
3071 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
3073 ngg_changed
= si_update_ngg(sctx
);
3074 if (ngg_changed
|| enable_changed
)
3075 si_shader_change_notify(sctx
);
3076 if (enable_changed
) {
3077 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
3078 si_update_tess_uses_prim_id(sctx
);
3080 si_update_vs_viewport_state(sctx
);
3081 si_set_active_descriptors_for_shader(sctx
, sel
);
3082 si_update_streamout_state(sctx
);
3083 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
3084 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
3087 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
3089 struct si_context
*sctx
= (struct si_context
*)ctx
;
3090 struct si_shader_selector
*sel
= state
;
3091 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
3093 if (sctx
->tcs_shader
.cso
== sel
)
3096 sctx
->tcs_shader
.cso
= sel
;
3097 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
3098 si_update_tess_uses_prim_id(sctx
);
3100 si_update_common_shader_state(sctx
);
3103 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
3105 si_set_active_descriptors_for_shader(sctx
, sel
);
3108 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
3110 struct si_context
*sctx
= (struct si_context
*)ctx
;
3111 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
3112 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
3113 struct si_shader_selector
*sel
= state
;
3114 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
3116 if (sctx
->tes_shader
.cso
== sel
)
3119 sctx
->tes_shader
.cso
= sel
;
3120 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
3121 sctx
->ia_multi_vgt_param_key
.u
.uses_tess
= sel
!= NULL
;
3122 si_update_tess_uses_prim_id(sctx
);
3124 si_update_common_shader_state(sctx
);
3125 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
3127 bool ngg_changed
= si_update_ngg(sctx
);
3128 if (ngg_changed
|| enable_changed
)
3129 si_shader_change_notify(sctx
);
3131 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
3132 si_update_vs_viewport_state(sctx
);
3133 si_set_active_descriptors_for_shader(sctx
, sel
);
3134 si_update_streamout_state(sctx
);
3135 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
3136 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
3139 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
3141 struct si_context
*sctx
= (struct si_context
*)ctx
;
3142 struct si_shader_selector
*old_sel
= sctx
->ps_shader
.cso
;
3143 struct si_shader_selector
*sel
= state
;
3145 /* skip if supplied shader is one already in use */
3149 sctx
->ps_shader
.cso
= sel
;
3150 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
3152 si_update_common_shader_state(sctx
);
3154 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
3155 si_update_tess_uses_prim_id(sctx
);
3158 old_sel
->info
.colors_written
!= sel
->info
.colors_written
)
3159 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3161 if (sctx
->screen
->has_out_of_order_rast
&&
3163 old_sel
->info
.writes_memory
!= sel
->info
.writes_memory
||
3164 old_sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] !=
3165 sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]))
3166 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3168 si_set_active_descriptors_for_shader(sctx
, sel
);
3169 si_update_ps_colorbuf0_slot(sctx
);
3172 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
3174 if (shader
->is_optimized
) {
3175 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue_low_priority
,
3179 util_queue_fence_destroy(&shader
->ready
);
3182 /* If destroyed shaders were not unbound, the next compiled
3183 * shader variant could get the same pointer address and so
3184 * binding it to the same shader stage would be considered
3185 * a no-op, causing random behavior.
3187 switch (shader
->selector
->type
) {
3188 case PIPE_SHADER_VERTEX
:
3189 if (shader
->key
.as_ls
) {
3190 assert(sctx
->chip_class
<= GFX8
);
3191 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
3192 } else if (shader
->key
.as_es
) {
3193 assert(sctx
->chip_class
<= GFX8
);
3194 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
3195 } else if (shader
->key
.as_ngg
) {
3196 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3198 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3201 case PIPE_SHADER_TESS_CTRL
:
3202 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
3204 case PIPE_SHADER_TESS_EVAL
:
3205 if (shader
->key
.as_es
) {
3206 assert(sctx
->chip_class
<= GFX8
);
3207 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
3208 } else if (shader
->key
.as_ngg
) {
3209 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3211 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3214 case PIPE_SHADER_GEOMETRY
:
3215 if (shader
->is_gs_copy_shader
)
3216 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3218 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3220 case PIPE_SHADER_FRAGMENT
:
3221 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
3227 si_shader_selector_reference(sctx
, &shader
->previous_stage_sel
, NULL
);
3228 si_shader_destroy(shader
);
3232 void si_destroy_shader_selector(struct si_context
*sctx
,
3233 struct si_shader_selector
*sel
)
3235 struct si_shader
*p
= sel
->first_variant
, *c
;
3236 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
3237 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
3238 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
3239 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
3240 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
3241 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
3244 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue
, &sel
->ready
);
3246 if (current_shader
[sel
->type
]->cso
== sel
) {
3247 current_shader
[sel
->type
]->cso
= NULL
;
3248 current_shader
[sel
->type
]->current
= NULL
;
3252 c
= p
->next_variant
;
3253 si_delete_shader(sctx
, p
);
3257 if (sel
->main_shader_part
)
3258 si_delete_shader(sctx
, sel
->main_shader_part
);
3259 if (sel
->main_shader_part_ls
)
3260 si_delete_shader(sctx
, sel
->main_shader_part_ls
);
3261 if (sel
->main_shader_part_es
)
3262 si_delete_shader(sctx
, sel
->main_shader_part_es
);
3263 if (sel
->main_shader_part_ngg
)
3264 si_delete_shader(sctx
, sel
->main_shader_part_ngg
);
3265 if (sel
->gs_copy_shader
)
3266 si_delete_shader(sctx
, sel
->gs_copy_shader
);
3268 util_queue_fence_destroy(&sel
->ready
);
3269 mtx_destroy(&sel
->mutex
);
3271 ralloc_free(sel
->nir
);
3275 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
3277 struct si_context
*sctx
= (struct si_context
*)ctx
;
3278 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
3280 si_shader_selector_reference(sctx
, &sel
, NULL
);
3283 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
3284 struct si_shader
*vs
, unsigned name
,
3285 unsigned index
, unsigned interpolate
)
3287 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
3288 unsigned j
, offset
, ps_input_cntl
= 0;
3290 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
3291 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
) ||
3292 name
== TGSI_SEMANTIC_PRIMID
)
3293 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
3295 if (name
== TGSI_SEMANTIC_PCOORD
||
3296 (name
== TGSI_SEMANTIC_TEXCOORD
&&
3297 sctx
->sprite_coord_enable
& (1 << index
))) {
3298 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
3301 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
3302 if (name
== vsinfo
->output_semantic_name
[j
] &&
3303 index
== vsinfo
->output_semantic_index
[j
]) {
3304 offset
= vs
->info
.vs_output_param_offset
[j
];
3306 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
3307 /* The input is loaded from parameter memory. */
3308 ps_input_cntl
|= S_028644_OFFSET(offset
);
3309 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
3310 if (offset
== AC_EXP_PARAM_UNDEFINED
) {
3311 /* This can happen with depth-only rendering. */
3314 /* The input is a DEFAULT_VAL constant. */
3315 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
3316 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
3317 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
3320 ps_input_cntl
= S_028644_OFFSET(0x20) |
3321 S_028644_DEFAULT_VAL(offset
);
3327 if (j
== vsinfo
->num_outputs
&& name
== TGSI_SEMANTIC_PRIMID
)
3328 /* PrimID is written after the last output when HW VS is used. */
3329 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
3330 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
3331 /* No corresponding output found, load defaults into input.
3332 * Don't set any other bits.
3333 * (FLAT_SHADE=1 completely changes behavior) */
3334 ps_input_cntl
= S_028644_OFFSET(0x20);
3335 /* D3D 9 behaviour. GL is undefined */
3336 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
3337 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
3339 return ps_input_cntl
;
3342 static void si_emit_spi_map(struct si_context
*sctx
)
3344 struct si_shader
*ps
= sctx
->ps_shader
.current
;
3345 struct si_shader
*vs
= si_get_vs_state(sctx
);
3346 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
3347 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
3348 unsigned spi_ps_input_cntl
[32];
3350 if (!ps
|| !ps
->selector
->info
.num_inputs
)
3353 num_interp
= si_get_ps_num_interp(ps
);
3354 assert(num_interp
> 0);
3356 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
3357 unsigned name
= psinfo
->input_semantic_name
[i
];
3358 unsigned index
= psinfo
->input_semantic_index
[i
];
3359 unsigned interpolate
= psinfo
->input_interpolate
[i
];
3361 spi_ps_input_cntl
[num_written
++] = si_get_ps_input_cntl(sctx
, vs
, name
,
3362 index
, interpolate
);
3364 if (name
== TGSI_SEMANTIC_COLOR
) {
3365 assert(index
< ARRAY_SIZE(bcol_interp
));
3366 bcol_interp
[index
] = interpolate
;
3370 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
3371 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
3373 for (i
= 0; i
< 2; i
++) {
3374 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
3377 spi_ps_input_cntl
[num_written
++] =
3378 si_get_ps_input_cntl(sctx
, vs
, bcol
, i
, bcol_interp
[i
]);
3382 assert(num_interp
== num_written
);
3384 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3385 /* Dota 2: Only ~16% of SPI map updates set different values. */
3386 /* Talos: Only ~9% of SPI map updates set different values. */
3387 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
3388 radeon_opt_set_context_regn(sctx
, R_028644_SPI_PS_INPUT_CNTL_0
,
3390 sctx
->tracked_regs
.spi_ps_input_cntl
, num_interp
);
3392 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
3393 sctx
->context_roll
= true;
3397 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3399 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
3401 if (sctx
->init_config_has_vgt_flush
)
3404 /* Done by Vulkan before VGT_FLUSH. */
3405 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
3406 si_pm4_cmd_add(sctx
->init_config
,
3407 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3408 si_pm4_cmd_end(sctx
->init_config
, false);
3410 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3411 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
3412 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
3413 si_pm4_cmd_end(sctx
->init_config
, false);
3414 sctx
->init_config_has_vgt_flush
= true;
3417 /* Initialize state related to ESGS / GSVS ring buffers */
3418 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
3420 struct si_shader_selector
*es
=
3421 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
3422 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
3423 struct si_pm4_state
*pm4
;
3425 /* Chip constants. */
3426 unsigned num_se
= sctx
->screen
->info
.max_se
;
3427 unsigned wave_size
= 64;
3428 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
3429 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3430 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3432 unsigned gs_vertex_reuse
= (sctx
->chip_class
>= GFX8
? 32 : 16) * num_se
;
3433 unsigned alignment
= 256 * num_se
;
3434 /* The maximum size is 63.999 MB per SE. */
3435 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
3437 /* Calculate the minimum size. */
3438 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
3439 wave_size
, alignment
);
3441 /* These are recommended sizes, not minimum sizes. */
3442 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
3443 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
3444 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
3445 gs
->max_gsvs_emit_size
;
3447 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
3448 esgs_ring_size
= align(esgs_ring_size
, alignment
);
3449 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
3451 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
3452 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
3454 /* Some rings don't have to be allocated if shaders don't use them.
3455 * (e.g. no varyings between ES and GS or GS and VS)
3457 * GFX9 doesn't have the ESGS ring.
3459 bool update_esgs
= sctx
->chip_class
<= GFX8
&&
3461 (!sctx
->esgs_ring
||
3462 sctx
->esgs_ring
->width0
< esgs_ring_size
);
3463 bool update_gsvs
= gsvs_ring_size
&&
3464 (!sctx
->gsvs_ring
||
3465 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
3467 if (!update_esgs
&& !update_gsvs
)
3471 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
3473 pipe_aligned_buffer_create(sctx
->b
.screen
,
3474 SI_RESOURCE_FLAG_UNMAPPABLE
,
3476 esgs_ring_size
, alignment
);
3477 if (!sctx
->esgs_ring
)
3482 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
3484 pipe_aligned_buffer_create(sctx
->b
.screen
,
3485 SI_RESOURCE_FLAG_UNMAPPABLE
,
3487 gsvs_ring_size
, alignment
);
3488 if (!sctx
->gsvs_ring
)
3492 /* Create the "init_config_gs_rings" state. */
3493 pm4
= CALLOC_STRUCT(si_pm4_state
);
3497 if (sctx
->chip_class
>= GFX7
) {
3498 if (sctx
->esgs_ring
) {
3499 assert(sctx
->chip_class
<= GFX8
);
3500 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
3501 sctx
->esgs_ring
->width0
/ 256);
3503 if (sctx
->gsvs_ring
)
3504 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
3505 sctx
->gsvs_ring
->width0
/ 256);
3507 if (sctx
->esgs_ring
)
3508 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
3509 sctx
->esgs_ring
->width0
/ 256);
3510 if (sctx
->gsvs_ring
)
3511 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
3512 sctx
->gsvs_ring
->width0
/ 256);
3515 /* Set the state. */
3516 if (sctx
->init_config_gs_rings
)
3517 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
3518 sctx
->init_config_gs_rings
= pm4
;
3520 if (!sctx
->init_config_has_vgt_flush
) {
3521 si_init_config_add_vgt_flush(sctx
);
3522 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3525 /* Flush the context to re-emit both init_config states. */
3526 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3527 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3529 /* Set ring bindings. */
3530 if (sctx
->esgs_ring
) {
3531 assert(sctx
->chip_class
<= GFX8
);
3532 si_set_ring_buffer(sctx
, SI_ES_RING_ESGS
,
3533 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
3534 true, true, 4, 64, 0);
3535 si_set_ring_buffer(sctx
, SI_GS_RING_ESGS
,
3536 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
3537 false, false, 0, 0, 0);
3539 if (sctx
->gsvs_ring
) {
3540 si_set_ring_buffer(sctx
, SI_RING_GSVS
,
3541 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
3542 false, false, 0, 0, 0);
3548 static void si_shader_lock(struct si_shader
*shader
)
3550 mtx_lock(&shader
->selector
->mutex
);
3551 if (shader
->previous_stage_sel
) {
3552 assert(shader
->previous_stage_sel
!= shader
->selector
);
3553 mtx_lock(&shader
->previous_stage_sel
->mutex
);
3557 static void si_shader_unlock(struct si_shader
*shader
)
3559 if (shader
->previous_stage_sel
)
3560 mtx_unlock(&shader
->previous_stage_sel
->mutex
);
3561 mtx_unlock(&shader
->selector
->mutex
);
3565 * @returns 1 if \p sel has been updated to use a new scratch buffer
3567 * < 0 if there was a failure
3569 static int si_update_scratch_buffer(struct si_context
*sctx
,
3570 struct si_shader
*shader
)
3572 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
3577 /* This shader doesn't need a scratch buffer */
3578 if (shader
->config
.scratch_bytes_per_wave
== 0)
3581 /* Prevent race conditions when updating:
3582 * - si_shader::scratch_bo
3583 * - si_shader::binary::code
3584 * - si_shader::previous_stage::binary::code.
3586 si_shader_lock(shader
);
3588 /* This shader is already configured to use the current
3589 * scratch buffer. */
3590 if (shader
->scratch_bo
== sctx
->scratch_buffer
) {
3591 si_shader_unlock(shader
);
3595 assert(sctx
->scratch_buffer
);
3597 /* Replace the shader bo with a new bo that has the relocs applied. */
3598 if (!si_shader_binary_upload(sctx
->screen
, shader
, scratch_va
)) {
3599 si_shader_unlock(shader
);
3603 /* Update the shader state to use the new shader bo. */
3604 si_shader_init_pm4_state(sctx
->screen
, shader
);
3606 si_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
3608 si_shader_unlock(shader
);
3612 static unsigned si_get_current_scratch_buffer_size(struct si_context
*sctx
)
3614 return sctx
->scratch_buffer
? sctx
->scratch_buffer
->b
.b
.width0
: 0;
3617 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
3619 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
3622 static struct si_shader
*si_get_tcs_current(struct si_context
*sctx
)
3624 if (!sctx
->tes_shader
.cso
)
3625 return NULL
; /* tessellation disabled */
3627 return sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.current
:
3628 sctx
->fixed_func_tcs_shader
.current
;
3631 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context
*sctx
)
3635 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
3636 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
3637 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
3638 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
3640 if (sctx
->tes_shader
.cso
) {
3641 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
3643 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(tcs
));
3648 static bool si_update_scratch_relocs(struct si_context
*sctx
)
3650 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
3653 /* Update the shaders, so that they are using the latest scratch.
3654 * The scratch buffer may have been changed since these shaders were
3655 * last used, so we still need to try to update them, even if they
3656 * require scratch buffers smaller than the current size.
3658 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
3662 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3664 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
3668 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3670 r
= si_update_scratch_buffer(sctx
, tcs
);
3674 si_pm4_bind_state(sctx
, hs
, tcs
->pm4
);
3676 /* VS can be bound as LS, ES, or VS. */
3677 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
3681 if (sctx
->vs_shader
.current
->key
.as_ls
)
3682 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3683 else if (sctx
->vs_shader
.current
->key
.as_es
)
3684 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3685 else if (sctx
->vs_shader
.current
->key
.as_ngg
)
3686 si_pm4_bind_state(sctx
, gs
, sctx
->vs_shader
.current
->pm4
);
3688 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3691 /* TES can be bound as ES or VS. */
3692 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
3696 if (sctx
->tes_shader
.current
->key
.as_es
)
3697 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3698 else if (sctx
->tes_shader
.current
->key
.as_ngg
)
3699 si_pm4_bind_state(sctx
, gs
, sctx
->tes_shader
.current
->pm4
);
3701 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3707 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
3709 unsigned current_scratch_buffer_size
=
3710 si_get_current_scratch_buffer_size(sctx
);
3711 unsigned scratch_bytes_per_wave
=
3712 si_get_max_scratch_bytes_per_wave(sctx
);
3713 unsigned scratch_needed_size
= scratch_bytes_per_wave
*
3714 sctx
->scratch_waves
;
3715 unsigned spi_tmpring_size
;
3717 if (scratch_needed_size
> 0) {
3718 if (scratch_needed_size
> current_scratch_buffer_size
) {
3719 /* Create a bigger scratch buffer */
3720 si_resource_reference(&sctx
->scratch_buffer
, NULL
);
3722 sctx
->scratch_buffer
=
3723 si_aligned_buffer_create(&sctx
->screen
->b
,
3724 SI_RESOURCE_FLAG_UNMAPPABLE
,
3726 scratch_needed_size
, 256);
3727 if (!sctx
->scratch_buffer
)
3730 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3731 si_context_add_resource_size(sctx
,
3732 &sctx
->scratch_buffer
->b
.b
);
3735 if (!si_update_scratch_relocs(sctx
))
3739 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3740 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
3741 "scratch size should already be aligned correctly.");
3743 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
3744 S_0286E8_WAVESIZE(scratch_bytes_per_wave
>> 10);
3745 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
3746 sctx
->spi_tmpring_size
= spi_tmpring_size
;
3747 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3752 static void si_init_tess_factor_ring(struct si_context
*sctx
)
3754 assert(!sctx
->tess_rings
);
3755 assert(((sctx
->screen
->tess_factor_ring_size
/ 4) & C_030938_SIZE
) == 0);
3757 /* The address must be aligned to 2^19, because the shader only
3758 * receives the high 13 bits.
3760 sctx
->tess_rings
= pipe_aligned_buffer_create(sctx
->b
.screen
,
3761 SI_RESOURCE_FLAG_32BIT
,
3763 sctx
->screen
->tess_offchip_ring_size
+
3764 sctx
->screen
->tess_factor_ring_size
,
3766 if (!sctx
->tess_rings
)
3769 si_init_config_add_vgt_flush(sctx
);
3771 si_pm4_add_bo(sctx
->init_config
, si_resource(sctx
->tess_rings
),
3772 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
3774 uint64_t factor_va
= si_resource(sctx
->tess_rings
)->gpu_address
+
3775 sctx
->screen
->tess_offchip_ring_size
;
3777 /* Append these registers to the init config state. */
3778 if (sctx
->chip_class
>= GFX7
) {
3779 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
3780 S_030938_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3781 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
3783 if (sctx
->chip_class
>= GFX10
)
3784 si_pm4_set_reg(sctx
->init_config
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
3785 S_030984_BASE_HI(factor_va
>> 40));
3786 else if (sctx
->chip_class
== GFX9
)
3787 si_pm4_set_reg(sctx
->init_config
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3788 S_030944_BASE_HI(factor_va
>> 40));
3789 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3790 sctx
->screen
->vgt_hs_offchip_param
);
3792 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
3793 S_008988_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3794 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
3796 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3797 sctx
->screen
->vgt_hs_offchip_param
);
3800 /* Flush the context to re-emit the init_config state.
3801 * This is done only once in a lifetime of a context.
3803 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3804 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3805 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3808 static struct si_pm4_state
*si_build_vgt_shader_config(struct si_screen
*screen
,
3809 union si_vgt_stages_key key
)
3811 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
3812 uint32_t stages
= 0;
3815 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3816 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3819 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3822 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
3824 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3825 } else if (key
.u
.gs
) {
3826 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3828 } else if (key
.u
.ngg
) {
3829 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
3833 stages
|= S_028B54_PRIMGEN_EN(1);
3834 if (key
.u
.streamout
)
3835 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
3836 } else if (key
.u
.gs
)
3837 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3839 if (screen
->info
.chip_class
>= GFX9
)
3840 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3842 if (screen
->info
.chip_class
>= GFX10
&& screen
->ge_wave_size
== 32) {
3843 stages
|= S_028B54_HS_W32_EN(1) |
3844 S_028B54_GS_W32_EN(key
.u
.ngg
) | /* legacy GS only supports Wave64 */
3845 S_028B54_VS_W32_EN(1);
3848 si_pm4_set_reg(pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
3852 static void si_update_vgt_shader_config(struct si_context
*sctx
,
3853 union si_vgt_stages_key key
)
3855 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[key
.index
];
3857 if (unlikely(!*pm4
))
3858 *pm4
= si_build_vgt_shader_config(sctx
->screen
, key
);
3859 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
3862 bool si_update_shaders(struct si_context
*sctx
)
3864 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
3865 struct si_compiler_ctx_state compiler_state
;
3866 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3867 struct si_shader
*old_vs
= si_get_vs_state(sctx
);
3868 bool old_clip_disable
= old_vs
? old_vs
->key
.opt
.clip_disable
: false;
3869 struct si_shader
*old_ps
= sctx
->ps_shader
.current
;
3870 union si_vgt_stages_key key
;
3871 unsigned old_spi_shader_col_format
=
3872 old_ps
? old_ps
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
3875 compiler_state
.compiler
= &sctx
->compiler
;
3876 compiler_state
.debug
= sctx
->debug
;
3877 compiler_state
.is_debug_context
= sctx
->is_debug
;
3881 if (sctx
->tes_shader
.cso
)
3883 if (sctx
->gs_shader
.cso
)
3888 key
.u
.streamout
= !!si_get_vs(sctx
)->cso
->so
.num_outputs
;
3891 /* Update TCS and TES. */
3892 if (sctx
->tes_shader
.cso
) {
3893 if (!sctx
->tess_rings
) {
3894 si_init_tess_factor_ring(sctx
);
3895 if (!sctx
->tess_rings
)
3899 if (sctx
->tcs_shader
.cso
) {
3900 r
= si_shader_select(ctx
, &sctx
->tcs_shader
, key
,
3904 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
3906 if (!sctx
->fixed_func_tcs_shader
.cso
) {
3907 sctx
->fixed_func_tcs_shader
.cso
=
3908 si_create_fixed_func_tcs(sctx
);
3909 if (!sctx
->fixed_func_tcs_shader
.cso
)
3913 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
,
3914 key
, &compiler_state
);
3917 si_pm4_bind_state(sctx
, hs
,
3918 sctx
->fixed_func_tcs_shader
.current
->pm4
);
3921 if (!sctx
->gs_shader
.cso
|| sctx
->chip_class
<= GFX8
) {
3922 r
= si_shader_select(ctx
, &sctx
->tes_shader
, key
, &compiler_state
);
3926 if (sctx
->gs_shader
.cso
) {
3928 assert(sctx
->chip_class
<= GFX8
);
3929 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3930 } else if (key
.u
.ngg
) {
3931 si_pm4_bind_state(sctx
, gs
, sctx
->tes_shader
.current
->pm4
);
3933 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3937 if (sctx
->chip_class
<= GFX8
)
3938 si_pm4_bind_state(sctx
, ls
, NULL
);
3939 si_pm4_bind_state(sctx
, hs
, NULL
);
3943 if (sctx
->gs_shader
.cso
) {
3944 r
= si_shader_select(ctx
, &sctx
->gs_shader
, key
, &compiler_state
);
3947 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3949 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
3951 if (!si_update_gs_ring_buffers(sctx
))
3954 si_pm4_bind_state(sctx
, vs
, NULL
);
3958 si_pm4_bind_state(sctx
, gs
, NULL
);
3959 if (sctx
->chip_class
<= GFX8
)
3960 si_pm4_bind_state(sctx
, es
, NULL
);
3965 if ((!key
.u
.tess
&& !key
.u
.gs
) || sctx
->chip_class
<= GFX8
) {
3966 r
= si_shader_select(ctx
, &sctx
->vs_shader
, key
, &compiler_state
);
3970 if (!key
.u
.tess
&& !key
.u
.gs
) {
3972 si_pm4_bind_state(sctx
, gs
, sctx
->vs_shader
.current
->pm4
);
3973 si_pm4_bind_state(sctx
, vs
, NULL
);
3975 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3977 } else if (sctx
->tes_shader
.cso
) {
3978 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3980 assert(sctx
->gs_shader
.cso
);
3981 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3985 si_update_vgt_shader_config(sctx
, key
);
3987 if (old_clip_disable
!= si_get_vs_state(sctx
)->key
.opt
.clip_disable
)
3988 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
3990 if (sctx
->ps_shader
.cso
) {
3991 unsigned db_shader_control
;
3993 r
= si_shader_select(ctx
, &sctx
->ps_shader
, key
, &compiler_state
);
3996 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3999 sctx
->ps_shader
.cso
->db_shader_control
|
4000 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
4002 if (si_pm4_state_changed(sctx
, ps
) ||
4003 si_pm4_state_changed(sctx
, vs
) ||
4004 (key
.u
.ngg
&& si_pm4_state_changed(sctx
, gs
)) ||
4005 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
4006 sctx
->flatshade
!= rs
->flatshade
) {
4007 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
4008 sctx
->flatshade
= rs
->flatshade
;
4009 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.spi_map
);
4012 if (sctx
->screen
->info
.rbplus_allowed
&&
4013 si_pm4_state_changed(sctx
, ps
) &&
4015 old_spi_shader_col_format
!=
4016 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
))
4017 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
4019 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
4020 sctx
->ps_db_shader_control
= db_shader_control
;
4021 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
4022 if (sctx
->screen
->dpbb_allowed
)
4023 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
4026 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
4027 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
4028 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
4030 if (sctx
->chip_class
== GFX6
)
4031 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
4033 if (sctx
->framebuffer
.nr_samples
<= 1)
4034 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
4038 if (si_pm4_state_enabled_and_changed(sctx
, ls
) ||
4039 si_pm4_state_enabled_and_changed(sctx
, hs
) ||
4040 si_pm4_state_enabled_and_changed(sctx
, es
) ||
4041 si_pm4_state_enabled_and_changed(sctx
, gs
) ||
4042 si_pm4_state_enabled_and_changed(sctx
, vs
) ||
4043 si_pm4_state_enabled_and_changed(sctx
, ps
)) {
4044 if (!si_update_spi_tmpring_size(sctx
))
4048 if (sctx
->chip_class
>= GFX7
) {
4049 if (si_pm4_state_enabled_and_changed(sctx
, ls
))
4050 sctx
->prefetch_L2_mask
|= SI_PREFETCH_LS
;
4051 else if (!sctx
->queued
.named
.ls
)
4052 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_LS
;
4054 if (si_pm4_state_enabled_and_changed(sctx
, hs
))
4055 sctx
->prefetch_L2_mask
|= SI_PREFETCH_HS
;
4056 else if (!sctx
->queued
.named
.hs
)
4057 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_HS
;
4059 if (si_pm4_state_enabled_and_changed(sctx
, es
))
4060 sctx
->prefetch_L2_mask
|= SI_PREFETCH_ES
;
4061 else if (!sctx
->queued
.named
.es
)
4062 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_ES
;
4064 if (si_pm4_state_enabled_and_changed(sctx
, gs
))
4065 sctx
->prefetch_L2_mask
|= SI_PREFETCH_GS
;
4066 else if (!sctx
->queued
.named
.gs
)
4067 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_GS
;
4069 if (si_pm4_state_enabled_and_changed(sctx
, vs
))
4070 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VS
;
4071 else if (!sctx
->queued
.named
.vs
)
4072 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_VS
;
4074 if (si_pm4_state_enabled_and_changed(sctx
, ps
))
4075 sctx
->prefetch_L2_mask
|= SI_PREFETCH_PS
;
4076 else if (!sctx
->queued
.named
.ps
)
4077 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_PS
;
4080 sctx
->do_update_shaders
= false;
4084 static void si_emit_scratch_state(struct si_context
*sctx
)
4086 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
4088 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
4089 sctx
->spi_tmpring_size
);
4091 if (sctx
->scratch_buffer
) {
4092 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
4093 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
4094 RADEON_PRIO_SCRATCH_BUFFER
);
4098 void si_init_shader_functions(struct si_context
*sctx
)
4100 sctx
->atoms
.s
.spi_map
.emit
= si_emit_spi_map
;
4101 sctx
->atoms
.s
.scratch_state
.emit
= si_emit_scratch_state
;
4103 sctx
->b
.create_vs_state
= si_create_shader_selector
;
4104 sctx
->b
.create_tcs_state
= si_create_shader_selector
;
4105 sctx
->b
.create_tes_state
= si_create_shader_selector
;
4106 sctx
->b
.create_gs_state
= si_create_shader_selector
;
4107 sctx
->b
.create_fs_state
= si_create_shader_selector
;
4109 sctx
->b
.bind_vs_state
= si_bind_vs_shader
;
4110 sctx
->b
.bind_tcs_state
= si_bind_tcs_shader
;
4111 sctx
->b
.bind_tes_state
= si_bind_tes_shader
;
4112 sctx
->b
.bind_gs_state
= si_bind_gs_shader
;
4113 sctx
->b
.bind_fs_state
= si_bind_ps_shader
;
4115 sctx
->b
.delete_vs_state
= si_delete_shader_selector
;
4116 sctx
->b
.delete_tcs_state
= si_delete_shader_selector
;
4117 sctx
->b
.delete_tes_state
= si_delete_shader_selector
;
4118 sctx
->b
.delete_gs_state
= si_delete_shader_selector
;
4119 sctx
->b
.delete_fs_state
= si_delete_shader_selector
;