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radeonsi: unify HS max_offchip_buffers workarounds
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "sid.h"
30 #include "gfx9d.h"
31 #include "radeon/r600_cs.h"
32
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/hash_table.h"
36 #include "util/crc32.h"
37 #include "util/u_memory.h"
38 #include "util/u_prim.h"
39
40 #include "util/disk_cache.h"
41 #include "util/mesa-sha1.h"
42
43 /* SHADER_CACHE */
44
45 /**
46 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
47 * integer.
48 */
49 static void *si_get_tgsi_binary(struct si_shader_selector *sel)
50 {
51 unsigned tgsi_size = tgsi_num_tokens(sel->tokens) *
52 sizeof(struct tgsi_token);
53 unsigned size = 4 + tgsi_size + sizeof(sel->so);
54 char *result = (char*)MALLOC(size);
55
56 if (!result)
57 return NULL;
58
59 *((uint32_t*)result) = size;
60 memcpy(result + 4, sel->tokens, tgsi_size);
61 memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so));
62 return result;
63 }
64
65 /** Copy "data" to "ptr" and return the next dword following copied data. */
66 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
67 {
68 /* data may be NULL if size == 0 */
69 if (size)
70 memcpy(ptr, data, size);
71 ptr += DIV_ROUND_UP(size, 4);
72 return ptr;
73 }
74
75 /** Read data from "ptr". Return the next dword following the data. */
76 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
77 {
78 memcpy(data, ptr, size);
79 ptr += DIV_ROUND_UP(size, 4);
80 return ptr;
81 }
82
83 /**
84 * Write the size as uint followed by the data. Return the next dword
85 * following the copied data.
86 */
87 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
88 {
89 *ptr++ = size;
90 return write_data(ptr, data, size);
91 }
92
93 /**
94 * Read the size as uint followed by the data. Return both via parameters.
95 * Return the next dword following the data.
96 */
97 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
98 {
99 *size = *ptr++;
100 assert(*data == NULL);
101 if (!*size)
102 return ptr;
103 *data = malloc(*size);
104 return read_data(ptr, *data, *size);
105 }
106
107 /**
108 * Return the shader binary in a buffer. The first 4 bytes contain its size
109 * as integer.
110 */
111 static void *si_get_shader_binary(struct si_shader *shader)
112 {
113 /* There is always a size of data followed by the data itself. */
114 unsigned relocs_size = shader->binary.reloc_count *
115 sizeof(shader->binary.relocs[0]);
116 unsigned disasm_size = strlen(shader->binary.disasm_string) + 1;
117 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
118 strlen(shader->binary.llvm_ir_string) + 1 : 0;
119 unsigned size =
120 4 + /* total size */
121 4 + /* CRC32 of the data below */
122 align(sizeof(shader->config), 4) +
123 align(sizeof(shader->info), 4) +
124 4 + align(shader->binary.code_size, 4) +
125 4 + align(shader->binary.rodata_size, 4) +
126 4 + align(relocs_size, 4) +
127 4 + align(disasm_size, 4) +
128 4 + align(llvm_ir_size, 4);
129 void *buffer = CALLOC(1, size);
130 uint32_t *ptr = (uint32_t*)buffer;
131
132 if (!buffer)
133 return NULL;
134
135 *ptr++ = size;
136 ptr++; /* CRC32 is calculated at the end. */
137
138 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
139 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
140 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
141 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
142 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
143 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
144 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
145 assert((char *)ptr - (char *)buffer == size);
146
147 /* Compute CRC32. */
148 ptr = (uint32_t*)buffer;
149 ptr++;
150 *ptr = util_hash_crc32(ptr + 1, size - 8);
151
152 return buffer;
153 }
154
155 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
156 {
157 uint32_t *ptr = (uint32_t*)binary;
158 uint32_t size = *ptr++;
159 uint32_t crc32 = *ptr++;
160 unsigned chunk_size;
161
162 if (util_hash_crc32(ptr, size - 8) != crc32) {
163 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
164 return false;
165 }
166
167 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
168 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
169 ptr = read_chunk(ptr, (void**)&shader->binary.code,
170 &shader->binary.code_size);
171 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
172 &shader->binary.rodata_size);
173 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
174 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
175 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
176 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
177
178 return true;
179 }
180
181 /**
182 * Insert a shader into the cache. It's assumed the shader is not in the cache.
183 * Use si_shader_cache_load_shader before calling this.
184 *
185 * Returns false on failure, in which case the tgsi_binary should be freed.
186 */
187 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
188 void *tgsi_binary,
189 struct si_shader *shader,
190 bool insert_into_disk_cache)
191 {
192 void *hw_binary;
193 struct hash_entry *entry;
194 uint8_t key[CACHE_KEY_SIZE];
195
196 entry = _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
197 if (entry)
198 return false; /* already added */
199
200 hw_binary = si_get_shader_binary(shader);
201 if (!hw_binary)
202 return false;
203
204 if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
205 hw_binary) == NULL) {
206 FREE(hw_binary);
207 return false;
208 }
209
210 if (sscreen->b.disk_shader_cache && insert_into_disk_cache) {
211 disk_cache_compute_key(sscreen->b.disk_shader_cache, tgsi_binary,
212 *((uint32_t *)tgsi_binary), key);
213 disk_cache_put(sscreen->b.disk_shader_cache, key, hw_binary,
214 *((uint32_t *) hw_binary));
215 }
216
217 return true;
218 }
219
220 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
221 void *tgsi_binary,
222 struct si_shader *shader)
223 {
224 struct hash_entry *entry =
225 _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
226 if (!entry) {
227 if (sscreen->b.disk_shader_cache) {
228 unsigned char sha1[CACHE_KEY_SIZE];
229 size_t tg_size = *((uint32_t *) tgsi_binary);
230
231 disk_cache_compute_key(sscreen->b.disk_shader_cache,
232 tgsi_binary, tg_size, sha1);
233
234 size_t binary_size;
235 uint8_t *buffer =
236 disk_cache_get(sscreen->b.disk_shader_cache,
237 sha1, &binary_size);
238 if (!buffer)
239 return false;
240
241 if (binary_size < sizeof(uint32_t) ||
242 *((uint32_t*)buffer) != binary_size) {
243 /* Something has gone wrong discard the item
244 * from the cache and rebuild/link from
245 * source.
246 */
247 assert(!"Invalid radeonsi shader disk cache "
248 "item!");
249
250 disk_cache_remove(sscreen->b.disk_shader_cache,
251 sha1);
252 free(buffer);
253
254 return false;
255 }
256
257 if (!si_load_shader_binary(shader, buffer)) {
258 free(buffer);
259 return false;
260 }
261 free(buffer);
262
263 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary,
264 shader, false))
265 FREE(tgsi_binary);
266 } else {
267 return false;
268 }
269 } else {
270 if (si_load_shader_binary(shader, entry->data))
271 FREE(tgsi_binary);
272 else
273 return false;
274 }
275 p_atomic_inc(&sscreen->b.num_shader_cache_hits);
276 return true;
277 }
278
279 static uint32_t si_shader_cache_key_hash(const void *key)
280 {
281 /* The first dword is the key size. */
282 return util_hash_crc32(key, *(uint32_t*)key);
283 }
284
285 static bool si_shader_cache_key_equals(const void *a, const void *b)
286 {
287 uint32_t *keya = (uint32_t*)a;
288 uint32_t *keyb = (uint32_t*)b;
289
290 /* The first dword is the key size. */
291 if (*keya != *keyb)
292 return false;
293
294 return memcmp(keya, keyb, *keya) == 0;
295 }
296
297 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
298 {
299 FREE((void*)entry->key);
300 FREE(entry->data);
301 }
302
303 bool si_init_shader_cache(struct si_screen *sscreen)
304 {
305 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
306 sscreen->shader_cache =
307 _mesa_hash_table_create(NULL,
308 si_shader_cache_key_hash,
309 si_shader_cache_key_equals);
310
311 return sscreen->shader_cache != NULL;
312 }
313
314 void si_destroy_shader_cache(struct si_screen *sscreen)
315 {
316 if (sscreen->shader_cache)
317 _mesa_hash_table_destroy(sscreen->shader_cache,
318 si_destroy_shader_cache_entry);
319 mtx_destroy(&sscreen->shader_cache_mutex);
320 }
321
322 /* SHADER STATES */
323
324 static void si_set_tesseval_regs(struct si_screen *sscreen,
325 struct si_shader *shader,
326 struct si_pm4_state *pm4)
327 {
328 struct tgsi_shader_info *info = &shader->selector->info;
329 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
330 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
331 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
332 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
333 unsigned type, partitioning, topology, distribution_mode;
334
335 switch (tes_prim_mode) {
336 case PIPE_PRIM_LINES:
337 type = V_028B6C_TESS_ISOLINE;
338 break;
339 case PIPE_PRIM_TRIANGLES:
340 type = V_028B6C_TESS_TRIANGLE;
341 break;
342 case PIPE_PRIM_QUADS:
343 type = V_028B6C_TESS_QUAD;
344 break;
345 default:
346 assert(0);
347 return;
348 }
349
350 switch (tes_spacing) {
351 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
352 partitioning = V_028B6C_PART_FRAC_ODD;
353 break;
354 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
355 partitioning = V_028B6C_PART_FRAC_EVEN;
356 break;
357 case PIPE_TESS_SPACING_EQUAL:
358 partitioning = V_028B6C_PART_INTEGER;
359 break;
360 default:
361 assert(0);
362 return;
363 }
364
365 if (tes_point_mode)
366 topology = V_028B6C_OUTPUT_POINT;
367 else if (tes_prim_mode == PIPE_PRIM_LINES)
368 topology = V_028B6C_OUTPUT_LINE;
369 else if (tes_vertex_order_cw)
370 /* for some reason, this must be the other way around */
371 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
372 else
373 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
374
375 if (sscreen->has_distributed_tess) {
376 if (sscreen->b.family == CHIP_FIJI ||
377 sscreen->b.family >= CHIP_POLARIS10)
378 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
379 else
380 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
381 } else
382 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
383
384 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
385 S_028B6C_TYPE(type) |
386 S_028B6C_PARTITIONING(partitioning) |
387 S_028B6C_TOPOLOGY(topology) |
388 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
389 }
390
391 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
392 * whether the "fractional odd" tessellation spacing is used.
393 *
394 * Possible VGT configurations and which state should set the register:
395 *
396 * Reg set in | VGT shader configuration | Value
397 * ------------------------------------------------------
398 * VS as VS | VS | 30
399 * VS as ES | ES -> GS -> VS | 30
400 * TES as VS | LS -> HS -> VS | 14 or 30
401 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
402 */
403 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
404 struct si_shader *shader,
405 struct si_pm4_state *pm4)
406 {
407 unsigned type = shader->selector->type;
408
409 if (sscreen->b.family < CHIP_POLARIS10)
410 return;
411
412 /* VS as VS, or VS as ES: */
413 if ((type == PIPE_SHADER_VERTEX &&
414 !shader->key.as_ls &&
415 !shader->is_gs_copy_shader) ||
416 /* TES as VS, or TES as ES: */
417 type == PIPE_SHADER_TESS_EVAL) {
418 unsigned vtx_reuse_depth = 30;
419
420 if (type == PIPE_SHADER_TESS_EVAL &&
421 shader->selector->info.properties[TGSI_PROPERTY_TES_SPACING] ==
422 PIPE_TESS_SPACING_FRACTIONAL_ODD)
423 vtx_reuse_depth = 14;
424
425 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
426 vtx_reuse_depth);
427 }
428 }
429
430 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
431 {
432 if (shader->pm4)
433 si_pm4_clear_state(shader->pm4);
434 else
435 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
436
437 return shader->pm4;
438 }
439
440 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
441 {
442 struct si_pm4_state *pm4;
443 unsigned vgpr_comp_cnt;
444 uint64_t va;
445
446 assert(sscreen->b.chip_class <= VI);
447
448 pm4 = si_get_shader_pm4_state(shader);
449 if (!pm4)
450 return;
451
452 va = shader->bo->gpu_address;
453 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
454
455 /* We need at least 2 components for LS.
456 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
457 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 1;
458
459 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
460 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
461
462 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
463 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
464 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
465 S_00B528_DX10_CLAMP(1) |
466 S_00B528_FLOAT_MODE(shader->config.float_mode);
467 shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_LS_NUM_USER_SGPR) |
468 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
469 }
470
471 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
472 {
473 struct si_pm4_state *pm4;
474 uint64_t va;
475
476 pm4 = si_get_shader_pm4_state(shader);
477 if (!pm4)
478 return;
479
480 va = shader->bo->gpu_address;
481 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
482
483 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
484 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
485 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
486 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
487 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
488 S_00B428_DX10_CLAMP(1) |
489 S_00B428_FLOAT_MODE(shader->config.float_mode));
490 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
491 S_00B42C_USER_SGPR(SI_TCS_NUM_USER_SGPR) |
492 S_00B42C_OC_LDS_EN(sscreen->b.chip_class <= VI) |
493 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
494 }
495
496 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
497 {
498 struct si_pm4_state *pm4;
499 unsigned num_user_sgprs;
500 unsigned vgpr_comp_cnt;
501 uint64_t va;
502 unsigned oc_lds_en;
503
504 assert(sscreen->b.chip_class <= VI);
505
506 pm4 = si_get_shader_pm4_state(shader);
507 if (!pm4)
508 return;
509
510 va = shader->bo->gpu_address;
511 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
512
513 if (shader->selector->type == PIPE_SHADER_VERTEX) {
514 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
515 num_user_sgprs = SI_ES_NUM_USER_SGPR;
516 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
517 vgpr_comp_cnt = 3; /* all components are needed for TES */
518 num_user_sgprs = SI_TES_NUM_USER_SGPR;
519 } else
520 unreachable("invalid shader selector type");
521
522 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
523
524 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
525 shader->selector->esgs_itemsize / 4);
526 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
527 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
528 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
529 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
530 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
531 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
532 S_00B328_DX10_CLAMP(1) |
533 S_00B328_FLOAT_MODE(shader->config.float_mode));
534 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
535 S_00B32C_USER_SGPR(num_user_sgprs) |
536 S_00B32C_OC_LDS_EN(oc_lds_en) |
537 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
538
539 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
540 si_set_tesseval_regs(sscreen, shader, pm4);
541
542 polaris_set_vgt_vertex_reuse(sscreen, shader, pm4);
543 }
544
545 /**
546 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
547 * geometry shader.
548 */
549 static uint32_t si_vgt_gs_mode(struct si_shader_selector *sel)
550 {
551 unsigned gs_max_vert_out = sel->gs_max_out_vertices;
552 unsigned cut_mode;
553
554 if (gs_max_vert_out <= 128) {
555 cut_mode = V_028A40_GS_CUT_128;
556 } else if (gs_max_vert_out <= 256) {
557 cut_mode = V_028A40_GS_CUT_256;
558 } else if (gs_max_vert_out <= 512) {
559 cut_mode = V_028A40_GS_CUT_512;
560 } else {
561 assert(gs_max_vert_out <= 1024);
562 cut_mode = V_028A40_GS_CUT_1024;
563 }
564
565 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
566 S_028A40_CUT_MODE(cut_mode)|
567 S_028A40_ES_WRITE_OPTIMIZE(1) |
568 S_028A40_GS_WRITE_OPTIMIZE(1);
569 }
570
571 static void si_shader_gs(struct si_shader *shader)
572 {
573 struct si_shader_selector *sel = shader->selector;
574 const ubyte *num_components = sel->info.num_stream_output_components;
575 unsigned gs_num_invocations = sel->gs_num_invocations;
576 struct si_pm4_state *pm4;
577 uint64_t va;
578 unsigned max_stream = sel->max_gs_stream;
579 unsigned offset;
580
581 pm4 = si_get_shader_pm4_state(shader);
582 if (!pm4)
583 return;
584
585 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(shader->selector));
586
587 offset = num_components[0] * sel->gs_max_out_vertices;
588 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, offset);
589 if (max_stream >= 1)
590 offset += num_components[1] * sel->gs_max_out_vertices;
591 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, offset);
592 if (max_stream >= 2)
593 offset += num_components[2] * sel->gs_max_out_vertices;
594 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, offset);
595 if (max_stream >= 3)
596 offset += num_components[3] * sel->gs_max_out_vertices;
597 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
598
599 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
600 assert(offset < (1 << 15));
601
602 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, shader->selector->gs_max_out_vertices);
603
604 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, num_components[0]);
605 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? num_components[1] : 0);
606 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? num_components[2] : 0);
607 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? num_components[3] : 0);
608
609 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
610 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
611 S_028B90_ENABLE(gs_num_invocations > 0));
612
613 va = shader->bo->gpu_address;
614 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
615 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
616 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
617
618 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
619 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
620 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
621 S_00B228_DX10_CLAMP(1) |
622 S_00B228_FLOAT_MODE(shader->config.float_mode));
623 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
624 S_00B22C_USER_SGPR(SI_GS_NUM_USER_SGPR) |
625 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
626 }
627
628 /**
629 * Compute the state for \p shader, which will run as a vertex shader on the
630 * hardware.
631 *
632 * If \p gs is non-NULL, it points to the geometry shader for which this shader
633 * is the copy shader.
634 */
635 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
636 struct si_shader_selector *gs)
637 {
638 struct si_pm4_state *pm4;
639 unsigned num_user_sgprs;
640 unsigned nparams, vgpr_comp_cnt;
641 uint64_t va;
642 unsigned oc_lds_en;
643 unsigned window_space =
644 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
645 bool enable_prim_id = si_vs_exports_prim_id(shader);
646
647 pm4 = si_get_shader_pm4_state(shader);
648 if (!pm4)
649 return;
650
651 /* We always write VGT_GS_MODE in the VS state, because every switch
652 * between different shader pipelines involving a different GS or no
653 * GS at all involves a switch of the VS (different GS use different
654 * copy shaders). On the other hand, when the API switches from a GS to
655 * no GS and then back to the same GS used originally, the GS state is
656 * not sent again.
657 */
658 if (!gs) {
659 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
660 S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
661 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
662 } else {
663 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
664 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
665 }
666
667 va = shader->bo->gpu_address;
668 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
669
670 if (gs) {
671 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
672 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
673 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
674 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
675 num_user_sgprs = SI_VS_NUM_USER_SGPR;
676 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
677 vgpr_comp_cnt = 3; /* all components are needed for TES */
678 num_user_sgprs = SI_TES_NUM_USER_SGPR;
679 } else
680 unreachable("invalid shader selector type");
681
682 /* VS is required to export at least one param. */
683 nparams = MAX2(shader->info.nr_param_exports, 1);
684 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
685 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
686
687 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
688 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
689 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
690 V_02870C_SPI_SHADER_4COMP :
691 V_02870C_SPI_SHADER_NONE) |
692 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
693 V_02870C_SPI_SHADER_4COMP :
694 V_02870C_SPI_SHADER_NONE) |
695 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
696 V_02870C_SPI_SHADER_4COMP :
697 V_02870C_SPI_SHADER_NONE));
698
699 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
700
701 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
702 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
703 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
704 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
705 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
706 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
707 S_00B128_DX10_CLAMP(1) |
708 S_00B128_FLOAT_MODE(shader->config.float_mode));
709 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
710 S_00B12C_USER_SGPR(num_user_sgprs) |
711 S_00B12C_OC_LDS_EN(oc_lds_en) |
712 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
713 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
714 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
715 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
716 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
717 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
718 if (window_space)
719 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
720 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
721 else
722 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
723 S_028818_VTX_W0_FMT(1) |
724 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
725 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
726 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
727
728 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
729 si_set_tesseval_regs(sscreen, shader, pm4);
730
731 polaris_set_vgt_vertex_reuse(sscreen, shader, pm4);
732 }
733
734 static unsigned si_get_ps_num_interp(struct si_shader *ps)
735 {
736 struct tgsi_shader_info *info = &ps->selector->info;
737 unsigned num_colors = !!(info->colors_read & 0x0f) +
738 !!(info->colors_read & 0xf0);
739 unsigned num_interp = ps->selector->info.num_inputs +
740 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
741
742 assert(num_interp <= 32);
743 return MIN2(num_interp, 32);
744 }
745
746 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
747 {
748 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
749 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
750
751 /* If the i-th target format is set, all previous target formats must
752 * be non-zero to avoid hangs.
753 */
754 for (i = 0; i < num_targets; i++)
755 if (!(value & (0xf << (i * 4))))
756 value |= V_028714_SPI_SHADER_32_R << (i * 4);
757
758 return value;
759 }
760
761 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
762 {
763 unsigned i, cb_shader_mask = 0;
764
765 for (i = 0; i < 8; i++) {
766 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
767 case V_028714_SPI_SHADER_ZERO:
768 break;
769 case V_028714_SPI_SHADER_32_R:
770 cb_shader_mask |= 0x1 << (i * 4);
771 break;
772 case V_028714_SPI_SHADER_32_GR:
773 cb_shader_mask |= 0x3 << (i * 4);
774 break;
775 case V_028714_SPI_SHADER_32_AR:
776 cb_shader_mask |= 0x9 << (i * 4);
777 break;
778 case V_028714_SPI_SHADER_FP16_ABGR:
779 case V_028714_SPI_SHADER_UNORM16_ABGR:
780 case V_028714_SPI_SHADER_SNORM16_ABGR:
781 case V_028714_SPI_SHADER_UINT16_ABGR:
782 case V_028714_SPI_SHADER_SINT16_ABGR:
783 case V_028714_SPI_SHADER_32_ABGR:
784 cb_shader_mask |= 0xf << (i * 4);
785 break;
786 default:
787 assert(0);
788 }
789 }
790 return cb_shader_mask;
791 }
792
793 static void si_shader_ps(struct si_shader *shader)
794 {
795 struct tgsi_shader_info *info = &shader->selector->info;
796 struct si_pm4_state *pm4;
797 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
798 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
799 uint64_t va;
800 unsigned input_ena = shader->config.spi_ps_input_ena;
801
802 /* we need to enable at least one of them, otherwise we hang the GPU */
803 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
804 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
805 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
806 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
807 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
808 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
809 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
810 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
811 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
812 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
813 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
814 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
815 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
816 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
817
818 /* Validate interpolation optimization flags (read as implications). */
819 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
820 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
821 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
822 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
823 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
824 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
825 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
826 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
827 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
828 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
829 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
830 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
831 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
832 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
833 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
834 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
835 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
836 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
837
838 /* Validate cases when the optimizations are off (read as implications). */
839 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
840 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
841 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
842 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
843 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
844 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
845
846 pm4 = si_get_shader_pm4_state(shader);
847 if (!pm4)
848 return;
849
850 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
851 * Possible vaules:
852 * 0 -> Position = pixel center
853 * 1 -> Position = pixel centroid
854 * 2 -> Position = at sample position
855 *
856 * From GLSL 4.5 specification, section 7.1:
857 * "The variable gl_FragCoord is available as an input variable from
858 * within fragment shaders and it holds the window relative coordinates
859 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
860 * value can be for any location within the pixel, or one of the
861 * fragment samples. The use of centroid does not further restrict
862 * this value to be inside the current primitive."
863 *
864 * Meaning that centroid has no effect and we can return anything within
865 * the pixel. Thus, return the value at sample position, because that's
866 * the most accurate one shaders can get.
867 */
868 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
869
870 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
871 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
872 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
873
874 spi_shader_col_format = si_get_spi_shader_col_format(shader);
875 cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
876
877 /* Ensure that some export memory is always allocated, for two reasons:
878 *
879 * 1) Correctness: The hardware ignores the EXEC mask if no export
880 * memory is allocated, so KILL and alpha test do not work correctly
881 * without this.
882 * 2) Performance: Every shader needs at least a NULL export, even when
883 * it writes no color/depth output. The NULL export instruction
884 * stalls without this setting.
885 *
886 * Don't add this to CB_SHADER_MASK.
887 */
888 if (!spi_shader_col_format &&
889 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
890 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
891
892 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
893 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
894 shader->config.spi_ps_input_addr);
895
896 /* Set interpolation controls. */
897 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
898
899 /* Set registers. */
900 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
901 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
902
903 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
904 si_get_spi_shader_z_format(info->writes_z,
905 info->writes_stencil,
906 info->writes_samplemask));
907
908 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
909 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
910
911 va = shader->bo->gpu_address;
912 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
913 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
914 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
915
916 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
917 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
918 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
919 S_00B028_DX10_CLAMP(1) |
920 S_00B028_FLOAT_MODE(shader->config.float_mode));
921 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
922 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
923 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
924 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
925 }
926
927 static void si_shader_init_pm4_state(struct si_screen *sscreen,
928 struct si_shader *shader)
929 {
930 switch (shader->selector->type) {
931 case PIPE_SHADER_VERTEX:
932 if (shader->key.as_ls)
933 si_shader_ls(sscreen, shader);
934 else if (shader->key.as_es)
935 si_shader_es(sscreen, shader);
936 else
937 si_shader_vs(sscreen, shader, NULL);
938 break;
939 case PIPE_SHADER_TESS_CTRL:
940 si_shader_hs(sscreen, shader);
941 break;
942 case PIPE_SHADER_TESS_EVAL:
943 if (shader->key.as_es)
944 si_shader_es(sscreen, shader);
945 else
946 si_shader_vs(sscreen, shader, NULL);
947 break;
948 case PIPE_SHADER_GEOMETRY:
949 si_shader_gs(shader);
950 break;
951 case PIPE_SHADER_FRAGMENT:
952 si_shader_ps(shader);
953 break;
954 default:
955 assert(0);
956 }
957 }
958
959 static unsigned si_get_alpha_test_func(struct si_context *sctx)
960 {
961 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
962 if (sctx->queued.named.dsa)
963 return sctx->queued.named.dsa->alpha_func;
964
965 return PIPE_FUNC_ALWAYS;
966 }
967
968 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
969 struct si_shader_selector *vs,
970 struct si_shader_key *key)
971 {
972 struct si_shader_selector *ps = sctx->ps_shader.cso;
973
974 key->opt.hw_vs.clip_disable =
975 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
976 (vs->info.clipdist_writemask ||
977 vs->info.writes_clipvertex) &&
978 !vs->info.culldist_writemask;
979
980 /* Find out if PS is disabled. */
981 bool ps_disabled = true;
982 if (ps) {
983 bool ps_modifies_zs = ps->info.uses_kill ||
984 ps->info.writes_z ||
985 ps->info.writes_stencil ||
986 ps->info.writes_samplemask ||
987 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
988
989 unsigned ps_colormask = sctx->framebuffer.colorbuf_enabled_4bit &
990 sctx->queued.named.blend->cb_target_mask;
991 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
992 ps_colormask &= ps->colors_written_4bit;
993
994 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
995 (!ps_colormask &&
996 !ps_modifies_zs &&
997 !ps->info.writes_memory);
998 }
999
1000 /* Find out which VS outputs aren't used by the PS. */
1001 uint64_t outputs_written = vs->outputs_written;
1002 uint32_t outputs_written2 = vs->outputs_written2;
1003 uint64_t inputs_read = 0;
1004 uint32_t inputs_read2 = 0;
1005
1006 outputs_written &= ~0x3; /* ignore POSITION, PSIZE */
1007
1008 if (!ps_disabled) {
1009 inputs_read = ps->inputs_read;
1010 inputs_read2 = ps->inputs_read2;
1011 }
1012
1013 uint64_t linked = outputs_written & inputs_read;
1014 uint32_t linked2 = outputs_written2 & inputs_read2;
1015
1016 key->opt.hw_vs.kill_outputs = ~linked & outputs_written;
1017 key->opt.hw_vs.kill_outputs2 = ~linked2 & outputs_written2;
1018 }
1019
1020 /* Compute the key for the hw shader variant */
1021 static inline void si_shader_selector_key(struct pipe_context *ctx,
1022 struct si_shader_selector *sel,
1023 struct si_shader_key *key)
1024 {
1025 struct si_context *sctx = (struct si_context *)ctx;
1026 unsigned i;
1027
1028 memset(key, 0, sizeof(*key));
1029
1030 switch (sel->type) {
1031 case PIPE_SHADER_VERTEX:
1032 if (sctx->vertex_elements) {
1033 unsigned count = MIN2(sel->info.num_inputs,
1034 sctx->vertex_elements->count);
1035 for (i = 0; i < count; ++i)
1036 key->part.vs.prolog.instance_divisors[i] =
1037 sctx->vertex_elements->elements[i].instance_divisor;
1038
1039 memcpy(key->mono.vs.fix_fetch,
1040 sctx->vertex_elements->fix_fetch, count);
1041 }
1042 if (sctx->tes_shader.cso)
1043 key->as_ls = 1;
1044 else if (sctx->gs_shader.cso)
1045 key->as_es = 1;
1046 else {
1047 si_shader_selector_key_hw_vs(sctx, sel, key);
1048
1049 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1050 key->part.vs.epilog.export_prim_id = 1;
1051 }
1052 break;
1053 case PIPE_SHADER_TESS_CTRL:
1054 key->part.tcs.epilog.prim_mode =
1055 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1056 key->part.tcs.epilog.tes_reads_tess_factors =
1057 sctx->tes_shader.cso->info.reads_tess_factors;
1058
1059 if (sel == sctx->fixed_func_tcs_shader.cso)
1060 key->mono.tcs.inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1061 break;
1062 case PIPE_SHADER_TESS_EVAL:
1063 if (sctx->gs_shader.cso)
1064 key->as_es = 1;
1065 else {
1066 si_shader_selector_key_hw_vs(sctx, sel, key);
1067
1068 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1069 key->part.tes.epilog.export_prim_id = 1;
1070 }
1071 break;
1072 case PIPE_SHADER_GEOMETRY:
1073 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1074 break;
1075 case PIPE_SHADER_FRAGMENT: {
1076 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1077 struct si_state_blend *blend = sctx->queued.named.blend;
1078
1079 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1080 sel->info.colors_written == 0x1)
1081 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1082
1083 if (blend) {
1084 /* Select the shader color format based on whether
1085 * blending or alpha are needed.
1086 */
1087 key->part.ps.epilog.spi_shader_col_format =
1088 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1089 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1090 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1091 sctx->framebuffer.spi_shader_col_format_blend) |
1092 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1093 sctx->framebuffer.spi_shader_col_format_alpha) |
1094 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1095 sctx->framebuffer.spi_shader_col_format);
1096
1097 /* The output for dual source blending should have
1098 * the same format as the first output.
1099 */
1100 if (blend->dual_src_blend)
1101 key->part.ps.epilog.spi_shader_col_format |=
1102 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1103 } else
1104 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1105
1106 /* If alpha-to-coverage is enabled, we have to export alpha
1107 * even if there is no color buffer.
1108 */
1109 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1110 blend && blend->alpha_to_coverage)
1111 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1112
1113 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1114 * to the range supported by the type if a channel has less
1115 * than 16 bits and the export format is 16_ABGR.
1116 */
1117 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII) {
1118 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1119 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1120 }
1121
1122 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1123 if (!key->part.ps.epilog.last_cbuf) {
1124 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1125 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1126 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1127 }
1128
1129 if (rs) {
1130 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
1131 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
1132 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
1133 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
1134
1135 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1136 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1137
1138 if (sctx->queued.named.blend) {
1139 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1140 rs->multisample_enable;
1141 }
1142
1143 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1144 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1145 (is_line && rs->line_smooth)) &&
1146 sctx->framebuffer.nr_samples <= 1;
1147 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1148
1149 if (rs->force_persample_interp &&
1150 rs->multisample_enable &&
1151 sctx->framebuffer.nr_samples > 1 &&
1152 sctx->ps_iter_samples > 1) {
1153 key->part.ps.prolog.force_persp_sample_interp =
1154 sel->info.uses_persp_center ||
1155 sel->info.uses_persp_centroid;
1156
1157 key->part.ps.prolog.force_linear_sample_interp =
1158 sel->info.uses_linear_center ||
1159 sel->info.uses_linear_centroid;
1160 } else if (rs->multisample_enable &&
1161 sctx->framebuffer.nr_samples > 1) {
1162 key->part.ps.prolog.bc_optimize_for_persp =
1163 sel->info.uses_persp_center &&
1164 sel->info.uses_persp_centroid;
1165 key->part.ps.prolog.bc_optimize_for_linear =
1166 sel->info.uses_linear_center &&
1167 sel->info.uses_linear_centroid;
1168 } else {
1169 /* Make sure SPI doesn't compute more than 1 pair
1170 * of (i,j), which is the optimization here. */
1171 key->part.ps.prolog.force_persp_center_interp =
1172 sel->info.uses_persp_center +
1173 sel->info.uses_persp_centroid +
1174 sel->info.uses_persp_sample > 1;
1175
1176 key->part.ps.prolog.force_linear_center_interp =
1177 sel->info.uses_linear_center +
1178 sel->info.uses_linear_centroid +
1179 sel->info.uses_linear_sample > 1;
1180 }
1181 }
1182
1183 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1184 break;
1185 }
1186 default:
1187 assert(0);
1188 }
1189 }
1190
1191 static void si_build_shader_variant(void *job, int thread_index)
1192 {
1193 struct si_shader *shader = (struct si_shader *)job;
1194 struct si_shader_selector *sel = shader->selector;
1195 struct si_screen *sscreen = sel->screen;
1196 LLVMTargetMachineRef tm;
1197 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1198 int r;
1199
1200 if (thread_index >= 0) {
1201 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1202 tm = sscreen->tm[thread_index];
1203 if (!debug->async)
1204 debug = NULL;
1205 } else {
1206 tm = shader->compiler_ctx_state.tm;
1207 }
1208
1209 r = si_shader_create(sscreen, tm, shader, debug);
1210 if (unlikely(r)) {
1211 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1212 sel->type, r);
1213 shader->compilation_failed = true;
1214 return;
1215 }
1216
1217 if (shader->compiler_ctx_state.is_debug_context) {
1218 FILE *f = open_memstream(&shader->shader_log,
1219 &shader->shader_log_size);
1220 if (f) {
1221 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1222 fclose(f);
1223 }
1224 }
1225
1226 si_shader_init_pm4_state(sscreen, shader);
1227 }
1228
1229 /* Select the hw shader variant depending on the current state. */
1230 static int si_shader_select_with_key(struct si_screen *sscreen,
1231 struct si_shader_ctx_state *state,
1232 struct si_compiler_ctx_state *compiler_state,
1233 struct si_shader_key *key,
1234 int thread_index)
1235 {
1236 static const struct si_shader_key zeroed;
1237 struct si_shader_selector *sel = state->cso;
1238 struct si_shader *current = state->current;
1239 struct si_shader *iter, *shader = NULL;
1240
1241 if (unlikely(sscreen->b.debug_flags & DBG_NO_OPT_VARIANT)) {
1242 memset(&key->opt, 0, sizeof(key->opt));
1243 }
1244
1245 again:
1246 /* Check if we don't need to change anything.
1247 * This path is also used for most shaders that don't need multiple
1248 * variants, it will cost just a computation of the key and this
1249 * test. */
1250 if (likely(current &&
1251 memcmp(&current->key, key, sizeof(*key)) == 0 &&
1252 (!current->is_optimized ||
1253 util_queue_fence_is_signalled(&current->optimized_ready))))
1254 return current->compilation_failed ? -1 : 0;
1255
1256 /* This must be done before the mutex is locked, because async GS
1257 * compilation calls this function too, and therefore must enter
1258 * the mutex first.
1259 *
1260 * Only wait if we are in a draw call. Don't wait if we are
1261 * in a compiler thread.
1262 */
1263 if (thread_index < 0)
1264 util_queue_fence_wait(&sel->ready);
1265
1266 mtx_lock(&sel->mutex);
1267
1268 /* Find the shader variant. */
1269 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1270 /* Don't check the "current" shader. We checked it above. */
1271 if (current != iter &&
1272 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1273 /* If it's an optimized shader and its compilation has
1274 * been started but isn't done, use the unoptimized
1275 * shader so as not to cause a stall due to compilation.
1276 */
1277 if (iter->is_optimized &&
1278 !util_queue_fence_is_signalled(&iter->optimized_ready)) {
1279 memset(&key->opt, 0, sizeof(key->opt));
1280 mtx_unlock(&sel->mutex);
1281 goto again;
1282 }
1283
1284 if (iter->compilation_failed) {
1285 mtx_unlock(&sel->mutex);
1286 return -1; /* skip the draw call */
1287 }
1288
1289 state->current = iter;
1290 mtx_unlock(&sel->mutex);
1291 return 0;
1292 }
1293 }
1294
1295 /* Build a new shader. */
1296 shader = CALLOC_STRUCT(si_shader);
1297 if (!shader) {
1298 mtx_unlock(&sel->mutex);
1299 return -ENOMEM;
1300 }
1301 shader->selector = sel;
1302 shader->key = *key;
1303 shader->compiler_ctx_state = *compiler_state;
1304
1305 /* Compile the main shader part if it doesn't exist. This can happen
1306 * if the initial guess was wrong. */
1307 struct si_shader **mainp = si_get_main_shader_part(sel, key);
1308 bool is_pure_monolithic =
1309 sscreen->use_monolithic_shaders ||
1310 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1311
1312 if (!*mainp && !is_pure_monolithic) {
1313 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1314
1315 if (!main_part) {
1316 FREE(shader);
1317 mtx_unlock(&sel->mutex);
1318 return -ENOMEM; /* skip the draw call */
1319 }
1320
1321 main_part->selector = sel;
1322 main_part->key.as_es = key->as_es;
1323 main_part->key.as_ls = key->as_ls;
1324
1325 if (si_compile_tgsi_shader(sscreen, compiler_state->tm,
1326 main_part, false,
1327 &compiler_state->debug) != 0) {
1328 FREE(main_part);
1329 FREE(shader);
1330 mtx_unlock(&sel->mutex);
1331 return -ENOMEM; /* skip the draw call */
1332 }
1333 *mainp = main_part;
1334 }
1335
1336 /* Monolithic-only shaders don't make a distinction between optimized
1337 * and unoptimized. */
1338 shader->is_monolithic =
1339 is_pure_monolithic ||
1340 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1341
1342 shader->is_optimized =
1343 !is_pure_monolithic &&
1344 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1345 if (shader->is_optimized)
1346 util_queue_fence_init(&shader->optimized_ready);
1347
1348 if (!sel->last_variant) {
1349 sel->first_variant = shader;
1350 sel->last_variant = shader;
1351 } else {
1352 sel->last_variant->next_variant = shader;
1353 sel->last_variant = shader;
1354 }
1355
1356 /* If it's an optimized shader, compile it asynchronously. */
1357 if (shader->is_optimized &&
1358 !is_pure_monolithic &&
1359 thread_index < 0) {
1360 /* Compile it asynchronously. */
1361 util_queue_add_job(&sscreen->shader_compiler_queue,
1362 shader, &shader->optimized_ready,
1363 si_build_shader_variant, NULL);
1364
1365 /* Use the default (unoptimized) shader for now. */
1366 memset(&key->opt, 0, sizeof(key->opt));
1367 mtx_unlock(&sel->mutex);
1368 goto again;
1369 }
1370
1371 assert(!shader->is_optimized);
1372 si_build_shader_variant(shader, thread_index);
1373
1374 if (!shader->compilation_failed)
1375 state->current = shader;
1376
1377 mtx_unlock(&sel->mutex);
1378 return shader->compilation_failed ? -1 : 0;
1379 }
1380
1381 static int si_shader_select(struct pipe_context *ctx,
1382 struct si_shader_ctx_state *state,
1383 struct si_compiler_ctx_state *compiler_state)
1384 {
1385 struct si_context *sctx = (struct si_context *)ctx;
1386 struct si_shader_key key;
1387
1388 si_shader_selector_key(ctx, state->cso, &key);
1389 return si_shader_select_with_key(sctx->screen, state, compiler_state,
1390 &key, -1);
1391 }
1392
1393 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1394 struct si_shader_key *key)
1395 {
1396 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1397
1398 switch (info->processor) {
1399 case PIPE_SHADER_VERTEX:
1400 switch (next_shader) {
1401 case PIPE_SHADER_GEOMETRY:
1402 key->as_es = 1;
1403 break;
1404 case PIPE_SHADER_TESS_CTRL:
1405 case PIPE_SHADER_TESS_EVAL:
1406 key->as_ls = 1;
1407 break;
1408 default:
1409 /* If POSITION isn't written, it can't be a HW VS.
1410 * Assume that it's a HW LS. (the next shader is TCS)
1411 * This heuristic is needed for separate shader objects.
1412 */
1413 if (!info->writes_position)
1414 key->as_ls = 1;
1415 }
1416 break;
1417
1418 case PIPE_SHADER_TESS_EVAL:
1419 if (next_shader == PIPE_SHADER_GEOMETRY ||
1420 !info->writes_position)
1421 key->as_es = 1;
1422 break;
1423 }
1424 }
1425
1426 /**
1427 * Compile the main shader part or the monolithic shader as part of
1428 * si_shader_selector initialization. Since it can be done asynchronously,
1429 * there is no way to report compile failures to applications.
1430 */
1431 void si_init_shader_selector_async(void *job, int thread_index)
1432 {
1433 struct si_shader_selector *sel = (struct si_shader_selector *)job;
1434 struct si_screen *sscreen = sel->screen;
1435 LLVMTargetMachineRef tm;
1436 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
1437 unsigned i;
1438
1439 if (thread_index >= 0) {
1440 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1441 tm = sscreen->tm[thread_index];
1442 if (!debug->async)
1443 debug = NULL;
1444 } else {
1445 tm = sel->compiler_ctx_state.tm;
1446 }
1447
1448 /* Compile the main shader part for use with a prolog and/or epilog.
1449 * If this fails, the driver will try to compile a monolithic shader
1450 * on demand.
1451 */
1452 if (!sscreen->use_monolithic_shaders) {
1453 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1454 void *tgsi_binary;
1455
1456 if (!shader) {
1457 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
1458 return;
1459 }
1460
1461 shader->selector = sel;
1462 si_parse_next_shader_property(&sel->info, &shader->key);
1463
1464 tgsi_binary = si_get_tgsi_binary(sel);
1465
1466 /* Try to load the shader from the shader cache. */
1467 mtx_lock(&sscreen->shader_cache_mutex);
1468
1469 if (tgsi_binary &&
1470 si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
1471 mtx_unlock(&sscreen->shader_cache_mutex);
1472 } else {
1473 mtx_unlock(&sscreen->shader_cache_mutex);
1474
1475 /* Compile the shader if it hasn't been loaded from the cache. */
1476 if (si_compile_tgsi_shader(sscreen, tm, shader, false,
1477 debug) != 0) {
1478 FREE(shader);
1479 FREE(tgsi_binary);
1480 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
1481 return;
1482 }
1483
1484 if (tgsi_binary) {
1485 mtx_lock(&sscreen->shader_cache_mutex);
1486 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary, shader, true))
1487 FREE(tgsi_binary);
1488 mtx_unlock(&sscreen->shader_cache_mutex);
1489 }
1490 }
1491
1492 *si_get_main_shader_part(sel, &shader->key) = shader;
1493
1494 /* Unset "outputs_written" flags for outputs converted to
1495 * DEFAULT_VAL, so that later inter-shader optimizations don't
1496 * try to eliminate outputs that don't exist in the final
1497 * shader.
1498 *
1499 * This is only done if non-monolithic shaders are enabled.
1500 */
1501 if ((sel->type == PIPE_SHADER_VERTEX ||
1502 sel->type == PIPE_SHADER_TESS_EVAL) &&
1503 !shader->key.as_ls &&
1504 !shader->key.as_es) {
1505 unsigned i;
1506
1507 for (i = 0; i < sel->info.num_outputs; i++) {
1508 unsigned offset = shader->info.vs_output_param_offset[i];
1509
1510 if (offset <= EXP_PARAM_OFFSET_31)
1511 continue;
1512
1513 unsigned name = sel->info.output_semantic_name[i];
1514 unsigned index = sel->info.output_semantic_index[i];
1515 unsigned id;
1516
1517 switch (name) {
1518 case TGSI_SEMANTIC_GENERIC:
1519 /* don't process indices the function can't handle */
1520 if (index >= 60)
1521 break;
1522 /* fall through */
1523 case TGSI_SEMANTIC_CLIPDIST:
1524 id = si_shader_io_get_unique_index(name, index);
1525 sel->outputs_written &= ~(1ull << id);
1526 break;
1527 case TGSI_SEMANTIC_POSITION: /* ignore these */
1528 case TGSI_SEMANTIC_PSIZE:
1529 case TGSI_SEMANTIC_CLIPVERTEX:
1530 case TGSI_SEMANTIC_EDGEFLAG:
1531 break;
1532 default:
1533 id = si_shader_io_get_unique_index2(name, index);
1534 sel->outputs_written2 &= ~(1u << id);
1535 }
1536 }
1537 }
1538 }
1539
1540 /* Pre-compilation. */
1541 if (sscreen->b.debug_flags & DBG_PRECOMPILE) {
1542 struct si_shader_ctx_state state = {sel};
1543 struct si_shader_key key;
1544
1545 memset(&key, 0, sizeof(key));
1546 si_parse_next_shader_property(&sel->info, &key);
1547
1548 /* Set reasonable defaults, so that the shader key doesn't
1549 * cause any code to be eliminated.
1550 */
1551 switch (sel->type) {
1552 case PIPE_SHADER_TESS_CTRL:
1553 key.part.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
1554 break;
1555 case PIPE_SHADER_FRAGMENT:
1556 key.part.ps.prolog.bc_optimize_for_persp =
1557 sel->info.uses_persp_center &&
1558 sel->info.uses_persp_centroid;
1559 key.part.ps.prolog.bc_optimize_for_linear =
1560 sel->info.uses_linear_center &&
1561 sel->info.uses_linear_centroid;
1562 key.part.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
1563 for (i = 0; i < 8; i++)
1564 if (sel->info.colors_written & (1 << i))
1565 key.part.ps.epilog.spi_shader_col_format |=
1566 V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
1567 break;
1568 }
1569
1570 if (si_shader_select_with_key(sscreen, &state,
1571 &sel->compiler_ctx_state, &key,
1572 thread_index))
1573 fprintf(stderr, "radeonsi: can't create a monolithic shader\n");
1574 }
1575
1576 /* The GS copy shader is always pre-compiled. */
1577 if (sel->type == PIPE_SHADER_GEOMETRY) {
1578 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, tm, sel, debug);
1579 if (!sel->gs_copy_shader) {
1580 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
1581 return;
1582 }
1583
1584 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
1585 }
1586 }
1587
1588 static void *si_create_shader_selector(struct pipe_context *ctx,
1589 const struct pipe_shader_state *state)
1590 {
1591 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
1592 struct si_context *sctx = (struct si_context*)ctx;
1593 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
1594 int i;
1595
1596 if (!sel)
1597 return NULL;
1598
1599 sel->screen = sscreen;
1600 sel->compiler_ctx_state.tm = sctx->tm;
1601 sel->compiler_ctx_state.debug = sctx->b.debug;
1602 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
1603 sel->tokens = tgsi_dup_tokens(state->tokens);
1604 if (!sel->tokens) {
1605 FREE(sel);
1606 return NULL;
1607 }
1608
1609 sel->so = state->stream_output;
1610 tgsi_scan_shader(state->tokens, &sel->info);
1611 sel->type = sel->info.processor;
1612 p_atomic_inc(&sscreen->b.num_shaders_created);
1613
1614 /* Set which opcode uses which (i,j) pair. */
1615 if (sel->info.uses_persp_opcode_interp_centroid)
1616 sel->info.uses_persp_centroid = true;
1617
1618 if (sel->info.uses_linear_opcode_interp_centroid)
1619 sel->info.uses_linear_centroid = true;
1620
1621 if (sel->info.uses_persp_opcode_interp_offset ||
1622 sel->info.uses_persp_opcode_interp_sample)
1623 sel->info.uses_persp_center = true;
1624
1625 if (sel->info.uses_linear_opcode_interp_offset ||
1626 sel->info.uses_linear_opcode_interp_sample)
1627 sel->info.uses_linear_center = true;
1628
1629 switch (sel->type) {
1630 case PIPE_SHADER_GEOMETRY:
1631 sel->gs_output_prim =
1632 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
1633 sel->gs_max_out_vertices =
1634 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
1635 sel->gs_num_invocations =
1636 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
1637 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
1638 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
1639 sel->gs_max_out_vertices;
1640
1641 sel->max_gs_stream = 0;
1642 for (i = 0; i < sel->so.num_outputs; i++)
1643 sel->max_gs_stream = MAX2(sel->max_gs_stream,
1644 sel->so.output[i].stream);
1645
1646 sel->gs_input_verts_per_prim =
1647 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
1648 break;
1649
1650 case PIPE_SHADER_TESS_CTRL:
1651 /* Always reserve space for these. */
1652 sel->patch_outputs_written |=
1653 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0)) |
1654 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0));
1655 /* fall through */
1656 case PIPE_SHADER_VERTEX:
1657 case PIPE_SHADER_TESS_EVAL:
1658 for (i = 0; i < sel->info.num_outputs; i++) {
1659 unsigned name = sel->info.output_semantic_name[i];
1660 unsigned index = sel->info.output_semantic_index[i];
1661
1662 switch (name) {
1663 case TGSI_SEMANTIC_TESSINNER:
1664 case TGSI_SEMANTIC_TESSOUTER:
1665 case TGSI_SEMANTIC_PATCH:
1666 sel->patch_outputs_written |=
1667 1llu << si_shader_io_get_unique_index(name, index);
1668 break;
1669
1670 case TGSI_SEMANTIC_GENERIC:
1671 /* don't process indices the function can't handle */
1672 if (index >= 60)
1673 break;
1674 /* fall through */
1675 case TGSI_SEMANTIC_POSITION:
1676 case TGSI_SEMANTIC_PSIZE:
1677 case TGSI_SEMANTIC_CLIPDIST:
1678 sel->outputs_written |=
1679 1llu << si_shader_io_get_unique_index(name, index);
1680 break;
1681 case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */
1682 case TGSI_SEMANTIC_EDGEFLAG:
1683 break;
1684 default:
1685 sel->outputs_written2 |=
1686 1u << si_shader_io_get_unique_index2(name, index);
1687 }
1688 }
1689 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
1690 break;
1691
1692 case PIPE_SHADER_FRAGMENT:
1693 for (i = 0; i < sel->info.num_inputs; i++) {
1694 unsigned name = sel->info.input_semantic_name[i];
1695 unsigned index = sel->info.input_semantic_index[i];
1696
1697 switch (name) {
1698 case TGSI_SEMANTIC_CLIPDIST:
1699 case TGSI_SEMANTIC_GENERIC:
1700 sel->inputs_read |=
1701 1llu << si_shader_io_get_unique_index(name, index);
1702 break;
1703 case TGSI_SEMANTIC_PCOORD: /* ignore this */
1704 break;
1705 default:
1706 sel->inputs_read2 |=
1707 1u << si_shader_io_get_unique_index2(name, index);
1708 }
1709 }
1710
1711 for (i = 0; i < 8; i++)
1712 if (sel->info.colors_written & (1 << i))
1713 sel->colors_written_4bit |= 0xf << (4 * i);
1714
1715 for (i = 0; i < sel->info.num_inputs; i++) {
1716 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
1717 int index = sel->info.input_semantic_index[i];
1718 sel->color_attr_index[index] = i;
1719 }
1720 }
1721 break;
1722 }
1723
1724 /* DB_SHADER_CONTROL */
1725 sel->db_shader_control =
1726 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
1727 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
1728 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
1729 S_02880C_KILL_ENABLE(sel->info.uses_kill);
1730
1731 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
1732 case TGSI_FS_DEPTH_LAYOUT_GREATER:
1733 sel->db_shader_control |=
1734 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
1735 break;
1736 case TGSI_FS_DEPTH_LAYOUT_LESS:
1737 sel->db_shader_control |=
1738 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
1739 break;
1740 }
1741
1742 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
1743 *
1744 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
1745 * --|-----------|------------|------------|--------------------|-------------------|-------------
1746 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
1747 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
1748 * 2 | false | true | n/a | LateZ | 1 | 0
1749 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
1750 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
1751 *
1752 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
1753 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
1754 *
1755 * Don't use ReZ without profiling !!!
1756 *
1757 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
1758 * shaders.
1759 */
1760 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
1761 /* Cases 3, 4. */
1762 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
1763 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
1764 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
1765 } else if (sel->info.writes_memory) {
1766 /* Case 2. */
1767 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
1768 S_02880C_EXEC_ON_HIER_FAIL(1);
1769 } else {
1770 /* Case 1. */
1771 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
1772 }
1773
1774 (void) mtx_init(&sel->mutex, mtx_plain);
1775 util_queue_fence_init(&sel->ready);
1776
1777 if ((sctx->b.debug.debug_message && !sctx->b.debug.async) ||
1778 sctx->is_debug ||
1779 r600_can_dump_shader(&sscreen->b, sel->info.processor))
1780 si_init_shader_selector_async(sel, -1);
1781 else
1782 util_queue_add_job(&sscreen->shader_compiler_queue, sel,
1783 &sel->ready, si_init_shader_selector_async,
1784 NULL);
1785
1786 return sel;
1787 }
1788
1789 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
1790 {
1791 struct si_context *sctx = (struct si_context *)ctx;
1792 struct si_shader_selector *sel = state;
1793
1794 if (sctx->vs_shader.cso == sel)
1795 return;
1796
1797 sctx->vs_shader.cso = sel;
1798 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
1799 sctx->do_update_shaders = true;
1800 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1801 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1802 }
1803
1804 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
1805 {
1806 struct si_context *sctx = (struct si_context *)ctx;
1807 struct si_shader_selector *sel = state;
1808 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
1809
1810 if (sctx->gs_shader.cso == sel)
1811 return;
1812
1813 sctx->gs_shader.cso = sel;
1814 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
1815 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
1816 sctx->do_update_shaders = true;
1817 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1818 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1819
1820 if (enable_changed)
1821 si_shader_change_notify(sctx);
1822 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1823 }
1824
1825 static void si_update_tcs_tes_uses_prim_id(struct si_context *sctx)
1826 {
1827 sctx->ia_multi_vgt_param_key.u.tcs_tes_uses_prim_id =
1828 (sctx->tes_shader.cso &&
1829 sctx->tes_shader.cso->info.uses_primid) ||
1830 (sctx->tcs_shader.cso &&
1831 sctx->tcs_shader.cso->info.uses_primid);
1832 }
1833
1834 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
1835 {
1836 struct si_context *sctx = (struct si_context *)ctx;
1837 struct si_shader_selector *sel = state;
1838 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
1839
1840 if (sctx->tcs_shader.cso == sel)
1841 return;
1842
1843 sctx->tcs_shader.cso = sel;
1844 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
1845 si_update_tcs_tes_uses_prim_id(sctx);
1846 sctx->do_update_shaders = true;
1847
1848 if (enable_changed)
1849 sctx->last_tcs = NULL; /* invalidate derived tess state */
1850 }
1851
1852 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
1853 {
1854 struct si_context *sctx = (struct si_context *)ctx;
1855 struct si_shader_selector *sel = state;
1856 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
1857
1858 if (sctx->tes_shader.cso == sel)
1859 return;
1860
1861 sctx->tes_shader.cso = sel;
1862 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
1863 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
1864 si_update_tcs_tes_uses_prim_id(sctx);
1865 sctx->do_update_shaders = true;
1866 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1867 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1868
1869 if (enable_changed) {
1870 si_shader_change_notify(sctx);
1871 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
1872 }
1873 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1874 }
1875
1876 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
1877 {
1878 struct si_context *sctx = (struct si_context *)ctx;
1879 struct si_shader_selector *sel = state;
1880
1881 /* skip if supplied shader is one already in use */
1882 if (sctx->ps_shader.cso == sel)
1883 return;
1884
1885 sctx->ps_shader.cso = sel;
1886 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
1887 sctx->do_update_shaders = true;
1888 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
1889 }
1890
1891 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
1892 {
1893 if (shader->is_optimized) {
1894 util_queue_fence_wait(&shader->optimized_ready);
1895 util_queue_fence_destroy(&shader->optimized_ready);
1896 }
1897
1898 if (shader->pm4) {
1899 switch (shader->selector->type) {
1900 case PIPE_SHADER_VERTEX:
1901 if (shader->key.as_ls) {
1902 assert(sctx->b.chip_class <= VI);
1903 si_pm4_delete_state(sctx, ls, shader->pm4);
1904 } else if (shader->key.as_es) {
1905 assert(sctx->b.chip_class <= VI);
1906 si_pm4_delete_state(sctx, es, shader->pm4);
1907 } else {
1908 si_pm4_delete_state(sctx, vs, shader->pm4);
1909 }
1910 break;
1911 case PIPE_SHADER_TESS_CTRL:
1912 si_pm4_delete_state(sctx, hs, shader->pm4);
1913 break;
1914 case PIPE_SHADER_TESS_EVAL:
1915 if (shader->key.as_es) {
1916 assert(sctx->b.chip_class <= VI);
1917 si_pm4_delete_state(sctx, es, shader->pm4);
1918 } else {
1919 si_pm4_delete_state(sctx, vs, shader->pm4);
1920 }
1921 break;
1922 case PIPE_SHADER_GEOMETRY:
1923 if (shader->is_gs_copy_shader)
1924 si_pm4_delete_state(sctx, vs, shader->pm4);
1925 else
1926 si_pm4_delete_state(sctx, gs, shader->pm4);
1927 break;
1928 case PIPE_SHADER_FRAGMENT:
1929 si_pm4_delete_state(sctx, ps, shader->pm4);
1930 break;
1931 }
1932 }
1933
1934 si_shader_destroy(shader);
1935 free(shader);
1936 }
1937
1938 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
1939 {
1940 struct si_context *sctx = (struct si_context *)ctx;
1941 struct si_shader_selector *sel = (struct si_shader_selector *)state;
1942 struct si_shader *p = sel->first_variant, *c;
1943 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
1944 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
1945 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
1946 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
1947 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
1948 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
1949 };
1950
1951 util_queue_fence_wait(&sel->ready);
1952
1953 if (current_shader[sel->type]->cso == sel) {
1954 current_shader[sel->type]->cso = NULL;
1955 current_shader[sel->type]->current = NULL;
1956 }
1957
1958 while (p) {
1959 c = p->next_variant;
1960 si_delete_shader(sctx, p);
1961 p = c;
1962 }
1963
1964 if (sel->main_shader_part)
1965 si_delete_shader(sctx, sel->main_shader_part);
1966 if (sel->main_shader_part_ls)
1967 si_delete_shader(sctx, sel->main_shader_part_ls);
1968 if (sel->main_shader_part_es)
1969 si_delete_shader(sctx, sel->main_shader_part_es);
1970 if (sel->gs_copy_shader)
1971 si_delete_shader(sctx, sel->gs_copy_shader);
1972
1973 util_queue_fence_destroy(&sel->ready);
1974 mtx_destroy(&sel->mutex);
1975 free(sel->tokens);
1976 free(sel);
1977 }
1978
1979 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
1980 struct si_shader *vs, unsigned name,
1981 unsigned index, unsigned interpolate)
1982 {
1983 struct tgsi_shader_info *vsinfo = &vs->selector->info;
1984 unsigned j, offset, ps_input_cntl = 0;
1985
1986 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
1987 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
1988 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1989
1990 if (name == TGSI_SEMANTIC_PCOORD ||
1991 (name == TGSI_SEMANTIC_TEXCOORD &&
1992 sctx->sprite_coord_enable & (1 << index))) {
1993 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
1994 }
1995
1996 for (j = 0; j < vsinfo->num_outputs; j++) {
1997 if (name == vsinfo->output_semantic_name[j] &&
1998 index == vsinfo->output_semantic_index[j]) {
1999 offset = vs->info.vs_output_param_offset[j];
2000
2001 if (offset <= EXP_PARAM_OFFSET_31) {
2002 /* The input is loaded from parameter memory. */
2003 ps_input_cntl |= S_028644_OFFSET(offset);
2004 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2005 if (offset == EXP_PARAM_UNDEFINED) {
2006 /* This can happen with depth-only rendering. */
2007 offset = 0;
2008 } else {
2009 /* The input is a DEFAULT_VAL constant. */
2010 assert(offset >= EXP_PARAM_DEFAULT_VAL_0000 &&
2011 offset <= EXP_PARAM_DEFAULT_VAL_1111);
2012 offset -= EXP_PARAM_DEFAULT_VAL_0000;
2013 }
2014
2015 ps_input_cntl = S_028644_OFFSET(0x20) |
2016 S_028644_DEFAULT_VAL(offset);
2017 }
2018 break;
2019 }
2020 }
2021
2022 if (name == TGSI_SEMANTIC_PRIMID)
2023 /* PrimID is written after the last output. */
2024 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
2025 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2026 /* No corresponding output found, load defaults into input.
2027 * Don't set any other bits.
2028 * (FLAT_SHADE=1 completely changes behavior) */
2029 ps_input_cntl = S_028644_OFFSET(0x20);
2030 /* D3D 9 behaviour. GL is undefined */
2031 if (name == TGSI_SEMANTIC_COLOR && index == 0)
2032 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
2033 }
2034 return ps_input_cntl;
2035 }
2036
2037 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
2038 {
2039 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2040 struct si_shader *ps = sctx->ps_shader.current;
2041 struct si_shader *vs = si_get_vs_state(sctx);
2042 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
2043 unsigned i, num_interp, num_written = 0, bcol_interp[2];
2044
2045 if (!ps || !ps->selector->info.num_inputs)
2046 return;
2047
2048 num_interp = si_get_ps_num_interp(ps);
2049 assert(num_interp > 0);
2050 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
2051
2052 for (i = 0; i < psinfo->num_inputs; i++) {
2053 unsigned name = psinfo->input_semantic_name[i];
2054 unsigned index = psinfo->input_semantic_index[i];
2055 unsigned interpolate = psinfo->input_interpolate[i];
2056
2057 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
2058 interpolate));
2059 num_written++;
2060
2061 if (name == TGSI_SEMANTIC_COLOR) {
2062 assert(index < ARRAY_SIZE(bcol_interp));
2063 bcol_interp[index] = interpolate;
2064 }
2065 }
2066
2067 if (ps->key.part.ps.prolog.color_two_side) {
2068 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
2069
2070 for (i = 0; i < 2; i++) {
2071 if (!(psinfo->colors_read & (0xf << (i * 4))))
2072 continue;
2073
2074 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
2075 i, bcol_interp[i]));
2076 num_written++;
2077 }
2078 }
2079 assert(num_interp == num_written);
2080 }
2081
2082 /**
2083 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2084 */
2085 static void si_init_config_add_vgt_flush(struct si_context *sctx)
2086 {
2087 if (sctx->init_config_has_vgt_flush)
2088 return;
2089
2090 /* Done by Vulkan before VGT_FLUSH. */
2091 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2092 si_pm4_cmd_add(sctx->init_config,
2093 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2094 si_pm4_cmd_end(sctx->init_config, false);
2095
2096 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2097 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2098 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2099 si_pm4_cmd_end(sctx->init_config, false);
2100 sctx->init_config_has_vgt_flush = true;
2101 }
2102
2103 /* Initialize state related to ESGS / GSVS ring buffers */
2104 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2105 {
2106 struct si_shader_selector *es =
2107 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2108 struct si_shader_selector *gs = sctx->gs_shader.cso;
2109 struct si_pm4_state *pm4;
2110
2111 /* Chip constants. */
2112 unsigned num_se = sctx->screen->b.info.max_se;
2113 unsigned wave_size = 64;
2114 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2115 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
2116 unsigned alignment = 256 * num_se;
2117 /* The maximum size is 63.999 MB per SE. */
2118 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2119
2120 /* Calculate the minimum size. */
2121 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
2122 wave_size, alignment);
2123
2124 /* These are recommended sizes, not minimum sizes. */
2125 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2126 es->esgs_itemsize * gs->gs_input_verts_per_prim;
2127 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2128 gs->max_gsvs_emit_size;
2129
2130 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2131 esgs_ring_size = align(esgs_ring_size, alignment);
2132 gsvs_ring_size = align(gsvs_ring_size, alignment);
2133
2134 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2135 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2136
2137 /* Some rings don't have to be allocated if shaders don't use them.
2138 * (e.g. no varyings between ES and GS or GS and VS)
2139 *
2140 * GFX9 doesn't have the ESGS ring.
2141 */
2142 bool update_esgs = sctx->b.chip_class <= VI &&
2143 esgs_ring_size &&
2144 (!sctx->esgs_ring ||
2145 sctx->esgs_ring->width0 < esgs_ring_size);
2146 bool update_gsvs = gsvs_ring_size &&
2147 (!sctx->gsvs_ring ||
2148 sctx->gsvs_ring->width0 < gsvs_ring_size);
2149
2150 if (!update_esgs && !update_gsvs)
2151 return true;
2152
2153 if (update_esgs) {
2154 pipe_resource_reference(&sctx->esgs_ring, NULL);
2155 sctx->esgs_ring =
2156 r600_aligned_buffer_create(sctx->b.b.screen,
2157 R600_RESOURCE_FLAG_UNMAPPABLE,
2158 PIPE_USAGE_DEFAULT,
2159 esgs_ring_size, alignment);
2160 if (!sctx->esgs_ring)
2161 return false;
2162 }
2163
2164 if (update_gsvs) {
2165 pipe_resource_reference(&sctx->gsvs_ring, NULL);
2166 sctx->gsvs_ring =
2167 r600_aligned_buffer_create(sctx->b.b.screen,
2168 R600_RESOURCE_FLAG_UNMAPPABLE,
2169 PIPE_USAGE_DEFAULT,
2170 gsvs_ring_size, alignment);
2171 if (!sctx->gsvs_ring)
2172 return false;
2173 }
2174
2175 /* Create the "init_config_gs_rings" state. */
2176 pm4 = CALLOC_STRUCT(si_pm4_state);
2177 if (!pm4)
2178 return false;
2179
2180 if (sctx->b.chip_class >= CIK) {
2181 if (sctx->esgs_ring) {
2182 assert(sctx->b.chip_class <= VI);
2183 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2184 sctx->esgs_ring->width0 / 256);
2185 }
2186 if (sctx->gsvs_ring)
2187 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2188 sctx->gsvs_ring->width0 / 256);
2189 } else {
2190 if (sctx->esgs_ring)
2191 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2192 sctx->esgs_ring->width0 / 256);
2193 if (sctx->gsvs_ring)
2194 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2195 sctx->gsvs_ring->width0 / 256);
2196 }
2197
2198 /* Set the state. */
2199 if (sctx->init_config_gs_rings)
2200 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
2201 sctx->init_config_gs_rings = pm4;
2202
2203 if (!sctx->init_config_has_vgt_flush) {
2204 si_init_config_add_vgt_flush(sctx);
2205 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2206 }
2207
2208 /* Flush the context to re-emit both init_config states. */
2209 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2210 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2211
2212 /* Set ring bindings. */
2213 if (sctx->esgs_ring) {
2214 assert(sctx->b.chip_class <= VI);
2215 si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
2216 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2217 true, true, 4, 64, 0);
2218 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
2219 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2220 false, false, 0, 0, 0);
2221 }
2222 if (sctx->gsvs_ring) {
2223 si_set_ring_buffer(&sctx->b.b, SI_RING_GSVS,
2224 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
2225 false, false, 0, 0, 0);
2226 }
2227
2228 return true;
2229 }
2230
2231 /**
2232 * @returns 1 if \p sel has been updated to use a new scratch buffer
2233 * 0 if not
2234 * < 0 if there was a failure
2235 */
2236 static int si_update_scratch_buffer(struct si_context *sctx,
2237 struct si_shader *shader)
2238 {
2239 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
2240 int r;
2241
2242 if (!shader)
2243 return 0;
2244
2245 /* This shader doesn't need a scratch buffer */
2246 if (shader->config.scratch_bytes_per_wave == 0)
2247 return 0;
2248
2249 /* This shader is already configured to use the current
2250 * scratch buffer. */
2251 if (shader->scratch_bo == sctx->scratch_buffer)
2252 return 0;
2253
2254 assert(sctx->scratch_buffer);
2255
2256 si_shader_apply_scratch_relocs(sctx, shader, &shader->config, scratch_va);
2257
2258 /* Replace the shader bo with a new bo that has the relocs applied. */
2259 r = si_shader_binary_upload(sctx->screen, shader);
2260 if (r)
2261 return r;
2262
2263 /* Update the shader state to use the new shader bo. */
2264 si_shader_init_pm4_state(sctx->screen, shader);
2265
2266 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
2267
2268 return 1;
2269 }
2270
2271 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
2272 {
2273 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
2274 }
2275
2276 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
2277 {
2278 return shader ? shader->config.scratch_bytes_per_wave : 0;
2279 }
2280
2281 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
2282 {
2283 unsigned bytes = 0;
2284
2285 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
2286 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
2287 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
2288 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tcs_shader.current));
2289 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
2290 return bytes;
2291 }
2292
2293 static bool si_update_spi_tmpring_size(struct si_context *sctx)
2294 {
2295 unsigned current_scratch_buffer_size =
2296 si_get_current_scratch_buffer_size(sctx);
2297 unsigned scratch_bytes_per_wave =
2298 si_get_max_scratch_bytes_per_wave(sctx);
2299 unsigned scratch_needed_size = scratch_bytes_per_wave *
2300 sctx->scratch_waves;
2301 unsigned spi_tmpring_size;
2302 int r;
2303
2304 if (scratch_needed_size > 0) {
2305 if (scratch_needed_size > current_scratch_buffer_size) {
2306 /* Create a bigger scratch buffer */
2307 r600_resource_reference(&sctx->scratch_buffer, NULL);
2308
2309 sctx->scratch_buffer = (struct r600_resource*)
2310 r600_aligned_buffer_create(&sctx->screen->b.b,
2311 R600_RESOURCE_FLAG_UNMAPPABLE,
2312 PIPE_USAGE_DEFAULT,
2313 scratch_needed_size, 256);
2314 if (!sctx->scratch_buffer)
2315 return false;
2316
2317 si_mark_atom_dirty(sctx, &sctx->scratch_state);
2318 r600_context_add_resource_size(&sctx->b.b,
2319 &sctx->scratch_buffer->b.b);
2320 }
2321
2322 /* Update the shaders, so they are using the latest scratch. The
2323 * scratch buffer may have been changed since these shaders were
2324 * last used, so we still need to try to update them, even if
2325 * they require scratch buffers smaller than the current size.
2326 */
2327 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
2328 if (r < 0)
2329 return false;
2330 if (r == 1)
2331 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2332
2333 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
2334 if (r < 0)
2335 return false;
2336 if (r == 1)
2337 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2338
2339 r = si_update_scratch_buffer(sctx, sctx->tcs_shader.current);
2340 if (r < 0)
2341 return false;
2342 if (r == 1)
2343 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
2344
2345 /* VS can be bound as LS, ES, or VS. */
2346 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
2347 if (r < 0)
2348 return false;
2349 if (r == 1) {
2350 if (sctx->tes_shader.current)
2351 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2352 else if (sctx->gs_shader.current)
2353 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2354 else
2355 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2356 }
2357
2358 /* TES can be bound as ES or VS. */
2359 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
2360 if (r < 0)
2361 return false;
2362 if (r == 1) {
2363 if (sctx->gs_shader.current)
2364 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2365 else
2366 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2367 }
2368 }
2369
2370 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
2371 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
2372 "scratch size should already be aligned correctly.");
2373
2374 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
2375 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
2376 if (spi_tmpring_size != sctx->spi_tmpring_size) {
2377 sctx->spi_tmpring_size = spi_tmpring_size;
2378 si_mark_atom_dirty(sctx, &sctx->scratch_state);
2379 }
2380 return true;
2381 }
2382
2383 static void si_init_tess_factor_ring(struct si_context *sctx)
2384 {
2385 bool double_offchip_buffers = sctx->b.chip_class >= CIK &&
2386 sctx->b.family != CHIP_CARRIZO &&
2387 sctx->b.family != CHIP_STONEY;
2388 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2389 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
2390 sctx->screen->b.info.max_se;
2391 unsigned offchip_granularity;
2392
2393 switch (sctx->screen->tess_offchip_block_dw_size) {
2394 default:
2395 assert(0);
2396 /* fall through */
2397 case 8192:
2398 offchip_granularity = V_03093C_X_8K_DWORDS;
2399 break;
2400 case 4096:
2401 offchip_granularity = V_03093C_X_4K_DWORDS;
2402 break;
2403 }
2404
2405 switch (sctx->b.chip_class) {
2406 case SI:
2407 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2408 break;
2409 case CIK:
2410 case VI:
2411 case GFX9:
2412 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2413 break;
2414 default:
2415 assert(0);
2416 return;
2417 }
2418
2419 assert(!sctx->tf_ring);
2420 sctx->tf_ring = r600_aligned_buffer_create(sctx->b.b.screen,
2421 R600_RESOURCE_FLAG_UNMAPPABLE,
2422 PIPE_USAGE_DEFAULT,
2423 32768 * sctx->screen->b.info.max_se,
2424 256);
2425 if (!sctx->tf_ring)
2426 return;
2427
2428 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
2429
2430 sctx->tess_offchip_ring =
2431 r600_aligned_buffer_create(sctx->b.b.screen,
2432 R600_RESOURCE_FLAG_UNMAPPABLE,
2433 PIPE_USAGE_DEFAULT,
2434 max_offchip_buffers *
2435 sctx->screen->tess_offchip_block_dw_size * 4,
2436 256);
2437 if (!sctx->tess_offchip_ring)
2438 return;
2439
2440 si_init_config_add_vgt_flush(sctx);
2441
2442 /* Append these registers to the init config state. */
2443 if (sctx->b.chip_class >= CIK) {
2444 if (sctx->b.chip_class >= VI)
2445 --max_offchip_buffers;
2446
2447 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
2448 S_030938_SIZE(sctx->tf_ring->width0 / 4));
2449 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
2450 r600_resource(sctx->tf_ring)->gpu_address >> 8);
2451 if (sctx->b.chip_class >= GFX9)
2452 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
2453 r600_resource(sctx->tf_ring)->gpu_address >> 40);
2454 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
2455 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2456 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity));
2457 } else {
2458 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
2459 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
2460 S_008988_SIZE(sctx->tf_ring->width0 / 4));
2461 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
2462 r600_resource(sctx->tf_ring)->gpu_address >> 8);
2463 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2464 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers));
2465 }
2466
2467 /* Flush the context to re-emit the init_config state.
2468 * This is done only once in a lifetime of a context.
2469 */
2470 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2471 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2472 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2473
2474 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_FACTOR, sctx->tf_ring,
2475 0, sctx->tf_ring->width0, false, false, 0, 0, 0);
2476
2477 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_OFFCHIP,
2478 sctx->tess_offchip_ring, 0,
2479 sctx->tess_offchip_ring->width0, false, false, 0, 0, 0);
2480 }
2481
2482 /**
2483 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
2484 * VS passes its outputs to TES directly, so the fixed-function shader only
2485 * has to write TESSOUTER and TESSINNER.
2486 */
2487 static void si_generate_fixed_func_tcs(struct si_context *sctx)
2488 {
2489 struct ureg_src outer, inner;
2490 struct ureg_dst tessouter, tessinner;
2491 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
2492
2493 if (!ureg)
2494 return; /* if we get here, we're screwed */
2495
2496 assert(!sctx->fixed_func_tcs_shader.cso);
2497
2498 outer = ureg_DECL_system_value(ureg,
2499 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
2500 inner = ureg_DECL_system_value(ureg,
2501 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
2502
2503 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
2504 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
2505
2506 ureg_MOV(ureg, tessouter, outer);
2507 ureg_MOV(ureg, tessinner, inner);
2508 ureg_END(ureg);
2509
2510 sctx->fixed_func_tcs_shader.cso =
2511 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
2512 }
2513
2514 static void si_update_vgt_shader_config(struct si_context *sctx)
2515 {
2516 /* Calculate the index of the config.
2517 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
2518 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
2519 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
2520
2521 if (!*pm4) {
2522 uint32_t stages = 0;
2523
2524 *pm4 = CALLOC_STRUCT(si_pm4_state);
2525
2526 if (sctx->tes_shader.cso) {
2527 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2528 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2529
2530 if (sctx->gs_shader.cso)
2531 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2532 S_028B54_GS_EN(1) |
2533 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2534 else
2535 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2536 } else if (sctx->gs_shader.cso) {
2537 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2538 S_028B54_GS_EN(1) |
2539 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2540 }
2541
2542 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
2543 }
2544 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
2545 }
2546
2547 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
2548 {
2549 struct pipe_stream_output_info *so = &shader->so;
2550 uint32_t enabled_stream_buffers_mask = 0;
2551 int i;
2552
2553 for (i = 0; i < so->num_outputs; i++)
2554 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
2555 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
2556 sctx->b.streamout.stride_in_dw = shader->so.stride;
2557 }
2558
2559 bool si_update_shaders(struct si_context *sctx)
2560 {
2561 struct pipe_context *ctx = (struct pipe_context*)sctx;
2562 struct si_compiler_ctx_state compiler_state;
2563 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2564 struct si_shader *old_vs = si_get_vs_state(sctx);
2565 bool old_clip_disable = old_vs ? old_vs->key.opt.hw_vs.clip_disable : false;
2566 int r;
2567
2568 compiler_state.tm = sctx->tm;
2569 compiler_state.debug = sctx->b.debug;
2570 compiler_state.is_debug_context = sctx->is_debug;
2571
2572 /* Update stages before GS. */
2573 if (sctx->tes_shader.cso) {
2574 if (!sctx->tf_ring) {
2575 si_init_tess_factor_ring(sctx);
2576 if (!sctx->tf_ring)
2577 return false;
2578 }
2579
2580 /* VS as LS */
2581 if (sctx->b.chip_class <= VI) {
2582 r = si_shader_select(ctx, &sctx->vs_shader,
2583 &compiler_state);
2584 if (r)
2585 return false;
2586 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2587 }
2588
2589 if (sctx->tcs_shader.cso) {
2590 r = si_shader_select(ctx, &sctx->tcs_shader,
2591 &compiler_state);
2592 if (r)
2593 return false;
2594 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
2595 } else {
2596 if (!sctx->fixed_func_tcs_shader.cso) {
2597 si_generate_fixed_func_tcs(sctx);
2598 if (!sctx->fixed_func_tcs_shader.cso)
2599 return false;
2600 }
2601
2602 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
2603 &compiler_state);
2604 if (r)
2605 return false;
2606 si_pm4_bind_state(sctx, hs,
2607 sctx->fixed_func_tcs_shader.current->pm4);
2608 }
2609
2610 if (sctx->gs_shader.cso) {
2611 /* TES as ES */
2612 if (sctx->b.chip_class <= VI) {
2613 r = si_shader_select(ctx, &sctx->tes_shader,
2614 &compiler_state);
2615 if (r)
2616 return false;
2617 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2618 }
2619 } else {
2620 /* TES as VS */
2621 r = si_shader_select(ctx, &sctx->tes_shader,
2622 &compiler_state);
2623 if (r)
2624 return false;
2625 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2626 si_update_so(sctx, sctx->tes_shader.cso);
2627 }
2628 } else if (sctx->gs_shader.cso) {
2629 if (sctx->b.chip_class <= VI) {
2630 /* VS as ES */
2631 r = si_shader_select(ctx, &sctx->vs_shader,
2632 &compiler_state);
2633 if (r)
2634 return false;
2635 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2636
2637 si_pm4_bind_state(sctx, ls, NULL);
2638 si_pm4_bind_state(sctx, hs, NULL);
2639 }
2640 } else {
2641 /* VS as VS */
2642 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
2643 if (r)
2644 return false;
2645 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2646 si_update_so(sctx, sctx->vs_shader.cso);
2647
2648 si_pm4_bind_state(sctx, ls, NULL);
2649 si_pm4_bind_state(sctx, hs, NULL);
2650 }
2651
2652 /* Update GS. */
2653 if (sctx->gs_shader.cso) {
2654 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
2655 if (r)
2656 return false;
2657 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2658 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
2659 si_update_so(sctx, sctx->gs_shader.cso);
2660
2661 if (!si_update_gs_ring_buffers(sctx))
2662 return false;
2663 } else {
2664 si_pm4_bind_state(sctx, gs, NULL);
2665 if (sctx->b.chip_class <= VI)
2666 si_pm4_bind_state(sctx, es, NULL);
2667 }
2668
2669 si_update_vgt_shader_config(sctx);
2670
2671 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.hw_vs.clip_disable)
2672 si_mark_atom_dirty(sctx, &sctx->clip_regs);
2673
2674 if (sctx->ps_shader.cso) {
2675 unsigned db_shader_control;
2676
2677 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
2678 if (r)
2679 return false;
2680 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2681
2682 db_shader_control =
2683 sctx->ps_shader.cso->db_shader_control |
2684 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
2685
2686 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
2687 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
2688 sctx->flatshade != rs->flatshade) {
2689 sctx->sprite_coord_enable = rs->sprite_coord_enable;
2690 sctx->flatshade = rs->flatshade;
2691 si_mark_atom_dirty(sctx, &sctx->spi_map);
2692 }
2693
2694 if (sctx->screen->b.rbplus_allowed && si_pm4_state_changed(sctx, ps))
2695 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2696
2697 if (sctx->ps_db_shader_control != db_shader_control) {
2698 sctx->ps_db_shader_control = db_shader_control;
2699 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2700 }
2701
2702 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
2703 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
2704 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2705
2706 if (sctx->b.chip_class == SI)
2707 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2708
2709 if (sctx->framebuffer.nr_samples <= 1)
2710 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2711 }
2712 }
2713
2714 if (si_pm4_state_changed(sctx, ls) ||
2715 si_pm4_state_changed(sctx, hs) ||
2716 si_pm4_state_changed(sctx, es) ||
2717 si_pm4_state_changed(sctx, gs) ||
2718 si_pm4_state_changed(sctx, vs) ||
2719 si_pm4_state_changed(sctx, ps)) {
2720 if (!si_update_spi_tmpring_size(sctx))
2721 return false;
2722 }
2723
2724 if (sctx->b.chip_class >= CIK)
2725 si_mark_atom_dirty(sctx, &sctx->prefetch_L2);
2726
2727 sctx->do_update_shaders = false;
2728 return true;
2729 }
2730
2731 static void si_emit_scratch_state(struct si_context *sctx,
2732 struct r600_atom *atom)
2733 {
2734 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2735
2736 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
2737 sctx->spi_tmpring_size);
2738
2739 if (sctx->scratch_buffer) {
2740 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2741 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
2742 RADEON_PRIO_SCRATCH_BUFFER);
2743 }
2744 }
2745
2746 void si_init_shader_functions(struct si_context *sctx)
2747 {
2748 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
2749 si_init_atom(sctx, &sctx->scratch_state, &sctx->atoms.s.scratch_state,
2750 si_emit_scratch_state);
2751
2752 sctx->b.b.create_vs_state = si_create_shader_selector;
2753 sctx->b.b.create_tcs_state = si_create_shader_selector;
2754 sctx->b.b.create_tes_state = si_create_shader_selector;
2755 sctx->b.b.create_gs_state = si_create_shader_selector;
2756 sctx->b.b.create_fs_state = si_create_shader_selector;
2757
2758 sctx->b.b.bind_vs_state = si_bind_vs_shader;
2759 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
2760 sctx->b.b.bind_tes_state = si_bind_tes_shader;
2761 sctx->b.b.bind_gs_state = si_bind_gs_shader;
2762 sctx->b.b.bind_fs_state = si_bind_ps_shader;
2763
2764 sctx->b.b.delete_vs_state = si_delete_shader_selector;
2765 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
2766 sctx->b.b.delete_tes_state = si_delete_shader_selector;
2767 sctx->b.b.delete_gs_state = si_delete_shader_selector;
2768 sctx->b.b.delete_fs_state = si_delete_shader_selector;
2769 }