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radeonsi: separate the call to si_llvm_emit_streamout from exports
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_ureg.h"
34 #include "util/hash_table.h"
35 #include "util/crc32.h"
36 #include "util/u_memory.h"
37 #include "util/u_prim.h"
38
39 /* SHADER_CACHE */
40
41 /**
42 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
43 * integer.
44 */
45 static void *si_get_tgsi_binary(struct si_shader_selector *sel)
46 {
47 unsigned tgsi_size = tgsi_num_tokens(sel->tokens) *
48 sizeof(struct tgsi_token);
49 unsigned size = 4 + tgsi_size + sizeof(sel->so);
50 char *result = (char*)MALLOC(size);
51
52 if (!result)
53 return NULL;
54
55 *((uint32_t*)result) = size;
56 memcpy(result + 4, sel->tokens, tgsi_size);
57 memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so));
58 return result;
59 }
60
61 /** Copy "data" to "ptr" and return the next dword following copied data. */
62 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
63 {
64 /* data may be NULL if size == 0 */
65 if (size)
66 memcpy(ptr, data, size);
67 ptr += DIV_ROUND_UP(size, 4);
68 return ptr;
69 }
70
71 /** Read data from "ptr". Return the next dword following the data. */
72 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
73 {
74 memcpy(data, ptr, size);
75 ptr += DIV_ROUND_UP(size, 4);
76 return ptr;
77 }
78
79 /**
80 * Write the size as uint followed by the data. Return the next dword
81 * following the copied data.
82 */
83 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
84 {
85 *ptr++ = size;
86 return write_data(ptr, data, size);
87 }
88
89 /**
90 * Read the size as uint followed by the data. Return both via parameters.
91 * Return the next dword following the data.
92 */
93 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
94 {
95 *size = *ptr++;
96 assert(*data == NULL);
97 if (!*size)
98 return ptr;
99 *data = malloc(*size);
100 return read_data(ptr, *data, *size);
101 }
102
103 /**
104 * Return the shader binary in a buffer. The first 4 bytes contain its size
105 * as integer.
106 */
107 static void *si_get_shader_binary(struct si_shader *shader)
108 {
109 /* There is always a size of data followed by the data itself. */
110 unsigned relocs_size = shader->binary.reloc_count *
111 sizeof(shader->binary.relocs[0]);
112 unsigned disasm_size = strlen(shader->binary.disasm_string) + 1;
113 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
114 strlen(shader->binary.llvm_ir_string) + 1 : 0;
115 unsigned size =
116 4 + /* total size */
117 4 + /* CRC32 of the data below */
118 align(sizeof(shader->config), 4) +
119 align(sizeof(shader->info), 4) +
120 4 + align(shader->binary.code_size, 4) +
121 4 + align(shader->binary.rodata_size, 4) +
122 4 + align(relocs_size, 4) +
123 4 + align(disasm_size, 4) +
124 4 + align(llvm_ir_size, 4);
125 void *buffer = CALLOC(1, size);
126 uint32_t *ptr = (uint32_t*)buffer;
127
128 if (!buffer)
129 return NULL;
130
131 *ptr++ = size;
132 ptr++; /* CRC32 is calculated at the end. */
133
134 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
135 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
136 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
137 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
138 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
139 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
140 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
141 assert((char *)ptr - (char *)buffer == size);
142
143 /* Compute CRC32. */
144 ptr = (uint32_t*)buffer;
145 ptr++;
146 *ptr = util_hash_crc32(ptr + 1, size - 8);
147
148 return buffer;
149 }
150
151 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
152 {
153 uint32_t *ptr = (uint32_t*)binary;
154 uint32_t size = *ptr++;
155 uint32_t crc32 = *ptr++;
156 unsigned chunk_size;
157
158 if (util_hash_crc32(ptr, size - 8) != crc32) {
159 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
160 return false;
161 }
162
163 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
164 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
165 ptr = read_chunk(ptr, (void**)&shader->binary.code,
166 &shader->binary.code_size);
167 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
168 &shader->binary.rodata_size);
169 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
170 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
171 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
172 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
173
174 return true;
175 }
176
177 /**
178 * Insert a shader into the cache. It's assumed the shader is not in the cache.
179 * Use si_shader_cache_load_shader before calling this.
180 *
181 * Returns false on failure, in which case the tgsi_binary should be freed.
182 */
183 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
184 void *tgsi_binary,
185 struct si_shader *shader)
186 {
187 void *hw_binary;
188 struct hash_entry *entry;
189
190 entry = _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
191 if (entry)
192 return false; /* already added */
193
194 hw_binary = si_get_shader_binary(shader);
195 if (!hw_binary)
196 return false;
197
198 if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
199 hw_binary) == NULL) {
200 FREE(hw_binary);
201 return false;
202 }
203
204 return true;
205 }
206
207 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
208 void *tgsi_binary,
209 struct si_shader *shader)
210 {
211 struct hash_entry *entry =
212 _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
213 if (!entry)
214 return false;
215
216 if (!si_load_shader_binary(shader, entry->data))
217 return false;
218
219 p_atomic_inc(&sscreen->b.num_shader_cache_hits);
220 return true;
221 }
222
223 static uint32_t si_shader_cache_key_hash(const void *key)
224 {
225 /* The first dword is the key size. */
226 return util_hash_crc32(key, *(uint32_t*)key);
227 }
228
229 static bool si_shader_cache_key_equals(const void *a, const void *b)
230 {
231 uint32_t *keya = (uint32_t*)a;
232 uint32_t *keyb = (uint32_t*)b;
233
234 /* The first dword is the key size. */
235 if (*keya != *keyb)
236 return false;
237
238 return memcmp(keya, keyb, *keya) == 0;
239 }
240
241 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
242 {
243 FREE((void*)entry->key);
244 FREE(entry->data);
245 }
246
247 bool si_init_shader_cache(struct si_screen *sscreen)
248 {
249 pipe_mutex_init(sscreen->shader_cache_mutex);
250 sscreen->shader_cache =
251 _mesa_hash_table_create(NULL,
252 si_shader_cache_key_hash,
253 si_shader_cache_key_equals);
254 return sscreen->shader_cache != NULL;
255 }
256
257 void si_destroy_shader_cache(struct si_screen *sscreen)
258 {
259 if (sscreen->shader_cache)
260 _mesa_hash_table_destroy(sscreen->shader_cache,
261 si_destroy_shader_cache_entry);
262 pipe_mutex_destroy(sscreen->shader_cache_mutex);
263 }
264
265 /* SHADER STATES */
266
267 static void si_set_tesseval_regs(struct si_screen *sscreen,
268 struct si_shader *shader,
269 struct si_pm4_state *pm4)
270 {
271 struct tgsi_shader_info *info = &shader->selector->info;
272 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
273 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
274 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
275 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
276 unsigned type, partitioning, topology, distribution_mode;
277
278 switch (tes_prim_mode) {
279 case PIPE_PRIM_LINES:
280 type = V_028B6C_TESS_ISOLINE;
281 break;
282 case PIPE_PRIM_TRIANGLES:
283 type = V_028B6C_TESS_TRIANGLE;
284 break;
285 case PIPE_PRIM_QUADS:
286 type = V_028B6C_TESS_QUAD;
287 break;
288 default:
289 assert(0);
290 return;
291 }
292
293 switch (tes_spacing) {
294 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
295 partitioning = V_028B6C_PART_FRAC_ODD;
296 break;
297 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
298 partitioning = V_028B6C_PART_FRAC_EVEN;
299 break;
300 case PIPE_TESS_SPACING_EQUAL:
301 partitioning = V_028B6C_PART_INTEGER;
302 break;
303 default:
304 assert(0);
305 return;
306 }
307
308 if (tes_point_mode)
309 topology = V_028B6C_OUTPUT_POINT;
310 else if (tes_prim_mode == PIPE_PRIM_LINES)
311 topology = V_028B6C_OUTPUT_LINE;
312 else if (tes_vertex_order_cw)
313 /* for some reason, this must be the other way around */
314 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
315 else
316 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
317
318 if (sscreen->has_distributed_tess) {
319 if (sscreen->b.family == CHIP_FIJI ||
320 sscreen->b.family >= CHIP_POLARIS10)
321 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
322 else
323 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
324 } else
325 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
326
327 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
328 S_028B6C_TYPE(type) |
329 S_028B6C_PARTITIONING(partitioning) |
330 S_028B6C_TOPOLOGY(topology) |
331 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
332 }
333
334 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
335 {
336 if (shader->pm4)
337 si_pm4_clear_state(shader->pm4);
338 else
339 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
340
341 return shader->pm4;
342 }
343
344 static void si_shader_ls(struct si_shader *shader)
345 {
346 struct si_pm4_state *pm4;
347 unsigned vgpr_comp_cnt;
348 uint64_t va;
349
350 pm4 = si_get_shader_pm4_state(shader);
351 if (!pm4)
352 return;
353
354 va = shader->bo->gpu_address;
355 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
356
357 /* We need at least 2 components for LS.
358 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
359 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 1;
360
361 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
362 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
363
364 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
365 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
366 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
367 S_00B528_DX10_CLAMP(1) |
368 S_00B528_FLOAT_MODE(shader->config.float_mode);
369 shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_LS_NUM_USER_SGPR) |
370 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
371 }
372
373 static void si_shader_hs(struct si_shader *shader)
374 {
375 struct si_pm4_state *pm4;
376 uint64_t va;
377
378 pm4 = si_get_shader_pm4_state(shader);
379 if (!pm4)
380 return;
381
382 va = shader->bo->gpu_address;
383 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
384
385 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
386 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
387 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
388 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
389 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
390 S_00B428_DX10_CLAMP(1) |
391 S_00B428_FLOAT_MODE(shader->config.float_mode));
392 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
393 S_00B42C_USER_SGPR(SI_TCS_NUM_USER_SGPR) |
394 S_00B42C_OC_LDS_EN(1) |
395 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
396 }
397
398 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
399 {
400 struct si_pm4_state *pm4;
401 unsigned num_user_sgprs;
402 unsigned vgpr_comp_cnt;
403 uint64_t va;
404 unsigned oc_lds_en;
405
406 pm4 = si_get_shader_pm4_state(shader);
407 if (!pm4)
408 return;
409
410 va = shader->bo->gpu_address;
411 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
412
413 if (shader->selector->type == PIPE_SHADER_VERTEX) {
414 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
415 num_user_sgprs = SI_ES_NUM_USER_SGPR;
416 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
417 vgpr_comp_cnt = 3; /* all components are needed for TES */
418 num_user_sgprs = SI_TES_NUM_USER_SGPR;
419 } else
420 unreachable("invalid shader selector type");
421
422 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
423
424 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
425 shader->selector->esgs_itemsize / 4);
426 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
427 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
428 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
429 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
430 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
431 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
432 S_00B328_DX10_CLAMP(1) |
433 S_00B328_FLOAT_MODE(shader->config.float_mode));
434 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
435 S_00B32C_USER_SGPR(num_user_sgprs) |
436 S_00B32C_OC_LDS_EN(oc_lds_en) |
437 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
438
439 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
440 si_set_tesseval_regs(sscreen, shader, pm4);
441 }
442
443 /**
444 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
445 * geometry shader.
446 */
447 static uint32_t si_vgt_gs_mode(struct si_shader_selector *sel)
448 {
449 unsigned gs_max_vert_out = sel->gs_max_out_vertices;
450 unsigned cut_mode;
451
452 if (gs_max_vert_out <= 128) {
453 cut_mode = V_028A40_GS_CUT_128;
454 } else if (gs_max_vert_out <= 256) {
455 cut_mode = V_028A40_GS_CUT_256;
456 } else if (gs_max_vert_out <= 512) {
457 cut_mode = V_028A40_GS_CUT_512;
458 } else {
459 assert(gs_max_vert_out <= 1024);
460 cut_mode = V_028A40_GS_CUT_1024;
461 }
462
463 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
464 S_028A40_CUT_MODE(cut_mode)|
465 S_028A40_ES_WRITE_OPTIMIZE(1) |
466 S_028A40_GS_WRITE_OPTIMIZE(1);
467 }
468
469 static void si_shader_gs(struct si_shader *shader)
470 {
471 unsigned gs_vert_itemsize = shader->selector->gsvs_vertex_size;
472 unsigned gsvs_itemsize = shader->selector->max_gsvs_emit_size >> 2;
473 unsigned gs_num_invocations = shader->selector->gs_num_invocations;
474 struct si_pm4_state *pm4;
475 uint64_t va;
476 unsigned max_stream = shader->selector->max_gs_stream;
477
478 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
479 assert(gsvs_itemsize < (1 << 15));
480
481 pm4 = si_get_shader_pm4_state(shader);
482 if (!pm4)
483 return;
484
485 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(shader->selector));
486
487 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
488 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize * ((max_stream >= 2) ? 2 : 1));
489 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize * ((max_stream >= 3) ? 3 : 1));
490
491 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize * (max_stream + 1));
492
493 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, shader->selector->gs_max_out_vertices);
494
495 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize >> 2);
496 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? gs_vert_itemsize >> 2 : 0);
497 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? gs_vert_itemsize >> 2 : 0);
498 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? gs_vert_itemsize >> 2 : 0);
499
500 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
501 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
502 S_028B90_ENABLE(gs_num_invocations > 0));
503
504 va = shader->bo->gpu_address;
505 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
506 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
507 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
508
509 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
510 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
511 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
512 S_00B228_DX10_CLAMP(1) |
513 S_00B228_FLOAT_MODE(shader->config.float_mode));
514 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
515 S_00B22C_USER_SGPR(SI_GS_NUM_USER_SGPR) |
516 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
517 }
518
519 /**
520 * Compute the state for \p shader, which will run as a vertex shader on the
521 * hardware.
522 *
523 * If \p gs is non-NULL, it points to the geometry shader for which this shader
524 * is the copy shader.
525 */
526 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
527 struct si_shader_selector *gs)
528 {
529 struct si_pm4_state *pm4;
530 unsigned num_user_sgprs;
531 unsigned nparams, vgpr_comp_cnt;
532 uint64_t va;
533 unsigned oc_lds_en;
534 unsigned window_space =
535 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
536 bool enable_prim_id = si_vs_exports_prim_id(shader);
537
538 pm4 = si_get_shader_pm4_state(shader);
539 if (!pm4)
540 return;
541
542 /* We always write VGT_GS_MODE in the VS state, because every switch
543 * between different shader pipelines involving a different GS or no
544 * GS at all involves a switch of the VS (different GS use different
545 * copy shaders). On the other hand, when the API switches from a GS to
546 * no GS and then back to the same GS used originally, the GS state is
547 * not sent again.
548 */
549 if (!gs) {
550 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
551 S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
552 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
553 } else {
554 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
555 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
556 }
557
558 va = shader->bo->gpu_address;
559 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
560
561 if (gs) {
562 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
563 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
564 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
565 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
566 num_user_sgprs = SI_VS_NUM_USER_SGPR;
567 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
568 vgpr_comp_cnt = 3; /* all components are needed for TES */
569 num_user_sgprs = SI_TES_NUM_USER_SGPR;
570 } else
571 unreachable("invalid shader selector type");
572
573 /* VS is required to export at least one param. */
574 nparams = MAX2(shader->info.nr_param_exports, 1);
575 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
576 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
577
578 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
579 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
580 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
581 V_02870C_SPI_SHADER_4COMP :
582 V_02870C_SPI_SHADER_NONE) |
583 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
584 V_02870C_SPI_SHADER_4COMP :
585 V_02870C_SPI_SHADER_NONE) |
586 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
587 V_02870C_SPI_SHADER_4COMP :
588 V_02870C_SPI_SHADER_NONE));
589
590 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
591
592 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
593 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
594 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
595 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
596 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
597 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
598 S_00B128_DX10_CLAMP(1) |
599 S_00B128_FLOAT_MODE(shader->config.float_mode));
600 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
601 S_00B12C_USER_SGPR(num_user_sgprs) |
602 S_00B12C_OC_LDS_EN(oc_lds_en) |
603 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
604 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
605 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
606 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
607 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
608 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
609 if (window_space)
610 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
611 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
612 else
613 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
614 S_028818_VTX_W0_FMT(1) |
615 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
616 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
617 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
618
619 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
620 si_set_tesseval_regs(sscreen, shader, pm4);
621 }
622
623 static unsigned si_get_ps_num_interp(struct si_shader *ps)
624 {
625 struct tgsi_shader_info *info = &ps->selector->info;
626 unsigned num_colors = !!(info->colors_read & 0x0f) +
627 !!(info->colors_read & 0xf0);
628 unsigned num_interp = ps->selector->info.num_inputs +
629 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
630
631 assert(num_interp <= 32);
632 return MIN2(num_interp, 32);
633 }
634
635 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
636 {
637 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
638 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
639
640 /* If the i-th target format is set, all previous target formats must
641 * be non-zero to avoid hangs.
642 */
643 for (i = 0; i < num_targets; i++)
644 if (!(value & (0xf << (i * 4))))
645 value |= V_028714_SPI_SHADER_32_R << (i * 4);
646
647 return value;
648 }
649
650 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
651 {
652 unsigned i, cb_shader_mask = 0;
653
654 for (i = 0; i < 8; i++) {
655 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
656 case V_028714_SPI_SHADER_ZERO:
657 break;
658 case V_028714_SPI_SHADER_32_R:
659 cb_shader_mask |= 0x1 << (i * 4);
660 break;
661 case V_028714_SPI_SHADER_32_GR:
662 cb_shader_mask |= 0x3 << (i * 4);
663 break;
664 case V_028714_SPI_SHADER_32_AR:
665 cb_shader_mask |= 0x9 << (i * 4);
666 break;
667 case V_028714_SPI_SHADER_FP16_ABGR:
668 case V_028714_SPI_SHADER_UNORM16_ABGR:
669 case V_028714_SPI_SHADER_SNORM16_ABGR:
670 case V_028714_SPI_SHADER_UINT16_ABGR:
671 case V_028714_SPI_SHADER_SINT16_ABGR:
672 case V_028714_SPI_SHADER_32_ABGR:
673 cb_shader_mask |= 0xf << (i * 4);
674 break;
675 default:
676 assert(0);
677 }
678 }
679 return cb_shader_mask;
680 }
681
682 static void si_shader_ps(struct si_shader *shader)
683 {
684 struct tgsi_shader_info *info = &shader->selector->info;
685 struct si_pm4_state *pm4;
686 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
687 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
688 uint64_t va;
689 unsigned input_ena = shader->config.spi_ps_input_ena;
690
691 /* we need to enable at least one of them, otherwise we hang the GPU */
692 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
693 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
694 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
695 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
696 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
697 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
698 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
699 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
700 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
701 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
702 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
703 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
704 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
705 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
706
707 /* Validate interpolation optimization flags (read as implications). */
708 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
709 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
710 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
711 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
712 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
713 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
714 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
715 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
716 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
717 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
718 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
719 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
720 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
721 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
722 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
723 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
724 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
725 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
726
727 /* Validate cases when the optimizations are off (read as implications). */
728 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
729 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
730 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
731 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
732 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
733 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
734
735 pm4 = si_get_shader_pm4_state(shader);
736 if (!pm4)
737 return;
738
739 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
740 * Possible vaules:
741 * 0 -> Position = pixel center
742 * 1 -> Position = pixel centroid
743 * 2 -> Position = at sample position
744 *
745 * From GLSL 4.5 specification, section 7.1:
746 * "The variable gl_FragCoord is available as an input variable from
747 * within fragment shaders and it holds the window relative coordinates
748 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
749 * value can be for any location within the pixel, or one of the
750 * fragment samples. The use of centroid does not further restrict
751 * this value to be inside the current primitive."
752 *
753 * Meaning that centroid has no effect and we can return anything within
754 * the pixel. Thus, return the value at sample position, because that's
755 * the most accurate one shaders can get.
756 */
757 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
758
759 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
760 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
761 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
762
763 spi_shader_col_format = si_get_spi_shader_col_format(shader);
764 cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
765
766 /* Ensure that some export memory is always allocated, for two reasons:
767 *
768 * 1) Correctness: The hardware ignores the EXEC mask if no export
769 * memory is allocated, so KILL and alpha test do not work correctly
770 * without this.
771 * 2) Performance: Every shader needs at least a NULL export, even when
772 * it writes no color/depth output. The NULL export instruction
773 * stalls without this setting.
774 *
775 * Don't add this to CB_SHADER_MASK.
776 */
777 if (!spi_shader_col_format &&
778 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
779 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
780
781 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
782 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
783 shader->config.spi_ps_input_addr);
784
785 /* Set interpolation controls. */
786 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
787
788 /* Set registers. */
789 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
790 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
791
792 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
793 si_get_spi_shader_z_format(info->writes_z,
794 info->writes_stencil,
795 info->writes_samplemask));
796
797 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
798 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
799
800 va = shader->bo->gpu_address;
801 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
802 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
803 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
804
805 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
806 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
807 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
808 S_00B028_DX10_CLAMP(1) |
809 S_00B028_FLOAT_MODE(shader->config.float_mode));
810 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
811 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
812 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
813 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
814 }
815
816 static void si_shader_init_pm4_state(struct si_screen *sscreen,
817 struct si_shader *shader)
818 {
819 switch (shader->selector->type) {
820 case PIPE_SHADER_VERTEX:
821 if (shader->key.as_ls)
822 si_shader_ls(shader);
823 else if (shader->key.as_es)
824 si_shader_es(sscreen, shader);
825 else
826 si_shader_vs(sscreen, shader, NULL);
827 break;
828 case PIPE_SHADER_TESS_CTRL:
829 si_shader_hs(shader);
830 break;
831 case PIPE_SHADER_TESS_EVAL:
832 if (shader->key.as_es)
833 si_shader_es(sscreen, shader);
834 else
835 si_shader_vs(sscreen, shader, NULL);
836 break;
837 case PIPE_SHADER_GEOMETRY:
838 si_shader_gs(shader);
839 break;
840 case PIPE_SHADER_FRAGMENT:
841 si_shader_ps(shader);
842 break;
843 default:
844 assert(0);
845 }
846 }
847
848 static unsigned si_get_alpha_test_func(struct si_context *sctx)
849 {
850 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
851 if (sctx->queued.named.dsa)
852 return sctx->queued.named.dsa->alpha_func;
853
854 return PIPE_FUNC_ALWAYS;
855 }
856
857 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
858 struct si_shader_selector *vs,
859 struct si_shader_key *key)
860 {
861 struct si_shader_selector *ps = sctx->ps_shader.cso;
862
863 key->opt.hw_vs.clip_disable =
864 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
865 (vs->info.clipdist_writemask ||
866 vs->info.writes_clipvertex) &&
867 !vs->info.culldist_writemask;
868
869 /* Find out if PS is disabled. */
870 bool ps_disabled = true;
871 if (ps) {
872 bool ps_modifies_zs = ps->info.uses_kill ||
873 ps->info.writes_z ||
874 ps->info.writes_stencil ||
875 ps->info.writes_samplemask ||
876 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
877
878 unsigned ps_colormask = sctx->framebuffer.colorbuf_enabled_4bit &
879 sctx->queued.named.blend->cb_target_mask;
880 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
881 ps_colormask &= ps->colors_written_4bit;
882
883 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
884 (!ps_colormask &&
885 !ps_modifies_zs &&
886 !ps->info.writes_memory);
887 }
888
889 /* Find out which VS outputs aren't used by the PS. */
890 uint64_t outputs_written = vs->outputs_written;
891 uint32_t outputs_written2 = vs->outputs_written2;
892 uint64_t inputs_read = 0;
893 uint32_t inputs_read2 = 0;
894
895 outputs_written &= ~0x3; /* ignore POSITION, PSIZE */
896
897 if (!ps_disabled) {
898 inputs_read = ps->inputs_read;
899 inputs_read2 = ps->inputs_read2;
900 }
901
902 uint64_t linked = outputs_written & inputs_read;
903 uint32_t linked2 = outputs_written2 & inputs_read2;
904
905 key->opt.hw_vs.kill_outputs = ~linked & outputs_written;
906 key->opt.hw_vs.kill_outputs2 = ~linked2 & outputs_written2;
907 }
908
909 /* Compute the key for the hw shader variant */
910 static inline void si_shader_selector_key(struct pipe_context *ctx,
911 struct si_shader_selector *sel,
912 struct si_shader_key *key)
913 {
914 struct si_context *sctx = (struct si_context *)ctx;
915 unsigned i;
916
917 memset(key, 0, sizeof(*key));
918
919 switch (sel->type) {
920 case PIPE_SHADER_VERTEX:
921 if (sctx->vertex_elements) {
922 unsigned count = MIN2(sel->info.num_inputs,
923 sctx->vertex_elements->count);
924 for (i = 0; i < count; ++i)
925 key->part.vs.prolog.instance_divisors[i] =
926 sctx->vertex_elements->elements[i].instance_divisor;
927
928 key->mono.vs.fix_fetch =
929 sctx->vertex_elements->fix_fetch &
930 u_bit_consecutive(0, 2 * count);
931 }
932 if (sctx->tes_shader.cso)
933 key->as_ls = 1;
934 else if (sctx->gs_shader.cso)
935 key->as_es = 1;
936 else {
937 si_shader_selector_key_hw_vs(sctx, sel, key);
938
939 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
940 key->part.vs.epilog.export_prim_id = 1;
941 }
942 break;
943 case PIPE_SHADER_TESS_CTRL:
944 key->part.tcs.epilog.prim_mode =
945 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
946
947 if (sel == sctx->fixed_func_tcs_shader.cso)
948 key->mono.tcs.inputs_to_copy = sctx->vs_shader.cso->outputs_written;
949 break;
950 case PIPE_SHADER_TESS_EVAL:
951 if (sctx->gs_shader.cso)
952 key->as_es = 1;
953 else {
954 si_shader_selector_key_hw_vs(sctx, sel, key);
955
956 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
957 key->part.tes.epilog.export_prim_id = 1;
958 }
959 break;
960 case PIPE_SHADER_GEOMETRY:
961 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
962 break;
963 case PIPE_SHADER_FRAGMENT: {
964 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
965 struct si_state_blend *blend = sctx->queued.named.blend;
966
967 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
968 sel->info.colors_written == 0x1)
969 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
970
971 if (blend) {
972 /* Select the shader color format based on whether
973 * blending or alpha are needed.
974 */
975 key->part.ps.epilog.spi_shader_col_format =
976 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
977 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
978 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
979 sctx->framebuffer.spi_shader_col_format_blend) |
980 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
981 sctx->framebuffer.spi_shader_col_format_alpha) |
982 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
983 sctx->framebuffer.spi_shader_col_format);
984
985 /* The output for dual source blending should have
986 * the same format as the first output.
987 */
988 if (blend->dual_src_blend)
989 key->part.ps.epilog.spi_shader_col_format |=
990 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
991 } else
992 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
993
994 /* If alpha-to-coverage is enabled, we have to export alpha
995 * even if there is no color buffer.
996 */
997 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
998 blend && blend->alpha_to_coverage)
999 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1000
1001 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1002 * to the range supported by the type if a channel has less
1003 * than 16 bits and the export format is 16_ABGR.
1004 */
1005 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII)
1006 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1007
1008 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1009 if (!key->part.ps.epilog.last_cbuf) {
1010 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1011 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1012 }
1013
1014 if (rs) {
1015 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
1016 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
1017 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
1018 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
1019
1020 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1021 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1022
1023 if (sctx->queued.named.blend) {
1024 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1025 rs->multisample_enable;
1026 }
1027
1028 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1029 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1030 (is_line && rs->line_smooth)) &&
1031 sctx->framebuffer.nr_samples <= 1;
1032 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1033
1034 if (rs->force_persample_interp &&
1035 rs->multisample_enable &&
1036 sctx->framebuffer.nr_samples > 1 &&
1037 sctx->ps_iter_samples > 1) {
1038 key->part.ps.prolog.force_persp_sample_interp =
1039 sel->info.uses_persp_center ||
1040 sel->info.uses_persp_centroid;
1041
1042 key->part.ps.prolog.force_linear_sample_interp =
1043 sel->info.uses_linear_center ||
1044 sel->info.uses_linear_centroid;
1045 } else if (rs->multisample_enable &&
1046 sctx->framebuffer.nr_samples > 1) {
1047 key->part.ps.prolog.bc_optimize_for_persp =
1048 sel->info.uses_persp_center &&
1049 sel->info.uses_persp_centroid;
1050 key->part.ps.prolog.bc_optimize_for_linear =
1051 sel->info.uses_linear_center &&
1052 sel->info.uses_linear_centroid;
1053 } else {
1054 /* Make sure SPI doesn't compute more than 1 pair
1055 * of (i,j), which is the optimization here. */
1056 key->part.ps.prolog.force_persp_center_interp =
1057 sel->info.uses_persp_center +
1058 sel->info.uses_persp_centroid +
1059 sel->info.uses_persp_sample > 1;
1060
1061 key->part.ps.prolog.force_linear_center_interp =
1062 sel->info.uses_linear_center +
1063 sel->info.uses_linear_centroid +
1064 sel->info.uses_linear_sample > 1;
1065 }
1066 }
1067
1068 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1069 break;
1070 }
1071 default:
1072 assert(0);
1073 }
1074 }
1075
1076 static void si_build_shader_variant(void *job, int thread_index)
1077 {
1078 struct si_shader *shader = (struct si_shader *)job;
1079 struct si_shader_selector *sel = shader->selector;
1080 struct si_screen *sscreen = sel->screen;
1081 LLVMTargetMachineRef tm;
1082 struct pipe_debug_callback *debug = &sel->debug;
1083 int r;
1084
1085 if (thread_index >= 0) {
1086 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1087 tm = sscreen->tm[thread_index];
1088 if (!debug->async)
1089 debug = NULL;
1090 } else {
1091 tm = sel->tm;
1092 }
1093
1094 r = si_shader_create(sscreen, tm, shader, debug);
1095 if (unlikely(r)) {
1096 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1097 sel->type, r);
1098 shader->compilation_failed = true;
1099 return;
1100 }
1101
1102 if (sel->is_debug_context) {
1103 FILE *f = open_memstream(&shader->shader_log,
1104 &shader->shader_log_size);
1105 if (f) {
1106 si_shader_dump(sscreen, shader, NULL, sel->type, f);
1107 fclose(f);
1108 }
1109 }
1110
1111 si_shader_init_pm4_state(sscreen, shader);
1112 }
1113
1114 /* Select the hw shader variant depending on the current state. */
1115 static int si_shader_select_with_key(struct si_screen *sscreen,
1116 struct si_shader_ctx_state *state,
1117 struct si_shader_key *key,
1118 int thread_index)
1119 {
1120 static const struct si_shader_key zeroed;
1121 struct si_shader_selector *sel = state->cso;
1122 struct si_shader *current = state->current;
1123 struct si_shader *iter, *shader = NULL;
1124
1125 if (unlikely(sscreen->b.chip_class & DBG_NO_OPT_VARIANT)) {
1126 memset(&key->opt, 0, sizeof(key->opt));
1127 }
1128
1129 again:
1130 /* Check if we don't need to change anything.
1131 * This path is also used for most shaders that don't need multiple
1132 * variants, it will cost just a computation of the key and this
1133 * test. */
1134 if (likely(current &&
1135 memcmp(&current->key, key, sizeof(*key)) == 0 &&
1136 (!current->is_optimized ||
1137 util_queue_fence_is_signalled(&current->optimized_ready))))
1138 return 0;
1139
1140 /* This must be done before the mutex is locked, because async GS
1141 * compilation calls this function too, and therefore must enter
1142 * the mutex first.
1143 *
1144 * Only wait if we are in a draw call. Don't wait if we are
1145 * in a compiler thread.
1146 */
1147 if (thread_index < 0)
1148 util_queue_job_wait(&sel->ready);
1149
1150 pipe_mutex_lock(sel->mutex);
1151
1152 /* Find the shader variant. */
1153 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1154 /* Don't check the "current" shader. We checked it above. */
1155 if (current != iter &&
1156 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1157 /* If it's an optimized shader and its compilation has
1158 * been started but isn't done, use the unoptimized
1159 * shader so as not to cause a stall due to compilation.
1160 */
1161 if (iter->is_optimized &&
1162 !util_queue_fence_is_signalled(&iter->optimized_ready)) {
1163 memset(&key->opt, 0, sizeof(key->opt));
1164 pipe_mutex_unlock(sel->mutex);
1165 goto again;
1166 }
1167
1168 if (iter->compilation_failed) {
1169 pipe_mutex_unlock(sel->mutex);
1170 return -1; /* skip the draw call */
1171 }
1172
1173 state->current = iter;
1174 pipe_mutex_unlock(sel->mutex);
1175 return 0;
1176 }
1177 }
1178
1179 /* Build a new shader. */
1180 shader = CALLOC_STRUCT(si_shader);
1181 if (!shader) {
1182 pipe_mutex_unlock(sel->mutex);
1183 return -ENOMEM;
1184 }
1185 shader->selector = sel;
1186 shader->key = *key;
1187
1188 /* Monolithic-only shaders don't make a distinction between optimized
1189 * and unoptimized. */
1190 shader->is_monolithic =
1191 !sel->main_shader_part ||
1192 sel->main_shader_part->key.as_ls != key->as_ls ||
1193 sel->main_shader_part->key.as_es != key->as_es ||
1194 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0 ||
1195 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1196
1197 shader->is_optimized =
1198 !sscreen->use_monolithic_shaders &&
1199 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1200 if (shader->is_optimized)
1201 util_queue_fence_init(&shader->optimized_ready);
1202
1203 if (!sel->last_variant) {
1204 sel->first_variant = shader;
1205 sel->last_variant = shader;
1206 } else {
1207 sel->last_variant->next_variant = shader;
1208 sel->last_variant = shader;
1209 }
1210
1211 /* If it's an optimized shader, compile it asynchronously. */
1212 if (shader->is_optimized &&
1213 thread_index < 0) {
1214 /* Compile it asynchronously. */
1215 util_queue_add_job(&sscreen->shader_compiler_queue,
1216 shader, &shader->optimized_ready,
1217 si_build_shader_variant, NULL);
1218
1219 /* Use the default (unoptimized) shader for now. */
1220 memset(&key->opt, 0, sizeof(key->opt));
1221 pipe_mutex_unlock(sel->mutex);
1222 goto again;
1223 }
1224
1225 assert(!shader->is_optimized);
1226 si_build_shader_variant(shader, thread_index);
1227
1228 if (!shader->compilation_failed)
1229 state->current = shader;
1230
1231 pipe_mutex_unlock(sel->mutex);
1232 return shader->compilation_failed ? -1 : 0;
1233 }
1234
1235 static int si_shader_select(struct pipe_context *ctx,
1236 struct si_shader_ctx_state *state)
1237 {
1238 struct si_context *sctx = (struct si_context *)ctx;
1239 struct si_shader_key key;
1240
1241 si_shader_selector_key(ctx, state->cso, &key);
1242 return si_shader_select_with_key(sctx->screen, state, &key, -1);
1243 }
1244
1245 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1246 struct si_shader_key *key)
1247 {
1248 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1249
1250 switch (info->processor) {
1251 case PIPE_SHADER_VERTEX:
1252 switch (next_shader) {
1253 case PIPE_SHADER_GEOMETRY:
1254 key->as_es = 1;
1255 break;
1256 case PIPE_SHADER_TESS_CTRL:
1257 case PIPE_SHADER_TESS_EVAL:
1258 key->as_ls = 1;
1259 break;
1260 default:
1261 /* If POSITION isn't written, it can't be a HW VS.
1262 * Assume that it's a HW LS. (the next shader is TCS)
1263 * This heuristic is needed for separate shader objects.
1264 */
1265 if (!info->writes_position)
1266 key->as_ls = 1;
1267 }
1268 break;
1269
1270 case PIPE_SHADER_TESS_EVAL:
1271 if (next_shader == PIPE_SHADER_GEOMETRY)
1272 key->as_es = 1;
1273 break;
1274 }
1275 }
1276
1277 /**
1278 * Compile the main shader part or the monolithic shader as part of
1279 * si_shader_selector initialization. Since it can be done asynchronously,
1280 * there is no way to report compile failures to applications.
1281 */
1282 void si_init_shader_selector_async(void *job, int thread_index)
1283 {
1284 struct si_shader_selector *sel = (struct si_shader_selector *)job;
1285 struct si_screen *sscreen = sel->screen;
1286 LLVMTargetMachineRef tm;
1287 struct pipe_debug_callback *debug = &sel->debug;
1288 unsigned i;
1289
1290 if (thread_index >= 0) {
1291 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1292 tm = sscreen->tm[thread_index];
1293 if (!debug->async)
1294 debug = NULL;
1295 } else {
1296 tm = sel->tm;
1297 }
1298
1299 /* Compile the main shader part for use with a prolog and/or epilog.
1300 * If this fails, the driver will try to compile a monolithic shader
1301 * on demand.
1302 */
1303 if (!sscreen->use_monolithic_shaders) {
1304 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1305 void *tgsi_binary;
1306
1307 if (!shader) {
1308 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
1309 return;
1310 }
1311
1312 shader->selector = sel;
1313 si_parse_next_shader_property(&sel->info, &shader->key);
1314
1315 tgsi_binary = si_get_tgsi_binary(sel);
1316
1317 /* Try to load the shader from the shader cache. */
1318 pipe_mutex_lock(sscreen->shader_cache_mutex);
1319
1320 if (tgsi_binary &&
1321 si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
1322 FREE(tgsi_binary);
1323 pipe_mutex_unlock(sscreen->shader_cache_mutex);
1324 } else {
1325 pipe_mutex_unlock(sscreen->shader_cache_mutex);
1326
1327 /* Compile the shader if it hasn't been loaded from the cache. */
1328 if (si_compile_tgsi_shader(sscreen, tm, shader, false,
1329 debug) != 0) {
1330 FREE(shader);
1331 FREE(tgsi_binary);
1332 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
1333 return;
1334 }
1335
1336 if (tgsi_binary) {
1337 pipe_mutex_lock(sscreen->shader_cache_mutex);
1338 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary, shader))
1339 FREE(tgsi_binary);
1340 pipe_mutex_unlock(sscreen->shader_cache_mutex);
1341 }
1342 }
1343
1344 sel->main_shader_part = shader;
1345
1346 /* Unset "outputs_written" flags for outputs converted to
1347 * DEFAULT_VAL, so that later inter-shader optimizations don't
1348 * try to eliminate outputs that don't exist in the final
1349 * shader.
1350 *
1351 * This is only done if non-monolithic shaders are enabled.
1352 */
1353 if ((sel->type == PIPE_SHADER_VERTEX ||
1354 sel->type == PIPE_SHADER_TESS_EVAL) &&
1355 !shader->key.as_ls &&
1356 !shader->key.as_es) {
1357 unsigned i;
1358
1359 for (i = 0; i < sel->info.num_outputs; i++) {
1360 unsigned offset = shader->info.vs_output_param_offset[i];
1361
1362 if (offset <= EXP_PARAM_OFFSET_31)
1363 continue;
1364
1365 unsigned name = sel->info.output_semantic_name[i];
1366 unsigned index = sel->info.output_semantic_index[i];
1367 unsigned id;
1368
1369 switch (name) {
1370 case TGSI_SEMANTIC_GENERIC:
1371 /* don't process indices the function can't handle */
1372 if (index >= 60)
1373 break;
1374 /* fall through */
1375 case TGSI_SEMANTIC_CLIPDIST:
1376 id = si_shader_io_get_unique_index(name, index);
1377 sel->outputs_written &= ~(1ull << id);
1378 break;
1379 case TGSI_SEMANTIC_POSITION: /* ignore these */
1380 case TGSI_SEMANTIC_PSIZE:
1381 case TGSI_SEMANTIC_CLIPVERTEX:
1382 case TGSI_SEMANTIC_EDGEFLAG:
1383 break;
1384 default:
1385 id = si_shader_io_get_unique_index2(name, index);
1386 sel->outputs_written2 &= ~(1u << id);
1387 }
1388 }
1389 }
1390 }
1391
1392 /* Pre-compilation. */
1393 if (sscreen->b.debug_flags & DBG_PRECOMPILE) {
1394 struct si_shader_ctx_state state = {sel};
1395 struct si_shader_key key;
1396
1397 memset(&key, 0, sizeof(key));
1398 si_parse_next_shader_property(&sel->info, &key);
1399
1400 /* Set reasonable defaults, so that the shader key doesn't
1401 * cause any code to be eliminated.
1402 */
1403 switch (sel->type) {
1404 case PIPE_SHADER_TESS_CTRL:
1405 key.part.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
1406 break;
1407 case PIPE_SHADER_FRAGMENT:
1408 key.part.ps.prolog.bc_optimize_for_persp =
1409 sel->info.uses_persp_center &&
1410 sel->info.uses_persp_centroid;
1411 key.part.ps.prolog.bc_optimize_for_linear =
1412 sel->info.uses_linear_center &&
1413 sel->info.uses_linear_centroid;
1414 key.part.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
1415 for (i = 0; i < 8; i++)
1416 if (sel->info.colors_written & (1 << i))
1417 key.part.ps.epilog.spi_shader_col_format |=
1418 V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
1419 break;
1420 }
1421
1422 if (si_shader_select_with_key(sscreen, &state, &key, thread_index))
1423 fprintf(stderr, "radeonsi: can't create a monolithic shader\n");
1424 }
1425
1426 /* The GS copy shader is always pre-compiled. */
1427 if (sel->type == PIPE_SHADER_GEOMETRY) {
1428 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, tm, sel, debug);
1429 if (!sel->gs_copy_shader) {
1430 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
1431 return;
1432 }
1433
1434 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
1435 }
1436 }
1437
1438 static void *si_create_shader_selector(struct pipe_context *ctx,
1439 const struct pipe_shader_state *state)
1440 {
1441 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
1442 struct si_context *sctx = (struct si_context*)ctx;
1443 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
1444 int i;
1445
1446 if (!sel)
1447 return NULL;
1448
1449 sel->screen = sscreen;
1450 sel->tm = sctx->tm;
1451 sel->debug = sctx->b.debug;
1452 sel->is_debug_context = sctx->is_debug;
1453 sel->tokens = tgsi_dup_tokens(state->tokens);
1454 if (!sel->tokens) {
1455 FREE(sel);
1456 return NULL;
1457 }
1458
1459 sel->so = state->stream_output;
1460 tgsi_scan_shader(state->tokens, &sel->info);
1461 sel->type = sel->info.processor;
1462 p_atomic_inc(&sscreen->b.num_shaders_created);
1463
1464 /* Set which opcode uses which (i,j) pair. */
1465 if (sel->info.uses_persp_opcode_interp_centroid)
1466 sel->info.uses_persp_centroid = true;
1467
1468 if (sel->info.uses_linear_opcode_interp_centroid)
1469 sel->info.uses_linear_centroid = true;
1470
1471 if (sel->info.uses_persp_opcode_interp_offset ||
1472 sel->info.uses_persp_opcode_interp_sample)
1473 sel->info.uses_persp_center = true;
1474
1475 if (sel->info.uses_linear_opcode_interp_offset ||
1476 sel->info.uses_linear_opcode_interp_sample)
1477 sel->info.uses_linear_center = true;
1478
1479 switch (sel->type) {
1480 case PIPE_SHADER_GEOMETRY:
1481 sel->gs_output_prim =
1482 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
1483 sel->gs_max_out_vertices =
1484 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
1485 sel->gs_num_invocations =
1486 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
1487 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
1488 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
1489 sel->gs_max_out_vertices;
1490
1491 sel->max_gs_stream = 0;
1492 for (i = 0; i < sel->so.num_outputs; i++)
1493 sel->max_gs_stream = MAX2(sel->max_gs_stream,
1494 sel->so.output[i].stream);
1495
1496 sel->gs_input_verts_per_prim =
1497 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
1498 break;
1499
1500 case PIPE_SHADER_TESS_CTRL:
1501 /* Always reserve space for these. */
1502 sel->patch_outputs_written |=
1503 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0)) |
1504 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0));
1505 /* fall through */
1506 case PIPE_SHADER_VERTEX:
1507 case PIPE_SHADER_TESS_EVAL:
1508 for (i = 0; i < sel->info.num_outputs; i++) {
1509 unsigned name = sel->info.output_semantic_name[i];
1510 unsigned index = sel->info.output_semantic_index[i];
1511
1512 switch (name) {
1513 case TGSI_SEMANTIC_TESSINNER:
1514 case TGSI_SEMANTIC_TESSOUTER:
1515 case TGSI_SEMANTIC_PATCH:
1516 sel->patch_outputs_written |=
1517 1llu << si_shader_io_get_unique_index(name, index);
1518 break;
1519
1520 case TGSI_SEMANTIC_GENERIC:
1521 /* don't process indices the function can't handle */
1522 if (index >= 60)
1523 break;
1524 /* fall through */
1525 case TGSI_SEMANTIC_POSITION:
1526 case TGSI_SEMANTIC_PSIZE:
1527 case TGSI_SEMANTIC_CLIPDIST:
1528 sel->outputs_written |=
1529 1llu << si_shader_io_get_unique_index(name, index);
1530 break;
1531 case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */
1532 case TGSI_SEMANTIC_EDGEFLAG:
1533 break;
1534 default:
1535 sel->outputs_written2 |=
1536 1u << si_shader_io_get_unique_index2(name, index);
1537 }
1538 }
1539 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
1540 break;
1541
1542 case PIPE_SHADER_FRAGMENT:
1543 for (i = 0; i < sel->info.num_inputs; i++) {
1544 unsigned name = sel->info.input_semantic_name[i];
1545 unsigned index = sel->info.input_semantic_index[i];
1546
1547 switch (name) {
1548 case TGSI_SEMANTIC_CLIPDIST:
1549 case TGSI_SEMANTIC_GENERIC:
1550 sel->inputs_read |=
1551 1llu << si_shader_io_get_unique_index(name, index);
1552 break;
1553 case TGSI_SEMANTIC_PCOORD: /* ignore this */
1554 break;
1555 default:
1556 sel->inputs_read2 |=
1557 1u << si_shader_io_get_unique_index2(name, index);
1558 }
1559 }
1560
1561 for (i = 0; i < 8; i++)
1562 if (sel->info.colors_written & (1 << i))
1563 sel->colors_written_4bit |= 0xf << (4 * i);
1564
1565 for (i = 0; i < sel->info.num_inputs; i++) {
1566 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
1567 int index = sel->info.input_semantic_index[i];
1568 sel->color_attr_index[index] = i;
1569 }
1570 }
1571 break;
1572 }
1573
1574 /* DB_SHADER_CONTROL */
1575 sel->db_shader_control =
1576 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
1577 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
1578 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
1579 S_02880C_KILL_ENABLE(sel->info.uses_kill);
1580
1581 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
1582 case TGSI_FS_DEPTH_LAYOUT_GREATER:
1583 sel->db_shader_control |=
1584 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
1585 break;
1586 case TGSI_FS_DEPTH_LAYOUT_LESS:
1587 sel->db_shader_control |=
1588 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
1589 break;
1590 }
1591
1592 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
1593 *
1594 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
1595 * --|-----------|------------|------------|--------------------|-------------------|-------------
1596 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
1597 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
1598 * 2 | false | true | n/a | LateZ | 1 | 0
1599 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
1600 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
1601 *
1602 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
1603 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
1604 *
1605 * Don't use ReZ without profiling !!!
1606 *
1607 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
1608 * shaders.
1609 */
1610 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
1611 /* Cases 3, 4. */
1612 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
1613 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
1614 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
1615 } else if (sel->info.writes_memory) {
1616 /* Case 2. */
1617 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
1618 S_02880C_EXEC_ON_HIER_FAIL(1);
1619 } else {
1620 /* Case 1. */
1621 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
1622 }
1623
1624 pipe_mutex_init(sel->mutex);
1625 util_queue_fence_init(&sel->ready);
1626
1627 if ((sctx->b.debug.debug_message && !sctx->b.debug.async) ||
1628 sctx->is_debug ||
1629 r600_can_dump_shader(&sscreen->b, sel->info.processor) ||
1630 !util_queue_is_initialized(&sscreen->shader_compiler_queue))
1631 si_init_shader_selector_async(sel, -1);
1632 else
1633 util_queue_add_job(&sscreen->shader_compiler_queue, sel,
1634 &sel->ready, si_init_shader_selector_async,
1635 NULL);
1636
1637 return sel;
1638 }
1639
1640 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
1641 {
1642 struct si_context *sctx = (struct si_context *)ctx;
1643 struct si_shader_selector *sel = state;
1644
1645 if (sctx->vs_shader.cso == sel)
1646 return;
1647
1648 sctx->vs_shader.cso = sel;
1649 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
1650 sctx->do_update_shaders = true;
1651 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1652 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1653 }
1654
1655 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
1656 {
1657 struct si_context *sctx = (struct si_context *)ctx;
1658 struct si_shader_selector *sel = state;
1659 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
1660
1661 if (sctx->gs_shader.cso == sel)
1662 return;
1663
1664 sctx->gs_shader.cso = sel;
1665 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
1666 sctx->do_update_shaders = true;
1667 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1668 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1669
1670 if (enable_changed)
1671 si_shader_change_notify(sctx);
1672 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1673 }
1674
1675 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
1676 {
1677 struct si_context *sctx = (struct si_context *)ctx;
1678 struct si_shader_selector *sel = state;
1679 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
1680
1681 if (sctx->tcs_shader.cso == sel)
1682 return;
1683
1684 sctx->tcs_shader.cso = sel;
1685 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
1686 sctx->do_update_shaders = true;
1687
1688 if (enable_changed)
1689 sctx->last_tcs = NULL; /* invalidate derived tess state */
1690 }
1691
1692 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
1693 {
1694 struct si_context *sctx = (struct si_context *)ctx;
1695 struct si_shader_selector *sel = state;
1696 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
1697
1698 if (sctx->tes_shader.cso == sel)
1699 return;
1700
1701 sctx->tes_shader.cso = sel;
1702 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
1703 sctx->do_update_shaders = true;
1704 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1705 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1706
1707 if (enable_changed) {
1708 si_shader_change_notify(sctx);
1709 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
1710 }
1711 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1712 }
1713
1714 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
1715 {
1716 struct si_context *sctx = (struct si_context *)ctx;
1717 struct si_shader_selector *sel = state;
1718
1719 /* skip if supplied shader is one already in use */
1720 if (sctx->ps_shader.cso == sel)
1721 return;
1722
1723 sctx->ps_shader.cso = sel;
1724 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
1725 sctx->do_update_shaders = true;
1726 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
1727 }
1728
1729 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
1730 {
1731 if (shader->is_optimized) {
1732 util_queue_job_wait(&shader->optimized_ready);
1733 util_queue_fence_destroy(&shader->optimized_ready);
1734 }
1735
1736 if (shader->pm4) {
1737 switch (shader->selector->type) {
1738 case PIPE_SHADER_VERTEX:
1739 if (shader->key.as_ls)
1740 si_pm4_delete_state(sctx, ls, shader->pm4);
1741 else if (shader->key.as_es)
1742 si_pm4_delete_state(sctx, es, shader->pm4);
1743 else
1744 si_pm4_delete_state(sctx, vs, shader->pm4);
1745 break;
1746 case PIPE_SHADER_TESS_CTRL:
1747 si_pm4_delete_state(sctx, hs, shader->pm4);
1748 break;
1749 case PIPE_SHADER_TESS_EVAL:
1750 if (shader->key.as_es)
1751 si_pm4_delete_state(sctx, es, shader->pm4);
1752 else
1753 si_pm4_delete_state(sctx, vs, shader->pm4);
1754 break;
1755 case PIPE_SHADER_GEOMETRY:
1756 if (shader->is_gs_copy_shader)
1757 si_pm4_delete_state(sctx, vs, shader->pm4);
1758 else
1759 si_pm4_delete_state(sctx, gs, shader->pm4);
1760 break;
1761 case PIPE_SHADER_FRAGMENT:
1762 si_pm4_delete_state(sctx, ps, shader->pm4);
1763 break;
1764 }
1765 }
1766
1767 si_shader_destroy(shader);
1768 free(shader);
1769 }
1770
1771 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
1772 {
1773 struct si_context *sctx = (struct si_context *)ctx;
1774 struct si_shader_selector *sel = (struct si_shader_selector *)state;
1775 struct si_shader *p = sel->first_variant, *c;
1776 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
1777 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
1778 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
1779 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
1780 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
1781 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
1782 };
1783
1784 util_queue_job_wait(&sel->ready);
1785
1786 if (current_shader[sel->type]->cso == sel) {
1787 current_shader[sel->type]->cso = NULL;
1788 current_shader[sel->type]->current = NULL;
1789 }
1790
1791 while (p) {
1792 c = p->next_variant;
1793 si_delete_shader(sctx, p);
1794 p = c;
1795 }
1796
1797 if (sel->main_shader_part)
1798 si_delete_shader(sctx, sel->main_shader_part);
1799 if (sel->gs_copy_shader)
1800 si_delete_shader(sctx, sel->gs_copy_shader);
1801
1802 util_queue_fence_destroy(&sel->ready);
1803 pipe_mutex_destroy(sel->mutex);
1804 free(sel->tokens);
1805 free(sel);
1806 }
1807
1808 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
1809 struct si_shader *vs, unsigned name,
1810 unsigned index, unsigned interpolate)
1811 {
1812 struct tgsi_shader_info *vsinfo = &vs->selector->info;
1813 unsigned j, offset, ps_input_cntl = 0;
1814
1815 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
1816 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
1817 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1818
1819 if (name == TGSI_SEMANTIC_PCOORD ||
1820 (name == TGSI_SEMANTIC_TEXCOORD &&
1821 sctx->sprite_coord_enable & (1 << index))) {
1822 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
1823 }
1824
1825 for (j = 0; j < vsinfo->num_outputs; j++) {
1826 if (name == vsinfo->output_semantic_name[j] &&
1827 index == vsinfo->output_semantic_index[j]) {
1828 offset = vs->info.vs_output_param_offset[j];
1829
1830 if (offset <= EXP_PARAM_OFFSET_31) {
1831 /* The input is loaded from parameter memory. */
1832 ps_input_cntl |= S_028644_OFFSET(offset);
1833 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
1834 if (offset == EXP_PARAM_UNDEFINED) {
1835 /* This can happen with depth-only rendering. */
1836 offset = 0;
1837 } else {
1838 /* The input is a DEFAULT_VAL constant. */
1839 assert(offset >= EXP_PARAM_DEFAULT_VAL_0000 &&
1840 offset <= EXP_PARAM_DEFAULT_VAL_1111);
1841 offset -= EXP_PARAM_DEFAULT_VAL_0000;
1842 }
1843
1844 ps_input_cntl = S_028644_OFFSET(0x20) |
1845 S_028644_DEFAULT_VAL(offset);
1846 }
1847 break;
1848 }
1849 }
1850
1851 if (name == TGSI_SEMANTIC_PRIMID)
1852 /* PrimID is written after the last output. */
1853 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
1854 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
1855 /* No corresponding output found, load defaults into input.
1856 * Don't set any other bits.
1857 * (FLAT_SHADE=1 completely changes behavior) */
1858 ps_input_cntl = S_028644_OFFSET(0x20);
1859 /* D3D 9 behaviour. GL is undefined */
1860 if (name == TGSI_SEMANTIC_COLOR && index == 0)
1861 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
1862 }
1863 return ps_input_cntl;
1864 }
1865
1866 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
1867 {
1868 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1869 struct si_shader *ps = sctx->ps_shader.current;
1870 struct si_shader *vs = si_get_vs_state(sctx);
1871 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
1872 unsigned i, num_interp, num_written = 0, bcol_interp[2];
1873
1874 if (!ps || !ps->selector->info.num_inputs)
1875 return;
1876
1877 num_interp = si_get_ps_num_interp(ps);
1878 assert(num_interp > 0);
1879 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
1880
1881 for (i = 0; i < psinfo->num_inputs; i++) {
1882 unsigned name = psinfo->input_semantic_name[i];
1883 unsigned index = psinfo->input_semantic_index[i];
1884 unsigned interpolate = psinfo->input_interpolate[i];
1885
1886 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
1887 interpolate));
1888 num_written++;
1889
1890 if (name == TGSI_SEMANTIC_COLOR) {
1891 assert(index < ARRAY_SIZE(bcol_interp));
1892 bcol_interp[index] = interpolate;
1893 }
1894 }
1895
1896 if (ps->key.part.ps.prolog.color_two_side) {
1897 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
1898
1899 for (i = 0; i < 2; i++) {
1900 if (!(psinfo->colors_read & (0xf << (i * 4))))
1901 continue;
1902
1903 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
1904 i, bcol_interp[i]));
1905 num_written++;
1906 }
1907 }
1908 assert(num_interp == num_written);
1909 }
1910
1911 /**
1912 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
1913 */
1914 static void si_init_config_add_vgt_flush(struct si_context *sctx)
1915 {
1916 if (sctx->init_config_has_vgt_flush)
1917 return;
1918
1919 /* Done by Vulkan before VGT_FLUSH. */
1920 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
1921 si_pm4_cmd_add(sctx->init_config,
1922 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1923 si_pm4_cmd_end(sctx->init_config, false);
1924
1925 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
1926 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
1927 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1928 si_pm4_cmd_end(sctx->init_config, false);
1929 sctx->init_config_has_vgt_flush = true;
1930 }
1931
1932 /* Initialize state related to ESGS / GSVS ring buffers */
1933 static bool si_update_gs_ring_buffers(struct si_context *sctx)
1934 {
1935 struct si_shader_selector *es =
1936 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
1937 struct si_shader_selector *gs = sctx->gs_shader.cso;
1938 struct si_pm4_state *pm4;
1939
1940 /* Chip constants. */
1941 unsigned num_se = sctx->screen->b.info.max_se;
1942 unsigned wave_size = 64;
1943 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1944 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1945 unsigned alignment = 256 * num_se;
1946 /* The maximum size is 63.999 MB per SE. */
1947 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1948
1949 /* Calculate the minimum size. */
1950 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
1951 wave_size, alignment);
1952
1953 /* These are recommended sizes, not minimum sizes. */
1954 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1955 es->esgs_itemsize * gs->gs_input_verts_per_prim;
1956 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1957 gs->max_gsvs_emit_size * (gs->max_gs_stream + 1);
1958
1959 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1960 esgs_ring_size = align(esgs_ring_size, alignment);
1961 gsvs_ring_size = align(gsvs_ring_size, alignment);
1962
1963 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1964 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1965
1966 /* Some rings don't have to be allocated if shaders don't use them.
1967 * (e.g. no varyings between ES and GS or GS and VS)
1968 */
1969 bool update_esgs = esgs_ring_size &&
1970 (!sctx->esgs_ring ||
1971 sctx->esgs_ring->width0 < esgs_ring_size);
1972 bool update_gsvs = gsvs_ring_size &&
1973 (!sctx->gsvs_ring ||
1974 sctx->gsvs_ring->width0 < gsvs_ring_size);
1975
1976 if (!update_esgs && !update_gsvs)
1977 return true;
1978
1979 if (update_esgs) {
1980 pipe_resource_reference(&sctx->esgs_ring, NULL);
1981 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, 0,
1982 PIPE_USAGE_DEFAULT,
1983 esgs_ring_size);
1984 if (!sctx->esgs_ring)
1985 return false;
1986 }
1987
1988 if (update_gsvs) {
1989 pipe_resource_reference(&sctx->gsvs_ring, NULL);
1990 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, 0,
1991 PIPE_USAGE_DEFAULT,
1992 gsvs_ring_size);
1993 if (!sctx->gsvs_ring)
1994 return false;
1995 }
1996
1997 /* Create the "init_config_gs_rings" state. */
1998 pm4 = CALLOC_STRUCT(si_pm4_state);
1999 if (!pm4)
2000 return false;
2001
2002 if (sctx->b.chip_class >= CIK) {
2003 if (sctx->esgs_ring)
2004 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2005 sctx->esgs_ring->width0 / 256);
2006 if (sctx->gsvs_ring)
2007 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2008 sctx->gsvs_ring->width0 / 256);
2009 } else {
2010 if (sctx->esgs_ring)
2011 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2012 sctx->esgs_ring->width0 / 256);
2013 if (sctx->gsvs_ring)
2014 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2015 sctx->gsvs_ring->width0 / 256);
2016 }
2017
2018 /* Set the state. */
2019 if (sctx->init_config_gs_rings)
2020 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
2021 sctx->init_config_gs_rings = pm4;
2022
2023 if (!sctx->init_config_has_vgt_flush) {
2024 si_init_config_add_vgt_flush(sctx);
2025 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2026 }
2027
2028 /* Flush the context to re-emit both init_config states. */
2029 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2030 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2031
2032 /* Set ring bindings. */
2033 if (sctx->esgs_ring) {
2034 si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
2035 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2036 true, true, 4, 64, 0);
2037 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
2038 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2039 false, false, 0, 0, 0);
2040 }
2041 if (sctx->gsvs_ring) {
2042 si_set_ring_buffer(&sctx->b.b, SI_VS_RING_GSVS,
2043 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
2044 false, false, 0, 0, 0);
2045
2046 /* Also update SI_GS_RING_GSVSi descriptors. */
2047 sctx->last_gsvs_itemsize = 0;
2048 }
2049
2050 return true;
2051 }
2052
2053 static void si_update_gsvs_ring_bindings(struct si_context *sctx)
2054 {
2055 unsigned gsvs_itemsize = sctx->gs_shader.cso->max_gsvs_emit_size;
2056 uint64_t offset;
2057
2058 if (!sctx->gsvs_ring || gsvs_itemsize == sctx->last_gsvs_itemsize)
2059 return;
2060
2061 sctx->last_gsvs_itemsize = gsvs_itemsize;
2062
2063 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS0,
2064 sctx->gsvs_ring, gsvs_itemsize,
2065 64, true, true, 4, 16, 0);
2066
2067 offset = gsvs_itemsize * 64;
2068 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS1,
2069 sctx->gsvs_ring, gsvs_itemsize,
2070 64, true, true, 4, 16, offset);
2071
2072 offset = (gsvs_itemsize * 2) * 64;
2073 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS2,
2074 sctx->gsvs_ring, gsvs_itemsize,
2075 64, true, true, 4, 16, offset);
2076
2077 offset = (gsvs_itemsize * 3) * 64;
2078 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS3,
2079 sctx->gsvs_ring, gsvs_itemsize,
2080 64, true, true, 4, 16, offset);
2081 }
2082
2083 /**
2084 * @returns 1 if \p sel has been updated to use a new scratch buffer
2085 * 0 if not
2086 * < 0 if there was a failure
2087 */
2088 static int si_update_scratch_buffer(struct si_context *sctx,
2089 struct si_shader *shader)
2090 {
2091 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
2092 int r;
2093
2094 if (!shader)
2095 return 0;
2096
2097 /* This shader doesn't need a scratch buffer */
2098 if (shader->config.scratch_bytes_per_wave == 0)
2099 return 0;
2100
2101 /* This shader is already configured to use the current
2102 * scratch buffer. */
2103 if (shader->scratch_bo == sctx->scratch_buffer)
2104 return 0;
2105
2106 assert(sctx->scratch_buffer);
2107
2108 si_shader_apply_scratch_relocs(sctx, shader, &shader->config, scratch_va);
2109
2110 /* Replace the shader bo with a new bo that has the relocs applied. */
2111 r = si_shader_binary_upload(sctx->screen, shader);
2112 if (r)
2113 return r;
2114
2115 /* Update the shader state to use the new shader bo. */
2116 si_shader_init_pm4_state(sctx->screen, shader);
2117
2118 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
2119
2120 return 1;
2121 }
2122
2123 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
2124 {
2125 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
2126 }
2127
2128 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
2129 {
2130 return shader ? shader->config.scratch_bytes_per_wave : 0;
2131 }
2132
2133 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
2134 {
2135 unsigned bytes = 0;
2136
2137 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
2138 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
2139 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
2140 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tcs_shader.current));
2141 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
2142 return bytes;
2143 }
2144
2145 static bool si_update_spi_tmpring_size(struct si_context *sctx)
2146 {
2147 unsigned current_scratch_buffer_size =
2148 si_get_current_scratch_buffer_size(sctx);
2149 unsigned scratch_bytes_per_wave =
2150 si_get_max_scratch_bytes_per_wave(sctx);
2151 unsigned scratch_needed_size = scratch_bytes_per_wave *
2152 sctx->scratch_waves;
2153 unsigned spi_tmpring_size;
2154 int r;
2155
2156 if (scratch_needed_size > 0) {
2157 if (scratch_needed_size > current_scratch_buffer_size) {
2158 /* Create a bigger scratch buffer */
2159 r600_resource_reference(&sctx->scratch_buffer, NULL);
2160
2161 sctx->scratch_buffer = (struct r600_resource*)
2162 pipe_buffer_create(&sctx->screen->b.b, 0,
2163 PIPE_USAGE_DEFAULT, scratch_needed_size);
2164 if (!sctx->scratch_buffer)
2165 return false;
2166 sctx->emit_scratch_reloc = true;
2167 }
2168
2169 /* Update the shaders, so they are using the latest scratch. The
2170 * scratch buffer may have been changed since these shaders were
2171 * last used, so we still need to try to update them, even if
2172 * they require scratch buffers smaller than the current size.
2173 */
2174 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
2175 if (r < 0)
2176 return false;
2177 if (r == 1)
2178 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2179
2180 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
2181 if (r < 0)
2182 return false;
2183 if (r == 1)
2184 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2185
2186 r = si_update_scratch_buffer(sctx, sctx->tcs_shader.current);
2187 if (r < 0)
2188 return false;
2189 if (r == 1)
2190 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
2191
2192 /* VS can be bound as LS, ES, or VS. */
2193 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
2194 if (r < 0)
2195 return false;
2196 if (r == 1) {
2197 if (sctx->tes_shader.current)
2198 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2199 else if (sctx->gs_shader.current)
2200 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2201 else
2202 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2203 }
2204
2205 /* TES can be bound as ES or VS. */
2206 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
2207 if (r < 0)
2208 return false;
2209 if (r == 1) {
2210 if (sctx->gs_shader.current)
2211 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2212 else
2213 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2214 }
2215 }
2216
2217 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
2218 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
2219 "scratch size should already be aligned correctly.");
2220
2221 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
2222 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
2223 if (spi_tmpring_size != sctx->spi_tmpring_size) {
2224 sctx->spi_tmpring_size = spi_tmpring_size;
2225 sctx->emit_scratch_reloc = true;
2226 }
2227 return true;
2228 }
2229
2230 static void si_init_tess_factor_ring(struct si_context *sctx)
2231 {
2232 bool double_offchip_buffers = sctx->b.chip_class >= CIK;
2233 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2234 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
2235 sctx->screen->b.info.max_se;
2236 unsigned offchip_granularity;
2237
2238 switch (sctx->screen->tess_offchip_block_dw_size) {
2239 default:
2240 assert(0);
2241 /* fall through */
2242 case 8192:
2243 offchip_granularity = V_03093C_X_8K_DWORDS;
2244 break;
2245 case 4096:
2246 offchip_granularity = V_03093C_X_4K_DWORDS;
2247 break;
2248 }
2249
2250 switch (sctx->b.chip_class) {
2251 case SI:
2252 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2253 break;
2254 case CIK:
2255 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2256 break;
2257 case VI:
2258 default:
2259 max_offchip_buffers = MIN2(max_offchip_buffers, 512);
2260 break;
2261 }
2262
2263 assert(!sctx->tf_ring);
2264 sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, 0,
2265 PIPE_USAGE_DEFAULT,
2266 32768 * sctx->screen->b.info.max_se);
2267 if (!sctx->tf_ring)
2268 return;
2269
2270 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
2271
2272 sctx->tess_offchip_ring = pipe_buffer_create(sctx->b.b.screen, 0,
2273 PIPE_USAGE_DEFAULT,
2274 max_offchip_buffers *
2275 sctx->screen->tess_offchip_block_dw_size * 4);
2276 if (!sctx->tess_offchip_ring)
2277 return;
2278
2279 si_init_config_add_vgt_flush(sctx);
2280
2281 /* Append these registers to the init config state. */
2282 if (sctx->b.chip_class >= CIK) {
2283 if (sctx->b.chip_class >= VI)
2284 --max_offchip_buffers;
2285
2286 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
2287 S_030938_SIZE(sctx->tf_ring->width0 / 4));
2288 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
2289 r600_resource(sctx->tf_ring)->gpu_address >> 8);
2290 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
2291 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2292 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity));
2293 } else {
2294 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
2295 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
2296 S_008988_SIZE(sctx->tf_ring->width0 / 4));
2297 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
2298 r600_resource(sctx->tf_ring)->gpu_address >> 8);
2299 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2300 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers));
2301 }
2302
2303 /* Flush the context to re-emit the init_config state.
2304 * This is done only once in a lifetime of a context.
2305 */
2306 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2307 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2308 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2309
2310 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_FACTOR, sctx->tf_ring,
2311 0, sctx->tf_ring->width0, false, false, 0, 0, 0);
2312
2313 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_OFFCHIP,
2314 sctx->tess_offchip_ring, 0,
2315 sctx->tess_offchip_ring->width0, false, false, 0, 0, 0);
2316 }
2317
2318 /**
2319 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
2320 * VS passes its outputs to TES directly, so the fixed-function shader only
2321 * has to write TESSOUTER and TESSINNER.
2322 */
2323 static void si_generate_fixed_func_tcs(struct si_context *sctx)
2324 {
2325 struct ureg_src outer, inner;
2326 struct ureg_dst tessouter, tessinner;
2327 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
2328
2329 if (!ureg)
2330 return; /* if we get here, we're screwed */
2331
2332 assert(!sctx->fixed_func_tcs_shader.cso);
2333
2334 outer = ureg_DECL_system_value(ureg,
2335 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
2336 inner = ureg_DECL_system_value(ureg,
2337 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
2338
2339 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
2340 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
2341
2342 ureg_MOV(ureg, tessouter, outer);
2343 ureg_MOV(ureg, tessinner, inner);
2344 ureg_END(ureg);
2345
2346 sctx->fixed_func_tcs_shader.cso =
2347 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
2348 }
2349
2350 static void si_update_vgt_shader_config(struct si_context *sctx)
2351 {
2352 /* Calculate the index of the config.
2353 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
2354 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
2355 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
2356
2357 if (!*pm4) {
2358 uint32_t stages = 0;
2359
2360 *pm4 = CALLOC_STRUCT(si_pm4_state);
2361
2362 if (sctx->tes_shader.cso) {
2363 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2364 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2365
2366 if (sctx->gs_shader.cso)
2367 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2368 S_028B54_GS_EN(1) |
2369 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2370 else
2371 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2372 } else if (sctx->gs_shader.cso) {
2373 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2374 S_028B54_GS_EN(1) |
2375 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2376 }
2377
2378 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
2379 }
2380 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
2381 }
2382
2383 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
2384 {
2385 struct pipe_stream_output_info *so = &shader->so;
2386 uint32_t enabled_stream_buffers_mask = 0;
2387 int i;
2388
2389 for (i = 0; i < so->num_outputs; i++)
2390 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
2391 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
2392 sctx->b.streamout.stride_in_dw = shader->so.stride;
2393 }
2394
2395 bool si_update_shaders(struct si_context *sctx)
2396 {
2397 struct pipe_context *ctx = (struct pipe_context*)sctx;
2398 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2399 int r;
2400
2401 /* Update stages before GS. */
2402 if (sctx->tes_shader.cso) {
2403 if (!sctx->tf_ring) {
2404 si_init_tess_factor_ring(sctx);
2405 if (!sctx->tf_ring)
2406 return false;
2407 }
2408
2409 /* VS as LS */
2410 r = si_shader_select(ctx, &sctx->vs_shader);
2411 if (r)
2412 return false;
2413 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2414
2415 if (sctx->tcs_shader.cso) {
2416 r = si_shader_select(ctx, &sctx->tcs_shader);
2417 if (r)
2418 return false;
2419 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
2420 } else {
2421 if (!sctx->fixed_func_tcs_shader.cso) {
2422 si_generate_fixed_func_tcs(sctx);
2423 if (!sctx->fixed_func_tcs_shader.cso)
2424 return false;
2425 }
2426
2427 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader);
2428 if (r)
2429 return false;
2430 si_pm4_bind_state(sctx, hs,
2431 sctx->fixed_func_tcs_shader.current->pm4);
2432 }
2433
2434 r = si_shader_select(ctx, &sctx->tes_shader);
2435 if (r)
2436 return false;
2437
2438 if (sctx->gs_shader.cso) {
2439 /* TES as ES */
2440 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2441 } else {
2442 /* TES as VS */
2443 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2444 si_update_so(sctx, sctx->tes_shader.cso);
2445 }
2446 } else if (sctx->gs_shader.cso) {
2447 /* VS as ES */
2448 r = si_shader_select(ctx, &sctx->vs_shader);
2449 if (r)
2450 return false;
2451 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2452 } else {
2453 /* VS as VS */
2454 r = si_shader_select(ctx, &sctx->vs_shader);
2455 if (r)
2456 return false;
2457 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2458 si_update_so(sctx, sctx->vs_shader.cso);
2459 }
2460
2461 /* Update GS. */
2462 if (sctx->gs_shader.cso) {
2463 r = si_shader_select(ctx, &sctx->gs_shader);
2464 if (r)
2465 return false;
2466 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2467 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
2468 si_update_so(sctx, sctx->gs_shader.cso);
2469
2470 if (!si_update_gs_ring_buffers(sctx))
2471 return false;
2472
2473 si_update_gsvs_ring_bindings(sctx);
2474 } else {
2475 si_pm4_bind_state(sctx, gs, NULL);
2476 si_pm4_bind_state(sctx, es, NULL);
2477 }
2478
2479 si_update_vgt_shader_config(sctx);
2480
2481 if (sctx->ps_shader.cso) {
2482 unsigned db_shader_control;
2483
2484 r = si_shader_select(ctx, &sctx->ps_shader);
2485 if (r)
2486 return false;
2487 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2488
2489 db_shader_control =
2490 sctx->ps_shader.cso->db_shader_control |
2491 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
2492
2493 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
2494 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
2495 sctx->flatshade != rs->flatshade) {
2496 sctx->sprite_coord_enable = rs->sprite_coord_enable;
2497 sctx->flatshade = rs->flatshade;
2498 si_mark_atom_dirty(sctx, &sctx->spi_map);
2499 }
2500
2501 if (sctx->b.family == CHIP_STONEY && si_pm4_state_changed(sctx, ps))
2502 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2503
2504 if (sctx->ps_db_shader_control != db_shader_control) {
2505 sctx->ps_db_shader_control = db_shader_control;
2506 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2507 }
2508
2509 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
2510 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
2511 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2512
2513 if (sctx->b.chip_class == SI)
2514 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2515
2516 if (sctx->framebuffer.nr_samples <= 1)
2517 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2518 }
2519 }
2520
2521 if (si_pm4_state_changed(sctx, ls) ||
2522 si_pm4_state_changed(sctx, hs) ||
2523 si_pm4_state_changed(sctx, es) ||
2524 si_pm4_state_changed(sctx, gs) ||
2525 si_pm4_state_changed(sctx, vs) ||
2526 si_pm4_state_changed(sctx, ps)) {
2527 if (!si_update_spi_tmpring_size(sctx))
2528 return false;
2529 }
2530
2531 sctx->do_update_shaders = false;
2532 return true;
2533 }
2534
2535 void si_init_shader_functions(struct si_context *sctx)
2536 {
2537 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
2538
2539 sctx->b.b.create_vs_state = si_create_shader_selector;
2540 sctx->b.b.create_tcs_state = si_create_shader_selector;
2541 sctx->b.b.create_tes_state = si_create_shader_selector;
2542 sctx->b.b.create_gs_state = si_create_shader_selector;
2543 sctx->b.b.create_fs_state = si_create_shader_selector;
2544
2545 sctx->b.b.bind_vs_state = si_bind_vs_shader;
2546 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
2547 sctx->b.b.bind_tes_state = si_bind_tes_shader;
2548 sctx->b.b.bind_gs_state = si_bind_gs_shader;
2549 sctx->b.b.bind_fs_state = si_bind_ps_shader;
2550
2551 sctx->b.b.delete_vs_state = si_delete_shader_selector;
2552 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
2553 sctx->b.b.delete_tes_state = si_delete_shader_selector;
2554 sctx->b.b.delete_gs_state = si_delete_shader_selector;
2555 sctx->b.b.delete_fs_state = si_delete_shader_selector;
2556 }