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Merge ../mesa into vulkan
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "si_shader.h"
30 #include "sid.h"
31 #include "radeon/r600_cs.h"
32
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/u_memory.h"
36 #include "util/u_prim.h"
37 #include "util/u_simple_shaders.h"
38
39 static void si_set_tesseval_regs(struct si_shader *shader,
40 struct si_pm4_state *pm4)
41 {
42 struct tgsi_shader_info *info = &shader->selector->info;
43 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
44 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
45 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
46 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
47 unsigned type, partitioning, topology;
48
49 switch (tes_prim_mode) {
50 case PIPE_PRIM_LINES:
51 type = V_028B6C_TESS_ISOLINE;
52 break;
53 case PIPE_PRIM_TRIANGLES:
54 type = V_028B6C_TESS_TRIANGLE;
55 break;
56 case PIPE_PRIM_QUADS:
57 type = V_028B6C_TESS_QUAD;
58 break;
59 default:
60 assert(0);
61 return;
62 }
63
64 switch (tes_spacing) {
65 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
66 partitioning = V_028B6C_PART_FRAC_ODD;
67 break;
68 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
69 partitioning = V_028B6C_PART_FRAC_EVEN;
70 break;
71 case PIPE_TESS_SPACING_EQUAL:
72 partitioning = V_028B6C_PART_INTEGER;
73 break;
74 default:
75 assert(0);
76 return;
77 }
78
79 if (tes_point_mode)
80 topology = V_028B6C_OUTPUT_POINT;
81 else if (tes_prim_mode == PIPE_PRIM_LINES)
82 topology = V_028B6C_OUTPUT_LINE;
83 else if (tes_vertex_order_cw)
84 /* for some reason, this must be the other way around */
85 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
86 else
87 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
88
89 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
90 S_028B6C_TYPE(type) |
91 S_028B6C_PARTITIONING(partitioning) |
92 S_028B6C_TOPOLOGY(topology));
93 }
94
95 static void si_shader_ls(struct si_shader *shader)
96 {
97 struct si_pm4_state *pm4;
98 unsigned num_sgprs, num_user_sgprs;
99 unsigned vgpr_comp_cnt;
100 uint64_t va;
101
102 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
103 if (!pm4)
104 return;
105
106 va = shader->bo->gpu_address;
107 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
108
109 /* We need at least 2 components for LS.
110 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
111 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 1;
112
113 num_user_sgprs = SI_LS_NUM_USER_SGPR;
114 num_sgprs = shader->num_sgprs;
115 if (num_user_sgprs > num_sgprs) {
116 /* Last 2 reserved SGPRs are used for VCC */
117 num_sgprs = num_user_sgprs + 2;
118 }
119 assert(num_sgprs <= 104);
120
121 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
122 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
123
124 shader->rsrc1 = S_00B528_VGPRS((shader->num_vgprs - 1) / 4) |
125 S_00B528_SGPRS((num_sgprs - 1) / 8) |
126 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
127 S_00B528_DX10_CLAMP(shader->dx10_clamp_mode);
128 shader->rsrc2 = S_00B52C_USER_SGPR(num_user_sgprs) |
129 S_00B52C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0);
130 }
131
132 static void si_shader_hs(struct si_shader *shader)
133 {
134 struct si_pm4_state *pm4;
135 unsigned num_sgprs, num_user_sgprs;
136 uint64_t va;
137
138 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
139 if (!pm4)
140 return;
141
142 va = shader->bo->gpu_address;
143 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
144
145 num_user_sgprs = SI_TCS_NUM_USER_SGPR;
146 num_sgprs = shader->num_sgprs;
147 /* One SGPR after user SGPRs is pre-loaded with tessellation factor
148 * buffer offset. */
149 if ((num_user_sgprs + 1) > num_sgprs) {
150 /* Last 2 reserved SGPRs are used for VCC */
151 num_sgprs = num_user_sgprs + 1 + 2;
152 }
153 assert(num_sgprs <= 104);
154
155 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
156 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
157 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
158 S_00B428_VGPRS((shader->num_vgprs - 1) / 4) |
159 S_00B428_SGPRS((num_sgprs - 1) / 8) |
160 S_00B428_DX10_CLAMP(shader->dx10_clamp_mode));
161 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
162 S_00B42C_USER_SGPR(num_user_sgprs) |
163 S_00B42C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
164 }
165
166 static void si_shader_es(struct si_shader *shader)
167 {
168 struct si_pm4_state *pm4;
169 unsigned num_sgprs, num_user_sgprs;
170 unsigned vgpr_comp_cnt;
171 uint64_t va;
172
173 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
174
175 if (!pm4)
176 return;
177
178 va = shader->bo->gpu_address;
179 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
180
181 if (shader->selector->type == PIPE_SHADER_VERTEX) {
182 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
183 num_user_sgprs = SI_ES_NUM_USER_SGPR;
184 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
185 vgpr_comp_cnt = 3; /* all components are needed for TES */
186 num_user_sgprs = SI_TES_NUM_USER_SGPR;
187 } else
188 unreachable("invalid shader selector type");
189
190 num_sgprs = shader->num_sgprs;
191 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
192 if ((num_user_sgprs + 1) > num_sgprs) {
193 /* Last 2 reserved SGPRs are used for VCC */
194 num_sgprs = num_user_sgprs + 1 + 2;
195 }
196 assert(num_sgprs <= 104);
197
198 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
199 shader->selector->esgs_itemsize / 4);
200 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
201 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
202 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
203 S_00B328_VGPRS((shader->num_vgprs - 1) / 4) |
204 S_00B328_SGPRS((num_sgprs - 1) / 8) |
205 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
206 S_00B328_DX10_CLAMP(shader->dx10_clamp_mode));
207 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
208 S_00B32C_USER_SGPR(num_user_sgprs) |
209 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
210
211 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
212 si_set_tesseval_regs(shader, pm4);
213 }
214
215 static void si_shader_gs(struct si_shader *shader)
216 {
217 unsigned gs_vert_itemsize = shader->selector->gsvs_vertex_size;
218 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
219 unsigned gsvs_itemsize = shader->selector->max_gsvs_emit_size >> 2;
220 unsigned gs_num_invocations = shader->selector->gs_num_invocations;
221 unsigned cut_mode;
222 struct si_pm4_state *pm4;
223 unsigned num_sgprs, num_user_sgprs;
224 uint64_t va;
225 unsigned max_stream = shader->selector->max_gs_stream;
226
227 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
228 assert(gsvs_itemsize < (1 << 15));
229
230 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
231
232 if (!pm4)
233 return;
234
235 if (gs_max_vert_out <= 128) {
236 cut_mode = V_028A40_GS_CUT_128;
237 } else if (gs_max_vert_out <= 256) {
238 cut_mode = V_028A40_GS_CUT_256;
239 } else if (gs_max_vert_out <= 512) {
240 cut_mode = V_028A40_GS_CUT_512;
241 } else {
242 assert(gs_max_vert_out <= 1024);
243 cut_mode = V_028A40_GS_CUT_1024;
244 }
245
246 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
247 S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
248 S_028A40_CUT_MODE(cut_mode)|
249 S_028A40_ES_WRITE_OPTIMIZE(1) |
250 S_028A40_GS_WRITE_OPTIMIZE(1));
251
252 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
253 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize * ((max_stream >= 2) ? 2 : 1));
254 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize * ((max_stream >= 3) ? 3 : 1));
255
256 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize * (max_stream + 1));
257
258 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, gs_max_vert_out);
259
260 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize >> 2);
261 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? gs_vert_itemsize >> 2 : 0);
262 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? gs_vert_itemsize >> 2 : 0);
263 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? gs_vert_itemsize >> 2 : 0);
264
265 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
266 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
267 S_028B90_ENABLE(gs_num_invocations > 0));
268
269 va = shader->bo->gpu_address;
270 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
271 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
272 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
273
274 num_user_sgprs = SI_GS_NUM_USER_SGPR;
275 num_sgprs = shader->num_sgprs;
276 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
277 if ((num_user_sgprs + 2) > num_sgprs) {
278 /* Last 2 reserved SGPRs are used for VCC */
279 num_sgprs = num_user_sgprs + 2 + 2;
280 }
281 assert(num_sgprs <= 104);
282
283 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
284 S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
285 S_00B228_SGPRS((num_sgprs - 1) / 8) |
286 S_00B228_DX10_CLAMP(shader->dx10_clamp_mode));
287 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
288 S_00B22C_USER_SGPR(num_user_sgprs) |
289 S_00B22C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
290 }
291
292 static void si_shader_vs(struct si_shader *shader)
293 {
294 struct si_pm4_state *pm4;
295 unsigned num_sgprs, num_user_sgprs;
296 unsigned nparams, vgpr_comp_cnt;
297 uint64_t va;
298 unsigned window_space =
299 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
300 bool enable_prim_id = si_vs_exports_prim_id(shader);
301
302 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
303
304 if (!pm4)
305 return;
306
307 /* If this is the GS copy shader, the GS state writes this register.
308 * Otherwise, the VS state writes it.
309 */
310 if (!shader->is_gs_copy_shader) {
311 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
312 S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
313 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
314 } else
315 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
316
317 va = shader->bo->gpu_address;
318 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
319
320 if (shader->is_gs_copy_shader) {
321 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
322 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
323 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
324 vgpr_comp_cnt = shader->uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
325 num_user_sgprs = SI_VS_NUM_USER_SGPR;
326 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
327 vgpr_comp_cnt = 3; /* all components are needed for TES */
328 num_user_sgprs = SI_TES_NUM_USER_SGPR;
329 } else
330 unreachable("invalid shader selector type");
331
332 num_sgprs = shader->num_sgprs;
333 if (num_user_sgprs > num_sgprs) {
334 /* Last 2 reserved SGPRs are used for VCC */
335 num_sgprs = num_user_sgprs + 2;
336 }
337 assert(num_sgprs <= 104);
338
339 /* VS is required to export at least one param. */
340 nparams = MAX2(shader->nr_param_exports, 1);
341 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
342 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
343
344 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
345 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
346 S_02870C_POS1_EXPORT_FORMAT(shader->nr_pos_exports > 1 ?
347 V_02870C_SPI_SHADER_4COMP :
348 V_02870C_SPI_SHADER_NONE) |
349 S_02870C_POS2_EXPORT_FORMAT(shader->nr_pos_exports > 2 ?
350 V_02870C_SPI_SHADER_4COMP :
351 V_02870C_SPI_SHADER_NONE) |
352 S_02870C_POS3_EXPORT_FORMAT(shader->nr_pos_exports > 3 ?
353 V_02870C_SPI_SHADER_4COMP :
354 V_02870C_SPI_SHADER_NONE));
355
356 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
357 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
358 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
359 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
360 S_00B128_SGPRS((num_sgprs - 1) / 8) |
361 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
362 S_00B128_DX10_CLAMP(shader->dx10_clamp_mode));
363 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
364 S_00B12C_USER_SGPR(num_user_sgprs) |
365 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
366 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
367 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
368 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
369 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
370 S_00B12C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
371 if (window_space)
372 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
373 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
374 else
375 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
376 S_028818_VTX_W0_FMT(1) |
377 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
378 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
379 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
380
381 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
382 si_set_tesseval_regs(shader, pm4);
383 }
384
385 static void si_shader_ps(struct si_shader *shader)
386 {
387 struct tgsi_shader_info *info = &shader->selector->info;
388 struct si_pm4_state *pm4;
389 unsigned i, spi_ps_in_control;
390 unsigned num_sgprs, num_user_sgprs;
391 unsigned spi_baryc_cntl = 0;
392 uint64_t va;
393 bool has_centroid;
394
395 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
396
397 if (!pm4)
398 return;
399
400 for (i = 0; i < info->num_inputs; i++) {
401 switch (info->input_semantic_name[i]) {
402 case TGSI_SEMANTIC_POSITION:
403 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
404 * Possible vaules:
405 * 0 -> Position = pixel center (default)
406 * 1 -> Position = pixel centroid
407 * 2 -> Position = at sample position
408 */
409 switch (info->input_interpolate_loc[i]) {
410 case TGSI_INTERPOLATE_LOC_CENTROID:
411 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
412 break;
413 case TGSI_INTERPOLATE_LOC_SAMPLE:
414 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
415 break;
416 }
417
418 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
419 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
420 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
421 break;
422 }
423 }
424
425 has_centroid = G_0286CC_PERSP_CENTROID_ENA(shader->spi_ps_input_ena) ||
426 G_0286CC_LINEAR_CENTROID_ENA(shader->spi_ps_input_ena);
427
428 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->nparam) |
429 S_0286D8_BC_OPTIMIZE_DISABLE(has_centroid);
430
431 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
432 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
433
434 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
435 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
436 shader->spi_shader_col_format);
437 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
438
439 va = shader->bo->gpu_address;
440 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
441 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
442 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
443
444 num_user_sgprs = SI_PS_NUM_USER_SGPR;
445 num_sgprs = shader->num_sgprs;
446 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
447 if ((num_user_sgprs + 1) > num_sgprs) {
448 /* Last 2 reserved SGPRs are used for VCC */
449 num_sgprs = num_user_sgprs + 1 + 2;
450 }
451 assert(num_sgprs <= 104);
452
453 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
454 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
455 S_00B028_SGPRS((num_sgprs - 1) / 8) |
456 S_00B028_DX10_CLAMP(shader->dx10_clamp_mode));
457 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
458 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
459 S_00B02C_USER_SGPR(num_user_sgprs) |
460 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
461 }
462
463 static void si_shader_init_pm4_state(struct si_shader *shader)
464 {
465
466 if (shader->pm4)
467 si_pm4_free_state_simple(shader->pm4);
468
469 switch (shader->selector->type) {
470 case PIPE_SHADER_VERTEX:
471 if (shader->key.vs.as_ls)
472 si_shader_ls(shader);
473 else if (shader->key.vs.as_es)
474 si_shader_es(shader);
475 else
476 si_shader_vs(shader);
477 break;
478 case PIPE_SHADER_TESS_CTRL:
479 si_shader_hs(shader);
480 break;
481 case PIPE_SHADER_TESS_EVAL:
482 if (shader->key.tes.as_es)
483 si_shader_es(shader);
484 else
485 si_shader_vs(shader);
486 break;
487 case PIPE_SHADER_GEOMETRY:
488 si_shader_gs(shader);
489 si_shader_vs(shader->gs_copy_shader);
490 break;
491 case PIPE_SHADER_FRAGMENT:
492 si_shader_ps(shader);
493 break;
494 default:
495 assert(0);
496 }
497 }
498
499 /* Compute the key for the hw shader variant */
500 static inline void si_shader_selector_key(struct pipe_context *ctx,
501 struct si_shader_selector *sel,
502 union si_shader_key *key)
503 {
504 struct si_context *sctx = (struct si_context *)ctx;
505 unsigned i;
506
507 memset(key, 0, sizeof(*key));
508
509 switch (sel->type) {
510 case PIPE_SHADER_VERTEX:
511 if (sctx->vertex_elements)
512 for (i = 0; i < sctx->vertex_elements->count; ++i)
513 key->vs.instance_divisors[i] =
514 sctx->vertex_elements->elements[i].instance_divisor;
515
516 if (sctx->tes_shader.cso)
517 key->vs.as_ls = 1;
518 else if (sctx->gs_shader.cso)
519 key->vs.as_es = 1;
520
521 if (!sctx->gs_shader.cso && sctx->ps_shader.cso &&
522 sctx->ps_shader.cso->info.uses_primid)
523 key->vs.export_prim_id = 1;
524 break;
525 case PIPE_SHADER_TESS_CTRL:
526 key->tcs.prim_mode =
527 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
528 break;
529 case PIPE_SHADER_TESS_EVAL:
530 if (sctx->gs_shader.cso)
531 key->tes.as_es = 1;
532 else if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
533 key->tes.export_prim_id = 1;
534 break;
535 case PIPE_SHADER_GEOMETRY:
536 break;
537 case PIPE_SHADER_FRAGMENT: {
538 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
539
540 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
541 key->ps.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
542 key->ps.export_16bpc = sctx->framebuffer.export_16bpc;
543
544 if (rs) {
545 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
546 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
547 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
548 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
549
550 key->ps.color_two_side = rs->two_side;
551
552 if (sctx->queued.named.blend) {
553 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
554 rs->multisample_enable &&
555 !sctx->framebuffer.cb0_is_integer;
556 }
557
558 key->ps.poly_stipple = rs->poly_stipple_enable && is_poly;
559 key->ps.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
560 (is_line && rs->line_smooth)) &&
561 sctx->framebuffer.nr_samples <= 1;
562 key->ps.clamp_color = rs->clamp_fragment_color;
563 }
564
565 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
566 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
567 if (sctx->queued.named.dsa &&
568 !sctx->framebuffer.cb0_is_integer)
569 key->ps.alpha_func = sctx->queued.named.dsa->alpha_func;
570 break;
571 }
572 default:
573 assert(0);
574 }
575 }
576
577 /* Select the hw shader variant depending on the current state. */
578 static int si_shader_select(struct pipe_context *ctx,
579 struct si_shader_ctx_state *state)
580 {
581 struct si_context *sctx = (struct si_context *)ctx;
582 struct si_shader_selector *sel = state->cso;
583 struct si_shader *current = state->current;
584 union si_shader_key key;
585 struct si_shader *iter, *shader = NULL;
586 int r;
587
588 si_shader_selector_key(ctx, sel, &key);
589
590 /* Check if we don't need to change anything.
591 * This path is also used for most shaders that don't need multiple
592 * variants, it will cost just a computation of the key and this
593 * test. */
594 if (likely(current && memcmp(&current->key, &key, sizeof(key)) == 0))
595 return 0;
596
597 pipe_mutex_lock(sel->mutex);
598
599 /* Find the shader variant. */
600 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
601 /* Don't check the "current" shader. We checked it above. */
602 if (current != iter &&
603 memcmp(&iter->key, &key, sizeof(key)) == 0) {
604 state->current = iter;
605 pipe_mutex_unlock(sel->mutex);
606 return 0;
607 }
608 }
609
610 /* Build a new shader. */
611 shader = CALLOC_STRUCT(si_shader);
612 if (!shader) {
613 pipe_mutex_unlock(sel->mutex);
614 return -ENOMEM;
615 }
616 shader->selector = sel;
617 shader->key = key;
618
619 r = si_shader_create(sctx->screen, sctx->tm, shader);
620 if (unlikely(r)) {
621 R600_ERR("Failed to build shader variant (type=%u) %d\n",
622 sel->type, r);
623 FREE(shader);
624 pipe_mutex_unlock(sel->mutex);
625 return r;
626 }
627 si_shader_init_pm4_state(shader);
628
629 if (!sel->last_variant) {
630 sel->first_variant = shader;
631 sel->last_variant = shader;
632 } else {
633 sel->last_variant->next_variant = shader;
634 sel->last_variant = shader;
635 }
636 state->current = shader;
637 p_atomic_inc(&sctx->screen->b.num_compilations);
638 pipe_mutex_unlock(sel->mutex);
639 return 0;
640 }
641
642 static void *si_create_shader_selector(struct pipe_context *ctx,
643 const struct pipe_shader_state *state)
644 {
645 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
646 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
647 int i;
648
649 if (!sel)
650 return NULL;
651
652 sel->tokens = tgsi_dup_tokens(state->tokens);
653 if (!sel->tokens) {
654 FREE(sel);
655 return NULL;
656 }
657
658 sel->so = state->stream_output;
659 tgsi_scan_shader(state->tokens, &sel->info);
660 sel->type = util_pipe_shader_from_tgsi_processor(sel->info.processor);
661 p_atomic_inc(&sscreen->b.num_shaders_created);
662
663 /* First set which opcode uses which (i,j) pair. */
664 if (sel->info.uses_persp_opcode_interp_centroid)
665 sel->info.uses_persp_centroid = true;
666
667 if (sel->info.uses_linear_opcode_interp_centroid)
668 sel->info.uses_linear_centroid = true;
669
670 if (sel->info.uses_persp_opcode_interp_offset ||
671 sel->info.uses_persp_opcode_interp_sample)
672 sel->info.uses_persp_center = true;
673
674 if (sel->info.uses_linear_opcode_interp_offset ||
675 sel->info.uses_linear_opcode_interp_sample)
676 sel->info.uses_linear_center = true;
677
678 /* Determine if the shader has to use a conditional assignment when
679 * emulating force_persample_interp.
680 */
681 sel->forces_persample_interp_for_persp =
682 sel->info.uses_persp_center +
683 sel->info.uses_persp_centroid +
684 sel->info.uses_persp_sample >= 2;
685
686 sel->forces_persample_interp_for_linear =
687 sel->info.uses_linear_center +
688 sel->info.uses_linear_centroid +
689 sel->info.uses_linear_sample >= 2;
690
691 switch (sel->type) {
692 case PIPE_SHADER_GEOMETRY:
693 sel->gs_output_prim =
694 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
695 sel->gs_max_out_vertices =
696 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
697 sel->gs_num_invocations =
698 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
699 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
700 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
701 sel->gs_max_out_vertices;
702
703 sel->max_gs_stream = 0;
704 for (i = 0; i < sel->so.num_outputs; i++)
705 sel->max_gs_stream = MAX2(sel->max_gs_stream,
706 sel->so.output[i].stream);
707
708 sel->gs_input_verts_per_prim =
709 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
710 break;
711
712 case PIPE_SHADER_VERTEX:
713 case PIPE_SHADER_TESS_CTRL:
714 case PIPE_SHADER_TESS_EVAL:
715 for (i = 0; i < sel->info.num_outputs; i++) {
716 unsigned name = sel->info.output_semantic_name[i];
717 unsigned index = sel->info.output_semantic_index[i];
718
719 switch (name) {
720 case TGSI_SEMANTIC_TESSINNER:
721 case TGSI_SEMANTIC_TESSOUTER:
722 case TGSI_SEMANTIC_PATCH:
723 sel->patch_outputs_written |=
724 1llu << si_shader_io_get_unique_index(name, index);
725 break;
726 default:
727 sel->outputs_written |=
728 1llu << si_shader_io_get_unique_index(name, index);
729 }
730 }
731 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
732 break;
733 }
734
735 if (sscreen->b.debug_flags & DBG_PRECOMPILE) {
736 struct si_shader_ctx_state state = {sel};
737
738 if (si_shader_select(ctx, &state)) {
739 fprintf(stderr, "radeonsi: can't create a shader\n");
740 tgsi_free_tokens(sel->tokens);
741 FREE(sel);
742 return NULL;
743 }
744 }
745
746 pipe_mutex_init(sel->mutex);
747 return sel;
748 }
749
750 /**
751 * Normally, we only emit 1 viewport and 1 scissor if no shader is using
752 * the VIEWPORT_INDEX output, and emitting the other viewports and scissors
753 * is delayed. When a shader with VIEWPORT_INDEX appears, this should be
754 * called to emit the rest.
755 */
756 static void si_update_viewports_and_scissors(struct si_context *sctx)
757 {
758 struct tgsi_shader_info *info = si_get_vs_info(sctx);
759
760 if (!info || !info->writes_viewport_index)
761 return;
762
763 if (sctx->scissors.dirty_mask)
764 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
765 if (sctx->viewports.dirty_mask)
766 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
767 }
768
769 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
770 {
771 struct si_context *sctx = (struct si_context *)ctx;
772 struct si_shader_selector *sel = state;
773
774 if (sctx->vs_shader.cso == sel)
775 return;
776
777 sctx->vs_shader.cso = sel;
778 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
779 si_mark_atom_dirty(sctx, &sctx->clip_regs);
780 si_update_viewports_and_scissors(sctx);
781 }
782
783 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
784 {
785 struct si_context *sctx = (struct si_context *)ctx;
786 struct si_shader_selector *sel = state;
787 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
788
789 if (sctx->gs_shader.cso == sel)
790 return;
791
792 sctx->gs_shader.cso = sel;
793 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
794 si_mark_atom_dirty(sctx, &sctx->clip_regs);
795 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
796
797 if (enable_changed)
798 si_shader_change_notify(sctx);
799 si_update_viewports_and_scissors(sctx);
800 }
801
802 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
803 {
804 struct si_context *sctx = (struct si_context *)ctx;
805 struct si_shader_selector *sel = state;
806 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
807
808 if (sctx->tcs_shader.cso == sel)
809 return;
810
811 sctx->tcs_shader.cso = sel;
812 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
813
814 if (enable_changed)
815 sctx->last_tcs = NULL; /* invalidate derived tess state */
816 }
817
818 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
819 {
820 struct si_context *sctx = (struct si_context *)ctx;
821 struct si_shader_selector *sel = state;
822 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
823
824 if (sctx->tes_shader.cso == sel)
825 return;
826
827 sctx->tes_shader.cso = sel;
828 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
829 si_mark_atom_dirty(sctx, &sctx->clip_regs);
830 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
831
832 if (enable_changed) {
833 si_shader_change_notify(sctx);
834 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
835 }
836 si_update_viewports_and_scissors(sctx);
837 }
838
839 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
840 {
841 struct si_context *sctx = (struct si_context *)ctx;
842 struct si_shader_selector *sel = state;
843
844 /* skip if supplied shader is one already in use */
845 if (sctx->ps_shader.cso == sel)
846 return;
847
848 sctx->ps_shader.cso = sel;
849 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
850 si_mark_atom_dirty(sctx, &sctx->cb_target_mask);
851 }
852
853 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
854 {
855 struct si_context *sctx = (struct si_context *)ctx;
856 struct si_shader_selector *sel = (struct si_shader_selector *)state;
857 struct si_shader *p = sel->first_variant, *c;
858 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
859 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
860 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
861 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
862 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
863 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
864 };
865
866 if (current_shader[sel->type]->cso == sel) {
867 current_shader[sel->type]->cso = NULL;
868 current_shader[sel->type]->current = NULL;
869 }
870
871 while (p) {
872 c = p->next_variant;
873 switch (sel->type) {
874 case PIPE_SHADER_VERTEX:
875 if (p->key.vs.as_ls)
876 si_pm4_delete_state(sctx, ls, p->pm4);
877 else if (p->key.vs.as_es)
878 si_pm4_delete_state(sctx, es, p->pm4);
879 else
880 si_pm4_delete_state(sctx, vs, p->pm4);
881 break;
882 case PIPE_SHADER_TESS_CTRL:
883 si_pm4_delete_state(sctx, hs, p->pm4);
884 break;
885 case PIPE_SHADER_TESS_EVAL:
886 if (p->key.tes.as_es)
887 si_pm4_delete_state(sctx, es, p->pm4);
888 else
889 si_pm4_delete_state(sctx, vs, p->pm4);
890 break;
891 case PIPE_SHADER_GEOMETRY:
892 si_pm4_delete_state(sctx, gs, p->pm4);
893 si_pm4_delete_state(sctx, vs, p->gs_copy_shader->pm4);
894 break;
895 case PIPE_SHADER_FRAGMENT:
896 si_pm4_delete_state(sctx, ps, p->pm4);
897 break;
898 }
899
900 si_shader_destroy(p);
901 free(p);
902 p = c;
903 }
904
905 pipe_mutex_destroy(sel->mutex);
906 free(sel->tokens);
907 free(sel);
908 }
909
910 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
911 {
912 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
913 struct si_shader *ps = sctx->ps_shader.current;
914 struct si_shader *vs = si_get_vs_state(sctx);
915 struct tgsi_shader_info *psinfo;
916 struct tgsi_shader_info *vsinfo = &vs->selector->info;
917 unsigned i, j, tmp, num_written = 0;
918
919 if (!ps || !ps->nparam)
920 return;
921
922 psinfo = &ps->selector->info;
923
924 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, ps->nparam);
925
926 for (i = 0; i < psinfo->num_inputs; i++) {
927 unsigned name = psinfo->input_semantic_name[i];
928 unsigned index = psinfo->input_semantic_index[i];
929 unsigned interpolate = psinfo->input_interpolate[i];
930 unsigned param_offset = ps->ps_input_param_offset[i];
931
932 if (name == TGSI_SEMANTIC_POSITION ||
933 name == TGSI_SEMANTIC_FACE)
934 /* Read from preloaded VGPRs, not parameters */
935 continue;
936
937 bcolor:
938 tmp = 0;
939
940 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
941 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
942 tmp |= S_028644_FLAT_SHADE(1);
943
944 if (name == TGSI_SEMANTIC_PCOORD ||
945 (name == TGSI_SEMANTIC_TEXCOORD &&
946 sctx->sprite_coord_enable & (1 << index))) {
947 tmp |= S_028644_PT_SPRITE_TEX(1);
948 }
949
950 for (j = 0; j < vsinfo->num_outputs; j++) {
951 if (name == vsinfo->output_semantic_name[j] &&
952 index == vsinfo->output_semantic_index[j]) {
953 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[j]);
954 break;
955 }
956 }
957
958 if (name == TGSI_SEMANTIC_PRIMID)
959 /* PrimID is written after the last output. */
960 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[vsinfo->num_outputs]);
961 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(tmp)) {
962 /* No corresponding output found, load defaults into input.
963 * Don't set any other bits.
964 * (FLAT_SHADE=1 completely changes behavior) */
965 tmp = S_028644_OFFSET(0x20);
966 }
967
968 assert(param_offset == num_written);
969 radeon_emit(cs, tmp);
970 num_written++;
971
972 if (name == TGSI_SEMANTIC_COLOR &&
973 ps->key.ps.color_two_side) {
974 name = TGSI_SEMANTIC_BCOLOR;
975 param_offset++;
976 goto bcolor;
977 }
978 }
979 assert(ps->nparam == num_written);
980 }
981
982 static void si_emit_spi_ps_input(struct si_context *sctx, struct r600_atom *atom)
983 {
984 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
985 struct si_shader *ps = sctx->ps_shader.current;
986 unsigned input_ena;
987
988 if (!ps)
989 return;
990
991 input_ena = ps->spi_ps_input_ena;
992
993 /* we need to enable at least one of them, otherwise we hang the GPU */
994 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
995 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
996 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
997 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
998 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
999 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1000 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1001 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1002
1003 if (sctx->force_persample_interp) {
1004 unsigned num_persp = G_0286CC_PERSP_SAMPLE_ENA(input_ena) +
1005 G_0286CC_PERSP_CENTER_ENA(input_ena) +
1006 G_0286CC_PERSP_CENTROID_ENA(input_ena);
1007 unsigned num_linear = G_0286CC_LINEAR_SAMPLE_ENA(input_ena) +
1008 G_0286CC_LINEAR_CENTER_ENA(input_ena) +
1009 G_0286CC_LINEAR_CENTROID_ENA(input_ena);
1010
1011 /* If only one set of (i,j) coordinates is used, we can disable
1012 * CENTER/CENTROID, enable SAMPLE and it will load SAMPLE coordinates
1013 * where CENTER/CENTROID are expected, effectively forcing per-sample
1014 * interpolation.
1015 */
1016 if (num_persp == 1) {
1017 input_ena &= C_0286CC_PERSP_CENTER_ENA;
1018 input_ena &= C_0286CC_PERSP_CENTROID_ENA;
1019 input_ena |= G_0286CC_PERSP_SAMPLE_ENA(1);
1020 }
1021 if (num_linear == 1) {
1022 input_ena &= C_0286CC_LINEAR_CENTER_ENA;
1023 input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
1024 input_ena |= G_0286CC_LINEAR_SAMPLE_ENA(1);
1025 }
1026
1027 /* If at least 2 sets of coordinates are used, we can't use this
1028 * trick and have to select SAMPLE using a conditional assignment
1029 * in the shader with "force_persample_interp" being a shader constant.
1030 */
1031 }
1032
1033 radeon_set_context_reg_seq(cs, R_0286CC_SPI_PS_INPUT_ENA, 2);
1034 radeon_emit(cs, input_ena);
1035 radeon_emit(cs, input_ena);
1036
1037 if (ps->selector->forces_persample_interp_for_persp ||
1038 ps->selector->forces_persample_interp_for_linear)
1039 radeon_set_sh_reg(cs, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1040 SI_SGPR_PS_STATE_BITS * 4,
1041 sctx->force_persample_interp);
1042 }
1043
1044 /**
1045 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
1046 */
1047 static void si_init_config_add_vgt_flush(struct si_context *sctx)
1048 {
1049 if (sctx->init_config_has_vgt_flush)
1050 return;
1051
1052 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
1053 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
1054 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1055 si_pm4_cmd_end(sctx->init_config, false);
1056 sctx->init_config_has_vgt_flush = true;
1057 }
1058
1059 /* Initialize state related to ESGS / GSVS ring buffers */
1060 static bool si_update_gs_ring_buffers(struct si_context *sctx)
1061 {
1062 struct si_shader_selector *es =
1063 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
1064 struct si_shader_selector *gs = sctx->gs_shader.cso;
1065 struct si_pm4_state *pm4;
1066
1067 /* Chip constants. */
1068 unsigned num_se = sctx->screen->b.info.max_se;
1069 unsigned wave_size = 64;
1070 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1071 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1072 unsigned alignment = 256 * num_se;
1073 /* The maximum size is 63.999 MB per SE. */
1074 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1075
1076 /* Calculate the minimum size. */
1077 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
1078 wave_size, alignment);
1079
1080 /* These are recommended sizes, not minimum sizes. */
1081 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1082 es->esgs_itemsize * gs->gs_input_verts_per_prim;
1083 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1084 gs->max_gsvs_emit_size * (gs->max_gs_stream + 1);
1085
1086 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1087 esgs_ring_size = align(esgs_ring_size, alignment);
1088 gsvs_ring_size = align(gsvs_ring_size, alignment);
1089
1090 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1091 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1092
1093 /* Some rings don't have to be allocated if shaders don't use them.
1094 * (e.g. no varyings between ES and GS or GS and VS)
1095 */
1096 bool update_esgs = esgs_ring_size &&
1097 (!sctx->esgs_ring ||
1098 sctx->esgs_ring->width0 < esgs_ring_size);
1099 bool update_gsvs = gsvs_ring_size &&
1100 (!sctx->gsvs_ring ||
1101 sctx->gsvs_ring->width0 < gsvs_ring_size);
1102
1103 if (!update_esgs && !update_gsvs)
1104 return true;
1105
1106 if (update_esgs) {
1107 pipe_resource_reference(&sctx->esgs_ring, NULL);
1108 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1109 PIPE_USAGE_DEFAULT,
1110 esgs_ring_size);
1111 if (!sctx->esgs_ring)
1112 return false;
1113 }
1114
1115 if (update_gsvs) {
1116 pipe_resource_reference(&sctx->gsvs_ring, NULL);
1117 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1118 PIPE_USAGE_DEFAULT,
1119 gsvs_ring_size);
1120 if (!sctx->gsvs_ring)
1121 return false;
1122 }
1123
1124 /* Create the "init_config_gs_rings" state. */
1125 pm4 = CALLOC_STRUCT(si_pm4_state);
1126 if (!pm4)
1127 return false;
1128
1129 if (sctx->b.chip_class >= CIK) {
1130 if (sctx->esgs_ring)
1131 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
1132 sctx->esgs_ring->width0 / 256);
1133 if (sctx->gsvs_ring)
1134 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
1135 sctx->gsvs_ring->width0 / 256);
1136 } else {
1137 if (sctx->esgs_ring)
1138 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
1139 sctx->esgs_ring->width0 / 256);
1140 if (sctx->gsvs_ring)
1141 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
1142 sctx->gsvs_ring->width0 / 256);
1143 }
1144
1145 /* Set the state. */
1146 if (sctx->init_config_gs_rings)
1147 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
1148 sctx->init_config_gs_rings = pm4;
1149
1150 if (!sctx->init_config_has_vgt_flush) {
1151 si_init_config_add_vgt_flush(sctx);
1152 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1153 }
1154
1155 /* Flush the context to re-emit both init_config states. */
1156 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1157 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1158
1159 /* Set ring bindings. */
1160 if (sctx->esgs_ring) {
1161 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
1162 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1163 true, true, 4, 64, 0);
1164 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
1165 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1166 false, false, 0, 0, 0);
1167 }
1168 if (sctx->gsvs_ring)
1169 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
1170 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
1171 false, false, 0, 0, 0);
1172 return true;
1173 }
1174
1175 static void si_update_gsvs_ring_bindings(struct si_context *sctx)
1176 {
1177 unsigned gsvs_itemsize = sctx->gs_shader.cso->max_gsvs_emit_size;
1178 uint64_t offset;
1179
1180 if (!sctx->gsvs_ring || gsvs_itemsize == sctx->last_gsvs_itemsize)
1181 return;
1182
1183 sctx->last_gsvs_itemsize = gsvs_itemsize;
1184
1185 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
1186 sctx->gsvs_ring, gsvs_itemsize,
1187 64, true, true, 4, 16, 0);
1188
1189 offset = gsvs_itemsize * 64;
1190 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_1,
1191 sctx->gsvs_ring, gsvs_itemsize,
1192 64, true, true, 4, 16, offset);
1193
1194 offset = (gsvs_itemsize * 2) * 64;
1195 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_2,
1196 sctx->gsvs_ring, gsvs_itemsize,
1197 64, true, true, 4, 16, offset);
1198
1199 offset = (gsvs_itemsize * 3) * 64;
1200 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_3,
1201 sctx->gsvs_ring, gsvs_itemsize,
1202 64, true, true, 4, 16, offset);
1203 }
1204
1205 /**
1206 * @returns 1 if \p sel has been updated to use a new scratch buffer
1207 * 0 if not
1208 * < 0 if there was a failure
1209 */
1210 static int si_update_scratch_buffer(struct si_context *sctx,
1211 struct si_shader *shader)
1212 {
1213 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
1214 int r;
1215
1216 if (!shader)
1217 return 0;
1218
1219 /* This shader doesn't need a scratch buffer */
1220 if (shader->scratch_bytes_per_wave == 0)
1221 return 0;
1222
1223 /* This shader is already configured to use the current
1224 * scratch buffer. */
1225 if (shader->scratch_bo == sctx->scratch_buffer)
1226 return 0;
1227
1228 assert(sctx->scratch_buffer);
1229
1230 si_shader_apply_scratch_relocs(sctx, shader, scratch_va);
1231
1232 /* Replace the shader bo with a new bo that has the relocs applied. */
1233 r = si_shader_binary_upload(sctx->screen, shader);
1234 if (r)
1235 return r;
1236
1237 /* Update the shader state to use the new shader bo. */
1238 si_shader_init_pm4_state(shader);
1239
1240 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
1241
1242 return 1;
1243 }
1244
1245 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
1246 {
1247 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
1248 }
1249
1250 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
1251 {
1252 return shader ? shader->scratch_bytes_per_wave : 0;
1253 }
1254
1255 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
1256 {
1257 unsigned bytes = 0;
1258
1259 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
1260 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
1261 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
1262 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tcs_shader.current));
1263 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
1264 return bytes;
1265 }
1266
1267 static bool si_update_spi_tmpring_size(struct si_context *sctx)
1268 {
1269 unsigned current_scratch_buffer_size =
1270 si_get_current_scratch_buffer_size(sctx);
1271 unsigned scratch_bytes_per_wave =
1272 si_get_max_scratch_bytes_per_wave(sctx);
1273 unsigned scratch_needed_size = scratch_bytes_per_wave *
1274 sctx->scratch_waves;
1275 int r;
1276
1277 if (scratch_needed_size > 0) {
1278 if (scratch_needed_size > current_scratch_buffer_size) {
1279 /* Create a bigger scratch buffer */
1280 pipe_resource_reference(
1281 (struct pipe_resource**)&sctx->scratch_buffer,
1282 NULL);
1283
1284 sctx->scratch_buffer =
1285 si_resource_create_custom(&sctx->screen->b.b,
1286 PIPE_USAGE_DEFAULT, scratch_needed_size);
1287 if (!sctx->scratch_buffer)
1288 return false;
1289 sctx->emit_scratch_reloc = true;
1290 }
1291
1292 /* Update the shaders, so they are using the latest scratch. The
1293 * scratch buffer may have been changed since these shaders were
1294 * last used, so we still need to try to update them, even if
1295 * they require scratch buffers smaller than the current size.
1296 */
1297 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
1298 if (r < 0)
1299 return false;
1300 if (r == 1)
1301 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
1302
1303 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
1304 if (r < 0)
1305 return false;
1306 if (r == 1)
1307 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1308
1309 r = si_update_scratch_buffer(sctx, sctx->tcs_shader.current);
1310 if (r < 0)
1311 return false;
1312 if (r == 1)
1313 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1314
1315 /* VS can be bound as LS, ES, or VS. */
1316 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
1317 if (r < 0)
1318 return false;
1319 if (r == 1) {
1320 if (sctx->tes_shader.current)
1321 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1322 else if (sctx->gs_shader.current)
1323 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1324 else
1325 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1326 }
1327
1328 /* TES can be bound as ES or VS. */
1329 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
1330 if (r < 0)
1331 return false;
1332 if (r == 1) {
1333 if (sctx->gs_shader.current)
1334 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1335 else
1336 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1337 }
1338 }
1339
1340 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
1341 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
1342 "scratch size should already be aligned correctly.");
1343
1344 sctx->spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
1345 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
1346 return true;
1347 }
1348
1349 static void si_init_tess_factor_ring(struct si_context *sctx)
1350 {
1351 assert(!sctx->tf_ring);
1352
1353 sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1354 PIPE_USAGE_DEFAULT,
1355 32768 * sctx->screen->b.info.max_se);
1356 if (!sctx->tf_ring)
1357 return;
1358
1359 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
1360
1361 si_init_config_add_vgt_flush(sctx);
1362
1363 /* Append these registers to the init config state. */
1364 if (sctx->b.chip_class >= CIK) {
1365 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
1366 S_030938_SIZE(sctx->tf_ring->width0 / 4));
1367 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
1368 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1369 } else {
1370 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
1371 S_008988_SIZE(sctx->tf_ring->width0 / 4));
1372 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
1373 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1374 }
1375
1376 /* Flush the context to re-emit the init_config state.
1377 * This is done only once in a lifetime of a context.
1378 */
1379 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1380 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1381 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1382
1383 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_TESS_CTRL,
1384 SI_RING_TESS_FACTOR, sctx->tf_ring, 0,
1385 sctx->tf_ring->width0, false, false, 0, 0, 0);
1386 }
1387
1388 /**
1389 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
1390 * VS passes its outputs to TES directly, so the fixed-function shader only
1391 * has to write TESSOUTER and TESSINNER.
1392 */
1393 static void si_generate_fixed_func_tcs(struct si_context *sctx)
1394 {
1395 struct ureg_src const0, const1;
1396 struct ureg_dst tessouter, tessinner;
1397 struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
1398
1399 if (!ureg)
1400 return; /* if we get here, we're screwed */
1401
1402 assert(!sctx->fixed_func_tcs_shader.cso);
1403
1404 ureg_DECL_constant2D(ureg, 0, 1, SI_DRIVER_STATE_CONST_BUF);
1405 const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 0),
1406 SI_DRIVER_STATE_CONST_BUF);
1407 const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 1),
1408 SI_DRIVER_STATE_CONST_BUF);
1409
1410 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1411 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1412
1413 ureg_MOV(ureg, tessouter, const0);
1414 ureg_MOV(ureg, tessinner, const1);
1415 ureg_END(ureg);
1416
1417 sctx->fixed_func_tcs_shader.cso =
1418 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
1419 }
1420
1421 static void si_update_vgt_shader_config(struct si_context *sctx)
1422 {
1423 /* Calculate the index of the config.
1424 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
1425 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
1426 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
1427
1428 if (!*pm4) {
1429 uint32_t stages = 0;
1430
1431 *pm4 = CALLOC_STRUCT(si_pm4_state);
1432
1433 if (sctx->tes_shader.cso) {
1434 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
1435 S_028B54_HS_EN(1);
1436
1437 if (sctx->gs_shader.cso)
1438 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
1439 S_028B54_GS_EN(1) |
1440 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1441 else
1442 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
1443 } else if (sctx->gs_shader.cso) {
1444 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1445 S_028B54_GS_EN(1) |
1446 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1447 }
1448
1449 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
1450 }
1451 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
1452 }
1453
1454 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
1455 {
1456 struct pipe_stream_output_info *so = &shader->so;
1457 uint32_t enabled_stream_buffers_mask = 0;
1458 int i;
1459
1460 for (i = 0; i < so->num_outputs; i++)
1461 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
1462 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
1463 sctx->b.streamout.stride_in_dw = shader->so.stride;
1464 }
1465
1466 bool si_update_shaders(struct si_context *sctx)
1467 {
1468 struct pipe_context *ctx = (struct pipe_context*)sctx;
1469 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1470 int r;
1471
1472 /* Update stages before GS. */
1473 if (sctx->tes_shader.cso) {
1474 if (!sctx->tf_ring) {
1475 si_init_tess_factor_ring(sctx);
1476 if (!sctx->tf_ring)
1477 return false;
1478 }
1479
1480 /* VS as LS */
1481 r = si_shader_select(ctx, &sctx->vs_shader);
1482 if (r)
1483 return false;
1484 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1485
1486 if (sctx->tcs_shader.cso) {
1487 r = si_shader_select(ctx, &sctx->tcs_shader);
1488 if (r)
1489 return false;
1490 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1491 } else {
1492 if (!sctx->fixed_func_tcs_shader.cso) {
1493 si_generate_fixed_func_tcs(sctx);
1494 if (!sctx->fixed_func_tcs_shader.cso)
1495 return false;
1496 }
1497
1498 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader);
1499 if (r)
1500 return false;
1501 si_pm4_bind_state(sctx, hs,
1502 sctx->fixed_func_tcs_shader.current->pm4);
1503 }
1504
1505 r = si_shader_select(ctx, &sctx->tes_shader);
1506 if (r)
1507 return false;
1508
1509 if (sctx->gs_shader.cso) {
1510 /* TES as ES */
1511 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1512 } else {
1513 /* TES as VS */
1514 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1515 si_update_so(sctx, sctx->tes_shader.cso);
1516 }
1517 } else if (sctx->gs_shader.cso) {
1518 /* VS as ES */
1519 r = si_shader_select(ctx, &sctx->vs_shader);
1520 if (r)
1521 return false;
1522 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1523 } else {
1524 /* VS as VS */
1525 r = si_shader_select(ctx, &sctx->vs_shader);
1526 if (r)
1527 return false;
1528 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1529 si_update_so(sctx, sctx->vs_shader.cso);
1530 }
1531
1532 /* Update GS. */
1533 if (sctx->gs_shader.cso) {
1534 r = si_shader_select(ctx, &sctx->gs_shader);
1535 if (r)
1536 return false;
1537 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1538 si_pm4_bind_state(sctx, vs, sctx->gs_shader.current->gs_copy_shader->pm4);
1539 si_update_so(sctx, sctx->gs_shader.cso);
1540
1541 if (!si_update_gs_ring_buffers(sctx))
1542 return false;
1543
1544 si_update_gsvs_ring_bindings(sctx);
1545 } else {
1546 si_pm4_bind_state(sctx, gs, NULL);
1547 si_pm4_bind_state(sctx, es, NULL);
1548 }
1549
1550 si_update_vgt_shader_config(sctx);
1551
1552 if (sctx->ps_shader.cso) {
1553 r = si_shader_select(ctx, &sctx->ps_shader);
1554 if (r)
1555 return false;
1556 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
1557
1558 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
1559 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
1560 sctx->flatshade != rs->flatshade) {
1561 sctx->sprite_coord_enable = rs->sprite_coord_enable;
1562 sctx->flatshade = rs->flatshade;
1563 si_mark_atom_dirty(sctx, &sctx->spi_map);
1564 }
1565
1566 if (si_pm4_state_changed(sctx, ps) ||
1567 sctx->force_persample_interp != rs->force_persample_interp) {
1568 sctx->force_persample_interp = rs->force_persample_interp;
1569 si_mark_atom_dirty(sctx, &sctx->spi_ps_input);
1570 }
1571
1572 if (sctx->ps_db_shader_control != sctx->ps_shader.current->db_shader_control) {
1573 sctx->ps_db_shader_control = sctx->ps_shader.current->db_shader_control;
1574 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1575 }
1576
1577 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.ps.poly_line_smoothing) {
1578 sctx->smoothing_enabled = sctx->ps_shader.current->key.ps.poly_line_smoothing;
1579 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1580
1581 if (sctx->b.chip_class == SI)
1582 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1583 }
1584 }
1585
1586 if (si_pm4_state_changed(sctx, ls) ||
1587 si_pm4_state_changed(sctx, hs) ||
1588 si_pm4_state_changed(sctx, es) ||
1589 si_pm4_state_changed(sctx, gs) ||
1590 si_pm4_state_changed(sctx, vs) ||
1591 si_pm4_state_changed(sctx, ps)) {
1592 if (!si_update_spi_tmpring_size(sctx))
1593 return false;
1594 }
1595 return true;
1596 }
1597
1598 void si_init_shader_functions(struct si_context *sctx)
1599 {
1600 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
1601 si_init_atom(sctx, &sctx->spi_ps_input, &sctx->atoms.s.spi_ps_input, si_emit_spi_ps_input);
1602
1603 sctx->b.b.create_vs_state = si_create_shader_selector;
1604 sctx->b.b.create_tcs_state = si_create_shader_selector;
1605 sctx->b.b.create_tes_state = si_create_shader_selector;
1606 sctx->b.b.create_gs_state = si_create_shader_selector;
1607 sctx->b.b.create_fs_state = si_create_shader_selector;
1608
1609 sctx->b.b.bind_vs_state = si_bind_vs_shader;
1610 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
1611 sctx->b.b.bind_tes_state = si_bind_tes_shader;
1612 sctx->b.b.bind_gs_state = si_bind_gs_shader;
1613 sctx->b.b.bind_fs_state = si_bind_ps_shader;
1614
1615 sctx->b.b.delete_vs_state = si_delete_shader_selector;
1616 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
1617 sctx->b.b.delete_tes_state = si_delete_shader_selector;
1618 sctx->b.b.delete_gs_state = si_delete_shader_selector;
1619 sctx->b.b.delete_fs_state = si_delete_shader_selector;
1620 }