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radeonsi: skip DCC render feedback checking if color writes are disabled
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "sid.h"
26 #include "gfx9d.h"
27 #include "radeon/r600_cs.h"
28
29 #include "compiler/nir/nir_serialize.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "tgsi/tgsi_ureg.h"
32 #include "util/hash_table.h"
33 #include "util/crc32.h"
34 #include "util/u_async_debug.h"
35 #include "util/u_memory.h"
36 #include "util/u_prim.h"
37
38 #include "util/disk_cache.h"
39 #include "util/mesa-sha1.h"
40 #include "ac_exp_param.h"
41 #include "ac_shader_util.h"
42
43 /* SHADER_CACHE */
44
45 /**
46 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
47 * size as integer.
48 */
49 static void *si_get_ir_binary(struct si_shader_selector *sel)
50 {
51 struct blob blob;
52 unsigned ir_size;
53 void *ir_binary;
54
55 if (sel->tokens) {
56 ir_binary = sel->tokens;
57 ir_size = tgsi_num_tokens(sel->tokens) *
58 sizeof(struct tgsi_token);
59 } else {
60 assert(sel->nir);
61
62 blob_init(&blob);
63 nir_serialize(&blob, sel->nir);
64 ir_binary = blob.data;
65 ir_size = blob.size;
66 }
67
68 unsigned size = 4 + ir_size + sizeof(sel->so);
69 char *result = (char*)MALLOC(size);
70 if (!result)
71 return NULL;
72
73 *((uint32_t*)result) = size;
74 memcpy(result + 4, ir_binary, ir_size);
75 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
76
77 if (sel->nir)
78 blob_finish(&blob);
79
80 return result;
81 }
82
83 /** Copy "data" to "ptr" and return the next dword following copied data. */
84 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
85 {
86 /* data may be NULL if size == 0 */
87 if (size)
88 memcpy(ptr, data, size);
89 ptr += DIV_ROUND_UP(size, 4);
90 return ptr;
91 }
92
93 /** Read data from "ptr". Return the next dword following the data. */
94 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
95 {
96 memcpy(data, ptr, size);
97 ptr += DIV_ROUND_UP(size, 4);
98 return ptr;
99 }
100
101 /**
102 * Write the size as uint followed by the data. Return the next dword
103 * following the copied data.
104 */
105 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
106 {
107 *ptr++ = size;
108 return write_data(ptr, data, size);
109 }
110
111 /**
112 * Read the size as uint followed by the data. Return both via parameters.
113 * Return the next dword following the data.
114 */
115 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
116 {
117 *size = *ptr++;
118 assert(*data == NULL);
119 if (!*size)
120 return ptr;
121 *data = malloc(*size);
122 return read_data(ptr, *data, *size);
123 }
124
125 /**
126 * Return the shader binary in a buffer. The first 4 bytes contain its size
127 * as integer.
128 */
129 static void *si_get_shader_binary(struct si_shader *shader)
130 {
131 /* There is always a size of data followed by the data itself. */
132 unsigned relocs_size = shader->binary.reloc_count *
133 sizeof(shader->binary.relocs[0]);
134 unsigned disasm_size = shader->binary.disasm_string ?
135 strlen(shader->binary.disasm_string) + 1 : 0;
136 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
137 strlen(shader->binary.llvm_ir_string) + 1 : 0;
138 unsigned size =
139 4 + /* total size */
140 4 + /* CRC32 of the data below */
141 align(sizeof(shader->config), 4) +
142 align(sizeof(shader->info), 4) +
143 4 + align(shader->binary.code_size, 4) +
144 4 + align(shader->binary.rodata_size, 4) +
145 4 + align(relocs_size, 4) +
146 4 + align(disasm_size, 4) +
147 4 + align(llvm_ir_size, 4);
148 void *buffer = CALLOC(1, size);
149 uint32_t *ptr = (uint32_t*)buffer;
150
151 if (!buffer)
152 return NULL;
153
154 *ptr++ = size;
155 ptr++; /* CRC32 is calculated at the end. */
156
157 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
158 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
159 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
160 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
161 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
162 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
163 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
164 assert((char *)ptr - (char *)buffer == size);
165
166 /* Compute CRC32. */
167 ptr = (uint32_t*)buffer;
168 ptr++;
169 *ptr = util_hash_crc32(ptr + 1, size - 8);
170
171 return buffer;
172 }
173
174 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
175 {
176 uint32_t *ptr = (uint32_t*)binary;
177 uint32_t size = *ptr++;
178 uint32_t crc32 = *ptr++;
179 unsigned chunk_size;
180
181 if (util_hash_crc32(ptr, size - 8) != crc32) {
182 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
183 return false;
184 }
185
186 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
187 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
188 ptr = read_chunk(ptr, (void**)&shader->binary.code,
189 &shader->binary.code_size);
190 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
191 &shader->binary.rodata_size);
192 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
193 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
194 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
195 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
196
197 return true;
198 }
199
200 /**
201 * Insert a shader into the cache. It's assumed the shader is not in the cache.
202 * Use si_shader_cache_load_shader before calling this.
203 *
204 * Returns false on failure, in which case the ir_binary should be freed.
205 */
206 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
207 void *ir_binary,
208 struct si_shader *shader,
209 bool insert_into_disk_cache)
210 {
211 void *hw_binary;
212 struct hash_entry *entry;
213 uint8_t key[CACHE_KEY_SIZE];
214
215 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
216 if (entry)
217 return false; /* already added */
218
219 hw_binary = si_get_shader_binary(shader);
220 if (!hw_binary)
221 return false;
222
223 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
224 hw_binary) == NULL) {
225 FREE(hw_binary);
226 return false;
227 }
228
229 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
230 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
231 *((uint32_t *)ir_binary), key);
232 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
233 *((uint32_t *) hw_binary), NULL);
234 }
235
236 return true;
237 }
238
239 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
240 void *ir_binary,
241 struct si_shader *shader)
242 {
243 struct hash_entry *entry =
244 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
245 if (!entry) {
246 if (sscreen->disk_shader_cache) {
247 unsigned char sha1[CACHE_KEY_SIZE];
248 size_t tg_size = *((uint32_t *) ir_binary);
249
250 disk_cache_compute_key(sscreen->disk_shader_cache,
251 ir_binary, tg_size, sha1);
252
253 size_t binary_size;
254 uint8_t *buffer =
255 disk_cache_get(sscreen->disk_shader_cache,
256 sha1, &binary_size);
257 if (!buffer)
258 return false;
259
260 if (binary_size < sizeof(uint32_t) ||
261 *((uint32_t*)buffer) != binary_size) {
262 /* Something has gone wrong discard the item
263 * from the cache and rebuild/link from
264 * source.
265 */
266 assert(!"Invalid radeonsi shader disk cache "
267 "item!");
268
269 disk_cache_remove(sscreen->disk_shader_cache,
270 sha1);
271 free(buffer);
272
273 return false;
274 }
275
276 if (!si_load_shader_binary(shader, buffer)) {
277 free(buffer);
278 return false;
279 }
280 free(buffer);
281
282 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
283 shader, false))
284 FREE(ir_binary);
285 } else {
286 return false;
287 }
288 } else {
289 if (si_load_shader_binary(shader, entry->data))
290 FREE(ir_binary);
291 else
292 return false;
293 }
294 p_atomic_inc(&sscreen->num_shader_cache_hits);
295 return true;
296 }
297
298 static uint32_t si_shader_cache_key_hash(const void *key)
299 {
300 /* The first dword is the key size. */
301 return util_hash_crc32(key, *(uint32_t*)key);
302 }
303
304 static bool si_shader_cache_key_equals(const void *a, const void *b)
305 {
306 uint32_t *keya = (uint32_t*)a;
307 uint32_t *keyb = (uint32_t*)b;
308
309 /* The first dword is the key size. */
310 if (*keya != *keyb)
311 return false;
312
313 return memcmp(keya, keyb, *keya) == 0;
314 }
315
316 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
317 {
318 FREE((void*)entry->key);
319 FREE(entry->data);
320 }
321
322 bool si_init_shader_cache(struct si_screen *sscreen)
323 {
324 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
325 sscreen->shader_cache =
326 _mesa_hash_table_create(NULL,
327 si_shader_cache_key_hash,
328 si_shader_cache_key_equals);
329
330 return sscreen->shader_cache != NULL;
331 }
332
333 void si_destroy_shader_cache(struct si_screen *sscreen)
334 {
335 if (sscreen->shader_cache)
336 _mesa_hash_table_destroy(sscreen->shader_cache,
337 si_destroy_shader_cache_entry);
338 mtx_destroy(&sscreen->shader_cache_mutex);
339 }
340
341 /* SHADER STATES */
342
343 static void si_set_tesseval_regs(struct si_screen *sscreen,
344 struct si_shader_selector *tes,
345 struct si_pm4_state *pm4)
346 {
347 struct tgsi_shader_info *info = &tes->info;
348 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
349 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
350 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
351 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
352 unsigned type, partitioning, topology, distribution_mode;
353
354 switch (tes_prim_mode) {
355 case PIPE_PRIM_LINES:
356 type = V_028B6C_TESS_ISOLINE;
357 break;
358 case PIPE_PRIM_TRIANGLES:
359 type = V_028B6C_TESS_TRIANGLE;
360 break;
361 case PIPE_PRIM_QUADS:
362 type = V_028B6C_TESS_QUAD;
363 break;
364 default:
365 assert(0);
366 return;
367 }
368
369 switch (tes_spacing) {
370 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
371 partitioning = V_028B6C_PART_FRAC_ODD;
372 break;
373 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
374 partitioning = V_028B6C_PART_FRAC_EVEN;
375 break;
376 case PIPE_TESS_SPACING_EQUAL:
377 partitioning = V_028B6C_PART_INTEGER;
378 break;
379 default:
380 assert(0);
381 return;
382 }
383
384 if (tes_point_mode)
385 topology = V_028B6C_OUTPUT_POINT;
386 else if (tes_prim_mode == PIPE_PRIM_LINES)
387 topology = V_028B6C_OUTPUT_LINE;
388 else if (tes_vertex_order_cw)
389 /* for some reason, this must be the other way around */
390 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
391 else
392 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
393
394 if (sscreen->has_distributed_tess) {
395 if (sscreen->info.family == CHIP_FIJI ||
396 sscreen->info.family >= CHIP_POLARIS10)
397 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
398 else
399 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
400 } else
401 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
402
403 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
404 S_028B6C_TYPE(type) |
405 S_028B6C_PARTITIONING(partitioning) |
406 S_028B6C_TOPOLOGY(topology) |
407 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
408 }
409
410 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
411 * whether the "fractional odd" tessellation spacing is used.
412 *
413 * Possible VGT configurations and which state should set the register:
414 *
415 * Reg set in | VGT shader configuration | Value
416 * ------------------------------------------------------
417 * VS as VS | VS | 30
418 * VS as ES | ES -> GS -> VS | 30
419 * TES as VS | LS -> HS -> VS | 14 or 30
420 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
421 *
422 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
423 */
424 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
425 struct si_shader_selector *sel,
426 struct si_shader *shader,
427 struct si_pm4_state *pm4)
428 {
429 unsigned type = sel->type;
430
431 if (sscreen->info.family < CHIP_POLARIS10)
432 return;
433
434 /* VS as VS, or VS as ES: */
435 if ((type == PIPE_SHADER_VERTEX &&
436 (!shader ||
437 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
438 /* TES as VS, or TES as ES: */
439 type == PIPE_SHADER_TESS_EVAL) {
440 unsigned vtx_reuse_depth = 30;
441
442 if (type == PIPE_SHADER_TESS_EVAL &&
443 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
444 PIPE_TESS_SPACING_FRACTIONAL_ODD)
445 vtx_reuse_depth = 14;
446
447 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
448 vtx_reuse_depth);
449 }
450 }
451
452 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
453 {
454 if (shader->pm4)
455 si_pm4_clear_state(shader->pm4);
456 else
457 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
458
459 return shader->pm4;
460 }
461
462 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
463 {
464 /* Add the pointer to VBO descriptors. */
465 if (HAVE_32BIT_POINTERS) {
466 return num_always_on_user_sgprs + 1;
467 } else {
468 assert(num_always_on_user_sgprs % 2 == 0);
469 return num_always_on_user_sgprs + 2;
470 }
471 }
472
473 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
474 {
475 struct si_pm4_state *pm4;
476 unsigned vgpr_comp_cnt;
477 uint64_t va;
478
479 assert(sscreen->info.chip_class <= VI);
480
481 pm4 = si_get_shader_pm4_state(shader);
482 if (!pm4)
483 return;
484
485 va = shader->bo->gpu_address;
486 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
487
488 /* We need at least 2 components for LS.
489 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
490 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
491 */
492 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
493
494 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
495 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
496
497 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
498 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
499 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
500 S_00B528_DX10_CLAMP(1) |
501 S_00B528_FLOAT_MODE(shader->config.float_mode);
502 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
503 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
504 }
505
506 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
507 {
508 struct si_pm4_state *pm4;
509 uint64_t va;
510 unsigned ls_vgpr_comp_cnt = 0;
511
512 pm4 = si_get_shader_pm4_state(shader);
513 if (!pm4)
514 return;
515
516 va = shader->bo->gpu_address;
517 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
518
519 if (sscreen->info.chip_class >= GFX9) {
520 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
521 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
522
523 /* We need at least 2 components for LS.
524 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
525 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
526 */
527 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
528
529 unsigned num_user_sgprs =
530 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
531
532 shader->config.rsrc2 =
533 S_00B42C_USER_SGPR(num_user_sgprs) |
534 S_00B42C_USER_SGPR_MSB(num_user_sgprs >> 5) |
535 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
536 } else {
537 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
538 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
539
540 shader->config.rsrc2 =
541 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
542 S_00B42C_OC_LDS_EN(1) |
543 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
544 }
545
546 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
547 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
548 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
549 S_00B428_DX10_CLAMP(1) |
550 S_00B428_FLOAT_MODE(shader->config.float_mode) |
551 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
552
553 if (sscreen->info.chip_class <= VI) {
554 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
555 shader->config.rsrc2);
556 }
557 }
558
559 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
560 {
561 struct si_pm4_state *pm4;
562 unsigned num_user_sgprs;
563 unsigned vgpr_comp_cnt;
564 uint64_t va;
565 unsigned oc_lds_en;
566
567 assert(sscreen->info.chip_class <= VI);
568
569 pm4 = si_get_shader_pm4_state(shader);
570 if (!pm4)
571 return;
572
573 va = shader->bo->gpu_address;
574 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
575
576 if (shader->selector->type == PIPE_SHADER_VERTEX) {
577 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
578 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
579 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
580 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
581 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
582 num_user_sgprs = SI_TES_NUM_USER_SGPR;
583 } else
584 unreachable("invalid shader selector type");
585
586 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
587
588 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
589 shader->selector->esgs_itemsize / 4);
590 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
591 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
592 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
593 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
594 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
595 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
596 S_00B328_DX10_CLAMP(1) |
597 S_00B328_FLOAT_MODE(shader->config.float_mode));
598 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
599 S_00B32C_USER_SGPR(num_user_sgprs) |
600 S_00B32C_OC_LDS_EN(oc_lds_en) |
601 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
602
603 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
604 si_set_tesseval_regs(sscreen, shader->selector, pm4);
605
606 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
607 }
608
609 struct gfx9_gs_info {
610 unsigned es_verts_per_subgroup;
611 unsigned gs_prims_per_subgroup;
612 unsigned gs_inst_prims_in_subgroup;
613 unsigned max_prims_per_subgroup;
614 unsigned lds_size;
615 };
616
617 static void gfx9_get_gs_info(struct si_shader_selector *es,
618 struct si_shader_selector *gs,
619 struct gfx9_gs_info *out)
620 {
621 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
622 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
623 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
624 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
625
626 /* All these are in dwords: */
627 /* We can't allow using the whole LDS, because GS waves compete with
628 * other shader stages for LDS space. */
629 const unsigned max_lds_size = 8 * 1024;
630 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
631 unsigned esgs_lds_size;
632
633 /* All these are per subgroup: */
634 const unsigned max_out_prims = 32 * 1024;
635 const unsigned max_es_verts = 255;
636 const unsigned ideal_gs_prims = 64;
637 unsigned max_gs_prims, gs_prims;
638 unsigned min_es_verts, es_verts, worst_case_es_verts;
639
640 assert(gs_num_invocations <= 32); /* GL maximum */
641
642 if (uses_adjacency || gs_num_invocations > 1)
643 max_gs_prims = 127 / gs_num_invocations;
644 else
645 max_gs_prims = 255;
646
647 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
648 * Make sure we don't go over the maximum value.
649 */
650 if (gs->gs_max_out_vertices > 0) {
651 max_gs_prims = MIN2(max_gs_prims,
652 max_out_prims /
653 (gs->gs_max_out_vertices * gs_num_invocations));
654 }
655 assert(max_gs_prims > 0);
656
657 /* If the primitive has adjacency, halve the number of vertices
658 * that will be reused in multiple primitives.
659 */
660 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
661
662 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
663 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
664
665 /* Compute ESGS LDS size based on the worst case number of ES vertices
666 * needed to create the target number of GS prims per subgroup.
667 */
668 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
669
670 /* If total LDS usage is too big, refactor partitions based on ratio
671 * of ESGS item sizes.
672 */
673 if (esgs_lds_size > max_lds_size) {
674 /* Our target GS Prims Per Subgroup was too large. Calculate
675 * the maximum number of GS Prims Per Subgroup that will fit
676 * into LDS, capped by the maximum that the hardware can support.
677 */
678 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
679 max_gs_prims);
680 assert(gs_prims > 0);
681 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
682 max_es_verts);
683
684 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
685 assert(esgs_lds_size <= max_lds_size);
686 }
687
688 /* Now calculate remaining ESGS information. */
689 if (esgs_lds_size)
690 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
691 else
692 es_verts = max_es_verts;
693
694 /* Vertices for adjacency primitives are not always reused, so restore
695 * it for ES_VERTS_PER_SUBGRP.
696 */
697 min_es_verts = gs->gs_input_verts_per_prim;
698
699 /* For normal primitives, the VGT only checks if they are past the ES
700 * verts per subgroup after allocating a full GS primitive and if they
701 * are, kick off a new subgroup. But if those additional ES verts are
702 * unique (e.g. not reused) we need to make sure there is enough LDS
703 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
704 */
705 es_verts -= min_es_verts - 1;
706
707 out->es_verts_per_subgroup = es_verts;
708 out->gs_prims_per_subgroup = gs_prims;
709 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
710 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
711 gs->gs_max_out_vertices;
712 out->lds_size = align(esgs_lds_size, 128) / 128;
713
714 assert(out->max_prims_per_subgroup <= max_out_prims);
715 }
716
717 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
718 {
719 struct si_shader_selector *sel = shader->selector;
720 const ubyte *num_components = sel->info.num_stream_output_components;
721 unsigned gs_num_invocations = sel->gs_num_invocations;
722 struct si_pm4_state *pm4;
723 uint64_t va;
724 unsigned max_stream = sel->max_gs_stream;
725 unsigned offset;
726
727 pm4 = si_get_shader_pm4_state(shader);
728 if (!pm4)
729 return;
730
731 offset = num_components[0] * sel->gs_max_out_vertices;
732 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, offset);
733 if (max_stream >= 1)
734 offset += num_components[1] * sel->gs_max_out_vertices;
735 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, offset);
736 if (max_stream >= 2)
737 offset += num_components[2] * sel->gs_max_out_vertices;
738 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, offset);
739 if (max_stream >= 3)
740 offset += num_components[3] * sel->gs_max_out_vertices;
741 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
742
743 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
744 assert(offset < (1 << 15));
745
746 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, sel->gs_max_out_vertices);
747
748 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, num_components[0]);
749 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? num_components[1] : 0);
750 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? num_components[2] : 0);
751 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? num_components[3] : 0);
752
753 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
754 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
755 S_028B90_ENABLE(gs_num_invocations > 0));
756
757 va = shader->bo->gpu_address;
758 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
759
760 if (sscreen->info.chip_class >= GFX9) {
761 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
762 unsigned es_type = shader->key.part.gs.es->type;
763 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
764 struct gfx9_gs_info gs_info;
765
766 if (es_type == PIPE_SHADER_VERTEX)
767 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
768 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
769 else if (es_type == PIPE_SHADER_TESS_EVAL)
770 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
771 else
772 unreachable("invalid shader selector type");
773
774 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
775 * VGPR[0:4] are always loaded.
776 */
777 if (sel->info.uses_invocationid)
778 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
779 else if (sel->info.uses_primid)
780 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
781 else if (input_prim >= PIPE_PRIM_TRIANGLES)
782 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
783 else
784 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
785
786 unsigned num_user_sgprs;
787 if (es_type == PIPE_SHADER_VERTEX)
788 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
789 else
790 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
791
792 gfx9_get_gs_info(shader->key.part.gs.es, sel, &gs_info);
793
794 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
795 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
796
797 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
798 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
799 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
800 S_00B228_DX10_CLAMP(1) |
801 S_00B228_FLOAT_MODE(shader->config.float_mode) |
802 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
803 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
804 S_00B22C_USER_SGPR(num_user_sgprs) |
805 S_00B22C_USER_SGPR_MSB(num_user_sgprs >> 5) |
806 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
807 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
808 S_00B22C_LDS_SIZE(gs_info.lds_size) |
809 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
810
811 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
812 S_028A44_ES_VERTS_PER_SUBGRP(gs_info.es_verts_per_subgroup) |
813 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info.gs_prims_per_subgroup) |
814 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info.gs_inst_prims_in_subgroup));
815 si_pm4_set_reg(pm4, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
816 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info.max_prims_per_subgroup));
817 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
818 shader->key.part.gs.es->esgs_itemsize / 4);
819
820 if (es_type == PIPE_SHADER_TESS_EVAL)
821 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
822
823 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
824 NULL, pm4);
825 } else {
826 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
827 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
828
829 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
830 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
831 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
832 S_00B228_DX10_CLAMP(1) |
833 S_00B228_FLOAT_MODE(shader->config.float_mode));
834 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
835 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
836 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
837 }
838 }
839
840 /**
841 * Compute the state for \p shader, which will run as a vertex shader on the
842 * hardware.
843 *
844 * If \p gs is non-NULL, it points to the geometry shader for which this shader
845 * is the copy shader.
846 */
847 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
848 struct si_shader_selector *gs)
849 {
850 const struct tgsi_shader_info *info = &shader->selector->info;
851 struct si_pm4_state *pm4;
852 unsigned num_user_sgprs;
853 unsigned nparams, vgpr_comp_cnt;
854 uint64_t va;
855 unsigned oc_lds_en;
856 unsigned window_space =
857 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
858 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
859
860 pm4 = si_get_shader_pm4_state(shader);
861 if (!pm4)
862 return;
863
864 /* We always write VGT_GS_MODE in the VS state, because every switch
865 * between different shader pipelines involving a different GS or no
866 * GS at all involves a switch of the VS (different GS use different
867 * copy shaders). On the other hand, when the API switches from a GS to
868 * no GS and then back to the same GS used originally, the GS state is
869 * not sent again.
870 */
871 if (!gs) {
872 unsigned mode = V_028A40_GS_OFF;
873
874 /* PrimID needs GS scenario A. */
875 if (enable_prim_id)
876 mode = V_028A40_GS_SCENARIO_A;
877
878 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, S_028A40_MODE(mode));
879 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
880 } else {
881 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
882 ac_vgt_gs_mode(gs->gs_max_out_vertices,
883 sscreen->info.chip_class));
884 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
885 }
886
887 if (sscreen->info.chip_class <= VI) {
888 /* Reuse needs to be set off if we write oViewport. */
889 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF,
890 S_028AB4_REUSE_OFF(info->writes_viewport_index));
891 }
892
893 va = shader->bo->gpu_address;
894 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
895
896 if (gs) {
897 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
898 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
899 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
900 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
901 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
902 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
903 */
904 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
905
906 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
907 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
908 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
909 } else {
910 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
911 }
912 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
913 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
914 num_user_sgprs = SI_TES_NUM_USER_SGPR;
915 } else
916 unreachable("invalid shader selector type");
917
918 /* VS is required to export at least one param. */
919 nparams = MAX2(shader->info.nr_param_exports, 1);
920 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
921 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
922
923 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
924 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
925 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
926 V_02870C_SPI_SHADER_4COMP :
927 V_02870C_SPI_SHADER_NONE) |
928 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
929 V_02870C_SPI_SHADER_4COMP :
930 V_02870C_SPI_SHADER_NONE) |
931 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
932 V_02870C_SPI_SHADER_4COMP :
933 V_02870C_SPI_SHADER_NONE));
934
935 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
936
937 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
938 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
939 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
940 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
941 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
942 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
943 S_00B128_DX10_CLAMP(1) |
944 S_00B128_FLOAT_MODE(shader->config.float_mode));
945 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
946 S_00B12C_USER_SGPR(num_user_sgprs) |
947 S_00B12C_OC_LDS_EN(oc_lds_en) |
948 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
949 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
950 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
951 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
952 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
953 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
954 if (window_space)
955 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
956 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
957 else
958 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
959 S_028818_VTX_W0_FMT(1) |
960 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
961 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
962 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
963
964 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
965 si_set_tesseval_regs(sscreen, shader->selector, pm4);
966
967 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
968 }
969
970 static unsigned si_get_ps_num_interp(struct si_shader *ps)
971 {
972 struct tgsi_shader_info *info = &ps->selector->info;
973 unsigned num_colors = !!(info->colors_read & 0x0f) +
974 !!(info->colors_read & 0xf0);
975 unsigned num_interp = ps->selector->info.num_inputs +
976 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
977
978 assert(num_interp <= 32);
979 return MIN2(num_interp, 32);
980 }
981
982 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
983 {
984 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
985 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
986
987 /* If the i-th target format is set, all previous target formats must
988 * be non-zero to avoid hangs.
989 */
990 for (i = 0; i < num_targets; i++)
991 if (!(value & (0xf << (i * 4))))
992 value |= V_028714_SPI_SHADER_32_R << (i * 4);
993
994 return value;
995 }
996
997 static void si_shader_ps(struct si_shader *shader)
998 {
999 struct tgsi_shader_info *info = &shader->selector->info;
1000 struct si_pm4_state *pm4;
1001 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1002 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1003 uint64_t va;
1004 unsigned input_ena = shader->config.spi_ps_input_ena;
1005
1006 /* we need to enable at least one of them, otherwise we hang the GPU */
1007 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1008 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1009 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1010 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1011 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1012 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1013 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1014 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1015 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1016 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1017 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1018 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1019 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1020 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1021
1022 /* Validate interpolation optimization flags (read as implications). */
1023 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1024 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1025 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1026 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1027 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1028 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1029 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1030 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1031 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1032 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1033 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1034 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1035 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1036 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1037 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1038 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1039 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1040 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1041
1042 /* Validate cases when the optimizations are off (read as implications). */
1043 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1044 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1045 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1046 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1047 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1048 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1049
1050 pm4 = si_get_shader_pm4_state(shader);
1051 if (!pm4)
1052 return;
1053
1054 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1055 * Possible vaules:
1056 * 0 -> Position = pixel center
1057 * 1 -> Position = pixel centroid
1058 * 2 -> Position = at sample position
1059 *
1060 * From GLSL 4.5 specification, section 7.1:
1061 * "The variable gl_FragCoord is available as an input variable from
1062 * within fragment shaders and it holds the window relative coordinates
1063 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1064 * value can be for any location within the pixel, or one of the
1065 * fragment samples. The use of centroid does not further restrict
1066 * this value to be inside the current primitive."
1067 *
1068 * Meaning that centroid has no effect and we can return anything within
1069 * the pixel. Thus, return the value at sample position, because that's
1070 * the most accurate one shaders can get.
1071 */
1072 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1073
1074 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1075 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1076 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1077
1078 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1079 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1080
1081 /* Ensure that some export memory is always allocated, for two reasons:
1082 *
1083 * 1) Correctness: The hardware ignores the EXEC mask if no export
1084 * memory is allocated, so KILL and alpha test do not work correctly
1085 * without this.
1086 * 2) Performance: Every shader needs at least a NULL export, even when
1087 * it writes no color/depth output. The NULL export instruction
1088 * stalls without this setting.
1089 *
1090 * Don't add this to CB_SHADER_MASK.
1091 */
1092 if (!spi_shader_col_format &&
1093 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1094 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1095
1096 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
1097 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
1098 shader->config.spi_ps_input_addr);
1099
1100 /* Set interpolation controls. */
1101 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1102
1103 /* Set registers. */
1104 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1105 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
1106
1107 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
1108 ac_get_spi_shader_z_format(info->writes_z,
1109 info->writes_stencil,
1110 info->writes_samplemask));
1111
1112 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
1113 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
1114
1115 va = shader->bo->gpu_address;
1116 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1117 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1118 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1119
1120 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
1121 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1122 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
1123 S_00B028_DX10_CLAMP(1) |
1124 S_00B028_FLOAT_MODE(shader->config.float_mode));
1125 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1126 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1127 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1128 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1129 }
1130
1131 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1132 struct si_shader *shader)
1133 {
1134 switch (shader->selector->type) {
1135 case PIPE_SHADER_VERTEX:
1136 if (shader->key.as_ls)
1137 si_shader_ls(sscreen, shader);
1138 else if (shader->key.as_es)
1139 si_shader_es(sscreen, shader);
1140 else
1141 si_shader_vs(sscreen, shader, NULL);
1142 break;
1143 case PIPE_SHADER_TESS_CTRL:
1144 si_shader_hs(sscreen, shader);
1145 break;
1146 case PIPE_SHADER_TESS_EVAL:
1147 if (shader->key.as_es)
1148 si_shader_es(sscreen, shader);
1149 else
1150 si_shader_vs(sscreen, shader, NULL);
1151 break;
1152 case PIPE_SHADER_GEOMETRY:
1153 si_shader_gs(sscreen, shader);
1154 break;
1155 case PIPE_SHADER_FRAGMENT:
1156 si_shader_ps(shader);
1157 break;
1158 default:
1159 assert(0);
1160 }
1161 }
1162
1163 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1164 {
1165 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1166 if (sctx->queued.named.dsa)
1167 return sctx->queued.named.dsa->alpha_func;
1168
1169 return PIPE_FUNC_ALWAYS;
1170 }
1171
1172 static void si_shader_selector_key_vs(struct si_context *sctx,
1173 struct si_shader_selector *vs,
1174 struct si_shader_key *key,
1175 struct si_vs_prolog_bits *prolog_key)
1176 {
1177 if (!sctx->vertex_elements)
1178 return;
1179
1180 prolog_key->instance_divisor_is_one =
1181 sctx->vertex_elements->instance_divisor_is_one;
1182 prolog_key->instance_divisor_is_fetched =
1183 sctx->vertex_elements->instance_divisor_is_fetched;
1184
1185 /* Prefer a monolithic shader to allow scheduling divisions around
1186 * VBO loads. */
1187 if (prolog_key->instance_divisor_is_fetched)
1188 key->opt.prefer_mono = 1;
1189
1190 unsigned count = MIN2(vs->info.num_inputs,
1191 sctx->vertex_elements->count);
1192 memcpy(key->mono.vs_fix_fetch, sctx->vertex_elements->fix_fetch, count);
1193 }
1194
1195 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1196 struct si_shader_selector *vs,
1197 struct si_shader_key *key)
1198 {
1199 struct si_shader_selector *ps = sctx->ps_shader.cso;
1200
1201 key->opt.clip_disable =
1202 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1203 (vs->info.clipdist_writemask ||
1204 vs->info.writes_clipvertex) &&
1205 !vs->info.culldist_writemask;
1206
1207 /* Find out if PS is disabled. */
1208 bool ps_disabled = true;
1209 if (ps) {
1210 const struct si_state_blend *blend = sctx->queued.named.blend;
1211 bool alpha_to_coverage = blend && blend->alpha_to_coverage;
1212 bool ps_modifies_zs = ps->info.uses_kill ||
1213 ps->info.writes_z ||
1214 ps->info.writes_stencil ||
1215 ps->info.writes_samplemask ||
1216 alpha_to_coverage ||
1217 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1218 unsigned ps_colormask = si_get_total_colormask(sctx);
1219
1220 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1221 (!ps_colormask &&
1222 !ps_modifies_zs &&
1223 !ps->info.writes_memory);
1224 }
1225
1226 /* Find out which VS outputs aren't used by the PS. */
1227 uint64_t outputs_written = vs->outputs_written;
1228 uint64_t inputs_read = 0;
1229
1230 /* ignore POSITION, PSIZE */
1231 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0) |
1232 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0))));
1233
1234 if (!ps_disabled) {
1235 inputs_read = ps->inputs_read;
1236 }
1237
1238 uint64_t linked = outputs_written & inputs_read;
1239
1240 key->opt.kill_outputs = ~linked & outputs_written;
1241 }
1242
1243 /* Compute the key for the hw shader variant */
1244 static inline void si_shader_selector_key(struct pipe_context *ctx,
1245 struct si_shader_selector *sel,
1246 struct si_shader_key *key)
1247 {
1248 struct si_context *sctx = (struct si_context *)ctx;
1249
1250 memset(key, 0, sizeof(*key));
1251
1252 switch (sel->type) {
1253 case PIPE_SHADER_VERTEX:
1254 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1255
1256 if (sctx->tes_shader.cso)
1257 key->as_ls = 1;
1258 else if (sctx->gs_shader.cso)
1259 key->as_es = 1;
1260 else {
1261 si_shader_selector_key_hw_vs(sctx, sel, key);
1262
1263 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1264 key->mono.u.vs_export_prim_id = 1;
1265 }
1266 break;
1267 case PIPE_SHADER_TESS_CTRL:
1268 if (sctx->b.chip_class >= GFX9) {
1269 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1270 key, &key->part.tcs.ls_prolog);
1271 key->part.tcs.ls = sctx->vs_shader.cso;
1272
1273 /* When the LS VGPR fix is needed, monolithic shaders
1274 * can:
1275 * - avoid initializing EXEC in both the LS prolog
1276 * and the LS main part when !vs_needs_prolog
1277 * - remove the fixup for unused input VGPRs
1278 */
1279 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1280
1281 /* The LS output / HS input layout can be communicated
1282 * directly instead of via user SGPRs for merged LS-HS.
1283 * The LS VGPR fix prefers this too.
1284 */
1285 key->opt.prefer_mono = 1;
1286 }
1287
1288 key->part.tcs.epilog.prim_mode =
1289 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1290 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1291 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1292 key->part.tcs.epilog.tes_reads_tess_factors =
1293 sctx->tes_shader.cso->info.reads_tess_factors;
1294
1295 if (sel == sctx->fixed_func_tcs_shader.cso)
1296 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1297 break;
1298 case PIPE_SHADER_TESS_EVAL:
1299 if (sctx->gs_shader.cso)
1300 key->as_es = 1;
1301 else {
1302 si_shader_selector_key_hw_vs(sctx, sel, key);
1303
1304 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1305 key->mono.u.vs_export_prim_id = 1;
1306 }
1307 break;
1308 case PIPE_SHADER_GEOMETRY:
1309 if (sctx->b.chip_class >= GFX9) {
1310 if (sctx->tes_shader.cso) {
1311 key->part.gs.es = sctx->tes_shader.cso;
1312 } else {
1313 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1314 key, &key->part.gs.vs_prolog);
1315 key->part.gs.es = sctx->vs_shader.cso;
1316 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1317 }
1318
1319 /* Merged ES-GS can have unbalanced wave usage.
1320 *
1321 * ES threads are per-vertex, while GS threads are
1322 * per-primitive. So without any amplification, there
1323 * are fewer GS threads than ES threads, which can result
1324 * in empty (no-op) GS waves. With too much amplification,
1325 * there are more GS threads than ES threads, which
1326 * can result in empty (no-op) ES waves.
1327 *
1328 * Non-monolithic shaders are implemented by setting EXEC
1329 * at the beginning of shader parts, and don't jump to
1330 * the end if EXEC is 0.
1331 *
1332 * Monolithic shaders use conditional blocks, so they can
1333 * jump and skip empty waves of ES or GS. So set this to
1334 * always use optimized variants, which are monolithic.
1335 */
1336 key->opt.prefer_mono = 1;
1337 }
1338 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1339 break;
1340 case PIPE_SHADER_FRAGMENT: {
1341 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1342 struct si_state_blend *blend = sctx->queued.named.blend;
1343
1344 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1345 sel->info.colors_written == 0x1)
1346 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1347
1348 if (blend) {
1349 /* Select the shader color format based on whether
1350 * blending or alpha are needed.
1351 */
1352 key->part.ps.epilog.spi_shader_col_format =
1353 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1354 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1355 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1356 sctx->framebuffer.spi_shader_col_format_blend) |
1357 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1358 sctx->framebuffer.spi_shader_col_format_alpha) |
1359 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1360 sctx->framebuffer.spi_shader_col_format);
1361 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1362
1363 /* The output for dual source blending should have
1364 * the same format as the first output.
1365 */
1366 if (blend->dual_src_blend)
1367 key->part.ps.epilog.spi_shader_col_format |=
1368 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1369 } else
1370 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1371
1372 /* If alpha-to-coverage is enabled, we have to export alpha
1373 * even if there is no color buffer.
1374 */
1375 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1376 blend && blend->alpha_to_coverage)
1377 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1378
1379 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1380 * to the range supported by the type if a channel has less
1381 * than 16 bits and the export format is 16_ABGR.
1382 */
1383 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII) {
1384 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1385 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1386 }
1387
1388 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1389 if (!key->part.ps.epilog.last_cbuf) {
1390 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1391 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1392 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1393 }
1394
1395 if (rs) {
1396 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
1397 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
1398 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
1399 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
1400
1401 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1402 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1403
1404 if (sctx->queued.named.blend) {
1405 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1406 rs->multisample_enable;
1407 }
1408
1409 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1410 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1411 (is_line && rs->line_smooth)) &&
1412 sctx->framebuffer.nr_samples <= 1;
1413 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1414
1415 if (sctx->ps_iter_samples > 1 &&
1416 sel->info.reads_samplemask) {
1417 key->part.ps.prolog.samplemask_log_ps_iter =
1418 util_logbase2(util_next_power_of_two(sctx->ps_iter_samples));
1419 }
1420
1421 if (rs->force_persample_interp &&
1422 rs->multisample_enable &&
1423 sctx->framebuffer.nr_samples > 1 &&
1424 sctx->ps_iter_samples > 1) {
1425 key->part.ps.prolog.force_persp_sample_interp =
1426 sel->info.uses_persp_center ||
1427 sel->info.uses_persp_centroid;
1428
1429 key->part.ps.prolog.force_linear_sample_interp =
1430 sel->info.uses_linear_center ||
1431 sel->info.uses_linear_centroid;
1432 } else if (rs->multisample_enable &&
1433 sctx->framebuffer.nr_samples > 1) {
1434 key->part.ps.prolog.bc_optimize_for_persp =
1435 sel->info.uses_persp_center &&
1436 sel->info.uses_persp_centroid;
1437 key->part.ps.prolog.bc_optimize_for_linear =
1438 sel->info.uses_linear_center &&
1439 sel->info.uses_linear_centroid;
1440 } else {
1441 /* Make sure SPI doesn't compute more than 1 pair
1442 * of (i,j), which is the optimization here. */
1443 key->part.ps.prolog.force_persp_center_interp =
1444 sel->info.uses_persp_center +
1445 sel->info.uses_persp_centroid +
1446 sel->info.uses_persp_sample > 1;
1447
1448 key->part.ps.prolog.force_linear_center_interp =
1449 sel->info.uses_linear_center +
1450 sel->info.uses_linear_centroid +
1451 sel->info.uses_linear_sample > 1;
1452
1453 if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
1454 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1455 }
1456 }
1457
1458 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1459
1460 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1461 if (sctx->ps_uses_fbfetch) {
1462 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
1463 struct pipe_resource *tex = cb0->texture;
1464
1465 /* 1D textures are allocated and used as 2D on GFX9. */
1466 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
1467 key->mono.u.ps.fbfetch_is_1D = sctx->b.chip_class != GFX9 &&
1468 (tex->target == PIPE_TEXTURE_1D ||
1469 tex->target == PIPE_TEXTURE_1D_ARRAY);
1470 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
1471 tex->target == PIPE_TEXTURE_2D_ARRAY ||
1472 tex->target == PIPE_TEXTURE_CUBE ||
1473 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
1474 tex->target == PIPE_TEXTURE_3D;
1475 }
1476 break;
1477 }
1478 default:
1479 assert(0);
1480 }
1481
1482 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
1483 memset(&key->opt, 0, sizeof(key->opt));
1484 }
1485
1486 static void si_build_shader_variant(struct si_shader *shader,
1487 int thread_index,
1488 bool low_priority)
1489 {
1490 struct si_shader_selector *sel = shader->selector;
1491 struct si_screen *sscreen = sel->screen;
1492 LLVMTargetMachineRef tm;
1493 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1494 int r;
1495
1496 if (thread_index >= 0) {
1497 if (low_priority) {
1498 assert(thread_index < ARRAY_SIZE(sscreen->tm_low_priority));
1499 tm = sscreen->tm_low_priority[thread_index];
1500 } else {
1501 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1502 tm = sscreen->tm[thread_index];
1503 }
1504 if (!debug->async)
1505 debug = NULL;
1506 } else {
1507 assert(!low_priority);
1508 tm = shader->compiler_ctx_state.tm;
1509 }
1510
1511 r = si_shader_create(sscreen, tm, shader, debug);
1512 if (unlikely(r)) {
1513 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1514 sel->type, r);
1515 shader->compilation_failed = true;
1516 return;
1517 }
1518
1519 if (shader->compiler_ctx_state.is_debug_context) {
1520 FILE *f = open_memstream(&shader->shader_log,
1521 &shader->shader_log_size);
1522 if (f) {
1523 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1524 fclose(f);
1525 }
1526 }
1527
1528 si_shader_init_pm4_state(sscreen, shader);
1529 }
1530
1531 static void si_build_shader_variant_low_priority(void *job, int thread_index)
1532 {
1533 struct si_shader *shader = (struct si_shader *)job;
1534
1535 assert(thread_index >= 0);
1536
1537 si_build_shader_variant(shader, thread_index, true);
1538 }
1539
1540 static const struct si_shader_key zeroed;
1541
1542 static bool si_check_missing_main_part(struct si_screen *sscreen,
1543 struct si_shader_selector *sel,
1544 struct si_compiler_ctx_state *compiler_state,
1545 struct si_shader_key *key)
1546 {
1547 struct si_shader **mainp = si_get_main_shader_part(sel, key);
1548
1549 if (!*mainp) {
1550 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1551
1552 if (!main_part)
1553 return false;
1554
1555 /* We can leave the fence as permanently signaled because the
1556 * main part becomes visible globally only after it has been
1557 * compiled. */
1558 util_queue_fence_init(&main_part->ready);
1559
1560 main_part->selector = sel;
1561 main_part->key.as_es = key->as_es;
1562 main_part->key.as_ls = key->as_ls;
1563
1564 if (si_compile_tgsi_shader(sscreen, compiler_state->tm,
1565 main_part, false,
1566 &compiler_state->debug) != 0) {
1567 FREE(main_part);
1568 return false;
1569 }
1570 *mainp = main_part;
1571 }
1572 return true;
1573 }
1574
1575 /* Select the hw shader variant depending on the current state. */
1576 static int si_shader_select_with_key(struct si_screen *sscreen,
1577 struct si_shader_ctx_state *state,
1578 struct si_compiler_ctx_state *compiler_state,
1579 struct si_shader_key *key,
1580 int thread_index)
1581 {
1582 struct si_shader_selector *sel = state->cso;
1583 struct si_shader_selector *previous_stage_sel = NULL;
1584 struct si_shader *current = state->current;
1585 struct si_shader *iter, *shader = NULL;
1586
1587 again:
1588 /* Check if we don't need to change anything.
1589 * This path is also used for most shaders that don't need multiple
1590 * variants, it will cost just a computation of the key and this
1591 * test. */
1592 if (likely(current &&
1593 memcmp(&current->key, key, sizeof(*key)) == 0)) {
1594 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
1595 if (current->is_optimized) {
1596 memset(&key->opt, 0, sizeof(key->opt));
1597 goto current_not_ready;
1598 }
1599
1600 util_queue_fence_wait(&current->ready);
1601 }
1602
1603 return current->compilation_failed ? -1 : 0;
1604 }
1605 current_not_ready:
1606
1607 /* This must be done before the mutex is locked, because async GS
1608 * compilation calls this function too, and therefore must enter
1609 * the mutex first.
1610 *
1611 * Only wait if we are in a draw call. Don't wait if we are
1612 * in a compiler thread.
1613 */
1614 if (thread_index < 0)
1615 util_queue_fence_wait(&sel->ready);
1616
1617 mtx_lock(&sel->mutex);
1618
1619 /* Find the shader variant. */
1620 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1621 /* Don't check the "current" shader. We checked it above. */
1622 if (current != iter &&
1623 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1624 mtx_unlock(&sel->mutex);
1625
1626 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
1627 /* If it's an optimized shader and its compilation has
1628 * been started but isn't done, use the unoptimized
1629 * shader so as not to cause a stall due to compilation.
1630 */
1631 if (iter->is_optimized) {
1632 memset(&key->opt, 0, sizeof(key->opt));
1633 goto again;
1634 }
1635
1636 util_queue_fence_wait(&iter->ready);
1637 }
1638
1639 if (iter->compilation_failed) {
1640 return -1; /* skip the draw call */
1641 }
1642
1643 state->current = iter;
1644 return 0;
1645 }
1646 }
1647
1648 /* Build a new shader. */
1649 shader = CALLOC_STRUCT(si_shader);
1650 if (!shader) {
1651 mtx_unlock(&sel->mutex);
1652 return -ENOMEM;
1653 }
1654
1655 util_queue_fence_init(&shader->ready);
1656
1657 shader->selector = sel;
1658 shader->key = *key;
1659 shader->compiler_ctx_state = *compiler_state;
1660
1661 /* If this is a merged shader, get the first shader's selector. */
1662 if (sscreen->info.chip_class >= GFX9) {
1663 if (sel->type == PIPE_SHADER_TESS_CTRL)
1664 previous_stage_sel = key->part.tcs.ls;
1665 else if (sel->type == PIPE_SHADER_GEOMETRY)
1666 previous_stage_sel = key->part.gs.es;
1667
1668 /* We need to wait for the previous shader. */
1669 if (previous_stage_sel && thread_index < 0)
1670 util_queue_fence_wait(&previous_stage_sel->ready);
1671 }
1672
1673 /* Compile the main shader part if it doesn't exist. This can happen
1674 * if the initial guess was wrong. */
1675 bool is_pure_monolithic =
1676 sscreen->use_monolithic_shaders ||
1677 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1678
1679 if (!is_pure_monolithic) {
1680 bool ok;
1681
1682 /* Make sure the main shader part is present. This is needed
1683 * for shaders that can be compiled as VS, LS, or ES, and only
1684 * one of them is compiled at creation.
1685 *
1686 * For merged shaders, check that the starting shader's main
1687 * part is present.
1688 */
1689 if (previous_stage_sel) {
1690 struct si_shader_key shader1_key = zeroed;
1691
1692 if (sel->type == PIPE_SHADER_TESS_CTRL)
1693 shader1_key.as_ls = 1;
1694 else if (sel->type == PIPE_SHADER_GEOMETRY)
1695 shader1_key.as_es = 1;
1696 else
1697 assert(0);
1698
1699 mtx_lock(&previous_stage_sel->mutex);
1700 ok = si_check_missing_main_part(sscreen,
1701 previous_stage_sel,
1702 compiler_state, &shader1_key);
1703 mtx_unlock(&previous_stage_sel->mutex);
1704 } else {
1705 ok = si_check_missing_main_part(sscreen, sel,
1706 compiler_state, key);
1707 }
1708 if (!ok) {
1709 FREE(shader);
1710 mtx_unlock(&sel->mutex);
1711 return -ENOMEM; /* skip the draw call */
1712 }
1713 }
1714
1715 /* Keep the reference to the 1st shader of merged shaders, so that
1716 * Gallium can't destroy it before we destroy the 2nd shader.
1717 *
1718 * Set sctx = NULL, because it's unused if we're not releasing
1719 * the shader, and we don't have any sctx here.
1720 */
1721 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
1722 previous_stage_sel);
1723
1724 /* Monolithic-only shaders don't make a distinction between optimized
1725 * and unoptimized. */
1726 shader->is_monolithic =
1727 is_pure_monolithic ||
1728 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1729
1730 shader->is_optimized =
1731 !is_pure_monolithic &&
1732 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1733
1734 /* If it's an optimized shader, compile it asynchronously. */
1735 if (shader->is_optimized &&
1736 !is_pure_monolithic &&
1737 thread_index < 0) {
1738 /* Compile it asynchronously. */
1739 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
1740 shader, &shader->ready,
1741 si_build_shader_variant_low_priority, NULL);
1742
1743 /* Add only after the ready fence was reset, to guard against a
1744 * race with si_bind_XX_shader. */
1745 if (!sel->last_variant) {
1746 sel->first_variant = shader;
1747 sel->last_variant = shader;
1748 } else {
1749 sel->last_variant->next_variant = shader;
1750 sel->last_variant = shader;
1751 }
1752
1753 /* Use the default (unoptimized) shader for now. */
1754 memset(&key->opt, 0, sizeof(key->opt));
1755 mtx_unlock(&sel->mutex);
1756 goto again;
1757 }
1758
1759 /* Reset the fence before adding to the variant list. */
1760 util_queue_fence_reset(&shader->ready);
1761
1762 if (!sel->last_variant) {
1763 sel->first_variant = shader;
1764 sel->last_variant = shader;
1765 } else {
1766 sel->last_variant->next_variant = shader;
1767 sel->last_variant = shader;
1768 }
1769
1770 mtx_unlock(&sel->mutex);
1771
1772 assert(!shader->is_optimized);
1773 si_build_shader_variant(shader, thread_index, false);
1774
1775 util_queue_fence_signal(&shader->ready);
1776
1777 if (!shader->compilation_failed)
1778 state->current = shader;
1779
1780 return shader->compilation_failed ? -1 : 0;
1781 }
1782
1783 static int si_shader_select(struct pipe_context *ctx,
1784 struct si_shader_ctx_state *state,
1785 struct si_compiler_ctx_state *compiler_state)
1786 {
1787 struct si_context *sctx = (struct si_context *)ctx;
1788 struct si_shader_key key;
1789
1790 si_shader_selector_key(ctx, state->cso, &key);
1791 return si_shader_select_with_key(sctx->screen, state, compiler_state,
1792 &key, -1);
1793 }
1794
1795 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1796 bool streamout,
1797 struct si_shader_key *key)
1798 {
1799 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1800
1801 switch (info->processor) {
1802 case PIPE_SHADER_VERTEX:
1803 switch (next_shader) {
1804 case PIPE_SHADER_GEOMETRY:
1805 key->as_es = 1;
1806 break;
1807 case PIPE_SHADER_TESS_CTRL:
1808 case PIPE_SHADER_TESS_EVAL:
1809 key->as_ls = 1;
1810 break;
1811 default:
1812 /* If POSITION isn't written, it can only be a HW VS
1813 * if streamout is used. If streamout isn't used,
1814 * assume that it's a HW LS. (the next shader is TCS)
1815 * This heuristic is needed for separate shader objects.
1816 */
1817 if (!info->writes_position && !streamout)
1818 key->as_ls = 1;
1819 }
1820 break;
1821
1822 case PIPE_SHADER_TESS_EVAL:
1823 if (next_shader == PIPE_SHADER_GEOMETRY ||
1824 !info->writes_position)
1825 key->as_es = 1;
1826 break;
1827 }
1828 }
1829
1830 /**
1831 * Compile the main shader part or the monolithic shader as part of
1832 * si_shader_selector initialization. Since it can be done asynchronously,
1833 * there is no way to report compile failures to applications.
1834 */
1835 static void si_init_shader_selector_async(void *job, int thread_index)
1836 {
1837 struct si_shader_selector *sel = (struct si_shader_selector *)job;
1838 struct si_screen *sscreen = sel->screen;
1839 LLVMTargetMachineRef tm;
1840 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
1841
1842 assert(!debug->debug_message || debug->async);
1843 assert(thread_index >= 0);
1844 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1845 tm = sscreen->tm[thread_index];
1846
1847 /* Compile the main shader part for use with a prolog and/or epilog.
1848 * If this fails, the driver will try to compile a monolithic shader
1849 * on demand.
1850 */
1851 if (!sscreen->use_monolithic_shaders) {
1852 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1853 void *ir_binary = NULL;
1854
1855 if (!shader) {
1856 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
1857 return;
1858 }
1859
1860 /* We can leave the fence signaled because use of the default
1861 * main part is guarded by the selector's ready fence. */
1862 util_queue_fence_init(&shader->ready);
1863
1864 shader->selector = sel;
1865 si_parse_next_shader_property(&sel->info,
1866 sel->so.num_outputs != 0,
1867 &shader->key);
1868
1869 if (sel->tokens || sel->nir)
1870 ir_binary = si_get_ir_binary(sel);
1871
1872 /* Try to load the shader from the shader cache. */
1873 mtx_lock(&sscreen->shader_cache_mutex);
1874
1875 if (ir_binary &&
1876 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
1877 mtx_unlock(&sscreen->shader_cache_mutex);
1878 si_shader_dump_stats_for_shader_db(shader, debug);
1879 } else {
1880 mtx_unlock(&sscreen->shader_cache_mutex);
1881
1882 /* Compile the shader if it hasn't been loaded from the cache. */
1883 if (si_compile_tgsi_shader(sscreen, tm, shader, false,
1884 debug) != 0) {
1885 FREE(shader);
1886 FREE(ir_binary);
1887 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
1888 return;
1889 }
1890
1891 if (ir_binary) {
1892 mtx_lock(&sscreen->shader_cache_mutex);
1893 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
1894 FREE(ir_binary);
1895 mtx_unlock(&sscreen->shader_cache_mutex);
1896 }
1897 }
1898
1899 *si_get_main_shader_part(sel, &shader->key) = shader;
1900
1901 /* Unset "outputs_written" flags for outputs converted to
1902 * DEFAULT_VAL, so that later inter-shader optimizations don't
1903 * try to eliminate outputs that don't exist in the final
1904 * shader.
1905 *
1906 * This is only done if non-monolithic shaders are enabled.
1907 */
1908 if ((sel->type == PIPE_SHADER_VERTEX ||
1909 sel->type == PIPE_SHADER_TESS_EVAL) &&
1910 !shader->key.as_ls &&
1911 !shader->key.as_es) {
1912 unsigned i;
1913
1914 for (i = 0; i < sel->info.num_outputs; i++) {
1915 unsigned offset = shader->info.vs_output_param_offset[i];
1916
1917 if (offset <= AC_EXP_PARAM_OFFSET_31)
1918 continue;
1919
1920 unsigned name = sel->info.output_semantic_name[i];
1921 unsigned index = sel->info.output_semantic_index[i];
1922 unsigned id;
1923
1924 switch (name) {
1925 case TGSI_SEMANTIC_GENERIC:
1926 /* don't process indices the function can't handle */
1927 if (index >= SI_MAX_IO_GENERIC)
1928 break;
1929 /* fall through */
1930 default:
1931 id = si_shader_io_get_unique_index(name, index);
1932 sel->outputs_written &= ~(1ull << id);
1933 break;
1934 case TGSI_SEMANTIC_POSITION: /* ignore these */
1935 case TGSI_SEMANTIC_PSIZE:
1936 case TGSI_SEMANTIC_CLIPVERTEX:
1937 case TGSI_SEMANTIC_EDGEFLAG:
1938 break;
1939 }
1940 }
1941 }
1942 }
1943
1944 /* The GS copy shader is always pre-compiled. */
1945 if (sel->type == PIPE_SHADER_GEOMETRY) {
1946 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, tm, sel, debug);
1947 if (!sel->gs_copy_shader) {
1948 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
1949 return;
1950 }
1951
1952 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
1953 }
1954 }
1955
1956 /* Return descriptor slot usage masks from the given shader info. */
1957 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
1958 uint32_t *const_and_shader_buffers,
1959 uint64_t *samplers_and_images)
1960 {
1961 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
1962
1963 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
1964 num_constbufs = util_last_bit(info->const_buffers_declared);
1965 /* two 8-byte images share one 16-byte slot */
1966 num_images = align(util_last_bit(info->images_declared), 2);
1967 num_samplers = util_last_bit(info->samplers_declared);
1968
1969 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
1970 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
1971 *const_and_shader_buffers =
1972 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
1973
1974 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
1975 start = si_get_image_slot(num_images - 1) / 2;
1976 *samplers_and_images =
1977 u_bit_consecutive64(start, num_images / 2 + num_samplers);
1978 }
1979
1980 static void *si_create_shader_selector(struct pipe_context *ctx,
1981 const struct pipe_shader_state *state)
1982 {
1983 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
1984 struct si_context *sctx = (struct si_context*)ctx;
1985 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
1986 int i;
1987
1988 if (!sel)
1989 return NULL;
1990
1991 pipe_reference_init(&sel->reference, 1);
1992 sel->screen = sscreen;
1993 sel->compiler_ctx_state.debug = sctx->debug;
1994 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
1995
1996 sel->so = state->stream_output;
1997
1998 if (state->type == PIPE_SHADER_IR_TGSI) {
1999 sel->tokens = tgsi_dup_tokens(state->tokens);
2000 if (!sel->tokens) {
2001 FREE(sel);
2002 return NULL;
2003 }
2004
2005 tgsi_scan_shader(state->tokens, &sel->info);
2006 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2007 } else {
2008 assert(state->type == PIPE_SHADER_IR_NIR);
2009
2010 sel->nir = state->ir.nir;
2011
2012 si_nir_scan_shader(sel->nir, &sel->info);
2013 si_nir_scan_tess_ctrl(sel->nir, &sel->info, &sel->tcs_info);
2014
2015 si_lower_nir(sel);
2016 }
2017
2018 sel->type = sel->info.processor;
2019 p_atomic_inc(&sscreen->num_shaders_created);
2020 si_get_active_slot_masks(&sel->info,
2021 &sel->active_const_and_shader_buffers,
2022 &sel->active_samplers_and_images);
2023
2024 /* Record which streamout buffers are enabled. */
2025 for (i = 0; i < sel->so.num_outputs; i++) {
2026 sel->enabled_streamout_buffer_mask |=
2027 (1 << sel->so.output[i].output_buffer) <<
2028 (sel->so.output[i].stream * 4);
2029 }
2030
2031 /* The prolog is a no-op if there are no inputs. */
2032 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2033 sel->info.num_inputs &&
2034 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2035
2036 sel->force_correct_derivs_after_kill =
2037 sel->type == PIPE_SHADER_FRAGMENT &&
2038 sel->info.uses_derivatives &&
2039 sel->info.uses_kill &&
2040 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2041
2042 /* Set which opcode uses which (i,j) pair. */
2043 if (sel->info.uses_persp_opcode_interp_centroid)
2044 sel->info.uses_persp_centroid = true;
2045
2046 if (sel->info.uses_linear_opcode_interp_centroid)
2047 sel->info.uses_linear_centroid = true;
2048
2049 if (sel->info.uses_persp_opcode_interp_offset ||
2050 sel->info.uses_persp_opcode_interp_sample)
2051 sel->info.uses_persp_center = true;
2052
2053 if (sel->info.uses_linear_opcode_interp_offset ||
2054 sel->info.uses_linear_opcode_interp_sample)
2055 sel->info.uses_linear_center = true;
2056
2057 switch (sel->type) {
2058 case PIPE_SHADER_GEOMETRY:
2059 sel->gs_output_prim =
2060 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2061 sel->gs_max_out_vertices =
2062 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2063 sel->gs_num_invocations =
2064 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2065 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2066 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2067 sel->gs_max_out_vertices;
2068
2069 sel->max_gs_stream = 0;
2070 for (i = 0; i < sel->so.num_outputs; i++)
2071 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2072 sel->so.output[i].stream);
2073
2074 sel->gs_input_verts_per_prim =
2075 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2076 break;
2077
2078 case PIPE_SHADER_TESS_CTRL:
2079 /* Always reserve space for these. */
2080 sel->patch_outputs_written |=
2081 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2082 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2083 /* fall through */
2084 case PIPE_SHADER_VERTEX:
2085 case PIPE_SHADER_TESS_EVAL:
2086 for (i = 0; i < sel->info.num_outputs; i++) {
2087 unsigned name = sel->info.output_semantic_name[i];
2088 unsigned index = sel->info.output_semantic_index[i];
2089
2090 switch (name) {
2091 case TGSI_SEMANTIC_TESSINNER:
2092 case TGSI_SEMANTIC_TESSOUTER:
2093 case TGSI_SEMANTIC_PATCH:
2094 sel->patch_outputs_written |=
2095 1ull << si_shader_io_get_unique_index_patch(name, index);
2096 break;
2097
2098 case TGSI_SEMANTIC_GENERIC:
2099 /* don't process indices the function can't handle */
2100 if (index >= SI_MAX_IO_GENERIC)
2101 break;
2102 /* fall through */
2103 default:
2104 sel->outputs_written |=
2105 1ull << si_shader_io_get_unique_index(name, index);
2106 break;
2107 case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */
2108 case TGSI_SEMANTIC_EDGEFLAG:
2109 break;
2110 }
2111 }
2112 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2113
2114 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2115 * conflicts, i.e. each vertex will start at a different bank.
2116 */
2117 if (sctx->b.chip_class >= GFX9)
2118 sel->esgs_itemsize += 4;
2119 break;
2120
2121 case PIPE_SHADER_FRAGMENT:
2122 for (i = 0; i < sel->info.num_inputs; i++) {
2123 unsigned name = sel->info.input_semantic_name[i];
2124 unsigned index = sel->info.input_semantic_index[i];
2125
2126 switch (name) {
2127 case TGSI_SEMANTIC_GENERIC:
2128 /* don't process indices the function can't handle */
2129 if (index >= SI_MAX_IO_GENERIC)
2130 break;
2131 /* fall through */
2132 default:
2133 sel->inputs_read |=
2134 1ull << si_shader_io_get_unique_index(name, index);
2135 break;
2136 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2137 break;
2138 }
2139 }
2140
2141 for (i = 0; i < 8; i++)
2142 if (sel->info.colors_written & (1 << i))
2143 sel->colors_written_4bit |= 0xf << (4 * i);
2144
2145 for (i = 0; i < sel->info.num_inputs; i++) {
2146 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2147 int index = sel->info.input_semantic_index[i];
2148 sel->color_attr_index[index] = i;
2149 }
2150 }
2151 break;
2152 }
2153
2154 /* PA_CL_VS_OUT_CNTL */
2155 bool misc_vec_ena =
2156 sel->info.writes_psize || sel->info.writes_edgeflag ||
2157 sel->info.writes_layer || sel->info.writes_viewport_index;
2158 sel->pa_cl_vs_out_cntl =
2159 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2160 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2161 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2162 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2163 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2164 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2165 sel->clipdist_mask = sel->info.writes_clipvertex ?
2166 SIX_BITS : sel->info.clipdist_writemask;
2167 sel->culldist_mask = sel->info.culldist_writemask <<
2168 sel->info.num_written_clipdistance;
2169
2170 /* DB_SHADER_CONTROL */
2171 sel->db_shader_control =
2172 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2173 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2174 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2175 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2176
2177 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2178 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2179 sel->db_shader_control |=
2180 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2181 break;
2182 case TGSI_FS_DEPTH_LAYOUT_LESS:
2183 sel->db_shader_control |=
2184 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2185 break;
2186 }
2187
2188 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2189 *
2190 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2191 * --|-----------|------------|------------|--------------------|-------------------|-------------
2192 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2193 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2194 * 2 | false | true | n/a | LateZ | 1 | 0
2195 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2196 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2197 *
2198 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2199 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2200 *
2201 * Don't use ReZ without profiling !!!
2202 *
2203 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2204 * shaders.
2205 */
2206 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2207 /* Cases 3, 4. */
2208 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2209 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2210 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2211 } else if (sel->info.writes_memory) {
2212 /* Case 2. */
2213 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2214 S_02880C_EXEC_ON_HIER_FAIL(1);
2215 } else {
2216 /* Case 1. */
2217 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2218 }
2219
2220 (void) mtx_init(&sel->mutex, mtx_plain);
2221 util_queue_fence_init(&sel->ready);
2222
2223 struct util_async_debug_callback async_debug;
2224 bool wait =
2225 (sctx->debug.debug_message && !sctx->debug.async) ||
2226 sctx->is_debug ||
2227 si_can_dump_shader(sscreen, sel->info.processor);
2228
2229 if (wait) {
2230 u_async_debug_init(&async_debug);
2231 sel->compiler_ctx_state.debug = async_debug.base;
2232 }
2233
2234 util_queue_add_job(&sscreen->shader_compiler_queue, sel,
2235 &sel->ready, si_init_shader_selector_async,
2236 NULL);
2237
2238 if (wait) {
2239 util_queue_fence_wait(&sel->ready);
2240 u_async_debug_drain(&async_debug, &sctx->debug);
2241 u_async_debug_cleanup(&async_debug);
2242 }
2243
2244 return sel;
2245 }
2246
2247 static void si_update_streamout_state(struct si_context *sctx)
2248 {
2249 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2250
2251 if (!shader_with_so)
2252 return;
2253
2254 sctx->streamout.enabled_stream_buffers_mask =
2255 shader_with_so->enabled_streamout_buffer_mask;
2256 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2257 }
2258
2259 static void si_update_clip_regs(struct si_context *sctx,
2260 struct si_shader_selector *old_hw_vs,
2261 struct si_shader *old_hw_vs_variant,
2262 struct si_shader_selector *next_hw_vs,
2263 struct si_shader *next_hw_vs_variant)
2264 {
2265 if (next_hw_vs &&
2266 (!old_hw_vs ||
2267 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2268 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2269 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2270 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2271 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2272 !old_hw_vs_variant ||
2273 !next_hw_vs_variant ||
2274 old_hw_vs_variant->key.opt.clip_disable !=
2275 next_hw_vs_variant->key.opt.clip_disable))
2276 si_mark_atom_dirty(sctx, &sctx->clip_regs);
2277 }
2278
2279 static void si_update_common_shader_state(struct si_context *sctx)
2280 {
2281 sctx->uses_bindless_samplers =
2282 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2283 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2284 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2285 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2286 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2287 sctx->uses_bindless_images =
2288 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2289 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2290 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2291 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2292 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2293 sctx->do_update_shaders = true;
2294 }
2295
2296 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2297 {
2298 struct si_context *sctx = (struct si_context *)ctx;
2299 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2300 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2301 struct si_shader_selector *sel = state;
2302
2303 if (sctx->vs_shader.cso == sel)
2304 return;
2305
2306 sctx->vs_shader.cso = sel;
2307 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2308 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2309
2310 si_update_common_shader_state(sctx);
2311 si_update_vs_viewport_state(sctx);
2312 si_set_active_descriptors_for_shader(sctx, sel);
2313 si_update_streamout_state(sctx);
2314 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2315 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2316 }
2317
2318 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2319 {
2320 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2321 (sctx->tes_shader.cso &&
2322 sctx->tes_shader.cso->info.uses_primid) ||
2323 (sctx->tcs_shader.cso &&
2324 sctx->tcs_shader.cso->info.uses_primid) ||
2325 (sctx->gs_shader.cso &&
2326 sctx->gs_shader.cso->info.uses_primid) ||
2327 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2328 sctx->ps_shader.cso->info.uses_primid);
2329 }
2330
2331 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2332 {
2333 struct si_context *sctx = (struct si_context *)ctx;
2334 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2335 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2336 struct si_shader_selector *sel = state;
2337 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2338
2339 if (sctx->gs_shader.cso == sel)
2340 return;
2341
2342 sctx->gs_shader.cso = sel;
2343 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2344 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2345
2346 si_update_common_shader_state(sctx);
2347 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2348
2349 if (enable_changed) {
2350 si_shader_change_notify(sctx);
2351 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2352 si_update_tess_uses_prim_id(sctx);
2353 }
2354 si_update_vs_viewport_state(sctx);
2355 si_set_active_descriptors_for_shader(sctx, sel);
2356 si_update_streamout_state(sctx);
2357 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2358 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2359 }
2360
2361 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2362 {
2363 struct si_context *sctx = (struct si_context *)ctx;
2364 struct si_shader_selector *sel = state;
2365 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2366
2367 if (sctx->tcs_shader.cso == sel)
2368 return;
2369
2370 sctx->tcs_shader.cso = sel;
2371 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
2372 si_update_tess_uses_prim_id(sctx);
2373
2374 si_update_common_shader_state(sctx);
2375
2376 if (enable_changed)
2377 sctx->last_tcs = NULL; /* invalidate derived tess state */
2378
2379 si_set_active_descriptors_for_shader(sctx, sel);
2380 }
2381
2382 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
2383 {
2384 struct si_context *sctx = (struct si_context *)ctx;
2385 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2386 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2387 struct si_shader_selector *sel = state;
2388 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
2389
2390 if (sctx->tes_shader.cso == sel)
2391 return;
2392
2393 sctx->tes_shader.cso = sel;
2394 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
2395 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
2396 si_update_tess_uses_prim_id(sctx);
2397
2398 si_update_common_shader_state(sctx);
2399 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2400
2401 if (enable_changed) {
2402 si_shader_change_notify(sctx);
2403 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
2404 }
2405 si_update_vs_viewport_state(sctx);
2406 si_set_active_descriptors_for_shader(sctx, sel);
2407 si_update_streamout_state(sctx);
2408 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2409 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2410 }
2411
2412 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2413 {
2414 struct si_context *sctx = (struct si_context *)ctx;
2415 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
2416 struct si_shader_selector *sel = state;
2417
2418 /* skip if supplied shader is one already in use */
2419 if (old_sel == sel)
2420 return;
2421
2422 sctx->ps_shader.cso = sel;
2423 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
2424
2425 si_update_common_shader_state(sctx);
2426 if (sel) {
2427 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2428 si_update_tess_uses_prim_id(sctx);
2429
2430 if (!old_sel ||
2431 old_sel->info.colors_written != sel->info.colors_written)
2432 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2433
2434 if (sctx->screen->has_out_of_order_rast &&
2435 (!old_sel ||
2436 old_sel->info.writes_memory != sel->info.writes_memory ||
2437 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
2438 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
2439 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2440 }
2441 si_set_active_descriptors_for_shader(sctx, sel);
2442 si_update_ps_colorbuf0_slot(sctx);
2443 }
2444
2445 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
2446 {
2447 if (shader->is_optimized) {
2448 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
2449 &shader->ready);
2450 }
2451
2452 util_queue_fence_destroy(&shader->ready);
2453
2454 if (shader->pm4) {
2455 switch (shader->selector->type) {
2456 case PIPE_SHADER_VERTEX:
2457 if (shader->key.as_ls) {
2458 assert(sctx->b.chip_class <= VI);
2459 si_pm4_delete_state(sctx, ls, shader->pm4);
2460 } else if (shader->key.as_es) {
2461 assert(sctx->b.chip_class <= VI);
2462 si_pm4_delete_state(sctx, es, shader->pm4);
2463 } else {
2464 si_pm4_delete_state(sctx, vs, shader->pm4);
2465 }
2466 break;
2467 case PIPE_SHADER_TESS_CTRL:
2468 si_pm4_delete_state(sctx, hs, shader->pm4);
2469 break;
2470 case PIPE_SHADER_TESS_EVAL:
2471 if (shader->key.as_es) {
2472 assert(sctx->b.chip_class <= VI);
2473 si_pm4_delete_state(sctx, es, shader->pm4);
2474 } else {
2475 si_pm4_delete_state(sctx, vs, shader->pm4);
2476 }
2477 break;
2478 case PIPE_SHADER_GEOMETRY:
2479 if (shader->is_gs_copy_shader)
2480 si_pm4_delete_state(sctx, vs, shader->pm4);
2481 else
2482 si_pm4_delete_state(sctx, gs, shader->pm4);
2483 break;
2484 case PIPE_SHADER_FRAGMENT:
2485 si_pm4_delete_state(sctx, ps, shader->pm4);
2486 break;
2487 }
2488 }
2489
2490 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
2491 si_shader_destroy(shader);
2492 free(shader);
2493 }
2494
2495 void si_destroy_shader_selector(struct si_context *sctx,
2496 struct si_shader_selector *sel)
2497 {
2498 struct si_shader *p = sel->first_variant, *c;
2499 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
2500 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
2501 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
2502 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
2503 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
2504 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
2505 };
2506
2507 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
2508
2509 if (current_shader[sel->type]->cso == sel) {
2510 current_shader[sel->type]->cso = NULL;
2511 current_shader[sel->type]->current = NULL;
2512 }
2513
2514 while (p) {
2515 c = p->next_variant;
2516 si_delete_shader(sctx, p);
2517 p = c;
2518 }
2519
2520 if (sel->main_shader_part)
2521 si_delete_shader(sctx, sel->main_shader_part);
2522 if (sel->main_shader_part_ls)
2523 si_delete_shader(sctx, sel->main_shader_part_ls);
2524 if (sel->main_shader_part_es)
2525 si_delete_shader(sctx, sel->main_shader_part_es);
2526 if (sel->gs_copy_shader)
2527 si_delete_shader(sctx, sel->gs_copy_shader);
2528
2529 util_queue_fence_destroy(&sel->ready);
2530 mtx_destroy(&sel->mutex);
2531 free(sel->tokens);
2532 ralloc_free(sel->nir);
2533 free(sel);
2534 }
2535
2536 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
2537 {
2538 struct si_context *sctx = (struct si_context *)ctx;
2539 struct si_shader_selector *sel = (struct si_shader_selector *)state;
2540
2541 si_shader_selector_reference(sctx, &sel, NULL);
2542 }
2543
2544 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
2545 struct si_shader *vs, unsigned name,
2546 unsigned index, unsigned interpolate)
2547 {
2548 struct tgsi_shader_info *vsinfo = &vs->selector->info;
2549 unsigned j, offset, ps_input_cntl = 0;
2550
2551 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
2552 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
2553 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2554
2555 if (name == TGSI_SEMANTIC_PCOORD ||
2556 (name == TGSI_SEMANTIC_TEXCOORD &&
2557 sctx->sprite_coord_enable & (1 << index))) {
2558 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
2559 }
2560
2561 for (j = 0; j < vsinfo->num_outputs; j++) {
2562 if (name == vsinfo->output_semantic_name[j] &&
2563 index == vsinfo->output_semantic_index[j]) {
2564 offset = vs->info.vs_output_param_offset[j];
2565
2566 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2567 /* The input is loaded from parameter memory. */
2568 ps_input_cntl |= S_028644_OFFSET(offset);
2569 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2570 if (offset == AC_EXP_PARAM_UNDEFINED) {
2571 /* This can happen with depth-only rendering. */
2572 offset = 0;
2573 } else {
2574 /* The input is a DEFAULT_VAL constant. */
2575 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2576 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2577 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2578 }
2579
2580 ps_input_cntl = S_028644_OFFSET(0x20) |
2581 S_028644_DEFAULT_VAL(offset);
2582 }
2583 break;
2584 }
2585 }
2586
2587 if (name == TGSI_SEMANTIC_PRIMID)
2588 /* PrimID is written after the last output. */
2589 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
2590 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2591 /* No corresponding output found, load defaults into input.
2592 * Don't set any other bits.
2593 * (FLAT_SHADE=1 completely changes behavior) */
2594 ps_input_cntl = S_028644_OFFSET(0x20);
2595 /* D3D 9 behaviour. GL is undefined */
2596 if (name == TGSI_SEMANTIC_COLOR && index == 0)
2597 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
2598 }
2599 return ps_input_cntl;
2600 }
2601
2602 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
2603 {
2604 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2605 struct si_shader *ps = sctx->ps_shader.current;
2606 struct si_shader *vs = si_get_vs_state(sctx);
2607 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
2608 unsigned i, num_interp, num_written = 0, bcol_interp[2];
2609
2610 if (!ps || !ps->selector->info.num_inputs)
2611 return;
2612
2613 num_interp = si_get_ps_num_interp(ps);
2614 assert(num_interp > 0);
2615 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
2616
2617 for (i = 0; i < psinfo->num_inputs; i++) {
2618 unsigned name = psinfo->input_semantic_name[i];
2619 unsigned index = psinfo->input_semantic_index[i];
2620 unsigned interpolate = psinfo->input_interpolate[i];
2621
2622 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
2623 interpolate));
2624 num_written++;
2625
2626 if (name == TGSI_SEMANTIC_COLOR) {
2627 assert(index < ARRAY_SIZE(bcol_interp));
2628 bcol_interp[index] = interpolate;
2629 }
2630 }
2631
2632 if (ps->key.part.ps.prolog.color_two_side) {
2633 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
2634
2635 for (i = 0; i < 2; i++) {
2636 if (!(psinfo->colors_read & (0xf << (i * 4))))
2637 continue;
2638
2639 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
2640 i, bcol_interp[i]));
2641 num_written++;
2642 }
2643 }
2644 assert(num_interp == num_written);
2645 }
2646
2647 /**
2648 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2649 */
2650 static void si_init_config_add_vgt_flush(struct si_context *sctx)
2651 {
2652 if (sctx->init_config_has_vgt_flush)
2653 return;
2654
2655 /* Done by Vulkan before VGT_FLUSH. */
2656 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2657 si_pm4_cmd_add(sctx->init_config,
2658 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2659 si_pm4_cmd_end(sctx->init_config, false);
2660
2661 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2662 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2663 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2664 si_pm4_cmd_end(sctx->init_config, false);
2665 sctx->init_config_has_vgt_flush = true;
2666 }
2667
2668 /* Initialize state related to ESGS / GSVS ring buffers */
2669 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2670 {
2671 struct si_shader_selector *es =
2672 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2673 struct si_shader_selector *gs = sctx->gs_shader.cso;
2674 struct si_pm4_state *pm4;
2675
2676 /* Chip constants. */
2677 unsigned num_se = sctx->screen->info.max_se;
2678 unsigned wave_size = 64;
2679 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2680 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2681 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2682 */
2683 unsigned gs_vertex_reuse = (sctx->b.chip_class >= VI ? 32 : 16) * num_se;
2684 unsigned alignment = 256 * num_se;
2685 /* The maximum size is 63.999 MB per SE. */
2686 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2687
2688 /* Calculate the minimum size. */
2689 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
2690 wave_size, alignment);
2691
2692 /* These are recommended sizes, not minimum sizes. */
2693 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2694 es->esgs_itemsize * gs->gs_input_verts_per_prim;
2695 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2696 gs->max_gsvs_emit_size;
2697
2698 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2699 esgs_ring_size = align(esgs_ring_size, alignment);
2700 gsvs_ring_size = align(gsvs_ring_size, alignment);
2701
2702 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2703 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2704
2705 /* Some rings don't have to be allocated if shaders don't use them.
2706 * (e.g. no varyings between ES and GS or GS and VS)
2707 *
2708 * GFX9 doesn't have the ESGS ring.
2709 */
2710 bool update_esgs = sctx->b.chip_class <= VI &&
2711 esgs_ring_size &&
2712 (!sctx->esgs_ring ||
2713 sctx->esgs_ring->width0 < esgs_ring_size);
2714 bool update_gsvs = gsvs_ring_size &&
2715 (!sctx->gsvs_ring ||
2716 sctx->gsvs_ring->width0 < gsvs_ring_size);
2717
2718 if (!update_esgs && !update_gsvs)
2719 return true;
2720
2721 if (update_esgs) {
2722 pipe_resource_reference(&sctx->esgs_ring, NULL);
2723 sctx->esgs_ring =
2724 si_aligned_buffer_create(sctx->b.b.screen,
2725 R600_RESOURCE_FLAG_UNMAPPABLE,
2726 PIPE_USAGE_DEFAULT,
2727 esgs_ring_size, alignment);
2728 if (!sctx->esgs_ring)
2729 return false;
2730 }
2731
2732 if (update_gsvs) {
2733 pipe_resource_reference(&sctx->gsvs_ring, NULL);
2734 sctx->gsvs_ring =
2735 si_aligned_buffer_create(sctx->b.b.screen,
2736 R600_RESOURCE_FLAG_UNMAPPABLE,
2737 PIPE_USAGE_DEFAULT,
2738 gsvs_ring_size, alignment);
2739 if (!sctx->gsvs_ring)
2740 return false;
2741 }
2742
2743 /* Create the "init_config_gs_rings" state. */
2744 pm4 = CALLOC_STRUCT(si_pm4_state);
2745 if (!pm4)
2746 return false;
2747
2748 if (sctx->b.chip_class >= CIK) {
2749 if (sctx->esgs_ring) {
2750 assert(sctx->b.chip_class <= VI);
2751 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2752 sctx->esgs_ring->width0 / 256);
2753 }
2754 if (sctx->gsvs_ring)
2755 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2756 sctx->gsvs_ring->width0 / 256);
2757 } else {
2758 if (sctx->esgs_ring)
2759 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2760 sctx->esgs_ring->width0 / 256);
2761 if (sctx->gsvs_ring)
2762 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2763 sctx->gsvs_ring->width0 / 256);
2764 }
2765
2766 /* Set the state. */
2767 if (sctx->init_config_gs_rings)
2768 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
2769 sctx->init_config_gs_rings = pm4;
2770
2771 if (!sctx->init_config_has_vgt_flush) {
2772 si_init_config_add_vgt_flush(sctx);
2773 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2774 }
2775
2776 /* Flush the context to re-emit both init_config states. */
2777 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2778 si_context_gfx_flush(sctx, PIPE_FLUSH_ASYNC, NULL);
2779
2780 /* Set ring bindings. */
2781 if (sctx->esgs_ring) {
2782 assert(sctx->b.chip_class <= VI);
2783 si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
2784 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2785 true, true, 4, 64, 0);
2786 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
2787 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2788 false, false, 0, 0, 0);
2789 }
2790 if (sctx->gsvs_ring) {
2791 si_set_ring_buffer(&sctx->b.b, SI_RING_GSVS,
2792 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
2793 false, false, 0, 0, 0);
2794 }
2795
2796 return true;
2797 }
2798
2799 static void si_shader_lock(struct si_shader *shader)
2800 {
2801 mtx_lock(&shader->selector->mutex);
2802 if (shader->previous_stage_sel) {
2803 assert(shader->previous_stage_sel != shader->selector);
2804 mtx_lock(&shader->previous_stage_sel->mutex);
2805 }
2806 }
2807
2808 static void si_shader_unlock(struct si_shader *shader)
2809 {
2810 if (shader->previous_stage_sel)
2811 mtx_unlock(&shader->previous_stage_sel->mutex);
2812 mtx_unlock(&shader->selector->mutex);
2813 }
2814
2815 /**
2816 * @returns 1 if \p sel has been updated to use a new scratch buffer
2817 * 0 if not
2818 * < 0 if there was a failure
2819 */
2820 static int si_update_scratch_buffer(struct si_context *sctx,
2821 struct si_shader *shader)
2822 {
2823 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
2824 int r;
2825
2826 if (!shader)
2827 return 0;
2828
2829 /* This shader doesn't need a scratch buffer */
2830 if (shader->config.scratch_bytes_per_wave == 0)
2831 return 0;
2832
2833 /* Prevent race conditions when updating:
2834 * - si_shader::scratch_bo
2835 * - si_shader::binary::code
2836 * - si_shader::previous_stage::binary::code.
2837 */
2838 si_shader_lock(shader);
2839
2840 /* This shader is already configured to use the current
2841 * scratch buffer. */
2842 if (shader->scratch_bo == sctx->scratch_buffer) {
2843 si_shader_unlock(shader);
2844 return 0;
2845 }
2846
2847 assert(sctx->scratch_buffer);
2848
2849 if (shader->previous_stage)
2850 si_shader_apply_scratch_relocs(shader->previous_stage, scratch_va);
2851
2852 si_shader_apply_scratch_relocs(shader, scratch_va);
2853
2854 /* Replace the shader bo with a new bo that has the relocs applied. */
2855 r = si_shader_binary_upload(sctx->screen, shader);
2856 if (r) {
2857 si_shader_unlock(shader);
2858 return r;
2859 }
2860
2861 /* Update the shader state to use the new shader bo. */
2862 si_shader_init_pm4_state(sctx->screen, shader);
2863
2864 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
2865
2866 si_shader_unlock(shader);
2867 return 1;
2868 }
2869
2870 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
2871 {
2872 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
2873 }
2874
2875 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
2876 {
2877 return shader ? shader->config.scratch_bytes_per_wave : 0;
2878 }
2879
2880 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
2881 {
2882 if (!sctx->tes_shader.cso)
2883 return NULL; /* tessellation disabled */
2884
2885 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
2886 sctx->fixed_func_tcs_shader.current;
2887 }
2888
2889 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
2890 {
2891 unsigned bytes = 0;
2892
2893 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
2894 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
2895 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
2896 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
2897
2898 if (sctx->tes_shader.cso) {
2899 struct si_shader *tcs = si_get_tcs_current(sctx);
2900
2901 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
2902 }
2903 return bytes;
2904 }
2905
2906 static bool si_update_scratch_relocs(struct si_context *sctx)
2907 {
2908 struct si_shader *tcs = si_get_tcs_current(sctx);
2909 int r;
2910
2911 /* Update the shaders, so that they are using the latest scratch.
2912 * The scratch buffer may have been changed since these shaders were
2913 * last used, so we still need to try to update them, even if they
2914 * require scratch buffers smaller than the current size.
2915 */
2916 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
2917 if (r < 0)
2918 return false;
2919 if (r == 1)
2920 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2921
2922 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
2923 if (r < 0)
2924 return false;
2925 if (r == 1)
2926 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2927
2928 r = si_update_scratch_buffer(sctx, tcs);
2929 if (r < 0)
2930 return false;
2931 if (r == 1)
2932 si_pm4_bind_state(sctx, hs, tcs->pm4);
2933
2934 /* VS can be bound as LS, ES, or VS. */
2935 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
2936 if (r < 0)
2937 return false;
2938 if (r == 1) {
2939 if (sctx->tes_shader.current)
2940 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2941 else if (sctx->gs_shader.current)
2942 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2943 else
2944 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2945 }
2946
2947 /* TES can be bound as ES or VS. */
2948 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
2949 if (r < 0)
2950 return false;
2951 if (r == 1) {
2952 if (sctx->gs_shader.current)
2953 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2954 else
2955 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2956 }
2957
2958 return true;
2959 }
2960
2961 static bool si_update_spi_tmpring_size(struct si_context *sctx)
2962 {
2963 unsigned current_scratch_buffer_size =
2964 si_get_current_scratch_buffer_size(sctx);
2965 unsigned scratch_bytes_per_wave =
2966 si_get_max_scratch_bytes_per_wave(sctx);
2967 unsigned scratch_needed_size = scratch_bytes_per_wave *
2968 sctx->scratch_waves;
2969 unsigned spi_tmpring_size;
2970
2971 if (scratch_needed_size > 0) {
2972 if (scratch_needed_size > current_scratch_buffer_size) {
2973 /* Create a bigger scratch buffer */
2974 r600_resource_reference(&sctx->scratch_buffer, NULL);
2975
2976 sctx->scratch_buffer = (struct r600_resource*)
2977 si_aligned_buffer_create(&sctx->screen->b,
2978 R600_RESOURCE_FLAG_UNMAPPABLE,
2979 PIPE_USAGE_DEFAULT,
2980 scratch_needed_size, 256);
2981 if (!sctx->scratch_buffer)
2982 return false;
2983
2984 si_mark_atom_dirty(sctx, &sctx->scratch_state);
2985 si_context_add_resource_size(&sctx->b.b,
2986 &sctx->scratch_buffer->b.b);
2987 }
2988
2989 if (!si_update_scratch_relocs(sctx))
2990 return false;
2991 }
2992
2993 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
2994 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
2995 "scratch size should already be aligned correctly.");
2996
2997 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
2998 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
2999 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3000 sctx->spi_tmpring_size = spi_tmpring_size;
3001 si_mark_atom_dirty(sctx, &sctx->scratch_state);
3002 }
3003 return true;
3004 }
3005
3006 static void si_init_tess_factor_ring(struct si_context *sctx)
3007 {
3008 assert(!sctx->tess_rings);
3009
3010 /* The address must be aligned to 2^19, because the shader only
3011 * receives the high 13 bits.
3012 */
3013 sctx->tess_rings = si_aligned_buffer_create(sctx->b.b.screen,
3014 R600_RESOURCE_FLAG_32BIT,
3015 PIPE_USAGE_DEFAULT,
3016 sctx->screen->tess_offchip_ring_size +
3017 sctx->screen->tess_factor_ring_size,
3018 1 << 19);
3019 if (!sctx->tess_rings)
3020 return;
3021
3022 si_init_config_add_vgt_flush(sctx);
3023
3024 si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_rings),
3025 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3026
3027 uint64_t factor_va = r600_resource(sctx->tess_rings)->gpu_address +
3028 sctx->screen->tess_offchip_ring_size;
3029
3030 /* Append these registers to the init config state. */
3031 if (sctx->b.chip_class >= CIK) {
3032 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3033 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3034 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3035 factor_va >> 8);
3036 if (sctx->b.chip_class >= GFX9)
3037 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3038 S_030944_BASE_HI(factor_va >> 40));
3039 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3040 sctx->screen->vgt_hs_offchip_param);
3041 } else {
3042 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3043 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3044 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3045 factor_va >> 8);
3046 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3047 sctx->screen->vgt_hs_offchip_param);
3048 }
3049
3050 /* Flush the context to re-emit the init_config state.
3051 * This is done only once in a lifetime of a context.
3052 */
3053 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3054 sctx->b.initial_gfx_cs_size = 0; /* force flush */
3055 si_context_gfx_flush(sctx, PIPE_FLUSH_ASYNC, NULL);
3056 }
3057
3058 /**
3059 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
3060 * VS passes its outputs to TES directly, so the fixed-function shader only
3061 * has to write TESSOUTER and TESSINNER.
3062 */
3063 static void si_generate_fixed_func_tcs(struct si_context *sctx)
3064 {
3065 struct ureg_src outer, inner;
3066 struct ureg_dst tessouter, tessinner;
3067 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
3068
3069 if (!ureg)
3070 return; /* if we get here, we're screwed */
3071
3072 assert(!sctx->fixed_func_tcs_shader.cso);
3073
3074 outer = ureg_DECL_system_value(ureg,
3075 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
3076 inner = ureg_DECL_system_value(ureg,
3077 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
3078
3079 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
3080 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
3081
3082 ureg_MOV(ureg, tessouter, outer);
3083 ureg_MOV(ureg, tessinner, inner);
3084 ureg_END(ureg);
3085
3086 sctx->fixed_func_tcs_shader.cso =
3087 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
3088 }
3089
3090 static void si_update_vgt_shader_config(struct si_context *sctx)
3091 {
3092 /* Calculate the index of the config.
3093 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3094 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
3095 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
3096
3097 if (!*pm4) {
3098 uint32_t stages = 0;
3099
3100 *pm4 = CALLOC_STRUCT(si_pm4_state);
3101
3102 if (sctx->tes_shader.cso) {
3103 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3104 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3105
3106 if (sctx->gs_shader.cso)
3107 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3108 S_028B54_GS_EN(1) |
3109 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3110 else
3111 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3112 } else if (sctx->gs_shader.cso) {
3113 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3114 S_028B54_GS_EN(1) |
3115 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3116 }
3117
3118 if (sctx->b.chip_class >= GFX9)
3119 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3120
3121 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3122 }
3123 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3124 }
3125
3126 bool si_update_shaders(struct si_context *sctx)
3127 {
3128 struct pipe_context *ctx = (struct pipe_context*)sctx;
3129 struct si_compiler_ctx_state compiler_state;
3130 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3131 struct si_shader *old_vs = si_get_vs_state(sctx);
3132 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3133 struct si_shader *old_ps = sctx->ps_shader.current;
3134 unsigned old_spi_shader_col_format =
3135 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3136 int r;
3137
3138 compiler_state.tm = sctx->tm;
3139 compiler_state.debug = sctx->debug;
3140 compiler_state.is_debug_context = sctx->is_debug;
3141
3142 /* Update stages before GS. */
3143 if (sctx->tes_shader.cso) {
3144 if (!sctx->tess_rings) {
3145 si_init_tess_factor_ring(sctx);
3146 if (!sctx->tess_rings)
3147 return false;
3148 }
3149
3150 /* VS as LS */
3151 if (sctx->b.chip_class <= VI) {
3152 r = si_shader_select(ctx, &sctx->vs_shader,
3153 &compiler_state);
3154 if (r)
3155 return false;
3156 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3157 }
3158
3159 if (sctx->tcs_shader.cso) {
3160 r = si_shader_select(ctx, &sctx->tcs_shader,
3161 &compiler_state);
3162 if (r)
3163 return false;
3164 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3165 } else {
3166 if (!sctx->fixed_func_tcs_shader.cso) {
3167 si_generate_fixed_func_tcs(sctx);
3168 if (!sctx->fixed_func_tcs_shader.cso)
3169 return false;
3170 }
3171
3172 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3173 &compiler_state);
3174 if (r)
3175 return false;
3176 si_pm4_bind_state(sctx, hs,
3177 sctx->fixed_func_tcs_shader.current->pm4);
3178 }
3179
3180 if (sctx->gs_shader.cso) {
3181 /* TES as ES */
3182 if (sctx->b.chip_class <= VI) {
3183 r = si_shader_select(ctx, &sctx->tes_shader,
3184 &compiler_state);
3185 if (r)
3186 return false;
3187 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3188 }
3189 } else {
3190 /* TES as VS */
3191 r = si_shader_select(ctx, &sctx->tes_shader,
3192 &compiler_state);
3193 if (r)
3194 return false;
3195 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3196 }
3197 } else if (sctx->gs_shader.cso) {
3198 if (sctx->b.chip_class <= VI) {
3199 /* VS as ES */
3200 r = si_shader_select(ctx, &sctx->vs_shader,
3201 &compiler_state);
3202 if (r)
3203 return false;
3204 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3205
3206 si_pm4_bind_state(sctx, ls, NULL);
3207 si_pm4_bind_state(sctx, hs, NULL);
3208 }
3209 } else {
3210 /* VS as VS */
3211 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
3212 if (r)
3213 return false;
3214 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3215 si_pm4_bind_state(sctx, ls, NULL);
3216 si_pm4_bind_state(sctx, hs, NULL);
3217 }
3218
3219 /* Update GS. */
3220 if (sctx->gs_shader.cso) {
3221 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
3222 if (r)
3223 return false;
3224 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3225 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3226
3227 if (!si_update_gs_ring_buffers(sctx))
3228 return false;
3229 } else {
3230 si_pm4_bind_state(sctx, gs, NULL);
3231 if (sctx->b.chip_class <= VI)
3232 si_pm4_bind_state(sctx, es, NULL);
3233 }
3234
3235 si_update_vgt_shader_config(sctx);
3236
3237 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3238 si_mark_atom_dirty(sctx, &sctx->clip_regs);
3239
3240 if (sctx->ps_shader.cso) {
3241 unsigned db_shader_control;
3242
3243 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
3244 if (r)
3245 return false;
3246 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3247
3248 db_shader_control =
3249 sctx->ps_shader.cso->db_shader_control |
3250 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3251
3252 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3253 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3254 sctx->flatshade != rs->flatshade) {
3255 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3256 sctx->flatshade = rs->flatshade;
3257 si_mark_atom_dirty(sctx, &sctx->spi_map);
3258 }
3259
3260 if (sctx->screen->rbplus_allowed &&
3261 si_pm4_state_changed(sctx, ps) &&
3262 (!old_ps ||
3263 old_spi_shader_col_format !=
3264 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3265 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
3266
3267 if (sctx->ps_db_shader_control != db_shader_control) {
3268 sctx->ps_db_shader_control = db_shader_control;
3269 si_mark_atom_dirty(sctx, &sctx->db_render_state);
3270 if (sctx->screen->dpbb_allowed)
3271 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
3272 }
3273
3274 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3275 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3276 si_mark_atom_dirty(sctx, &sctx->msaa_config);
3277
3278 if (sctx->b.chip_class == SI)
3279 si_mark_atom_dirty(sctx, &sctx->db_render_state);
3280
3281 if (sctx->framebuffer.nr_samples <= 1)
3282 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
3283 }
3284 }
3285
3286 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3287 si_pm4_state_enabled_and_changed(sctx, hs) ||
3288 si_pm4_state_enabled_and_changed(sctx, es) ||
3289 si_pm4_state_enabled_and_changed(sctx, gs) ||
3290 si_pm4_state_enabled_and_changed(sctx, vs) ||
3291 si_pm4_state_enabled_and_changed(sctx, ps)) {
3292 if (!si_update_spi_tmpring_size(sctx))
3293 return false;
3294 }
3295
3296 if (sctx->b.chip_class >= CIK) {
3297 if (si_pm4_state_enabled_and_changed(sctx, ls))
3298 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3299 else if (!sctx->queued.named.ls)
3300 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3301
3302 if (si_pm4_state_enabled_and_changed(sctx, hs))
3303 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3304 else if (!sctx->queued.named.hs)
3305 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3306
3307 if (si_pm4_state_enabled_and_changed(sctx, es))
3308 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
3309 else if (!sctx->queued.named.es)
3310 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
3311
3312 if (si_pm4_state_enabled_and_changed(sctx, gs))
3313 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
3314 else if (!sctx->queued.named.gs)
3315 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
3316
3317 if (si_pm4_state_enabled_and_changed(sctx, vs))
3318 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
3319 else if (!sctx->queued.named.vs)
3320 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
3321
3322 if (si_pm4_state_enabled_and_changed(sctx, ps))
3323 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
3324 else if (!sctx->queued.named.ps)
3325 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
3326 }
3327
3328 sctx->do_update_shaders = false;
3329 return true;
3330 }
3331
3332 static void si_emit_scratch_state(struct si_context *sctx,
3333 struct r600_atom *atom)
3334 {
3335 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3336
3337 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3338 sctx->spi_tmpring_size);
3339
3340 if (sctx->scratch_buffer) {
3341 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
3342 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3343 RADEON_PRIO_SCRATCH_BUFFER);
3344 }
3345 }
3346
3347 void *si_get_blit_vs(struct si_context *sctx, enum blitter_attrib_type type,
3348 unsigned num_layers)
3349 {
3350 struct pipe_context *pipe = &sctx->b.b;
3351 unsigned vs_blit_property;
3352 void **vs;
3353
3354 switch (type) {
3355 case UTIL_BLITTER_ATTRIB_NONE:
3356 vs = num_layers > 1 ? &sctx->vs_blit_pos_layered :
3357 &sctx->vs_blit_pos;
3358 vs_blit_property = SI_VS_BLIT_SGPRS_POS;
3359 break;
3360 case UTIL_BLITTER_ATTRIB_COLOR:
3361 vs = num_layers > 1 ? &sctx->vs_blit_color_layered :
3362 &sctx->vs_blit_color;
3363 vs_blit_property = SI_VS_BLIT_SGPRS_POS_COLOR;
3364 break;
3365 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
3366 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
3367 assert(num_layers == 1);
3368 vs = &sctx->vs_blit_texcoord;
3369 vs_blit_property = SI_VS_BLIT_SGPRS_POS_TEXCOORD;
3370 break;
3371 default:
3372 assert(0);
3373 return NULL;
3374 }
3375 if (*vs)
3376 return *vs;
3377
3378 struct ureg_program *ureg = ureg_create(PIPE_SHADER_VERTEX);
3379 if (!ureg)
3380 return NULL;
3381
3382 /* Tell the shader to load VS inputs from SGPRs: */
3383 ureg_property(ureg, TGSI_PROPERTY_VS_BLIT_SGPRS, vs_blit_property);
3384 ureg_property(ureg, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION, true);
3385
3386 /* This is just a pass-through shader with 1-3 MOV instructions. */
3387 ureg_MOV(ureg,
3388 ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0),
3389 ureg_DECL_vs_input(ureg, 0));
3390
3391 if (type != UTIL_BLITTER_ATTRIB_NONE) {
3392 ureg_MOV(ureg,
3393 ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, 0),
3394 ureg_DECL_vs_input(ureg, 1));
3395 }
3396
3397 if (num_layers > 1) {
3398 struct ureg_src instance_id =
3399 ureg_DECL_system_value(ureg, TGSI_SEMANTIC_INSTANCEID, 0);
3400 struct ureg_dst layer =
3401 ureg_DECL_output(ureg, TGSI_SEMANTIC_LAYER, 0);
3402
3403 ureg_MOV(ureg, ureg_writemask(layer, TGSI_WRITEMASK_X),
3404 ureg_scalar(instance_id, TGSI_SWIZZLE_X));
3405 }
3406 ureg_END(ureg);
3407
3408 *vs = ureg_create_shader_and_destroy(ureg, pipe);
3409 return *vs;
3410 }
3411
3412 void si_init_shader_functions(struct si_context *sctx)
3413 {
3414 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
3415 si_init_atom(sctx, &sctx->scratch_state, &sctx->atoms.s.scratch_state,
3416 si_emit_scratch_state);
3417
3418 sctx->b.b.create_vs_state = si_create_shader_selector;
3419 sctx->b.b.create_tcs_state = si_create_shader_selector;
3420 sctx->b.b.create_tes_state = si_create_shader_selector;
3421 sctx->b.b.create_gs_state = si_create_shader_selector;
3422 sctx->b.b.create_fs_state = si_create_shader_selector;
3423
3424 sctx->b.b.bind_vs_state = si_bind_vs_shader;
3425 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
3426 sctx->b.b.bind_tes_state = si_bind_tes_shader;
3427 sctx->b.b.bind_gs_state = si_bind_gs_shader;
3428 sctx->b.b.bind_fs_state = si_bind_ps_shader;
3429
3430 sctx->b.b.delete_vs_state = si_delete_shader_selector;
3431 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
3432 sctx->b.b.delete_tes_state = si_delete_shader_selector;
3433 sctx->b.b.delete_gs_state = si_delete_shader_selector;
3434 sctx->b.b.delete_fs_state = si_delete_shader_selector;
3435 }