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radeonsi:optimizing SET_CONTEXT_REG for shaders vgt_vertex_reuse
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
45 * size as integer.
46 */
47 void *si_get_ir_binary(struct si_shader_selector *sel)
48 {
49 struct blob blob;
50 unsigned ir_size;
51 void *ir_binary;
52
53 if (sel->tokens) {
54 ir_binary = sel->tokens;
55 ir_size = tgsi_num_tokens(sel->tokens) *
56 sizeof(struct tgsi_token);
57 } else {
58 assert(sel->nir);
59
60 blob_init(&blob);
61 nir_serialize(&blob, sel->nir);
62 ir_binary = blob.data;
63 ir_size = blob.size;
64 }
65
66 unsigned size = 4 + ir_size + sizeof(sel->so);
67 char *result = (char*)MALLOC(size);
68 if (!result)
69 return NULL;
70
71 *((uint32_t*)result) = size;
72 memcpy(result + 4, ir_binary, ir_size);
73 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
74
75 if (sel->nir)
76 blob_finish(&blob);
77
78 return result;
79 }
80
81 /** Copy "data" to "ptr" and return the next dword following copied data. */
82 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
83 {
84 /* data may be NULL if size == 0 */
85 if (size)
86 memcpy(ptr, data, size);
87 ptr += DIV_ROUND_UP(size, 4);
88 return ptr;
89 }
90
91 /** Read data from "ptr". Return the next dword following the data. */
92 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
93 {
94 memcpy(data, ptr, size);
95 ptr += DIV_ROUND_UP(size, 4);
96 return ptr;
97 }
98
99 /**
100 * Write the size as uint followed by the data. Return the next dword
101 * following the copied data.
102 */
103 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
104 {
105 *ptr++ = size;
106 return write_data(ptr, data, size);
107 }
108
109 /**
110 * Read the size as uint followed by the data. Return both via parameters.
111 * Return the next dword following the data.
112 */
113 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
114 {
115 *size = *ptr++;
116 assert(*data == NULL);
117 if (!*size)
118 return ptr;
119 *data = malloc(*size);
120 return read_data(ptr, *data, *size);
121 }
122
123 /**
124 * Return the shader binary in a buffer. The first 4 bytes contain its size
125 * as integer.
126 */
127 static void *si_get_shader_binary(struct si_shader *shader)
128 {
129 /* There is always a size of data followed by the data itself. */
130 unsigned relocs_size = shader->binary.reloc_count *
131 sizeof(shader->binary.relocs[0]);
132 unsigned disasm_size = shader->binary.disasm_string ?
133 strlen(shader->binary.disasm_string) + 1 : 0;
134 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
135 strlen(shader->binary.llvm_ir_string) + 1 : 0;
136 unsigned size =
137 4 + /* total size */
138 4 + /* CRC32 of the data below */
139 align(sizeof(shader->config), 4) +
140 align(sizeof(shader->info), 4) +
141 4 + align(shader->binary.code_size, 4) +
142 4 + align(shader->binary.rodata_size, 4) +
143 4 + align(relocs_size, 4) +
144 4 + align(disasm_size, 4) +
145 4 + align(llvm_ir_size, 4);
146 void *buffer = CALLOC(1, size);
147 uint32_t *ptr = (uint32_t*)buffer;
148
149 if (!buffer)
150 return NULL;
151
152 *ptr++ = size;
153 ptr++; /* CRC32 is calculated at the end. */
154
155 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
156 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
157 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
158 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
159 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
160 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
161 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
162 assert((char *)ptr - (char *)buffer == size);
163
164 /* Compute CRC32. */
165 ptr = (uint32_t*)buffer;
166 ptr++;
167 *ptr = util_hash_crc32(ptr + 1, size - 8);
168
169 return buffer;
170 }
171
172 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
173 {
174 uint32_t *ptr = (uint32_t*)binary;
175 uint32_t size = *ptr++;
176 uint32_t crc32 = *ptr++;
177 unsigned chunk_size;
178
179 if (util_hash_crc32(ptr, size - 8) != crc32) {
180 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
181 return false;
182 }
183
184 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
185 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
186 ptr = read_chunk(ptr, (void**)&shader->binary.code,
187 &shader->binary.code_size);
188 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
189 &shader->binary.rodata_size);
190 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
191 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
192 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
193 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
194
195 return true;
196 }
197
198 /**
199 * Insert a shader into the cache. It's assumed the shader is not in the cache.
200 * Use si_shader_cache_load_shader before calling this.
201 *
202 * Returns false on failure, in which case the ir_binary should be freed.
203 */
204 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
205 struct si_shader *shader,
206 bool insert_into_disk_cache)
207 {
208 void *hw_binary;
209 struct hash_entry *entry;
210 uint8_t key[CACHE_KEY_SIZE];
211
212 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
213 if (entry)
214 return false; /* already added */
215
216 hw_binary = si_get_shader_binary(shader);
217 if (!hw_binary)
218 return false;
219
220 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
221 hw_binary) == NULL) {
222 FREE(hw_binary);
223 return false;
224 }
225
226 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
227 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
228 *((uint32_t *)ir_binary), key);
229 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
230 *((uint32_t *) hw_binary), NULL);
231 }
232
233 return true;
234 }
235
236 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
237 struct si_shader *shader)
238 {
239 struct hash_entry *entry =
240 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
241 if (!entry) {
242 if (sscreen->disk_shader_cache) {
243 unsigned char sha1[CACHE_KEY_SIZE];
244 size_t tg_size = *((uint32_t *) ir_binary);
245
246 disk_cache_compute_key(sscreen->disk_shader_cache,
247 ir_binary, tg_size, sha1);
248
249 size_t binary_size;
250 uint8_t *buffer =
251 disk_cache_get(sscreen->disk_shader_cache,
252 sha1, &binary_size);
253 if (!buffer)
254 return false;
255
256 if (binary_size < sizeof(uint32_t) ||
257 *((uint32_t*)buffer) != binary_size) {
258 /* Something has gone wrong discard the item
259 * from the cache and rebuild/link from
260 * source.
261 */
262 assert(!"Invalid radeonsi shader disk cache "
263 "item!");
264
265 disk_cache_remove(sscreen->disk_shader_cache,
266 sha1);
267 free(buffer);
268
269 return false;
270 }
271
272 if (!si_load_shader_binary(shader, buffer)) {
273 free(buffer);
274 return false;
275 }
276 free(buffer);
277
278 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
279 shader, false))
280 FREE(ir_binary);
281 } else {
282 return false;
283 }
284 } else {
285 if (si_load_shader_binary(shader, entry->data))
286 FREE(ir_binary);
287 else
288 return false;
289 }
290 p_atomic_inc(&sscreen->num_shader_cache_hits);
291 return true;
292 }
293
294 static uint32_t si_shader_cache_key_hash(const void *key)
295 {
296 /* The first dword is the key size. */
297 return util_hash_crc32(key, *(uint32_t*)key);
298 }
299
300 static bool si_shader_cache_key_equals(const void *a, const void *b)
301 {
302 uint32_t *keya = (uint32_t*)a;
303 uint32_t *keyb = (uint32_t*)b;
304
305 /* The first dword is the key size. */
306 if (*keya != *keyb)
307 return false;
308
309 return memcmp(keya, keyb, *keya) == 0;
310 }
311
312 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
313 {
314 FREE((void*)entry->key);
315 FREE(entry->data);
316 }
317
318 bool si_init_shader_cache(struct si_screen *sscreen)
319 {
320 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
321 sscreen->shader_cache =
322 _mesa_hash_table_create(NULL,
323 si_shader_cache_key_hash,
324 si_shader_cache_key_equals);
325
326 return sscreen->shader_cache != NULL;
327 }
328
329 void si_destroy_shader_cache(struct si_screen *sscreen)
330 {
331 if (sscreen->shader_cache)
332 _mesa_hash_table_destroy(sscreen->shader_cache,
333 si_destroy_shader_cache_entry);
334 mtx_destroy(&sscreen->shader_cache_mutex);
335 }
336
337 /* SHADER STATES */
338
339 static void si_set_tesseval_regs(struct si_screen *sscreen,
340 struct si_shader_selector *tes,
341 struct si_pm4_state *pm4)
342 {
343 struct tgsi_shader_info *info = &tes->info;
344 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
345 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
346 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
347 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
348 unsigned type, partitioning, topology, distribution_mode;
349
350 switch (tes_prim_mode) {
351 case PIPE_PRIM_LINES:
352 type = V_028B6C_TESS_ISOLINE;
353 break;
354 case PIPE_PRIM_TRIANGLES:
355 type = V_028B6C_TESS_TRIANGLE;
356 break;
357 case PIPE_PRIM_QUADS:
358 type = V_028B6C_TESS_QUAD;
359 break;
360 default:
361 assert(0);
362 return;
363 }
364
365 switch (tes_spacing) {
366 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
367 partitioning = V_028B6C_PART_FRAC_ODD;
368 break;
369 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
370 partitioning = V_028B6C_PART_FRAC_EVEN;
371 break;
372 case PIPE_TESS_SPACING_EQUAL:
373 partitioning = V_028B6C_PART_INTEGER;
374 break;
375 default:
376 assert(0);
377 return;
378 }
379
380 if (tes_point_mode)
381 topology = V_028B6C_OUTPUT_POINT;
382 else if (tes_prim_mode == PIPE_PRIM_LINES)
383 topology = V_028B6C_OUTPUT_LINE;
384 else if (tes_vertex_order_cw)
385 /* for some reason, this must be the other way around */
386 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
387 else
388 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
389
390 if (sscreen->has_distributed_tess) {
391 if (sscreen->info.family == CHIP_FIJI ||
392 sscreen->info.family >= CHIP_POLARIS10)
393 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
394 else
395 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
396 } else
397 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
398
399 assert(pm4->shader);
400 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
401 S_028B6C_PARTITIONING(partitioning) |
402 S_028B6C_TOPOLOGY(topology) |
403 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
404 }
405
406 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
407 * whether the "fractional odd" tessellation spacing is used.
408 *
409 * Possible VGT configurations and which state should set the register:
410 *
411 * Reg set in | VGT shader configuration | Value
412 * ------------------------------------------------------
413 * VS as VS | VS | 30
414 * VS as ES | ES -> GS -> VS | 30
415 * TES as VS | LS -> HS -> VS | 14 or 30
416 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
417 *
418 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
419 */
420 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
421 struct si_shader_selector *sel,
422 struct si_shader *shader,
423 struct si_pm4_state *pm4)
424 {
425 unsigned type = sel->type;
426
427 if (sscreen->info.family < CHIP_POLARIS10)
428 return;
429
430 /* VS as VS, or VS as ES: */
431 if ((type == PIPE_SHADER_VERTEX &&
432 (!shader ||
433 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
434 /* TES as VS, or TES as ES: */
435 type == PIPE_SHADER_TESS_EVAL) {
436 unsigned vtx_reuse_depth = 30;
437
438 if (type == PIPE_SHADER_TESS_EVAL &&
439 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
440 PIPE_TESS_SPACING_FRACTIONAL_ODD)
441 vtx_reuse_depth = 14;
442
443 assert(pm4->shader);
444 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
445 }
446 }
447
448 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
449 {
450 if (shader->pm4)
451 si_pm4_clear_state(shader->pm4);
452 else
453 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
454
455 if (shader->pm4) {
456 shader->pm4->shader = shader;
457 return shader->pm4;
458 } else {
459 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
460 return NULL;
461 }
462 }
463
464 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
465 {
466 /* Add the pointer to VBO descriptors. */
467 if (HAVE_32BIT_POINTERS) {
468 return num_always_on_user_sgprs + 1;
469 } else {
470 assert(num_always_on_user_sgprs % 2 == 0);
471 return num_always_on_user_sgprs + 2;
472 }
473 }
474
475 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
476 {
477 struct si_pm4_state *pm4;
478 unsigned vgpr_comp_cnt;
479 uint64_t va;
480
481 assert(sscreen->info.chip_class <= VI);
482
483 pm4 = si_get_shader_pm4_state(shader);
484 if (!pm4)
485 return;
486
487 va = shader->bo->gpu_address;
488 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
489
490 /* We need at least 2 components for LS.
491 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
492 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
493 */
494 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
495
496 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
497 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
498
499 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
500 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
501 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
502 S_00B528_DX10_CLAMP(1) |
503 S_00B528_FLOAT_MODE(shader->config.float_mode);
504 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
505 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
506 }
507
508 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
509 {
510 struct si_pm4_state *pm4;
511 uint64_t va;
512 unsigned ls_vgpr_comp_cnt = 0;
513
514 pm4 = si_get_shader_pm4_state(shader);
515 if (!pm4)
516 return;
517
518 va = shader->bo->gpu_address;
519 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
520
521 if (sscreen->info.chip_class >= GFX9) {
522 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
523 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
524
525 /* We need at least 2 components for LS.
526 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
527 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
528 */
529 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
530
531 unsigned num_user_sgprs =
532 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
533
534 shader->config.rsrc2 =
535 S_00B42C_USER_SGPR(num_user_sgprs) |
536 S_00B42C_USER_SGPR_MSB(num_user_sgprs >> 5) |
537 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
538 } else {
539 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
540 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
541
542 shader->config.rsrc2 =
543 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
544 S_00B42C_OC_LDS_EN(1) |
545 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
546 }
547
548 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
549 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
550 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
551 S_00B428_DX10_CLAMP(1) |
552 S_00B428_FLOAT_MODE(shader->config.float_mode) |
553 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
554
555 if (sscreen->info.chip_class <= VI) {
556 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
557 shader->config.rsrc2);
558 }
559 }
560
561 static void si_emit_shader_es(struct si_context *sctx)
562 {
563 struct si_shader *shader = sctx->queued.named.es->shader;
564
565 if (!shader)
566 return;
567
568 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
569 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
570 shader->selector->esgs_itemsize / 4);
571
572 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
573 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
574 SI_TRACKED_VGT_TF_PARAM,
575 shader->vgt_tf_param);
576
577 if (shader->vgt_vertex_reuse_block_cntl)
578 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
579 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
580 shader->vgt_vertex_reuse_block_cntl);
581 }
582
583 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
584 {
585 struct si_pm4_state *pm4;
586 unsigned num_user_sgprs;
587 unsigned vgpr_comp_cnt;
588 uint64_t va;
589 unsigned oc_lds_en;
590
591 assert(sscreen->info.chip_class <= VI);
592
593 pm4 = si_get_shader_pm4_state(shader);
594 if (!pm4)
595 return;
596
597 pm4->atom.emit = si_emit_shader_es;
598 va = shader->bo->gpu_address;
599 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
600
601 if (shader->selector->type == PIPE_SHADER_VERTEX) {
602 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
603 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
604 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
605 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
606 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
607 num_user_sgprs = SI_TES_NUM_USER_SGPR;
608 } else
609 unreachable("invalid shader selector type");
610
611 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
612
613 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
614 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
615 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
616 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
617 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
618 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
619 S_00B328_DX10_CLAMP(1) |
620 S_00B328_FLOAT_MODE(shader->config.float_mode));
621 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
622 S_00B32C_USER_SGPR(num_user_sgprs) |
623 S_00B32C_OC_LDS_EN(oc_lds_en) |
624 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
625
626 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
627 si_set_tesseval_regs(sscreen, shader->selector, pm4);
628
629 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
630 }
631
632 static unsigned si_conv_prim_to_gs_out(unsigned mode)
633 {
634 static const int prim_conv[] = {
635 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
636 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
637 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
638 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
639 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
640 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
641 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
642 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
643 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
644 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
645 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
646 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
647 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
648 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
649 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
650 };
651 assert(mode < ARRAY_SIZE(prim_conv));
652
653 return prim_conv[mode];
654 }
655
656 struct gfx9_gs_info {
657 unsigned es_verts_per_subgroup;
658 unsigned gs_prims_per_subgroup;
659 unsigned gs_inst_prims_in_subgroup;
660 unsigned max_prims_per_subgroup;
661 unsigned lds_size;
662 };
663
664 static void gfx9_get_gs_info(struct si_shader_selector *es,
665 struct si_shader_selector *gs,
666 struct gfx9_gs_info *out)
667 {
668 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
669 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
670 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
671 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
672
673 /* All these are in dwords: */
674 /* We can't allow using the whole LDS, because GS waves compete with
675 * other shader stages for LDS space. */
676 const unsigned max_lds_size = 8 * 1024;
677 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
678 unsigned esgs_lds_size;
679
680 /* All these are per subgroup: */
681 const unsigned max_out_prims = 32 * 1024;
682 const unsigned max_es_verts = 255;
683 const unsigned ideal_gs_prims = 64;
684 unsigned max_gs_prims, gs_prims;
685 unsigned min_es_verts, es_verts, worst_case_es_verts;
686
687 if (uses_adjacency || gs_num_invocations > 1)
688 max_gs_prims = 127 / gs_num_invocations;
689 else
690 max_gs_prims = 255;
691
692 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
693 * Make sure we don't go over the maximum value.
694 */
695 if (gs->gs_max_out_vertices > 0) {
696 max_gs_prims = MIN2(max_gs_prims,
697 max_out_prims /
698 (gs->gs_max_out_vertices * gs_num_invocations));
699 }
700 assert(max_gs_prims > 0);
701
702 /* If the primitive has adjacency, halve the number of vertices
703 * that will be reused in multiple primitives.
704 */
705 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
706
707 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
708 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
709
710 /* Compute ESGS LDS size based on the worst case number of ES vertices
711 * needed to create the target number of GS prims per subgroup.
712 */
713 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
714
715 /* If total LDS usage is too big, refactor partitions based on ratio
716 * of ESGS item sizes.
717 */
718 if (esgs_lds_size > max_lds_size) {
719 /* Our target GS Prims Per Subgroup was too large. Calculate
720 * the maximum number of GS Prims Per Subgroup that will fit
721 * into LDS, capped by the maximum that the hardware can support.
722 */
723 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
724 max_gs_prims);
725 assert(gs_prims > 0);
726 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
727 max_es_verts);
728
729 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
730 assert(esgs_lds_size <= max_lds_size);
731 }
732
733 /* Now calculate remaining ESGS information. */
734 if (esgs_lds_size)
735 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
736 else
737 es_verts = max_es_verts;
738
739 /* Vertices for adjacency primitives are not always reused, so restore
740 * it for ES_VERTS_PER_SUBGRP.
741 */
742 min_es_verts = gs->gs_input_verts_per_prim;
743
744 /* For normal primitives, the VGT only checks if they are past the ES
745 * verts per subgroup after allocating a full GS primitive and if they
746 * are, kick off a new subgroup. But if those additional ES verts are
747 * unique (e.g. not reused) we need to make sure there is enough LDS
748 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
749 */
750 es_verts -= min_es_verts - 1;
751
752 out->es_verts_per_subgroup = es_verts;
753 out->gs_prims_per_subgroup = gs_prims;
754 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
755 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
756 gs->gs_max_out_vertices;
757 out->lds_size = align(esgs_lds_size, 128) / 128;
758
759 assert(out->max_prims_per_subgroup <= max_out_prims);
760 }
761
762 static void si_emit_shader_gs(struct si_context *sctx)
763 {
764 struct si_shader *shader = sctx->queued.named.gs->shader;
765 if (!shader)
766 return;
767
768 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
769 * R_028A68_VGT_GSVS_RING_OFFSET_3, R_028A6C_VGT_GS_OUT_PRIM_TYPE */
770 radeon_opt_set_context_reg4(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
771 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
772 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
773 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
774 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3,
775 shader->ctx_reg.gs.vgt_gs_out_prim_type);
776
777
778 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
779 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
780 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
781 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
782
783 /* R_028B38_VGT_GS_MAX_VERT_OUT */
784 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
785 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
786 shader->ctx_reg.gs.vgt_gs_max_vert_out);
787
788 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
789 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
790 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
791 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
792 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
793 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
794 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
795 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
796
797 /* R_028B90_VGT_GS_INSTANCE_CNT */
798 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
799 SI_TRACKED_VGT_GS_INSTANCE_CNT,
800 shader->ctx_reg.gs.vgt_gs_instance_cnt);
801
802 if (sctx->chip_class >= GFX9) {
803 /* R_028A44_VGT_GS_ONCHIP_CNTL */
804 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
805 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
806 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
807 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
808 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
809 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
810 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
811 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
812 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
813 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
814 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
815
816 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
817 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
818 SI_TRACKED_VGT_TF_PARAM,
819 shader->vgt_tf_param);
820 if (shader->vgt_vertex_reuse_block_cntl)
821 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
822 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
823 shader->vgt_vertex_reuse_block_cntl);
824 }
825 }
826
827 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
828 {
829 struct si_shader_selector *sel = shader->selector;
830 const ubyte *num_components = sel->info.num_stream_output_components;
831 unsigned gs_num_invocations = sel->gs_num_invocations;
832 struct si_pm4_state *pm4;
833 uint64_t va;
834 unsigned max_stream = sel->max_gs_stream;
835 unsigned offset;
836
837 pm4 = si_get_shader_pm4_state(shader);
838 if (!pm4)
839 return;
840
841 pm4->atom.emit = si_emit_shader_gs;
842
843 offset = num_components[0] * sel->gs_max_out_vertices;
844 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
845
846 if (max_stream >= 1)
847 offset += num_components[1] * sel->gs_max_out_vertices;
848 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
849
850 if (max_stream >= 2)
851 offset += num_components[2] * sel->gs_max_out_vertices;
852 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
853
854 shader->ctx_reg.gs.vgt_gs_out_prim_type =
855 si_conv_prim_to_gs_out(sel->gs_output_prim);
856
857 if (max_stream >= 3)
858 offset += num_components[3] * sel->gs_max_out_vertices;
859 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
860
861 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
862 assert(offset < (1 << 15));
863
864 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
865
866 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
867 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
868 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
869 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
870
871 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
872 S_028B90_ENABLE(gs_num_invocations > 0);
873
874 va = shader->bo->gpu_address;
875 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
876
877 if (sscreen->info.chip_class >= GFX9) {
878 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
879 unsigned es_type = shader->key.part.gs.es->type;
880 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
881 struct gfx9_gs_info gs_info;
882
883 if (es_type == PIPE_SHADER_VERTEX)
884 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
885 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
886 else if (es_type == PIPE_SHADER_TESS_EVAL)
887 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
888 else
889 unreachable("invalid shader selector type");
890
891 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
892 * VGPR[0:4] are always loaded.
893 */
894 if (sel->info.uses_invocationid)
895 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
896 else if (sel->info.uses_primid)
897 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
898 else if (input_prim >= PIPE_PRIM_TRIANGLES)
899 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
900 else
901 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
902
903 unsigned num_user_sgprs;
904 if (es_type == PIPE_SHADER_VERTEX)
905 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
906 else
907 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
908
909 gfx9_get_gs_info(shader->key.part.gs.es, sel, &gs_info);
910
911 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
912 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
913
914 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
915 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
916 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
917 S_00B228_DX10_CLAMP(1) |
918 S_00B228_FLOAT_MODE(shader->config.float_mode) |
919 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
920 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
921 S_00B22C_USER_SGPR(num_user_sgprs) |
922 S_00B22C_USER_SGPR_MSB(num_user_sgprs >> 5) |
923 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
924 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
925 S_00B22C_LDS_SIZE(gs_info.lds_size) |
926 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
927
928 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
929 S_028A44_ES_VERTS_PER_SUBGRP(gs_info.es_verts_per_subgroup) |
930 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info.gs_prims_per_subgroup) |
931 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info.gs_inst_prims_in_subgroup);
932 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
933 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info.max_prims_per_subgroup);
934 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
935 shader->key.part.gs.es->esgs_itemsize / 4;
936
937 if (es_type == PIPE_SHADER_TESS_EVAL)
938 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
939
940 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
941 NULL, pm4);
942 } else {
943 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
944 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
945
946 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
947 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
948 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
949 S_00B228_DX10_CLAMP(1) |
950 S_00B228_FLOAT_MODE(shader->config.float_mode));
951 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
952 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
953 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
954 }
955 }
956
957 static void si_emit_shader_vs(struct si_context *sctx)
958 {
959 struct si_shader *shader = sctx->queued.named.vs->shader;
960 if (!shader)
961 return;
962
963 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
964 SI_TRACKED_VGT_GS_MODE,
965 shader->ctx_reg.vs.vgt_gs_mode);
966 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
967 SI_TRACKED_VGT_PRIMITIVEID_EN,
968 shader->ctx_reg.vs.vgt_primitiveid_en);
969
970 if (sctx->chip_class <= VI) {
971 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
972 SI_TRACKED_VGT_REUSE_OFF,
973 shader->ctx_reg.vs.vgt_reuse_off);
974 }
975
976 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
977 SI_TRACKED_SPI_VS_OUT_CONFIG,
978 shader->ctx_reg.vs.spi_vs_out_config);
979
980 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
981 SI_TRACKED_SPI_SHADER_POS_FORMAT,
982 shader->ctx_reg.vs.spi_shader_pos_format);
983
984 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
985 SI_TRACKED_PA_CL_VTE_CNTL,
986 shader->ctx_reg.vs.pa_cl_vte_cntl);
987
988 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
989 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
990 SI_TRACKED_VGT_TF_PARAM,
991 shader->vgt_tf_param);
992
993 if (shader->vgt_vertex_reuse_block_cntl)
994 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
995 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
996 shader->vgt_vertex_reuse_block_cntl);
997 }
998
999 /**
1000 * Compute the state for \p shader, which will run as a vertex shader on the
1001 * hardware.
1002 *
1003 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1004 * is the copy shader.
1005 */
1006 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1007 struct si_shader_selector *gs)
1008 {
1009 const struct tgsi_shader_info *info = &shader->selector->info;
1010 struct si_pm4_state *pm4;
1011 unsigned num_user_sgprs, vgpr_comp_cnt;
1012 uint64_t va;
1013 unsigned nparams, oc_lds_en;
1014 unsigned window_space =
1015 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1016 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1017
1018 pm4 = si_get_shader_pm4_state(shader);
1019 if (!pm4)
1020 return;
1021
1022 pm4->atom.emit = si_emit_shader_vs;
1023
1024 /* We always write VGT_GS_MODE in the VS state, because every switch
1025 * between different shader pipelines involving a different GS or no
1026 * GS at all involves a switch of the VS (different GS use different
1027 * copy shaders). On the other hand, when the API switches from a GS to
1028 * no GS and then back to the same GS used originally, the GS state is
1029 * not sent again.
1030 */
1031 if (!gs) {
1032 unsigned mode = V_028A40_GS_OFF;
1033
1034 /* PrimID needs GS scenario A. */
1035 if (enable_prim_id)
1036 mode = V_028A40_GS_SCENARIO_A;
1037
1038 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1039 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1040 } else {
1041 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1042 sscreen->info.chip_class);
1043 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1044 }
1045
1046 if (sscreen->info.chip_class <= VI) {
1047 /* Reuse needs to be set off if we write oViewport. */
1048 shader->ctx_reg.vs.vgt_reuse_off =
1049 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1050 }
1051
1052 va = shader->bo->gpu_address;
1053 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1054
1055 if (gs) {
1056 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1057 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1058 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1059 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1060 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1061 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1062 */
1063 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
1064
1065 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1066 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1067 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1068 } else {
1069 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1070 }
1071 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1072 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1073 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1074 } else
1075 unreachable("invalid shader selector type");
1076
1077 /* VS is required to export at least one param. */
1078 nparams = MAX2(shader->info.nr_param_exports, 1);
1079 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1080
1081 shader->ctx_reg.vs.spi_shader_pos_format =
1082 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1083 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1084 V_02870C_SPI_SHADER_4COMP :
1085 V_02870C_SPI_SHADER_NONE) |
1086 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1087 V_02870C_SPI_SHADER_4COMP :
1088 V_02870C_SPI_SHADER_NONE) |
1089 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1090 V_02870C_SPI_SHADER_4COMP :
1091 V_02870C_SPI_SHADER_NONE);
1092
1093 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1094
1095 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1096 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1097 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
1098 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
1099 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
1100 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1101 S_00B128_DX10_CLAMP(1) |
1102 S_00B128_FLOAT_MODE(shader->config.float_mode));
1103 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
1104 S_00B12C_USER_SGPR(num_user_sgprs) |
1105 S_00B12C_OC_LDS_EN(oc_lds_en) |
1106 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1107 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1108 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1109 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1110 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
1111 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1112
1113 if (window_space)
1114 shader->ctx_reg.vs.pa_cl_vte_cntl =
1115 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1116 else
1117 shader->ctx_reg.vs.pa_cl_vte_cntl =
1118 S_028818_VTX_W0_FMT(1) |
1119 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1120 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1121 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1122
1123 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1124 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1125
1126 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1127 }
1128
1129 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1130 {
1131 struct tgsi_shader_info *info = &ps->selector->info;
1132 unsigned num_colors = !!(info->colors_read & 0x0f) +
1133 !!(info->colors_read & 0xf0);
1134 unsigned num_interp = ps->selector->info.num_inputs +
1135 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1136
1137 assert(num_interp <= 32);
1138 return MIN2(num_interp, 32);
1139 }
1140
1141 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1142 {
1143 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1144 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1145
1146 /* If the i-th target format is set, all previous target formats must
1147 * be non-zero to avoid hangs.
1148 */
1149 for (i = 0; i < num_targets; i++)
1150 if (!(value & (0xf << (i * 4))))
1151 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1152
1153 return value;
1154 }
1155
1156 static void si_emit_shader_ps(struct si_context *sctx)
1157 {
1158 struct si_shader *shader = sctx->queued.named.ps->shader;
1159 if (!shader)
1160 return;
1161
1162 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1163 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1164 SI_TRACKED_SPI_PS_INPUT_ENA,
1165 shader->ctx_reg.ps.spi_ps_input_ena,
1166 shader->ctx_reg.ps.spi_ps_input_addr);
1167
1168 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1169 SI_TRACKED_SPI_BARYC_CNTL,
1170 shader->ctx_reg.ps.spi_baryc_cntl);
1171 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1172 SI_TRACKED_SPI_PS_IN_CONTROL,
1173 shader->ctx_reg.ps.spi_ps_in_control);
1174
1175 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1176 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1177 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1178 shader->ctx_reg.ps.spi_shader_z_format,
1179 shader->ctx_reg.ps.spi_shader_col_format);
1180
1181 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1182 SI_TRACKED_CB_SHADER_MASK,
1183 shader->ctx_reg.ps.cb_shader_mask);
1184 }
1185
1186 static void si_shader_ps(struct si_shader *shader)
1187 {
1188 struct tgsi_shader_info *info = &shader->selector->info;
1189 struct si_pm4_state *pm4;
1190 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1191 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1192 uint64_t va;
1193 unsigned input_ena = shader->config.spi_ps_input_ena;
1194
1195 /* we need to enable at least one of them, otherwise we hang the GPU */
1196 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1197 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1198 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1199 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1200 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1201 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1202 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1203 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1204 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1205 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1206 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1207 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1208 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1209 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1210
1211 /* Validate interpolation optimization flags (read as implications). */
1212 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1213 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1214 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1215 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1216 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1217 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1218 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1219 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1220 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1221 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1222 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1223 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1224 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1225 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1226 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1227 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1228 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1229 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1230
1231 /* Validate cases when the optimizations are off (read as implications). */
1232 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1233 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1234 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1235 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1236 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1237 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1238
1239 pm4 = si_get_shader_pm4_state(shader);
1240 if (!pm4)
1241 return;
1242
1243 pm4->atom.emit = si_emit_shader_ps;
1244
1245 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1246 * Possible vaules:
1247 * 0 -> Position = pixel center
1248 * 1 -> Position = pixel centroid
1249 * 2 -> Position = at sample position
1250 *
1251 * From GLSL 4.5 specification, section 7.1:
1252 * "The variable gl_FragCoord is available as an input variable from
1253 * within fragment shaders and it holds the window relative coordinates
1254 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1255 * value can be for any location within the pixel, or one of the
1256 * fragment samples. The use of centroid does not further restrict
1257 * this value to be inside the current primitive."
1258 *
1259 * Meaning that centroid has no effect and we can return anything within
1260 * the pixel. Thus, return the value at sample position, because that's
1261 * the most accurate one shaders can get.
1262 */
1263 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1264
1265 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1266 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1267 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1268
1269 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1270 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1271
1272 /* Ensure that some export memory is always allocated, for two reasons:
1273 *
1274 * 1) Correctness: The hardware ignores the EXEC mask if no export
1275 * memory is allocated, so KILL and alpha test do not work correctly
1276 * without this.
1277 * 2) Performance: Every shader needs at least a NULL export, even when
1278 * it writes no color/depth output. The NULL export instruction
1279 * stalls without this setting.
1280 *
1281 * Don't add this to CB_SHADER_MASK.
1282 */
1283 if (!spi_shader_col_format &&
1284 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1285 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1286
1287 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1288 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1289
1290 /* Set interpolation controls. */
1291 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1292
1293 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1294 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1295 shader->ctx_reg.ps.spi_shader_z_format =
1296 ac_get_spi_shader_z_format(info->writes_z,
1297 info->writes_stencil,
1298 info->writes_samplemask);
1299 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1300 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1301
1302 va = shader->bo->gpu_address;
1303 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1304 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1305 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1306
1307 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
1308 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1309 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
1310 S_00B028_DX10_CLAMP(1) |
1311 S_00B028_FLOAT_MODE(shader->config.float_mode));
1312 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1313 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1314 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1315 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1316 }
1317
1318 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1319 struct si_shader *shader)
1320 {
1321 switch (shader->selector->type) {
1322 case PIPE_SHADER_VERTEX:
1323 if (shader->key.as_ls)
1324 si_shader_ls(sscreen, shader);
1325 else if (shader->key.as_es)
1326 si_shader_es(sscreen, shader);
1327 else
1328 si_shader_vs(sscreen, shader, NULL);
1329 break;
1330 case PIPE_SHADER_TESS_CTRL:
1331 si_shader_hs(sscreen, shader);
1332 break;
1333 case PIPE_SHADER_TESS_EVAL:
1334 if (shader->key.as_es)
1335 si_shader_es(sscreen, shader);
1336 else
1337 si_shader_vs(sscreen, shader, NULL);
1338 break;
1339 case PIPE_SHADER_GEOMETRY:
1340 si_shader_gs(sscreen, shader);
1341 break;
1342 case PIPE_SHADER_FRAGMENT:
1343 si_shader_ps(shader);
1344 break;
1345 default:
1346 assert(0);
1347 }
1348 }
1349
1350 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1351 {
1352 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1353 if (sctx->queued.named.dsa)
1354 return sctx->queued.named.dsa->alpha_func;
1355
1356 return PIPE_FUNC_ALWAYS;
1357 }
1358
1359 static void si_shader_selector_key_vs(struct si_context *sctx,
1360 struct si_shader_selector *vs,
1361 struct si_shader_key *key,
1362 struct si_vs_prolog_bits *prolog_key)
1363 {
1364 if (!sctx->vertex_elements ||
1365 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS])
1366 return;
1367
1368 prolog_key->instance_divisor_is_one =
1369 sctx->vertex_elements->instance_divisor_is_one;
1370 prolog_key->instance_divisor_is_fetched =
1371 sctx->vertex_elements->instance_divisor_is_fetched;
1372
1373 /* Prefer a monolithic shader to allow scheduling divisions around
1374 * VBO loads. */
1375 if (prolog_key->instance_divisor_is_fetched)
1376 key->opt.prefer_mono = 1;
1377
1378 unsigned count = MIN2(vs->info.num_inputs,
1379 sctx->vertex_elements->count);
1380 memcpy(key->mono.vs_fix_fetch, sctx->vertex_elements->fix_fetch, count);
1381 }
1382
1383 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1384 struct si_shader_selector *vs,
1385 struct si_shader_key *key)
1386 {
1387 struct si_shader_selector *ps = sctx->ps_shader.cso;
1388
1389 key->opt.clip_disable =
1390 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1391 (vs->info.clipdist_writemask ||
1392 vs->info.writes_clipvertex) &&
1393 !vs->info.culldist_writemask;
1394
1395 /* Find out if PS is disabled. */
1396 bool ps_disabled = true;
1397 if (ps) {
1398 const struct si_state_blend *blend = sctx->queued.named.blend;
1399 bool alpha_to_coverage = blend && blend->alpha_to_coverage;
1400 bool ps_modifies_zs = ps->info.uses_kill ||
1401 ps->info.writes_z ||
1402 ps->info.writes_stencil ||
1403 ps->info.writes_samplemask ||
1404 alpha_to_coverage ||
1405 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1406 unsigned ps_colormask = si_get_total_colormask(sctx);
1407
1408 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1409 (!ps_colormask &&
1410 !ps_modifies_zs &&
1411 !ps->info.writes_memory);
1412 }
1413
1414 /* Find out which VS outputs aren't used by the PS. */
1415 uint64_t outputs_written = vs->outputs_written_before_ps;
1416 uint64_t inputs_read = 0;
1417
1418 /* Ignore outputs that are not passed from VS to PS. */
1419 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1420 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1421 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1422
1423 if (!ps_disabled) {
1424 inputs_read = ps->inputs_read;
1425 }
1426
1427 uint64_t linked = outputs_written & inputs_read;
1428
1429 key->opt.kill_outputs = ~linked & outputs_written;
1430 }
1431
1432 /* Compute the key for the hw shader variant */
1433 static inline void si_shader_selector_key(struct pipe_context *ctx,
1434 struct si_shader_selector *sel,
1435 struct si_shader_key *key)
1436 {
1437 struct si_context *sctx = (struct si_context *)ctx;
1438
1439 memset(key, 0, sizeof(*key));
1440
1441 switch (sel->type) {
1442 case PIPE_SHADER_VERTEX:
1443 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1444
1445 if (sctx->tes_shader.cso)
1446 key->as_ls = 1;
1447 else if (sctx->gs_shader.cso)
1448 key->as_es = 1;
1449 else {
1450 si_shader_selector_key_hw_vs(sctx, sel, key);
1451
1452 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1453 key->mono.u.vs_export_prim_id = 1;
1454 }
1455 break;
1456 case PIPE_SHADER_TESS_CTRL:
1457 if (sctx->chip_class >= GFX9) {
1458 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1459 key, &key->part.tcs.ls_prolog);
1460 key->part.tcs.ls = sctx->vs_shader.cso;
1461
1462 /* When the LS VGPR fix is needed, monolithic shaders
1463 * can:
1464 * - avoid initializing EXEC in both the LS prolog
1465 * and the LS main part when !vs_needs_prolog
1466 * - remove the fixup for unused input VGPRs
1467 */
1468 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1469
1470 /* The LS output / HS input layout can be communicated
1471 * directly instead of via user SGPRs for merged LS-HS.
1472 * The LS VGPR fix prefers this too.
1473 */
1474 key->opt.prefer_mono = 1;
1475 }
1476
1477 key->part.tcs.epilog.prim_mode =
1478 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1479 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1480 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1481 key->part.tcs.epilog.tes_reads_tess_factors =
1482 sctx->tes_shader.cso->info.reads_tess_factors;
1483
1484 if (sel == sctx->fixed_func_tcs_shader.cso)
1485 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1486 break;
1487 case PIPE_SHADER_TESS_EVAL:
1488 if (sctx->gs_shader.cso)
1489 key->as_es = 1;
1490 else {
1491 si_shader_selector_key_hw_vs(sctx, sel, key);
1492
1493 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1494 key->mono.u.vs_export_prim_id = 1;
1495 }
1496 break;
1497 case PIPE_SHADER_GEOMETRY:
1498 if (sctx->chip_class >= GFX9) {
1499 if (sctx->tes_shader.cso) {
1500 key->part.gs.es = sctx->tes_shader.cso;
1501 } else {
1502 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1503 key, &key->part.gs.vs_prolog);
1504 key->part.gs.es = sctx->vs_shader.cso;
1505 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1506 }
1507
1508 /* Merged ES-GS can have unbalanced wave usage.
1509 *
1510 * ES threads are per-vertex, while GS threads are
1511 * per-primitive. So without any amplification, there
1512 * are fewer GS threads than ES threads, which can result
1513 * in empty (no-op) GS waves. With too much amplification,
1514 * there are more GS threads than ES threads, which
1515 * can result in empty (no-op) ES waves.
1516 *
1517 * Non-monolithic shaders are implemented by setting EXEC
1518 * at the beginning of shader parts, and don't jump to
1519 * the end if EXEC is 0.
1520 *
1521 * Monolithic shaders use conditional blocks, so they can
1522 * jump and skip empty waves of ES or GS. So set this to
1523 * always use optimized variants, which are monolithic.
1524 */
1525 key->opt.prefer_mono = 1;
1526 }
1527 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1528 break;
1529 case PIPE_SHADER_FRAGMENT: {
1530 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1531 struct si_state_blend *blend = sctx->queued.named.blend;
1532
1533 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1534 sel->info.colors_written == 0x1)
1535 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1536
1537 if (blend) {
1538 /* Select the shader color format based on whether
1539 * blending or alpha are needed.
1540 */
1541 key->part.ps.epilog.spi_shader_col_format =
1542 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1543 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1544 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1545 sctx->framebuffer.spi_shader_col_format_blend) |
1546 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1547 sctx->framebuffer.spi_shader_col_format_alpha) |
1548 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1549 sctx->framebuffer.spi_shader_col_format);
1550 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1551
1552 /* The output for dual source blending should have
1553 * the same format as the first output.
1554 */
1555 if (blend->dual_src_blend)
1556 key->part.ps.epilog.spi_shader_col_format |=
1557 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1558 } else
1559 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1560
1561 /* If alpha-to-coverage is enabled, we have to export alpha
1562 * even if there is no color buffer.
1563 */
1564 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1565 blend && blend->alpha_to_coverage)
1566 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1567
1568 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1569 * to the range supported by the type if a channel has less
1570 * than 16 bits and the export format is 16_ABGR.
1571 */
1572 if (sctx->chip_class <= CIK && sctx->family != CHIP_HAWAII) {
1573 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1574 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1575 }
1576
1577 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1578 if (!key->part.ps.epilog.last_cbuf) {
1579 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1580 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1581 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1582 }
1583
1584 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1585 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1586
1587 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1588 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1589
1590 if (sctx->queued.named.blend) {
1591 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1592 rs->multisample_enable;
1593 }
1594
1595 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1596 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1597 (is_line && rs->line_smooth)) &&
1598 sctx->framebuffer.nr_samples <= 1;
1599 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1600
1601 if (sctx->ps_iter_samples > 1 &&
1602 sel->info.reads_samplemask) {
1603 key->part.ps.prolog.samplemask_log_ps_iter =
1604 util_logbase2(sctx->ps_iter_samples);
1605 }
1606
1607 if (rs->force_persample_interp &&
1608 rs->multisample_enable &&
1609 sctx->framebuffer.nr_samples > 1 &&
1610 sctx->ps_iter_samples > 1) {
1611 key->part.ps.prolog.force_persp_sample_interp =
1612 sel->info.uses_persp_center ||
1613 sel->info.uses_persp_centroid;
1614
1615 key->part.ps.prolog.force_linear_sample_interp =
1616 sel->info.uses_linear_center ||
1617 sel->info.uses_linear_centroid;
1618 } else if (rs->multisample_enable &&
1619 sctx->framebuffer.nr_samples > 1) {
1620 key->part.ps.prolog.bc_optimize_for_persp =
1621 sel->info.uses_persp_center &&
1622 sel->info.uses_persp_centroid;
1623 key->part.ps.prolog.bc_optimize_for_linear =
1624 sel->info.uses_linear_center &&
1625 sel->info.uses_linear_centroid;
1626 } else {
1627 /* Make sure SPI doesn't compute more than 1 pair
1628 * of (i,j), which is the optimization here. */
1629 key->part.ps.prolog.force_persp_center_interp =
1630 sel->info.uses_persp_center +
1631 sel->info.uses_persp_centroid +
1632 sel->info.uses_persp_sample > 1;
1633
1634 key->part.ps.prolog.force_linear_center_interp =
1635 sel->info.uses_linear_center +
1636 sel->info.uses_linear_centroid +
1637 sel->info.uses_linear_sample > 1;
1638
1639 if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
1640 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1641 }
1642
1643 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1644
1645 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1646 if (sctx->ps_uses_fbfetch) {
1647 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
1648 struct pipe_resource *tex = cb0->texture;
1649
1650 /* 1D textures are allocated and used as 2D on GFX9. */
1651 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
1652 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
1653 (tex->target == PIPE_TEXTURE_1D ||
1654 tex->target == PIPE_TEXTURE_1D_ARRAY);
1655 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
1656 tex->target == PIPE_TEXTURE_2D_ARRAY ||
1657 tex->target == PIPE_TEXTURE_CUBE ||
1658 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
1659 tex->target == PIPE_TEXTURE_3D;
1660 }
1661 break;
1662 }
1663 default:
1664 assert(0);
1665 }
1666
1667 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
1668 memset(&key->opt, 0, sizeof(key->opt));
1669 }
1670
1671 static void si_build_shader_variant(struct si_shader *shader,
1672 int thread_index,
1673 bool low_priority)
1674 {
1675 struct si_shader_selector *sel = shader->selector;
1676 struct si_screen *sscreen = sel->screen;
1677 struct ac_llvm_compiler *compiler;
1678 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1679 int r;
1680
1681 if (thread_index >= 0) {
1682 if (low_priority) {
1683 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
1684 compiler = &sscreen->compiler_lowp[thread_index];
1685 } else {
1686 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
1687 compiler = &sscreen->compiler[thread_index];
1688 }
1689 if (!debug->async)
1690 debug = NULL;
1691 } else {
1692 assert(!low_priority);
1693 compiler = shader->compiler_ctx_state.compiler;
1694 }
1695
1696 r = si_shader_create(sscreen, compiler, shader, debug);
1697 if (unlikely(r)) {
1698 PRINT_ERR("Failed to build shader variant (type=%u) %d\n",
1699 sel->type, r);
1700 shader->compilation_failed = true;
1701 return;
1702 }
1703
1704 if (shader->compiler_ctx_state.is_debug_context) {
1705 FILE *f = open_memstream(&shader->shader_log,
1706 &shader->shader_log_size);
1707 if (f) {
1708 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1709 fclose(f);
1710 }
1711 }
1712
1713 si_shader_init_pm4_state(sscreen, shader);
1714 }
1715
1716 static void si_build_shader_variant_low_priority(void *job, int thread_index)
1717 {
1718 struct si_shader *shader = (struct si_shader *)job;
1719
1720 assert(thread_index >= 0);
1721
1722 si_build_shader_variant(shader, thread_index, true);
1723 }
1724
1725 static const struct si_shader_key zeroed;
1726
1727 static bool si_check_missing_main_part(struct si_screen *sscreen,
1728 struct si_shader_selector *sel,
1729 struct si_compiler_ctx_state *compiler_state,
1730 struct si_shader_key *key)
1731 {
1732 struct si_shader **mainp = si_get_main_shader_part(sel, key);
1733
1734 if (!*mainp) {
1735 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1736
1737 if (!main_part)
1738 return false;
1739
1740 /* We can leave the fence as permanently signaled because the
1741 * main part becomes visible globally only after it has been
1742 * compiled. */
1743 util_queue_fence_init(&main_part->ready);
1744
1745 main_part->selector = sel;
1746 main_part->key.as_es = key->as_es;
1747 main_part->key.as_ls = key->as_ls;
1748 main_part->is_monolithic = false;
1749
1750 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
1751 main_part, &compiler_state->debug) != 0) {
1752 FREE(main_part);
1753 return false;
1754 }
1755 *mainp = main_part;
1756 }
1757 return true;
1758 }
1759
1760 /* Select the hw shader variant depending on the current state. */
1761 static int si_shader_select_with_key(struct si_screen *sscreen,
1762 struct si_shader_ctx_state *state,
1763 struct si_compiler_ctx_state *compiler_state,
1764 struct si_shader_key *key,
1765 int thread_index)
1766 {
1767 struct si_shader_selector *sel = state->cso;
1768 struct si_shader_selector *previous_stage_sel = NULL;
1769 struct si_shader *current = state->current;
1770 struct si_shader *iter, *shader = NULL;
1771
1772 again:
1773 /* Check if we don't need to change anything.
1774 * This path is also used for most shaders that don't need multiple
1775 * variants, it will cost just a computation of the key and this
1776 * test. */
1777 if (likely(current &&
1778 memcmp(&current->key, key, sizeof(*key)) == 0)) {
1779 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
1780 if (current->is_optimized) {
1781 memset(&key->opt, 0, sizeof(key->opt));
1782 goto current_not_ready;
1783 }
1784
1785 util_queue_fence_wait(&current->ready);
1786 }
1787
1788 return current->compilation_failed ? -1 : 0;
1789 }
1790 current_not_ready:
1791
1792 /* This must be done before the mutex is locked, because async GS
1793 * compilation calls this function too, and therefore must enter
1794 * the mutex first.
1795 *
1796 * Only wait if we are in a draw call. Don't wait if we are
1797 * in a compiler thread.
1798 */
1799 if (thread_index < 0)
1800 util_queue_fence_wait(&sel->ready);
1801
1802 mtx_lock(&sel->mutex);
1803
1804 /* Find the shader variant. */
1805 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1806 /* Don't check the "current" shader. We checked it above. */
1807 if (current != iter &&
1808 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1809 mtx_unlock(&sel->mutex);
1810
1811 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
1812 /* If it's an optimized shader and its compilation has
1813 * been started but isn't done, use the unoptimized
1814 * shader so as not to cause a stall due to compilation.
1815 */
1816 if (iter->is_optimized) {
1817 memset(&key->opt, 0, sizeof(key->opt));
1818 goto again;
1819 }
1820
1821 util_queue_fence_wait(&iter->ready);
1822 }
1823
1824 if (iter->compilation_failed) {
1825 return -1; /* skip the draw call */
1826 }
1827
1828 state->current = iter;
1829 return 0;
1830 }
1831 }
1832
1833 /* Build a new shader. */
1834 shader = CALLOC_STRUCT(si_shader);
1835 if (!shader) {
1836 mtx_unlock(&sel->mutex);
1837 return -ENOMEM;
1838 }
1839
1840 util_queue_fence_init(&shader->ready);
1841
1842 shader->selector = sel;
1843 shader->key = *key;
1844 shader->compiler_ctx_state = *compiler_state;
1845
1846 /* If this is a merged shader, get the first shader's selector. */
1847 if (sscreen->info.chip_class >= GFX9) {
1848 if (sel->type == PIPE_SHADER_TESS_CTRL)
1849 previous_stage_sel = key->part.tcs.ls;
1850 else if (sel->type == PIPE_SHADER_GEOMETRY)
1851 previous_stage_sel = key->part.gs.es;
1852
1853 /* We need to wait for the previous shader. */
1854 if (previous_stage_sel && thread_index < 0)
1855 util_queue_fence_wait(&previous_stage_sel->ready);
1856 }
1857
1858 /* Compile the main shader part if it doesn't exist. This can happen
1859 * if the initial guess was wrong. */
1860 bool is_pure_monolithic =
1861 sscreen->use_monolithic_shaders ||
1862 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1863
1864 if (!is_pure_monolithic) {
1865 bool ok;
1866
1867 /* Make sure the main shader part is present. This is needed
1868 * for shaders that can be compiled as VS, LS, or ES, and only
1869 * one of them is compiled at creation.
1870 *
1871 * For merged shaders, check that the starting shader's main
1872 * part is present.
1873 */
1874 if (previous_stage_sel) {
1875 struct si_shader_key shader1_key = zeroed;
1876
1877 if (sel->type == PIPE_SHADER_TESS_CTRL)
1878 shader1_key.as_ls = 1;
1879 else if (sel->type == PIPE_SHADER_GEOMETRY)
1880 shader1_key.as_es = 1;
1881 else
1882 assert(0);
1883
1884 mtx_lock(&previous_stage_sel->mutex);
1885 ok = si_check_missing_main_part(sscreen,
1886 previous_stage_sel,
1887 compiler_state, &shader1_key);
1888 mtx_unlock(&previous_stage_sel->mutex);
1889 } else {
1890 ok = si_check_missing_main_part(sscreen, sel,
1891 compiler_state, key);
1892 }
1893 if (!ok) {
1894 FREE(shader);
1895 mtx_unlock(&sel->mutex);
1896 return -ENOMEM; /* skip the draw call */
1897 }
1898 }
1899
1900 /* Keep the reference to the 1st shader of merged shaders, so that
1901 * Gallium can't destroy it before we destroy the 2nd shader.
1902 *
1903 * Set sctx = NULL, because it's unused if we're not releasing
1904 * the shader, and we don't have any sctx here.
1905 */
1906 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
1907 previous_stage_sel);
1908
1909 /* Monolithic-only shaders don't make a distinction between optimized
1910 * and unoptimized. */
1911 shader->is_monolithic =
1912 is_pure_monolithic ||
1913 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1914
1915 shader->is_optimized =
1916 !is_pure_monolithic &&
1917 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1918
1919 /* If it's an optimized shader, compile it asynchronously. */
1920 if (shader->is_optimized &&
1921 !is_pure_monolithic &&
1922 thread_index < 0) {
1923 /* Compile it asynchronously. */
1924 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
1925 shader, &shader->ready,
1926 si_build_shader_variant_low_priority, NULL);
1927
1928 /* Add only after the ready fence was reset, to guard against a
1929 * race with si_bind_XX_shader. */
1930 if (!sel->last_variant) {
1931 sel->first_variant = shader;
1932 sel->last_variant = shader;
1933 } else {
1934 sel->last_variant->next_variant = shader;
1935 sel->last_variant = shader;
1936 }
1937
1938 /* Use the default (unoptimized) shader for now. */
1939 memset(&key->opt, 0, sizeof(key->opt));
1940 mtx_unlock(&sel->mutex);
1941 goto again;
1942 }
1943
1944 /* Reset the fence before adding to the variant list. */
1945 util_queue_fence_reset(&shader->ready);
1946
1947 if (!sel->last_variant) {
1948 sel->first_variant = shader;
1949 sel->last_variant = shader;
1950 } else {
1951 sel->last_variant->next_variant = shader;
1952 sel->last_variant = shader;
1953 }
1954
1955 mtx_unlock(&sel->mutex);
1956
1957 assert(!shader->is_optimized);
1958 si_build_shader_variant(shader, thread_index, false);
1959
1960 util_queue_fence_signal(&shader->ready);
1961
1962 if (!shader->compilation_failed)
1963 state->current = shader;
1964
1965 return shader->compilation_failed ? -1 : 0;
1966 }
1967
1968 static int si_shader_select(struct pipe_context *ctx,
1969 struct si_shader_ctx_state *state,
1970 struct si_compiler_ctx_state *compiler_state)
1971 {
1972 struct si_context *sctx = (struct si_context *)ctx;
1973 struct si_shader_key key;
1974
1975 si_shader_selector_key(ctx, state->cso, &key);
1976 return si_shader_select_with_key(sctx->screen, state, compiler_state,
1977 &key, -1);
1978 }
1979
1980 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1981 bool streamout,
1982 struct si_shader_key *key)
1983 {
1984 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1985
1986 switch (info->processor) {
1987 case PIPE_SHADER_VERTEX:
1988 switch (next_shader) {
1989 case PIPE_SHADER_GEOMETRY:
1990 key->as_es = 1;
1991 break;
1992 case PIPE_SHADER_TESS_CTRL:
1993 case PIPE_SHADER_TESS_EVAL:
1994 key->as_ls = 1;
1995 break;
1996 default:
1997 /* If POSITION isn't written, it can only be a HW VS
1998 * if streamout is used. If streamout isn't used,
1999 * assume that it's a HW LS. (the next shader is TCS)
2000 * This heuristic is needed for separate shader objects.
2001 */
2002 if (!info->writes_position && !streamout)
2003 key->as_ls = 1;
2004 }
2005 break;
2006
2007 case PIPE_SHADER_TESS_EVAL:
2008 if (next_shader == PIPE_SHADER_GEOMETRY ||
2009 !info->writes_position)
2010 key->as_es = 1;
2011 break;
2012 }
2013 }
2014
2015 /**
2016 * Compile the main shader part or the monolithic shader as part of
2017 * si_shader_selector initialization. Since it can be done asynchronously,
2018 * there is no way to report compile failures to applications.
2019 */
2020 static void si_init_shader_selector_async(void *job, int thread_index)
2021 {
2022 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2023 struct si_screen *sscreen = sel->screen;
2024 struct ac_llvm_compiler *compiler;
2025 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2026
2027 assert(!debug->debug_message || debug->async);
2028 assert(thread_index >= 0);
2029 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2030 compiler = &sscreen->compiler[thread_index];
2031
2032 /* Compile the main shader part for use with a prolog and/or epilog.
2033 * If this fails, the driver will try to compile a monolithic shader
2034 * on demand.
2035 */
2036 if (!sscreen->use_monolithic_shaders) {
2037 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2038 void *ir_binary = NULL;
2039
2040 if (!shader) {
2041 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2042 return;
2043 }
2044
2045 /* We can leave the fence signaled because use of the default
2046 * main part is guarded by the selector's ready fence. */
2047 util_queue_fence_init(&shader->ready);
2048
2049 shader->selector = sel;
2050 shader->is_monolithic = false;
2051 si_parse_next_shader_property(&sel->info,
2052 sel->so.num_outputs != 0,
2053 &shader->key);
2054
2055 if (sel->tokens || sel->nir)
2056 ir_binary = si_get_ir_binary(sel);
2057
2058 /* Try to load the shader from the shader cache. */
2059 mtx_lock(&sscreen->shader_cache_mutex);
2060
2061 if (ir_binary &&
2062 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
2063 mtx_unlock(&sscreen->shader_cache_mutex);
2064 si_shader_dump_stats_for_shader_db(shader, debug);
2065 } else {
2066 mtx_unlock(&sscreen->shader_cache_mutex);
2067
2068 /* Compile the shader if it hasn't been loaded from the cache. */
2069 if (si_compile_tgsi_shader(sscreen, compiler, shader,
2070 debug) != 0) {
2071 FREE(shader);
2072 FREE(ir_binary);
2073 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2074 return;
2075 }
2076
2077 if (ir_binary) {
2078 mtx_lock(&sscreen->shader_cache_mutex);
2079 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
2080 FREE(ir_binary);
2081 mtx_unlock(&sscreen->shader_cache_mutex);
2082 }
2083 }
2084
2085 *si_get_main_shader_part(sel, &shader->key) = shader;
2086
2087 /* Unset "outputs_written" flags for outputs converted to
2088 * DEFAULT_VAL, so that later inter-shader optimizations don't
2089 * try to eliminate outputs that don't exist in the final
2090 * shader.
2091 *
2092 * This is only done if non-monolithic shaders are enabled.
2093 */
2094 if ((sel->type == PIPE_SHADER_VERTEX ||
2095 sel->type == PIPE_SHADER_TESS_EVAL) &&
2096 !shader->key.as_ls &&
2097 !shader->key.as_es) {
2098 unsigned i;
2099
2100 for (i = 0; i < sel->info.num_outputs; i++) {
2101 unsigned offset = shader->info.vs_output_param_offset[i];
2102
2103 if (offset <= AC_EXP_PARAM_OFFSET_31)
2104 continue;
2105
2106 unsigned name = sel->info.output_semantic_name[i];
2107 unsigned index = sel->info.output_semantic_index[i];
2108 unsigned id;
2109
2110 switch (name) {
2111 case TGSI_SEMANTIC_GENERIC:
2112 /* don't process indices the function can't handle */
2113 if (index >= SI_MAX_IO_GENERIC)
2114 break;
2115 /* fall through */
2116 default:
2117 id = si_shader_io_get_unique_index(name, index, true);
2118 sel->outputs_written_before_ps &= ~(1ull << id);
2119 break;
2120 case TGSI_SEMANTIC_POSITION: /* ignore these */
2121 case TGSI_SEMANTIC_PSIZE:
2122 case TGSI_SEMANTIC_CLIPVERTEX:
2123 case TGSI_SEMANTIC_EDGEFLAG:
2124 break;
2125 }
2126 }
2127 }
2128 }
2129
2130 /* The GS copy shader is always pre-compiled. */
2131 if (sel->type == PIPE_SHADER_GEOMETRY) {
2132 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2133 if (!sel->gs_copy_shader) {
2134 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2135 return;
2136 }
2137
2138 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2139 }
2140 }
2141
2142 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2143 struct util_queue_fence *ready_fence,
2144 struct si_compiler_ctx_state *compiler_ctx_state,
2145 void *job, util_queue_execute_func execute)
2146 {
2147 util_queue_fence_init(ready_fence);
2148
2149 struct util_async_debug_callback async_debug;
2150 bool wait =
2151 (sctx->debug.debug_message && !sctx->debug.async) ||
2152 sctx->is_debug ||
2153 si_can_dump_shader(sctx->screen, processor);
2154
2155 if (wait) {
2156 u_async_debug_init(&async_debug);
2157 compiler_ctx_state->debug = async_debug.base;
2158 }
2159
2160 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2161 ready_fence, execute, NULL);
2162
2163 if (wait) {
2164 util_queue_fence_wait(ready_fence);
2165 u_async_debug_drain(&async_debug, &sctx->debug);
2166 u_async_debug_cleanup(&async_debug);
2167 }
2168 }
2169
2170 /* Return descriptor slot usage masks from the given shader info. */
2171 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2172 uint32_t *const_and_shader_buffers,
2173 uint64_t *samplers_and_images)
2174 {
2175 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2176
2177 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2178 num_constbufs = util_last_bit(info->const_buffers_declared);
2179 /* two 8-byte images share one 16-byte slot */
2180 num_images = align(util_last_bit(info->images_declared), 2);
2181 num_samplers = util_last_bit(info->samplers_declared);
2182
2183 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2184 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2185 *const_and_shader_buffers =
2186 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2187
2188 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2189 start = si_get_image_slot(num_images - 1) / 2;
2190 *samplers_and_images =
2191 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2192 }
2193
2194 static void *si_create_shader_selector(struct pipe_context *ctx,
2195 const struct pipe_shader_state *state)
2196 {
2197 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2198 struct si_context *sctx = (struct si_context*)ctx;
2199 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2200 int i;
2201
2202 if (!sel)
2203 return NULL;
2204
2205 pipe_reference_init(&sel->reference, 1);
2206 sel->screen = sscreen;
2207 sel->compiler_ctx_state.debug = sctx->debug;
2208 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2209
2210 sel->so = state->stream_output;
2211
2212 if (state->type == PIPE_SHADER_IR_TGSI) {
2213 sel->tokens = tgsi_dup_tokens(state->tokens);
2214 if (!sel->tokens) {
2215 FREE(sel);
2216 return NULL;
2217 }
2218
2219 tgsi_scan_shader(state->tokens, &sel->info);
2220 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2221 } else {
2222 assert(state->type == PIPE_SHADER_IR_NIR);
2223
2224 sel->nir = state->ir.nir;
2225
2226 si_nir_scan_shader(sel->nir, &sel->info);
2227 si_nir_scan_tess_ctrl(sel->nir, &sel->info, &sel->tcs_info);
2228
2229 si_lower_nir(sel);
2230 }
2231
2232 sel->type = sel->info.processor;
2233 p_atomic_inc(&sscreen->num_shaders_created);
2234 si_get_active_slot_masks(&sel->info,
2235 &sel->active_const_and_shader_buffers,
2236 &sel->active_samplers_and_images);
2237
2238 /* Record which streamout buffers are enabled. */
2239 for (i = 0; i < sel->so.num_outputs; i++) {
2240 sel->enabled_streamout_buffer_mask |=
2241 (1 << sel->so.output[i].output_buffer) <<
2242 (sel->so.output[i].stream * 4);
2243 }
2244
2245 /* The prolog is a no-op if there are no inputs. */
2246 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2247 sel->info.num_inputs &&
2248 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2249
2250 sel->force_correct_derivs_after_kill =
2251 sel->type == PIPE_SHADER_FRAGMENT &&
2252 sel->info.uses_derivatives &&
2253 sel->info.uses_kill &&
2254 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2255
2256 /* Set which opcode uses which (i,j) pair. */
2257 if (sel->info.uses_persp_opcode_interp_centroid)
2258 sel->info.uses_persp_centroid = true;
2259
2260 if (sel->info.uses_linear_opcode_interp_centroid)
2261 sel->info.uses_linear_centroid = true;
2262
2263 if (sel->info.uses_persp_opcode_interp_offset ||
2264 sel->info.uses_persp_opcode_interp_sample)
2265 sel->info.uses_persp_center = true;
2266
2267 if (sel->info.uses_linear_opcode_interp_offset ||
2268 sel->info.uses_linear_opcode_interp_sample)
2269 sel->info.uses_linear_center = true;
2270
2271 switch (sel->type) {
2272 case PIPE_SHADER_GEOMETRY:
2273 sel->gs_output_prim =
2274 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2275 sel->gs_max_out_vertices =
2276 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2277 sel->gs_num_invocations =
2278 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2279 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2280 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2281 sel->gs_max_out_vertices;
2282
2283 sel->max_gs_stream = 0;
2284 for (i = 0; i < sel->so.num_outputs; i++)
2285 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2286 sel->so.output[i].stream);
2287
2288 sel->gs_input_verts_per_prim =
2289 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2290 break;
2291
2292 case PIPE_SHADER_TESS_CTRL:
2293 /* Always reserve space for these. */
2294 sel->patch_outputs_written |=
2295 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2296 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2297 /* fall through */
2298 case PIPE_SHADER_VERTEX:
2299 case PIPE_SHADER_TESS_EVAL:
2300 for (i = 0; i < sel->info.num_outputs; i++) {
2301 unsigned name = sel->info.output_semantic_name[i];
2302 unsigned index = sel->info.output_semantic_index[i];
2303
2304 switch (name) {
2305 case TGSI_SEMANTIC_TESSINNER:
2306 case TGSI_SEMANTIC_TESSOUTER:
2307 case TGSI_SEMANTIC_PATCH:
2308 sel->patch_outputs_written |=
2309 1ull << si_shader_io_get_unique_index_patch(name, index);
2310 break;
2311
2312 case TGSI_SEMANTIC_GENERIC:
2313 /* don't process indices the function can't handle */
2314 if (index >= SI_MAX_IO_GENERIC)
2315 break;
2316 /* fall through */
2317 default:
2318 sel->outputs_written |=
2319 1ull << si_shader_io_get_unique_index(name, index, false);
2320 sel->outputs_written_before_ps |=
2321 1ull << si_shader_io_get_unique_index(name, index, true);
2322 break;
2323 case TGSI_SEMANTIC_EDGEFLAG:
2324 break;
2325 }
2326 }
2327 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2328 sel->lshs_vertex_stride = sel->esgs_itemsize;
2329
2330 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2331 * will start on a different bank. (except for the maximum 32*16).
2332 */
2333 if (sel->lshs_vertex_stride < 32*16)
2334 sel->lshs_vertex_stride += 4;
2335
2336 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2337 * conflicts, i.e. each vertex will start at a different bank.
2338 */
2339 if (sctx->chip_class >= GFX9)
2340 sel->esgs_itemsize += 4;
2341
2342 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2343 break;
2344
2345 case PIPE_SHADER_FRAGMENT:
2346 for (i = 0; i < sel->info.num_inputs; i++) {
2347 unsigned name = sel->info.input_semantic_name[i];
2348 unsigned index = sel->info.input_semantic_index[i];
2349
2350 switch (name) {
2351 case TGSI_SEMANTIC_GENERIC:
2352 /* don't process indices the function can't handle */
2353 if (index >= SI_MAX_IO_GENERIC)
2354 break;
2355 /* fall through */
2356 default:
2357 sel->inputs_read |=
2358 1ull << si_shader_io_get_unique_index(name, index, true);
2359 break;
2360 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2361 break;
2362 }
2363 }
2364
2365 for (i = 0; i < 8; i++)
2366 if (sel->info.colors_written & (1 << i))
2367 sel->colors_written_4bit |= 0xf << (4 * i);
2368
2369 for (i = 0; i < sel->info.num_inputs; i++) {
2370 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2371 int index = sel->info.input_semantic_index[i];
2372 sel->color_attr_index[index] = i;
2373 }
2374 }
2375 break;
2376 }
2377
2378 /* PA_CL_VS_OUT_CNTL */
2379 bool misc_vec_ena =
2380 sel->info.writes_psize || sel->info.writes_edgeflag ||
2381 sel->info.writes_layer || sel->info.writes_viewport_index;
2382 sel->pa_cl_vs_out_cntl =
2383 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2384 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2385 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2386 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2387 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2388 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2389 sel->clipdist_mask = sel->info.writes_clipvertex ?
2390 SIX_BITS : sel->info.clipdist_writemask;
2391 sel->culldist_mask = sel->info.culldist_writemask <<
2392 sel->info.num_written_clipdistance;
2393
2394 /* DB_SHADER_CONTROL */
2395 sel->db_shader_control =
2396 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2397 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2398 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2399 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2400
2401 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2402 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2403 sel->db_shader_control |=
2404 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2405 break;
2406 case TGSI_FS_DEPTH_LAYOUT_LESS:
2407 sel->db_shader_control |=
2408 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2409 break;
2410 }
2411
2412 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2413 *
2414 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2415 * --|-----------|------------|------------|--------------------|-------------------|-------------
2416 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2417 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2418 * 2 | false | true | n/a | LateZ | 1 | 0
2419 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2420 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2421 *
2422 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2423 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2424 *
2425 * Don't use ReZ without profiling !!!
2426 *
2427 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2428 * shaders.
2429 */
2430 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2431 /* Cases 3, 4. */
2432 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2433 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2434 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2435 } else if (sel->info.writes_memory) {
2436 /* Case 2. */
2437 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2438 S_02880C_EXEC_ON_HIER_FAIL(1);
2439 } else {
2440 /* Case 1. */
2441 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2442 }
2443
2444 (void) mtx_init(&sel->mutex, mtx_plain);
2445
2446 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2447 &sel->compiler_ctx_state, sel,
2448 si_init_shader_selector_async);
2449 return sel;
2450 }
2451
2452 static void si_update_streamout_state(struct si_context *sctx)
2453 {
2454 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2455
2456 if (!shader_with_so)
2457 return;
2458
2459 sctx->streamout.enabled_stream_buffers_mask =
2460 shader_with_so->enabled_streamout_buffer_mask;
2461 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2462 }
2463
2464 static void si_update_clip_regs(struct si_context *sctx,
2465 struct si_shader_selector *old_hw_vs,
2466 struct si_shader *old_hw_vs_variant,
2467 struct si_shader_selector *next_hw_vs,
2468 struct si_shader *next_hw_vs_variant)
2469 {
2470 if (next_hw_vs &&
2471 (!old_hw_vs ||
2472 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2473 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2474 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2475 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2476 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2477 !old_hw_vs_variant ||
2478 !next_hw_vs_variant ||
2479 old_hw_vs_variant->key.opt.clip_disable !=
2480 next_hw_vs_variant->key.opt.clip_disable))
2481 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2482 }
2483
2484 static void si_update_common_shader_state(struct si_context *sctx)
2485 {
2486 sctx->uses_bindless_samplers =
2487 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2488 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2489 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2490 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2491 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2492 sctx->uses_bindless_images =
2493 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2494 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2495 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2496 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2497 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2498 sctx->do_update_shaders = true;
2499 }
2500
2501 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2502 {
2503 struct si_context *sctx = (struct si_context *)ctx;
2504 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2505 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2506 struct si_shader_selector *sel = state;
2507
2508 if (sctx->vs_shader.cso == sel)
2509 return;
2510
2511 sctx->vs_shader.cso = sel;
2512 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2513 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2514
2515 si_update_common_shader_state(sctx);
2516 si_update_vs_viewport_state(sctx);
2517 si_set_active_descriptors_for_shader(sctx, sel);
2518 si_update_streamout_state(sctx);
2519 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2520 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2521 }
2522
2523 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2524 {
2525 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2526 (sctx->tes_shader.cso &&
2527 sctx->tes_shader.cso->info.uses_primid) ||
2528 (sctx->tcs_shader.cso &&
2529 sctx->tcs_shader.cso->info.uses_primid) ||
2530 (sctx->gs_shader.cso &&
2531 sctx->gs_shader.cso->info.uses_primid) ||
2532 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2533 sctx->ps_shader.cso->info.uses_primid);
2534 }
2535
2536 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2537 {
2538 struct si_context *sctx = (struct si_context *)ctx;
2539 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2540 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2541 struct si_shader_selector *sel = state;
2542 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2543
2544 if (sctx->gs_shader.cso == sel)
2545 return;
2546
2547 sctx->gs_shader.cso = sel;
2548 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2549 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2550
2551 si_update_common_shader_state(sctx);
2552 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2553
2554 if (enable_changed) {
2555 si_shader_change_notify(sctx);
2556 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2557 si_update_tess_uses_prim_id(sctx);
2558 }
2559 si_update_vs_viewport_state(sctx);
2560 si_set_active_descriptors_for_shader(sctx, sel);
2561 si_update_streamout_state(sctx);
2562 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2563 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2564 }
2565
2566 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2567 {
2568 struct si_context *sctx = (struct si_context *)ctx;
2569 struct si_shader_selector *sel = state;
2570 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2571
2572 if (sctx->tcs_shader.cso == sel)
2573 return;
2574
2575 sctx->tcs_shader.cso = sel;
2576 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
2577 si_update_tess_uses_prim_id(sctx);
2578
2579 si_update_common_shader_state(sctx);
2580
2581 if (enable_changed)
2582 sctx->last_tcs = NULL; /* invalidate derived tess state */
2583
2584 si_set_active_descriptors_for_shader(sctx, sel);
2585 }
2586
2587 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
2588 {
2589 struct si_context *sctx = (struct si_context *)ctx;
2590 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2591 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2592 struct si_shader_selector *sel = state;
2593 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
2594
2595 if (sctx->tes_shader.cso == sel)
2596 return;
2597
2598 sctx->tes_shader.cso = sel;
2599 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
2600 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
2601 si_update_tess_uses_prim_id(sctx);
2602
2603 si_update_common_shader_state(sctx);
2604 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2605
2606 if (enable_changed) {
2607 si_shader_change_notify(sctx);
2608 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
2609 }
2610 si_update_vs_viewport_state(sctx);
2611 si_set_active_descriptors_for_shader(sctx, sel);
2612 si_update_streamout_state(sctx);
2613 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2614 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2615 }
2616
2617 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2618 {
2619 struct si_context *sctx = (struct si_context *)ctx;
2620 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
2621 struct si_shader_selector *sel = state;
2622
2623 /* skip if supplied shader is one already in use */
2624 if (old_sel == sel)
2625 return;
2626
2627 sctx->ps_shader.cso = sel;
2628 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
2629
2630 si_update_common_shader_state(sctx);
2631 if (sel) {
2632 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2633 si_update_tess_uses_prim_id(sctx);
2634
2635 if (!old_sel ||
2636 old_sel->info.colors_written != sel->info.colors_written)
2637 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2638
2639 if (sctx->screen->has_out_of_order_rast &&
2640 (!old_sel ||
2641 old_sel->info.writes_memory != sel->info.writes_memory ||
2642 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
2643 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
2644 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2645 }
2646 si_set_active_descriptors_for_shader(sctx, sel);
2647 si_update_ps_colorbuf0_slot(sctx);
2648 }
2649
2650 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
2651 {
2652 if (shader->is_optimized) {
2653 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
2654 &shader->ready);
2655 }
2656
2657 util_queue_fence_destroy(&shader->ready);
2658
2659 if (shader->pm4) {
2660 switch (shader->selector->type) {
2661 case PIPE_SHADER_VERTEX:
2662 if (shader->key.as_ls) {
2663 assert(sctx->chip_class <= VI);
2664 si_pm4_delete_state(sctx, ls, shader->pm4);
2665 } else if (shader->key.as_es) {
2666 assert(sctx->chip_class <= VI);
2667 si_pm4_delete_state(sctx, es, shader->pm4);
2668 } else {
2669 si_pm4_delete_state(sctx, vs, shader->pm4);
2670 }
2671 break;
2672 case PIPE_SHADER_TESS_CTRL:
2673 si_pm4_delete_state(sctx, hs, shader->pm4);
2674 break;
2675 case PIPE_SHADER_TESS_EVAL:
2676 if (shader->key.as_es) {
2677 assert(sctx->chip_class <= VI);
2678 si_pm4_delete_state(sctx, es, shader->pm4);
2679 } else {
2680 si_pm4_delete_state(sctx, vs, shader->pm4);
2681 }
2682 break;
2683 case PIPE_SHADER_GEOMETRY:
2684 if (shader->is_gs_copy_shader)
2685 si_pm4_delete_state(sctx, vs, shader->pm4);
2686 else
2687 si_pm4_delete_state(sctx, gs, shader->pm4);
2688 break;
2689 case PIPE_SHADER_FRAGMENT:
2690 si_pm4_delete_state(sctx, ps, shader->pm4);
2691 break;
2692 }
2693 }
2694
2695 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
2696 si_shader_destroy(shader);
2697 free(shader);
2698 }
2699
2700 void si_destroy_shader_selector(struct si_context *sctx,
2701 struct si_shader_selector *sel)
2702 {
2703 struct si_shader *p = sel->first_variant, *c;
2704 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
2705 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
2706 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
2707 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
2708 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
2709 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
2710 };
2711
2712 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
2713
2714 if (current_shader[sel->type]->cso == sel) {
2715 current_shader[sel->type]->cso = NULL;
2716 current_shader[sel->type]->current = NULL;
2717 }
2718
2719 while (p) {
2720 c = p->next_variant;
2721 si_delete_shader(sctx, p);
2722 p = c;
2723 }
2724
2725 if (sel->main_shader_part)
2726 si_delete_shader(sctx, sel->main_shader_part);
2727 if (sel->main_shader_part_ls)
2728 si_delete_shader(sctx, sel->main_shader_part_ls);
2729 if (sel->main_shader_part_es)
2730 si_delete_shader(sctx, sel->main_shader_part_es);
2731 if (sel->gs_copy_shader)
2732 si_delete_shader(sctx, sel->gs_copy_shader);
2733
2734 util_queue_fence_destroy(&sel->ready);
2735 mtx_destroy(&sel->mutex);
2736 free(sel->tokens);
2737 ralloc_free(sel->nir);
2738 free(sel);
2739 }
2740
2741 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
2742 {
2743 struct si_context *sctx = (struct si_context *)ctx;
2744 struct si_shader_selector *sel = (struct si_shader_selector *)state;
2745
2746 si_shader_selector_reference(sctx, &sel, NULL);
2747 }
2748
2749 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
2750 struct si_shader *vs, unsigned name,
2751 unsigned index, unsigned interpolate)
2752 {
2753 struct tgsi_shader_info *vsinfo = &vs->selector->info;
2754 unsigned j, offset, ps_input_cntl = 0;
2755
2756 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
2757 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
2758 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2759
2760 if (name == TGSI_SEMANTIC_PCOORD ||
2761 (name == TGSI_SEMANTIC_TEXCOORD &&
2762 sctx->sprite_coord_enable & (1 << index))) {
2763 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
2764 }
2765
2766 for (j = 0; j < vsinfo->num_outputs; j++) {
2767 if (name == vsinfo->output_semantic_name[j] &&
2768 index == vsinfo->output_semantic_index[j]) {
2769 offset = vs->info.vs_output_param_offset[j];
2770
2771 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2772 /* The input is loaded from parameter memory. */
2773 ps_input_cntl |= S_028644_OFFSET(offset);
2774 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2775 if (offset == AC_EXP_PARAM_UNDEFINED) {
2776 /* This can happen with depth-only rendering. */
2777 offset = 0;
2778 } else {
2779 /* The input is a DEFAULT_VAL constant. */
2780 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2781 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2782 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2783 }
2784
2785 ps_input_cntl = S_028644_OFFSET(0x20) |
2786 S_028644_DEFAULT_VAL(offset);
2787 }
2788 break;
2789 }
2790 }
2791
2792 if (name == TGSI_SEMANTIC_PRIMID)
2793 /* PrimID is written after the last output. */
2794 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
2795 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2796 /* No corresponding output found, load defaults into input.
2797 * Don't set any other bits.
2798 * (FLAT_SHADE=1 completely changes behavior) */
2799 ps_input_cntl = S_028644_OFFSET(0x20);
2800 /* D3D 9 behaviour. GL is undefined */
2801 if (name == TGSI_SEMANTIC_COLOR && index == 0)
2802 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
2803 }
2804 return ps_input_cntl;
2805 }
2806
2807 static void si_emit_spi_map(struct si_context *sctx)
2808 {
2809 struct si_shader *ps = sctx->ps_shader.current;
2810 struct si_shader *vs = si_get_vs_state(sctx);
2811 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
2812 unsigned i, num_interp, num_written = 0, bcol_interp[2];
2813 unsigned spi_ps_input_cntl[32];
2814
2815 if (!ps || !ps->selector->info.num_inputs)
2816 return;
2817
2818 num_interp = si_get_ps_num_interp(ps);
2819 assert(num_interp > 0);
2820
2821 for (i = 0; i < psinfo->num_inputs; i++) {
2822 unsigned name = psinfo->input_semantic_name[i];
2823 unsigned index = psinfo->input_semantic_index[i];
2824 unsigned interpolate = psinfo->input_interpolate[i];
2825
2826 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
2827 index, interpolate);
2828
2829 if (name == TGSI_SEMANTIC_COLOR) {
2830 assert(index < ARRAY_SIZE(bcol_interp));
2831 bcol_interp[index] = interpolate;
2832 }
2833 }
2834
2835 if (ps->key.part.ps.prolog.color_two_side) {
2836 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
2837
2838 for (i = 0; i < 2; i++) {
2839 if (!(psinfo->colors_read & (0xf << (i * 4))))
2840 continue;
2841
2842 spi_ps_input_cntl[num_written++] =
2843 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
2844
2845 }
2846 }
2847 assert(num_interp == num_written);
2848
2849 /* R_028644_SPI_PS_INPUT_CNTL_0 */
2850 /* Dota 2: Only ~16% of SPI map updates set different values. */
2851 /* Talos: Only ~9% of SPI map updates set different values. */
2852 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
2853 spi_ps_input_cntl,
2854 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
2855 }
2856
2857 /**
2858 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2859 */
2860 static void si_init_config_add_vgt_flush(struct si_context *sctx)
2861 {
2862 if (sctx->init_config_has_vgt_flush)
2863 return;
2864
2865 /* Done by Vulkan before VGT_FLUSH. */
2866 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2867 si_pm4_cmd_add(sctx->init_config,
2868 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2869 si_pm4_cmd_end(sctx->init_config, false);
2870
2871 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2872 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2873 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2874 si_pm4_cmd_end(sctx->init_config, false);
2875 sctx->init_config_has_vgt_flush = true;
2876 }
2877
2878 /* Initialize state related to ESGS / GSVS ring buffers */
2879 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2880 {
2881 struct si_shader_selector *es =
2882 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2883 struct si_shader_selector *gs = sctx->gs_shader.cso;
2884 struct si_pm4_state *pm4;
2885
2886 /* Chip constants. */
2887 unsigned num_se = sctx->screen->info.max_se;
2888 unsigned wave_size = 64;
2889 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2890 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2891 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2892 */
2893 unsigned gs_vertex_reuse = (sctx->chip_class >= VI ? 32 : 16) * num_se;
2894 unsigned alignment = 256 * num_se;
2895 /* The maximum size is 63.999 MB per SE. */
2896 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2897
2898 /* Calculate the minimum size. */
2899 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
2900 wave_size, alignment);
2901
2902 /* These are recommended sizes, not minimum sizes. */
2903 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2904 es->esgs_itemsize * gs->gs_input_verts_per_prim;
2905 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2906 gs->max_gsvs_emit_size;
2907
2908 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2909 esgs_ring_size = align(esgs_ring_size, alignment);
2910 gsvs_ring_size = align(gsvs_ring_size, alignment);
2911
2912 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2913 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2914
2915 /* Some rings don't have to be allocated if shaders don't use them.
2916 * (e.g. no varyings between ES and GS or GS and VS)
2917 *
2918 * GFX9 doesn't have the ESGS ring.
2919 */
2920 bool update_esgs = sctx->chip_class <= VI &&
2921 esgs_ring_size &&
2922 (!sctx->esgs_ring ||
2923 sctx->esgs_ring->width0 < esgs_ring_size);
2924 bool update_gsvs = gsvs_ring_size &&
2925 (!sctx->gsvs_ring ||
2926 sctx->gsvs_ring->width0 < gsvs_ring_size);
2927
2928 if (!update_esgs && !update_gsvs)
2929 return true;
2930
2931 if (update_esgs) {
2932 pipe_resource_reference(&sctx->esgs_ring, NULL);
2933 sctx->esgs_ring =
2934 pipe_aligned_buffer_create(sctx->b.screen,
2935 SI_RESOURCE_FLAG_UNMAPPABLE,
2936 PIPE_USAGE_DEFAULT,
2937 esgs_ring_size, alignment);
2938 if (!sctx->esgs_ring)
2939 return false;
2940 }
2941
2942 if (update_gsvs) {
2943 pipe_resource_reference(&sctx->gsvs_ring, NULL);
2944 sctx->gsvs_ring =
2945 pipe_aligned_buffer_create(sctx->b.screen,
2946 SI_RESOURCE_FLAG_UNMAPPABLE,
2947 PIPE_USAGE_DEFAULT,
2948 gsvs_ring_size, alignment);
2949 if (!sctx->gsvs_ring)
2950 return false;
2951 }
2952
2953 /* Create the "init_config_gs_rings" state. */
2954 pm4 = CALLOC_STRUCT(si_pm4_state);
2955 if (!pm4)
2956 return false;
2957
2958 if (sctx->chip_class >= CIK) {
2959 if (sctx->esgs_ring) {
2960 assert(sctx->chip_class <= VI);
2961 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2962 sctx->esgs_ring->width0 / 256);
2963 }
2964 if (sctx->gsvs_ring)
2965 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2966 sctx->gsvs_ring->width0 / 256);
2967 } else {
2968 if (sctx->esgs_ring)
2969 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2970 sctx->esgs_ring->width0 / 256);
2971 if (sctx->gsvs_ring)
2972 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2973 sctx->gsvs_ring->width0 / 256);
2974 }
2975
2976 /* Set the state. */
2977 if (sctx->init_config_gs_rings)
2978 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
2979 sctx->init_config_gs_rings = pm4;
2980
2981 if (!sctx->init_config_has_vgt_flush) {
2982 si_init_config_add_vgt_flush(sctx);
2983 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2984 }
2985
2986 /* Flush the context to re-emit both init_config states. */
2987 sctx->initial_gfx_cs_size = 0; /* force flush */
2988 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
2989
2990 /* Set ring bindings. */
2991 if (sctx->esgs_ring) {
2992 assert(sctx->chip_class <= VI);
2993 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
2994 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2995 true, true, 4, 64, 0);
2996 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
2997 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2998 false, false, 0, 0, 0);
2999 }
3000 if (sctx->gsvs_ring) {
3001 si_set_ring_buffer(sctx, SI_RING_GSVS,
3002 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3003 false, false, 0, 0, 0);
3004 }
3005
3006 return true;
3007 }
3008
3009 static void si_shader_lock(struct si_shader *shader)
3010 {
3011 mtx_lock(&shader->selector->mutex);
3012 if (shader->previous_stage_sel) {
3013 assert(shader->previous_stage_sel != shader->selector);
3014 mtx_lock(&shader->previous_stage_sel->mutex);
3015 }
3016 }
3017
3018 static void si_shader_unlock(struct si_shader *shader)
3019 {
3020 if (shader->previous_stage_sel)
3021 mtx_unlock(&shader->previous_stage_sel->mutex);
3022 mtx_unlock(&shader->selector->mutex);
3023 }
3024
3025 /**
3026 * @returns 1 if \p sel has been updated to use a new scratch buffer
3027 * 0 if not
3028 * < 0 if there was a failure
3029 */
3030 static int si_update_scratch_buffer(struct si_context *sctx,
3031 struct si_shader *shader)
3032 {
3033 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3034 int r;
3035
3036 if (!shader)
3037 return 0;
3038
3039 /* This shader doesn't need a scratch buffer */
3040 if (shader->config.scratch_bytes_per_wave == 0)
3041 return 0;
3042
3043 /* Prevent race conditions when updating:
3044 * - si_shader::scratch_bo
3045 * - si_shader::binary::code
3046 * - si_shader::previous_stage::binary::code.
3047 */
3048 si_shader_lock(shader);
3049
3050 /* This shader is already configured to use the current
3051 * scratch buffer. */
3052 if (shader->scratch_bo == sctx->scratch_buffer) {
3053 si_shader_unlock(shader);
3054 return 0;
3055 }
3056
3057 assert(sctx->scratch_buffer);
3058
3059 if (shader->previous_stage)
3060 si_shader_apply_scratch_relocs(shader->previous_stage, scratch_va);
3061
3062 si_shader_apply_scratch_relocs(shader, scratch_va);
3063
3064 /* Replace the shader bo with a new bo that has the relocs applied. */
3065 r = si_shader_binary_upload(sctx->screen, shader);
3066 if (r) {
3067 si_shader_unlock(shader);
3068 return r;
3069 }
3070
3071 /* Update the shader state to use the new shader bo. */
3072 si_shader_init_pm4_state(sctx->screen, shader);
3073
3074 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3075
3076 si_shader_unlock(shader);
3077 return 1;
3078 }
3079
3080 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
3081 {
3082 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
3083 }
3084
3085 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3086 {
3087 return shader ? shader->config.scratch_bytes_per_wave : 0;
3088 }
3089
3090 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3091 {
3092 if (!sctx->tes_shader.cso)
3093 return NULL; /* tessellation disabled */
3094
3095 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3096 sctx->fixed_func_tcs_shader.current;
3097 }
3098
3099 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
3100 {
3101 unsigned bytes = 0;
3102
3103 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3104 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3105 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3106 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3107
3108 if (sctx->tes_shader.cso) {
3109 struct si_shader *tcs = si_get_tcs_current(sctx);
3110
3111 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
3112 }
3113 return bytes;
3114 }
3115
3116 static bool si_update_scratch_relocs(struct si_context *sctx)
3117 {
3118 struct si_shader *tcs = si_get_tcs_current(sctx);
3119 int r;
3120
3121 /* Update the shaders, so that they are using the latest scratch.
3122 * The scratch buffer may have been changed since these shaders were
3123 * last used, so we still need to try to update them, even if they
3124 * require scratch buffers smaller than the current size.
3125 */
3126 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3127 if (r < 0)
3128 return false;
3129 if (r == 1)
3130 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3131
3132 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3133 if (r < 0)
3134 return false;
3135 if (r == 1)
3136 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3137
3138 r = si_update_scratch_buffer(sctx, tcs);
3139 if (r < 0)
3140 return false;
3141 if (r == 1)
3142 si_pm4_bind_state(sctx, hs, tcs->pm4);
3143
3144 /* VS can be bound as LS, ES, or VS. */
3145 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3146 if (r < 0)
3147 return false;
3148 if (r == 1) {
3149 if (sctx->tes_shader.current)
3150 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3151 else if (sctx->gs_shader.current)
3152 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3153 else
3154 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3155 }
3156
3157 /* TES can be bound as ES or VS. */
3158 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3159 if (r < 0)
3160 return false;
3161 if (r == 1) {
3162 if (sctx->gs_shader.current)
3163 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3164 else
3165 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3166 }
3167
3168 return true;
3169 }
3170
3171 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3172 {
3173 unsigned current_scratch_buffer_size =
3174 si_get_current_scratch_buffer_size(sctx);
3175 unsigned scratch_bytes_per_wave =
3176 si_get_max_scratch_bytes_per_wave(sctx);
3177 unsigned scratch_needed_size = scratch_bytes_per_wave *
3178 sctx->scratch_waves;
3179 unsigned spi_tmpring_size;
3180
3181 if (scratch_needed_size > 0) {
3182 if (scratch_needed_size > current_scratch_buffer_size) {
3183 /* Create a bigger scratch buffer */
3184 r600_resource_reference(&sctx->scratch_buffer, NULL);
3185
3186 sctx->scratch_buffer =
3187 si_aligned_buffer_create(&sctx->screen->b,
3188 SI_RESOURCE_FLAG_UNMAPPABLE,
3189 PIPE_USAGE_DEFAULT,
3190 scratch_needed_size, 256);
3191 if (!sctx->scratch_buffer)
3192 return false;
3193
3194 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3195 si_context_add_resource_size(sctx,
3196 &sctx->scratch_buffer->b.b);
3197 }
3198
3199 if (!si_update_scratch_relocs(sctx))
3200 return false;
3201 }
3202
3203 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3204 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3205 "scratch size should already be aligned correctly.");
3206
3207 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3208 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3209 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3210 sctx->spi_tmpring_size = spi_tmpring_size;
3211 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3212 }
3213 return true;
3214 }
3215
3216 static void si_init_tess_factor_ring(struct si_context *sctx)
3217 {
3218 assert(!sctx->tess_rings);
3219
3220 /* The address must be aligned to 2^19, because the shader only
3221 * receives the high 13 bits.
3222 */
3223 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3224 SI_RESOURCE_FLAG_32BIT,
3225 PIPE_USAGE_DEFAULT,
3226 sctx->screen->tess_offchip_ring_size +
3227 sctx->screen->tess_factor_ring_size,
3228 1 << 19);
3229 if (!sctx->tess_rings)
3230 return;
3231
3232 si_init_config_add_vgt_flush(sctx);
3233
3234 si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_rings),
3235 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3236
3237 uint64_t factor_va = r600_resource(sctx->tess_rings)->gpu_address +
3238 sctx->screen->tess_offchip_ring_size;
3239
3240 /* Append these registers to the init config state. */
3241 if (sctx->chip_class >= CIK) {
3242 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3243 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3244 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3245 factor_va >> 8);
3246 if (sctx->chip_class >= GFX9)
3247 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3248 S_030944_BASE_HI(factor_va >> 40));
3249 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3250 sctx->screen->vgt_hs_offchip_param);
3251 } else {
3252 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3253 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3254 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3255 factor_va >> 8);
3256 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3257 sctx->screen->vgt_hs_offchip_param);
3258 }
3259
3260 /* Flush the context to re-emit the init_config state.
3261 * This is done only once in a lifetime of a context.
3262 */
3263 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3264 sctx->initial_gfx_cs_size = 0; /* force flush */
3265 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3266 }
3267
3268 static void si_update_vgt_shader_config(struct si_context *sctx)
3269 {
3270 /* Calculate the index of the config.
3271 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3272 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
3273 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
3274
3275 if (!*pm4) {
3276 uint32_t stages = 0;
3277
3278 *pm4 = CALLOC_STRUCT(si_pm4_state);
3279
3280 if (sctx->tes_shader.cso) {
3281 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3282 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3283
3284 if (sctx->gs_shader.cso)
3285 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3286 S_028B54_GS_EN(1) |
3287 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3288 else
3289 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3290 } else if (sctx->gs_shader.cso) {
3291 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3292 S_028B54_GS_EN(1) |
3293 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3294 }
3295
3296 if (sctx->chip_class >= GFX9)
3297 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3298
3299 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3300 }
3301 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3302 }
3303
3304 bool si_update_shaders(struct si_context *sctx)
3305 {
3306 struct pipe_context *ctx = (struct pipe_context*)sctx;
3307 struct si_compiler_ctx_state compiler_state;
3308 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3309 struct si_shader *old_vs = si_get_vs_state(sctx);
3310 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3311 struct si_shader *old_ps = sctx->ps_shader.current;
3312 unsigned old_spi_shader_col_format =
3313 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3314 int r;
3315
3316 compiler_state.compiler = &sctx->compiler;
3317 compiler_state.debug = sctx->debug;
3318 compiler_state.is_debug_context = sctx->is_debug;
3319
3320 /* Update stages before GS. */
3321 if (sctx->tes_shader.cso) {
3322 if (!sctx->tess_rings) {
3323 si_init_tess_factor_ring(sctx);
3324 if (!sctx->tess_rings)
3325 return false;
3326 }
3327
3328 /* VS as LS */
3329 if (sctx->chip_class <= VI) {
3330 r = si_shader_select(ctx, &sctx->vs_shader,
3331 &compiler_state);
3332 if (r)
3333 return false;
3334 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3335 }
3336
3337 if (sctx->tcs_shader.cso) {
3338 r = si_shader_select(ctx, &sctx->tcs_shader,
3339 &compiler_state);
3340 if (r)
3341 return false;
3342 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3343 } else {
3344 if (!sctx->fixed_func_tcs_shader.cso) {
3345 sctx->fixed_func_tcs_shader.cso =
3346 si_create_fixed_func_tcs(sctx);
3347 if (!sctx->fixed_func_tcs_shader.cso)
3348 return false;
3349 }
3350
3351 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3352 &compiler_state);
3353 if (r)
3354 return false;
3355 si_pm4_bind_state(sctx, hs,
3356 sctx->fixed_func_tcs_shader.current->pm4);
3357 }
3358
3359 if (sctx->gs_shader.cso) {
3360 /* TES as ES */
3361 if (sctx->chip_class <= VI) {
3362 r = si_shader_select(ctx, &sctx->tes_shader,
3363 &compiler_state);
3364 if (r)
3365 return false;
3366 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3367 }
3368 } else {
3369 /* TES as VS */
3370 r = si_shader_select(ctx, &sctx->tes_shader,
3371 &compiler_state);
3372 if (r)
3373 return false;
3374 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3375 }
3376 } else if (sctx->gs_shader.cso) {
3377 if (sctx->chip_class <= VI) {
3378 /* VS as ES */
3379 r = si_shader_select(ctx, &sctx->vs_shader,
3380 &compiler_state);
3381 if (r)
3382 return false;
3383 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3384
3385 si_pm4_bind_state(sctx, ls, NULL);
3386 si_pm4_bind_state(sctx, hs, NULL);
3387 }
3388 } else {
3389 /* VS as VS */
3390 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
3391 if (r)
3392 return false;
3393 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3394 si_pm4_bind_state(sctx, ls, NULL);
3395 si_pm4_bind_state(sctx, hs, NULL);
3396 }
3397
3398 /* Update GS. */
3399 if (sctx->gs_shader.cso) {
3400 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
3401 if (r)
3402 return false;
3403 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3404 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3405
3406 if (!si_update_gs_ring_buffers(sctx))
3407 return false;
3408 } else {
3409 si_pm4_bind_state(sctx, gs, NULL);
3410 if (sctx->chip_class <= VI)
3411 si_pm4_bind_state(sctx, es, NULL);
3412 }
3413
3414 si_update_vgt_shader_config(sctx);
3415
3416 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3417 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3418
3419 if (sctx->ps_shader.cso) {
3420 unsigned db_shader_control;
3421
3422 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
3423 if (r)
3424 return false;
3425 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3426
3427 db_shader_control =
3428 sctx->ps_shader.cso->db_shader_control |
3429 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3430
3431 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3432 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3433 sctx->flatshade != rs->flatshade) {
3434 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3435 sctx->flatshade = rs->flatshade;
3436 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3437 }
3438
3439 if (sctx->screen->rbplus_allowed &&
3440 si_pm4_state_changed(sctx, ps) &&
3441 (!old_ps ||
3442 old_spi_shader_col_format !=
3443 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3444 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3445
3446 if (sctx->ps_db_shader_control != db_shader_control) {
3447 sctx->ps_db_shader_control = db_shader_control;
3448 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3449 if (sctx->screen->dpbb_allowed)
3450 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3451 }
3452
3453 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3454 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3455 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3456
3457 if (sctx->chip_class == SI)
3458 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3459
3460 if (sctx->framebuffer.nr_samples <= 1)
3461 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3462 }
3463 }
3464
3465 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3466 si_pm4_state_enabled_and_changed(sctx, hs) ||
3467 si_pm4_state_enabled_and_changed(sctx, es) ||
3468 si_pm4_state_enabled_and_changed(sctx, gs) ||
3469 si_pm4_state_enabled_and_changed(sctx, vs) ||
3470 si_pm4_state_enabled_and_changed(sctx, ps)) {
3471 if (!si_update_spi_tmpring_size(sctx))
3472 return false;
3473 }
3474
3475 if (sctx->chip_class >= CIK) {
3476 if (si_pm4_state_enabled_and_changed(sctx, ls))
3477 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3478 else if (!sctx->queued.named.ls)
3479 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3480
3481 if (si_pm4_state_enabled_and_changed(sctx, hs))
3482 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3483 else if (!sctx->queued.named.hs)
3484 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3485
3486 if (si_pm4_state_enabled_and_changed(sctx, es))
3487 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
3488 else if (!sctx->queued.named.es)
3489 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
3490
3491 if (si_pm4_state_enabled_and_changed(sctx, gs))
3492 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
3493 else if (!sctx->queued.named.gs)
3494 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
3495
3496 if (si_pm4_state_enabled_and_changed(sctx, vs))
3497 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
3498 else if (!sctx->queued.named.vs)
3499 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
3500
3501 if (si_pm4_state_enabled_and_changed(sctx, ps))
3502 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
3503 else if (!sctx->queued.named.ps)
3504 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
3505 }
3506
3507 sctx->do_update_shaders = false;
3508 return true;
3509 }
3510
3511 static void si_emit_scratch_state(struct si_context *sctx)
3512 {
3513 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3514
3515 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3516 sctx->spi_tmpring_size);
3517
3518 if (sctx->scratch_buffer) {
3519 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3520 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3521 RADEON_PRIO_SCRATCH_BUFFER);
3522 }
3523 }
3524
3525 void si_init_shader_functions(struct si_context *sctx)
3526 {
3527 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
3528 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
3529
3530 sctx->b.create_vs_state = si_create_shader_selector;
3531 sctx->b.create_tcs_state = si_create_shader_selector;
3532 sctx->b.create_tes_state = si_create_shader_selector;
3533 sctx->b.create_gs_state = si_create_shader_selector;
3534 sctx->b.create_fs_state = si_create_shader_selector;
3535
3536 sctx->b.bind_vs_state = si_bind_vs_shader;
3537 sctx->b.bind_tcs_state = si_bind_tcs_shader;
3538 sctx->b.bind_tes_state = si_bind_tes_shader;
3539 sctx->b.bind_gs_state = si_bind_gs_shader;
3540 sctx->b.bind_fs_state = si_bind_ps_shader;
3541
3542 sctx->b.delete_vs_state = si_delete_shader_selector;
3543 sctx->b.delete_tcs_state = si_delete_shader_selector;
3544 sctx->b.delete_tes_state = si_delete_shader_selector;
3545 sctx->b.delete_gs_state = si_delete_shader_selector;
3546 sctx->b.delete_fs_state = si_delete_shader_selector;
3547 }