projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: remove the gs_rings state, add the registers to init_config
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "si_shader.h"
30 #include "sid.h"
31
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_ureg.h"
34 #include "util/u_memory.h"
35 #include "util/u_simple_shaders.h"
36
37 static void si_set_tesseval_regs(struct si_shader *shader,
38 struct si_pm4_state *pm4)
39 {
40 struct tgsi_shader_info *info = &shader->selector->info;
41 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
42 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
43 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
44 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
45 unsigned type, partitioning, topology;
46
47 switch (tes_prim_mode) {
48 case PIPE_PRIM_LINES:
49 type = V_028B6C_TESS_ISOLINE;
50 break;
51 case PIPE_PRIM_TRIANGLES:
52 type = V_028B6C_TESS_TRIANGLE;
53 break;
54 case PIPE_PRIM_QUADS:
55 type = V_028B6C_TESS_QUAD;
56 break;
57 default:
58 assert(0);
59 return;
60 }
61
62 switch (tes_spacing) {
63 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
64 partitioning = V_028B6C_PART_FRAC_ODD;
65 break;
66 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
67 partitioning = V_028B6C_PART_FRAC_EVEN;
68 break;
69 case PIPE_TESS_SPACING_EQUAL:
70 partitioning = V_028B6C_PART_INTEGER;
71 break;
72 default:
73 assert(0);
74 return;
75 }
76
77 if (tes_point_mode)
78 topology = V_028B6C_OUTPUT_POINT;
79 else if (tes_prim_mode == PIPE_PRIM_LINES)
80 topology = V_028B6C_OUTPUT_LINE;
81 else if (tes_vertex_order_cw)
82 /* for some reason, this must be the other way around */
83 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
84 else
85 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
86
87 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
88 S_028B6C_TYPE(type) |
89 S_028B6C_PARTITIONING(partitioning) |
90 S_028B6C_TOPOLOGY(topology));
91 }
92
93 static void si_shader_ls(struct si_shader *shader)
94 {
95 struct si_pm4_state *pm4;
96 unsigned num_sgprs, num_user_sgprs;
97 unsigned vgpr_comp_cnt;
98 uint64_t va;
99
100 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
101 if (pm4 == NULL)
102 return;
103
104 va = shader->bo->gpu_address;
105 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
106
107 /* We need at least 2 components for LS.
108 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
109 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 1;
110
111 num_user_sgprs = SI_LS_NUM_USER_SGPR;
112 num_sgprs = shader->num_sgprs;
113 if (num_user_sgprs > num_sgprs) {
114 /* Last 2 reserved SGPRs are used for VCC */
115 num_sgprs = num_user_sgprs + 2;
116 }
117 assert(num_sgprs <= 104);
118
119 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
120 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
121
122 shader->ls_rsrc1 = S_00B528_VGPRS((shader->num_vgprs - 1) / 4) |
123 S_00B528_SGPRS((num_sgprs - 1) / 8) |
124 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt);
125 shader->ls_rsrc2 = S_00B52C_USER_SGPR(num_user_sgprs) |
126 S_00B52C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0);
127 }
128
129 static void si_shader_hs(struct si_shader *shader)
130 {
131 struct si_pm4_state *pm4;
132 unsigned num_sgprs, num_user_sgprs;
133 uint64_t va;
134
135 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
136 if (pm4 == NULL)
137 return;
138
139 va = shader->bo->gpu_address;
140 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
141
142 num_user_sgprs = SI_TCS_NUM_USER_SGPR;
143 num_sgprs = shader->num_sgprs;
144 /* One SGPR after user SGPRs is pre-loaded with tessellation factor
145 * buffer offset. */
146 if ((num_user_sgprs + 1) > num_sgprs) {
147 /* Last 2 reserved SGPRs are used for VCC */
148 num_sgprs = num_user_sgprs + 1 + 2;
149 }
150 assert(num_sgprs <= 104);
151
152 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
153 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
154 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
155 S_00B428_VGPRS((shader->num_vgprs - 1) / 4) |
156 S_00B428_SGPRS((num_sgprs - 1) / 8));
157 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
158 S_00B42C_USER_SGPR(num_user_sgprs) |
159 S_00B42C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
160 }
161
162 static void si_shader_es(struct si_shader *shader)
163 {
164 struct si_pm4_state *pm4;
165 unsigned num_sgprs, num_user_sgprs;
166 unsigned vgpr_comp_cnt;
167 uint64_t va;
168
169 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
170
171 if (pm4 == NULL)
172 return;
173
174 va = shader->bo->gpu_address;
175 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
176
177 if (shader->selector->type == PIPE_SHADER_VERTEX) {
178 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
179 num_user_sgprs = SI_VS_NUM_USER_SGPR;
180 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
181 vgpr_comp_cnt = 3; /* all components are needed for TES */
182 num_user_sgprs = SI_TES_NUM_USER_SGPR;
183 } else
184 unreachable("invalid shader selector type");
185
186 num_sgprs = shader->num_sgprs;
187 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
188 if ((num_user_sgprs + 1) > num_sgprs) {
189 /* Last 2 reserved SGPRs are used for VCC */
190 num_sgprs = num_user_sgprs + 1 + 2;
191 }
192 assert(num_sgprs <= 104);
193
194 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
195 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
196 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
197 S_00B328_VGPRS((shader->num_vgprs - 1) / 4) |
198 S_00B328_SGPRS((num_sgprs - 1) / 8) |
199 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
200 S_00B328_DX10_CLAMP(shader->dx10_clamp_mode));
201 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
202 S_00B32C_USER_SGPR(num_user_sgprs) |
203 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
204
205 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
206 si_set_tesseval_regs(shader, pm4);
207 }
208
209 static unsigned si_gs_get_max_stream(struct si_shader *shader)
210 {
211 struct pipe_stream_output_info *so = &shader->selector->so;
212 unsigned max_stream = 0, i;
213
214 if (so->num_outputs == 0)
215 return 0;
216
217 for (i = 0; i < so->num_outputs; i++) {
218 if (so->output[i].stream > max_stream)
219 max_stream = so->output[i].stream;
220 }
221 return max_stream;
222 }
223
224 static void si_shader_gs(struct si_shader *shader)
225 {
226 unsigned gs_vert_itemsize = shader->selector->info.num_outputs * 16;
227 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
228 unsigned gsvs_itemsize = (gs_vert_itemsize * gs_max_vert_out) >> 2;
229 unsigned gs_num_invocations = shader->selector->gs_num_invocations;
230 unsigned cut_mode;
231 struct si_pm4_state *pm4;
232 unsigned num_sgprs, num_user_sgprs;
233 uint64_t va;
234 unsigned max_stream = si_gs_get_max_stream(shader);
235
236 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
237 assert(gsvs_itemsize < (1 << 15));
238
239 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
240
241 if (pm4 == NULL)
242 return;
243
244 if (gs_max_vert_out <= 128) {
245 cut_mode = V_028A40_GS_CUT_128;
246 } else if (gs_max_vert_out <= 256) {
247 cut_mode = V_028A40_GS_CUT_256;
248 } else if (gs_max_vert_out <= 512) {
249 cut_mode = V_028A40_GS_CUT_512;
250 } else {
251 assert(gs_max_vert_out <= 1024);
252 cut_mode = V_028A40_GS_CUT_1024;
253 }
254
255 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
256 S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
257 S_028A40_CUT_MODE(cut_mode)|
258 S_028A40_ES_WRITE_OPTIMIZE(1) |
259 S_028A40_GS_WRITE_OPTIMIZE(1));
260
261 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
262 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize * ((max_stream >= 2) ? 2 : 1));
263 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize * ((max_stream >= 3) ? 3 : 1));
264
265 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
266 util_bitcount64(shader->selector->inputs_read) * (16 >> 2));
267 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize * (max_stream + 1));
268
269 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, gs_max_vert_out);
270
271 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize >> 2);
272 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? gs_vert_itemsize >> 2 : 0);
273 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? gs_vert_itemsize >> 2 : 0);
274 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? gs_vert_itemsize >> 2 : 0);
275
276 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
277 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
278 S_028B90_ENABLE(gs_num_invocations > 0));
279
280 va = shader->bo->gpu_address;
281 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
282 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
283 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
284
285 num_user_sgprs = SI_GS_NUM_USER_SGPR;
286 num_sgprs = shader->num_sgprs;
287 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
288 if ((num_user_sgprs + 2) > num_sgprs) {
289 /* Last 2 reserved SGPRs are used for VCC */
290 num_sgprs = num_user_sgprs + 2 + 2;
291 }
292 assert(num_sgprs <= 104);
293
294 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
295 S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
296 S_00B228_SGPRS((num_sgprs - 1) / 8) |
297 S_00B228_DX10_CLAMP(shader->dx10_clamp_mode));
298 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
299 S_00B22C_USER_SGPR(num_user_sgprs) |
300 S_00B22C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
301 }
302
303 static void si_shader_vs(struct si_shader *shader)
304 {
305 struct si_pm4_state *pm4;
306 unsigned num_sgprs, num_user_sgprs;
307 unsigned nparams, vgpr_comp_cnt;
308 uint64_t va;
309 unsigned window_space =
310 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
311 bool enable_prim_id = si_vs_exports_prim_id(shader);
312
313 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
314
315 if (pm4 == NULL)
316 return;
317
318 /* If this is the GS copy shader, the GS state writes this register.
319 * Otherwise, the VS state writes it.
320 */
321 if (!shader->is_gs_copy_shader) {
322 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
323 S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
324 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
325 } else
326 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
327
328 va = shader->bo->gpu_address;
329 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
330
331 if (shader->is_gs_copy_shader) {
332 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
333 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
334 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
335 vgpr_comp_cnt = shader->uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
336 num_user_sgprs = SI_VS_NUM_USER_SGPR;
337 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
338 vgpr_comp_cnt = 3; /* all components are needed for TES */
339 num_user_sgprs = SI_TES_NUM_USER_SGPR;
340 } else
341 unreachable("invalid shader selector type");
342
343 num_sgprs = shader->num_sgprs;
344 if (num_user_sgprs > num_sgprs) {
345 /* Last 2 reserved SGPRs are used for VCC */
346 num_sgprs = num_user_sgprs + 2;
347 }
348 assert(num_sgprs <= 104);
349
350 /* VS is required to export at least one param. */
351 nparams = MAX2(shader->nr_param_exports, 1);
352 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
353 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
354
355 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
356 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
357 S_02870C_POS1_EXPORT_FORMAT(shader->nr_pos_exports > 1 ?
358 V_02870C_SPI_SHADER_4COMP :
359 V_02870C_SPI_SHADER_NONE) |
360 S_02870C_POS2_EXPORT_FORMAT(shader->nr_pos_exports > 2 ?
361 V_02870C_SPI_SHADER_4COMP :
362 V_02870C_SPI_SHADER_NONE) |
363 S_02870C_POS3_EXPORT_FORMAT(shader->nr_pos_exports > 3 ?
364 V_02870C_SPI_SHADER_4COMP :
365 V_02870C_SPI_SHADER_NONE));
366
367 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
368 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
369 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
370 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
371 S_00B128_SGPRS((num_sgprs - 1) / 8) |
372 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
373 S_00B128_DX10_CLAMP(shader->dx10_clamp_mode));
374 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
375 S_00B12C_USER_SGPR(num_user_sgprs) |
376 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
377 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
378 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
379 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
380 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
381 S_00B12C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
382 if (window_space)
383 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
384 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
385 else
386 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
387 S_028818_VTX_W0_FMT(1) |
388 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
389 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
390 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
391
392 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
393 si_set_tesseval_regs(shader, pm4);
394 }
395
396 static void si_shader_ps(struct si_shader *shader)
397 {
398 struct tgsi_shader_info *info = &shader->selector->info;
399 struct si_pm4_state *pm4;
400 unsigned i, spi_ps_in_control;
401 unsigned num_sgprs, num_user_sgprs;
402 unsigned spi_baryc_cntl = 0, spi_ps_input_ena;
403 uint64_t va;
404
405 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
406
407 if (pm4 == NULL)
408 return;
409
410 for (i = 0; i < info->num_inputs; i++) {
411 switch (info->input_semantic_name[i]) {
412 case TGSI_SEMANTIC_POSITION:
413 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
414 * Possible vaules:
415 * 0 -> Position = pixel center (default)
416 * 1 -> Position = pixel centroid
417 * 2 -> Position = at sample position
418 */
419 switch (info->input_interpolate_loc[i]) {
420 case TGSI_INTERPOLATE_LOC_CENTROID:
421 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
422 break;
423 case TGSI_INTERPOLATE_LOC_SAMPLE:
424 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
425 break;
426 }
427
428 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
429 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
430 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
431 break;
432 }
433 }
434
435 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->nparam) |
436 S_0286D8_BC_OPTIMIZE_DISABLE(1);
437
438 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
439 spi_ps_input_ena = shader->spi_ps_input_ena;
440 /* we need to enable at least one of them, otherwise we hang the GPU */
441 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
442 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
443 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
444 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
445 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
446 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
447 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
448 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
449
450 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
451 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
452 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
453
454 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
455 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
456 shader->spi_shader_col_format);
457 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
458
459 va = shader->bo->gpu_address;
460 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
461 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
462 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
463
464 num_user_sgprs = SI_PS_NUM_USER_SGPR;
465 num_sgprs = shader->num_sgprs;
466 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
467 if ((num_user_sgprs + 1) > num_sgprs) {
468 /* Last 2 reserved SGPRs are used for VCC */
469 num_sgprs = num_user_sgprs + 1 + 2;
470 }
471 assert(num_sgprs <= 104);
472
473 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
474 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
475 S_00B028_SGPRS((num_sgprs - 1) / 8) |
476 S_00B028_DX10_CLAMP(shader->dx10_clamp_mode));
477 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
478 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
479 S_00B02C_USER_SGPR(num_user_sgprs) |
480 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
481 }
482
483 static void si_shader_init_pm4_state(struct si_shader *shader)
484 {
485
486 if (shader->pm4)
487 si_pm4_free_state_simple(shader->pm4);
488
489 switch (shader->selector->type) {
490 case PIPE_SHADER_VERTEX:
491 if (shader->key.vs.as_ls)
492 si_shader_ls(shader);
493 else if (shader->key.vs.as_es)
494 si_shader_es(shader);
495 else
496 si_shader_vs(shader);
497 break;
498 case PIPE_SHADER_TESS_CTRL:
499 si_shader_hs(shader);
500 break;
501 case PIPE_SHADER_TESS_EVAL:
502 if (shader->key.tes.as_es)
503 si_shader_es(shader);
504 else
505 si_shader_vs(shader);
506 break;
507 case PIPE_SHADER_GEOMETRY:
508 si_shader_gs(shader);
509 si_shader_vs(shader->gs_copy_shader);
510 break;
511 case PIPE_SHADER_FRAGMENT:
512 si_shader_ps(shader);
513 break;
514 default:
515 assert(0);
516 }
517 }
518
519 /* Compute the key for the hw shader variant */
520 static inline void si_shader_selector_key(struct pipe_context *ctx,
521 struct si_shader_selector *sel,
522 union si_shader_key *key)
523 {
524 struct si_context *sctx = (struct si_context *)ctx;
525 unsigned i;
526
527 memset(key, 0, sizeof(*key));
528
529 switch (sel->type) {
530 case PIPE_SHADER_VERTEX:
531 if (sctx->vertex_elements)
532 for (i = 0; i < sctx->vertex_elements->count; ++i)
533 key->vs.instance_divisors[i] =
534 sctx->vertex_elements->elements[i].instance_divisor;
535
536 if (sctx->tes_shader)
537 key->vs.as_ls = 1;
538 else if (sctx->gs_shader) {
539 key->vs.as_es = 1;
540 key->vs.es_enabled_outputs = sctx->gs_shader->inputs_read;
541 }
542
543 if (!sctx->gs_shader && sctx->ps_shader &&
544 sctx->ps_shader->info.uses_primid)
545 key->vs.export_prim_id = 1;
546 break;
547 case PIPE_SHADER_TESS_CTRL:
548 key->tcs.prim_mode =
549 sctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
550 break;
551 case PIPE_SHADER_TESS_EVAL:
552 if (sctx->gs_shader) {
553 key->tes.as_es = 1;
554 key->tes.es_enabled_outputs = sctx->gs_shader->inputs_read;
555 } else if (sctx->ps_shader && sctx->ps_shader->info.uses_primid)
556 key->tes.export_prim_id = 1;
557 break;
558 case PIPE_SHADER_GEOMETRY:
559 break;
560 case PIPE_SHADER_FRAGMENT: {
561 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
562
563 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
564 key->ps.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
565 key->ps.export_16bpc = sctx->framebuffer.export_16bpc;
566
567 if (rs) {
568 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
569 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
570 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
571 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
572
573 key->ps.color_two_side = rs->two_side;
574
575 if (sctx->queued.named.blend) {
576 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
577 rs->multisample_enable &&
578 !sctx->framebuffer.cb0_is_integer;
579 }
580
581 key->ps.poly_stipple = rs->poly_stipple_enable && is_poly;
582 key->ps.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
583 (is_line && rs->line_smooth)) &&
584 sctx->framebuffer.nr_samples <= 1;
585 }
586
587 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
588 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
589 if (sctx->queued.named.dsa &&
590 !sctx->framebuffer.cb0_is_integer)
591 key->ps.alpha_func = sctx->queued.named.dsa->alpha_func;
592 break;
593 }
594 default:
595 assert(0);
596 }
597 }
598
599 /* Select the hw shader variant depending on the current state. */
600 static int si_shader_select(struct pipe_context *ctx,
601 struct si_shader_selector *sel)
602 {
603 struct si_context *sctx = (struct si_context *)ctx;
604 union si_shader_key key;
605 struct si_shader * shader = NULL;
606 int r;
607
608 si_shader_selector_key(ctx, sel, &key);
609
610 /* Check if we don't need to change anything.
611 * This path is also used for most shaders that don't need multiple
612 * variants, it will cost just a computation of the key and this
613 * test. */
614 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
615 return 0;
616 }
617
618 /* lookup if we have other variants in the list */
619 if (sel->num_shaders > 1) {
620 struct si_shader *p = sel->current, *c = p->next_variant;
621
622 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
623 p = c;
624 c = c->next_variant;
625 }
626
627 if (c) {
628 p->next_variant = c->next_variant;
629 shader = c;
630 }
631 }
632
633 if (shader) {
634 shader->next_variant = sel->current;
635 sel->current = shader;
636 } else {
637 shader = CALLOC(1, sizeof(struct si_shader));
638 shader->selector = sel;
639 shader->key = key;
640
641 shader->next_variant = sel->current;
642 sel->current = shader;
643 r = si_shader_create((struct si_screen*)ctx->screen, sctx->tm,
644 shader);
645 if (unlikely(r)) {
646 R600_ERR("Failed to build shader variant (type=%u) %d\n",
647 sel->type, r);
648 sel->current = NULL;
649 FREE(shader);
650 return r;
651 }
652 si_shader_init_pm4_state(shader);
653 sel->num_shaders++;
654 p_atomic_inc(&sctx->screen->b.num_compilations);
655 }
656
657 return 0;
658 }
659
660 static void *si_create_shader_state(struct pipe_context *ctx,
661 const struct pipe_shader_state *state,
662 unsigned pipe_shader_type)
663 {
664 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
665 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
666 int i;
667
668 sel->type = pipe_shader_type;
669 sel->tokens = tgsi_dup_tokens(state->tokens);
670 sel->so = state->stream_output;
671 tgsi_scan_shader(state->tokens, &sel->info);
672 p_atomic_inc(&sscreen->b.num_shaders_created);
673
674 switch (pipe_shader_type) {
675 case PIPE_SHADER_GEOMETRY:
676 sel->gs_output_prim =
677 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
678 sel->gs_max_out_vertices =
679 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
680 sel->gs_num_invocations =
681 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
682
683 for (i = 0; i < sel->info.num_inputs; i++) {
684 unsigned name = sel->info.input_semantic_name[i];
685 unsigned index = sel->info.input_semantic_index[i];
686
687 switch (name) {
688 case TGSI_SEMANTIC_PRIMID:
689 break;
690 default:
691 sel->inputs_read |=
692 1llu << si_shader_io_get_unique_index(name, index);
693 }
694 }
695 break;
696
697 case PIPE_SHADER_VERTEX:
698 case PIPE_SHADER_TESS_CTRL:
699 for (i = 0; i < sel->info.num_outputs; i++) {
700 unsigned name = sel->info.output_semantic_name[i];
701 unsigned index = sel->info.output_semantic_index[i];
702
703 switch (name) {
704 case TGSI_SEMANTIC_TESSINNER:
705 case TGSI_SEMANTIC_TESSOUTER:
706 case TGSI_SEMANTIC_PATCH:
707 sel->patch_outputs_written |=
708 1llu << si_shader_io_get_unique_index(name, index);
709 break;
710 default:
711 sel->outputs_written |=
712 1llu << si_shader_io_get_unique_index(name, index);
713 }
714 }
715 break;
716 case PIPE_SHADER_FRAGMENT:
717 for (i = 0; i < sel->info.num_outputs; i++) {
718 unsigned name = sel->info.output_semantic_name[i];
719 unsigned index = sel->info.output_semantic_index[i];
720
721 if (name == TGSI_SEMANTIC_COLOR)
722 sel->ps_colors_written |= 1 << index;
723 }
724 break;
725 }
726
727 if (sscreen->b.debug_flags & DBG_PRECOMPILE)
728 si_shader_select(ctx, sel);
729
730 return sel;
731 }
732
733 static void *si_create_fs_state(struct pipe_context *ctx,
734 const struct pipe_shader_state *state)
735 {
736 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
737 }
738
739 static void *si_create_gs_state(struct pipe_context *ctx,
740 const struct pipe_shader_state *state)
741 {
742 return si_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
743 }
744
745 static void *si_create_vs_state(struct pipe_context *ctx,
746 const struct pipe_shader_state *state)
747 {
748 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
749 }
750
751 static void *si_create_tcs_state(struct pipe_context *ctx,
752 const struct pipe_shader_state *state)
753 {
754 return si_create_shader_state(ctx, state, PIPE_SHADER_TESS_CTRL);
755 }
756
757 static void *si_create_tes_state(struct pipe_context *ctx,
758 const struct pipe_shader_state *state)
759 {
760 return si_create_shader_state(ctx, state, PIPE_SHADER_TESS_EVAL);
761 }
762
763 /**
764 * Normally, we only emit 1 viewport and 1 scissor if no shader is using
765 * the VIEWPORT_INDEX output, and emitting the other viewports and scissors
766 * is delayed. When a shader with VIEWPORT_INDEX appears, this should be
767 * called to emit the rest.
768 */
769 static void si_update_viewports_and_scissors(struct si_context *sctx)
770 {
771 struct tgsi_shader_info *info = si_get_vs_info(sctx);
772
773 if (!info || !info->writes_viewport_index)
774 return;
775
776 if (sctx->scissors.dirty_mask)
777 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
778 if (sctx->viewports.dirty_mask)
779 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
780 }
781
782 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
783 {
784 struct si_context *sctx = (struct si_context *)ctx;
785 struct si_shader_selector *sel = state;
786
787 if (sctx->vs_shader == sel || !sel)
788 return;
789
790 sctx->vs_shader = sel;
791 si_mark_atom_dirty(sctx, &sctx->clip_regs);
792 si_update_viewports_and_scissors(sctx);
793 }
794
795 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
796 {
797 struct si_context *sctx = (struct si_context *)ctx;
798 struct si_shader_selector *sel = state;
799 bool enable_changed = !!sctx->gs_shader != !!sel;
800
801 if (sctx->gs_shader == sel)
802 return;
803
804 sctx->gs_shader = sel;
805 si_mark_atom_dirty(sctx, &sctx->clip_regs);
806 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
807
808 if (enable_changed)
809 si_shader_change_notify(sctx);
810 si_update_viewports_and_scissors(sctx);
811 }
812
813 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
814 {
815 struct si_context *sctx = (struct si_context *)ctx;
816 struct si_shader_selector *sel = state;
817 bool enable_changed = !!sctx->tcs_shader != !!sel;
818
819 if (sctx->tcs_shader == sel)
820 return;
821
822 sctx->tcs_shader = sel;
823
824 if (enable_changed)
825 sctx->last_tcs = NULL; /* invalidate derived tess state */
826 }
827
828 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
829 {
830 struct si_context *sctx = (struct si_context *)ctx;
831 struct si_shader_selector *sel = state;
832 bool enable_changed = !!sctx->tes_shader != !!sel;
833
834 if (sctx->tes_shader == sel)
835 return;
836
837 sctx->tes_shader = sel;
838 si_mark_atom_dirty(sctx, &sctx->clip_regs);
839 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
840
841 if (enable_changed) {
842 si_shader_change_notify(sctx);
843 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
844 }
845 si_update_viewports_and_scissors(sctx);
846 }
847
848 static void si_make_dummy_ps(struct si_context *sctx)
849 {
850 if (!sctx->dummy_pixel_shader) {
851 sctx->dummy_pixel_shader =
852 util_make_fragment_cloneinput_shader(&sctx->b.b, 0,
853 TGSI_SEMANTIC_GENERIC,
854 TGSI_INTERPOLATE_CONSTANT);
855 }
856 }
857
858 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
859 {
860 struct si_context *sctx = (struct si_context *)ctx;
861 struct si_shader_selector *sel = state;
862
863 /* skip if supplied shader is one already in use */
864 if (sctx->ps_shader == sel)
865 return;
866
867 /* use a dummy shader if binding a NULL shader */
868 if (!sel) {
869 si_make_dummy_ps(sctx);
870 sel = sctx->dummy_pixel_shader;
871 }
872
873 sctx->ps_shader = sel;
874 si_update_fb_blend_state(sctx);
875 }
876
877 static void si_delete_shader_selector(struct pipe_context *ctx,
878 struct si_shader_selector *sel)
879 {
880 struct si_context *sctx = (struct si_context *)ctx;
881 struct si_shader *p = sel->current, *c;
882
883 while (p) {
884 c = p->next_variant;
885 switch (sel->type) {
886 case PIPE_SHADER_VERTEX:
887 if (p->key.vs.as_ls)
888 si_pm4_delete_state(sctx, ls, p->pm4);
889 else if (p->key.vs.as_es)
890 si_pm4_delete_state(sctx, es, p->pm4);
891 else
892 si_pm4_delete_state(sctx, vs, p->pm4);
893 break;
894 case PIPE_SHADER_TESS_CTRL:
895 si_pm4_delete_state(sctx, hs, p->pm4);
896 break;
897 case PIPE_SHADER_TESS_EVAL:
898 if (p->key.tes.as_es)
899 si_pm4_delete_state(sctx, es, p->pm4);
900 else
901 si_pm4_delete_state(sctx, vs, p->pm4);
902 break;
903 case PIPE_SHADER_GEOMETRY:
904 si_pm4_delete_state(sctx, gs, p->pm4);
905 si_pm4_delete_state(sctx, vs, p->gs_copy_shader->pm4);
906 break;
907 case PIPE_SHADER_FRAGMENT:
908 si_pm4_delete_state(sctx, ps, p->pm4);
909 break;
910 }
911
912 si_shader_destroy(ctx, p);
913 free(p);
914 p = c;
915 }
916
917 free(sel->tokens);
918 free(sel);
919 }
920
921 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
922 {
923 struct si_context *sctx = (struct si_context *)ctx;
924 struct si_shader_selector *sel = (struct si_shader_selector *)state;
925
926 if (sctx->vs_shader == sel) {
927 sctx->vs_shader = NULL;
928 }
929
930 si_delete_shader_selector(ctx, sel);
931 }
932
933 static void si_delete_gs_shader(struct pipe_context *ctx, void *state)
934 {
935 struct si_context *sctx = (struct si_context *)ctx;
936 struct si_shader_selector *sel = (struct si_shader_selector *)state;
937
938 if (sctx->gs_shader == sel) {
939 sctx->gs_shader = NULL;
940 }
941
942 si_delete_shader_selector(ctx, sel);
943 }
944
945 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
946 {
947 struct si_context *sctx = (struct si_context *)ctx;
948 struct si_shader_selector *sel = (struct si_shader_selector *)state;
949
950 if (sctx->ps_shader == sel) {
951 sctx->ps_shader = NULL;
952 }
953
954 si_delete_shader_selector(ctx, sel);
955 }
956
957 static void si_delete_tcs_shader(struct pipe_context *ctx, void *state)
958 {
959 struct si_context *sctx = (struct si_context *)ctx;
960 struct si_shader_selector *sel = (struct si_shader_selector *)state;
961
962 if (sctx->tcs_shader == sel) {
963 sctx->tcs_shader = NULL;
964 }
965
966 si_delete_shader_selector(ctx, sel);
967 }
968
969 static void si_delete_tes_shader(struct pipe_context *ctx, void *state)
970 {
971 struct si_context *sctx = (struct si_context *)ctx;
972 struct si_shader_selector *sel = (struct si_shader_selector *)state;
973
974 if (sctx->tes_shader == sel) {
975 sctx->tes_shader = NULL;
976 }
977
978 si_delete_shader_selector(ctx, sel);
979 }
980
981 static void si_update_spi_map(struct si_context *sctx)
982 {
983 struct si_shader *ps = sctx->ps_shader->current;
984 struct si_shader *vs = si_get_vs_state(sctx);
985 struct tgsi_shader_info *psinfo = &ps->selector->info;
986 struct tgsi_shader_info *vsinfo = &vs->selector->info;
987 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
988 unsigned i, j, tmp;
989
990 for (i = 0; i < psinfo->num_inputs; i++) {
991 unsigned name = psinfo->input_semantic_name[i];
992 unsigned index = psinfo->input_semantic_index[i];
993 unsigned interpolate = psinfo->input_interpolate[i];
994 unsigned param_offset = ps->ps_input_param_offset[i];
995
996 if (name == TGSI_SEMANTIC_POSITION ||
997 name == TGSI_SEMANTIC_FACE)
998 /* Read from preloaded VGPRs, not parameters */
999 continue;
1000
1001 bcolor:
1002 tmp = 0;
1003
1004 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
1005 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
1006 tmp |= S_028644_FLAT_SHADE(1);
1007
1008 if (name == TGSI_SEMANTIC_PCOORD ||
1009 (name == TGSI_SEMANTIC_TEXCOORD &&
1010 sctx->sprite_coord_enable & (1 << index))) {
1011 tmp |= S_028644_PT_SPRITE_TEX(1);
1012 }
1013
1014 for (j = 0; j < vsinfo->num_outputs; j++) {
1015 if (name == vsinfo->output_semantic_name[j] &&
1016 index == vsinfo->output_semantic_index[j]) {
1017 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[j]);
1018 break;
1019 }
1020 }
1021
1022 if (name == TGSI_SEMANTIC_PRIMID)
1023 /* PrimID is written after the last output. */
1024 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[vsinfo->num_outputs]);
1025 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(tmp)) {
1026 /* No corresponding output found, load defaults into input.
1027 * Don't set any other bits.
1028 * (FLAT_SHADE=1 completely changes behavior) */
1029 tmp = S_028644_OFFSET(0x20);
1030 }
1031
1032 si_pm4_set_reg(pm4,
1033 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
1034 tmp);
1035
1036 if (name == TGSI_SEMANTIC_COLOR &&
1037 ps->key.ps.color_two_side) {
1038 name = TGSI_SEMANTIC_BCOLOR;
1039 param_offset++;
1040 goto bcolor;
1041 }
1042 }
1043
1044 si_pm4_set_state(sctx, spi, pm4);
1045 }
1046
1047 /* Initialize state related to ESGS / GSVS ring buffers */
1048 static void si_init_gs_rings(struct si_context *sctx)
1049 {
1050 unsigned esgs_ring_size = 128 * 1024;
1051 unsigned gsvs_ring_size = 60 * 1024 * 1024;
1052
1053 assert(!sctx->esgs_ring && !sctx->gsvs_ring);
1054
1055 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1056 PIPE_USAGE_DEFAULT, esgs_ring_size);
1057
1058 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1059 PIPE_USAGE_DEFAULT, gsvs_ring_size);
1060
1061 /* Append these registers to the init config state. */
1062 if (sctx->b.chip_class >= CIK) {
1063 if (sctx->b.chip_class >= VI) {
1064 /* The maximum sizes are 63.999 MB on VI, because
1065 * the register fields only have 18 bits. */
1066 assert(esgs_ring_size / 256 < (1 << 18));
1067 assert(gsvs_ring_size / 256 < (1 << 18));
1068 }
1069 si_pm4_set_reg(sctx->init_config, R_030900_VGT_ESGS_RING_SIZE,
1070 esgs_ring_size / 256);
1071 si_pm4_set_reg(sctx->init_config, R_030904_VGT_GSVS_RING_SIZE,
1072 gsvs_ring_size / 256);
1073 } else {
1074 si_pm4_set_reg(sctx->init_config, R_0088C8_VGT_ESGS_RING_SIZE,
1075 esgs_ring_size / 256);
1076 si_pm4_set_reg(sctx->init_config, R_0088CC_VGT_GSVS_RING_SIZE,
1077 gsvs_ring_size / 256);
1078 }
1079
1080 /* Flush the context to re-emit the init_config state.
1081 * This is done only once in a lifetime of a context.
1082 */
1083 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1084 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1085
1086 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
1087 sctx->esgs_ring, 0, esgs_ring_size,
1088 true, true, 4, 64, 0);
1089 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
1090 sctx->esgs_ring, 0, esgs_ring_size,
1091 false, false, 0, 0, 0);
1092 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
1093 sctx->gsvs_ring, 0, gsvs_ring_size,
1094 false, false, 0, 0, 0);
1095 }
1096
1097 static void si_update_gs_rings(struct si_context *sctx)
1098 {
1099 unsigned gs_vert_itemsize = sctx->gs_shader->info.num_outputs * 16;
1100 unsigned gs_max_vert_out = sctx->gs_shader->gs_max_out_vertices;
1101 unsigned gsvs_itemsize = gs_vert_itemsize * gs_max_vert_out;
1102 uint64_t offset;
1103
1104 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
1105 sctx->gsvs_ring, gsvs_itemsize,
1106 64, true, true, 4, 16, 0);
1107
1108 offset = gsvs_itemsize * 64;
1109 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_1,
1110 sctx->gsvs_ring, gsvs_itemsize,
1111 64, true, true, 4, 16, offset);
1112
1113 offset = (gsvs_itemsize * 2) * 64;
1114 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_2,
1115 sctx->gsvs_ring, gsvs_itemsize,
1116 64, true, true, 4, 16, offset);
1117
1118 offset = (gsvs_itemsize * 3) * 64;
1119 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_3,
1120 sctx->gsvs_ring, gsvs_itemsize,
1121 64, true, true, 4, 16, offset);
1122 }
1123
1124 /**
1125 * @returns 1 if \p sel has been updated to use a new scratch buffer and 0
1126 * otherwise.
1127 */
1128 static unsigned si_update_scratch_buffer(struct si_context *sctx,
1129 struct si_shader_selector *sel)
1130 {
1131 struct si_shader *shader;
1132 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
1133
1134 if (!sel)
1135 return 0;
1136
1137 shader = sel->current;
1138
1139 /* This shader doesn't need a scratch buffer */
1140 if (shader->scratch_bytes_per_wave == 0)
1141 return 0;
1142
1143 /* This shader is already configured to use the current
1144 * scratch buffer. */
1145 if (shader->scratch_bo == sctx->scratch_buffer)
1146 return 0;
1147
1148 assert(sctx->scratch_buffer);
1149
1150 si_shader_apply_scratch_relocs(sctx, shader, scratch_va);
1151
1152 /* Replace the shader bo with a new bo that has the relocs applied. */
1153 si_shader_binary_upload(sctx->screen, shader);
1154
1155 /* Update the shader state to use the new shader bo. */
1156 si_shader_init_pm4_state(shader);
1157
1158 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
1159
1160 return 1;
1161 }
1162
1163 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
1164 {
1165 if (!sctx->scratch_buffer)
1166 return 0;
1167
1168 return sctx->scratch_buffer->b.b.width0;
1169 }
1170
1171 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_context *sctx,
1172 struct si_shader_selector *sel)
1173 {
1174 if (!sel)
1175 return 0;
1176
1177 return sel->current->scratch_bytes_per_wave;
1178 }
1179
1180 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
1181 {
1182 unsigned bytes = 0;
1183
1184 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx, sctx->ps_shader));
1185 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx, sctx->gs_shader));
1186 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx, sctx->vs_shader));
1187 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx, sctx->tcs_shader));
1188 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx, sctx->tes_shader));
1189 return bytes;
1190 }
1191
1192 static void si_update_spi_tmpring_size(struct si_context *sctx)
1193 {
1194 unsigned current_scratch_buffer_size =
1195 si_get_current_scratch_buffer_size(sctx);
1196 unsigned scratch_bytes_per_wave =
1197 si_get_max_scratch_bytes_per_wave(sctx);
1198 unsigned scratch_needed_size = scratch_bytes_per_wave *
1199 sctx->scratch_waves;
1200
1201 if (scratch_needed_size > 0) {
1202
1203 if (scratch_needed_size > current_scratch_buffer_size) {
1204 /* Create a bigger scratch buffer */
1205 pipe_resource_reference(
1206 (struct pipe_resource**)&sctx->scratch_buffer,
1207 NULL);
1208
1209 sctx->scratch_buffer =
1210 si_resource_create_custom(&sctx->screen->b.b,
1211 PIPE_USAGE_DEFAULT, scratch_needed_size);
1212 }
1213
1214 /* Update the shaders, so they are using the latest scratch. The
1215 * scratch buffer may have been changed since these shaders were
1216 * last used, so we still need to try to update them, even if
1217 * they require scratch buffers smaller than the current size.
1218 */
1219 if (si_update_scratch_buffer(sctx, sctx->ps_shader))
1220 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
1221 if (si_update_scratch_buffer(sctx, sctx->gs_shader))
1222 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
1223 if (si_update_scratch_buffer(sctx, sctx->tcs_shader))
1224 si_pm4_bind_state(sctx, hs, sctx->tcs_shader->current->pm4);
1225
1226 /* VS can be bound as LS, ES, or VS. */
1227 if (sctx->tes_shader) {
1228 if (si_update_scratch_buffer(sctx, sctx->vs_shader))
1229 si_pm4_bind_state(sctx, ls, sctx->vs_shader->current->pm4);
1230 } else if (sctx->gs_shader) {
1231 if (si_update_scratch_buffer(sctx, sctx->vs_shader))
1232 si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
1233 } else {
1234 if (si_update_scratch_buffer(sctx, sctx->vs_shader))
1235 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
1236 }
1237
1238 /* TES can be bound as ES or VS. */
1239 if (sctx->gs_shader) {
1240 if (si_update_scratch_buffer(sctx, sctx->tes_shader))
1241 si_pm4_bind_state(sctx, es, sctx->tes_shader->current->pm4);
1242 } else {
1243 if (si_update_scratch_buffer(sctx, sctx->tes_shader))
1244 si_pm4_bind_state(sctx, vs, sctx->tes_shader->current->pm4);
1245 }
1246 }
1247
1248 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
1249 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
1250 "scratch size should already be aligned correctly.");
1251
1252 sctx->spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
1253 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
1254 }
1255
1256 static void si_init_tess_factor_ring(struct si_context *sctx)
1257 {
1258 assert(!sctx->tf_state);
1259 sctx->tf_state = CALLOC_STRUCT(si_pm4_state);
1260
1261 sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1262 PIPE_USAGE_DEFAULT,
1263 32768 * sctx->screen->b.info.max_se);
1264 sctx->b.clear_buffer(&sctx->b.b, sctx->tf_ring, 0,
1265 sctx->tf_ring->width0, fui(0), false);
1266 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
1267
1268 if (sctx->b.chip_class >= CIK) {
1269 si_pm4_set_reg(sctx->tf_state, R_030938_VGT_TF_RING_SIZE,
1270 S_030938_SIZE(sctx->tf_ring->width0 / 4));
1271 si_pm4_set_reg(sctx->tf_state, R_030940_VGT_TF_MEMORY_BASE,
1272 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1273 } else {
1274 si_pm4_set_reg(sctx->tf_state, R_008988_VGT_TF_RING_SIZE,
1275 S_008988_SIZE(sctx->tf_ring->width0 / 4));
1276 si_pm4_set_reg(sctx->tf_state, R_0089B8_VGT_TF_MEMORY_BASE,
1277 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1278 }
1279 si_pm4_add_bo(sctx->tf_state, r600_resource(sctx->tf_ring),
1280 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RESOURCE_RW);
1281 si_pm4_bind_state(sctx, tf_ring, sctx->tf_state);
1282
1283 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_TESS_CTRL,
1284 SI_RING_TESS_FACTOR, sctx->tf_ring, 0,
1285 sctx->tf_ring->width0, false, false, 0, 0, 0);
1286
1287 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
1288 }
1289
1290 /**
1291 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
1292 * VS passes its outputs to TES directly, so the fixed-function shader only
1293 * has to write TESSOUTER and TESSINNER.
1294 */
1295 static void si_generate_fixed_func_tcs(struct si_context *sctx)
1296 {
1297 struct ureg_src const0, const1;
1298 struct ureg_dst tessouter, tessinner;
1299 struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
1300
1301 if (!ureg)
1302 return; /* if we get here, we're screwed */
1303
1304 assert(!sctx->fixed_func_tcs_shader);
1305
1306 ureg_DECL_constant2D(ureg, 0, 1, SI_DRIVER_STATE_CONST_BUF);
1307 const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 0),
1308 SI_DRIVER_STATE_CONST_BUF);
1309 const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 1),
1310 SI_DRIVER_STATE_CONST_BUF);
1311
1312 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1313 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1314
1315 ureg_MOV(ureg, tessouter, const0);
1316 ureg_MOV(ureg, tessinner, const1);
1317 ureg_END(ureg);
1318
1319 sctx->fixed_func_tcs_shader =
1320 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
1321 assert(sctx->fixed_func_tcs_shader);
1322 }
1323
1324 static void si_update_vgt_shader_config(struct si_context *sctx)
1325 {
1326 /* Calculate the index of the config.
1327 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
1328 unsigned index = 2*!!sctx->tes_shader + !!sctx->gs_shader;
1329 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
1330
1331 if (!*pm4) {
1332 uint32_t stages = 0;
1333
1334 *pm4 = CALLOC_STRUCT(si_pm4_state);
1335
1336 if (sctx->tes_shader) {
1337 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
1338 S_028B54_HS_EN(1);
1339
1340 if (sctx->gs_shader)
1341 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
1342 S_028B54_GS_EN(1) |
1343 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1344 else
1345 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
1346 } else if (sctx->gs_shader) {
1347 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1348 S_028B54_GS_EN(1) |
1349 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1350 }
1351
1352 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
1353 }
1354 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
1355 }
1356
1357 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
1358 {
1359 struct pipe_stream_output_info *so = &shader->so;
1360 uint32_t enabled_stream_buffers_mask = 0;
1361 int i;
1362
1363 for (i = 0; i < so->num_outputs; i++)
1364 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
1365 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
1366 sctx->b.streamout.stride_in_dw = shader->so.stride;
1367 }
1368
1369 void si_update_shaders(struct si_context *sctx)
1370 {
1371 struct pipe_context *ctx = (struct pipe_context*)sctx;
1372 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1373
1374 /* Update stages before GS. */
1375 if (sctx->tes_shader) {
1376 if (!sctx->tf_state)
1377 si_init_tess_factor_ring(sctx);
1378
1379 /* VS as LS */
1380 si_shader_select(ctx, sctx->vs_shader);
1381 si_pm4_bind_state(sctx, ls, sctx->vs_shader->current->pm4);
1382
1383 if (sctx->tcs_shader) {
1384 si_shader_select(ctx, sctx->tcs_shader);
1385 si_pm4_bind_state(sctx, hs, sctx->tcs_shader->current->pm4);
1386 } else {
1387 if (!sctx->fixed_func_tcs_shader)
1388 si_generate_fixed_func_tcs(sctx);
1389 si_shader_select(ctx, sctx->fixed_func_tcs_shader);
1390 si_pm4_bind_state(sctx, hs,
1391 sctx->fixed_func_tcs_shader->current->pm4);
1392 }
1393
1394 si_shader_select(ctx, sctx->tes_shader);
1395 if (sctx->gs_shader) {
1396 /* TES as ES */
1397 si_pm4_bind_state(sctx, es, sctx->tes_shader->current->pm4);
1398 } else {
1399 /* TES as VS */
1400 si_pm4_bind_state(sctx, vs, sctx->tes_shader->current->pm4);
1401 si_update_so(sctx, sctx->tes_shader);
1402 }
1403 } else if (sctx->gs_shader) {
1404 /* VS as ES */
1405 si_shader_select(ctx, sctx->vs_shader);
1406 si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
1407 } else {
1408 /* VS as VS */
1409 si_shader_select(ctx, sctx->vs_shader);
1410 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
1411 si_update_so(sctx, sctx->vs_shader);
1412 }
1413
1414 /* Update GS. */
1415 if (sctx->gs_shader) {
1416 si_shader_select(ctx, sctx->gs_shader);
1417 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
1418 si_pm4_bind_state(sctx, vs, sctx->gs_shader->current->gs_copy_shader->pm4);
1419 si_update_so(sctx, sctx->gs_shader);
1420
1421 if (!sctx->gsvs_ring)
1422 si_init_gs_rings(sctx);
1423
1424 si_update_gs_rings(sctx);
1425 } else {
1426 si_pm4_bind_state(sctx, gs, NULL);
1427 si_pm4_bind_state(sctx, es, NULL);
1428 }
1429
1430 si_update_vgt_shader_config(sctx);
1431
1432 si_shader_select(ctx, sctx->ps_shader);
1433
1434 if (!sctx->ps_shader->current) {
1435 struct si_shader_selector *sel;
1436
1437 /* use a dummy shader if compiling the shader (variant) failed */
1438 si_make_dummy_ps(sctx);
1439 sel = sctx->dummy_pixel_shader;
1440 si_shader_select(ctx, sel);
1441 sctx->ps_shader->current = sel->current;
1442 }
1443
1444 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
1445
1446 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
1447 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
1448 sctx->flatshade != rs->flatshade) {
1449 sctx->sprite_coord_enable = rs->sprite_coord_enable;
1450 sctx->flatshade = rs->flatshade;
1451 si_update_spi_map(sctx);
1452 }
1453
1454 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
1455 si_pm4_state_changed(sctx, gs)) {
1456 si_update_spi_tmpring_size(sctx);
1457 }
1458
1459 if (sctx->ps_db_shader_control != sctx->ps_shader->current->db_shader_control) {
1460 sctx->ps_db_shader_control = sctx->ps_shader->current->db_shader_control;
1461 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1462 }
1463
1464 if (sctx->smoothing_enabled != sctx->ps_shader->current->key.ps.poly_line_smoothing) {
1465 sctx->smoothing_enabled = sctx->ps_shader->current->key.ps.poly_line_smoothing;
1466 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1467
1468 if (sctx->b.chip_class == SI)
1469 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1470 }
1471 }
1472
1473 void si_init_shader_functions(struct si_context *sctx)
1474 {
1475 sctx->b.b.create_vs_state = si_create_vs_state;
1476 sctx->b.b.create_tcs_state = si_create_tcs_state;
1477 sctx->b.b.create_tes_state = si_create_tes_state;
1478 sctx->b.b.create_gs_state = si_create_gs_state;
1479 sctx->b.b.create_fs_state = si_create_fs_state;
1480
1481 sctx->b.b.bind_vs_state = si_bind_vs_shader;
1482 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
1483 sctx->b.b.bind_tes_state = si_bind_tes_shader;
1484 sctx->b.b.bind_gs_state = si_bind_gs_shader;
1485 sctx->b.b.bind_fs_state = si_bind_ps_shader;
1486
1487 sctx->b.b.delete_vs_state = si_delete_vs_shader;
1488 sctx->b.b.delete_tcs_state = si_delete_tcs_shader;
1489 sctx->b.b.delete_tes_state = si_delete_tes_shader;
1490 sctx->b.b.delete_gs_state = si_delete_gs_shader;
1491 sctx->b.b.delete_fs_state = si_delete_ps_shader;
1492 }