projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: rename si_compiler -> ac_llvm_compiler
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_ureg.h"
31 #include "util/hash_table.h"
32 #include "util/crc32.h"
33 #include "util/u_async_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
36
37 #include "util/disk_cache.h"
38 #include "util/mesa-sha1.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41
42 /* SHADER_CACHE */
43
44 /**
45 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
46 * size as integer.
47 */
48 void *si_get_ir_binary(struct si_shader_selector *sel)
49 {
50 struct blob blob;
51 unsigned ir_size;
52 void *ir_binary;
53
54 if (sel->tokens) {
55 ir_binary = sel->tokens;
56 ir_size = tgsi_num_tokens(sel->tokens) *
57 sizeof(struct tgsi_token);
58 } else {
59 assert(sel->nir);
60
61 blob_init(&blob);
62 nir_serialize(&blob, sel->nir);
63 ir_binary = blob.data;
64 ir_size = blob.size;
65 }
66
67 unsigned size = 4 + ir_size + sizeof(sel->so);
68 char *result = (char*)MALLOC(size);
69 if (!result)
70 return NULL;
71
72 *((uint32_t*)result) = size;
73 memcpy(result + 4, ir_binary, ir_size);
74 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
75
76 if (sel->nir)
77 blob_finish(&blob);
78
79 return result;
80 }
81
82 /** Copy "data" to "ptr" and return the next dword following copied data. */
83 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
84 {
85 /* data may be NULL if size == 0 */
86 if (size)
87 memcpy(ptr, data, size);
88 ptr += DIV_ROUND_UP(size, 4);
89 return ptr;
90 }
91
92 /** Read data from "ptr". Return the next dword following the data. */
93 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
94 {
95 memcpy(data, ptr, size);
96 ptr += DIV_ROUND_UP(size, 4);
97 return ptr;
98 }
99
100 /**
101 * Write the size as uint followed by the data. Return the next dword
102 * following the copied data.
103 */
104 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
105 {
106 *ptr++ = size;
107 return write_data(ptr, data, size);
108 }
109
110 /**
111 * Read the size as uint followed by the data. Return both via parameters.
112 * Return the next dword following the data.
113 */
114 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
115 {
116 *size = *ptr++;
117 assert(*data == NULL);
118 if (!*size)
119 return ptr;
120 *data = malloc(*size);
121 return read_data(ptr, *data, *size);
122 }
123
124 /**
125 * Return the shader binary in a buffer. The first 4 bytes contain its size
126 * as integer.
127 */
128 static void *si_get_shader_binary(struct si_shader *shader)
129 {
130 /* There is always a size of data followed by the data itself. */
131 unsigned relocs_size = shader->binary.reloc_count *
132 sizeof(shader->binary.relocs[0]);
133 unsigned disasm_size = shader->binary.disasm_string ?
134 strlen(shader->binary.disasm_string) + 1 : 0;
135 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
136 strlen(shader->binary.llvm_ir_string) + 1 : 0;
137 unsigned size =
138 4 + /* total size */
139 4 + /* CRC32 of the data below */
140 align(sizeof(shader->config), 4) +
141 align(sizeof(shader->info), 4) +
142 4 + align(shader->binary.code_size, 4) +
143 4 + align(shader->binary.rodata_size, 4) +
144 4 + align(relocs_size, 4) +
145 4 + align(disasm_size, 4) +
146 4 + align(llvm_ir_size, 4);
147 void *buffer = CALLOC(1, size);
148 uint32_t *ptr = (uint32_t*)buffer;
149
150 if (!buffer)
151 return NULL;
152
153 *ptr++ = size;
154 ptr++; /* CRC32 is calculated at the end. */
155
156 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
157 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
158 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
159 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
160 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
161 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
162 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
163 assert((char *)ptr - (char *)buffer == size);
164
165 /* Compute CRC32. */
166 ptr = (uint32_t*)buffer;
167 ptr++;
168 *ptr = util_hash_crc32(ptr + 1, size - 8);
169
170 return buffer;
171 }
172
173 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
174 {
175 uint32_t *ptr = (uint32_t*)binary;
176 uint32_t size = *ptr++;
177 uint32_t crc32 = *ptr++;
178 unsigned chunk_size;
179
180 if (util_hash_crc32(ptr, size - 8) != crc32) {
181 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
182 return false;
183 }
184
185 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
186 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
187 ptr = read_chunk(ptr, (void**)&shader->binary.code,
188 &shader->binary.code_size);
189 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
190 &shader->binary.rodata_size);
191 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
192 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
193 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
194 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
195
196 return true;
197 }
198
199 /**
200 * Insert a shader into the cache. It's assumed the shader is not in the cache.
201 * Use si_shader_cache_load_shader before calling this.
202 *
203 * Returns false on failure, in which case the ir_binary should be freed.
204 */
205 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
206 struct si_shader *shader,
207 bool insert_into_disk_cache)
208 {
209 void *hw_binary;
210 struct hash_entry *entry;
211 uint8_t key[CACHE_KEY_SIZE];
212
213 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
214 if (entry)
215 return false; /* already added */
216
217 hw_binary = si_get_shader_binary(shader);
218 if (!hw_binary)
219 return false;
220
221 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
222 hw_binary) == NULL) {
223 FREE(hw_binary);
224 return false;
225 }
226
227 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
228 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
229 *((uint32_t *)ir_binary), key);
230 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
231 *((uint32_t *) hw_binary), NULL);
232 }
233
234 return true;
235 }
236
237 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
238 struct si_shader *shader)
239 {
240 struct hash_entry *entry =
241 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
242 if (!entry) {
243 if (sscreen->disk_shader_cache) {
244 unsigned char sha1[CACHE_KEY_SIZE];
245 size_t tg_size = *((uint32_t *) ir_binary);
246
247 disk_cache_compute_key(sscreen->disk_shader_cache,
248 ir_binary, tg_size, sha1);
249
250 size_t binary_size;
251 uint8_t *buffer =
252 disk_cache_get(sscreen->disk_shader_cache,
253 sha1, &binary_size);
254 if (!buffer)
255 return false;
256
257 if (binary_size < sizeof(uint32_t) ||
258 *((uint32_t*)buffer) != binary_size) {
259 /* Something has gone wrong discard the item
260 * from the cache and rebuild/link from
261 * source.
262 */
263 assert(!"Invalid radeonsi shader disk cache "
264 "item!");
265
266 disk_cache_remove(sscreen->disk_shader_cache,
267 sha1);
268 free(buffer);
269
270 return false;
271 }
272
273 if (!si_load_shader_binary(shader, buffer)) {
274 free(buffer);
275 return false;
276 }
277 free(buffer);
278
279 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
280 shader, false))
281 FREE(ir_binary);
282 } else {
283 return false;
284 }
285 } else {
286 if (si_load_shader_binary(shader, entry->data))
287 FREE(ir_binary);
288 else
289 return false;
290 }
291 p_atomic_inc(&sscreen->num_shader_cache_hits);
292 return true;
293 }
294
295 static uint32_t si_shader_cache_key_hash(const void *key)
296 {
297 /* The first dword is the key size. */
298 return util_hash_crc32(key, *(uint32_t*)key);
299 }
300
301 static bool si_shader_cache_key_equals(const void *a, const void *b)
302 {
303 uint32_t *keya = (uint32_t*)a;
304 uint32_t *keyb = (uint32_t*)b;
305
306 /* The first dword is the key size. */
307 if (*keya != *keyb)
308 return false;
309
310 return memcmp(keya, keyb, *keya) == 0;
311 }
312
313 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
314 {
315 FREE((void*)entry->key);
316 FREE(entry->data);
317 }
318
319 bool si_init_shader_cache(struct si_screen *sscreen)
320 {
321 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
322 sscreen->shader_cache =
323 _mesa_hash_table_create(NULL,
324 si_shader_cache_key_hash,
325 si_shader_cache_key_equals);
326
327 return sscreen->shader_cache != NULL;
328 }
329
330 void si_destroy_shader_cache(struct si_screen *sscreen)
331 {
332 if (sscreen->shader_cache)
333 _mesa_hash_table_destroy(sscreen->shader_cache,
334 si_destroy_shader_cache_entry);
335 mtx_destroy(&sscreen->shader_cache_mutex);
336 }
337
338 /* SHADER STATES */
339
340 static void si_set_tesseval_regs(struct si_screen *sscreen,
341 struct si_shader_selector *tes,
342 struct si_pm4_state *pm4)
343 {
344 struct tgsi_shader_info *info = &tes->info;
345 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
346 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
347 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
348 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
349 unsigned type, partitioning, topology, distribution_mode;
350
351 switch (tes_prim_mode) {
352 case PIPE_PRIM_LINES:
353 type = V_028B6C_TESS_ISOLINE;
354 break;
355 case PIPE_PRIM_TRIANGLES:
356 type = V_028B6C_TESS_TRIANGLE;
357 break;
358 case PIPE_PRIM_QUADS:
359 type = V_028B6C_TESS_QUAD;
360 break;
361 default:
362 assert(0);
363 return;
364 }
365
366 switch (tes_spacing) {
367 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
368 partitioning = V_028B6C_PART_FRAC_ODD;
369 break;
370 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
371 partitioning = V_028B6C_PART_FRAC_EVEN;
372 break;
373 case PIPE_TESS_SPACING_EQUAL:
374 partitioning = V_028B6C_PART_INTEGER;
375 break;
376 default:
377 assert(0);
378 return;
379 }
380
381 if (tes_point_mode)
382 topology = V_028B6C_OUTPUT_POINT;
383 else if (tes_prim_mode == PIPE_PRIM_LINES)
384 topology = V_028B6C_OUTPUT_LINE;
385 else if (tes_vertex_order_cw)
386 /* for some reason, this must be the other way around */
387 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
388 else
389 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
390
391 if (sscreen->has_distributed_tess) {
392 if (sscreen->info.family == CHIP_FIJI ||
393 sscreen->info.family >= CHIP_POLARIS10)
394 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
395 else
396 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
397 } else
398 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
399
400 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
401 S_028B6C_TYPE(type) |
402 S_028B6C_PARTITIONING(partitioning) |
403 S_028B6C_TOPOLOGY(topology) |
404 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
405 }
406
407 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
408 * whether the "fractional odd" tessellation spacing is used.
409 *
410 * Possible VGT configurations and which state should set the register:
411 *
412 * Reg set in | VGT shader configuration | Value
413 * ------------------------------------------------------
414 * VS as VS | VS | 30
415 * VS as ES | ES -> GS -> VS | 30
416 * TES as VS | LS -> HS -> VS | 14 or 30
417 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
418 *
419 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
420 */
421 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
422 struct si_shader_selector *sel,
423 struct si_shader *shader,
424 struct si_pm4_state *pm4)
425 {
426 unsigned type = sel->type;
427
428 if (sscreen->info.family < CHIP_POLARIS10)
429 return;
430
431 /* VS as VS, or VS as ES: */
432 if ((type == PIPE_SHADER_VERTEX &&
433 (!shader ||
434 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
435 /* TES as VS, or TES as ES: */
436 type == PIPE_SHADER_TESS_EVAL) {
437 unsigned vtx_reuse_depth = 30;
438
439 if (type == PIPE_SHADER_TESS_EVAL &&
440 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
441 PIPE_TESS_SPACING_FRACTIONAL_ODD)
442 vtx_reuse_depth = 14;
443
444 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
445 vtx_reuse_depth);
446 }
447 }
448
449 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
450 {
451 if (shader->pm4)
452 si_pm4_clear_state(shader->pm4);
453 else
454 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
455
456 return shader->pm4;
457 }
458
459 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
460 {
461 /* Add the pointer to VBO descriptors. */
462 if (HAVE_32BIT_POINTERS) {
463 return num_always_on_user_sgprs + 1;
464 } else {
465 assert(num_always_on_user_sgprs % 2 == 0);
466 return num_always_on_user_sgprs + 2;
467 }
468 }
469
470 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
471 {
472 struct si_pm4_state *pm4;
473 unsigned vgpr_comp_cnt;
474 uint64_t va;
475
476 assert(sscreen->info.chip_class <= VI);
477
478 pm4 = si_get_shader_pm4_state(shader);
479 if (!pm4)
480 return;
481
482 va = shader->bo->gpu_address;
483 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
484
485 /* We need at least 2 components for LS.
486 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
487 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
488 */
489 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
490
491 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
492 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
493
494 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
495 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
496 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
497 S_00B528_DX10_CLAMP(1) |
498 S_00B528_FLOAT_MODE(shader->config.float_mode);
499 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
500 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
501 }
502
503 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
504 {
505 struct si_pm4_state *pm4;
506 uint64_t va;
507 unsigned ls_vgpr_comp_cnt = 0;
508
509 pm4 = si_get_shader_pm4_state(shader);
510 if (!pm4)
511 return;
512
513 va = shader->bo->gpu_address;
514 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
515
516 if (sscreen->info.chip_class >= GFX9) {
517 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
518 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
519
520 /* We need at least 2 components for LS.
521 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
522 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
523 */
524 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
525
526 unsigned num_user_sgprs =
527 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
528
529 shader->config.rsrc2 =
530 S_00B42C_USER_SGPR(num_user_sgprs) |
531 S_00B42C_USER_SGPR_MSB(num_user_sgprs >> 5) |
532 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
533 } else {
534 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
535 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
536
537 shader->config.rsrc2 =
538 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
539 S_00B42C_OC_LDS_EN(1) |
540 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
541 }
542
543 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
544 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
545 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
546 S_00B428_DX10_CLAMP(1) |
547 S_00B428_FLOAT_MODE(shader->config.float_mode) |
548 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
549
550 if (sscreen->info.chip_class <= VI) {
551 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
552 shader->config.rsrc2);
553 }
554 }
555
556 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
557 {
558 struct si_pm4_state *pm4;
559 unsigned num_user_sgprs;
560 unsigned vgpr_comp_cnt;
561 uint64_t va;
562 unsigned oc_lds_en;
563
564 assert(sscreen->info.chip_class <= VI);
565
566 pm4 = si_get_shader_pm4_state(shader);
567 if (!pm4)
568 return;
569
570 va = shader->bo->gpu_address;
571 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
572
573 if (shader->selector->type == PIPE_SHADER_VERTEX) {
574 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
575 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
576 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
577 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
578 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
579 num_user_sgprs = SI_TES_NUM_USER_SGPR;
580 } else
581 unreachable("invalid shader selector type");
582
583 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
584
585 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
586 shader->selector->esgs_itemsize / 4);
587 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
588 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
589 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
590 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
591 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
592 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
593 S_00B328_DX10_CLAMP(1) |
594 S_00B328_FLOAT_MODE(shader->config.float_mode));
595 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
596 S_00B32C_USER_SGPR(num_user_sgprs) |
597 S_00B32C_OC_LDS_EN(oc_lds_en) |
598 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
599
600 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
601 si_set_tesseval_regs(sscreen, shader->selector, pm4);
602
603 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
604 }
605
606 static unsigned si_conv_prim_to_gs_out(unsigned mode)
607 {
608 static const int prim_conv[] = {
609 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
610 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
611 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
612 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
613 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
614 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
615 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
616 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
617 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
618 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
619 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
620 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
621 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
622 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
623 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
624 };
625 assert(mode < ARRAY_SIZE(prim_conv));
626
627 return prim_conv[mode];
628 }
629
630 struct gfx9_gs_info {
631 unsigned es_verts_per_subgroup;
632 unsigned gs_prims_per_subgroup;
633 unsigned gs_inst_prims_in_subgroup;
634 unsigned max_prims_per_subgroup;
635 unsigned lds_size;
636 };
637
638 static void gfx9_get_gs_info(struct si_shader_selector *es,
639 struct si_shader_selector *gs,
640 struct gfx9_gs_info *out)
641 {
642 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
643 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
644 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
645 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
646
647 /* All these are in dwords: */
648 /* We can't allow using the whole LDS, because GS waves compete with
649 * other shader stages for LDS space. */
650 const unsigned max_lds_size = 8 * 1024;
651 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
652 unsigned esgs_lds_size;
653
654 /* All these are per subgroup: */
655 const unsigned max_out_prims = 32 * 1024;
656 const unsigned max_es_verts = 255;
657 const unsigned ideal_gs_prims = 64;
658 unsigned max_gs_prims, gs_prims;
659 unsigned min_es_verts, es_verts, worst_case_es_verts;
660
661 assert(gs_num_invocations <= 32); /* GL maximum */
662
663 if (uses_adjacency || gs_num_invocations > 1)
664 max_gs_prims = 127 / gs_num_invocations;
665 else
666 max_gs_prims = 255;
667
668 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
669 * Make sure we don't go over the maximum value.
670 */
671 if (gs->gs_max_out_vertices > 0) {
672 max_gs_prims = MIN2(max_gs_prims,
673 max_out_prims /
674 (gs->gs_max_out_vertices * gs_num_invocations));
675 }
676 assert(max_gs_prims > 0);
677
678 /* If the primitive has adjacency, halve the number of vertices
679 * that will be reused in multiple primitives.
680 */
681 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
682
683 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
684 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
685
686 /* Compute ESGS LDS size based on the worst case number of ES vertices
687 * needed to create the target number of GS prims per subgroup.
688 */
689 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
690
691 /* If total LDS usage is too big, refactor partitions based on ratio
692 * of ESGS item sizes.
693 */
694 if (esgs_lds_size > max_lds_size) {
695 /* Our target GS Prims Per Subgroup was too large. Calculate
696 * the maximum number of GS Prims Per Subgroup that will fit
697 * into LDS, capped by the maximum that the hardware can support.
698 */
699 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
700 max_gs_prims);
701 assert(gs_prims > 0);
702 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
703 max_es_verts);
704
705 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
706 assert(esgs_lds_size <= max_lds_size);
707 }
708
709 /* Now calculate remaining ESGS information. */
710 if (esgs_lds_size)
711 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
712 else
713 es_verts = max_es_verts;
714
715 /* Vertices for adjacency primitives are not always reused, so restore
716 * it for ES_VERTS_PER_SUBGRP.
717 */
718 min_es_verts = gs->gs_input_verts_per_prim;
719
720 /* For normal primitives, the VGT only checks if they are past the ES
721 * verts per subgroup after allocating a full GS primitive and if they
722 * are, kick off a new subgroup. But if those additional ES verts are
723 * unique (e.g. not reused) we need to make sure there is enough LDS
724 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
725 */
726 es_verts -= min_es_verts - 1;
727
728 out->es_verts_per_subgroup = es_verts;
729 out->gs_prims_per_subgroup = gs_prims;
730 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
731 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
732 gs->gs_max_out_vertices;
733 out->lds_size = align(esgs_lds_size, 128) / 128;
734
735 assert(out->max_prims_per_subgroup <= max_out_prims);
736 }
737
738 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
739 {
740 struct si_shader_selector *sel = shader->selector;
741 const ubyte *num_components = sel->info.num_stream_output_components;
742 unsigned gs_num_invocations = sel->gs_num_invocations;
743 struct si_pm4_state *pm4;
744 uint64_t va;
745 unsigned max_stream = sel->max_gs_stream;
746 unsigned offset;
747
748 pm4 = si_get_shader_pm4_state(shader);
749 if (!pm4)
750 return;
751
752 offset = num_components[0] * sel->gs_max_out_vertices;
753 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, offset);
754 if (max_stream >= 1)
755 offset += num_components[1] * sel->gs_max_out_vertices;
756 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, offset);
757 if (max_stream >= 2)
758 offset += num_components[2] * sel->gs_max_out_vertices;
759 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, offset);
760 si_pm4_set_reg(pm4, R_028A6C_VGT_GS_OUT_PRIM_TYPE,
761 si_conv_prim_to_gs_out(sel->gs_output_prim));
762 if (max_stream >= 3)
763 offset += num_components[3] * sel->gs_max_out_vertices;
764 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
765
766 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
767 assert(offset < (1 << 15));
768
769 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, sel->gs_max_out_vertices);
770
771 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, num_components[0]);
772 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? num_components[1] : 0);
773 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? num_components[2] : 0);
774 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? num_components[3] : 0);
775
776 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
777 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
778 S_028B90_ENABLE(gs_num_invocations > 0));
779
780 va = shader->bo->gpu_address;
781 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
782
783 if (sscreen->info.chip_class >= GFX9) {
784 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
785 unsigned es_type = shader->key.part.gs.es->type;
786 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
787 struct gfx9_gs_info gs_info;
788
789 if (es_type == PIPE_SHADER_VERTEX)
790 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
791 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
792 else if (es_type == PIPE_SHADER_TESS_EVAL)
793 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
794 else
795 unreachable("invalid shader selector type");
796
797 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
798 * VGPR[0:4] are always loaded.
799 */
800 if (sel->info.uses_invocationid)
801 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
802 else if (sel->info.uses_primid)
803 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
804 else if (input_prim >= PIPE_PRIM_TRIANGLES)
805 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
806 else
807 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
808
809 unsigned num_user_sgprs;
810 if (es_type == PIPE_SHADER_VERTEX)
811 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
812 else
813 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
814
815 gfx9_get_gs_info(shader->key.part.gs.es, sel, &gs_info);
816
817 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
818 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
819
820 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
821 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
822 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
823 S_00B228_DX10_CLAMP(1) |
824 S_00B228_FLOAT_MODE(shader->config.float_mode) |
825 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
826 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
827 S_00B22C_USER_SGPR(num_user_sgprs) |
828 S_00B22C_USER_SGPR_MSB(num_user_sgprs >> 5) |
829 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
830 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
831 S_00B22C_LDS_SIZE(gs_info.lds_size) |
832 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
833
834 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
835 S_028A44_ES_VERTS_PER_SUBGRP(gs_info.es_verts_per_subgroup) |
836 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info.gs_prims_per_subgroup) |
837 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info.gs_inst_prims_in_subgroup));
838 si_pm4_set_reg(pm4, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
839 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info.max_prims_per_subgroup));
840 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
841 shader->key.part.gs.es->esgs_itemsize / 4);
842
843 if (es_type == PIPE_SHADER_TESS_EVAL)
844 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
845
846 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
847 NULL, pm4);
848 } else {
849 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
850 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
851
852 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
853 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
854 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
855 S_00B228_DX10_CLAMP(1) |
856 S_00B228_FLOAT_MODE(shader->config.float_mode));
857 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
858 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
859 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
860 }
861 }
862
863 /**
864 * Compute the state for \p shader, which will run as a vertex shader on the
865 * hardware.
866 *
867 * If \p gs is non-NULL, it points to the geometry shader for which this shader
868 * is the copy shader.
869 */
870 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
871 struct si_shader_selector *gs)
872 {
873 const struct tgsi_shader_info *info = &shader->selector->info;
874 struct si_pm4_state *pm4;
875 unsigned num_user_sgprs;
876 unsigned nparams, vgpr_comp_cnt;
877 uint64_t va;
878 unsigned oc_lds_en;
879 unsigned window_space =
880 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
881 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
882
883 pm4 = si_get_shader_pm4_state(shader);
884 if (!pm4)
885 return;
886
887 /* We always write VGT_GS_MODE in the VS state, because every switch
888 * between different shader pipelines involving a different GS or no
889 * GS at all involves a switch of the VS (different GS use different
890 * copy shaders). On the other hand, when the API switches from a GS to
891 * no GS and then back to the same GS used originally, the GS state is
892 * not sent again.
893 */
894 if (!gs) {
895 unsigned mode = V_028A40_GS_OFF;
896
897 /* PrimID needs GS scenario A. */
898 if (enable_prim_id)
899 mode = V_028A40_GS_SCENARIO_A;
900
901 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, S_028A40_MODE(mode));
902 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
903 } else {
904 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
905 ac_vgt_gs_mode(gs->gs_max_out_vertices,
906 sscreen->info.chip_class));
907 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
908 }
909
910 if (sscreen->info.chip_class <= VI) {
911 /* Reuse needs to be set off if we write oViewport. */
912 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF,
913 S_028AB4_REUSE_OFF(info->writes_viewport_index));
914 }
915
916 va = shader->bo->gpu_address;
917 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
918
919 if (gs) {
920 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
921 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
922 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
923 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
924 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
925 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
926 */
927 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
928
929 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
930 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
931 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
932 } else {
933 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
934 }
935 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
936 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
937 num_user_sgprs = SI_TES_NUM_USER_SGPR;
938 } else
939 unreachable("invalid shader selector type");
940
941 /* VS is required to export at least one param. */
942 nparams = MAX2(shader->info.nr_param_exports, 1);
943 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
944 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
945
946 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
947 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
948 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
949 V_02870C_SPI_SHADER_4COMP :
950 V_02870C_SPI_SHADER_NONE) |
951 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
952 V_02870C_SPI_SHADER_4COMP :
953 V_02870C_SPI_SHADER_NONE) |
954 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
955 V_02870C_SPI_SHADER_4COMP :
956 V_02870C_SPI_SHADER_NONE));
957
958 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
959
960 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
961 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
962 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
963 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
964 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
965 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
966 S_00B128_DX10_CLAMP(1) |
967 S_00B128_FLOAT_MODE(shader->config.float_mode));
968 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
969 S_00B12C_USER_SGPR(num_user_sgprs) |
970 S_00B12C_OC_LDS_EN(oc_lds_en) |
971 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
972 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
973 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
974 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
975 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
976 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
977 if (window_space)
978 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
979 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
980 else
981 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
982 S_028818_VTX_W0_FMT(1) |
983 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
984 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
985 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
986
987 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
988 si_set_tesseval_regs(sscreen, shader->selector, pm4);
989
990 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
991 }
992
993 static unsigned si_get_ps_num_interp(struct si_shader *ps)
994 {
995 struct tgsi_shader_info *info = &ps->selector->info;
996 unsigned num_colors = !!(info->colors_read & 0x0f) +
997 !!(info->colors_read & 0xf0);
998 unsigned num_interp = ps->selector->info.num_inputs +
999 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1000
1001 assert(num_interp <= 32);
1002 return MIN2(num_interp, 32);
1003 }
1004
1005 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1006 {
1007 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1008 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1009
1010 /* If the i-th target format is set, all previous target formats must
1011 * be non-zero to avoid hangs.
1012 */
1013 for (i = 0; i < num_targets; i++)
1014 if (!(value & (0xf << (i * 4))))
1015 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1016
1017 return value;
1018 }
1019
1020 static void si_shader_ps(struct si_shader *shader)
1021 {
1022 struct tgsi_shader_info *info = &shader->selector->info;
1023 struct si_pm4_state *pm4;
1024 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1025 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1026 uint64_t va;
1027 unsigned input_ena = shader->config.spi_ps_input_ena;
1028
1029 /* we need to enable at least one of them, otherwise we hang the GPU */
1030 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1031 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1032 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1033 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1034 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1035 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1036 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1037 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1038 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1039 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1040 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1041 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1042 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1043 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1044
1045 /* Validate interpolation optimization flags (read as implications). */
1046 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1047 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1048 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1049 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1050 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1051 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1052 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1053 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1054 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1055 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1056 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1057 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1058 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1059 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1060 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1061 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1062 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1063 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1064
1065 /* Validate cases when the optimizations are off (read as implications). */
1066 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1067 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1068 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1069 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1070 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1071 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1072
1073 pm4 = si_get_shader_pm4_state(shader);
1074 if (!pm4)
1075 return;
1076
1077 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1078 * Possible vaules:
1079 * 0 -> Position = pixel center
1080 * 1 -> Position = pixel centroid
1081 * 2 -> Position = at sample position
1082 *
1083 * From GLSL 4.5 specification, section 7.1:
1084 * "The variable gl_FragCoord is available as an input variable from
1085 * within fragment shaders and it holds the window relative coordinates
1086 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1087 * value can be for any location within the pixel, or one of the
1088 * fragment samples. The use of centroid does not further restrict
1089 * this value to be inside the current primitive."
1090 *
1091 * Meaning that centroid has no effect and we can return anything within
1092 * the pixel. Thus, return the value at sample position, because that's
1093 * the most accurate one shaders can get.
1094 */
1095 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1096
1097 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1098 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1099 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1100
1101 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1102 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1103
1104 /* Ensure that some export memory is always allocated, for two reasons:
1105 *
1106 * 1) Correctness: The hardware ignores the EXEC mask if no export
1107 * memory is allocated, so KILL and alpha test do not work correctly
1108 * without this.
1109 * 2) Performance: Every shader needs at least a NULL export, even when
1110 * it writes no color/depth output. The NULL export instruction
1111 * stalls without this setting.
1112 *
1113 * Don't add this to CB_SHADER_MASK.
1114 */
1115 if (!spi_shader_col_format &&
1116 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1117 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1118
1119 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
1120 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
1121 shader->config.spi_ps_input_addr);
1122
1123 /* Set interpolation controls. */
1124 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1125
1126 /* Set registers. */
1127 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1128 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
1129
1130 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
1131 ac_get_spi_shader_z_format(info->writes_z,
1132 info->writes_stencil,
1133 info->writes_samplemask));
1134
1135 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
1136 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
1137
1138 va = shader->bo->gpu_address;
1139 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1140 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1141 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1142
1143 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
1144 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1145 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
1146 S_00B028_DX10_CLAMP(1) |
1147 S_00B028_FLOAT_MODE(shader->config.float_mode));
1148 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1149 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1150 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1151 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1152 }
1153
1154 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1155 struct si_shader *shader)
1156 {
1157 switch (shader->selector->type) {
1158 case PIPE_SHADER_VERTEX:
1159 if (shader->key.as_ls)
1160 si_shader_ls(sscreen, shader);
1161 else if (shader->key.as_es)
1162 si_shader_es(sscreen, shader);
1163 else
1164 si_shader_vs(sscreen, shader, NULL);
1165 break;
1166 case PIPE_SHADER_TESS_CTRL:
1167 si_shader_hs(sscreen, shader);
1168 break;
1169 case PIPE_SHADER_TESS_EVAL:
1170 if (shader->key.as_es)
1171 si_shader_es(sscreen, shader);
1172 else
1173 si_shader_vs(sscreen, shader, NULL);
1174 break;
1175 case PIPE_SHADER_GEOMETRY:
1176 si_shader_gs(sscreen, shader);
1177 break;
1178 case PIPE_SHADER_FRAGMENT:
1179 si_shader_ps(shader);
1180 break;
1181 default:
1182 assert(0);
1183 }
1184 }
1185
1186 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1187 {
1188 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1189 if (sctx->queued.named.dsa)
1190 return sctx->queued.named.dsa->alpha_func;
1191
1192 return PIPE_FUNC_ALWAYS;
1193 }
1194
1195 static void si_shader_selector_key_vs(struct si_context *sctx,
1196 struct si_shader_selector *vs,
1197 struct si_shader_key *key,
1198 struct si_vs_prolog_bits *prolog_key)
1199 {
1200 if (!sctx->vertex_elements)
1201 return;
1202
1203 prolog_key->instance_divisor_is_one =
1204 sctx->vertex_elements->instance_divisor_is_one;
1205 prolog_key->instance_divisor_is_fetched =
1206 sctx->vertex_elements->instance_divisor_is_fetched;
1207
1208 /* Prefer a monolithic shader to allow scheduling divisions around
1209 * VBO loads. */
1210 if (prolog_key->instance_divisor_is_fetched)
1211 key->opt.prefer_mono = 1;
1212
1213 unsigned count = MIN2(vs->info.num_inputs,
1214 sctx->vertex_elements->count);
1215 memcpy(key->mono.vs_fix_fetch, sctx->vertex_elements->fix_fetch, count);
1216 }
1217
1218 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1219 struct si_shader_selector *vs,
1220 struct si_shader_key *key)
1221 {
1222 struct si_shader_selector *ps = sctx->ps_shader.cso;
1223
1224 key->opt.clip_disable =
1225 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1226 (vs->info.clipdist_writemask ||
1227 vs->info.writes_clipvertex) &&
1228 !vs->info.culldist_writemask;
1229
1230 /* Find out if PS is disabled. */
1231 bool ps_disabled = true;
1232 if (ps) {
1233 const struct si_state_blend *blend = sctx->queued.named.blend;
1234 bool alpha_to_coverage = blend && blend->alpha_to_coverage;
1235 bool ps_modifies_zs = ps->info.uses_kill ||
1236 ps->info.writes_z ||
1237 ps->info.writes_stencil ||
1238 ps->info.writes_samplemask ||
1239 alpha_to_coverage ||
1240 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1241 unsigned ps_colormask = si_get_total_colormask(sctx);
1242
1243 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1244 (!ps_colormask &&
1245 !ps_modifies_zs &&
1246 !ps->info.writes_memory);
1247 }
1248
1249 /* Find out which VS outputs aren't used by the PS. */
1250 uint64_t outputs_written = vs->outputs_written_before_ps;
1251 uint64_t inputs_read = 0;
1252
1253 /* Ignore outputs that are not passed from VS to PS. */
1254 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1255 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1256 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1257
1258 if (!ps_disabled) {
1259 inputs_read = ps->inputs_read;
1260 }
1261
1262 uint64_t linked = outputs_written & inputs_read;
1263
1264 key->opt.kill_outputs = ~linked & outputs_written;
1265 }
1266
1267 /* Compute the key for the hw shader variant */
1268 static inline void si_shader_selector_key(struct pipe_context *ctx,
1269 struct si_shader_selector *sel,
1270 struct si_shader_key *key)
1271 {
1272 struct si_context *sctx = (struct si_context *)ctx;
1273
1274 memset(key, 0, sizeof(*key));
1275
1276 switch (sel->type) {
1277 case PIPE_SHADER_VERTEX:
1278 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1279
1280 if (sctx->tes_shader.cso)
1281 key->as_ls = 1;
1282 else if (sctx->gs_shader.cso)
1283 key->as_es = 1;
1284 else {
1285 si_shader_selector_key_hw_vs(sctx, sel, key);
1286
1287 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1288 key->mono.u.vs_export_prim_id = 1;
1289 }
1290 break;
1291 case PIPE_SHADER_TESS_CTRL:
1292 if (sctx->chip_class >= GFX9) {
1293 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1294 key, &key->part.tcs.ls_prolog);
1295 key->part.tcs.ls = sctx->vs_shader.cso;
1296
1297 /* When the LS VGPR fix is needed, monolithic shaders
1298 * can:
1299 * - avoid initializing EXEC in both the LS prolog
1300 * and the LS main part when !vs_needs_prolog
1301 * - remove the fixup for unused input VGPRs
1302 */
1303 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1304
1305 /* The LS output / HS input layout can be communicated
1306 * directly instead of via user SGPRs for merged LS-HS.
1307 * The LS VGPR fix prefers this too.
1308 */
1309 key->opt.prefer_mono = 1;
1310 }
1311
1312 key->part.tcs.epilog.prim_mode =
1313 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1314 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1315 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1316 key->part.tcs.epilog.tes_reads_tess_factors =
1317 sctx->tes_shader.cso->info.reads_tess_factors;
1318
1319 if (sel == sctx->fixed_func_tcs_shader.cso)
1320 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1321 break;
1322 case PIPE_SHADER_TESS_EVAL:
1323 if (sctx->gs_shader.cso)
1324 key->as_es = 1;
1325 else {
1326 si_shader_selector_key_hw_vs(sctx, sel, key);
1327
1328 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1329 key->mono.u.vs_export_prim_id = 1;
1330 }
1331 break;
1332 case PIPE_SHADER_GEOMETRY:
1333 if (sctx->chip_class >= GFX9) {
1334 if (sctx->tes_shader.cso) {
1335 key->part.gs.es = sctx->tes_shader.cso;
1336 } else {
1337 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1338 key, &key->part.gs.vs_prolog);
1339 key->part.gs.es = sctx->vs_shader.cso;
1340 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1341 }
1342
1343 /* Merged ES-GS can have unbalanced wave usage.
1344 *
1345 * ES threads are per-vertex, while GS threads are
1346 * per-primitive. So without any amplification, there
1347 * are fewer GS threads than ES threads, which can result
1348 * in empty (no-op) GS waves. With too much amplification,
1349 * there are more GS threads than ES threads, which
1350 * can result in empty (no-op) ES waves.
1351 *
1352 * Non-monolithic shaders are implemented by setting EXEC
1353 * at the beginning of shader parts, and don't jump to
1354 * the end if EXEC is 0.
1355 *
1356 * Monolithic shaders use conditional blocks, so they can
1357 * jump and skip empty waves of ES or GS. So set this to
1358 * always use optimized variants, which are monolithic.
1359 */
1360 key->opt.prefer_mono = 1;
1361 }
1362 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1363 break;
1364 case PIPE_SHADER_FRAGMENT: {
1365 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1366 struct si_state_blend *blend = sctx->queued.named.blend;
1367
1368 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1369 sel->info.colors_written == 0x1)
1370 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1371
1372 if (blend) {
1373 /* Select the shader color format based on whether
1374 * blending or alpha are needed.
1375 */
1376 key->part.ps.epilog.spi_shader_col_format =
1377 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1378 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1379 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1380 sctx->framebuffer.spi_shader_col_format_blend) |
1381 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1382 sctx->framebuffer.spi_shader_col_format_alpha) |
1383 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1384 sctx->framebuffer.spi_shader_col_format);
1385 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1386
1387 /* The output for dual source blending should have
1388 * the same format as the first output.
1389 */
1390 if (blend->dual_src_blend)
1391 key->part.ps.epilog.spi_shader_col_format |=
1392 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1393 } else
1394 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1395
1396 /* If alpha-to-coverage is enabled, we have to export alpha
1397 * even if there is no color buffer.
1398 */
1399 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1400 blend && blend->alpha_to_coverage)
1401 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1402
1403 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1404 * to the range supported by the type if a channel has less
1405 * than 16 bits and the export format is 16_ABGR.
1406 */
1407 if (sctx->chip_class <= CIK && sctx->family != CHIP_HAWAII) {
1408 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1409 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1410 }
1411
1412 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1413 if (!key->part.ps.epilog.last_cbuf) {
1414 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1415 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1416 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1417 }
1418
1419 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1420 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1421
1422 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1423 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1424
1425 if (sctx->queued.named.blend) {
1426 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1427 rs->multisample_enable;
1428 }
1429
1430 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1431 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1432 (is_line && rs->line_smooth)) &&
1433 sctx->framebuffer.nr_samples <= 1;
1434 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1435
1436 if (sctx->ps_iter_samples > 1 &&
1437 sel->info.reads_samplemask) {
1438 key->part.ps.prolog.samplemask_log_ps_iter =
1439 util_logbase2(sctx->ps_iter_samples);
1440 }
1441
1442 if (rs->force_persample_interp &&
1443 rs->multisample_enable &&
1444 sctx->framebuffer.nr_samples > 1 &&
1445 sctx->ps_iter_samples > 1) {
1446 key->part.ps.prolog.force_persp_sample_interp =
1447 sel->info.uses_persp_center ||
1448 sel->info.uses_persp_centroid;
1449
1450 key->part.ps.prolog.force_linear_sample_interp =
1451 sel->info.uses_linear_center ||
1452 sel->info.uses_linear_centroid;
1453 } else if (rs->multisample_enable &&
1454 sctx->framebuffer.nr_samples > 1) {
1455 key->part.ps.prolog.bc_optimize_for_persp =
1456 sel->info.uses_persp_center &&
1457 sel->info.uses_persp_centroid;
1458 key->part.ps.prolog.bc_optimize_for_linear =
1459 sel->info.uses_linear_center &&
1460 sel->info.uses_linear_centroid;
1461 } else {
1462 /* Make sure SPI doesn't compute more than 1 pair
1463 * of (i,j), which is the optimization here. */
1464 key->part.ps.prolog.force_persp_center_interp =
1465 sel->info.uses_persp_center +
1466 sel->info.uses_persp_centroid +
1467 sel->info.uses_persp_sample > 1;
1468
1469 key->part.ps.prolog.force_linear_center_interp =
1470 sel->info.uses_linear_center +
1471 sel->info.uses_linear_centroid +
1472 sel->info.uses_linear_sample > 1;
1473
1474 if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
1475 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1476 }
1477
1478 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1479
1480 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1481 if (sctx->ps_uses_fbfetch) {
1482 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
1483 struct pipe_resource *tex = cb0->texture;
1484
1485 /* 1D textures are allocated and used as 2D on GFX9. */
1486 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
1487 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
1488 (tex->target == PIPE_TEXTURE_1D ||
1489 tex->target == PIPE_TEXTURE_1D_ARRAY);
1490 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
1491 tex->target == PIPE_TEXTURE_2D_ARRAY ||
1492 tex->target == PIPE_TEXTURE_CUBE ||
1493 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
1494 tex->target == PIPE_TEXTURE_3D;
1495 }
1496 break;
1497 }
1498 default:
1499 assert(0);
1500 }
1501
1502 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
1503 memset(&key->opt, 0, sizeof(key->opt));
1504 }
1505
1506 static void si_build_shader_variant(struct si_shader *shader,
1507 int thread_index,
1508 bool low_priority)
1509 {
1510 struct si_shader_selector *sel = shader->selector;
1511 struct si_screen *sscreen = sel->screen;
1512 struct ac_llvm_compiler *compiler;
1513 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1514 int r;
1515
1516 if (thread_index >= 0) {
1517 if (low_priority) {
1518 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
1519 compiler = &sscreen->compiler_lowp[thread_index];
1520 } else {
1521 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
1522 compiler = &sscreen->compiler[thread_index];
1523 }
1524 if (!debug->async)
1525 debug = NULL;
1526 } else {
1527 assert(!low_priority);
1528 compiler = shader->compiler_ctx_state.compiler;
1529 }
1530
1531 r = si_shader_create(sscreen, compiler, shader, debug);
1532 if (unlikely(r)) {
1533 PRINT_ERR("Failed to build shader variant (type=%u) %d\n",
1534 sel->type, r);
1535 shader->compilation_failed = true;
1536 return;
1537 }
1538
1539 if (shader->compiler_ctx_state.is_debug_context) {
1540 FILE *f = open_memstream(&shader->shader_log,
1541 &shader->shader_log_size);
1542 if (f) {
1543 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1544 fclose(f);
1545 }
1546 }
1547
1548 si_shader_init_pm4_state(sscreen, shader);
1549 }
1550
1551 static void si_build_shader_variant_low_priority(void *job, int thread_index)
1552 {
1553 struct si_shader *shader = (struct si_shader *)job;
1554
1555 assert(thread_index >= 0);
1556
1557 si_build_shader_variant(shader, thread_index, true);
1558 }
1559
1560 static const struct si_shader_key zeroed;
1561
1562 static bool si_check_missing_main_part(struct si_screen *sscreen,
1563 struct si_shader_selector *sel,
1564 struct si_compiler_ctx_state *compiler_state,
1565 struct si_shader_key *key)
1566 {
1567 struct si_shader **mainp = si_get_main_shader_part(sel, key);
1568
1569 if (!*mainp) {
1570 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1571
1572 if (!main_part)
1573 return false;
1574
1575 /* We can leave the fence as permanently signaled because the
1576 * main part becomes visible globally only after it has been
1577 * compiled. */
1578 util_queue_fence_init(&main_part->ready);
1579
1580 main_part->selector = sel;
1581 main_part->key.as_es = key->as_es;
1582 main_part->key.as_ls = key->as_ls;
1583 main_part->is_monolithic = false;
1584
1585 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
1586 main_part, &compiler_state->debug) != 0) {
1587 FREE(main_part);
1588 return false;
1589 }
1590 *mainp = main_part;
1591 }
1592 return true;
1593 }
1594
1595 /* Select the hw shader variant depending on the current state. */
1596 static int si_shader_select_with_key(struct si_screen *sscreen,
1597 struct si_shader_ctx_state *state,
1598 struct si_compiler_ctx_state *compiler_state,
1599 struct si_shader_key *key,
1600 int thread_index)
1601 {
1602 struct si_shader_selector *sel = state->cso;
1603 struct si_shader_selector *previous_stage_sel = NULL;
1604 struct si_shader *current = state->current;
1605 struct si_shader *iter, *shader = NULL;
1606
1607 again:
1608 /* Check if we don't need to change anything.
1609 * This path is also used for most shaders that don't need multiple
1610 * variants, it will cost just a computation of the key and this
1611 * test. */
1612 if (likely(current &&
1613 memcmp(&current->key, key, sizeof(*key)) == 0)) {
1614 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
1615 if (current->is_optimized) {
1616 memset(&key->opt, 0, sizeof(key->opt));
1617 goto current_not_ready;
1618 }
1619
1620 util_queue_fence_wait(&current->ready);
1621 }
1622
1623 return current->compilation_failed ? -1 : 0;
1624 }
1625 current_not_ready:
1626
1627 /* This must be done before the mutex is locked, because async GS
1628 * compilation calls this function too, and therefore must enter
1629 * the mutex first.
1630 *
1631 * Only wait if we are in a draw call. Don't wait if we are
1632 * in a compiler thread.
1633 */
1634 if (thread_index < 0)
1635 util_queue_fence_wait(&sel->ready);
1636
1637 mtx_lock(&sel->mutex);
1638
1639 /* Find the shader variant. */
1640 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1641 /* Don't check the "current" shader. We checked it above. */
1642 if (current != iter &&
1643 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1644 mtx_unlock(&sel->mutex);
1645
1646 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
1647 /* If it's an optimized shader and its compilation has
1648 * been started but isn't done, use the unoptimized
1649 * shader so as not to cause a stall due to compilation.
1650 */
1651 if (iter->is_optimized) {
1652 memset(&key->opt, 0, sizeof(key->opt));
1653 goto again;
1654 }
1655
1656 util_queue_fence_wait(&iter->ready);
1657 }
1658
1659 if (iter->compilation_failed) {
1660 return -1; /* skip the draw call */
1661 }
1662
1663 state->current = iter;
1664 return 0;
1665 }
1666 }
1667
1668 /* Build a new shader. */
1669 shader = CALLOC_STRUCT(si_shader);
1670 if (!shader) {
1671 mtx_unlock(&sel->mutex);
1672 return -ENOMEM;
1673 }
1674
1675 util_queue_fence_init(&shader->ready);
1676
1677 shader->selector = sel;
1678 shader->key = *key;
1679 shader->compiler_ctx_state = *compiler_state;
1680
1681 /* If this is a merged shader, get the first shader's selector. */
1682 if (sscreen->info.chip_class >= GFX9) {
1683 if (sel->type == PIPE_SHADER_TESS_CTRL)
1684 previous_stage_sel = key->part.tcs.ls;
1685 else if (sel->type == PIPE_SHADER_GEOMETRY)
1686 previous_stage_sel = key->part.gs.es;
1687
1688 /* We need to wait for the previous shader. */
1689 if (previous_stage_sel && thread_index < 0)
1690 util_queue_fence_wait(&previous_stage_sel->ready);
1691 }
1692
1693 /* Compile the main shader part if it doesn't exist. This can happen
1694 * if the initial guess was wrong. */
1695 bool is_pure_monolithic =
1696 sscreen->use_monolithic_shaders ||
1697 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1698
1699 if (!is_pure_monolithic) {
1700 bool ok;
1701
1702 /* Make sure the main shader part is present. This is needed
1703 * for shaders that can be compiled as VS, LS, or ES, and only
1704 * one of them is compiled at creation.
1705 *
1706 * For merged shaders, check that the starting shader's main
1707 * part is present.
1708 */
1709 if (previous_stage_sel) {
1710 struct si_shader_key shader1_key = zeroed;
1711
1712 if (sel->type == PIPE_SHADER_TESS_CTRL)
1713 shader1_key.as_ls = 1;
1714 else if (sel->type == PIPE_SHADER_GEOMETRY)
1715 shader1_key.as_es = 1;
1716 else
1717 assert(0);
1718
1719 mtx_lock(&previous_stage_sel->mutex);
1720 ok = si_check_missing_main_part(sscreen,
1721 previous_stage_sel,
1722 compiler_state, &shader1_key);
1723 mtx_unlock(&previous_stage_sel->mutex);
1724 } else {
1725 ok = si_check_missing_main_part(sscreen, sel,
1726 compiler_state, key);
1727 }
1728 if (!ok) {
1729 FREE(shader);
1730 mtx_unlock(&sel->mutex);
1731 return -ENOMEM; /* skip the draw call */
1732 }
1733 }
1734
1735 /* Keep the reference to the 1st shader of merged shaders, so that
1736 * Gallium can't destroy it before we destroy the 2nd shader.
1737 *
1738 * Set sctx = NULL, because it's unused if we're not releasing
1739 * the shader, and we don't have any sctx here.
1740 */
1741 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
1742 previous_stage_sel);
1743
1744 /* Monolithic-only shaders don't make a distinction between optimized
1745 * and unoptimized. */
1746 shader->is_monolithic =
1747 is_pure_monolithic ||
1748 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1749
1750 shader->is_optimized =
1751 !is_pure_monolithic &&
1752 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1753
1754 /* If it's an optimized shader, compile it asynchronously. */
1755 if (shader->is_optimized &&
1756 !is_pure_monolithic &&
1757 thread_index < 0) {
1758 /* Compile it asynchronously. */
1759 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
1760 shader, &shader->ready,
1761 si_build_shader_variant_low_priority, NULL);
1762
1763 /* Add only after the ready fence was reset, to guard against a
1764 * race with si_bind_XX_shader. */
1765 if (!sel->last_variant) {
1766 sel->first_variant = shader;
1767 sel->last_variant = shader;
1768 } else {
1769 sel->last_variant->next_variant = shader;
1770 sel->last_variant = shader;
1771 }
1772
1773 /* Use the default (unoptimized) shader for now. */
1774 memset(&key->opt, 0, sizeof(key->opt));
1775 mtx_unlock(&sel->mutex);
1776 goto again;
1777 }
1778
1779 /* Reset the fence before adding to the variant list. */
1780 util_queue_fence_reset(&shader->ready);
1781
1782 if (!sel->last_variant) {
1783 sel->first_variant = shader;
1784 sel->last_variant = shader;
1785 } else {
1786 sel->last_variant->next_variant = shader;
1787 sel->last_variant = shader;
1788 }
1789
1790 mtx_unlock(&sel->mutex);
1791
1792 assert(!shader->is_optimized);
1793 si_build_shader_variant(shader, thread_index, false);
1794
1795 util_queue_fence_signal(&shader->ready);
1796
1797 if (!shader->compilation_failed)
1798 state->current = shader;
1799
1800 return shader->compilation_failed ? -1 : 0;
1801 }
1802
1803 static int si_shader_select(struct pipe_context *ctx,
1804 struct si_shader_ctx_state *state,
1805 struct si_compiler_ctx_state *compiler_state)
1806 {
1807 struct si_context *sctx = (struct si_context *)ctx;
1808 struct si_shader_key key;
1809
1810 si_shader_selector_key(ctx, state->cso, &key);
1811 return si_shader_select_with_key(sctx->screen, state, compiler_state,
1812 &key, -1);
1813 }
1814
1815 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1816 bool streamout,
1817 struct si_shader_key *key)
1818 {
1819 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1820
1821 switch (info->processor) {
1822 case PIPE_SHADER_VERTEX:
1823 switch (next_shader) {
1824 case PIPE_SHADER_GEOMETRY:
1825 key->as_es = 1;
1826 break;
1827 case PIPE_SHADER_TESS_CTRL:
1828 case PIPE_SHADER_TESS_EVAL:
1829 key->as_ls = 1;
1830 break;
1831 default:
1832 /* If POSITION isn't written, it can only be a HW VS
1833 * if streamout is used. If streamout isn't used,
1834 * assume that it's a HW LS. (the next shader is TCS)
1835 * This heuristic is needed for separate shader objects.
1836 */
1837 if (!info->writes_position && !streamout)
1838 key->as_ls = 1;
1839 }
1840 break;
1841
1842 case PIPE_SHADER_TESS_EVAL:
1843 if (next_shader == PIPE_SHADER_GEOMETRY ||
1844 !info->writes_position)
1845 key->as_es = 1;
1846 break;
1847 }
1848 }
1849
1850 /**
1851 * Compile the main shader part or the monolithic shader as part of
1852 * si_shader_selector initialization. Since it can be done asynchronously,
1853 * there is no way to report compile failures to applications.
1854 */
1855 static void si_init_shader_selector_async(void *job, int thread_index)
1856 {
1857 struct si_shader_selector *sel = (struct si_shader_selector *)job;
1858 struct si_screen *sscreen = sel->screen;
1859 struct ac_llvm_compiler *compiler;
1860 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
1861
1862 assert(!debug->debug_message || debug->async);
1863 assert(thread_index >= 0);
1864 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
1865 compiler = &sscreen->compiler[thread_index];
1866
1867 /* Compile the main shader part for use with a prolog and/or epilog.
1868 * If this fails, the driver will try to compile a monolithic shader
1869 * on demand.
1870 */
1871 if (!sscreen->use_monolithic_shaders) {
1872 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1873 void *ir_binary = NULL;
1874
1875 if (!shader) {
1876 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
1877 return;
1878 }
1879
1880 /* We can leave the fence signaled because use of the default
1881 * main part is guarded by the selector's ready fence. */
1882 util_queue_fence_init(&shader->ready);
1883
1884 shader->selector = sel;
1885 shader->is_monolithic = false;
1886 si_parse_next_shader_property(&sel->info,
1887 sel->so.num_outputs != 0,
1888 &shader->key);
1889
1890 if (sel->tokens || sel->nir)
1891 ir_binary = si_get_ir_binary(sel);
1892
1893 /* Try to load the shader from the shader cache. */
1894 mtx_lock(&sscreen->shader_cache_mutex);
1895
1896 if (ir_binary &&
1897 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
1898 mtx_unlock(&sscreen->shader_cache_mutex);
1899 si_shader_dump_stats_for_shader_db(shader, debug);
1900 } else {
1901 mtx_unlock(&sscreen->shader_cache_mutex);
1902
1903 /* Compile the shader if it hasn't been loaded from the cache. */
1904 if (si_compile_tgsi_shader(sscreen, compiler, shader,
1905 debug) != 0) {
1906 FREE(shader);
1907 FREE(ir_binary);
1908 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
1909 return;
1910 }
1911
1912 if (ir_binary) {
1913 mtx_lock(&sscreen->shader_cache_mutex);
1914 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
1915 FREE(ir_binary);
1916 mtx_unlock(&sscreen->shader_cache_mutex);
1917 }
1918 }
1919
1920 *si_get_main_shader_part(sel, &shader->key) = shader;
1921
1922 /* Unset "outputs_written" flags for outputs converted to
1923 * DEFAULT_VAL, so that later inter-shader optimizations don't
1924 * try to eliminate outputs that don't exist in the final
1925 * shader.
1926 *
1927 * This is only done if non-monolithic shaders are enabled.
1928 */
1929 if ((sel->type == PIPE_SHADER_VERTEX ||
1930 sel->type == PIPE_SHADER_TESS_EVAL) &&
1931 !shader->key.as_ls &&
1932 !shader->key.as_es) {
1933 unsigned i;
1934
1935 for (i = 0; i < sel->info.num_outputs; i++) {
1936 unsigned offset = shader->info.vs_output_param_offset[i];
1937
1938 if (offset <= AC_EXP_PARAM_OFFSET_31)
1939 continue;
1940
1941 unsigned name = sel->info.output_semantic_name[i];
1942 unsigned index = sel->info.output_semantic_index[i];
1943 unsigned id;
1944
1945 switch (name) {
1946 case TGSI_SEMANTIC_GENERIC:
1947 /* don't process indices the function can't handle */
1948 if (index >= SI_MAX_IO_GENERIC)
1949 break;
1950 /* fall through */
1951 default:
1952 id = si_shader_io_get_unique_index(name, index, true);
1953 sel->outputs_written_before_ps &= ~(1ull << id);
1954 break;
1955 case TGSI_SEMANTIC_POSITION: /* ignore these */
1956 case TGSI_SEMANTIC_PSIZE:
1957 case TGSI_SEMANTIC_CLIPVERTEX:
1958 case TGSI_SEMANTIC_EDGEFLAG:
1959 break;
1960 }
1961 }
1962 }
1963 }
1964
1965 /* The GS copy shader is always pre-compiled. */
1966 if (sel->type == PIPE_SHADER_GEOMETRY) {
1967 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
1968 if (!sel->gs_copy_shader) {
1969 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
1970 return;
1971 }
1972
1973 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
1974 }
1975 }
1976
1977 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
1978 struct util_queue_fence *ready_fence,
1979 struct si_compiler_ctx_state *compiler_ctx_state,
1980 void *job, util_queue_execute_func execute)
1981 {
1982 util_queue_fence_init(ready_fence);
1983
1984 struct util_async_debug_callback async_debug;
1985 bool wait =
1986 (sctx->debug.debug_message && !sctx->debug.async) ||
1987 sctx->is_debug ||
1988 si_can_dump_shader(sctx->screen, processor);
1989
1990 if (wait) {
1991 u_async_debug_init(&async_debug);
1992 compiler_ctx_state->debug = async_debug.base;
1993 }
1994
1995 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
1996 ready_fence, execute, NULL);
1997
1998 if (wait) {
1999 util_queue_fence_wait(ready_fence);
2000 u_async_debug_drain(&async_debug, &sctx->debug);
2001 u_async_debug_cleanup(&async_debug);
2002 }
2003 }
2004
2005 /* Return descriptor slot usage masks from the given shader info. */
2006 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2007 uint32_t *const_and_shader_buffers,
2008 uint64_t *samplers_and_images)
2009 {
2010 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2011
2012 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2013 num_constbufs = util_last_bit(info->const_buffers_declared);
2014 /* two 8-byte images share one 16-byte slot */
2015 num_images = align(util_last_bit(info->images_declared), 2);
2016 num_samplers = util_last_bit(info->samplers_declared);
2017
2018 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2019 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2020 *const_and_shader_buffers =
2021 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2022
2023 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2024 start = si_get_image_slot(num_images - 1) / 2;
2025 *samplers_and_images =
2026 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2027 }
2028
2029 static void *si_create_shader_selector(struct pipe_context *ctx,
2030 const struct pipe_shader_state *state)
2031 {
2032 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2033 struct si_context *sctx = (struct si_context*)ctx;
2034 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2035 int i;
2036
2037 if (!sel)
2038 return NULL;
2039
2040 pipe_reference_init(&sel->reference, 1);
2041 sel->screen = sscreen;
2042 sel->compiler_ctx_state.debug = sctx->debug;
2043 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2044
2045 sel->so = state->stream_output;
2046
2047 if (state->type == PIPE_SHADER_IR_TGSI) {
2048 sel->tokens = tgsi_dup_tokens(state->tokens);
2049 if (!sel->tokens) {
2050 FREE(sel);
2051 return NULL;
2052 }
2053
2054 tgsi_scan_shader(state->tokens, &sel->info);
2055 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2056 } else {
2057 assert(state->type == PIPE_SHADER_IR_NIR);
2058
2059 sel->nir = state->ir.nir;
2060
2061 si_nir_scan_shader(sel->nir, &sel->info);
2062 si_nir_scan_tess_ctrl(sel->nir, &sel->info, &sel->tcs_info);
2063
2064 si_lower_nir(sel);
2065 }
2066
2067 sel->type = sel->info.processor;
2068 p_atomic_inc(&sscreen->num_shaders_created);
2069 si_get_active_slot_masks(&sel->info,
2070 &sel->active_const_and_shader_buffers,
2071 &sel->active_samplers_and_images);
2072
2073 /* Record which streamout buffers are enabled. */
2074 for (i = 0; i < sel->so.num_outputs; i++) {
2075 sel->enabled_streamout_buffer_mask |=
2076 (1 << sel->so.output[i].output_buffer) <<
2077 (sel->so.output[i].stream * 4);
2078 }
2079
2080 /* The prolog is a no-op if there are no inputs. */
2081 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2082 sel->info.num_inputs &&
2083 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2084
2085 sel->force_correct_derivs_after_kill =
2086 sel->type == PIPE_SHADER_FRAGMENT &&
2087 sel->info.uses_derivatives &&
2088 sel->info.uses_kill &&
2089 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2090
2091 /* Set which opcode uses which (i,j) pair. */
2092 if (sel->info.uses_persp_opcode_interp_centroid)
2093 sel->info.uses_persp_centroid = true;
2094
2095 if (sel->info.uses_linear_opcode_interp_centroid)
2096 sel->info.uses_linear_centroid = true;
2097
2098 if (sel->info.uses_persp_opcode_interp_offset ||
2099 sel->info.uses_persp_opcode_interp_sample)
2100 sel->info.uses_persp_center = true;
2101
2102 if (sel->info.uses_linear_opcode_interp_offset ||
2103 sel->info.uses_linear_opcode_interp_sample)
2104 sel->info.uses_linear_center = true;
2105
2106 switch (sel->type) {
2107 case PIPE_SHADER_GEOMETRY:
2108 sel->gs_output_prim =
2109 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2110 sel->gs_max_out_vertices =
2111 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2112 sel->gs_num_invocations =
2113 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2114 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2115 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2116 sel->gs_max_out_vertices;
2117
2118 sel->max_gs_stream = 0;
2119 for (i = 0; i < sel->so.num_outputs; i++)
2120 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2121 sel->so.output[i].stream);
2122
2123 sel->gs_input_verts_per_prim =
2124 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2125 break;
2126
2127 case PIPE_SHADER_TESS_CTRL:
2128 /* Always reserve space for these. */
2129 sel->patch_outputs_written |=
2130 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2131 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2132 /* fall through */
2133 case PIPE_SHADER_VERTEX:
2134 case PIPE_SHADER_TESS_EVAL:
2135 for (i = 0; i < sel->info.num_outputs; i++) {
2136 unsigned name = sel->info.output_semantic_name[i];
2137 unsigned index = sel->info.output_semantic_index[i];
2138
2139 switch (name) {
2140 case TGSI_SEMANTIC_TESSINNER:
2141 case TGSI_SEMANTIC_TESSOUTER:
2142 case TGSI_SEMANTIC_PATCH:
2143 sel->patch_outputs_written |=
2144 1ull << si_shader_io_get_unique_index_patch(name, index);
2145 break;
2146
2147 case TGSI_SEMANTIC_GENERIC:
2148 /* don't process indices the function can't handle */
2149 if (index >= SI_MAX_IO_GENERIC)
2150 break;
2151 /* fall through */
2152 default:
2153 sel->outputs_written |=
2154 1ull << si_shader_io_get_unique_index(name, index, false);
2155 sel->outputs_written_before_ps |=
2156 1ull << si_shader_io_get_unique_index(name, index, true);
2157 break;
2158 case TGSI_SEMANTIC_EDGEFLAG:
2159 break;
2160 }
2161 }
2162 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2163
2164 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2165 * conflicts, i.e. each vertex will start at a different bank.
2166 */
2167 if (sctx->chip_class >= GFX9)
2168 sel->esgs_itemsize += 4;
2169
2170 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2171 break;
2172
2173 case PIPE_SHADER_FRAGMENT:
2174 for (i = 0; i < sel->info.num_inputs; i++) {
2175 unsigned name = sel->info.input_semantic_name[i];
2176 unsigned index = sel->info.input_semantic_index[i];
2177
2178 switch (name) {
2179 case TGSI_SEMANTIC_GENERIC:
2180 /* don't process indices the function can't handle */
2181 if (index >= SI_MAX_IO_GENERIC)
2182 break;
2183 /* fall through */
2184 default:
2185 sel->inputs_read |=
2186 1ull << si_shader_io_get_unique_index(name, index, true);
2187 break;
2188 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2189 break;
2190 }
2191 }
2192
2193 for (i = 0; i < 8; i++)
2194 if (sel->info.colors_written & (1 << i))
2195 sel->colors_written_4bit |= 0xf << (4 * i);
2196
2197 for (i = 0; i < sel->info.num_inputs; i++) {
2198 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2199 int index = sel->info.input_semantic_index[i];
2200 sel->color_attr_index[index] = i;
2201 }
2202 }
2203 break;
2204 }
2205
2206 /* PA_CL_VS_OUT_CNTL */
2207 bool misc_vec_ena =
2208 sel->info.writes_psize || sel->info.writes_edgeflag ||
2209 sel->info.writes_layer || sel->info.writes_viewport_index;
2210 sel->pa_cl_vs_out_cntl =
2211 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2212 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2213 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2214 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2215 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2216 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2217 sel->clipdist_mask = sel->info.writes_clipvertex ?
2218 SIX_BITS : sel->info.clipdist_writemask;
2219 sel->culldist_mask = sel->info.culldist_writemask <<
2220 sel->info.num_written_clipdistance;
2221
2222 /* DB_SHADER_CONTROL */
2223 sel->db_shader_control =
2224 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2225 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2226 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2227 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2228
2229 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2230 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2231 sel->db_shader_control |=
2232 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2233 break;
2234 case TGSI_FS_DEPTH_LAYOUT_LESS:
2235 sel->db_shader_control |=
2236 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2237 break;
2238 }
2239
2240 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2241 *
2242 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2243 * --|-----------|------------|------------|--------------------|-------------------|-------------
2244 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2245 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2246 * 2 | false | true | n/a | LateZ | 1 | 0
2247 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2248 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2249 *
2250 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2251 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2252 *
2253 * Don't use ReZ without profiling !!!
2254 *
2255 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2256 * shaders.
2257 */
2258 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2259 /* Cases 3, 4. */
2260 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2261 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2262 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2263 } else if (sel->info.writes_memory) {
2264 /* Case 2. */
2265 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2266 S_02880C_EXEC_ON_HIER_FAIL(1);
2267 } else {
2268 /* Case 1. */
2269 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2270 }
2271
2272 (void) mtx_init(&sel->mutex, mtx_plain);
2273
2274 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2275 &sel->compiler_ctx_state, sel,
2276 si_init_shader_selector_async);
2277 return sel;
2278 }
2279
2280 static void si_update_streamout_state(struct si_context *sctx)
2281 {
2282 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2283
2284 if (!shader_with_so)
2285 return;
2286
2287 sctx->streamout.enabled_stream_buffers_mask =
2288 shader_with_so->enabled_streamout_buffer_mask;
2289 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2290 }
2291
2292 static void si_update_clip_regs(struct si_context *sctx,
2293 struct si_shader_selector *old_hw_vs,
2294 struct si_shader *old_hw_vs_variant,
2295 struct si_shader_selector *next_hw_vs,
2296 struct si_shader *next_hw_vs_variant)
2297 {
2298 if (next_hw_vs &&
2299 (!old_hw_vs ||
2300 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2301 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2302 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2303 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2304 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2305 !old_hw_vs_variant ||
2306 !next_hw_vs_variant ||
2307 old_hw_vs_variant->key.opt.clip_disable !=
2308 next_hw_vs_variant->key.opt.clip_disable))
2309 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2310 }
2311
2312 static void si_update_common_shader_state(struct si_context *sctx)
2313 {
2314 sctx->uses_bindless_samplers =
2315 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2316 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2317 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2318 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2319 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2320 sctx->uses_bindless_images =
2321 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2322 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2323 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2324 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2325 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2326 sctx->do_update_shaders = true;
2327 }
2328
2329 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2330 {
2331 struct si_context *sctx = (struct si_context *)ctx;
2332 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2333 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2334 struct si_shader_selector *sel = state;
2335
2336 if (sctx->vs_shader.cso == sel)
2337 return;
2338
2339 sctx->vs_shader.cso = sel;
2340 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2341 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2342
2343 si_update_common_shader_state(sctx);
2344 si_update_vs_viewport_state(sctx);
2345 si_set_active_descriptors_for_shader(sctx, sel);
2346 si_update_streamout_state(sctx);
2347 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2348 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2349 }
2350
2351 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2352 {
2353 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2354 (sctx->tes_shader.cso &&
2355 sctx->tes_shader.cso->info.uses_primid) ||
2356 (sctx->tcs_shader.cso &&
2357 sctx->tcs_shader.cso->info.uses_primid) ||
2358 (sctx->gs_shader.cso &&
2359 sctx->gs_shader.cso->info.uses_primid) ||
2360 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2361 sctx->ps_shader.cso->info.uses_primid);
2362 }
2363
2364 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2365 {
2366 struct si_context *sctx = (struct si_context *)ctx;
2367 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2368 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2369 struct si_shader_selector *sel = state;
2370 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2371
2372 if (sctx->gs_shader.cso == sel)
2373 return;
2374
2375 sctx->gs_shader.cso = sel;
2376 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2377 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2378
2379 si_update_common_shader_state(sctx);
2380 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2381
2382 if (enable_changed) {
2383 si_shader_change_notify(sctx);
2384 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2385 si_update_tess_uses_prim_id(sctx);
2386 }
2387 si_update_vs_viewport_state(sctx);
2388 si_set_active_descriptors_for_shader(sctx, sel);
2389 si_update_streamout_state(sctx);
2390 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2391 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2392 }
2393
2394 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2395 {
2396 struct si_context *sctx = (struct si_context *)ctx;
2397 struct si_shader_selector *sel = state;
2398 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2399
2400 if (sctx->tcs_shader.cso == sel)
2401 return;
2402
2403 sctx->tcs_shader.cso = sel;
2404 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
2405 si_update_tess_uses_prim_id(sctx);
2406
2407 si_update_common_shader_state(sctx);
2408
2409 if (enable_changed)
2410 sctx->last_tcs = NULL; /* invalidate derived tess state */
2411
2412 si_set_active_descriptors_for_shader(sctx, sel);
2413 }
2414
2415 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
2416 {
2417 struct si_context *sctx = (struct si_context *)ctx;
2418 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2419 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2420 struct si_shader_selector *sel = state;
2421 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
2422
2423 if (sctx->tes_shader.cso == sel)
2424 return;
2425
2426 sctx->tes_shader.cso = sel;
2427 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
2428 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
2429 si_update_tess_uses_prim_id(sctx);
2430
2431 si_update_common_shader_state(sctx);
2432 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2433
2434 if (enable_changed) {
2435 si_shader_change_notify(sctx);
2436 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
2437 }
2438 si_update_vs_viewport_state(sctx);
2439 si_set_active_descriptors_for_shader(sctx, sel);
2440 si_update_streamout_state(sctx);
2441 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2442 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2443 }
2444
2445 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2446 {
2447 struct si_context *sctx = (struct si_context *)ctx;
2448 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
2449 struct si_shader_selector *sel = state;
2450
2451 /* skip if supplied shader is one already in use */
2452 if (old_sel == sel)
2453 return;
2454
2455 sctx->ps_shader.cso = sel;
2456 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
2457
2458 si_update_common_shader_state(sctx);
2459 if (sel) {
2460 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2461 si_update_tess_uses_prim_id(sctx);
2462
2463 if (!old_sel ||
2464 old_sel->info.colors_written != sel->info.colors_written)
2465 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2466
2467 if (sctx->screen->has_out_of_order_rast &&
2468 (!old_sel ||
2469 old_sel->info.writes_memory != sel->info.writes_memory ||
2470 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
2471 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
2472 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2473 }
2474 si_set_active_descriptors_for_shader(sctx, sel);
2475 si_update_ps_colorbuf0_slot(sctx);
2476 }
2477
2478 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
2479 {
2480 if (shader->is_optimized) {
2481 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
2482 &shader->ready);
2483 }
2484
2485 util_queue_fence_destroy(&shader->ready);
2486
2487 if (shader->pm4) {
2488 switch (shader->selector->type) {
2489 case PIPE_SHADER_VERTEX:
2490 if (shader->key.as_ls) {
2491 assert(sctx->chip_class <= VI);
2492 si_pm4_delete_state(sctx, ls, shader->pm4);
2493 } else if (shader->key.as_es) {
2494 assert(sctx->chip_class <= VI);
2495 si_pm4_delete_state(sctx, es, shader->pm4);
2496 } else {
2497 si_pm4_delete_state(sctx, vs, shader->pm4);
2498 }
2499 break;
2500 case PIPE_SHADER_TESS_CTRL:
2501 si_pm4_delete_state(sctx, hs, shader->pm4);
2502 break;
2503 case PIPE_SHADER_TESS_EVAL:
2504 if (shader->key.as_es) {
2505 assert(sctx->chip_class <= VI);
2506 si_pm4_delete_state(sctx, es, shader->pm4);
2507 } else {
2508 si_pm4_delete_state(sctx, vs, shader->pm4);
2509 }
2510 break;
2511 case PIPE_SHADER_GEOMETRY:
2512 if (shader->is_gs_copy_shader)
2513 si_pm4_delete_state(sctx, vs, shader->pm4);
2514 else
2515 si_pm4_delete_state(sctx, gs, shader->pm4);
2516 break;
2517 case PIPE_SHADER_FRAGMENT:
2518 si_pm4_delete_state(sctx, ps, shader->pm4);
2519 break;
2520 }
2521 }
2522
2523 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
2524 si_shader_destroy(shader);
2525 free(shader);
2526 }
2527
2528 void si_destroy_shader_selector(struct si_context *sctx,
2529 struct si_shader_selector *sel)
2530 {
2531 struct si_shader *p = sel->first_variant, *c;
2532 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
2533 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
2534 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
2535 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
2536 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
2537 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
2538 };
2539
2540 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
2541
2542 if (current_shader[sel->type]->cso == sel) {
2543 current_shader[sel->type]->cso = NULL;
2544 current_shader[sel->type]->current = NULL;
2545 }
2546
2547 while (p) {
2548 c = p->next_variant;
2549 si_delete_shader(sctx, p);
2550 p = c;
2551 }
2552
2553 if (sel->main_shader_part)
2554 si_delete_shader(sctx, sel->main_shader_part);
2555 if (sel->main_shader_part_ls)
2556 si_delete_shader(sctx, sel->main_shader_part_ls);
2557 if (sel->main_shader_part_es)
2558 si_delete_shader(sctx, sel->main_shader_part_es);
2559 if (sel->gs_copy_shader)
2560 si_delete_shader(sctx, sel->gs_copy_shader);
2561
2562 util_queue_fence_destroy(&sel->ready);
2563 mtx_destroy(&sel->mutex);
2564 free(sel->tokens);
2565 ralloc_free(sel->nir);
2566 free(sel);
2567 }
2568
2569 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
2570 {
2571 struct si_context *sctx = (struct si_context *)ctx;
2572 struct si_shader_selector *sel = (struct si_shader_selector *)state;
2573
2574 si_shader_selector_reference(sctx, &sel, NULL);
2575 }
2576
2577 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
2578 struct si_shader *vs, unsigned name,
2579 unsigned index, unsigned interpolate)
2580 {
2581 struct tgsi_shader_info *vsinfo = &vs->selector->info;
2582 unsigned j, offset, ps_input_cntl = 0;
2583
2584 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
2585 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
2586 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2587
2588 if (name == TGSI_SEMANTIC_PCOORD ||
2589 (name == TGSI_SEMANTIC_TEXCOORD &&
2590 sctx->sprite_coord_enable & (1 << index))) {
2591 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
2592 }
2593
2594 for (j = 0; j < vsinfo->num_outputs; j++) {
2595 if (name == vsinfo->output_semantic_name[j] &&
2596 index == vsinfo->output_semantic_index[j]) {
2597 offset = vs->info.vs_output_param_offset[j];
2598
2599 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2600 /* The input is loaded from parameter memory. */
2601 ps_input_cntl |= S_028644_OFFSET(offset);
2602 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2603 if (offset == AC_EXP_PARAM_UNDEFINED) {
2604 /* This can happen with depth-only rendering. */
2605 offset = 0;
2606 } else {
2607 /* The input is a DEFAULT_VAL constant. */
2608 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2609 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2610 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2611 }
2612
2613 ps_input_cntl = S_028644_OFFSET(0x20) |
2614 S_028644_DEFAULT_VAL(offset);
2615 }
2616 break;
2617 }
2618 }
2619
2620 if (name == TGSI_SEMANTIC_PRIMID)
2621 /* PrimID is written after the last output. */
2622 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
2623 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2624 /* No corresponding output found, load defaults into input.
2625 * Don't set any other bits.
2626 * (FLAT_SHADE=1 completely changes behavior) */
2627 ps_input_cntl = S_028644_OFFSET(0x20);
2628 /* D3D 9 behaviour. GL is undefined */
2629 if (name == TGSI_SEMANTIC_COLOR && index == 0)
2630 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
2631 }
2632 return ps_input_cntl;
2633 }
2634
2635 static void si_emit_spi_map(struct si_context *sctx)
2636 {
2637 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2638 struct si_shader *ps = sctx->ps_shader.current;
2639 struct si_shader *vs = si_get_vs_state(sctx);
2640 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
2641 unsigned i, num_interp, num_written = 0, bcol_interp[2];
2642
2643 if (!ps || !ps->selector->info.num_inputs)
2644 return;
2645
2646 num_interp = si_get_ps_num_interp(ps);
2647 assert(num_interp > 0);
2648 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
2649
2650 for (i = 0; i < psinfo->num_inputs; i++) {
2651 unsigned name = psinfo->input_semantic_name[i];
2652 unsigned index = psinfo->input_semantic_index[i];
2653 unsigned interpolate = psinfo->input_interpolate[i];
2654
2655 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
2656 interpolate));
2657 num_written++;
2658
2659 if (name == TGSI_SEMANTIC_COLOR) {
2660 assert(index < ARRAY_SIZE(bcol_interp));
2661 bcol_interp[index] = interpolate;
2662 }
2663 }
2664
2665 if (ps->key.part.ps.prolog.color_two_side) {
2666 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
2667
2668 for (i = 0; i < 2; i++) {
2669 if (!(psinfo->colors_read & (0xf << (i * 4))))
2670 continue;
2671
2672 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
2673 i, bcol_interp[i]));
2674 num_written++;
2675 }
2676 }
2677 assert(num_interp == num_written);
2678 }
2679
2680 /**
2681 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2682 */
2683 static void si_init_config_add_vgt_flush(struct si_context *sctx)
2684 {
2685 if (sctx->init_config_has_vgt_flush)
2686 return;
2687
2688 /* Done by Vulkan before VGT_FLUSH. */
2689 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2690 si_pm4_cmd_add(sctx->init_config,
2691 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2692 si_pm4_cmd_end(sctx->init_config, false);
2693
2694 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2695 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2696 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2697 si_pm4_cmd_end(sctx->init_config, false);
2698 sctx->init_config_has_vgt_flush = true;
2699 }
2700
2701 /* Initialize state related to ESGS / GSVS ring buffers */
2702 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2703 {
2704 struct si_shader_selector *es =
2705 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2706 struct si_shader_selector *gs = sctx->gs_shader.cso;
2707 struct si_pm4_state *pm4;
2708
2709 /* Chip constants. */
2710 unsigned num_se = sctx->screen->info.max_se;
2711 unsigned wave_size = 64;
2712 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2713 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2714 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2715 */
2716 unsigned gs_vertex_reuse = (sctx->chip_class >= VI ? 32 : 16) * num_se;
2717 unsigned alignment = 256 * num_se;
2718 /* The maximum size is 63.999 MB per SE. */
2719 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2720
2721 /* Calculate the minimum size. */
2722 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
2723 wave_size, alignment);
2724
2725 /* These are recommended sizes, not minimum sizes. */
2726 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2727 es->esgs_itemsize * gs->gs_input_verts_per_prim;
2728 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2729 gs->max_gsvs_emit_size;
2730
2731 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2732 esgs_ring_size = align(esgs_ring_size, alignment);
2733 gsvs_ring_size = align(gsvs_ring_size, alignment);
2734
2735 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2736 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2737
2738 /* Some rings don't have to be allocated if shaders don't use them.
2739 * (e.g. no varyings between ES and GS or GS and VS)
2740 *
2741 * GFX9 doesn't have the ESGS ring.
2742 */
2743 bool update_esgs = sctx->chip_class <= VI &&
2744 esgs_ring_size &&
2745 (!sctx->esgs_ring ||
2746 sctx->esgs_ring->width0 < esgs_ring_size);
2747 bool update_gsvs = gsvs_ring_size &&
2748 (!sctx->gsvs_ring ||
2749 sctx->gsvs_ring->width0 < gsvs_ring_size);
2750
2751 if (!update_esgs && !update_gsvs)
2752 return true;
2753
2754 if (update_esgs) {
2755 pipe_resource_reference(&sctx->esgs_ring, NULL);
2756 sctx->esgs_ring =
2757 pipe_aligned_buffer_create(sctx->b.screen,
2758 SI_RESOURCE_FLAG_UNMAPPABLE,
2759 PIPE_USAGE_DEFAULT,
2760 esgs_ring_size, alignment);
2761 if (!sctx->esgs_ring)
2762 return false;
2763 }
2764
2765 if (update_gsvs) {
2766 pipe_resource_reference(&sctx->gsvs_ring, NULL);
2767 sctx->gsvs_ring =
2768 pipe_aligned_buffer_create(sctx->b.screen,
2769 SI_RESOURCE_FLAG_UNMAPPABLE,
2770 PIPE_USAGE_DEFAULT,
2771 gsvs_ring_size, alignment);
2772 if (!sctx->gsvs_ring)
2773 return false;
2774 }
2775
2776 /* Create the "init_config_gs_rings" state. */
2777 pm4 = CALLOC_STRUCT(si_pm4_state);
2778 if (!pm4)
2779 return false;
2780
2781 if (sctx->chip_class >= CIK) {
2782 if (sctx->esgs_ring) {
2783 assert(sctx->chip_class <= VI);
2784 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2785 sctx->esgs_ring->width0 / 256);
2786 }
2787 if (sctx->gsvs_ring)
2788 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2789 sctx->gsvs_ring->width0 / 256);
2790 } else {
2791 if (sctx->esgs_ring)
2792 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2793 sctx->esgs_ring->width0 / 256);
2794 if (sctx->gsvs_ring)
2795 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2796 sctx->gsvs_ring->width0 / 256);
2797 }
2798
2799 /* Set the state. */
2800 if (sctx->init_config_gs_rings)
2801 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
2802 sctx->init_config_gs_rings = pm4;
2803
2804 if (!sctx->init_config_has_vgt_flush) {
2805 si_init_config_add_vgt_flush(sctx);
2806 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2807 }
2808
2809 /* Flush the context to re-emit both init_config states. */
2810 sctx->initial_gfx_cs_size = 0; /* force flush */
2811 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
2812
2813 /* Set ring bindings. */
2814 if (sctx->esgs_ring) {
2815 assert(sctx->chip_class <= VI);
2816 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
2817 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2818 true, true, 4, 64, 0);
2819 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
2820 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2821 false, false, 0, 0, 0);
2822 }
2823 if (sctx->gsvs_ring) {
2824 si_set_ring_buffer(sctx, SI_RING_GSVS,
2825 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
2826 false, false, 0, 0, 0);
2827 }
2828
2829 return true;
2830 }
2831
2832 static void si_shader_lock(struct si_shader *shader)
2833 {
2834 mtx_lock(&shader->selector->mutex);
2835 if (shader->previous_stage_sel) {
2836 assert(shader->previous_stage_sel != shader->selector);
2837 mtx_lock(&shader->previous_stage_sel->mutex);
2838 }
2839 }
2840
2841 static void si_shader_unlock(struct si_shader *shader)
2842 {
2843 if (shader->previous_stage_sel)
2844 mtx_unlock(&shader->previous_stage_sel->mutex);
2845 mtx_unlock(&shader->selector->mutex);
2846 }
2847
2848 /**
2849 * @returns 1 if \p sel has been updated to use a new scratch buffer
2850 * 0 if not
2851 * < 0 if there was a failure
2852 */
2853 static int si_update_scratch_buffer(struct si_context *sctx,
2854 struct si_shader *shader)
2855 {
2856 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
2857 int r;
2858
2859 if (!shader)
2860 return 0;
2861
2862 /* This shader doesn't need a scratch buffer */
2863 if (shader->config.scratch_bytes_per_wave == 0)
2864 return 0;
2865
2866 /* Prevent race conditions when updating:
2867 * - si_shader::scratch_bo
2868 * - si_shader::binary::code
2869 * - si_shader::previous_stage::binary::code.
2870 */
2871 si_shader_lock(shader);
2872
2873 /* This shader is already configured to use the current
2874 * scratch buffer. */
2875 if (shader->scratch_bo == sctx->scratch_buffer) {
2876 si_shader_unlock(shader);
2877 return 0;
2878 }
2879
2880 assert(sctx->scratch_buffer);
2881
2882 if (shader->previous_stage)
2883 si_shader_apply_scratch_relocs(shader->previous_stage, scratch_va);
2884
2885 si_shader_apply_scratch_relocs(shader, scratch_va);
2886
2887 /* Replace the shader bo with a new bo that has the relocs applied. */
2888 r = si_shader_binary_upload(sctx->screen, shader);
2889 if (r) {
2890 si_shader_unlock(shader);
2891 return r;
2892 }
2893
2894 /* Update the shader state to use the new shader bo. */
2895 si_shader_init_pm4_state(sctx->screen, shader);
2896
2897 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
2898
2899 si_shader_unlock(shader);
2900 return 1;
2901 }
2902
2903 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
2904 {
2905 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
2906 }
2907
2908 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
2909 {
2910 return shader ? shader->config.scratch_bytes_per_wave : 0;
2911 }
2912
2913 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
2914 {
2915 if (!sctx->tes_shader.cso)
2916 return NULL; /* tessellation disabled */
2917
2918 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
2919 sctx->fixed_func_tcs_shader.current;
2920 }
2921
2922 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
2923 {
2924 unsigned bytes = 0;
2925
2926 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
2927 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
2928 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
2929 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
2930
2931 if (sctx->tes_shader.cso) {
2932 struct si_shader *tcs = si_get_tcs_current(sctx);
2933
2934 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
2935 }
2936 return bytes;
2937 }
2938
2939 static bool si_update_scratch_relocs(struct si_context *sctx)
2940 {
2941 struct si_shader *tcs = si_get_tcs_current(sctx);
2942 int r;
2943
2944 /* Update the shaders, so that they are using the latest scratch.
2945 * The scratch buffer may have been changed since these shaders were
2946 * last used, so we still need to try to update them, even if they
2947 * require scratch buffers smaller than the current size.
2948 */
2949 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
2950 if (r < 0)
2951 return false;
2952 if (r == 1)
2953 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2954
2955 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
2956 if (r < 0)
2957 return false;
2958 if (r == 1)
2959 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2960
2961 r = si_update_scratch_buffer(sctx, tcs);
2962 if (r < 0)
2963 return false;
2964 if (r == 1)
2965 si_pm4_bind_state(sctx, hs, tcs->pm4);
2966
2967 /* VS can be bound as LS, ES, or VS. */
2968 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
2969 if (r < 0)
2970 return false;
2971 if (r == 1) {
2972 if (sctx->tes_shader.current)
2973 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2974 else if (sctx->gs_shader.current)
2975 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2976 else
2977 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2978 }
2979
2980 /* TES can be bound as ES or VS. */
2981 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
2982 if (r < 0)
2983 return false;
2984 if (r == 1) {
2985 if (sctx->gs_shader.current)
2986 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2987 else
2988 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2989 }
2990
2991 return true;
2992 }
2993
2994 static bool si_update_spi_tmpring_size(struct si_context *sctx)
2995 {
2996 unsigned current_scratch_buffer_size =
2997 si_get_current_scratch_buffer_size(sctx);
2998 unsigned scratch_bytes_per_wave =
2999 si_get_max_scratch_bytes_per_wave(sctx);
3000 unsigned scratch_needed_size = scratch_bytes_per_wave *
3001 sctx->scratch_waves;
3002 unsigned spi_tmpring_size;
3003
3004 if (scratch_needed_size > 0) {
3005 if (scratch_needed_size > current_scratch_buffer_size) {
3006 /* Create a bigger scratch buffer */
3007 r600_resource_reference(&sctx->scratch_buffer, NULL);
3008
3009 sctx->scratch_buffer =
3010 si_aligned_buffer_create(&sctx->screen->b,
3011 SI_RESOURCE_FLAG_UNMAPPABLE,
3012 PIPE_USAGE_DEFAULT,
3013 scratch_needed_size, 256);
3014 if (!sctx->scratch_buffer)
3015 return false;
3016
3017 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3018 si_context_add_resource_size(sctx,
3019 &sctx->scratch_buffer->b.b);
3020 }
3021
3022 if (!si_update_scratch_relocs(sctx))
3023 return false;
3024 }
3025
3026 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3027 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3028 "scratch size should already be aligned correctly.");
3029
3030 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3031 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3032 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3033 sctx->spi_tmpring_size = spi_tmpring_size;
3034 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3035 }
3036 return true;
3037 }
3038
3039 static void si_init_tess_factor_ring(struct si_context *sctx)
3040 {
3041 assert(!sctx->tess_rings);
3042
3043 /* The address must be aligned to 2^19, because the shader only
3044 * receives the high 13 bits.
3045 */
3046 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3047 SI_RESOURCE_FLAG_32BIT,
3048 PIPE_USAGE_DEFAULT,
3049 sctx->screen->tess_offchip_ring_size +
3050 sctx->screen->tess_factor_ring_size,
3051 1 << 19);
3052 if (!sctx->tess_rings)
3053 return;
3054
3055 si_init_config_add_vgt_flush(sctx);
3056
3057 si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_rings),
3058 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3059
3060 uint64_t factor_va = r600_resource(sctx->tess_rings)->gpu_address +
3061 sctx->screen->tess_offchip_ring_size;
3062
3063 /* Append these registers to the init config state. */
3064 if (sctx->chip_class >= CIK) {
3065 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3066 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3067 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3068 factor_va >> 8);
3069 if (sctx->chip_class >= GFX9)
3070 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3071 S_030944_BASE_HI(factor_va >> 40));
3072 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3073 sctx->screen->vgt_hs_offchip_param);
3074 } else {
3075 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3076 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3077 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3078 factor_va >> 8);
3079 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3080 sctx->screen->vgt_hs_offchip_param);
3081 }
3082
3083 /* Flush the context to re-emit the init_config state.
3084 * This is done only once in a lifetime of a context.
3085 */
3086 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3087 sctx->initial_gfx_cs_size = 0; /* force flush */
3088 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3089 }
3090
3091 /**
3092 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
3093 * VS passes its outputs to TES directly, so the fixed-function shader only
3094 * has to write TESSOUTER and TESSINNER.
3095 */
3096 static void si_generate_fixed_func_tcs(struct si_context *sctx)
3097 {
3098 struct ureg_src outer, inner;
3099 struct ureg_dst tessouter, tessinner;
3100 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
3101
3102 if (!ureg)
3103 return; /* if we get here, we're screwed */
3104
3105 assert(!sctx->fixed_func_tcs_shader.cso);
3106
3107 outer = ureg_DECL_system_value(ureg,
3108 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
3109 inner = ureg_DECL_system_value(ureg,
3110 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
3111
3112 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
3113 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
3114
3115 ureg_MOV(ureg, tessouter, outer);
3116 ureg_MOV(ureg, tessinner, inner);
3117 ureg_END(ureg);
3118
3119 sctx->fixed_func_tcs_shader.cso =
3120 ureg_create_shader_and_destroy(ureg, &sctx->b);
3121 }
3122
3123 static void si_update_vgt_shader_config(struct si_context *sctx)
3124 {
3125 /* Calculate the index of the config.
3126 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3127 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
3128 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
3129
3130 if (!*pm4) {
3131 uint32_t stages = 0;
3132
3133 *pm4 = CALLOC_STRUCT(si_pm4_state);
3134
3135 if (sctx->tes_shader.cso) {
3136 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3137 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3138
3139 if (sctx->gs_shader.cso)
3140 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3141 S_028B54_GS_EN(1) |
3142 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3143 else
3144 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3145 } else if (sctx->gs_shader.cso) {
3146 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3147 S_028B54_GS_EN(1) |
3148 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3149 }
3150
3151 if (sctx->chip_class >= GFX9)
3152 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3153
3154 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3155 }
3156 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3157 }
3158
3159 bool si_update_shaders(struct si_context *sctx)
3160 {
3161 struct pipe_context *ctx = (struct pipe_context*)sctx;
3162 struct si_compiler_ctx_state compiler_state;
3163 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3164 struct si_shader *old_vs = si_get_vs_state(sctx);
3165 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3166 struct si_shader *old_ps = sctx->ps_shader.current;
3167 unsigned old_spi_shader_col_format =
3168 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3169 int r;
3170
3171 compiler_state.compiler = &sctx->compiler;
3172 compiler_state.debug = sctx->debug;
3173 compiler_state.is_debug_context = sctx->is_debug;
3174
3175 /* Update stages before GS. */
3176 if (sctx->tes_shader.cso) {
3177 if (!sctx->tess_rings) {
3178 si_init_tess_factor_ring(sctx);
3179 if (!sctx->tess_rings)
3180 return false;
3181 }
3182
3183 /* VS as LS */
3184 if (sctx->chip_class <= VI) {
3185 r = si_shader_select(ctx, &sctx->vs_shader,
3186 &compiler_state);
3187 if (r)
3188 return false;
3189 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3190 }
3191
3192 if (sctx->tcs_shader.cso) {
3193 r = si_shader_select(ctx, &sctx->tcs_shader,
3194 &compiler_state);
3195 if (r)
3196 return false;
3197 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3198 } else {
3199 if (!sctx->fixed_func_tcs_shader.cso) {
3200 si_generate_fixed_func_tcs(sctx);
3201 if (!sctx->fixed_func_tcs_shader.cso)
3202 return false;
3203 }
3204
3205 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3206 &compiler_state);
3207 if (r)
3208 return false;
3209 si_pm4_bind_state(sctx, hs,
3210 sctx->fixed_func_tcs_shader.current->pm4);
3211 }
3212
3213 if (sctx->gs_shader.cso) {
3214 /* TES as ES */
3215 if (sctx->chip_class <= VI) {
3216 r = si_shader_select(ctx, &sctx->tes_shader,
3217 &compiler_state);
3218 if (r)
3219 return false;
3220 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3221 }
3222 } else {
3223 /* TES as VS */
3224 r = si_shader_select(ctx, &sctx->tes_shader,
3225 &compiler_state);
3226 if (r)
3227 return false;
3228 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3229 }
3230 } else if (sctx->gs_shader.cso) {
3231 if (sctx->chip_class <= VI) {
3232 /* VS as ES */
3233 r = si_shader_select(ctx, &sctx->vs_shader,
3234 &compiler_state);
3235 if (r)
3236 return false;
3237 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3238
3239 si_pm4_bind_state(sctx, ls, NULL);
3240 si_pm4_bind_state(sctx, hs, NULL);
3241 }
3242 } else {
3243 /* VS as VS */
3244 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
3245 if (r)
3246 return false;
3247 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3248 si_pm4_bind_state(sctx, ls, NULL);
3249 si_pm4_bind_state(sctx, hs, NULL);
3250 }
3251
3252 /* Update GS. */
3253 if (sctx->gs_shader.cso) {
3254 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
3255 if (r)
3256 return false;
3257 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3258 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3259
3260 if (!si_update_gs_ring_buffers(sctx))
3261 return false;
3262 } else {
3263 si_pm4_bind_state(sctx, gs, NULL);
3264 if (sctx->chip_class <= VI)
3265 si_pm4_bind_state(sctx, es, NULL);
3266 }
3267
3268 si_update_vgt_shader_config(sctx);
3269
3270 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3271 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3272
3273 if (sctx->ps_shader.cso) {
3274 unsigned db_shader_control;
3275
3276 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
3277 if (r)
3278 return false;
3279 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3280
3281 db_shader_control =
3282 sctx->ps_shader.cso->db_shader_control |
3283 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3284
3285 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3286 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3287 sctx->flatshade != rs->flatshade) {
3288 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3289 sctx->flatshade = rs->flatshade;
3290 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3291 }
3292
3293 if (sctx->screen->rbplus_allowed &&
3294 si_pm4_state_changed(sctx, ps) &&
3295 (!old_ps ||
3296 old_spi_shader_col_format !=
3297 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3298 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3299
3300 if (sctx->ps_db_shader_control != db_shader_control) {
3301 sctx->ps_db_shader_control = db_shader_control;
3302 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3303 if (sctx->screen->dpbb_allowed)
3304 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3305 }
3306
3307 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3308 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3309 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3310
3311 if (sctx->chip_class == SI)
3312 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3313
3314 if (sctx->framebuffer.nr_samples <= 1)
3315 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3316 }
3317 }
3318
3319 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3320 si_pm4_state_enabled_and_changed(sctx, hs) ||
3321 si_pm4_state_enabled_and_changed(sctx, es) ||
3322 si_pm4_state_enabled_and_changed(sctx, gs) ||
3323 si_pm4_state_enabled_and_changed(sctx, vs) ||
3324 si_pm4_state_enabled_and_changed(sctx, ps)) {
3325 if (!si_update_spi_tmpring_size(sctx))
3326 return false;
3327 }
3328
3329 if (sctx->chip_class >= CIK) {
3330 if (si_pm4_state_enabled_and_changed(sctx, ls))
3331 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3332 else if (!sctx->queued.named.ls)
3333 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3334
3335 if (si_pm4_state_enabled_and_changed(sctx, hs))
3336 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3337 else if (!sctx->queued.named.hs)
3338 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3339
3340 if (si_pm4_state_enabled_and_changed(sctx, es))
3341 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
3342 else if (!sctx->queued.named.es)
3343 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
3344
3345 if (si_pm4_state_enabled_and_changed(sctx, gs))
3346 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
3347 else if (!sctx->queued.named.gs)
3348 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
3349
3350 if (si_pm4_state_enabled_and_changed(sctx, vs))
3351 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
3352 else if (!sctx->queued.named.vs)
3353 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
3354
3355 if (si_pm4_state_enabled_and_changed(sctx, ps))
3356 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
3357 else if (!sctx->queued.named.ps)
3358 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
3359 }
3360
3361 sctx->do_update_shaders = false;
3362 return true;
3363 }
3364
3365 static void si_emit_scratch_state(struct si_context *sctx)
3366 {
3367 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3368
3369 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3370 sctx->spi_tmpring_size);
3371
3372 if (sctx->scratch_buffer) {
3373 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3374 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3375 RADEON_PRIO_SCRATCH_BUFFER);
3376 }
3377 }
3378
3379 void *si_get_blit_vs(struct si_context *sctx, enum blitter_attrib_type type,
3380 unsigned num_layers)
3381 {
3382 unsigned vs_blit_property;
3383 void **vs;
3384
3385 switch (type) {
3386 case UTIL_BLITTER_ATTRIB_NONE:
3387 vs = num_layers > 1 ? &sctx->vs_blit_pos_layered :
3388 &sctx->vs_blit_pos;
3389 vs_blit_property = SI_VS_BLIT_SGPRS_POS;
3390 break;
3391 case UTIL_BLITTER_ATTRIB_COLOR:
3392 vs = num_layers > 1 ? &sctx->vs_blit_color_layered :
3393 &sctx->vs_blit_color;
3394 vs_blit_property = SI_VS_BLIT_SGPRS_POS_COLOR;
3395 break;
3396 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
3397 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
3398 assert(num_layers == 1);
3399 vs = &sctx->vs_blit_texcoord;
3400 vs_blit_property = SI_VS_BLIT_SGPRS_POS_TEXCOORD;
3401 break;
3402 default:
3403 assert(0);
3404 return NULL;
3405 }
3406 if (*vs)
3407 return *vs;
3408
3409 struct ureg_program *ureg = ureg_create(PIPE_SHADER_VERTEX);
3410 if (!ureg)
3411 return NULL;
3412
3413 /* Tell the shader to load VS inputs from SGPRs: */
3414 ureg_property(ureg, TGSI_PROPERTY_VS_BLIT_SGPRS, vs_blit_property);
3415 ureg_property(ureg, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION, true);
3416
3417 /* This is just a pass-through shader with 1-3 MOV instructions. */
3418 ureg_MOV(ureg,
3419 ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0),
3420 ureg_DECL_vs_input(ureg, 0));
3421
3422 if (type != UTIL_BLITTER_ATTRIB_NONE) {
3423 ureg_MOV(ureg,
3424 ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, 0),
3425 ureg_DECL_vs_input(ureg, 1));
3426 }
3427
3428 if (num_layers > 1) {
3429 struct ureg_src instance_id =
3430 ureg_DECL_system_value(ureg, TGSI_SEMANTIC_INSTANCEID, 0);
3431 struct ureg_dst layer =
3432 ureg_DECL_output(ureg, TGSI_SEMANTIC_LAYER, 0);
3433
3434 ureg_MOV(ureg, ureg_writemask(layer, TGSI_WRITEMASK_X),
3435 ureg_scalar(instance_id, TGSI_SWIZZLE_X));
3436 }
3437 ureg_END(ureg);
3438
3439 *vs = ureg_create_shader_and_destroy(ureg, &sctx->b);
3440 return *vs;
3441 }
3442
3443 void si_init_shader_functions(struct si_context *sctx)
3444 {
3445 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
3446 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
3447
3448 sctx->b.create_vs_state = si_create_shader_selector;
3449 sctx->b.create_tcs_state = si_create_shader_selector;
3450 sctx->b.create_tes_state = si_create_shader_selector;
3451 sctx->b.create_gs_state = si_create_shader_selector;
3452 sctx->b.create_fs_state = si_create_shader_selector;
3453
3454 sctx->b.bind_vs_state = si_bind_vs_shader;
3455 sctx->b.bind_tcs_state = si_bind_tcs_shader;
3456 sctx->b.bind_tes_state = si_bind_tes_shader;
3457 sctx->b.bind_gs_state = si_bind_gs_shader;
3458 sctx->b.bind_fs_state = si_bind_ps_shader;
3459
3460 sctx->b.delete_vs_state = si_delete_shader_selector;
3461 sctx->b.delete_tcs_state = si_delete_shader_selector;
3462 sctx->b.delete_tes_state = si_delete_shader_selector;
3463 sctx->b.delete_gs_state = si_delete_shader_selector;
3464 sctx->b.delete_fs_state = si_delete_shader_selector;
3465 }