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radeonsi: reduce the scope of sel->mutex in si_shader_select_with_key
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "sid.h"
26 #include "gfx9d.h"
27 #include "radeon/r600_cs.h"
28
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_ureg.h"
31 #include "util/hash_table.h"
32 #include "util/crc32.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39
40 /* SHADER_CACHE */
41
42 /**
43 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
44 * integer.
45 */
46 static void *si_get_tgsi_binary(struct si_shader_selector *sel)
47 {
48 unsigned tgsi_size = tgsi_num_tokens(sel->tokens) *
49 sizeof(struct tgsi_token);
50 unsigned size = 4 + tgsi_size + sizeof(sel->so);
51 char *result = (char*)MALLOC(size);
52
53 if (!result)
54 return NULL;
55
56 *((uint32_t*)result) = size;
57 memcpy(result + 4, sel->tokens, tgsi_size);
58 memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so));
59 return result;
60 }
61
62 /** Copy "data" to "ptr" and return the next dword following copied data. */
63 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
64 {
65 /* data may be NULL if size == 0 */
66 if (size)
67 memcpy(ptr, data, size);
68 ptr += DIV_ROUND_UP(size, 4);
69 return ptr;
70 }
71
72 /** Read data from "ptr". Return the next dword following the data. */
73 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
74 {
75 memcpy(data, ptr, size);
76 ptr += DIV_ROUND_UP(size, 4);
77 return ptr;
78 }
79
80 /**
81 * Write the size as uint followed by the data. Return the next dword
82 * following the copied data.
83 */
84 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
85 {
86 *ptr++ = size;
87 return write_data(ptr, data, size);
88 }
89
90 /**
91 * Read the size as uint followed by the data. Return both via parameters.
92 * Return the next dword following the data.
93 */
94 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
95 {
96 *size = *ptr++;
97 assert(*data == NULL);
98 if (!*size)
99 return ptr;
100 *data = malloc(*size);
101 return read_data(ptr, *data, *size);
102 }
103
104 /**
105 * Return the shader binary in a buffer. The first 4 bytes contain its size
106 * as integer.
107 */
108 static void *si_get_shader_binary(struct si_shader *shader)
109 {
110 /* There is always a size of data followed by the data itself. */
111 unsigned relocs_size = shader->binary.reloc_count *
112 sizeof(shader->binary.relocs[0]);
113 unsigned disasm_size = shader->binary.disasm_string ?
114 strlen(shader->binary.disasm_string) + 1 : 0;
115 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
116 strlen(shader->binary.llvm_ir_string) + 1 : 0;
117 unsigned size =
118 4 + /* total size */
119 4 + /* CRC32 of the data below */
120 align(sizeof(shader->config), 4) +
121 align(sizeof(shader->info), 4) +
122 4 + align(shader->binary.code_size, 4) +
123 4 + align(shader->binary.rodata_size, 4) +
124 4 + align(relocs_size, 4) +
125 4 + align(disasm_size, 4) +
126 4 + align(llvm_ir_size, 4);
127 void *buffer = CALLOC(1, size);
128 uint32_t *ptr = (uint32_t*)buffer;
129
130 if (!buffer)
131 return NULL;
132
133 *ptr++ = size;
134 ptr++; /* CRC32 is calculated at the end. */
135
136 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
137 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
138 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
139 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
140 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
141 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
142 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
143 assert((char *)ptr - (char *)buffer == size);
144
145 /* Compute CRC32. */
146 ptr = (uint32_t*)buffer;
147 ptr++;
148 *ptr = util_hash_crc32(ptr + 1, size - 8);
149
150 return buffer;
151 }
152
153 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
154 {
155 uint32_t *ptr = (uint32_t*)binary;
156 uint32_t size = *ptr++;
157 uint32_t crc32 = *ptr++;
158 unsigned chunk_size;
159
160 if (util_hash_crc32(ptr, size - 8) != crc32) {
161 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
162 return false;
163 }
164
165 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
166 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
167 ptr = read_chunk(ptr, (void**)&shader->binary.code,
168 &shader->binary.code_size);
169 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
170 &shader->binary.rodata_size);
171 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
172 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
173 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
174 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
175
176 return true;
177 }
178
179 /**
180 * Insert a shader into the cache. It's assumed the shader is not in the cache.
181 * Use si_shader_cache_load_shader before calling this.
182 *
183 * Returns false on failure, in which case the tgsi_binary should be freed.
184 */
185 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
186 void *tgsi_binary,
187 struct si_shader *shader,
188 bool insert_into_disk_cache)
189 {
190 void *hw_binary;
191 struct hash_entry *entry;
192 uint8_t key[CACHE_KEY_SIZE];
193
194 entry = _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
195 if (entry)
196 return false; /* already added */
197
198 hw_binary = si_get_shader_binary(shader);
199 if (!hw_binary)
200 return false;
201
202 if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
203 hw_binary) == NULL) {
204 FREE(hw_binary);
205 return false;
206 }
207
208 if (sscreen->b.disk_shader_cache && insert_into_disk_cache) {
209 disk_cache_compute_key(sscreen->b.disk_shader_cache, tgsi_binary,
210 *((uint32_t *)tgsi_binary), key);
211 disk_cache_put(sscreen->b.disk_shader_cache, key, hw_binary,
212 *((uint32_t *) hw_binary), NULL);
213 }
214
215 return true;
216 }
217
218 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
219 void *tgsi_binary,
220 struct si_shader *shader)
221 {
222 struct hash_entry *entry =
223 _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
224 if (!entry) {
225 if (sscreen->b.disk_shader_cache) {
226 unsigned char sha1[CACHE_KEY_SIZE];
227 size_t tg_size = *((uint32_t *) tgsi_binary);
228
229 disk_cache_compute_key(sscreen->b.disk_shader_cache,
230 tgsi_binary, tg_size, sha1);
231
232 size_t binary_size;
233 uint8_t *buffer =
234 disk_cache_get(sscreen->b.disk_shader_cache,
235 sha1, &binary_size);
236 if (!buffer)
237 return false;
238
239 if (binary_size < sizeof(uint32_t) ||
240 *((uint32_t*)buffer) != binary_size) {
241 /* Something has gone wrong discard the item
242 * from the cache and rebuild/link from
243 * source.
244 */
245 assert(!"Invalid radeonsi shader disk cache "
246 "item!");
247
248 disk_cache_remove(sscreen->b.disk_shader_cache,
249 sha1);
250 free(buffer);
251
252 return false;
253 }
254
255 if (!si_load_shader_binary(shader, buffer)) {
256 free(buffer);
257 return false;
258 }
259 free(buffer);
260
261 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary,
262 shader, false))
263 FREE(tgsi_binary);
264 } else {
265 return false;
266 }
267 } else {
268 if (si_load_shader_binary(shader, entry->data))
269 FREE(tgsi_binary);
270 else
271 return false;
272 }
273 p_atomic_inc(&sscreen->b.num_shader_cache_hits);
274 return true;
275 }
276
277 static uint32_t si_shader_cache_key_hash(const void *key)
278 {
279 /* The first dword is the key size. */
280 return util_hash_crc32(key, *(uint32_t*)key);
281 }
282
283 static bool si_shader_cache_key_equals(const void *a, const void *b)
284 {
285 uint32_t *keya = (uint32_t*)a;
286 uint32_t *keyb = (uint32_t*)b;
287
288 /* The first dword is the key size. */
289 if (*keya != *keyb)
290 return false;
291
292 return memcmp(keya, keyb, *keya) == 0;
293 }
294
295 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
296 {
297 FREE((void*)entry->key);
298 FREE(entry->data);
299 }
300
301 bool si_init_shader_cache(struct si_screen *sscreen)
302 {
303 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
304 sscreen->shader_cache =
305 _mesa_hash_table_create(NULL,
306 si_shader_cache_key_hash,
307 si_shader_cache_key_equals);
308
309 return sscreen->shader_cache != NULL;
310 }
311
312 void si_destroy_shader_cache(struct si_screen *sscreen)
313 {
314 if (sscreen->shader_cache)
315 _mesa_hash_table_destroy(sscreen->shader_cache,
316 si_destroy_shader_cache_entry);
317 mtx_destroy(&sscreen->shader_cache_mutex);
318 }
319
320 /* SHADER STATES */
321
322 static void si_set_tesseval_regs(struct si_screen *sscreen,
323 struct si_shader_selector *tes,
324 struct si_pm4_state *pm4)
325 {
326 struct tgsi_shader_info *info = &tes->info;
327 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
328 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
329 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
330 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
331 unsigned type, partitioning, topology, distribution_mode;
332
333 switch (tes_prim_mode) {
334 case PIPE_PRIM_LINES:
335 type = V_028B6C_TESS_ISOLINE;
336 break;
337 case PIPE_PRIM_TRIANGLES:
338 type = V_028B6C_TESS_TRIANGLE;
339 break;
340 case PIPE_PRIM_QUADS:
341 type = V_028B6C_TESS_QUAD;
342 break;
343 default:
344 assert(0);
345 return;
346 }
347
348 switch (tes_spacing) {
349 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
350 partitioning = V_028B6C_PART_FRAC_ODD;
351 break;
352 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
353 partitioning = V_028B6C_PART_FRAC_EVEN;
354 break;
355 case PIPE_TESS_SPACING_EQUAL:
356 partitioning = V_028B6C_PART_INTEGER;
357 break;
358 default:
359 assert(0);
360 return;
361 }
362
363 if (tes_point_mode)
364 topology = V_028B6C_OUTPUT_POINT;
365 else if (tes_prim_mode == PIPE_PRIM_LINES)
366 topology = V_028B6C_OUTPUT_LINE;
367 else if (tes_vertex_order_cw)
368 /* for some reason, this must be the other way around */
369 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
370 else
371 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
372
373 if (sscreen->has_distributed_tess) {
374 if (sscreen->b.family == CHIP_FIJI ||
375 sscreen->b.family >= CHIP_POLARIS10)
376 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
377 else
378 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
379 } else
380 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
381
382 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
383 S_028B6C_TYPE(type) |
384 S_028B6C_PARTITIONING(partitioning) |
385 S_028B6C_TOPOLOGY(topology) |
386 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
387 }
388
389 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
390 * whether the "fractional odd" tessellation spacing is used.
391 *
392 * Possible VGT configurations and which state should set the register:
393 *
394 * Reg set in | VGT shader configuration | Value
395 * ------------------------------------------------------
396 * VS as VS | VS | 30
397 * VS as ES | ES -> GS -> VS | 30
398 * TES as VS | LS -> HS -> VS | 14 or 30
399 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
400 *
401 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
402 */
403 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
404 struct si_shader_selector *sel,
405 struct si_shader *shader,
406 struct si_pm4_state *pm4)
407 {
408 unsigned type = sel->type;
409
410 if (sscreen->b.family < CHIP_POLARIS10)
411 return;
412
413 /* VS as VS, or VS as ES: */
414 if ((type == PIPE_SHADER_VERTEX &&
415 (!shader ||
416 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
417 /* TES as VS, or TES as ES: */
418 type == PIPE_SHADER_TESS_EVAL) {
419 unsigned vtx_reuse_depth = 30;
420
421 if (type == PIPE_SHADER_TESS_EVAL &&
422 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
423 PIPE_TESS_SPACING_FRACTIONAL_ODD)
424 vtx_reuse_depth = 14;
425
426 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
427 vtx_reuse_depth);
428 }
429 }
430
431 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
432 {
433 if (shader->pm4)
434 si_pm4_clear_state(shader->pm4);
435 else
436 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
437
438 return shader->pm4;
439 }
440
441 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
442 {
443 struct si_pm4_state *pm4;
444 unsigned vgpr_comp_cnt;
445 uint64_t va;
446
447 assert(sscreen->b.chip_class <= VI);
448
449 pm4 = si_get_shader_pm4_state(shader);
450 if (!pm4)
451 return;
452
453 va = shader->bo->gpu_address;
454 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
455
456 /* We need at least 2 components for LS.
457 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
458 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
459 */
460 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
461
462 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
463 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
464
465 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
466 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
467 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
468 S_00B528_DX10_CLAMP(1) |
469 S_00B528_FLOAT_MODE(shader->config.float_mode);
470 shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_VS_NUM_USER_SGPR) |
471 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
472 }
473
474 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
475 {
476 struct si_pm4_state *pm4;
477 uint64_t va;
478 unsigned ls_vgpr_comp_cnt = 0;
479
480 pm4 = si_get_shader_pm4_state(shader);
481 if (!pm4)
482 return;
483
484 va = shader->bo->gpu_address;
485 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
486
487 if (sscreen->b.chip_class >= GFX9) {
488 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
489 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, va >> 40);
490
491 /* We need at least 2 components for LS.
492 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
493 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
494 */
495 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
496
497 shader->config.rsrc2 =
498 S_00B42C_USER_SGPR(GFX9_TCS_NUM_USER_SGPR) |
499 S_00B42C_USER_SGPR_MSB(GFX9_TCS_NUM_USER_SGPR >> 5) |
500 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
501 } else {
502 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
503 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
504
505 shader->config.rsrc2 =
506 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
507 S_00B42C_OC_LDS_EN(1) |
508 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
509 }
510
511 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
512 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
513 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
514 S_00B428_DX10_CLAMP(1) |
515 S_00B428_FLOAT_MODE(shader->config.float_mode) |
516 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
517
518 if (sscreen->b.chip_class <= VI) {
519 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
520 shader->config.rsrc2);
521 }
522 }
523
524 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
525 {
526 struct si_pm4_state *pm4;
527 unsigned num_user_sgprs;
528 unsigned vgpr_comp_cnt;
529 uint64_t va;
530 unsigned oc_lds_en;
531
532 assert(sscreen->b.chip_class <= VI);
533
534 pm4 = si_get_shader_pm4_state(shader);
535 if (!pm4)
536 return;
537
538 va = shader->bo->gpu_address;
539 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
540
541 if (shader->selector->type == PIPE_SHADER_VERTEX) {
542 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
543 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
544 num_user_sgprs = SI_VS_NUM_USER_SGPR;
545 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
546 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
547 num_user_sgprs = SI_TES_NUM_USER_SGPR;
548 } else
549 unreachable("invalid shader selector type");
550
551 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
552
553 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
554 shader->selector->esgs_itemsize / 4);
555 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
556 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
557 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
558 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
559 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
560 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
561 S_00B328_DX10_CLAMP(1) |
562 S_00B328_FLOAT_MODE(shader->config.float_mode));
563 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
564 S_00B32C_USER_SGPR(num_user_sgprs) |
565 S_00B32C_OC_LDS_EN(oc_lds_en) |
566 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
567
568 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
569 si_set_tesseval_regs(sscreen, shader->selector, pm4);
570
571 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
572 }
573
574 /**
575 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
576 * geometry shader.
577 */
578 static uint32_t si_vgt_gs_mode(struct si_shader_selector *sel)
579 {
580 enum chip_class chip_class = sel->screen->b.chip_class;
581 unsigned gs_max_vert_out = sel->gs_max_out_vertices;
582 unsigned cut_mode;
583
584 if (gs_max_vert_out <= 128) {
585 cut_mode = V_028A40_GS_CUT_128;
586 } else if (gs_max_vert_out <= 256) {
587 cut_mode = V_028A40_GS_CUT_256;
588 } else if (gs_max_vert_out <= 512) {
589 cut_mode = V_028A40_GS_CUT_512;
590 } else {
591 assert(gs_max_vert_out <= 1024);
592 cut_mode = V_028A40_GS_CUT_1024;
593 }
594
595 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
596 S_028A40_CUT_MODE(cut_mode)|
597 S_028A40_ES_WRITE_OPTIMIZE(chip_class <= VI) |
598 S_028A40_GS_WRITE_OPTIMIZE(1) |
599 S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0);
600 }
601
602 struct gfx9_gs_info {
603 unsigned es_verts_per_subgroup;
604 unsigned gs_prims_per_subgroup;
605 unsigned gs_inst_prims_in_subgroup;
606 unsigned max_prims_per_subgroup;
607 unsigned lds_size;
608 };
609
610 static void gfx9_get_gs_info(struct si_shader_selector *es,
611 struct si_shader_selector *gs,
612 struct gfx9_gs_info *out)
613 {
614 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
615 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
616 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
617 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
618
619 /* All these are in dwords: */
620 /* We can't allow using the whole LDS, because GS waves compete with
621 * other shader stages for LDS space. */
622 const unsigned max_lds_size = 8 * 1024;
623 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
624 unsigned esgs_lds_size;
625
626 /* All these are per subgroup: */
627 const unsigned max_out_prims = 32 * 1024;
628 const unsigned max_es_verts = 255;
629 const unsigned ideal_gs_prims = 64;
630 unsigned max_gs_prims, gs_prims;
631 unsigned min_es_verts, es_verts, worst_case_es_verts;
632
633 assert(gs_num_invocations <= 32); /* GL maximum */
634
635 if (uses_adjacency || gs_num_invocations > 1)
636 max_gs_prims = 127 / gs_num_invocations;
637 else
638 max_gs_prims = 255;
639
640 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
641 * Make sure we don't go over the maximum value.
642 */
643 if (gs->gs_max_out_vertices > 0) {
644 max_gs_prims = MIN2(max_gs_prims,
645 max_out_prims /
646 (gs->gs_max_out_vertices * gs_num_invocations));
647 }
648 assert(max_gs_prims > 0);
649
650 /* If the primitive has adjacency, halve the number of vertices
651 * that will be reused in multiple primitives.
652 */
653 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
654
655 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
656 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
657
658 /* Compute ESGS LDS size based on the worst case number of ES vertices
659 * needed to create the target number of GS prims per subgroup.
660 */
661 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
662
663 /* If total LDS usage is too big, refactor partitions based on ratio
664 * of ESGS item sizes.
665 */
666 if (esgs_lds_size > max_lds_size) {
667 /* Our target GS Prims Per Subgroup was too large. Calculate
668 * the maximum number of GS Prims Per Subgroup that will fit
669 * into LDS, capped by the maximum that the hardware can support.
670 */
671 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
672 max_gs_prims);
673 assert(gs_prims > 0);
674 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
675 max_es_verts);
676
677 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
678 assert(esgs_lds_size <= max_lds_size);
679 }
680
681 /* Now calculate remaining ESGS information. */
682 if (esgs_lds_size)
683 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
684 else
685 es_verts = max_es_verts;
686
687 /* Vertices for adjacency primitives are not always reused, so restore
688 * it for ES_VERTS_PER_SUBGRP.
689 */
690 min_es_verts = gs->gs_input_verts_per_prim;
691
692 /* For normal primitives, the VGT only checks if they are past the ES
693 * verts per subgroup after allocating a full GS primitive and if they
694 * are, kick off a new subgroup. But if those additional ES verts are
695 * unique (e.g. not reused) we need to make sure there is enough LDS
696 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
697 */
698 es_verts -= min_es_verts - 1;
699
700 out->es_verts_per_subgroup = es_verts;
701 out->gs_prims_per_subgroup = gs_prims;
702 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
703 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
704 gs->gs_max_out_vertices;
705 out->lds_size = align(esgs_lds_size, 128) / 128;
706
707 assert(out->max_prims_per_subgroup <= max_out_prims);
708 }
709
710 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
711 {
712 struct si_shader_selector *sel = shader->selector;
713 const ubyte *num_components = sel->info.num_stream_output_components;
714 unsigned gs_num_invocations = sel->gs_num_invocations;
715 struct si_pm4_state *pm4;
716 uint64_t va;
717 unsigned max_stream = sel->max_gs_stream;
718 unsigned offset;
719
720 pm4 = si_get_shader_pm4_state(shader);
721 if (!pm4)
722 return;
723
724 offset = num_components[0] * sel->gs_max_out_vertices;
725 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, offset);
726 if (max_stream >= 1)
727 offset += num_components[1] * sel->gs_max_out_vertices;
728 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, offset);
729 if (max_stream >= 2)
730 offset += num_components[2] * sel->gs_max_out_vertices;
731 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, offset);
732 if (max_stream >= 3)
733 offset += num_components[3] * sel->gs_max_out_vertices;
734 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
735
736 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
737 assert(offset < (1 << 15));
738
739 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, sel->gs_max_out_vertices);
740
741 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, num_components[0]);
742 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? num_components[1] : 0);
743 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? num_components[2] : 0);
744 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? num_components[3] : 0);
745
746 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
747 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
748 S_028B90_ENABLE(gs_num_invocations > 0));
749
750 va = shader->bo->gpu_address;
751 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
752
753 if (sscreen->b.chip_class >= GFX9) {
754 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
755 unsigned es_type = shader->key.part.gs.es->type;
756 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
757 struct gfx9_gs_info gs_info;
758
759 if (es_type == PIPE_SHADER_VERTEX)
760 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
761 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
762 else if (es_type == PIPE_SHADER_TESS_EVAL)
763 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
764 else
765 unreachable("invalid shader selector type");
766
767 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
768 * VGPR[0:4] are always loaded.
769 */
770 if (sel->info.uses_invocationid)
771 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
772 else if (sel->info.uses_primid)
773 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
774 else if (input_prim >= PIPE_PRIM_TRIANGLES)
775 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
776 else
777 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
778
779 gfx9_get_gs_info(shader->key.part.gs.es, sel, &gs_info);
780
781 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
782 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, va >> 40);
783
784 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
785 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
786 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
787 S_00B228_DX10_CLAMP(1) |
788 S_00B228_FLOAT_MODE(shader->config.float_mode) |
789 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
790 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
791 S_00B22C_USER_SGPR(GFX9_GS_NUM_USER_SGPR) |
792 S_00B22C_USER_SGPR_MSB(GFX9_GS_NUM_USER_SGPR >> 5) |
793 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
794 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
795 S_00B22C_LDS_SIZE(gs_info.lds_size) |
796 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
797
798 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
799 S_028A44_ES_VERTS_PER_SUBGRP(gs_info.es_verts_per_subgroup) |
800 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info.gs_prims_per_subgroup) |
801 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info.gs_inst_prims_in_subgroup));
802 si_pm4_set_reg(pm4, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
803 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info.max_prims_per_subgroup));
804 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
805 shader->key.part.gs.es->esgs_itemsize / 4);
806
807 if (es_type == PIPE_SHADER_TESS_EVAL)
808 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
809
810 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
811 NULL, pm4);
812 } else {
813 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
814 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
815
816 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
817 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
818 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
819 S_00B228_DX10_CLAMP(1) |
820 S_00B228_FLOAT_MODE(shader->config.float_mode));
821 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
822 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
823 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
824 }
825 }
826
827 /**
828 * Compute the state for \p shader, which will run as a vertex shader on the
829 * hardware.
830 *
831 * If \p gs is non-NULL, it points to the geometry shader for which this shader
832 * is the copy shader.
833 */
834 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
835 struct si_shader_selector *gs)
836 {
837 const struct tgsi_shader_info *info = &shader->selector->info;
838 struct si_pm4_state *pm4;
839 unsigned num_user_sgprs;
840 unsigned nparams, vgpr_comp_cnt;
841 uint64_t va;
842 unsigned oc_lds_en;
843 unsigned window_space =
844 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
845 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
846
847 pm4 = si_get_shader_pm4_state(shader);
848 if (!pm4)
849 return;
850
851 /* We always write VGT_GS_MODE in the VS state, because every switch
852 * between different shader pipelines involving a different GS or no
853 * GS at all involves a switch of the VS (different GS use different
854 * copy shaders). On the other hand, when the API switches from a GS to
855 * no GS and then back to the same GS used originally, the GS state is
856 * not sent again.
857 */
858 if (!gs) {
859 unsigned mode = V_028A40_GS_OFF;
860
861 /* PrimID needs GS scenario A. */
862 if (enable_prim_id)
863 mode = V_028A40_GS_SCENARIO_A;
864
865 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, S_028A40_MODE(mode));
866 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
867 } else {
868 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
869 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
870 }
871
872 if (sscreen->b.chip_class <= VI) {
873 /* Reuse needs to be set off if we write oViewport. */
874 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF,
875 S_028AB4_REUSE_OFF(info->writes_viewport_index));
876 }
877
878 va = shader->bo->gpu_address;
879 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
880
881 if (gs) {
882 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
883 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
884 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
885 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
886 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
887 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
888 */
889 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
890
891 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
892 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
893 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
894 } else {
895 num_user_sgprs = SI_VS_NUM_USER_SGPR;
896 }
897 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
898 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
899 num_user_sgprs = SI_TES_NUM_USER_SGPR;
900 } else
901 unreachable("invalid shader selector type");
902
903 /* VS is required to export at least one param. */
904 nparams = MAX2(shader->info.nr_param_exports, 1);
905 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
906 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
907
908 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
909 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
910 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
911 V_02870C_SPI_SHADER_4COMP :
912 V_02870C_SPI_SHADER_NONE) |
913 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
914 V_02870C_SPI_SHADER_4COMP :
915 V_02870C_SPI_SHADER_NONE) |
916 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
917 V_02870C_SPI_SHADER_4COMP :
918 V_02870C_SPI_SHADER_NONE));
919
920 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
921
922 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
923 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
924 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
925 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
926 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
927 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
928 S_00B128_DX10_CLAMP(1) |
929 S_00B128_FLOAT_MODE(shader->config.float_mode));
930 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
931 S_00B12C_USER_SGPR(num_user_sgprs) |
932 S_00B12C_OC_LDS_EN(oc_lds_en) |
933 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
934 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
935 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
936 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
937 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
938 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
939 if (window_space)
940 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
941 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
942 else
943 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
944 S_028818_VTX_W0_FMT(1) |
945 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
946 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
947 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
948
949 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
950 si_set_tesseval_regs(sscreen, shader->selector, pm4);
951
952 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
953 }
954
955 static unsigned si_get_ps_num_interp(struct si_shader *ps)
956 {
957 struct tgsi_shader_info *info = &ps->selector->info;
958 unsigned num_colors = !!(info->colors_read & 0x0f) +
959 !!(info->colors_read & 0xf0);
960 unsigned num_interp = ps->selector->info.num_inputs +
961 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
962
963 assert(num_interp <= 32);
964 return MIN2(num_interp, 32);
965 }
966
967 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
968 {
969 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
970 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
971
972 /* If the i-th target format is set, all previous target formats must
973 * be non-zero to avoid hangs.
974 */
975 for (i = 0; i < num_targets; i++)
976 if (!(value & (0xf << (i * 4))))
977 value |= V_028714_SPI_SHADER_32_R << (i * 4);
978
979 return value;
980 }
981
982 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
983 {
984 unsigned i, cb_shader_mask = 0;
985
986 for (i = 0; i < 8; i++) {
987 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
988 case V_028714_SPI_SHADER_ZERO:
989 break;
990 case V_028714_SPI_SHADER_32_R:
991 cb_shader_mask |= 0x1 << (i * 4);
992 break;
993 case V_028714_SPI_SHADER_32_GR:
994 cb_shader_mask |= 0x3 << (i * 4);
995 break;
996 case V_028714_SPI_SHADER_32_AR:
997 cb_shader_mask |= 0x9 << (i * 4);
998 break;
999 case V_028714_SPI_SHADER_FP16_ABGR:
1000 case V_028714_SPI_SHADER_UNORM16_ABGR:
1001 case V_028714_SPI_SHADER_SNORM16_ABGR:
1002 case V_028714_SPI_SHADER_UINT16_ABGR:
1003 case V_028714_SPI_SHADER_SINT16_ABGR:
1004 case V_028714_SPI_SHADER_32_ABGR:
1005 cb_shader_mask |= 0xf << (i * 4);
1006 break;
1007 default:
1008 assert(0);
1009 }
1010 }
1011 return cb_shader_mask;
1012 }
1013
1014 static void si_shader_ps(struct si_shader *shader)
1015 {
1016 struct tgsi_shader_info *info = &shader->selector->info;
1017 struct si_pm4_state *pm4;
1018 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1019 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1020 uint64_t va;
1021 unsigned input_ena = shader->config.spi_ps_input_ena;
1022
1023 /* we need to enable at least one of them, otherwise we hang the GPU */
1024 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1025 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1026 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1027 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1028 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1029 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1030 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1031 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1032 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1033 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1034 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1035 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1036 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1037 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1038
1039 /* Validate interpolation optimization flags (read as implications). */
1040 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1041 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1042 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1043 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1044 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1045 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1046 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1047 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1048 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1049 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1050 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1051 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1052 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1053 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1054 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1055 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1056 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1057 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1058
1059 /* Validate cases when the optimizations are off (read as implications). */
1060 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1061 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1062 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1063 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1064 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1065 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1066
1067 pm4 = si_get_shader_pm4_state(shader);
1068 if (!pm4)
1069 return;
1070
1071 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1072 * Possible vaules:
1073 * 0 -> Position = pixel center
1074 * 1 -> Position = pixel centroid
1075 * 2 -> Position = at sample position
1076 *
1077 * From GLSL 4.5 specification, section 7.1:
1078 * "The variable gl_FragCoord is available as an input variable from
1079 * within fragment shaders and it holds the window relative coordinates
1080 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1081 * value can be for any location within the pixel, or one of the
1082 * fragment samples. The use of centroid does not further restrict
1083 * this value to be inside the current primitive."
1084 *
1085 * Meaning that centroid has no effect and we can return anything within
1086 * the pixel. Thus, return the value at sample position, because that's
1087 * the most accurate one shaders can get.
1088 */
1089 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1090
1091 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1092 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1093 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1094
1095 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1096 cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
1097
1098 /* Ensure that some export memory is always allocated, for two reasons:
1099 *
1100 * 1) Correctness: The hardware ignores the EXEC mask if no export
1101 * memory is allocated, so KILL and alpha test do not work correctly
1102 * without this.
1103 * 2) Performance: Every shader needs at least a NULL export, even when
1104 * it writes no color/depth output. The NULL export instruction
1105 * stalls without this setting.
1106 *
1107 * Don't add this to CB_SHADER_MASK.
1108 */
1109 if (!spi_shader_col_format &&
1110 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1111 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1112
1113 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
1114 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
1115 shader->config.spi_ps_input_addr);
1116
1117 /* Set interpolation controls. */
1118 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1119
1120 /* Set registers. */
1121 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1122 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
1123
1124 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
1125 si_get_spi_shader_z_format(info->writes_z,
1126 info->writes_stencil,
1127 info->writes_samplemask));
1128
1129 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
1130 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
1131
1132 va = shader->bo->gpu_address;
1133 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1134 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1135 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
1136
1137 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
1138 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1139 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
1140 S_00B028_DX10_CLAMP(1) |
1141 S_00B028_FLOAT_MODE(shader->config.float_mode));
1142 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1143 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1144 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1145 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1146 }
1147
1148 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1149 struct si_shader *shader)
1150 {
1151 switch (shader->selector->type) {
1152 case PIPE_SHADER_VERTEX:
1153 if (shader->key.as_ls)
1154 si_shader_ls(sscreen, shader);
1155 else if (shader->key.as_es)
1156 si_shader_es(sscreen, shader);
1157 else
1158 si_shader_vs(sscreen, shader, NULL);
1159 break;
1160 case PIPE_SHADER_TESS_CTRL:
1161 si_shader_hs(sscreen, shader);
1162 break;
1163 case PIPE_SHADER_TESS_EVAL:
1164 if (shader->key.as_es)
1165 si_shader_es(sscreen, shader);
1166 else
1167 si_shader_vs(sscreen, shader, NULL);
1168 break;
1169 case PIPE_SHADER_GEOMETRY:
1170 si_shader_gs(sscreen, shader);
1171 break;
1172 case PIPE_SHADER_FRAGMENT:
1173 si_shader_ps(shader);
1174 break;
1175 default:
1176 assert(0);
1177 }
1178 }
1179
1180 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1181 {
1182 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1183 if (sctx->queued.named.dsa)
1184 return sctx->queued.named.dsa->alpha_func;
1185
1186 return PIPE_FUNC_ALWAYS;
1187 }
1188
1189 static void si_shader_selector_key_vs(struct si_context *sctx,
1190 struct si_shader_selector *vs,
1191 struct si_shader_key *key,
1192 struct si_vs_prolog_bits *prolog_key)
1193 {
1194 if (!sctx->vertex_elements)
1195 return;
1196
1197 prolog_key->instance_divisor_is_one =
1198 sctx->vertex_elements->instance_divisor_is_one;
1199 prolog_key->instance_divisor_is_fetched =
1200 sctx->vertex_elements->instance_divisor_is_fetched;
1201
1202 /* Prefer a monolithic shader to allow scheduling divisions around
1203 * VBO loads. */
1204 if (prolog_key->instance_divisor_is_fetched)
1205 key->opt.prefer_mono = 1;
1206
1207 unsigned count = MIN2(vs->info.num_inputs,
1208 sctx->vertex_elements->count);
1209 memcpy(key->mono.vs_fix_fetch, sctx->vertex_elements->fix_fetch, count);
1210 }
1211
1212 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1213 struct si_shader_selector *vs,
1214 struct si_shader_key *key)
1215 {
1216 struct si_shader_selector *ps = sctx->ps_shader.cso;
1217
1218 key->opt.clip_disable =
1219 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1220 (vs->info.clipdist_writemask ||
1221 vs->info.writes_clipvertex) &&
1222 !vs->info.culldist_writemask;
1223
1224 /* Find out if PS is disabled. */
1225 bool ps_disabled = true;
1226 if (ps) {
1227 bool ps_modifies_zs = ps->info.uses_kill ||
1228 ps->info.writes_z ||
1229 ps->info.writes_stencil ||
1230 ps->info.writes_samplemask ||
1231 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1232
1233 unsigned ps_colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1234 sctx->queued.named.blend->cb_target_mask;
1235 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1236 ps_colormask &= ps->colors_written_4bit;
1237
1238 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1239 (!ps_colormask &&
1240 !ps_modifies_zs &&
1241 !ps->info.writes_memory);
1242 }
1243
1244 /* Find out which VS outputs aren't used by the PS. */
1245 uint64_t outputs_written = vs->outputs_written;
1246 uint64_t inputs_read = 0;
1247
1248 /* ignore POSITION, PSIZE */
1249 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0) |
1250 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0))));
1251
1252 if (!ps_disabled) {
1253 inputs_read = ps->inputs_read;
1254 }
1255
1256 uint64_t linked = outputs_written & inputs_read;
1257
1258 key->opt.kill_outputs = ~linked & outputs_written;
1259 }
1260
1261 /* Compute the key for the hw shader variant */
1262 static inline void si_shader_selector_key(struct pipe_context *ctx,
1263 struct si_shader_selector *sel,
1264 struct si_shader_key *key)
1265 {
1266 struct si_context *sctx = (struct si_context *)ctx;
1267
1268 memset(key, 0, sizeof(*key));
1269
1270 switch (sel->type) {
1271 case PIPE_SHADER_VERTEX:
1272 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1273
1274 if (sctx->tes_shader.cso)
1275 key->as_ls = 1;
1276 else if (sctx->gs_shader.cso)
1277 key->as_es = 1;
1278 else {
1279 si_shader_selector_key_hw_vs(sctx, sel, key);
1280
1281 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1282 key->mono.u.vs_export_prim_id = 1;
1283 }
1284 break;
1285 case PIPE_SHADER_TESS_CTRL:
1286 if (sctx->b.chip_class >= GFX9) {
1287 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1288 key, &key->part.tcs.ls_prolog);
1289 key->part.tcs.ls = sctx->vs_shader.cso;
1290
1291 /* When the LS VGPR fix is needed, monolithic shaders
1292 * can:
1293 * - avoid initializing EXEC in both the LS prolog
1294 * and the LS main part when !vs_needs_prolog
1295 * - remove the fixup for unused input VGPRs
1296 */
1297 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1298
1299 /* The LS output / HS input layout can be communicated
1300 * directly instead of via user SGPRs for merged LS-HS.
1301 * The LS VGPR fix prefers this too.
1302 */
1303 key->opt.prefer_mono = 1;
1304 }
1305
1306 key->part.tcs.epilog.prim_mode =
1307 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1308 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1309 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1310 key->part.tcs.epilog.tes_reads_tess_factors =
1311 sctx->tes_shader.cso->info.reads_tess_factors;
1312
1313 if (sel == sctx->fixed_func_tcs_shader.cso)
1314 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1315 break;
1316 case PIPE_SHADER_TESS_EVAL:
1317 if (sctx->gs_shader.cso)
1318 key->as_es = 1;
1319 else {
1320 si_shader_selector_key_hw_vs(sctx, sel, key);
1321
1322 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1323 key->mono.u.vs_export_prim_id = 1;
1324 }
1325 break;
1326 case PIPE_SHADER_GEOMETRY:
1327 if (sctx->b.chip_class >= GFX9) {
1328 if (sctx->tes_shader.cso) {
1329 key->part.gs.es = sctx->tes_shader.cso;
1330 } else {
1331 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1332 key, &key->part.gs.vs_prolog);
1333 key->part.gs.es = sctx->vs_shader.cso;
1334 }
1335
1336 /* Merged ES-GS can have unbalanced wave usage.
1337 *
1338 * ES threads are per-vertex, while GS threads are
1339 * per-primitive. So without any amplification, there
1340 * are fewer GS threads than ES threads, which can result
1341 * in empty (no-op) GS waves. With too much amplification,
1342 * there are more GS threads than ES threads, which
1343 * can result in empty (no-op) ES waves.
1344 *
1345 * Non-monolithic shaders are implemented by setting EXEC
1346 * at the beginning of shader parts, and don't jump to
1347 * the end if EXEC is 0.
1348 *
1349 * Monolithic shaders use conditional blocks, so they can
1350 * jump and skip empty waves of ES or GS. So set this to
1351 * always use optimized variants, which are monolithic.
1352 */
1353 key->opt.prefer_mono = 1;
1354 }
1355 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1356 break;
1357 case PIPE_SHADER_FRAGMENT: {
1358 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1359 struct si_state_blend *blend = sctx->queued.named.blend;
1360
1361 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1362 sel->info.colors_written == 0x1)
1363 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1364
1365 if (blend) {
1366 /* Select the shader color format based on whether
1367 * blending or alpha are needed.
1368 */
1369 key->part.ps.epilog.spi_shader_col_format =
1370 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1371 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1372 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1373 sctx->framebuffer.spi_shader_col_format_blend) |
1374 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1375 sctx->framebuffer.spi_shader_col_format_alpha) |
1376 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1377 sctx->framebuffer.spi_shader_col_format);
1378 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1379
1380 /* The output for dual source blending should have
1381 * the same format as the first output.
1382 */
1383 if (blend->dual_src_blend)
1384 key->part.ps.epilog.spi_shader_col_format |=
1385 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1386 } else
1387 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1388
1389 /* If alpha-to-coverage is enabled, we have to export alpha
1390 * even if there is no color buffer.
1391 */
1392 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1393 blend && blend->alpha_to_coverage)
1394 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1395
1396 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1397 * to the range supported by the type if a channel has less
1398 * than 16 bits and the export format is 16_ABGR.
1399 */
1400 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII) {
1401 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1402 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1403 }
1404
1405 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1406 if (!key->part.ps.epilog.last_cbuf) {
1407 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1408 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1409 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1410 }
1411
1412 if (rs) {
1413 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
1414 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
1415 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
1416 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
1417
1418 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1419 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1420
1421 if (sctx->queued.named.blend) {
1422 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1423 rs->multisample_enable;
1424 }
1425
1426 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1427 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1428 (is_line && rs->line_smooth)) &&
1429 sctx->framebuffer.nr_samples <= 1;
1430 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1431
1432 if (sctx->ps_iter_samples > 1 &&
1433 sel->info.reads_samplemask) {
1434 key->part.ps.prolog.samplemask_log_ps_iter =
1435 util_logbase2(util_next_power_of_two(sctx->ps_iter_samples));
1436 }
1437
1438 if (rs->force_persample_interp &&
1439 rs->multisample_enable &&
1440 sctx->framebuffer.nr_samples > 1 &&
1441 sctx->ps_iter_samples > 1) {
1442 key->part.ps.prolog.force_persp_sample_interp =
1443 sel->info.uses_persp_center ||
1444 sel->info.uses_persp_centroid;
1445
1446 key->part.ps.prolog.force_linear_sample_interp =
1447 sel->info.uses_linear_center ||
1448 sel->info.uses_linear_centroid;
1449 } else if (rs->multisample_enable &&
1450 sctx->framebuffer.nr_samples > 1) {
1451 key->part.ps.prolog.bc_optimize_for_persp =
1452 sel->info.uses_persp_center &&
1453 sel->info.uses_persp_centroid;
1454 key->part.ps.prolog.bc_optimize_for_linear =
1455 sel->info.uses_linear_center &&
1456 sel->info.uses_linear_centroid;
1457 } else {
1458 /* Make sure SPI doesn't compute more than 1 pair
1459 * of (i,j), which is the optimization here. */
1460 key->part.ps.prolog.force_persp_center_interp =
1461 sel->info.uses_persp_center +
1462 sel->info.uses_persp_centroid +
1463 sel->info.uses_persp_sample > 1;
1464
1465 key->part.ps.prolog.force_linear_center_interp =
1466 sel->info.uses_linear_center +
1467 sel->info.uses_linear_centroid +
1468 sel->info.uses_linear_sample > 1;
1469
1470 if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
1471 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1472 }
1473 }
1474
1475 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1476 break;
1477 }
1478 default:
1479 assert(0);
1480 }
1481
1482 if (unlikely(sctx->screen->b.debug_flags & DBG(NO_OPT_VARIANT)))
1483 memset(&key->opt, 0, sizeof(key->opt));
1484 }
1485
1486 static void si_build_shader_variant(struct si_shader *shader,
1487 int thread_index,
1488 bool low_priority)
1489 {
1490 struct si_shader_selector *sel = shader->selector;
1491 struct si_screen *sscreen = sel->screen;
1492 LLVMTargetMachineRef tm;
1493 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1494 int r;
1495
1496 if (thread_index >= 0) {
1497 if (low_priority) {
1498 assert(thread_index < ARRAY_SIZE(sscreen->tm_low_priority));
1499 tm = sscreen->tm_low_priority[thread_index];
1500 } else {
1501 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1502 tm = sscreen->tm[thread_index];
1503 }
1504 if (!debug->async)
1505 debug = NULL;
1506 } else {
1507 assert(!low_priority);
1508 tm = shader->compiler_ctx_state.tm;
1509 }
1510
1511 r = si_shader_create(sscreen, tm, shader, debug);
1512 if (unlikely(r)) {
1513 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1514 sel->type, r);
1515 shader->compilation_failed = true;
1516 return;
1517 }
1518
1519 if (shader->compiler_ctx_state.is_debug_context) {
1520 FILE *f = open_memstream(&shader->shader_log,
1521 &shader->shader_log_size);
1522 if (f) {
1523 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1524 fclose(f);
1525 }
1526 }
1527
1528 si_shader_init_pm4_state(sscreen, shader);
1529 }
1530
1531 static void si_build_shader_variant_low_priority(void *job, int thread_index)
1532 {
1533 struct si_shader *shader = (struct si_shader *)job;
1534
1535 assert(thread_index >= 0);
1536
1537 si_build_shader_variant(shader, thread_index, true);
1538 }
1539
1540 static const struct si_shader_key zeroed;
1541
1542 static bool si_check_missing_main_part(struct si_screen *sscreen,
1543 struct si_shader_selector *sel,
1544 struct si_compiler_ctx_state *compiler_state,
1545 struct si_shader_key *key)
1546 {
1547 struct si_shader **mainp = si_get_main_shader_part(sel, key);
1548
1549 if (!*mainp) {
1550 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1551
1552 if (!main_part)
1553 return false;
1554
1555 /* We can leave the fence as permanently signaled because the
1556 * main part becomes visible globally only after it has been
1557 * compiled. */
1558 util_queue_fence_init(&main_part->ready);
1559
1560 main_part->selector = sel;
1561 main_part->key.as_es = key->as_es;
1562 main_part->key.as_ls = key->as_ls;
1563
1564 if (si_compile_tgsi_shader(sscreen, compiler_state->tm,
1565 main_part, false,
1566 &compiler_state->debug) != 0) {
1567 FREE(main_part);
1568 return false;
1569 }
1570 *mainp = main_part;
1571 }
1572 return true;
1573 }
1574
1575 /* Select the hw shader variant depending on the current state. */
1576 static int si_shader_select_with_key(struct si_screen *sscreen,
1577 struct si_shader_ctx_state *state,
1578 struct si_compiler_ctx_state *compiler_state,
1579 struct si_shader_key *key,
1580 int thread_index)
1581 {
1582 struct si_shader_selector *sel = state->cso;
1583 struct si_shader_selector *previous_stage_sel = NULL;
1584 struct si_shader *current = state->current;
1585 struct si_shader *iter, *shader = NULL;
1586
1587 again:
1588 /* Check if we don't need to change anything.
1589 * This path is also used for most shaders that don't need multiple
1590 * variants, it will cost just a computation of the key and this
1591 * test. */
1592 if (likely(current &&
1593 memcmp(&current->key, key, sizeof(*key)) == 0)) {
1594 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
1595 if (current->is_optimized) {
1596 memset(&key->opt, 0, sizeof(key->opt));
1597 goto current_not_ready;
1598 }
1599
1600 util_queue_fence_wait(&current->ready);
1601 }
1602
1603 return current->compilation_failed ? -1 : 0;
1604 }
1605 current_not_ready:
1606
1607 /* This must be done before the mutex is locked, because async GS
1608 * compilation calls this function too, and therefore must enter
1609 * the mutex first.
1610 *
1611 * Only wait if we are in a draw call. Don't wait if we are
1612 * in a compiler thread.
1613 */
1614 if (thread_index < 0)
1615 util_queue_fence_wait(&sel->ready);
1616
1617 mtx_lock(&sel->mutex);
1618
1619 /* Find the shader variant. */
1620 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1621 /* Don't check the "current" shader. We checked it above. */
1622 if (current != iter &&
1623 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1624 mtx_unlock(&sel->mutex);
1625
1626 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
1627 /* If it's an optimized shader and its compilation has
1628 * been started but isn't done, use the unoptimized
1629 * shader so as not to cause a stall due to compilation.
1630 */
1631 if (iter->is_optimized) {
1632 memset(&key->opt, 0, sizeof(key->opt));
1633 goto again;
1634 }
1635
1636 util_queue_fence_wait(&iter->ready);
1637 }
1638
1639 if (iter->compilation_failed) {
1640 return -1; /* skip the draw call */
1641 }
1642
1643 state->current = iter;
1644 return 0;
1645 }
1646 }
1647
1648 /* Build a new shader. */
1649 shader = CALLOC_STRUCT(si_shader);
1650 if (!shader) {
1651 mtx_unlock(&sel->mutex);
1652 return -ENOMEM;
1653 }
1654
1655 util_queue_fence_init(&shader->ready);
1656
1657 shader->selector = sel;
1658 shader->key = *key;
1659 shader->compiler_ctx_state = *compiler_state;
1660
1661 /* If this is a merged shader, get the first shader's selector. */
1662 if (sscreen->b.chip_class >= GFX9) {
1663 if (sel->type == PIPE_SHADER_TESS_CTRL)
1664 previous_stage_sel = key->part.tcs.ls;
1665 else if (sel->type == PIPE_SHADER_GEOMETRY)
1666 previous_stage_sel = key->part.gs.es;
1667
1668 /* We need to wait for the previous shader. */
1669 if (previous_stage_sel && thread_index < 0)
1670 util_queue_fence_wait(&previous_stage_sel->ready);
1671 }
1672
1673 /* Compile the main shader part if it doesn't exist. This can happen
1674 * if the initial guess was wrong. */
1675 bool is_pure_monolithic =
1676 sscreen->use_monolithic_shaders ||
1677 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1678
1679 if (!is_pure_monolithic) {
1680 bool ok;
1681
1682 /* Make sure the main shader part is present. This is needed
1683 * for shaders that can be compiled as VS, LS, or ES, and only
1684 * one of them is compiled at creation.
1685 *
1686 * For merged shaders, check that the starting shader's main
1687 * part is present.
1688 */
1689 if (previous_stage_sel) {
1690 struct si_shader_key shader1_key = zeroed;
1691
1692 if (sel->type == PIPE_SHADER_TESS_CTRL)
1693 shader1_key.as_ls = 1;
1694 else if (sel->type == PIPE_SHADER_GEOMETRY)
1695 shader1_key.as_es = 1;
1696 else
1697 assert(0);
1698
1699 mtx_lock(&previous_stage_sel->mutex);
1700 ok = si_check_missing_main_part(sscreen,
1701 previous_stage_sel,
1702 compiler_state, &shader1_key);
1703 mtx_unlock(&previous_stage_sel->mutex);
1704 } else {
1705 ok = si_check_missing_main_part(sscreen, sel,
1706 compiler_state, key);
1707 }
1708 if (!ok) {
1709 FREE(shader);
1710 mtx_unlock(&sel->mutex);
1711 return -ENOMEM; /* skip the draw call */
1712 }
1713 }
1714
1715 /* Keep the reference to the 1st shader of merged shaders, so that
1716 * Gallium can't destroy it before we destroy the 2nd shader.
1717 *
1718 * Set sctx = NULL, because it's unused if we're not releasing
1719 * the shader, and we don't have any sctx here.
1720 */
1721 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
1722 previous_stage_sel);
1723
1724 /* Monolithic-only shaders don't make a distinction between optimized
1725 * and unoptimized. */
1726 shader->is_monolithic =
1727 is_pure_monolithic ||
1728 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1729
1730 shader->is_optimized =
1731 !is_pure_monolithic &&
1732 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1733
1734 /* If it's an optimized shader, compile it asynchronously. */
1735 if (shader->is_optimized &&
1736 !is_pure_monolithic &&
1737 thread_index < 0) {
1738 /* Compile it asynchronously. */
1739 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
1740 shader, &shader->ready,
1741 si_build_shader_variant_low_priority, NULL);
1742
1743 /* Add only after the ready fence was reset, to guard against a
1744 * race with si_bind_XX_shader. */
1745 if (!sel->last_variant) {
1746 sel->first_variant = shader;
1747 sel->last_variant = shader;
1748 } else {
1749 sel->last_variant->next_variant = shader;
1750 sel->last_variant = shader;
1751 }
1752
1753 /* Use the default (unoptimized) shader for now. */
1754 memset(&key->opt, 0, sizeof(key->opt));
1755 mtx_unlock(&sel->mutex);
1756 goto again;
1757 }
1758
1759 /* Reset the fence before adding to the variant list. */
1760 util_queue_fence_reset(&shader->ready);
1761
1762 if (!sel->last_variant) {
1763 sel->first_variant = shader;
1764 sel->last_variant = shader;
1765 } else {
1766 sel->last_variant->next_variant = shader;
1767 sel->last_variant = shader;
1768 }
1769
1770 mtx_unlock(&sel->mutex);
1771
1772 assert(!shader->is_optimized);
1773 si_build_shader_variant(shader, thread_index, false);
1774
1775 util_queue_fence_signal(&shader->ready);
1776
1777 if (!shader->compilation_failed)
1778 state->current = shader;
1779
1780 return shader->compilation_failed ? -1 : 0;
1781 }
1782
1783 static int si_shader_select(struct pipe_context *ctx,
1784 struct si_shader_ctx_state *state,
1785 struct si_compiler_ctx_state *compiler_state)
1786 {
1787 struct si_context *sctx = (struct si_context *)ctx;
1788 struct si_shader_key key;
1789
1790 si_shader_selector_key(ctx, state->cso, &key);
1791 return si_shader_select_with_key(sctx->screen, state, compiler_state,
1792 &key, -1);
1793 }
1794
1795 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1796 bool streamout,
1797 struct si_shader_key *key)
1798 {
1799 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1800
1801 switch (info->processor) {
1802 case PIPE_SHADER_VERTEX:
1803 switch (next_shader) {
1804 case PIPE_SHADER_GEOMETRY:
1805 key->as_es = 1;
1806 break;
1807 case PIPE_SHADER_TESS_CTRL:
1808 case PIPE_SHADER_TESS_EVAL:
1809 key->as_ls = 1;
1810 break;
1811 default:
1812 /* If POSITION isn't written, it can only be a HW VS
1813 * if streamout is used. If streamout isn't used,
1814 * assume that it's a HW LS. (the next shader is TCS)
1815 * This heuristic is needed for separate shader objects.
1816 */
1817 if (!info->writes_position && !streamout)
1818 key->as_ls = 1;
1819 }
1820 break;
1821
1822 case PIPE_SHADER_TESS_EVAL:
1823 if (next_shader == PIPE_SHADER_GEOMETRY ||
1824 !info->writes_position)
1825 key->as_es = 1;
1826 break;
1827 }
1828 }
1829
1830 /**
1831 * Compile the main shader part or the monolithic shader as part of
1832 * si_shader_selector initialization. Since it can be done asynchronously,
1833 * there is no way to report compile failures to applications.
1834 */
1835 static void si_init_shader_selector_async(void *job, int thread_index)
1836 {
1837 struct si_shader_selector *sel = (struct si_shader_selector *)job;
1838 struct si_screen *sscreen = sel->screen;
1839 LLVMTargetMachineRef tm;
1840 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
1841 unsigned i;
1842
1843 if (thread_index >= 0) {
1844 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1845 tm = sscreen->tm[thread_index];
1846 if (!debug->async)
1847 debug = NULL;
1848 } else {
1849 tm = sel->compiler_ctx_state.tm;
1850 }
1851
1852 /* Compile the main shader part for use with a prolog and/or epilog.
1853 * If this fails, the driver will try to compile a monolithic shader
1854 * on demand.
1855 */
1856 if (!sscreen->use_monolithic_shaders) {
1857 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1858 void *tgsi_binary = NULL;
1859
1860 if (!shader) {
1861 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
1862 return;
1863 }
1864
1865 /* We can leave the fence signaled because use of the default
1866 * main part is guarded by the selector's ready fence. */
1867 util_queue_fence_init(&shader->ready);
1868
1869 shader->selector = sel;
1870 si_parse_next_shader_property(&sel->info,
1871 sel->so.num_outputs != 0,
1872 &shader->key);
1873
1874 if (sel->tokens)
1875 tgsi_binary = si_get_tgsi_binary(sel);
1876
1877 /* Try to load the shader from the shader cache. */
1878 mtx_lock(&sscreen->shader_cache_mutex);
1879
1880 if (tgsi_binary &&
1881 si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
1882 mtx_unlock(&sscreen->shader_cache_mutex);
1883 } else {
1884 mtx_unlock(&sscreen->shader_cache_mutex);
1885
1886 /* Compile the shader if it hasn't been loaded from the cache. */
1887 if (si_compile_tgsi_shader(sscreen, tm, shader, false,
1888 debug) != 0) {
1889 FREE(shader);
1890 FREE(tgsi_binary);
1891 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
1892 return;
1893 }
1894
1895 if (tgsi_binary) {
1896 mtx_lock(&sscreen->shader_cache_mutex);
1897 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary, shader, true))
1898 FREE(tgsi_binary);
1899 mtx_unlock(&sscreen->shader_cache_mutex);
1900 }
1901 }
1902
1903 *si_get_main_shader_part(sel, &shader->key) = shader;
1904
1905 /* Unset "outputs_written" flags for outputs converted to
1906 * DEFAULT_VAL, so that later inter-shader optimizations don't
1907 * try to eliminate outputs that don't exist in the final
1908 * shader.
1909 *
1910 * This is only done if non-monolithic shaders are enabled.
1911 */
1912 if ((sel->type == PIPE_SHADER_VERTEX ||
1913 sel->type == PIPE_SHADER_TESS_EVAL) &&
1914 !shader->key.as_ls &&
1915 !shader->key.as_es) {
1916 unsigned i;
1917
1918 for (i = 0; i < sel->info.num_outputs; i++) {
1919 unsigned offset = shader->info.vs_output_param_offset[i];
1920
1921 if (offset <= AC_EXP_PARAM_OFFSET_31)
1922 continue;
1923
1924 unsigned name = sel->info.output_semantic_name[i];
1925 unsigned index = sel->info.output_semantic_index[i];
1926 unsigned id;
1927
1928 switch (name) {
1929 case TGSI_SEMANTIC_GENERIC:
1930 /* don't process indices the function can't handle */
1931 if (index >= SI_MAX_IO_GENERIC)
1932 break;
1933 /* fall through */
1934 default:
1935 id = si_shader_io_get_unique_index(name, index);
1936 sel->outputs_written &= ~(1ull << id);
1937 break;
1938 case TGSI_SEMANTIC_POSITION: /* ignore these */
1939 case TGSI_SEMANTIC_PSIZE:
1940 case TGSI_SEMANTIC_CLIPVERTEX:
1941 case TGSI_SEMANTIC_EDGEFLAG:
1942 break;
1943 }
1944 }
1945 }
1946 }
1947
1948 /* Pre-compilation. */
1949 if (sscreen->b.debug_flags & DBG(PRECOMPILE) &&
1950 /* GFX9 needs LS or ES for compilation, which we don't have here. */
1951 (sscreen->b.chip_class <= VI ||
1952 (sel->type != PIPE_SHADER_TESS_CTRL &&
1953 sel->type != PIPE_SHADER_GEOMETRY))) {
1954 struct si_shader_ctx_state state = {sel};
1955 struct si_shader_key key;
1956
1957 memset(&key, 0, sizeof(key));
1958 si_parse_next_shader_property(&sel->info,
1959 sel->so.num_outputs != 0,
1960 &key);
1961
1962 /* GFX9 doesn't have LS and ES. */
1963 if (sscreen->b.chip_class >= GFX9) {
1964 key.as_ls = 0;
1965 key.as_es = 0;
1966 }
1967
1968 /* Set reasonable defaults, so that the shader key doesn't
1969 * cause any code to be eliminated.
1970 */
1971 switch (sel->type) {
1972 case PIPE_SHADER_TESS_CTRL:
1973 key.part.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
1974 break;
1975 case PIPE_SHADER_FRAGMENT:
1976 key.part.ps.prolog.bc_optimize_for_persp =
1977 sel->info.uses_persp_center &&
1978 sel->info.uses_persp_centroid;
1979 key.part.ps.prolog.bc_optimize_for_linear =
1980 sel->info.uses_linear_center &&
1981 sel->info.uses_linear_centroid;
1982 key.part.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
1983 for (i = 0; i < 8; i++)
1984 if (sel->info.colors_written & (1 << i))
1985 key.part.ps.epilog.spi_shader_col_format |=
1986 V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
1987 break;
1988 }
1989
1990 if (si_shader_select_with_key(sscreen, &state,
1991 &sel->compiler_ctx_state, &key,
1992 thread_index))
1993 fprintf(stderr, "radeonsi: can't create a monolithic shader\n");
1994 }
1995
1996 /* The GS copy shader is always pre-compiled. */
1997 if (sel->type == PIPE_SHADER_GEOMETRY) {
1998 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, tm, sel, debug);
1999 if (!sel->gs_copy_shader) {
2000 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2001 return;
2002 }
2003
2004 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2005 }
2006 }
2007
2008 /* Return descriptor slot usage masks from the given shader info. */
2009 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2010 uint32_t *const_and_shader_buffers,
2011 uint64_t *samplers_and_images)
2012 {
2013 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2014
2015 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2016 num_constbufs = util_last_bit(info->const_buffers_declared);
2017 /* two 8-byte images share one 16-byte slot */
2018 num_images = align(util_last_bit(info->images_declared), 2);
2019 num_samplers = util_last_bit(info->samplers_declared);
2020
2021 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2022 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2023 *const_and_shader_buffers =
2024 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2025
2026 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2027 start = si_get_image_slot(num_images - 1) / 2;
2028 *samplers_and_images =
2029 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2030 }
2031
2032 static void *si_create_shader_selector(struct pipe_context *ctx,
2033 const struct pipe_shader_state *state)
2034 {
2035 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2036 struct si_context *sctx = (struct si_context*)ctx;
2037 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2038 int i;
2039
2040 if (!sel)
2041 return NULL;
2042
2043 pipe_reference_init(&sel->reference, 1);
2044 sel->screen = sscreen;
2045 sel->compiler_ctx_state.tm = sctx->tm;
2046 sel->compiler_ctx_state.debug = sctx->b.debug;
2047 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2048
2049 sel->so = state->stream_output;
2050
2051 if (state->type == PIPE_SHADER_IR_TGSI) {
2052 sel->tokens = tgsi_dup_tokens(state->tokens);
2053 if (!sel->tokens) {
2054 FREE(sel);
2055 return NULL;
2056 }
2057
2058 tgsi_scan_shader(state->tokens, &sel->info);
2059 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2060 } else {
2061 assert(state->type == PIPE_SHADER_IR_NIR);
2062
2063 sel->nir = state->ir.nir;
2064
2065 si_nir_scan_shader(sel->nir, &sel->info);
2066
2067 si_lower_nir(sel);
2068 }
2069
2070 sel->type = sel->info.processor;
2071 p_atomic_inc(&sscreen->b.num_shaders_created);
2072 si_get_active_slot_masks(&sel->info,
2073 &sel->active_const_and_shader_buffers,
2074 &sel->active_samplers_and_images);
2075
2076 /* Record which streamout buffers are enabled. */
2077 for (i = 0; i < sel->so.num_outputs; i++) {
2078 sel->enabled_streamout_buffer_mask |=
2079 (1 << sel->so.output[i].output_buffer) <<
2080 (sel->so.output[i].stream * 4);
2081 }
2082
2083 /* The prolog is a no-op if there are no inputs. */
2084 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2085 sel->info.num_inputs &&
2086 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2087
2088 sel->force_correct_derivs_after_kill =
2089 sel->type == PIPE_SHADER_FRAGMENT &&
2090 sel->info.uses_derivatives &&
2091 sel->info.uses_kill &&
2092 sctx->screen->b.debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2093
2094 /* Set which opcode uses which (i,j) pair. */
2095 if (sel->info.uses_persp_opcode_interp_centroid)
2096 sel->info.uses_persp_centroid = true;
2097
2098 if (sel->info.uses_linear_opcode_interp_centroid)
2099 sel->info.uses_linear_centroid = true;
2100
2101 if (sel->info.uses_persp_opcode_interp_offset ||
2102 sel->info.uses_persp_opcode_interp_sample)
2103 sel->info.uses_persp_center = true;
2104
2105 if (sel->info.uses_linear_opcode_interp_offset ||
2106 sel->info.uses_linear_opcode_interp_sample)
2107 sel->info.uses_linear_center = true;
2108
2109 switch (sel->type) {
2110 case PIPE_SHADER_GEOMETRY:
2111 sel->gs_output_prim =
2112 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2113 sel->gs_max_out_vertices =
2114 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2115 sel->gs_num_invocations =
2116 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2117 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2118 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2119 sel->gs_max_out_vertices;
2120
2121 sel->max_gs_stream = 0;
2122 for (i = 0; i < sel->so.num_outputs; i++)
2123 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2124 sel->so.output[i].stream);
2125
2126 sel->gs_input_verts_per_prim =
2127 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2128 break;
2129
2130 case PIPE_SHADER_TESS_CTRL:
2131 /* Always reserve space for these. */
2132 sel->patch_outputs_written |=
2133 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2134 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2135 /* fall through */
2136 case PIPE_SHADER_VERTEX:
2137 case PIPE_SHADER_TESS_EVAL:
2138 for (i = 0; i < sel->info.num_outputs; i++) {
2139 unsigned name = sel->info.output_semantic_name[i];
2140 unsigned index = sel->info.output_semantic_index[i];
2141
2142 switch (name) {
2143 case TGSI_SEMANTIC_TESSINNER:
2144 case TGSI_SEMANTIC_TESSOUTER:
2145 case TGSI_SEMANTIC_PATCH:
2146 sel->patch_outputs_written |=
2147 1ull << si_shader_io_get_unique_index_patch(name, index);
2148 break;
2149
2150 case TGSI_SEMANTIC_GENERIC:
2151 /* don't process indices the function can't handle */
2152 if (index >= SI_MAX_IO_GENERIC)
2153 break;
2154 /* fall through */
2155 default:
2156 sel->outputs_written |=
2157 1ull << si_shader_io_get_unique_index(name, index);
2158 break;
2159 case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */
2160 case TGSI_SEMANTIC_EDGEFLAG:
2161 break;
2162 }
2163 }
2164 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2165
2166 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2167 * conflicts, i.e. each vertex will start at a different bank.
2168 */
2169 if (sctx->b.chip_class >= GFX9)
2170 sel->esgs_itemsize += 4;
2171 break;
2172
2173 case PIPE_SHADER_FRAGMENT:
2174 for (i = 0; i < sel->info.num_inputs; i++) {
2175 unsigned name = sel->info.input_semantic_name[i];
2176 unsigned index = sel->info.input_semantic_index[i];
2177
2178 switch (name) {
2179 case TGSI_SEMANTIC_GENERIC:
2180 /* don't process indices the function can't handle */
2181 if (index >= SI_MAX_IO_GENERIC)
2182 break;
2183 /* fall through */
2184 default:
2185 sel->inputs_read |=
2186 1ull << si_shader_io_get_unique_index(name, index);
2187 break;
2188 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2189 break;
2190 }
2191 }
2192
2193 for (i = 0; i < 8; i++)
2194 if (sel->info.colors_written & (1 << i))
2195 sel->colors_written_4bit |= 0xf << (4 * i);
2196
2197 for (i = 0; i < sel->info.num_inputs; i++) {
2198 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2199 int index = sel->info.input_semantic_index[i];
2200 sel->color_attr_index[index] = i;
2201 }
2202 }
2203 break;
2204 }
2205
2206 /* PA_CL_VS_OUT_CNTL */
2207 bool misc_vec_ena =
2208 sel->info.writes_psize || sel->info.writes_edgeflag ||
2209 sel->info.writes_layer || sel->info.writes_viewport_index;
2210 sel->pa_cl_vs_out_cntl =
2211 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2212 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2213 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2214 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2215 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2216 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2217 sel->clipdist_mask = sel->info.writes_clipvertex ?
2218 SIX_BITS : sel->info.clipdist_writemask;
2219 sel->culldist_mask = sel->info.culldist_writemask <<
2220 sel->info.num_written_clipdistance;
2221
2222 /* DB_SHADER_CONTROL */
2223 sel->db_shader_control =
2224 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2225 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2226 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2227 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2228
2229 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2230 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2231 sel->db_shader_control |=
2232 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2233 break;
2234 case TGSI_FS_DEPTH_LAYOUT_LESS:
2235 sel->db_shader_control |=
2236 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2237 break;
2238 }
2239
2240 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2241 *
2242 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2243 * --|-----------|------------|------------|--------------------|-------------------|-------------
2244 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2245 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2246 * 2 | false | true | n/a | LateZ | 1 | 0
2247 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2248 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2249 *
2250 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2251 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2252 *
2253 * Don't use ReZ without profiling !!!
2254 *
2255 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2256 * shaders.
2257 */
2258 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2259 /* Cases 3, 4. */
2260 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2261 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2262 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2263 } else if (sel->info.writes_memory) {
2264 /* Case 2. */
2265 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2266 S_02880C_EXEC_ON_HIER_FAIL(1);
2267 } else {
2268 /* Case 1. */
2269 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2270 }
2271
2272 (void) mtx_init(&sel->mutex, mtx_plain);
2273 util_queue_fence_init(&sel->ready);
2274
2275 if ((sctx->b.debug.debug_message && !sctx->b.debug.async) ||
2276 sctx->is_debug ||
2277 si_can_dump_shader(&sscreen->b, sel->info.processor))
2278 si_init_shader_selector_async(sel, -1);
2279 else
2280 util_queue_add_job(&sscreen->shader_compiler_queue, sel,
2281 &sel->ready, si_init_shader_selector_async,
2282 NULL);
2283
2284 return sel;
2285 }
2286
2287 static void si_update_streamout_state(struct si_context *sctx)
2288 {
2289 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2290
2291 if (!shader_with_so)
2292 return;
2293
2294 sctx->streamout.enabled_stream_buffers_mask =
2295 shader_with_so->enabled_streamout_buffer_mask;
2296 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2297 }
2298
2299 static void si_update_clip_regs(struct si_context *sctx,
2300 struct si_shader_selector *old_hw_vs,
2301 struct si_shader *old_hw_vs_variant,
2302 struct si_shader_selector *next_hw_vs,
2303 struct si_shader *next_hw_vs_variant)
2304 {
2305 if (next_hw_vs &&
2306 (!old_hw_vs ||
2307 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2308 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2309 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2310 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2311 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2312 !old_hw_vs_variant ||
2313 !next_hw_vs_variant ||
2314 old_hw_vs_variant->key.opt.clip_disable !=
2315 next_hw_vs_variant->key.opt.clip_disable))
2316 si_mark_atom_dirty(sctx, &sctx->clip_regs);
2317 }
2318
2319 static void si_update_common_shader_state(struct si_context *sctx)
2320 {
2321 sctx->uses_bindless_samplers =
2322 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2323 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2324 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2325 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2326 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2327 sctx->uses_bindless_images =
2328 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2329 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2330 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2331 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2332 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2333 sctx->do_update_shaders = true;
2334 }
2335
2336 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2337 {
2338 struct si_context *sctx = (struct si_context *)ctx;
2339 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2340 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2341 struct si_shader_selector *sel = state;
2342
2343 if (sctx->vs_shader.cso == sel)
2344 return;
2345
2346 sctx->vs_shader.cso = sel;
2347 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2348 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2349
2350 si_update_common_shader_state(sctx);
2351 si_update_vs_viewport_state(sctx);
2352 si_set_active_descriptors_for_shader(sctx, sel);
2353 si_update_streamout_state(sctx);
2354 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2355 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2356 }
2357
2358 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2359 {
2360 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2361 (sctx->tes_shader.cso &&
2362 sctx->tes_shader.cso->info.uses_primid) ||
2363 (sctx->tcs_shader.cso &&
2364 sctx->tcs_shader.cso->info.uses_primid) ||
2365 (sctx->gs_shader.cso &&
2366 sctx->gs_shader.cso->info.uses_primid) ||
2367 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2368 sctx->ps_shader.cso->info.uses_primid);
2369 }
2370
2371 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2372 {
2373 struct si_context *sctx = (struct si_context *)ctx;
2374 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2375 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2376 struct si_shader_selector *sel = state;
2377 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2378
2379 if (sctx->gs_shader.cso == sel)
2380 return;
2381
2382 sctx->gs_shader.cso = sel;
2383 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2384 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2385
2386 si_update_common_shader_state(sctx);
2387 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2388
2389 if (enable_changed) {
2390 si_shader_change_notify(sctx);
2391 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2392 si_update_tess_uses_prim_id(sctx);
2393 }
2394 si_update_vs_viewport_state(sctx);
2395 si_set_active_descriptors_for_shader(sctx, sel);
2396 si_update_streamout_state(sctx);
2397 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2398 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2399 }
2400
2401 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2402 {
2403 struct si_context *sctx = (struct si_context *)ctx;
2404 struct si_shader_selector *sel = state;
2405 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2406
2407 if (sctx->tcs_shader.cso == sel)
2408 return;
2409
2410 sctx->tcs_shader.cso = sel;
2411 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
2412 si_update_tess_uses_prim_id(sctx);
2413
2414 si_update_common_shader_state(sctx);
2415
2416 if (enable_changed)
2417 sctx->last_tcs = NULL; /* invalidate derived tess state */
2418
2419 si_set_active_descriptors_for_shader(sctx, sel);
2420 }
2421
2422 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
2423 {
2424 struct si_context *sctx = (struct si_context *)ctx;
2425 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2426 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2427 struct si_shader_selector *sel = state;
2428 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
2429
2430 if (sctx->tes_shader.cso == sel)
2431 return;
2432
2433 sctx->tes_shader.cso = sel;
2434 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
2435 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
2436 si_update_tess_uses_prim_id(sctx);
2437
2438 si_update_common_shader_state(sctx);
2439 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2440
2441 if (enable_changed) {
2442 si_shader_change_notify(sctx);
2443 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
2444 }
2445 si_update_vs_viewport_state(sctx);
2446 si_set_active_descriptors_for_shader(sctx, sel);
2447 si_update_streamout_state(sctx);
2448 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2449 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2450 }
2451
2452 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2453 {
2454 struct si_context *sctx = (struct si_context *)ctx;
2455 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
2456 struct si_shader_selector *sel = state;
2457
2458 /* skip if supplied shader is one already in use */
2459 if (old_sel == sel)
2460 return;
2461
2462 sctx->ps_shader.cso = sel;
2463 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
2464
2465 si_update_common_shader_state(sctx);
2466 if (sel) {
2467 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2468 si_update_tess_uses_prim_id(sctx);
2469
2470 if (!old_sel ||
2471 old_sel->info.colors_written != sel->info.colors_written)
2472 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2473
2474 if (sctx->screen->has_out_of_order_rast &&
2475 (!old_sel ||
2476 old_sel->info.writes_memory != sel->info.writes_memory ||
2477 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
2478 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
2479 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2480 }
2481 si_set_active_descriptors_for_shader(sctx, sel);
2482 }
2483
2484 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
2485 {
2486 if (shader->is_optimized) {
2487 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
2488 &shader->ready);
2489 }
2490
2491 util_queue_fence_destroy(&shader->ready);
2492
2493 if (shader->pm4) {
2494 switch (shader->selector->type) {
2495 case PIPE_SHADER_VERTEX:
2496 if (shader->key.as_ls) {
2497 assert(sctx->b.chip_class <= VI);
2498 si_pm4_delete_state(sctx, ls, shader->pm4);
2499 } else if (shader->key.as_es) {
2500 assert(sctx->b.chip_class <= VI);
2501 si_pm4_delete_state(sctx, es, shader->pm4);
2502 } else {
2503 si_pm4_delete_state(sctx, vs, shader->pm4);
2504 }
2505 break;
2506 case PIPE_SHADER_TESS_CTRL:
2507 si_pm4_delete_state(sctx, hs, shader->pm4);
2508 break;
2509 case PIPE_SHADER_TESS_EVAL:
2510 if (shader->key.as_es) {
2511 assert(sctx->b.chip_class <= VI);
2512 si_pm4_delete_state(sctx, es, shader->pm4);
2513 } else {
2514 si_pm4_delete_state(sctx, vs, shader->pm4);
2515 }
2516 break;
2517 case PIPE_SHADER_GEOMETRY:
2518 if (shader->is_gs_copy_shader)
2519 si_pm4_delete_state(sctx, vs, shader->pm4);
2520 else
2521 si_pm4_delete_state(sctx, gs, shader->pm4);
2522 break;
2523 case PIPE_SHADER_FRAGMENT:
2524 si_pm4_delete_state(sctx, ps, shader->pm4);
2525 break;
2526 }
2527 }
2528
2529 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
2530 si_shader_destroy(shader);
2531 free(shader);
2532 }
2533
2534 void si_destroy_shader_selector(struct si_context *sctx,
2535 struct si_shader_selector *sel)
2536 {
2537 struct si_shader *p = sel->first_variant, *c;
2538 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
2539 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
2540 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
2541 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
2542 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
2543 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
2544 };
2545
2546 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
2547
2548 if (current_shader[sel->type]->cso == sel) {
2549 current_shader[sel->type]->cso = NULL;
2550 current_shader[sel->type]->current = NULL;
2551 }
2552
2553 while (p) {
2554 c = p->next_variant;
2555 si_delete_shader(sctx, p);
2556 p = c;
2557 }
2558
2559 if (sel->main_shader_part)
2560 si_delete_shader(sctx, sel->main_shader_part);
2561 if (sel->main_shader_part_ls)
2562 si_delete_shader(sctx, sel->main_shader_part_ls);
2563 if (sel->main_shader_part_es)
2564 si_delete_shader(sctx, sel->main_shader_part_es);
2565 if (sel->gs_copy_shader)
2566 si_delete_shader(sctx, sel->gs_copy_shader);
2567
2568 util_queue_fence_destroy(&sel->ready);
2569 mtx_destroy(&sel->mutex);
2570 free(sel->tokens);
2571 ralloc_free(sel->nir);
2572 free(sel);
2573 }
2574
2575 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
2576 {
2577 struct si_context *sctx = (struct si_context *)ctx;
2578 struct si_shader_selector *sel = (struct si_shader_selector *)state;
2579
2580 si_shader_selector_reference(sctx, &sel, NULL);
2581 }
2582
2583 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
2584 struct si_shader *vs, unsigned name,
2585 unsigned index, unsigned interpolate)
2586 {
2587 struct tgsi_shader_info *vsinfo = &vs->selector->info;
2588 unsigned j, offset, ps_input_cntl = 0;
2589
2590 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
2591 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
2592 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2593
2594 if (name == TGSI_SEMANTIC_PCOORD ||
2595 (name == TGSI_SEMANTIC_TEXCOORD &&
2596 sctx->sprite_coord_enable & (1 << index))) {
2597 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
2598 }
2599
2600 for (j = 0; j < vsinfo->num_outputs; j++) {
2601 if (name == vsinfo->output_semantic_name[j] &&
2602 index == vsinfo->output_semantic_index[j]) {
2603 offset = vs->info.vs_output_param_offset[j];
2604
2605 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2606 /* The input is loaded from parameter memory. */
2607 ps_input_cntl |= S_028644_OFFSET(offset);
2608 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2609 if (offset == AC_EXP_PARAM_UNDEFINED) {
2610 /* This can happen with depth-only rendering. */
2611 offset = 0;
2612 } else {
2613 /* The input is a DEFAULT_VAL constant. */
2614 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2615 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2616 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2617 }
2618
2619 ps_input_cntl = S_028644_OFFSET(0x20) |
2620 S_028644_DEFAULT_VAL(offset);
2621 }
2622 break;
2623 }
2624 }
2625
2626 if (name == TGSI_SEMANTIC_PRIMID)
2627 /* PrimID is written after the last output. */
2628 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
2629 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2630 /* No corresponding output found, load defaults into input.
2631 * Don't set any other bits.
2632 * (FLAT_SHADE=1 completely changes behavior) */
2633 ps_input_cntl = S_028644_OFFSET(0x20);
2634 /* D3D 9 behaviour. GL is undefined */
2635 if (name == TGSI_SEMANTIC_COLOR && index == 0)
2636 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
2637 }
2638 return ps_input_cntl;
2639 }
2640
2641 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
2642 {
2643 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2644 struct si_shader *ps = sctx->ps_shader.current;
2645 struct si_shader *vs = si_get_vs_state(sctx);
2646 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
2647 unsigned i, num_interp, num_written = 0, bcol_interp[2];
2648
2649 if (!ps || !ps->selector->info.num_inputs)
2650 return;
2651
2652 num_interp = si_get_ps_num_interp(ps);
2653 assert(num_interp > 0);
2654 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
2655
2656 for (i = 0; i < psinfo->num_inputs; i++) {
2657 unsigned name = psinfo->input_semantic_name[i];
2658 unsigned index = psinfo->input_semantic_index[i];
2659 unsigned interpolate = psinfo->input_interpolate[i];
2660
2661 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
2662 interpolate));
2663 num_written++;
2664
2665 if (name == TGSI_SEMANTIC_COLOR) {
2666 assert(index < ARRAY_SIZE(bcol_interp));
2667 bcol_interp[index] = interpolate;
2668 }
2669 }
2670
2671 if (ps->key.part.ps.prolog.color_two_side) {
2672 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
2673
2674 for (i = 0; i < 2; i++) {
2675 if (!(psinfo->colors_read & (0xf << (i * 4))))
2676 continue;
2677
2678 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
2679 i, bcol_interp[i]));
2680 num_written++;
2681 }
2682 }
2683 assert(num_interp == num_written);
2684 }
2685
2686 /**
2687 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2688 */
2689 static void si_init_config_add_vgt_flush(struct si_context *sctx)
2690 {
2691 if (sctx->init_config_has_vgt_flush)
2692 return;
2693
2694 /* Done by Vulkan before VGT_FLUSH. */
2695 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2696 si_pm4_cmd_add(sctx->init_config,
2697 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2698 si_pm4_cmd_end(sctx->init_config, false);
2699
2700 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2701 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2702 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2703 si_pm4_cmd_end(sctx->init_config, false);
2704 sctx->init_config_has_vgt_flush = true;
2705 }
2706
2707 /* Initialize state related to ESGS / GSVS ring buffers */
2708 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2709 {
2710 struct si_shader_selector *es =
2711 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2712 struct si_shader_selector *gs = sctx->gs_shader.cso;
2713 struct si_pm4_state *pm4;
2714
2715 /* Chip constants. */
2716 unsigned num_se = sctx->screen->b.info.max_se;
2717 unsigned wave_size = 64;
2718 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2719 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2720 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2721 */
2722 unsigned gs_vertex_reuse = (sctx->b.chip_class >= VI ? 32 : 16) * num_se;
2723 unsigned alignment = 256 * num_se;
2724 /* The maximum size is 63.999 MB per SE. */
2725 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2726
2727 /* Calculate the minimum size. */
2728 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
2729 wave_size, alignment);
2730
2731 /* These are recommended sizes, not minimum sizes. */
2732 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2733 es->esgs_itemsize * gs->gs_input_verts_per_prim;
2734 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2735 gs->max_gsvs_emit_size;
2736
2737 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2738 esgs_ring_size = align(esgs_ring_size, alignment);
2739 gsvs_ring_size = align(gsvs_ring_size, alignment);
2740
2741 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2742 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2743
2744 /* Some rings don't have to be allocated if shaders don't use them.
2745 * (e.g. no varyings between ES and GS or GS and VS)
2746 *
2747 * GFX9 doesn't have the ESGS ring.
2748 */
2749 bool update_esgs = sctx->b.chip_class <= VI &&
2750 esgs_ring_size &&
2751 (!sctx->esgs_ring ||
2752 sctx->esgs_ring->width0 < esgs_ring_size);
2753 bool update_gsvs = gsvs_ring_size &&
2754 (!sctx->gsvs_ring ||
2755 sctx->gsvs_ring->width0 < gsvs_ring_size);
2756
2757 if (!update_esgs && !update_gsvs)
2758 return true;
2759
2760 if (update_esgs) {
2761 pipe_resource_reference(&sctx->esgs_ring, NULL);
2762 sctx->esgs_ring =
2763 si_aligned_buffer_create(sctx->b.b.screen,
2764 R600_RESOURCE_FLAG_UNMAPPABLE,
2765 PIPE_USAGE_DEFAULT,
2766 esgs_ring_size, alignment);
2767 if (!sctx->esgs_ring)
2768 return false;
2769 }
2770
2771 if (update_gsvs) {
2772 pipe_resource_reference(&sctx->gsvs_ring, NULL);
2773 sctx->gsvs_ring =
2774 si_aligned_buffer_create(sctx->b.b.screen,
2775 R600_RESOURCE_FLAG_UNMAPPABLE,
2776 PIPE_USAGE_DEFAULT,
2777 gsvs_ring_size, alignment);
2778 if (!sctx->gsvs_ring)
2779 return false;
2780 }
2781
2782 /* Create the "init_config_gs_rings" state. */
2783 pm4 = CALLOC_STRUCT(si_pm4_state);
2784 if (!pm4)
2785 return false;
2786
2787 if (sctx->b.chip_class >= CIK) {
2788 if (sctx->esgs_ring) {
2789 assert(sctx->b.chip_class <= VI);
2790 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2791 sctx->esgs_ring->width0 / 256);
2792 }
2793 if (sctx->gsvs_ring)
2794 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2795 sctx->gsvs_ring->width0 / 256);
2796 } else {
2797 if (sctx->esgs_ring)
2798 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2799 sctx->esgs_ring->width0 / 256);
2800 if (sctx->gsvs_ring)
2801 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2802 sctx->gsvs_ring->width0 / 256);
2803 }
2804
2805 /* Set the state. */
2806 if (sctx->init_config_gs_rings)
2807 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
2808 sctx->init_config_gs_rings = pm4;
2809
2810 if (!sctx->init_config_has_vgt_flush) {
2811 si_init_config_add_vgt_flush(sctx);
2812 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2813 }
2814
2815 /* Flush the context to re-emit both init_config states. */
2816 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2817 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2818
2819 /* Set ring bindings. */
2820 if (sctx->esgs_ring) {
2821 assert(sctx->b.chip_class <= VI);
2822 si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
2823 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2824 true, true, 4, 64, 0);
2825 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
2826 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2827 false, false, 0, 0, 0);
2828 }
2829 if (sctx->gsvs_ring) {
2830 si_set_ring_buffer(&sctx->b.b, SI_RING_GSVS,
2831 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
2832 false, false, 0, 0, 0);
2833 }
2834
2835 return true;
2836 }
2837
2838 static void si_shader_lock(struct si_shader *shader)
2839 {
2840 mtx_lock(&shader->selector->mutex);
2841 if (shader->previous_stage_sel) {
2842 assert(shader->previous_stage_sel != shader->selector);
2843 mtx_lock(&shader->previous_stage_sel->mutex);
2844 }
2845 }
2846
2847 static void si_shader_unlock(struct si_shader *shader)
2848 {
2849 if (shader->previous_stage_sel)
2850 mtx_unlock(&shader->previous_stage_sel->mutex);
2851 mtx_unlock(&shader->selector->mutex);
2852 }
2853
2854 /**
2855 * @returns 1 if \p sel has been updated to use a new scratch buffer
2856 * 0 if not
2857 * < 0 if there was a failure
2858 */
2859 static int si_update_scratch_buffer(struct si_context *sctx,
2860 struct si_shader *shader)
2861 {
2862 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
2863 int r;
2864
2865 if (!shader)
2866 return 0;
2867
2868 /* This shader doesn't need a scratch buffer */
2869 if (shader->config.scratch_bytes_per_wave == 0)
2870 return 0;
2871
2872 /* Prevent race conditions when updating:
2873 * - si_shader::scratch_bo
2874 * - si_shader::binary::code
2875 * - si_shader::previous_stage::binary::code.
2876 */
2877 si_shader_lock(shader);
2878
2879 /* This shader is already configured to use the current
2880 * scratch buffer. */
2881 if (shader->scratch_bo == sctx->scratch_buffer) {
2882 si_shader_unlock(shader);
2883 return 0;
2884 }
2885
2886 assert(sctx->scratch_buffer);
2887
2888 if (shader->previous_stage)
2889 si_shader_apply_scratch_relocs(shader->previous_stage, scratch_va);
2890
2891 si_shader_apply_scratch_relocs(shader, scratch_va);
2892
2893 /* Replace the shader bo with a new bo that has the relocs applied. */
2894 r = si_shader_binary_upload(sctx->screen, shader);
2895 if (r) {
2896 si_shader_unlock(shader);
2897 return r;
2898 }
2899
2900 /* Update the shader state to use the new shader bo. */
2901 si_shader_init_pm4_state(sctx->screen, shader);
2902
2903 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
2904
2905 si_shader_unlock(shader);
2906 return 1;
2907 }
2908
2909 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
2910 {
2911 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
2912 }
2913
2914 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
2915 {
2916 return shader ? shader->config.scratch_bytes_per_wave : 0;
2917 }
2918
2919 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
2920 {
2921 if (!sctx->tes_shader.cso)
2922 return NULL; /* tessellation disabled */
2923
2924 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
2925 sctx->fixed_func_tcs_shader.current;
2926 }
2927
2928 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
2929 {
2930 unsigned bytes = 0;
2931
2932 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
2933 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
2934 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
2935 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
2936
2937 if (sctx->tes_shader.cso) {
2938 struct si_shader *tcs = si_get_tcs_current(sctx);
2939
2940 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
2941 }
2942 return bytes;
2943 }
2944
2945 static bool si_update_scratch_relocs(struct si_context *sctx)
2946 {
2947 struct si_shader *tcs = si_get_tcs_current(sctx);
2948 int r;
2949
2950 /* Update the shaders, so that they are using the latest scratch.
2951 * The scratch buffer may have been changed since these shaders were
2952 * last used, so we still need to try to update them, even if they
2953 * require scratch buffers smaller than the current size.
2954 */
2955 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
2956 if (r < 0)
2957 return false;
2958 if (r == 1)
2959 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2960
2961 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
2962 if (r < 0)
2963 return false;
2964 if (r == 1)
2965 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2966
2967 r = si_update_scratch_buffer(sctx, tcs);
2968 if (r < 0)
2969 return false;
2970 if (r == 1)
2971 si_pm4_bind_state(sctx, hs, tcs->pm4);
2972
2973 /* VS can be bound as LS, ES, or VS. */
2974 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
2975 if (r < 0)
2976 return false;
2977 if (r == 1) {
2978 if (sctx->tes_shader.current)
2979 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2980 else if (sctx->gs_shader.current)
2981 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2982 else
2983 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2984 }
2985
2986 /* TES can be bound as ES or VS. */
2987 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
2988 if (r < 0)
2989 return false;
2990 if (r == 1) {
2991 if (sctx->gs_shader.current)
2992 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2993 else
2994 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2995 }
2996
2997 return true;
2998 }
2999
3000 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3001 {
3002 unsigned current_scratch_buffer_size =
3003 si_get_current_scratch_buffer_size(sctx);
3004 unsigned scratch_bytes_per_wave =
3005 si_get_max_scratch_bytes_per_wave(sctx);
3006 unsigned scratch_needed_size = scratch_bytes_per_wave *
3007 sctx->scratch_waves;
3008 unsigned spi_tmpring_size;
3009
3010 if (scratch_needed_size > 0) {
3011 if (scratch_needed_size > current_scratch_buffer_size) {
3012 /* Create a bigger scratch buffer */
3013 r600_resource_reference(&sctx->scratch_buffer, NULL);
3014
3015 sctx->scratch_buffer = (struct r600_resource*)
3016 si_aligned_buffer_create(&sctx->screen->b.b,
3017 R600_RESOURCE_FLAG_UNMAPPABLE,
3018 PIPE_USAGE_DEFAULT,
3019 scratch_needed_size, 256);
3020 if (!sctx->scratch_buffer)
3021 return false;
3022
3023 si_mark_atom_dirty(sctx, &sctx->scratch_state);
3024 r600_context_add_resource_size(&sctx->b.b,
3025 &sctx->scratch_buffer->b.b);
3026 }
3027
3028 if (!si_update_scratch_relocs(sctx))
3029 return false;
3030 }
3031
3032 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3033 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3034 "scratch size should already be aligned correctly.");
3035
3036 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3037 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3038 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3039 sctx->spi_tmpring_size = spi_tmpring_size;
3040 si_mark_atom_dirty(sctx, &sctx->scratch_state);
3041 }
3042 return true;
3043 }
3044
3045 static void si_init_tess_factor_ring(struct si_context *sctx)
3046 {
3047 bool double_offchip_buffers = sctx->b.chip_class >= CIK &&
3048 sctx->b.family != CHIP_CARRIZO &&
3049 sctx->b.family != CHIP_STONEY;
3050 /* This must be one less than the maximum number due to a hw limitation.
3051 * Various hardware bugs in SI, CIK, and GFX9 need this.
3052 */
3053 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
3054 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
3055 sctx->screen->b.info.max_se;
3056 unsigned offchip_granularity;
3057
3058 switch (sctx->screen->tess_offchip_block_dw_size) {
3059 default:
3060 assert(0);
3061 /* fall through */
3062 case 8192:
3063 offchip_granularity = V_03093C_X_8K_DWORDS;
3064 break;
3065 case 4096:
3066 offchip_granularity = V_03093C_X_4K_DWORDS;
3067 break;
3068 }
3069
3070 assert(!sctx->tf_ring);
3071 /* Use 64K alignment for both rings, so that we can pass the address
3072 * to shaders as one SGPR containing bits [16:47].
3073 */
3074 sctx->tf_ring = si_aligned_buffer_create(sctx->b.b.screen,
3075 R600_RESOURCE_FLAG_UNMAPPABLE,
3076 PIPE_USAGE_DEFAULT,
3077 32768 * sctx->screen->b.info.max_se,
3078 64 * 1024);
3079 if (!sctx->tf_ring)
3080 return;
3081
3082 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
3083
3084 sctx->tess_offchip_ring =
3085 si_aligned_buffer_create(sctx->b.b.screen,
3086 R600_RESOURCE_FLAG_UNMAPPABLE,
3087 PIPE_USAGE_DEFAULT,
3088 max_offchip_buffers *
3089 sctx->screen->tess_offchip_block_dw_size * 4,
3090 64 * 1024);
3091 if (!sctx->tess_offchip_ring)
3092 return;
3093
3094 si_init_config_add_vgt_flush(sctx);
3095
3096 uint64_t offchip_va = r600_resource(sctx->tess_offchip_ring)->gpu_address;
3097 uint64_t factor_va = r600_resource(sctx->tf_ring)->gpu_address;
3098 assert((offchip_va & 0xffff) == 0);
3099 assert((factor_va & 0xffff) == 0);
3100
3101 si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_offchip_ring),
3102 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3103 si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tf_ring),
3104 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3105
3106 /* Append these registers to the init config state. */
3107 if (sctx->b.chip_class >= CIK) {
3108 if (sctx->b.chip_class >= VI)
3109 --max_offchip_buffers;
3110
3111 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3112 S_030938_SIZE(sctx->tf_ring->width0 / 4));
3113 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3114 factor_va >> 8);
3115 if (sctx->b.chip_class >= GFX9)
3116 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3117 factor_va >> 40);
3118 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3119 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
3120 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity));
3121 } else {
3122 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
3123 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3124 S_008988_SIZE(sctx->tf_ring->width0 / 4));
3125 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3126 factor_va >> 8);
3127 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3128 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers));
3129 }
3130
3131 if (sctx->b.chip_class >= GFX9) {
3132 si_pm4_set_reg(sctx->init_config,
3133 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
3134 GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K * 4,
3135 offchip_va >> 16);
3136 si_pm4_set_reg(sctx->init_config,
3137 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
3138 GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K * 4,
3139 factor_va >> 16);
3140 } else {
3141 si_pm4_set_reg(sctx->init_config,
3142 R_00B430_SPI_SHADER_USER_DATA_HS_0 +
3143 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K * 4,
3144 offchip_va >> 16);
3145 si_pm4_set_reg(sctx->init_config,
3146 R_00B430_SPI_SHADER_USER_DATA_HS_0 +
3147 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K * 4,
3148 factor_va >> 16);
3149 }
3150
3151 /* Flush the context to re-emit the init_config state.
3152 * This is done only once in a lifetime of a context.
3153 */
3154 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3155 sctx->b.initial_gfx_cs_size = 0; /* force flush */
3156 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
3157 }
3158
3159 /**
3160 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
3161 * VS passes its outputs to TES directly, so the fixed-function shader only
3162 * has to write TESSOUTER and TESSINNER.
3163 */
3164 static void si_generate_fixed_func_tcs(struct si_context *sctx)
3165 {
3166 struct ureg_src outer, inner;
3167 struct ureg_dst tessouter, tessinner;
3168 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
3169
3170 if (!ureg)
3171 return; /* if we get here, we're screwed */
3172
3173 assert(!sctx->fixed_func_tcs_shader.cso);
3174
3175 outer = ureg_DECL_system_value(ureg,
3176 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
3177 inner = ureg_DECL_system_value(ureg,
3178 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
3179
3180 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
3181 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
3182
3183 ureg_MOV(ureg, tessouter, outer);
3184 ureg_MOV(ureg, tessinner, inner);
3185 ureg_END(ureg);
3186
3187 sctx->fixed_func_tcs_shader.cso =
3188 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
3189 }
3190
3191 static void si_update_vgt_shader_config(struct si_context *sctx)
3192 {
3193 /* Calculate the index of the config.
3194 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3195 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
3196 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
3197
3198 if (!*pm4) {
3199 uint32_t stages = 0;
3200
3201 *pm4 = CALLOC_STRUCT(si_pm4_state);
3202
3203 if (sctx->tes_shader.cso) {
3204 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3205 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3206
3207 if (sctx->gs_shader.cso)
3208 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3209 S_028B54_GS_EN(1) |
3210 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3211 else
3212 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3213 } else if (sctx->gs_shader.cso) {
3214 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3215 S_028B54_GS_EN(1) |
3216 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3217 }
3218
3219 if (sctx->b.chip_class >= GFX9)
3220 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3221
3222 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3223 }
3224 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3225 }
3226
3227 bool si_update_shaders(struct si_context *sctx)
3228 {
3229 struct pipe_context *ctx = (struct pipe_context*)sctx;
3230 struct si_compiler_ctx_state compiler_state;
3231 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3232 struct si_shader *old_vs = si_get_vs_state(sctx);
3233 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3234 struct si_shader *old_ps = sctx->ps_shader.current;
3235 unsigned old_spi_shader_col_format =
3236 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3237 int r;
3238
3239 compiler_state.tm = sctx->tm;
3240 compiler_state.debug = sctx->b.debug;
3241 compiler_state.is_debug_context = sctx->is_debug;
3242
3243 /* Update stages before GS. */
3244 if (sctx->tes_shader.cso) {
3245 if (!sctx->tf_ring) {
3246 si_init_tess_factor_ring(sctx);
3247 if (!sctx->tf_ring)
3248 return false;
3249 }
3250
3251 /* VS as LS */
3252 if (sctx->b.chip_class <= VI) {
3253 r = si_shader_select(ctx, &sctx->vs_shader,
3254 &compiler_state);
3255 if (r)
3256 return false;
3257 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3258 }
3259
3260 if (sctx->tcs_shader.cso) {
3261 r = si_shader_select(ctx, &sctx->tcs_shader,
3262 &compiler_state);
3263 if (r)
3264 return false;
3265 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3266 } else {
3267 if (!sctx->fixed_func_tcs_shader.cso) {
3268 si_generate_fixed_func_tcs(sctx);
3269 if (!sctx->fixed_func_tcs_shader.cso)
3270 return false;
3271 }
3272
3273 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3274 &compiler_state);
3275 if (r)
3276 return false;
3277 si_pm4_bind_state(sctx, hs,
3278 sctx->fixed_func_tcs_shader.current->pm4);
3279 }
3280
3281 if (sctx->gs_shader.cso) {
3282 /* TES as ES */
3283 if (sctx->b.chip_class <= VI) {
3284 r = si_shader_select(ctx, &sctx->tes_shader,
3285 &compiler_state);
3286 if (r)
3287 return false;
3288 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3289 }
3290 } else {
3291 /* TES as VS */
3292 r = si_shader_select(ctx, &sctx->tes_shader,
3293 &compiler_state);
3294 if (r)
3295 return false;
3296 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3297 }
3298 } else if (sctx->gs_shader.cso) {
3299 if (sctx->b.chip_class <= VI) {
3300 /* VS as ES */
3301 r = si_shader_select(ctx, &sctx->vs_shader,
3302 &compiler_state);
3303 if (r)
3304 return false;
3305 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3306
3307 si_pm4_bind_state(sctx, ls, NULL);
3308 si_pm4_bind_state(sctx, hs, NULL);
3309 }
3310 } else {
3311 /* VS as VS */
3312 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
3313 if (r)
3314 return false;
3315 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3316 si_pm4_bind_state(sctx, ls, NULL);
3317 si_pm4_bind_state(sctx, hs, NULL);
3318 }
3319
3320 /* Update GS. */
3321 if (sctx->gs_shader.cso) {
3322 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
3323 if (r)
3324 return false;
3325 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3326 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3327
3328 if (!si_update_gs_ring_buffers(sctx))
3329 return false;
3330 } else {
3331 si_pm4_bind_state(sctx, gs, NULL);
3332 if (sctx->b.chip_class <= VI)
3333 si_pm4_bind_state(sctx, es, NULL);
3334 }
3335
3336 si_update_vgt_shader_config(sctx);
3337
3338 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3339 si_mark_atom_dirty(sctx, &sctx->clip_regs);
3340
3341 if (sctx->ps_shader.cso) {
3342 unsigned db_shader_control;
3343
3344 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
3345 if (r)
3346 return false;
3347 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3348
3349 db_shader_control =
3350 sctx->ps_shader.cso->db_shader_control |
3351 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3352
3353 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3354 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3355 sctx->flatshade != rs->flatshade) {
3356 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3357 sctx->flatshade = rs->flatshade;
3358 si_mark_atom_dirty(sctx, &sctx->spi_map);
3359 }
3360
3361 if (sctx->screen->b.rbplus_allowed &&
3362 si_pm4_state_changed(sctx, ps) &&
3363 (!old_ps ||
3364 old_spi_shader_col_format !=
3365 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3366 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
3367
3368 if (sctx->ps_db_shader_control != db_shader_control) {
3369 sctx->ps_db_shader_control = db_shader_control;
3370 si_mark_atom_dirty(sctx, &sctx->db_render_state);
3371 if (sctx->screen->dpbb_allowed)
3372 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
3373 }
3374
3375 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3376 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3377 si_mark_atom_dirty(sctx, &sctx->msaa_config);
3378
3379 if (sctx->b.chip_class == SI)
3380 si_mark_atom_dirty(sctx, &sctx->db_render_state);
3381
3382 if (sctx->framebuffer.nr_samples <= 1)
3383 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
3384 }
3385 }
3386
3387 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3388 si_pm4_state_enabled_and_changed(sctx, hs) ||
3389 si_pm4_state_enabled_and_changed(sctx, es) ||
3390 si_pm4_state_enabled_and_changed(sctx, gs) ||
3391 si_pm4_state_enabled_and_changed(sctx, vs) ||
3392 si_pm4_state_enabled_and_changed(sctx, ps)) {
3393 if (!si_update_spi_tmpring_size(sctx))
3394 return false;
3395 }
3396
3397 if (sctx->b.chip_class >= CIK) {
3398 if (si_pm4_state_enabled_and_changed(sctx, ls))
3399 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3400 else if (!sctx->queued.named.ls)
3401 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3402
3403 if (si_pm4_state_enabled_and_changed(sctx, hs))
3404 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3405 else if (!sctx->queued.named.hs)
3406 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3407
3408 if (si_pm4_state_enabled_and_changed(sctx, es))
3409 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
3410 else if (!sctx->queued.named.es)
3411 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
3412
3413 if (si_pm4_state_enabled_and_changed(sctx, gs))
3414 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
3415 else if (!sctx->queued.named.gs)
3416 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
3417
3418 if (si_pm4_state_enabled_and_changed(sctx, vs))
3419 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
3420 else if (!sctx->queued.named.vs)
3421 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
3422
3423 if (si_pm4_state_enabled_and_changed(sctx, ps))
3424 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
3425 else if (!sctx->queued.named.ps)
3426 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
3427 }
3428
3429 sctx->do_update_shaders = false;
3430 return true;
3431 }
3432
3433 static void si_emit_scratch_state(struct si_context *sctx,
3434 struct r600_atom *atom)
3435 {
3436 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3437
3438 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3439 sctx->spi_tmpring_size);
3440
3441 if (sctx->scratch_buffer) {
3442 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
3443 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3444 RADEON_PRIO_SCRATCH_BUFFER);
3445 }
3446 }
3447
3448 void *si_get_blit_vs(struct si_context *sctx, enum blitter_attrib_type type,
3449 unsigned num_layers)
3450 {
3451 struct pipe_context *pipe = &sctx->b.b;
3452 unsigned vs_blit_property;
3453 void **vs;
3454
3455 switch (type) {
3456 case UTIL_BLITTER_ATTRIB_NONE:
3457 vs = num_layers > 1 ? &sctx->vs_blit_pos_layered :
3458 &sctx->vs_blit_pos;
3459 vs_blit_property = SI_VS_BLIT_SGPRS_POS;
3460 break;
3461 case UTIL_BLITTER_ATTRIB_COLOR:
3462 vs = num_layers > 1 ? &sctx->vs_blit_color_layered :
3463 &sctx->vs_blit_color;
3464 vs_blit_property = SI_VS_BLIT_SGPRS_POS_COLOR;
3465 break;
3466 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
3467 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
3468 assert(num_layers == 1);
3469 vs = &sctx->vs_blit_texcoord;
3470 vs_blit_property = SI_VS_BLIT_SGPRS_POS_TEXCOORD;
3471 break;
3472 default:
3473 assert(0);
3474 return NULL;
3475 }
3476 if (*vs)
3477 return *vs;
3478
3479 struct ureg_program *ureg = ureg_create(PIPE_SHADER_VERTEX);
3480 if (!ureg)
3481 return NULL;
3482
3483 /* Tell the shader to load VS inputs from SGPRs: */
3484 ureg_property(ureg, TGSI_PROPERTY_VS_BLIT_SGPRS, vs_blit_property);
3485 ureg_property(ureg, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION, true);
3486
3487 /* This is just a pass-through shader with 1-3 MOV instructions. */
3488 ureg_MOV(ureg,
3489 ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0),
3490 ureg_DECL_vs_input(ureg, 0));
3491
3492 if (type != UTIL_BLITTER_ATTRIB_NONE) {
3493 ureg_MOV(ureg,
3494 ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, 0),
3495 ureg_DECL_vs_input(ureg, 1));
3496 }
3497
3498 if (num_layers > 1) {
3499 struct ureg_src instance_id =
3500 ureg_DECL_system_value(ureg, TGSI_SEMANTIC_INSTANCEID, 0);
3501 struct ureg_dst layer =
3502 ureg_DECL_output(ureg, TGSI_SEMANTIC_LAYER, 0);
3503
3504 ureg_MOV(ureg, ureg_writemask(layer, TGSI_WRITEMASK_X),
3505 ureg_scalar(instance_id, TGSI_SWIZZLE_X));
3506 }
3507 ureg_END(ureg);
3508
3509 *vs = ureg_create_shader_and_destroy(ureg, pipe);
3510 return *vs;
3511 }
3512
3513 void si_init_shader_functions(struct si_context *sctx)
3514 {
3515 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
3516 si_init_atom(sctx, &sctx->scratch_state, &sctx->atoms.s.scratch_state,
3517 si_emit_scratch_state);
3518
3519 sctx->b.b.create_vs_state = si_create_shader_selector;
3520 sctx->b.b.create_tcs_state = si_create_shader_selector;
3521 sctx->b.b.create_tes_state = si_create_shader_selector;
3522 sctx->b.b.create_gs_state = si_create_shader_selector;
3523 sctx->b.b.create_fs_state = si_create_shader_selector;
3524
3525 sctx->b.b.bind_vs_state = si_bind_vs_shader;
3526 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
3527 sctx->b.b.bind_tes_state = si_bind_tes_shader;
3528 sctx->b.b.bind_gs_state = si_bind_gs_shader;
3529 sctx->b.b.bind_fs_state = si_bind_ps_shader;
3530
3531 sctx->b.b.delete_vs_state = si_delete_shader_selector;
3532 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
3533 sctx->b.b.delete_tes_state = si_delete_shader_selector;
3534 sctx->b.b.delete_gs_state = si_delete_shader_selector;
3535 sctx->b.b.delete_fs_state = si_delete_shader_selector;
3536 }