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radeonsi/gfx10: implement si_shader_ps
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
45 * size as integer.
46 */
47 void *si_get_ir_binary(struct si_shader_selector *sel)
48 {
49 struct blob blob;
50 unsigned ir_size;
51 void *ir_binary;
52
53 if (sel->tokens) {
54 ir_binary = sel->tokens;
55 ir_size = tgsi_num_tokens(sel->tokens) *
56 sizeof(struct tgsi_token);
57 } else {
58 assert(sel->nir);
59
60 blob_init(&blob);
61 nir_serialize(&blob, sel->nir);
62 ir_binary = blob.data;
63 ir_size = blob.size;
64 }
65
66 unsigned size = 4 + ir_size + sizeof(sel->so);
67 char *result = (char*)MALLOC(size);
68 if (!result)
69 return NULL;
70
71 *((uint32_t*)result) = size;
72 memcpy(result + 4, ir_binary, ir_size);
73 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
74
75 if (sel->nir)
76 blob_finish(&blob);
77
78 return result;
79 }
80
81 /** Copy "data" to "ptr" and return the next dword following copied data. */
82 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
83 {
84 /* data may be NULL if size == 0 */
85 if (size)
86 memcpy(ptr, data, size);
87 ptr += DIV_ROUND_UP(size, 4);
88 return ptr;
89 }
90
91 /** Read data from "ptr". Return the next dword following the data. */
92 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
93 {
94 memcpy(data, ptr, size);
95 ptr += DIV_ROUND_UP(size, 4);
96 return ptr;
97 }
98
99 /**
100 * Write the size as uint followed by the data. Return the next dword
101 * following the copied data.
102 */
103 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
104 {
105 *ptr++ = size;
106 return write_data(ptr, data, size);
107 }
108
109 /**
110 * Read the size as uint followed by the data. Return both via parameters.
111 * Return the next dword following the data.
112 */
113 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
114 {
115 *size = *ptr++;
116 assert(*data == NULL);
117 if (!*size)
118 return ptr;
119 *data = malloc(*size);
120 return read_data(ptr, *data, *size);
121 }
122
123 /**
124 * Return the shader binary in a buffer. The first 4 bytes contain its size
125 * as integer.
126 */
127 static void *si_get_shader_binary(struct si_shader *shader)
128 {
129 /* There is always a size of data followed by the data itself. */
130 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
131 strlen(shader->binary.llvm_ir_string) + 1 : 0;
132
133 /* Refuse to allocate overly large buffers and guard against integer
134 * overflow. */
135 if (shader->binary.elf_size > UINT_MAX / 4 ||
136 llvm_ir_size > UINT_MAX / 4)
137 return NULL;
138
139 unsigned size =
140 4 + /* total size */
141 4 + /* CRC32 of the data below */
142 align(sizeof(shader->config), 4) +
143 align(sizeof(shader->info), 4) +
144 4 + align(shader->binary.elf_size, 4) +
145 4 + align(llvm_ir_size, 4);
146 void *buffer = CALLOC(1, size);
147 uint32_t *ptr = (uint32_t*)buffer;
148
149 if (!buffer)
150 return NULL;
151
152 *ptr++ = size;
153 ptr++; /* CRC32 is calculated at the end. */
154
155 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
156 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
157 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
158 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
159 assert((char *)ptr - (char *)buffer == size);
160
161 /* Compute CRC32. */
162 ptr = (uint32_t*)buffer;
163 ptr++;
164 *ptr = util_hash_crc32(ptr + 1, size - 8);
165
166 return buffer;
167 }
168
169 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
170 {
171 uint32_t *ptr = (uint32_t*)binary;
172 uint32_t size = *ptr++;
173 uint32_t crc32 = *ptr++;
174 unsigned chunk_size;
175 unsigned elf_size;
176
177 if (util_hash_crc32(ptr, size - 8) != crc32) {
178 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
179 return false;
180 }
181
182 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
183 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
184 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
185 &elf_size);
186 shader->binary.elf_size = elf_size;
187 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
188
189 return true;
190 }
191
192 /**
193 * Insert a shader into the cache. It's assumed the shader is not in the cache.
194 * Use si_shader_cache_load_shader before calling this.
195 *
196 * Returns false on failure, in which case the ir_binary should be freed.
197 */
198 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
199 struct si_shader *shader,
200 bool insert_into_disk_cache)
201 {
202 void *hw_binary;
203 struct hash_entry *entry;
204 uint8_t key[CACHE_KEY_SIZE];
205
206 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
207 if (entry)
208 return false; /* already added */
209
210 hw_binary = si_get_shader_binary(shader);
211 if (!hw_binary)
212 return false;
213
214 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
215 hw_binary) == NULL) {
216 FREE(hw_binary);
217 return false;
218 }
219
220 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
221 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
222 *((uint32_t *)ir_binary), key);
223 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
224 *((uint32_t *) hw_binary), NULL);
225 }
226
227 return true;
228 }
229
230 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
231 struct si_shader *shader)
232 {
233 struct hash_entry *entry =
234 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
235 if (!entry) {
236 if (sscreen->disk_shader_cache) {
237 unsigned char sha1[CACHE_KEY_SIZE];
238 size_t tg_size = *((uint32_t *) ir_binary);
239
240 disk_cache_compute_key(sscreen->disk_shader_cache,
241 ir_binary, tg_size, sha1);
242
243 size_t binary_size;
244 uint8_t *buffer =
245 disk_cache_get(sscreen->disk_shader_cache,
246 sha1, &binary_size);
247 if (!buffer)
248 return false;
249
250 if (binary_size < sizeof(uint32_t) ||
251 *((uint32_t*)buffer) != binary_size) {
252 /* Something has gone wrong discard the item
253 * from the cache and rebuild/link from
254 * source.
255 */
256 assert(!"Invalid radeonsi shader disk cache "
257 "item!");
258
259 disk_cache_remove(sscreen->disk_shader_cache,
260 sha1);
261 free(buffer);
262
263 return false;
264 }
265
266 if (!si_load_shader_binary(shader, buffer)) {
267 free(buffer);
268 return false;
269 }
270 free(buffer);
271
272 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
273 shader, false))
274 FREE(ir_binary);
275 } else {
276 return false;
277 }
278 } else {
279 if (si_load_shader_binary(shader, entry->data))
280 FREE(ir_binary);
281 else
282 return false;
283 }
284 p_atomic_inc(&sscreen->num_shader_cache_hits);
285 return true;
286 }
287
288 static uint32_t si_shader_cache_key_hash(const void *key)
289 {
290 /* The first dword is the key size. */
291 return util_hash_crc32(key, *(uint32_t*)key);
292 }
293
294 static bool si_shader_cache_key_equals(const void *a, const void *b)
295 {
296 uint32_t *keya = (uint32_t*)a;
297 uint32_t *keyb = (uint32_t*)b;
298
299 /* The first dword is the key size. */
300 if (*keya != *keyb)
301 return false;
302
303 return memcmp(keya, keyb, *keya) == 0;
304 }
305
306 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
307 {
308 FREE((void*)entry->key);
309 FREE(entry->data);
310 }
311
312 bool si_init_shader_cache(struct si_screen *sscreen)
313 {
314 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
315 sscreen->shader_cache =
316 _mesa_hash_table_create(NULL,
317 si_shader_cache_key_hash,
318 si_shader_cache_key_equals);
319
320 return sscreen->shader_cache != NULL;
321 }
322
323 void si_destroy_shader_cache(struct si_screen *sscreen)
324 {
325 if (sscreen->shader_cache)
326 _mesa_hash_table_destroy(sscreen->shader_cache,
327 si_destroy_shader_cache_entry);
328 mtx_destroy(&sscreen->shader_cache_mutex);
329 }
330
331 /* SHADER STATES */
332
333 static void si_set_tesseval_regs(struct si_screen *sscreen,
334 const struct si_shader_selector *tes,
335 struct si_pm4_state *pm4)
336 {
337 const struct tgsi_shader_info *info = &tes->info;
338 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
339 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
340 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
341 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
342 unsigned type, partitioning, topology, distribution_mode;
343
344 switch (tes_prim_mode) {
345 case PIPE_PRIM_LINES:
346 type = V_028B6C_TESS_ISOLINE;
347 break;
348 case PIPE_PRIM_TRIANGLES:
349 type = V_028B6C_TESS_TRIANGLE;
350 break;
351 case PIPE_PRIM_QUADS:
352 type = V_028B6C_TESS_QUAD;
353 break;
354 default:
355 assert(0);
356 return;
357 }
358
359 switch (tes_spacing) {
360 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
361 partitioning = V_028B6C_PART_FRAC_ODD;
362 break;
363 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
364 partitioning = V_028B6C_PART_FRAC_EVEN;
365 break;
366 case PIPE_TESS_SPACING_EQUAL:
367 partitioning = V_028B6C_PART_INTEGER;
368 break;
369 default:
370 assert(0);
371 return;
372 }
373
374 if (tes_point_mode)
375 topology = V_028B6C_OUTPUT_POINT;
376 else if (tes_prim_mode == PIPE_PRIM_LINES)
377 topology = V_028B6C_OUTPUT_LINE;
378 else if (tes_vertex_order_cw)
379 /* for some reason, this must be the other way around */
380 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
381 else
382 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
383
384 if (sscreen->has_distributed_tess) {
385 if (sscreen->info.family == CHIP_FIJI ||
386 sscreen->info.family >= CHIP_POLARIS10)
387 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
388 else
389 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
390 } else
391 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
392
393 assert(pm4->shader);
394 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
395 S_028B6C_PARTITIONING(partitioning) |
396 S_028B6C_TOPOLOGY(topology) |
397 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
398 }
399
400 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
401 * whether the "fractional odd" tessellation spacing is used.
402 *
403 * Possible VGT configurations and which state should set the register:
404 *
405 * Reg set in | VGT shader configuration | Value
406 * ------------------------------------------------------
407 * VS as VS | VS | 30
408 * VS as ES | ES -> GS -> VS | 30
409 * TES as VS | LS -> HS -> VS | 14 or 30
410 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
411 *
412 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
413 */
414 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
415 struct si_shader_selector *sel,
416 struct si_shader *shader,
417 struct si_pm4_state *pm4)
418 {
419 unsigned type = sel->type;
420
421 if (sscreen->info.family < CHIP_POLARIS10)
422 return;
423
424 /* VS as VS, or VS as ES: */
425 if ((type == PIPE_SHADER_VERTEX &&
426 (!shader ||
427 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
428 /* TES as VS, or TES as ES: */
429 type == PIPE_SHADER_TESS_EVAL) {
430 unsigned vtx_reuse_depth = 30;
431
432 if (type == PIPE_SHADER_TESS_EVAL &&
433 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
434 PIPE_TESS_SPACING_FRACTIONAL_ODD)
435 vtx_reuse_depth = 14;
436
437 assert(pm4->shader);
438 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
439 }
440 }
441
442 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
443 {
444 if (shader->pm4)
445 si_pm4_clear_state(shader->pm4);
446 else
447 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
448
449 if (shader->pm4) {
450 shader->pm4->shader = shader;
451 return shader->pm4;
452 } else {
453 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
454 return NULL;
455 }
456 }
457
458 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
459 {
460 /* Add the pointer to VBO descriptors. */
461 return num_always_on_user_sgprs + 1;
462 }
463
464 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
465 {
466 struct si_pm4_state *pm4;
467 unsigned vgpr_comp_cnt;
468 uint64_t va;
469
470 assert(sscreen->info.chip_class <= GFX8);
471
472 pm4 = si_get_shader_pm4_state(shader);
473 if (!pm4)
474 return;
475
476 va = shader->bo->gpu_address;
477 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
478
479 /* We need at least 2 components for LS.
480 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
481 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
482 */
483 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
484
485 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
486 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
487
488 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
489 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
490 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
491 S_00B528_DX10_CLAMP(1) |
492 S_00B528_FLOAT_MODE(shader->config.float_mode);
493 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
494 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
495 }
496
497 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
498 {
499 struct si_pm4_state *pm4;
500 uint64_t va;
501 unsigned ls_vgpr_comp_cnt = 0;
502
503 pm4 = si_get_shader_pm4_state(shader);
504 if (!pm4)
505 return;
506
507 va = shader->bo->gpu_address;
508 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
509
510 if (sscreen->info.chip_class >= GFX9) {
511 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
512 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
513
514 /* We need at least 2 components for LS.
515 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
516 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
517 */
518 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
519
520 unsigned num_user_sgprs =
521 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
522
523 shader->config.rsrc2 =
524 S_00B42C_USER_SGPR(num_user_sgprs) |
525 S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5) |
526 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
527 } else {
528 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
529 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
530
531 shader->config.rsrc2 =
532 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
533 S_00B42C_OC_LDS_EN(1) |
534 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
535 }
536
537 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
538 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
539 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
540 S_00B428_DX10_CLAMP(1) |
541 S_00B428_FLOAT_MODE(shader->config.float_mode) |
542 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
543
544 if (sscreen->info.chip_class <= GFX8) {
545 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
546 shader->config.rsrc2);
547 }
548 }
549
550 static void si_emit_shader_es(struct si_context *sctx)
551 {
552 struct si_shader *shader = sctx->queued.named.es->shader;
553 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
554
555 if (!shader)
556 return;
557
558 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
559 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
560 shader->selector->esgs_itemsize / 4);
561
562 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
563 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
564 SI_TRACKED_VGT_TF_PARAM,
565 shader->vgt_tf_param);
566
567 if (shader->vgt_vertex_reuse_block_cntl)
568 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
569 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
570 shader->vgt_vertex_reuse_block_cntl);
571
572 if (initial_cdw != sctx->gfx_cs->current.cdw)
573 sctx->context_roll = true;
574 }
575
576 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
577 {
578 struct si_pm4_state *pm4;
579 unsigned num_user_sgprs;
580 unsigned vgpr_comp_cnt;
581 uint64_t va;
582 unsigned oc_lds_en;
583
584 assert(sscreen->info.chip_class <= GFX8);
585
586 pm4 = si_get_shader_pm4_state(shader);
587 if (!pm4)
588 return;
589
590 pm4->atom.emit = si_emit_shader_es;
591 va = shader->bo->gpu_address;
592 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
593
594 if (shader->selector->type == PIPE_SHADER_VERTEX) {
595 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
596 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
597 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
598 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
599 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
600 num_user_sgprs = SI_TES_NUM_USER_SGPR;
601 } else
602 unreachable("invalid shader selector type");
603
604 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
605
606 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
607 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
608 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
609 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
610 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
611 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
612 S_00B328_DX10_CLAMP(1) |
613 S_00B328_FLOAT_MODE(shader->config.float_mode));
614 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
615 S_00B32C_USER_SGPR(num_user_sgprs) |
616 S_00B32C_OC_LDS_EN(oc_lds_en) |
617 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
618
619 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
620 si_set_tesseval_regs(sscreen, shader->selector, pm4);
621
622 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
623 }
624
625 static unsigned si_conv_prim_to_gs_out(unsigned mode)
626 {
627 static const int prim_conv[] = {
628 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
629 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
630 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
631 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
632 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
633 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
634 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
635 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
636 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
637 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
638 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
639 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
640 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
641 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
642 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
643 };
644 assert(mode < ARRAY_SIZE(prim_conv));
645
646 return prim_conv[mode];
647 }
648
649 void gfx9_get_gs_info(struct si_shader_selector *es,
650 struct si_shader_selector *gs,
651 struct gfx9_gs_info *out)
652 {
653 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
654 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
655 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
656 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
657
658 /* All these are in dwords: */
659 /* We can't allow using the whole LDS, because GS waves compete with
660 * other shader stages for LDS space. */
661 const unsigned max_lds_size = 8 * 1024;
662 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
663 unsigned esgs_lds_size;
664
665 /* All these are per subgroup: */
666 const unsigned max_out_prims = 32 * 1024;
667 const unsigned max_es_verts = 255;
668 const unsigned ideal_gs_prims = 64;
669 unsigned max_gs_prims, gs_prims;
670 unsigned min_es_verts, es_verts, worst_case_es_verts;
671
672 if (uses_adjacency || gs_num_invocations > 1)
673 max_gs_prims = 127 / gs_num_invocations;
674 else
675 max_gs_prims = 255;
676
677 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
678 * Make sure we don't go over the maximum value.
679 */
680 if (gs->gs_max_out_vertices > 0) {
681 max_gs_prims = MIN2(max_gs_prims,
682 max_out_prims /
683 (gs->gs_max_out_vertices * gs_num_invocations));
684 }
685 assert(max_gs_prims > 0);
686
687 /* If the primitive has adjacency, halve the number of vertices
688 * that will be reused in multiple primitives.
689 */
690 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
691
692 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
693 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
694
695 /* Compute ESGS LDS size based on the worst case number of ES vertices
696 * needed to create the target number of GS prims per subgroup.
697 */
698 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
699
700 /* If total LDS usage is too big, refactor partitions based on ratio
701 * of ESGS item sizes.
702 */
703 if (esgs_lds_size > max_lds_size) {
704 /* Our target GS Prims Per Subgroup was too large. Calculate
705 * the maximum number of GS Prims Per Subgroup that will fit
706 * into LDS, capped by the maximum that the hardware can support.
707 */
708 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
709 max_gs_prims);
710 assert(gs_prims > 0);
711 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
712 max_es_verts);
713
714 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
715 assert(esgs_lds_size <= max_lds_size);
716 }
717
718 /* Now calculate remaining ESGS information. */
719 if (esgs_lds_size)
720 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
721 else
722 es_verts = max_es_verts;
723
724 /* Vertices for adjacency primitives are not always reused, so restore
725 * it for ES_VERTS_PER_SUBGRP.
726 */
727 min_es_verts = gs->gs_input_verts_per_prim;
728
729 /* For normal primitives, the VGT only checks if they are past the ES
730 * verts per subgroup after allocating a full GS primitive and if they
731 * are, kick off a new subgroup. But if those additional ES verts are
732 * unique (e.g. not reused) we need to make sure there is enough LDS
733 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
734 */
735 es_verts -= min_es_verts - 1;
736
737 out->es_verts_per_subgroup = es_verts;
738 out->gs_prims_per_subgroup = gs_prims;
739 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
740 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
741 gs->gs_max_out_vertices;
742 out->esgs_ring_size = 4 * esgs_lds_size;
743
744 assert(out->max_prims_per_subgroup <= max_out_prims);
745 }
746
747 static void si_emit_shader_gs(struct si_context *sctx)
748 {
749 struct si_shader *shader = sctx->queued.named.gs->shader;
750 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
751
752 if (!shader)
753 return;
754
755 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
756 * R_028A68_VGT_GSVS_RING_OFFSET_3, R_028A6C_VGT_GS_OUT_PRIM_TYPE */
757 radeon_opt_set_context_reg4(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
758 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
759 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
760 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
761 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3,
762 shader->ctx_reg.gs.vgt_gs_out_prim_type);
763
764
765 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
766 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
767 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
768 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
769
770 /* R_028B38_VGT_GS_MAX_VERT_OUT */
771 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
772 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
773 shader->ctx_reg.gs.vgt_gs_max_vert_out);
774
775 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
776 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
777 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
778 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
779 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
780 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
781 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
782 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
783
784 /* R_028B90_VGT_GS_INSTANCE_CNT */
785 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
786 SI_TRACKED_VGT_GS_INSTANCE_CNT,
787 shader->ctx_reg.gs.vgt_gs_instance_cnt);
788
789 if (sctx->chip_class >= GFX9) {
790 /* R_028A44_VGT_GS_ONCHIP_CNTL */
791 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
792 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
793 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
794 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
795 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
796 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
797 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
798 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
799 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
800 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
801 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
802
803 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
804 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
805 SI_TRACKED_VGT_TF_PARAM,
806 shader->vgt_tf_param);
807 if (shader->vgt_vertex_reuse_block_cntl)
808 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
809 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
810 shader->vgt_vertex_reuse_block_cntl);
811 }
812
813 if (initial_cdw != sctx->gfx_cs->current.cdw)
814 sctx->context_roll = true;
815 }
816
817 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
818 {
819 struct si_shader_selector *sel = shader->selector;
820 const ubyte *num_components = sel->info.num_stream_output_components;
821 unsigned gs_num_invocations = sel->gs_num_invocations;
822 struct si_pm4_state *pm4;
823 uint64_t va;
824 unsigned max_stream = sel->max_gs_stream;
825 unsigned offset;
826
827 pm4 = si_get_shader_pm4_state(shader);
828 if (!pm4)
829 return;
830
831 pm4->atom.emit = si_emit_shader_gs;
832
833 offset = num_components[0] * sel->gs_max_out_vertices;
834 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
835
836 if (max_stream >= 1)
837 offset += num_components[1] * sel->gs_max_out_vertices;
838 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
839
840 if (max_stream >= 2)
841 offset += num_components[2] * sel->gs_max_out_vertices;
842 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
843
844 shader->ctx_reg.gs.vgt_gs_out_prim_type =
845 si_conv_prim_to_gs_out(sel->gs_output_prim);
846
847 if (max_stream >= 3)
848 offset += num_components[3] * sel->gs_max_out_vertices;
849 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
850
851 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
852 assert(offset < (1 << 15));
853
854 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
855
856 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
857 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
858 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
859 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
860
861 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
862 S_028B90_ENABLE(gs_num_invocations > 0);
863
864 va = shader->bo->gpu_address;
865 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
866
867 if (sscreen->info.chip_class >= GFX9) {
868 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
869 unsigned es_type = shader->key.part.gs.es->type;
870 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
871
872 if (es_type == PIPE_SHADER_VERTEX)
873 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
874 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
875 else if (es_type == PIPE_SHADER_TESS_EVAL)
876 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
877 else
878 unreachable("invalid shader selector type");
879
880 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
881 * VGPR[0:4] are always loaded.
882 */
883 if (sel->info.uses_invocationid)
884 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
885 else if (sel->info.uses_primid)
886 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
887 else if (input_prim >= PIPE_PRIM_TRIANGLES)
888 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
889 else
890 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
891
892 unsigned num_user_sgprs;
893 if (es_type == PIPE_SHADER_VERTEX)
894 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
895 else
896 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
897
898 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
899 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
900
901 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
902 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
903 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
904 S_00B228_DX10_CLAMP(1) |
905 S_00B228_FLOAT_MODE(shader->config.float_mode) |
906 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
907 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
908 S_00B22C_USER_SGPR(num_user_sgprs) |
909 S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5) |
910 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
911 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
912 S_00B22C_LDS_SIZE(shader->config.lds_size) |
913 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
914
915 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
916 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
917 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
918 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
919 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
920 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
921 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
922 shader->key.part.gs.es->esgs_itemsize / 4;
923
924 if (es_type == PIPE_SHADER_TESS_EVAL)
925 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
926
927 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
928 NULL, pm4);
929 } else {
930 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
931 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
932
933 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
934 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
935 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
936 S_00B228_DX10_CLAMP(1) |
937 S_00B228_FLOAT_MODE(shader->config.float_mode));
938 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
939 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
940 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
941 }
942 }
943
944 static void si_emit_shader_vs(struct si_context *sctx)
945 {
946 struct si_shader *shader = sctx->queued.named.vs->shader;
947 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
948
949 if (!shader)
950 return;
951
952 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
953 SI_TRACKED_VGT_GS_MODE,
954 shader->ctx_reg.vs.vgt_gs_mode);
955 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
956 SI_TRACKED_VGT_PRIMITIVEID_EN,
957 shader->ctx_reg.vs.vgt_primitiveid_en);
958
959 if (sctx->chip_class <= GFX8) {
960 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
961 SI_TRACKED_VGT_REUSE_OFF,
962 shader->ctx_reg.vs.vgt_reuse_off);
963 }
964
965 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
966 SI_TRACKED_SPI_VS_OUT_CONFIG,
967 shader->ctx_reg.vs.spi_vs_out_config);
968
969 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
970 SI_TRACKED_SPI_SHADER_POS_FORMAT,
971 shader->ctx_reg.vs.spi_shader_pos_format);
972
973 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
974 SI_TRACKED_PA_CL_VTE_CNTL,
975 shader->ctx_reg.vs.pa_cl_vte_cntl);
976
977 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
978 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
979 SI_TRACKED_VGT_TF_PARAM,
980 shader->vgt_tf_param);
981
982 if (shader->vgt_vertex_reuse_block_cntl)
983 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
984 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
985 shader->vgt_vertex_reuse_block_cntl);
986
987 if (initial_cdw != sctx->gfx_cs->current.cdw)
988 sctx->context_roll = true;
989 }
990
991 /**
992 * Compute the state for \p shader, which will run as a vertex shader on the
993 * hardware.
994 *
995 * If \p gs is non-NULL, it points to the geometry shader for which this shader
996 * is the copy shader.
997 */
998 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
999 struct si_shader_selector *gs)
1000 {
1001 const struct tgsi_shader_info *info = &shader->selector->info;
1002 struct si_pm4_state *pm4;
1003 unsigned num_user_sgprs, vgpr_comp_cnt;
1004 uint64_t va;
1005 unsigned nparams, oc_lds_en;
1006 unsigned window_space =
1007 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1008 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1009
1010 pm4 = si_get_shader_pm4_state(shader);
1011 if (!pm4)
1012 return;
1013
1014 pm4->atom.emit = si_emit_shader_vs;
1015
1016 /* We always write VGT_GS_MODE in the VS state, because every switch
1017 * between different shader pipelines involving a different GS or no
1018 * GS at all involves a switch of the VS (different GS use different
1019 * copy shaders). On the other hand, when the API switches from a GS to
1020 * no GS and then back to the same GS used originally, the GS state is
1021 * not sent again.
1022 */
1023 if (!gs) {
1024 unsigned mode = V_028A40_GS_OFF;
1025
1026 /* PrimID needs GS scenario A. */
1027 if (enable_prim_id)
1028 mode = V_028A40_GS_SCENARIO_A;
1029
1030 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1031 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1032 } else {
1033 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1034 sscreen->info.chip_class);
1035 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1036 }
1037
1038 if (sscreen->info.chip_class <= GFX8) {
1039 /* Reuse needs to be set off if we write oViewport. */
1040 shader->ctx_reg.vs.vgt_reuse_off =
1041 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1042 }
1043
1044 va = shader->bo->gpu_address;
1045 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1046
1047 if (gs) {
1048 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1049 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1050 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1051 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1052 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1053 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1054 */
1055 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
1056
1057 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1058 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1059 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1060 } else {
1061 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1062 }
1063 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1064 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1065 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1066 } else
1067 unreachable("invalid shader selector type");
1068
1069 /* VS is required to export at least one param. */
1070 nparams = MAX2(shader->info.nr_param_exports, 1);
1071 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1072
1073 shader->ctx_reg.vs.spi_shader_pos_format =
1074 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1075 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1076 V_02870C_SPI_SHADER_4COMP :
1077 V_02870C_SPI_SHADER_NONE) |
1078 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1079 V_02870C_SPI_SHADER_4COMP :
1080 V_02870C_SPI_SHADER_NONE) |
1081 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1082 V_02870C_SPI_SHADER_4COMP :
1083 V_02870C_SPI_SHADER_NONE);
1084
1085 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1086
1087 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1088 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1089 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
1090 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
1091 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
1092 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1093 S_00B128_DX10_CLAMP(1) |
1094 S_00B128_FLOAT_MODE(shader->config.float_mode));
1095 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
1096 S_00B12C_USER_SGPR(num_user_sgprs) |
1097 S_00B12C_OC_LDS_EN(oc_lds_en) |
1098 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1099 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1100 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1101 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1102 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
1103 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1104
1105 if (window_space)
1106 shader->ctx_reg.vs.pa_cl_vte_cntl =
1107 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1108 else
1109 shader->ctx_reg.vs.pa_cl_vte_cntl =
1110 S_028818_VTX_W0_FMT(1) |
1111 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1112 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1113 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1114
1115 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1116 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1117
1118 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1119 }
1120
1121 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1122 {
1123 struct tgsi_shader_info *info = &ps->selector->info;
1124 unsigned num_colors = !!(info->colors_read & 0x0f) +
1125 !!(info->colors_read & 0xf0);
1126 unsigned num_interp = ps->selector->info.num_inputs +
1127 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1128
1129 assert(num_interp <= 32);
1130 return MIN2(num_interp, 32);
1131 }
1132
1133 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1134 {
1135 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1136 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1137
1138 /* If the i-th target format is set, all previous target formats must
1139 * be non-zero to avoid hangs.
1140 */
1141 for (i = 0; i < num_targets; i++)
1142 if (!(value & (0xf << (i * 4))))
1143 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1144
1145 return value;
1146 }
1147
1148 static void si_emit_shader_ps(struct si_context *sctx)
1149 {
1150 struct si_shader *shader = sctx->queued.named.ps->shader;
1151 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1152
1153 if (!shader)
1154 return;
1155
1156 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1157 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1158 SI_TRACKED_SPI_PS_INPUT_ENA,
1159 shader->ctx_reg.ps.spi_ps_input_ena,
1160 shader->ctx_reg.ps.spi_ps_input_addr);
1161
1162 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1163 SI_TRACKED_SPI_BARYC_CNTL,
1164 shader->ctx_reg.ps.spi_baryc_cntl);
1165 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1166 SI_TRACKED_SPI_PS_IN_CONTROL,
1167 shader->ctx_reg.ps.spi_ps_in_control);
1168
1169 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1170 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1171 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1172 shader->ctx_reg.ps.spi_shader_z_format,
1173 shader->ctx_reg.ps.spi_shader_col_format);
1174
1175 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1176 SI_TRACKED_CB_SHADER_MASK,
1177 shader->ctx_reg.ps.cb_shader_mask);
1178
1179 if (initial_cdw != sctx->gfx_cs->current.cdw)
1180 sctx->context_roll = true;
1181 }
1182
1183 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1184 {
1185 struct tgsi_shader_info *info = &shader->selector->info;
1186 struct si_pm4_state *pm4;
1187 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1188 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1189 uint64_t va;
1190 unsigned input_ena = shader->config.spi_ps_input_ena;
1191
1192 /* we need to enable at least one of them, otherwise we hang the GPU */
1193 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1194 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1195 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1196 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1197 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1198 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1199 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1200 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1201 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1202 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1203 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1204 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1205 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1206 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1207
1208 /* Validate interpolation optimization flags (read as implications). */
1209 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1210 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1211 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1212 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1213 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1214 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1215 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1216 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1217 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1218 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1219 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1220 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1221 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1222 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1223 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1224 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1225 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1226 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1227
1228 /* Validate cases when the optimizations are off (read as implications). */
1229 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1230 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1231 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1232 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1233 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1234 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1235
1236 pm4 = si_get_shader_pm4_state(shader);
1237 if (!pm4)
1238 return;
1239
1240 pm4->atom.emit = si_emit_shader_ps;
1241
1242 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1243 * Possible vaules:
1244 * 0 -> Position = pixel center
1245 * 1 -> Position = pixel centroid
1246 * 2 -> Position = at sample position
1247 *
1248 * From GLSL 4.5 specification, section 7.1:
1249 * "The variable gl_FragCoord is available as an input variable from
1250 * within fragment shaders and it holds the window relative coordinates
1251 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1252 * value can be for any location within the pixel, or one of the
1253 * fragment samples. The use of centroid does not further restrict
1254 * this value to be inside the current primitive."
1255 *
1256 * Meaning that centroid has no effect and we can return anything within
1257 * the pixel. Thus, return the value at sample position, because that's
1258 * the most accurate one shaders can get.
1259 */
1260 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1261
1262 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1263 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1264 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1265
1266 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1267 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1268
1269 /* Ensure that some export memory is always allocated, for two reasons:
1270 *
1271 * 1) Correctness: The hardware ignores the EXEC mask if no export
1272 * memory is allocated, so KILL and alpha test do not work correctly
1273 * without this.
1274 * 2) Performance: Every shader needs at least a NULL export, even when
1275 * it writes no color/depth output. The NULL export instruction
1276 * stalls without this setting.
1277 *
1278 * Don't add this to CB_SHADER_MASK.
1279 */
1280 if (!spi_shader_col_format &&
1281 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1282 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1283
1284 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1285 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1286
1287 /* Set interpolation controls. */
1288 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1289
1290 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1291 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1292 shader->ctx_reg.ps.spi_shader_z_format =
1293 ac_get_spi_shader_z_format(info->writes_z,
1294 info->writes_stencil,
1295 info->writes_samplemask);
1296 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1297 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1298
1299 va = shader->bo->gpu_address;
1300 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1301 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1302 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1303
1304 uint32_t rsrc1 =
1305 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1306 S_00B028_DX10_CLAMP(1) |
1307 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1308 S_00B028_FLOAT_MODE(shader->config.float_mode);
1309
1310 if (sscreen->info.chip_class < GFX10) {
1311 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1312 }
1313
1314 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1315 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1316 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1317 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1318 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1319 }
1320
1321 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1322 struct si_shader *shader)
1323 {
1324 switch (shader->selector->type) {
1325 case PIPE_SHADER_VERTEX:
1326 if (shader->key.as_ls)
1327 si_shader_ls(sscreen, shader);
1328 else if (shader->key.as_es)
1329 si_shader_es(sscreen, shader);
1330 else
1331 si_shader_vs(sscreen, shader, NULL);
1332 break;
1333 case PIPE_SHADER_TESS_CTRL:
1334 si_shader_hs(sscreen, shader);
1335 break;
1336 case PIPE_SHADER_TESS_EVAL:
1337 if (shader->key.as_es)
1338 si_shader_es(sscreen, shader);
1339 else
1340 si_shader_vs(sscreen, shader, NULL);
1341 break;
1342 case PIPE_SHADER_GEOMETRY:
1343 si_shader_gs(sscreen, shader);
1344 break;
1345 case PIPE_SHADER_FRAGMENT:
1346 si_shader_ps(sscreen, shader);
1347 break;
1348 default:
1349 assert(0);
1350 }
1351 }
1352
1353 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1354 {
1355 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1356 if (sctx->queued.named.dsa)
1357 return sctx->queued.named.dsa->alpha_func;
1358
1359 return PIPE_FUNC_ALWAYS;
1360 }
1361
1362 void si_shader_selector_key_vs(struct si_context *sctx,
1363 struct si_shader_selector *vs,
1364 struct si_shader_key *key,
1365 struct si_vs_prolog_bits *prolog_key)
1366 {
1367 if (!sctx->vertex_elements ||
1368 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS])
1369 return;
1370
1371 struct si_vertex_elements *elts = sctx->vertex_elements;
1372
1373 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1374 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1375 prolog_key->unpack_instance_id_from_vertex_id =
1376 sctx->prim_discard_cs_instancing;
1377
1378 /* Prefer a monolithic shader to allow scheduling divisions around
1379 * VBO loads. */
1380 if (prolog_key->instance_divisor_is_fetched)
1381 key->opt.prefer_mono = 1;
1382
1383 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1384 unsigned count_mask = (1 << count) - 1;
1385 unsigned fix = elts->fix_fetch_always & count_mask;
1386 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1387
1388 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1389 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1390 while (mask) {
1391 unsigned i = u_bit_scan(&mask);
1392 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1393 unsigned vbidx = elts->vertex_buffer_index[i];
1394 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1395 unsigned align_mask = (1 << log_hw_load_size) - 1;
1396 if (vb->buffer_offset & align_mask ||
1397 vb->stride & align_mask) {
1398 fix |= 1 << i;
1399 opencode |= 1 << i;
1400 }
1401 }
1402 }
1403
1404 while (fix) {
1405 unsigned i = u_bit_scan(&fix);
1406 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1407 }
1408 key->mono.vs_fetch_opencode = opencode;
1409 }
1410
1411 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1412 struct si_shader_selector *vs,
1413 struct si_shader_key *key)
1414 {
1415 struct si_shader_selector *ps = sctx->ps_shader.cso;
1416
1417 key->opt.clip_disable =
1418 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1419 (vs->info.clipdist_writemask ||
1420 vs->info.writes_clipvertex) &&
1421 !vs->info.culldist_writemask;
1422
1423 /* Find out if PS is disabled. */
1424 bool ps_disabled = true;
1425 if (ps) {
1426 const struct si_state_blend *blend = sctx->queued.named.blend;
1427 bool alpha_to_coverage = blend && blend->alpha_to_coverage;
1428 bool ps_modifies_zs = ps->info.uses_kill ||
1429 ps->info.writes_z ||
1430 ps->info.writes_stencil ||
1431 ps->info.writes_samplemask ||
1432 alpha_to_coverage ||
1433 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1434 unsigned ps_colormask = si_get_total_colormask(sctx);
1435
1436 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1437 (!ps_colormask &&
1438 !ps_modifies_zs &&
1439 !ps->info.writes_memory);
1440 }
1441
1442 /* Find out which VS outputs aren't used by the PS. */
1443 uint64_t outputs_written = vs->outputs_written_before_ps;
1444 uint64_t inputs_read = 0;
1445
1446 /* Ignore outputs that are not passed from VS to PS. */
1447 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1448 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1449 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1450
1451 if (!ps_disabled) {
1452 inputs_read = ps->inputs_read;
1453 }
1454
1455 uint64_t linked = outputs_written & inputs_read;
1456
1457 key->opt.kill_outputs = ~linked & outputs_written;
1458 }
1459
1460 /* Compute the key for the hw shader variant */
1461 static inline void si_shader_selector_key(struct pipe_context *ctx,
1462 struct si_shader_selector *sel,
1463 union si_vgt_stages_key stages_key,
1464 struct si_shader_key *key)
1465 {
1466 struct si_context *sctx = (struct si_context *)ctx;
1467
1468 memset(key, 0, sizeof(*key));
1469
1470 switch (sel->type) {
1471 case PIPE_SHADER_VERTEX:
1472 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1473
1474 if (sctx->tes_shader.cso)
1475 key->as_ls = 1;
1476 else if (sctx->gs_shader.cso)
1477 key->as_es = 1;
1478 else {
1479 key->as_ngg = stages_key.u.ngg;
1480 si_shader_selector_key_hw_vs(sctx, sel, key);
1481
1482 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1483 key->mono.u.vs_export_prim_id = 1;
1484 }
1485 break;
1486 case PIPE_SHADER_TESS_CTRL:
1487 if (sctx->chip_class >= GFX9) {
1488 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1489 key, &key->part.tcs.ls_prolog);
1490 key->part.tcs.ls = sctx->vs_shader.cso;
1491
1492 /* When the LS VGPR fix is needed, monolithic shaders
1493 * can:
1494 * - avoid initializing EXEC in both the LS prolog
1495 * and the LS main part when !vs_needs_prolog
1496 * - remove the fixup for unused input VGPRs
1497 */
1498 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1499
1500 /* The LS output / HS input layout can be communicated
1501 * directly instead of via user SGPRs for merged LS-HS.
1502 * The LS VGPR fix prefers this too.
1503 */
1504 key->opt.prefer_mono = 1;
1505 }
1506
1507 key->part.tcs.epilog.prim_mode =
1508 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1509 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1510 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1511 key->part.tcs.epilog.tes_reads_tess_factors =
1512 sctx->tes_shader.cso->info.reads_tess_factors;
1513
1514 if (sel == sctx->fixed_func_tcs_shader.cso)
1515 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1516 break;
1517 case PIPE_SHADER_TESS_EVAL:
1518 if (sctx->gs_shader.cso)
1519 key->as_es = 1;
1520 else {
1521 key->as_ngg = stages_key.u.ngg;
1522 si_shader_selector_key_hw_vs(sctx, sel, key);
1523
1524 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1525 key->mono.u.vs_export_prim_id = 1;
1526 }
1527 break;
1528 case PIPE_SHADER_GEOMETRY:
1529 if (sctx->chip_class >= GFX9) {
1530 if (sctx->tes_shader.cso) {
1531 key->part.gs.es = sctx->tes_shader.cso;
1532 } else {
1533 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1534 key, &key->part.gs.vs_prolog);
1535 key->part.gs.es = sctx->vs_shader.cso;
1536 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1537 }
1538
1539 key->as_ngg = stages_key.u.ngg;
1540
1541 /* Merged ES-GS can have unbalanced wave usage.
1542 *
1543 * ES threads are per-vertex, while GS threads are
1544 * per-primitive. So without any amplification, there
1545 * are fewer GS threads than ES threads, which can result
1546 * in empty (no-op) GS waves. With too much amplification,
1547 * there are more GS threads than ES threads, which
1548 * can result in empty (no-op) ES waves.
1549 *
1550 * Non-monolithic shaders are implemented by setting EXEC
1551 * at the beginning of shader parts, and don't jump to
1552 * the end if EXEC is 0.
1553 *
1554 * Monolithic shaders use conditional blocks, so they can
1555 * jump and skip empty waves of ES or GS. So set this to
1556 * always use optimized variants, which are monolithic.
1557 */
1558 key->opt.prefer_mono = 1;
1559 }
1560 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1561 break;
1562 case PIPE_SHADER_FRAGMENT: {
1563 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1564 struct si_state_blend *blend = sctx->queued.named.blend;
1565
1566 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1567 sel->info.colors_written == 0x1)
1568 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1569
1570 if (blend) {
1571 /* Select the shader color format based on whether
1572 * blending or alpha are needed.
1573 */
1574 key->part.ps.epilog.spi_shader_col_format =
1575 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1576 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1577 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1578 sctx->framebuffer.spi_shader_col_format_blend) |
1579 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1580 sctx->framebuffer.spi_shader_col_format_alpha) |
1581 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1582 sctx->framebuffer.spi_shader_col_format);
1583 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1584
1585 /* The output for dual source blending should have
1586 * the same format as the first output.
1587 */
1588 if (blend->dual_src_blend)
1589 key->part.ps.epilog.spi_shader_col_format |=
1590 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1591 } else
1592 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1593
1594 /* If alpha-to-coverage is enabled, we have to export alpha
1595 * even if there is no color buffer.
1596 */
1597 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1598 blend && blend->alpha_to_coverage)
1599 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1600
1601 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1602 * to the range supported by the type if a channel has less
1603 * than 16 bits and the export format is 16_ABGR.
1604 */
1605 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1606 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1607 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1608 }
1609
1610 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1611 if (!key->part.ps.epilog.last_cbuf) {
1612 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1613 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1614 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1615 }
1616
1617 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1618 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1619
1620 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1621 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1622
1623 if (sctx->queued.named.blend) {
1624 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1625 rs->multisample_enable;
1626 }
1627
1628 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1629 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1630 (is_line && rs->line_smooth)) &&
1631 sctx->framebuffer.nr_samples <= 1;
1632 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1633
1634 if (sctx->ps_iter_samples > 1 &&
1635 sel->info.reads_samplemask) {
1636 key->part.ps.prolog.samplemask_log_ps_iter =
1637 util_logbase2(sctx->ps_iter_samples);
1638 }
1639
1640 if (rs->force_persample_interp &&
1641 rs->multisample_enable &&
1642 sctx->framebuffer.nr_samples > 1 &&
1643 sctx->ps_iter_samples > 1) {
1644 key->part.ps.prolog.force_persp_sample_interp =
1645 sel->info.uses_persp_center ||
1646 sel->info.uses_persp_centroid;
1647
1648 key->part.ps.prolog.force_linear_sample_interp =
1649 sel->info.uses_linear_center ||
1650 sel->info.uses_linear_centroid;
1651 } else if (rs->multisample_enable &&
1652 sctx->framebuffer.nr_samples > 1) {
1653 key->part.ps.prolog.bc_optimize_for_persp =
1654 sel->info.uses_persp_center &&
1655 sel->info.uses_persp_centroid;
1656 key->part.ps.prolog.bc_optimize_for_linear =
1657 sel->info.uses_linear_center &&
1658 sel->info.uses_linear_centroid;
1659 } else {
1660 /* Make sure SPI doesn't compute more than 1 pair
1661 * of (i,j), which is the optimization here. */
1662 key->part.ps.prolog.force_persp_center_interp =
1663 sel->info.uses_persp_center +
1664 sel->info.uses_persp_centroid +
1665 sel->info.uses_persp_sample > 1;
1666
1667 key->part.ps.prolog.force_linear_center_interp =
1668 sel->info.uses_linear_center +
1669 sel->info.uses_linear_centroid +
1670 sel->info.uses_linear_sample > 1;
1671
1672 if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
1673 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1674 }
1675
1676 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1677
1678 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1679 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
1680 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
1681 struct pipe_resource *tex = cb0->texture;
1682
1683 /* 1D textures are allocated and used as 2D on GFX9. */
1684 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
1685 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
1686 (tex->target == PIPE_TEXTURE_1D ||
1687 tex->target == PIPE_TEXTURE_1D_ARRAY);
1688 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
1689 tex->target == PIPE_TEXTURE_2D_ARRAY ||
1690 tex->target == PIPE_TEXTURE_CUBE ||
1691 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
1692 tex->target == PIPE_TEXTURE_3D;
1693 }
1694 break;
1695 }
1696 default:
1697 assert(0);
1698 }
1699
1700 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
1701 memset(&key->opt, 0, sizeof(key->opt));
1702 }
1703
1704 static void si_build_shader_variant(struct si_shader *shader,
1705 int thread_index,
1706 bool low_priority)
1707 {
1708 struct si_shader_selector *sel = shader->selector;
1709 struct si_screen *sscreen = sel->screen;
1710 struct ac_llvm_compiler *compiler;
1711 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1712
1713 if (thread_index >= 0) {
1714 if (low_priority) {
1715 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
1716 compiler = &sscreen->compiler_lowp[thread_index];
1717 } else {
1718 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
1719 compiler = &sscreen->compiler[thread_index];
1720 }
1721 if (!debug->async)
1722 debug = NULL;
1723 } else {
1724 assert(!low_priority);
1725 compiler = shader->compiler_ctx_state.compiler;
1726 }
1727
1728 if (unlikely(!si_shader_create(sscreen, compiler, shader, debug))) {
1729 PRINT_ERR("Failed to build shader variant (type=%u)\n",
1730 sel->type);
1731 shader->compilation_failed = true;
1732 return;
1733 }
1734
1735 if (shader->compiler_ctx_state.is_debug_context) {
1736 FILE *f = open_memstream(&shader->shader_log,
1737 &shader->shader_log_size);
1738 if (f) {
1739 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1740 fclose(f);
1741 }
1742 }
1743
1744 si_shader_init_pm4_state(sscreen, shader);
1745 }
1746
1747 static void si_build_shader_variant_low_priority(void *job, int thread_index)
1748 {
1749 struct si_shader *shader = (struct si_shader *)job;
1750
1751 assert(thread_index >= 0);
1752
1753 si_build_shader_variant(shader, thread_index, true);
1754 }
1755
1756 static const struct si_shader_key zeroed;
1757
1758 static bool si_check_missing_main_part(struct si_screen *sscreen,
1759 struct si_shader_selector *sel,
1760 struct si_compiler_ctx_state *compiler_state,
1761 struct si_shader_key *key)
1762 {
1763 struct si_shader **mainp = si_get_main_shader_part(sel, key);
1764
1765 if (!*mainp) {
1766 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1767
1768 if (!main_part)
1769 return false;
1770
1771 /* We can leave the fence as permanently signaled because the
1772 * main part becomes visible globally only after it has been
1773 * compiled. */
1774 util_queue_fence_init(&main_part->ready);
1775
1776 main_part->selector = sel;
1777 main_part->key.as_es = key->as_es;
1778 main_part->key.as_ls = key->as_ls;
1779 main_part->key.as_ngg = key->as_ngg;
1780 main_part->is_monolithic = false;
1781
1782 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
1783 main_part, &compiler_state->debug) != 0) {
1784 FREE(main_part);
1785 return false;
1786 }
1787 *mainp = main_part;
1788 }
1789 return true;
1790 }
1791
1792 /**
1793 * Select a shader variant according to the shader key.
1794 *
1795 * \param optimized_or_none If the key describes an optimized shader variant and
1796 * the compilation isn't finished, don't select any
1797 * shader and return an error.
1798 */
1799 int si_shader_select_with_key(struct si_screen *sscreen,
1800 struct si_shader_ctx_state *state,
1801 struct si_compiler_ctx_state *compiler_state,
1802 struct si_shader_key *key,
1803 int thread_index,
1804 bool optimized_or_none)
1805 {
1806 struct si_shader_selector *sel = state->cso;
1807 struct si_shader_selector *previous_stage_sel = NULL;
1808 struct si_shader *current = state->current;
1809 struct si_shader *iter, *shader = NULL;
1810
1811 again:
1812 /* Check if we don't need to change anything.
1813 * This path is also used for most shaders that don't need multiple
1814 * variants, it will cost just a computation of the key and this
1815 * test. */
1816 if (likely(current &&
1817 memcmp(&current->key, key, sizeof(*key)) == 0)) {
1818 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
1819 if (current->is_optimized) {
1820 if (optimized_or_none)
1821 return -1;
1822
1823 memset(&key->opt, 0, sizeof(key->opt));
1824 goto current_not_ready;
1825 }
1826
1827 util_queue_fence_wait(&current->ready);
1828 }
1829
1830 return current->compilation_failed ? -1 : 0;
1831 }
1832 current_not_ready:
1833
1834 /* This must be done before the mutex is locked, because async GS
1835 * compilation calls this function too, and therefore must enter
1836 * the mutex first.
1837 *
1838 * Only wait if we are in a draw call. Don't wait if we are
1839 * in a compiler thread.
1840 */
1841 if (thread_index < 0)
1842 util_queue_fence_wait(&sel->ready);
1843
1844 mtx_lock(&sel->mutex);
1845
1846 /* Find the shader variant. */
1847 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1848 /* Don't check the "current" shader. We checked it above. */
1849 if (current != iter &&
1850 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1851 mtx_unlock(&sel->mutex);
1852
1853 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
1854 /* If it's an optimized shader and its compilation has
1855 * been started but isn't done, use the unoptimized
1856 * shader so as not to cause a stall due to compilation.
1857 */
1858 if (iter->is_optimized) {
1859 if (optimized_or_none)
1860 return -1;
1861 memset(&key->opt, 0, sizeof(key->opt));
1862 goto again;
1863 }
1864
1865 util_queue_fence_wait(&iter->ready);
1866 }
1867
1868 if (iter->compilation_failed) {
1869 return -1; /* skip the draw call */
1870 }
1871
1872 state->current = iter;
1873 return 0;
1874 }
1875 }
1876
1877 /* Build a new shader. */
1878 shader = CALLOC_STRUCT(si_shader);
1879 if (!shader) {
1880 mtx_unlock(&sel->mutex);
1881 return -ENOMEM;
1882 }
1883
1884 util_queue_fence_init(&shader->ready);
1885
1886 shader->selector = sel;
1887 shader->key = *key;
1888 shader->compiler_ctx_state = *compiler_state;
1889
1890 /* If this is a merged shader, get the first shader's selector. */
1891 if (sscreen->info.chip_class >= GFX9) {
1892 if (sel->type == PIPE_SHADER_TESS_CTRL)
1893 previous_stage_sel = key->part.tcs.ls;
1894 else if (sel->type == PIPE_SHADER_GEOMETRY)
1895 previous_stage_sel = key->part.gs.es;
1896
1897 /* We need to wait for the previous shader. */
1898 if (previous_stage_sel && thread_index < 0)
1899 util_queue_fence_wait(&previous_stage_sel->ready);
1900 }
1901
1902 bool is_pure_monolithic =
1903 sscreen->use_monolithic_shaders ||
1904 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1905
1906 /* Compile the main shader part if it doesn't exist. This can happen
1907 * if the initial guess was wrong.
1908 *
1909 * The prim discard CS doesn't need the main shader part.
1910 */
1911 if (!is_pure_monolithic &&
1912 !key->opt.vs_as_prim_discard_cs) {
1913 bool ok = true;
1914
1915 /* Make sure the main shader part is present. This is needed
1916 * for shaders that can be compiled as VS, LS, or ES, and only
1917 * one of them is compiled at creation.
1918 *
1919 * It is also needed for GS, which can be compiled as non-NGG
1920 * and NGG.
1921 *
1922 * For merged shaders, check that the starting shader's main
1923 * part is present.
1924 */
1925 if (previous_stage_sel) {
1926 struct si_shader_key shader1_key = zeroed;
1927
1928 if (sel->type == PIPE_SHADER_TESS_CTRL)
1929 shader1_key.as_ls = 1;
1930 else if (sel->type == PIPE_SHADER_GEOMETRY)
1931 shader1_key.as_es = 1;
1932 else
1933 assert(0);
1934
1935 mtx_lock(&previous_stage_sel->mutex);
1936 ok = si_check_missing_main_part(sscreen,
1937 previous_stage_sel,
1938 compiler_state, &shader1_key);
1939 mtx_unlock(&previous_stage_sel->mutex);
1940 }
1941
1942 if (ok) {
1943 ok = si_check_missing_main_part(sscreen, sel,
1944 compiler_state, key);
1945 }
1946
1947 if (!ok) {
1948 FREE(shader);
1949 mtx_unlock(&sel->mutex);
1950 return -ENOMEM; /* skip the draw call */
1951 }
1952 }
1953
1954 /* Keep the reference to the 1st shader of merged shaders, so that
1955 * Gallium can't destroy it before we destroy the 2nd shader.
1956 *
1957 * Set sctx = NULL, because it's unused if we're not releasing
1958 * the shader, and we don't have any sctx here.
1959 */
1960 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
1961 previous_stage_sel);
1962
1963 /* Monolithic-only shaders don't make a distinction between optimized
1964 * and unoptimized. */
1965 shader->is_monolithic =
1966 is_pure_monolithic ||
1967 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1968
1969 /* The prim discard CS is always optimized. */
1970 shader->is_optimized =
1971 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
1972 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1973
1974 /* If it's an optimized shader, compile it asynchronously. */
1975 if (shader->is_optimized && thread_index < 0) {
1976 /* Compile it asynchronously. */
1977 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
1978 shader, &shader->ready,
1979 si_build_shader_variant_low_priority, NULL);
1980
1981 /* Add only after the ready fence was reset, to guard against a
1982 * race with si_bind_XX_shader. */
1983 if (!sel->last_variant) {
1984 sel->first_variant = shader;
1985 sel->last_variant = shader;
1986 } else {
1987 sel->last_variant->next_variant = shader;
1988 sel->last_variant = shader;
1989 }
1990
1991 /* Use the default (unoptimized) shader for now. */
1992 memset(&key->opt, 0, sizeof(key->opt));
1993 mtx_unlock(&sel->mutex);
1994
1995 if (sscreen->options.sync_compile)
1996 util_queue_fence_wait(&shader->ready);
1997
1998 if (optimized_or_none)
1999 return -1;
2000 goto again;
2001 }
2002
2003 /* Reset the fence before adding to the variant list. */
2004 util_queue_fence_reset(&shader->ready);
2005
2006 if (!sel->last_variant) {
2007 sel->first_variant = shader;
2008 sel->last_variant = shader;
2009 } else {
2010 sel->last_variant->next_variant = shader;
2011 sel->last_variant = shader;
2012 }
2013
2014 mtx_unlock(&sel->mutex);
2015
2016 assert(!shader->is_optimized);
2017 si_build_shader_variant(shader, thread_index, false);
2018
2019 util_queue_fence_signal(&shader->ready);
2020
2021 if (!shader->compilation_failed)
2022 state->current = shader;
2023
2024 return shader->compilation_failed ? -1 : 0;
2025 }
2026
2027 static int si_shader_select(struct pipe_context *ctx,
2028 struct si_shader_ctx_state *state,
2029 union si_vgt_stages_key stages_key,
2030 struct si_compiler_ctx_state *compiler_state)
2031 {
2032 struct si_context *sctx = (struct si_context *)ctx;
2033 struct si_shader_key key;
2034
2035 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2036 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2037 &key, -1, false);
2038 }
2039
2040 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
2041 bool streamout,
2042 struct si_shader_key *key)
2043 {
2044 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2045
2046 switch (info->processor) {
2047 case PIPE_SHADER_VERTEX:
2048 switch (next_shader) {
2049 case PIPE_SHADER_GEOMETRY:
2050 key->as_es = 1;
2051 break;
2052 case PIPE_SHADER_TESS_CTRL:
2053 case PIPE_SHADER_TESS_EVAL:
2054 key->as_ls = 1;
2055 break;
2056 default:
2057 /* If POSITION isn't written, it can only be a HW VS
2058 * if streamout is used. If streamout isn't used,
2059 * assume that it's a HW LS. (the next shader is TCS)
2060 * This heuristic is needed for separate shader objects.
2061 */
2062 if (!info->writes_position && !streamout)
2063 key->as_ls = 1;
2064 }
2065 break;
2066
2067 case PIPE_SHADER_TESS_EVAL:
2068 if (next_shader == PIPE_SHADER_GEOMETRY ||
2069 !info->writes_position)
2070 key->as_es = 1;
2071 break;
2072 }
2073 }
2074
2075 /**
2076 * Compile the main shader part or the monolithic shader as part of
2077 * si_shader_selector initialization. Since it can be done asynchronously,
2078 * there is no way to report compile failures to applications.
2079 */
2080 static void si_init_shader_selector_async(void *job, int thread_index)
2081 {
2082 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2083 struct si_screen *sscreen = sel->screen;
2084 struct ac_llvm_compiler *compiler;
2085 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2086
2087 assert(!debug->debug_message || debug->async);
2088 assert(thread_index >= 0);
2089 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2090 compiler = &sscreen->compiler[thread_index];
2091
2092 if (sel->nir)
2093 si_lower_nir(sel);
2094
2095 /* Compile the main shader part for use with a prolog and/or epilog.
2096 * If this fails, the driver will try to compile a monolithic shader
2097 * on demand.
2098 */
2099 if (!sscreen->use_monolithic_shaders) {
2100 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2101 void *ir_binary = NULL;
2102
2103 if (!shader) {
2104 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2105 return;
2106 }
2107
2108 /* We can leave the fence signaled because use of the default
2109 * main part is guarded by the selector's ready fence. */
2110 util_queue_fence_init(&shader->ready);
2111
2112 shader->selector = sel;
2113 shader->is_monolithic = false;
2114 si_parse_next_shader_property(&sel->info,
2115 sel->so.num_outputs != 0,
2116 &shader->key);
2117 if (sscreen->info.chip_class >= GFX10 &&
2118 !sscreen->options.disable_ngg &&
2119 (((sel->type == PIPE_SHADER_VERTEX ||
2120 sel->type == PIPE_SHADER_TESS_EVAL) &&
2121 !shader->key.as_ls && !shader->key.as_es) ||
2122 sel->type == PIPE_SHADER_GEOMETRY))
2123 shader->key.as_ngg = 1;
2124
2125 if (sel->tokens || sel->nir)
2126 ir_binary = si_get_ir_binary(sel);
2127
2128 /* Try to load the shader from the shader cache. */
2129 mtx_lock(&sscreen->shader_cache_mutex);
2130
2131 if (ir_binary &&
2132 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
2133 mtx_unlock(&sscreen->shader_cache_mutex);
2134 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2135 } else {
2136 mtx_unlock(&sscreen->shader_cache_mutex);
2137
2138 /* Compile the shader if it hasn't been loaded from the cache. */
2139 if (si_compile_tgsi_shader(sscreen, compiler, shader,
2140 debug) != 0) {
2141 FREE(shader);
2142 FREE(ir_binary);
2143 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2144 return;
2145 }
2146
2147 if (ir_binary) {
2148 mtx_lock(&sscreen->shader_cache_mutex);
2149 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
2150 FREE(ir_binary);
2151 mtx_unlock(&sscreen->shader_cache_mutex);
2152 }
2153 }
2154
2155 *si_get_main_shader_part(sel, &shader->key) = shader;
2156
2157 /* Unset "outputs_written" flags for outputs converted to
2158 * DEFAULT_VAL, so that later inter-shader optimizations don't
2159 * try to eliminate outputs that don't exist in the final
2160 * shader.
2161 *
2162 * This is only done if non-monolithic shaders are enabled.
2163 */
2164 if ((sel->type == PIPE_SHADER_VERTEX ||
2165 sel->type == PIPE_SHADER_TESS_EVAL) &&
2166 !shader->key.as_ls &&
2167 !shader->key.as_es) {
2168 unsigned i;
2169
2170 for (i = 0; i < sel->info.num_outputs; i++) {
2171 unsigned offset = shader->info.vs_output_param_offset[i];
2172
2173 if (offset <= AC_EXP_PARAM_OFFSET_31)
2174 continue;
2175
2176 unsigned name = sel->info.output_semantic_name[i];
2177 unsigned index = sel->info.output_semantic_index[i];
2178 unsigned id;
2179
2180 switch (name) {
2181 case TGSI_SEMANTIC_GENERIC:
2182 /* don't process indices the function can't handle */
2183 if (index >= SI_MAX_IO_GENERIC)
2184 break;
2185 /* fall through */
2186 default:
2187 id = si_shader_io_get_unique_index(name, index, true);
2188 sel->outputs_written_before_ps &= ~(1ull << id);
2189 break;
2190 case TGSI_SEMANTIC_POSITION: /* ignore these */
2191 case TGSI_SEMANTIC_PSIZE:
2192 case TGSI_SEMANTIC_CLIPVERTEX:
2193 case TGSI_SEMANTIC_EDGEFLAG:
2194 break;
2195 }
2196 }
2197 }
2198 }
2199
2200 /* The GS copy shader is always pre-compiled. */
2201 if (sel->type == PIPE_SHADER_GEOMETRY) {
2202 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2203 if (!sel->gs_copy_shader) {
2204 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2205 return;
2206 }
2207
2208 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2209 }
2210 }
2211
2212 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2213 struct util_queue_fence *ready_fence,
2214 struct si_compiler_ctx_state *compiler_ctx_state,
2215 void *job, util_queue_execute_func execute)
2216 {
2217 util_queue_fence_init(ready_fence);
2218
2219 struct util_async_debug_callback async_debug;
2220 bool debug =
2221 (sctx->debug.debug_message && !sctx->debug.async) ||
2222 sctx->is_debug ||
2223 si_can_dump_shader(sctx->screen, processor);
2224
2225 if (debug) {
2226 u_async_debug_init(&async_debug);
2227 compiler_ctx_state->debug = async_debug.base;
2228 }
2229
2230 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2231 ready_fence, execute, NULL);
2232
2233 if (debug) {
2234 util_queue_fence_wait(ready_fence);
2235 u_async_debug_drain(&async_debug, &sctx->debug);
2236 u_async_debug_cleanup(&async_debug);
2237 }
2238
2239 if (sctx->screen->options.sync_compile)
2240 util_queue_fence_wait(ready_fence);
2241 }
2242
2243 /* Return descriptor slot usage masks from the given shader info. */
2244 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2245 uint32_t *const_and_shader_buffers,
2246 uint64_t *samplers_and_images)
2247 {
2248 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2249
2250 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2251 num_constbufs = util_last_bit(info->const_buffers_declared);
2252 /* two 8-byte images share one 16-byte slot */
2253 num_images = align(util_last_bit(info->images_declared), 2);
2254 num_samplers = util_last_bit(info->samplers_declared);
2255
2256 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2257 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2258 *const_and_shader_buffers =
2259 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2260
2261 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2262 start = si_get_image_slot(num_images - 1) / 2;
2263 *samplers_and_images =
2264 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2265 }
2266
2267 static void *si_create_shader_selector(struct pipe_context *ctx,
2268 const struct pipe_shader_state *state)
2269 {
2270 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2271 struct si_context *sctx = (struct si_context*)ctx;
2272 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2273 int i;
2274
2275 if (!sel)
2276 return NULL;
2277
2278 pipe_reference_init(&sel->reference, 1);
2279 sel->screen = sscreen;
2280 sel->compiler_ctx_state.debug = sctx->debug;
2281 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2282
2283 sel->so = state->stream_output;
2284
2285 if (state->type == PIPE_SHADER_IR_TGSI) {
2286 sel->tokens = tgsi_dup_tokens(state->tokens);
2287 if (!sel->tokens) {
2288 FREE(sel);
2289 return NULL;
2290 }
2291
2292 tgsi_scan_shader(state->tokens, &sel->info);
2293 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2294 } else {
2295 assert(state->type == PIPE_SHADER_IR_NIR);
2296
2297 sel->nir = state->ir.nir;
2298
2299 si_nir_opts(sel->nir);
2300 si_nir_scan_shader(sel->nir, &sel->info);
2301 si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
2302 }
2303
2304 sel->type = sel->info.processor;
2305 p_atomic_inc(&sscreen->num_shaders_created);
2306 si_get_active_slot_masks(&sel->info,
2307 &sel->active_const_and_shader_buffers,
2308 &sel->active_samplers_and_images);
2309
2310 /* Record which streamout buffers are enabled. */
2311 for (i = 0; i < sel->so.num_outputs; i++) {
2312 sel->enabled_streamout_buffer_mask |=
2313 (1 << sel->so.output[i].output_buffer) <<
2314 (sel->so.output[i].stream * 4);
2315 }
2316
2317 /* The prolog is a no-op if there are no inputs. */
2318 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2319 sel->info.num_inputs &&
2320 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2321
2322 sel->force_correct_derivs_after_kill =
2323 sel->type == PIPE_SHADER_FRAGMENT &&
2324 sel->info.uses_derivatives &&
2325 sel->info.uses_kill &&
2326 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2327
2328 sel->prim_discard_cs_allowed =
2329 sel->type == PIPE_SHADER_VERTEX &&
2330 !sel->info.uses_bindless_images &&
2331 !sel->info.uses_bindless_samplers &&
2332 !sel->info.writes_memory &&
2333 !sel->info.writes_viewport_index &&
2334 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2335 !sel->so.num_outputs;
2336
2337 /* Set which opcode uses which (i,j) pair. */
2338 if (sel->info.uses_persp_opcode_interp_centroid)
2339 sel->info.uses_persp_centroid = true;
2340
2341 if (sel->info.uses_linear_opcode_interp_centroid)
2342 sel->info.uses_linear_centroid = true;
2343
2344 if (sel->info.uses_persp_opcode_interp_offset ||
2345 sel->info.uses_persp_opcode_interp_sample)
2346 sel->info.uses_persp_center = true;
2347
2348 if (sel->info.uses_linear_opcode_interp_offset ||
2349 sel->info.uses_linear_opcode_interp_sample)
2350 sel->info.uses_linear_center = true;
2351
2352 switch (sel->type) {
2353 case PIPE_SHADER_GEOMETRY:
2354 sel->gs_output_prim =
2355 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2356 sel->gs_max_out_vertices =
2357 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2358 sel->gs_num_invocations =
2359 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2360 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2361 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2362 sel->gs_max_out_vertices;
2363
2364 sel->max_gs_stream = 0;
2365 for (i = 0; i < sel->so.num_outputs; i++)
2366 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2367 sel->so.output[i].stream);
2368
2369 sel->gs_input_verts_per_prim =
2370 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2371 break;
2372
2373 case PIPE_SHADER_TESS_CTRL:
2374 /* Always reserve space for these. */
2375 sel->patch_outputs_written |=
2376 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2377 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2378 /* fall through */
2379 case PIPE_SHADER_VERTEX:
2380 case PIPE_SHADER_TESS_EVAL:
2381 for (i = 0; i < sel->info.num_outputs; i++) {
2382 unsigned name = sel->info.output_semantic_name[i];
2383 unsigned index = sel->info.output_semantic_index[i];
2384
2385 switch (name) {
2386 case TGSI_SEMANTIC_TESSINNER:
2387 case TGSI_SEMANTIC_TESSOUTER:
2388 case TGSI_SEMANTIC_PATCH:
2389 sel->patch_outputs_written |=
2390 1ull << si_shader_io_get_unique_index_patch(name, index);
2391 break;
2392
2393 case TGSI_SEMANTIC_GENERIC:
2394 /* don't process indices the function can't handle */
2395 if (index >= SI_MAX_IO_GENERIC)
2396 break;
2397 /* fall through */
2398 default:
2399 sel->outputs_written |=
2400 1ull << si_shader_io_get_unique_index(name, index, false);
2401 sel->outputs_written_before_ps |=
2402 1ull << si_shader_io_get_unique_index(name, index, true);
2403 break;
2404 case TGSI_SEMANTIC_EDGEFLAG:
2405 break;
2406 }
2407 }
2408 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2409 sel->lshs_vertex_stride = sel->esgs_itemsize;
2410
2411 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2412 * will start on a different bank. (except for the maximum 32*16).
2413 */
2414 if (sel->lshs_vertex_stride < 32*16)
2415 sel->lshs_vertex_stride += 4;
2416
2417 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2418 * conflicts, i.e. each vertex will start at a different bank.
2419 */
2420 if (sctx->chip_class >= GFX9)
2421 sel->esgs_itemsize += 4;
2422
2423 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2424 break;
2425
2426 case PIPE_SHADER_FRAGMENT:
2427 for (i = 0; i < sel->info.num_inputs; i++) {
2428 unsigned name = sel->info.input_semantic_name[i];
2429 unsigned index = sel->info.input_semantic_index[i];
2430
2431 switch (name) {
2432 case TGSI_SEMANTIC_GENERIC:
2433 /* don't process indices the function can't handle */
2434 if (index >= SI_MAX_IO_GENERIC)
2435 break;
2436 /* fall through */
2437 default:
2438 sel->inputs_read |=
2439 1ull << si_shader_io_get_unique_index(name, index, true);
2440 break;
2441 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2442 break;
2443 }
2444 }
2445
2446 for (i = 0; i < 8; i++)
2447 if (sel->info.colors_written & (1 << i))
2448 sel->colors_written_4bit |= 0xf << (4 * i);
2449
2450 for (i = 0; i < sel->info.num_inputs; i++) {
2451 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2452 int index = sel->info.input_semantic_index[i];
2453 sel->color_attr_index[index] = i;
2454 }
2455 }
2456 break;
2457 }
2458
2459 /* PA_CL_VS_OUT_CNTL */
2460 bool misc_vec_ena =
2461 sel->info.writes_psize || sel->info.writes_edgeflag ||
2462 sel->info.writes_layer || sel->info.writes_viewport_index;
2463 sel->pa_cl_vs_out_cntl =
2464 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2465 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2466 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2467 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2468 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2469 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2470 sel->clipdist_mask = sel->info.writes_clipvertex ?
2471 SIX_BITS : sel->info.clipdist_writemask;
2472 sel->culldist_mask = sel->info.culldist_writemask <<
2473 sel->info.num_written_clipdistance;
2474
2475 /* DB_SHADER_CONTROL */
2476 sel->db_shader_control =
2477 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2478 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2479 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2480 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2481
2482 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2483 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2484 sel->db_shader_control |=
2485 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2486 break;
2487 case TGSI_FS_DEPTH_LAYOUT_LESS:
2488 sel->db_shader_control |=
2489 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2490 break;
2491 }
2492
2493 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2494 *
2495 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2496 * --|-----------|------------|------------|--------------------|-------------------|-------------
2497 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2498 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2499 * 2 | false | true | n/a | LateZ | 1 | 0
2500 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2501 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2502 *
2503 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2504 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2505 *
2506 * Don't use ReZ without profiling !!!
2507 *
2508 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2509 * shaders.
2510 */
2511 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2512 /* Cases 3, 4. */
2513 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2514 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2515 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2516 } else if (sel->info.writes_memory) {
2517 /* Case 2. */
2518 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2519 S_02880C_EXEC_ON_HIER_FAIL(1);
2520 } else {
2521 /* Case 1. */
2522 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2523 }
2524
2525 (void) mtx_init(&sel->mutex, mtx_plain);
2526
2527 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2528 &sel->compiler_ctx_state, sel,
2529 si_init_shader_selector_async);
2530 return sel;
2531 }
2532
2533 static void si_update_streamout_state(struct si_context *sctx)
2534 {
2535 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2536
2537 if (!shader_with_so)
2538 return;
2539
2540 sctx->streamout.enabled_stream_buffers_mask =
2541 shader_with_so->enabled_streamout_buffer_mask;
2542 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2543 }
2544
2545 static void si_update_clip_regs(struct si_context *sctx,
2546 struct si_shader_selector *old_hw_vs,
2547 struct si_shader *old_hw_vs_variant,
2548 struct si_shader_selector *next_hw_vs,
2549 struct si_shader *next_hw_vs_variant)
2550 {
2551 if (next_hw_vs &&
2552 (!old_hw_vs ||
2553 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2554 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2555 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2556 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2557 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2558 !old_hw_vs_variant ||
2559 !next_hw_vs_variant ||
2560 old_hw_vs_variant->key.opt.clip_disable !=
2561 next_hw_vs_variant->key.opt.clip_disable))
2562 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2563 }
2564
2565 static void si_update_common_shader_state(struct si_context *sctx)
2566 {
2567 sctx->uses_bindless_samplers =
2568 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2569 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2570 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2571 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2572 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2573 sctx->uses_bindless_images =
2574 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2575 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2576 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2577 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2578 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2579 sctx->do_update_shaders = true;
2580 }
2581
2582 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2583 {
2584 struct si_context *sctx = (struct si_context *)ctx;
2585 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2586 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2587 struct si_shader_selector *sel = state;
2588
2589 if (sctx->vs_shader.cso == sel)
2590 return;
2591
2592 sctx->vs_shader.cso = sel;
2593 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2594 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2595
2596 si_update_common_shader_state(sctx);
2597 si_update_vs_viewport_state(sctx);
2598 si_set_active_descriptors_for_shader(sctx, sel);
2599 si_update_streamout_state(sctx);
2600 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2601 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2602 }
2603
2604 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2605 {
2606 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2607 (sctx->tes_shader.cso &&
2608 sctx->tes_shader.cso->info.uses_primid) ||
2609 (sctx->tcs_shader.cso &&
2610 sctx->tcs_shader.cso->info.uses_primid) ||
2611 (sctx->gs_shader.cso &&
2612 sctx->gs_shader.cso->info.uses_primid) ||
2613 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2614 sctx->ps_shader.cso->info.uses_primid);
2615 }
2616
2617 static bool si_update_ngg(struct si_context *sctx)
2618 {
2619 if (sctx->chip_class <= GFX9 ||
2620 sctx->screen->options.disable_ngg)
2621 return false;
2622
2623 bool new_ngg = true;
2624
2625 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2626 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
2627 sctx->gs_shader.cso->gs_num_invocations * sctx->gs_shader.cso->gs_max_out_vertices > 256)
2628 new_ngg = false;
2629
2630 if (new_ngg != sctx->ngg) {
2631 sctx->ngg = new_ngg;
2632 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2633 return true;
2634 }
2635 return false;
2636 }
2637
2638 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2639 {
2640 struct si_context *sctx = (struct si_context *)ctx;
2641 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2642 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2643 struct si_shader_selector *sel = state;
2644 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2645 bool ngg_changed;
2646
2647 if (sctx->gs_shader.cso == sel)
2648 return;
2649
2650 sctx->gs_shader.cso = sel;
2651 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2652 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2653
2654 si_update_common_shader_state(sctx);
2655 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2656
2657 ngg_changed = si_update_ngg(sctx);
2658 if (ngg_changed || enable_changed)
2659 si_shader_change_notify(sctx);
2660 if (enable_changed) {
2661 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2662 si_update_tess_uses_prim_id(sctx);
2663 }
2664 si_update_vs_viewport_state(sctx);
2665 si_set_active_descriptors_for_shader(sctx, sel);
2666 si_update_streamout_state(sctx);
2667 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2668 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2669 }
2670
2671 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2672 {
2673 struct si_context *sctx = (struct si_context *)ctx;
2674 struct si_shader_selector *sel = state;
2675 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2676
2677 if (sctx->tcs_shader.cso == sel)
2678 return;
2679
2680 sctx->tcs_shader.cso = sel;
2681 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
2682 si_update_tess_uses_prim_id(sctx);
2683
2684 si_update_common_shader_state(sctx);
2685
2686 if (enable_changed)
2687 sctx->last_tcs = NULL; /* invalidate derived tess state */
2688
2689 si_set_active_descriptors_for_shader(sctx, sel);
2690 }
2691
2692 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
2693 {
2694 struct si_context *sctx = (struct si_context *)ctx;
2695 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2696 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2697 struct si_shader_selector *sel = state;
2698 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
2699
2700 if (sctx->tes_shader.cso == sel)
2701 return;
2702
2703 sctx->tes_shader.cso = sel;
2704 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
2705 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
2706 si_update_tess_uses_prim_id(sctx);
2707
2708 si_update_common_shader_state(sctx);
2709 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2710
2711 if (enable_changed) {
2712 si_update_ngg(sctx);
2713 si_shader_change_notify(sctx);
2714 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
2715 }
2716 si_update_vs_viewport_state(sctx);
2717 si_set_active_descriptors_for_shader(sctx, sel);
2718 si_update_streamout_state(sctx);
2719 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2720 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2721 }
2722
2723 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2724 {
2725 struct si_context *sctx = (struct si_context *)ctx;
2726 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
2727 struct si_shader_selector *sel = state;
2728
2729 /* skip if supplied shader is one already in use */
2730 if (old_sel == sel)
2731 return;
2732
2733 sctx->ps_shader.cso = sel;
2734 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
2735
2736 si_update_common_shader_state(sctx);
2737 if (sel) {
2738 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2739 si_update_tess_uses_prim_id(sctx);
2740
2741 if (!old_sel ||
2742 old_sel->info.colors_written != sel->info.colors_written)
2743 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2744
2745 if (sctx->screen->has_out_of_order_rast &&
2746 (!old_sel ||
2747 old_sel->info.writes_memory != sel->info.writes_memory ||
2748 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
2749 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
2750 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2751 }
2752 si_set_active_descriptors_for_shader(sctx, sel);
2753 si_update_ps_colorbuf0_slot(sctx);
2754 }
2755
2756 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
2757 {
2758 if (shader->is_optimized) {
2759 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
2760 &shader->ready);
2761 }
2762
2763 util_queue_fence_destroy(&shader->ready);
2764
2765 if (shader->pm4) {
2766 switch (shader->selector->type) {
2767 case PIPE_SHADER_VERTEX:
2768 if (shader->key.as_ls) {
2769 assert(sctx->chip_class <= GFX8);
2770 si_pm4_delete_state(sctx, ls, shader->pm4);
2771 } else if (shader->key.as_es) {
2772 assert(sctx->chip_class <= GFX8);
2773 si_pm4_delete_state(sctx, es, shader->pm4);
2774 } else {
2775 si_pm4_delete_state(sctx, vs, shader->pm4);
2776 }
2777 break;
2778 case PIPE_SHADER_TESS_CTRL:
2779 si_pm4_delete_state(sctx, hs, shader->pm4);
2780 break;
2781 case PIPE_SHADER_TESS_EVAL:
2782 if (shader->key.as_es) {
2783 assert(sctx->chip_class <= GFX8);
2784 si_pm4_delete_state(sctx, es, shader->pm4);
2785 } else {
2786 si_pm4_delete_state(sctx, vs, shader->pm4);
2787 }
2788 break;
2789 case PIPE_SHADER_GEOMETRY:
2790 if (shader->is_gs_copy_shader)
2791 si_pm4_delete_state(sctx, vs, shader->pm4);
2792 else
2793 si_pm4_delete_state(sctx, gs, shader->pm4);
2794 break;
2795 case PIPE_SHADER_FRAGMENT:
2796 si_pm4_delete_state(sctx, ps, shader->pm4);
2797 break;
2798 }
2799 }
2800
2801 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
2802 si_shader_destroy(shader);
2803 free(shader);
2804 }
2805
2806 void si_destroy_shader_selector(struct si_context *sctx,
2807 struct si_shader_selector *sel)
2808 {
2809 struct si_shader *p = sel->first_variant, *c;
2810 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
2811 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
2812 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
2813 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
2814 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
2815 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
2816 };
2817
2818 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
2819
2820 if (current_shader[sel->type]->cso == sel) {
2821 current_shader[sel->type]->cso = NULL;
2822 current_shader[sel->type]->current = NULL;
2823 }
2824
2825 while (p) {
2826 c = p->next_variant;
2827 si_delete_shader(sctx, p);
2828 p = c;
2829 }
2830
2831 if (sel->main_shader_part)
2832 si_delete_shader(sctx, sel->main_shader_part);
2833 if (sel->main_shader_part_ls)
2834 si_delete_shader(sctx, sel->main_shader_part_ls);
2835 if (sel->main_shader_part_es)
2836 si_delete_shader(sctx, sel->main_shader_part_es);
2837 if (sel->main_shader_part_ngg)
2838 si_delete_shader(sctx, sel->main_shader_part_ngg);
2839 if (sel->gs_copy_shader)
2840 si_delete_shader(sctx, sel->gs_copy_shader);
2841
2842 util_queue_fence_destroy(&sel->ready);
2843 mtx_destroy(&sel->mutex);
2844 free(sel->tokens);
2845 ralloc_free(sel->nir);
2846 free(sel);
2847 }
2848
2849 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
2850 {
2851 struct si_context *sctx = (struct si_context *)ctx;
2852 struct si_shader_selector *sel = (struct si_shader_selector *)state;
2853
2854 si_shader_selector_reference(sctx, &sel, NULL);
2855 }
2856
2857 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
2858 struct si_shader *vs, unsigned name,
2859 unsigned index, unsigned interpolate)
2860 {
2861 struct tgsi_shader_info *vsinfo = &vs->selector->info;
2862 unsigned j, offset, ps_input_cntl = 0;
2863
2864 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
2865 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
2866 name == TGSI_SEMANTIC_PRIMID)
2867 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2868
2869 if (name == TGSI_SEMANTIC_PCOORD ||
2870 (name == TGSI_SEMANTIC_TEXCOORD &&
2871 sctx->sprite_coord_enable & (1 << index))) {
2872 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
2873 }
2874
2875 for (j = 0; j < vsinfo->num_outputs; j++) {
2876 if (name == vsinfo->output_semantic_name[j] &&
2877 index == vsinfo->output_semantic_index[j]) {
2878 offset = vs->info.vs_output_param_offset[j];
2879
2880 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2881 /* The input is loaded from parameter memory. */
2882 ps_input_cntl |= S_028644_OFFSET(offset);
2883 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2884 if (offset == AC_EXP_PARAM_UNDEFINED) {
2885 /* This can happen with depth-only rendering. */
2886 offset = 0;
2887 } else {
2888 /* The input is a DEFAULT_VAL constant. */
2889 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2890 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2891 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2892 }
2893
2894 ps_input_cntl = S_028644_OFFSET(0x20) |
2895 S_028644_DEFAULT_VAL(offset);
2896 }
2897 break;
2898 }
2899 }
2900
2901 if (name == TGSI_SEMANTIC_PRIMID)
2902 /* PrimID is written after the last output. */
2903 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
2904 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2905 /* No corresponding output found, load defaults into input.
2906 * Don't set any other bits.
2907 * (FLAT_SHADE=1 completely changes behavior) */
2908 ps_input_cntl = S_028644_OFFSET(0x20);
2909 /* D3D 9 behaviour. GL is undefined */
2910 if (name == TGSI_SEMANTIC_COLOR && index == 0)
2911 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
2912 }
2913 return ps_input_cntl;
2914 }
2915
2916 static void si_emit_spi_map(struct si_context *sctx)
2917 {
2918 struct si_shader *ps = sctx->ps_shader.current;
2919 struct si_shader *vs = si_get_vs_state(sctx);
2920 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
2921 unsigned i, num_interp, num_written = 0, bcol_interp[2];
2922 unsigned spi_ps_input_cntl[32];
2923
2924 if (!ps || !ps->selector->info.num_inputs)
2925 return;
2926
2927 num_interp = si_get_ps_num_interp(ps);
2928 assert(num_interp > 0);
2929
2930 for (i = 0; i < psinfo->num_inputs; i++) {
2931 unsigned name = psinfo->input_semantic_name[i];
2932 unsigned index = psinfo->input_semantic_index[i];
2933 unsigned interpolate = psinfo->input_interpolate[i];
2934
2935 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
2936 index, interpolate);
2937
2938 if (name == TGSI_SEMANTIC_COLOR) {
2939 assert(index < ARRAY_SIZE(bcol_interp));
2940 bcol_interp[index] = interpolate;
2941 }
2942 }
2943
2944 if (ps->key.part.ps.prolog.color_two_side) {
2945 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
2946
2947 for (i = 0; i < 2; i++) {
2948 if (!(psinfo->colors_read & (0xf << (i * 4))))
2949 continue;
2950
2951 spi_ps_input_cntl[num_written++] =
2952 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
2953
2954 }
2955 }
2956 assert(num_interp == num_written);
2957
2958 /* R_028644_SPI_PS_INPUT_CNTL_0 */
2959 /* Dota 2: Only ~16% of SPI map updates set different values. */
2960 /* Talos: Only ~9% of SPI map updates set different values. */
2961 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
2962 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
2963 spi_ps_input_cntl,
2964 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
2965
2966 if (initial_cdw != sctx->gfx_cs->current.cdw)
2967 sctx->context_roll = true;
2968 }
2969
2970 /**
2971 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2972 */
2973 static void si_init_config_add_vgt_flush(struct si_context *sctx)
2974 {
2975 if (sctx->init_config_has_vgt_flush)
2976 return;
2977
2978 /* Done by Vulkan before VGT_FLUSH. */
2979 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2980 si_pm4_cmd_add(sctx->init_config,
2981 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2982 si_pm4_cmd_end(sctx->init_config, false);
2983
2984 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2985 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2986 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2987 si_pm4_cmd_end(sctx->init_config, false);
2988 sctx->init_config_has_vgt_flush = true;
2989 }
2990
2991 /* Initialize state related to ESGS / GSVS ring buffers */
2992 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2993 {
2994 struct si_shader_selector *es =
2995 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2996 struct si_shader_selector *gs = sctx->gs_shader.cso;
2997 struct si_pm4_state *pm4;
2998
2999 /* Chip constants. */
3000 unsigned num_se = sctx->screen->info.max_se;
3001 unsigned wave_size = 64;
3002 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3003 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3004 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3005 */
3006 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3007 unsigned alignment = 256 * num_se;
3008 /* The maximum size is 63.999 MB per SE. */
3009 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3010
3011 /* Calculate the minimum size. */
3012 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3013 wave_size, alignment);
3014
3015 /* These are recommended sizes, not minimum sizes. */
3016 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3017 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3018 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3019 gs->max_gsvs_emit_size;
3020
3021 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3022 esgs_ring_size = align(esgs_ring_size, alignment);
3023 gsvs_ring_size = align(gsvs_ring_size, alignment);
3024
3025 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3026 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3027
3028 /* Some rings don't have to be allocated if shaders don't use them.
3029 * (e.g. no varyings between ES and GS or GS and VS)
3030 *
3031 * GFX9 doesn't have the ESGS ring.
3032 */
3033 bool update_esgs = sctx->chip_class <= GFX8 &&
3034 esgs_ring_size &&
3035 (!sctx->esgs_ring ||
3036 sctx->esgs_ring->width0 < esgs_ring_size);
3037 bool update_gsvs = gsvs_ring_size &&
3038 (!sctx->gsvs_ring ||
3039 sctx->gsvs_ring->width0 < gsvs_ring_size);
3040
3041 if (!update_esgs && !update_gsvs)
3042 return true;
3043
3044 if (update_esgs) {
3045 pipe_resource_reference(&sctx->esgs_ring, NULL);
3046 sctx->esgs_ring =
3047 pipe_aligned_buffer_create(sctx->b.screen,
3048 SI_RESOURCE_FLAG_UNMAPPABLE,
3049 PIPE_USAGE_DEFAULT,
3050 esgs_ring_size, alignment);
3051 if (!sctx->esgs_ring)
3052 return false;
3053 }
3054
3055 if (update_gsvs) {
3056 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3057 sctx->gsvs_ring =
3058 pipe_aligned_buffer_create(sctx->b.screen,
3059 SI_RESOURCE_FLAG_UNMAPPABLE,
3060 PIPE_USAGE_DEFAULT,
3061 gsvs_ring_size, alignment);
3062 if (!sctx->gsvs_ring)
3063 return false;
3064 }
3065
3066 /* Create the "init_config_gs_rings" state. */
3067 pm4 = CALLOC_STRUCT(si_pm4_state);
3068 if (!pm4)
3069 return false;
3070
3071 if (sctx->chip_class >= GFX7) {
3072 if (sctx->esgs_ring) {
3073 assert(sctx->chip_class <= GFX8);
3074 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3075 sctx->esgs_ring->width0 / 256);
3076 }
3077 if (sctx->gsvs_ring)
3078 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3079 sctx->gsvs_ring->width0 / 256);
3080 } else {
3081 if (sctx->esgs_ring)
3082 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3083 sctx->esgs_ring->width0 / 256);
3084 if (sctx->gsvs_ring)
3085 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3086 sctx->gsvs_ring->width0 / 256);
3087 }
3088
3089 /* Set the state. */
3090 if (sctx->init_config_gs_rings)
3091 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3092 sctx->init_config_gs_rings = pm4;
3093
3094 if (!sctx->init_config_has_vgt_flush) {
3095 si_init_config_add_vgt_flush(sctx);
3096 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3097 }
3098
3099 /* Flush the context to re-emit both init_config states. */
3100 sctx->initial_gfx_cs_size = 0; /* force flush */
3101 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3102
3103 /* Set ring bindings. */
3104 if (sctx->esgs_ring) {
3105 assert(sctx->chip_class <= GFX8);
3106 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3107 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3108 true, true, 4, 64, 0);
3109 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3110 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3111 false, false, 0, 0, 0);
3112 }
3113 if (sctx->gsvs_ring) {
3114 si_set_ring_buffer(sctx, SI_RING_GSVS,
3115 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3116 false, false, 0, 0, 0);
3117 }
3118
3119 return true;
3120 }
3121
3122 static void si_shader_lock(struct si_shader *shader)
3123 {
3124 mtx_lock(&shader->selector->mutex);
3125 if (shader->previous_stage_sel) {
3126 assert(shader->previous_stage_sel != shader->selector);
3127 mtx_lock(&shader->previous_stage_sel->mutex);
3128 }
3129 }
3130
3131 static void si_shader_unlock(struct si_shader *shader)
3132 {
3133 if (shader->previous_stage_sel)
3134 mtx_unlock(&shader->previous_stage_sel->mutex);
3135 mtx_unlock(&shader->selector->mutex);
3136 }
3137
3138 /**
3139 * @returns 1 if \p sel has been updated to use a new scratch buffer
3140 * 0 if not
3141 * < 0 if there was a failure
3142 */
3143 static int si_update_scratch_buffer(struct si_context *sctx,
3144 struct si_shader *shader)
3145 {
3146 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3147
3148 if (!shader)
3149 return 0;
3150
3151 /* This shader doesn't need a scratch buffer */
3152 if (shader->config.scratch_bytes_per_wave == 0)
3153 return 0;
3154
3155 /* Prevent race conditions when updating:
3156 * - si_shader::scratch_bo
3157 * - si_shader::binary::code
3158 * - si_shader::previous_stage::binary::code.
3159 */
3160 si_shader_lock(shader);
3161
3162 /* This shader is already configured to use the current
3163 * scratch buffer. */
3164 if (shader->scratch_bo == sctx->scratch_buffer) {
3165 si_shader_unlock(shader);
3166 return 0;
3167 }
3168
3169 assert(sctx->scratch_buffer);
3170
3171 /* Replace the shader bo with a new bo that has the relocs applied. */
3172 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3173 si_shader_unlock(shader);
3174 return -1;
3175 }
3176
3177 /* Update the shader state to use the new shader bo. */
3178 si_shader_init_pm4_state(sctx->screen, shader);
3179
3180 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3181
3182 si_shader_unlock(shader);
3183 return 1;
3184 }
3185
3186 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
3187 {
3188 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
3189 }
3190
3191 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3192 {
3193 return shader ? shader->config.scratch_bytes_per_wave : 0;
3194 }
3195
3196 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3197 {
3198 if (!sctx->tes_shader.cso)
3199 return NULL; /* tessellation disabled */
3200
3201 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3202 sctx->fixed_func_tcs_shader.current;
3203 }
3204
3205 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
3206 {
3207 unsigned bytes = 0;
3208
3209 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3210 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3211 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3212 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3213
3214 if (sctx->tes_shader.cso) {
3215 struct si_shader *tcs = si_get_tcs_current(sctx);
3216
3217 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
3218 }
3219 return bytes;
3220 }
3221
3222 static bool si_update_scratch_relocs(struct si_context *sctx)
3223 {
3224 struct si_shader *tcs = si_get_tcs_current(sctx);
3225 int r;
3226
3227 /* Update the shaders, so that they are using the latest scratch.
3228 * The scratch buffer may have been changed since these shaders were
3229 * last used, so we still need to try to update them, even if they
3230 * require scratch buffers smaller than the current size.
3231 */
3232 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3233 if (r < 0)
3234 return false;
3235 if (r == 1)
3236 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3237
3238 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3239 if (r < 0)
3240 return false;
3241 if (r == 1)
3242 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3243
3244 r = si_update_scratch_buffer(sctx, tcs);
3245 if (r < 0)
3246 return false;
3247 if (r == 1)
3248 si_pm4_bind_state(sctx, hs, tcs->pm4);
3249
3250 /* VS can be bound as LS, ES, or VS. */
3251 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3252 if (r < 0)
3253 return false;
3254 if (r == 1) {
3255 if (sctx->tes_shader.current)
3256 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3257 else if (sctx->gs_shader.current)
3258 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3259 else
3260 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3261 }
3262
3263 /* TES can be bound as ES or VS. */
3264 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3265 if (r < 0)
3266 return false;
3267 if (r == 1) {
3268 if (sctx->gs_shader.current)
3269 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3270 else
3271 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3272 }
3273
3274 return true;
3275 }
3276
3277 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3278 {
3279 unsigned current_scratch_buffer_size =
3280 si_get_current_scratch_buffer_size(sctx);
3281 unsigned scratch_bytes_per_wave =
3282 si_get_max_scratch_bytes_per_wave(sctx);
3283 unsigned scratch_needed_size = scratch_bytes_per_wave *
3284 sctx->scratch_waves;
3285 unsigned spi_tmpring_size;
3286
3287 if (scratch_needed_size > 0) {
3288 if (scratch_needed_size > current_scratch_buffer_size) {
3289 /* Create a bigger scratch buffer */
3290 si_resource_reference(&sctx->scratch_buffer, NULL);
3291
3292 sctx->scratch_buffer =
3293 si_aligned_buffer_create(&sctx->screen->b,
3294 SI_RESOURCE_FLAG_UNMAPPABLE,
3295 PIPE_USAGE_DEFAULT,
3296 scratch_needed_size, 256);
3297 if (!sctx->scratch_buffer)
3298 return false;
3299
3300 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3301 si_context_add_resource_size(sctx,
3302 &sctx->scratch_buffer->b.b);
3303 }
3304
3305 if (!si_update_scratch_relocs(sctx))
3306 return false;
3307 }
3308
3309 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3310 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3311 "scratch size should already be aligned correctly.");
3312
3313 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3314 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3315 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3316 sctx->spi_tmpring_size = spi_tmpring_size;
3317 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3318 }
3319 return true;
3320 }
3321
3322 static void si_init_tess_factor_ring(struct si_context *sctx)
3323 {
3324 assert(!sctx->tess_rings);
3325
3326 /* The address must be aligned to 2^19, because the shader only
3327 * receives the high 13 bits.
3328 */
3329 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3330 SI_RESOURCE_FLAG_32BIT,
3331 PIPE_USAGE_DEFAULT,
3332 sctx->screen->tess_offchip_ring_size +
3333 sctx->screen->tess_factor_ring_size,
3334 1 << 19);
3335 if (!sctx->tess_rings)
3336 return;
3337
3338 si_init_config_add_vgt_flush(sctx);
3339
3340 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3341 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3342
3343 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3344 sctx->screen->tess_offchip_ring_size;
3345
3346 /* Append these registers to the init config state. */
3347 if (sctx->chip_class >= GFX7) {
3348 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3349 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3350 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3351 factor_va >> 8);
3352 if (sctx->chip_class >= GFX9)
3353 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3354 S_030944_BASE_HI(factor_va >> 40));
3355 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3356 sctx->screen->vgt_hs_offchip_param);
3357 } else {
3358 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3359 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3360 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3361 factor_va >> 8);
3362 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3363 sctx->screen->vgt_hs_offchip_param);
3364 }
3365
3366 /* Flush the context to re-emit the init_config state.
3367 * This is done only once in a lifetime of a context.
3368 */
3369 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3370 sctx->initial_gfx_cs_size = 0; /* force flush */
3371 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3372 }
3373
3374 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3375 union si_vgt_stages_key key)
3376 {
3377 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3378 uint32_t stages = 0;
3379
3380 if (key.u.tess) {
3381 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3382 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3383
3384 if (key.u.gs)
3385 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3386 S_028B54_GS_EN(1);
3387 else if (key.u.ngg)
3388 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3389 else
3390 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3391 } else if (key.u.gs) {
3392 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3393 S_028B54_GS_EN(1);
3394 } else if (key.u.ngg) {
3395 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3396 }
3397
3398 if (key.u.ngg) {
3399 stages |= S_028B54_PRIMGEN_EN(1);
3400 if (key.u.streamout)
3401 stages |= S_028B54_NGG_WAVE_ID_EN(1);
3402 } else if (key.u.gs)
3403 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3404
3405 if (screen->info.chip_class >= GFX9)
3406 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3407
3408 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3409 return pm4;
3410 }
3411
3412 static void si_update_vgt_shader_config(struct si_context *sctx,
3413 union si_vgt_stages_key key)
3414 {
3415 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3416
3417 if (unlikely(!*pm4))
3418 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3419 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3420 }
3421
3422 bool si_update_shaders(struct si_context *sctx)
3423 {
3424 struct pipe_context *ctx = (struct pipe_context*)sctx;
3425 struct si_compiler_ctx_state compiler_state;
3426 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3427 struct si_shader *old_vs = si_get_vs_state(sctx);
3428 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3429 struct si_shader *old_ps = sctx->ps_shader.current;
3430 union si_vgt_stages_key key;
3431 unsigned old_spi_shader_col_format =
3432 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3433 int r;
3434
3435 compiler_state.compiler = &sctx->compiler;
3436 compiler_state.debug = sctx->debug;
3437 compiler_state.is_debug_context = sctx->is_debug;
3438
3439 key.index = 0;
3440
3441 if (sctx->tes_shader.cso)
3442 key.u.tess = 1;
3443 if (sctx->gs_shader.cso)
3444 key.u.gs = 1;
3445
3446 if (sctx->chip_class >= GFX10) {
3447 key.u.ngg = sctx->ngg;
3448
3449 if (sctx->gs_shader.cso)
3450 key.u.streamout = !!sctx->gs_shader.cso->so.num_outputs;
3451 else if (sctx->tes_shader.cso)
3452 key.u.streamout = !!sctx->tes_shader.cso->so.num_outputs;
3453 else
3454 key.u.streamout = !!sctx->vs_shader.cso->so.num_outputs;
3455 }
3456
3457 /* Update TCS and TES. */
3458 if (sctx->tes_shader.cso) {
3459 if (!sctx->tess_rings) {
3460 si_init_tess_factor_ring(sctx);
3461 if (!sctx->tess_rings)
3462 return false;
3463 }
3464
3465 if (sctx->tcs_shader.cso) {
3466 r = si_shader_select(ctx, &sctx->tcs_shader, key,
3467 &compiler_state);
3468 if (r)
3469 return false;
3470 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3471 } else {
3472 if (!sctx->fixed_func_tcs_shader.cso) {
3473 sctx->fixed_func_tcs_shader.cso =
3474 si_create_fixed_func_tcs(sctx);
3475 if (!sctx->fixed_func_tcs_shader.cso)
3476 return false;
3477 }
3478
3479 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3480 key, &compiler_state);
3481 if (r)
3482 return false;
3483 si_pm4_bind_state(sctx, hs,
3484 sctx->fixed_func_tcs_shader.current->pm4);
3485 }
3486
3487 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3488 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3489 if (r)
3490 return false;
3491
3492 if (sctx->gs_shader.cso) {
3493 /* TES as ES */
3494 assert(sctx->chip_class <= GFX8);
3495 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3496 } else if (key.u.ngg) {
3497 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3498 } else {
3499 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3500 }
3501 }
3502 } else {
3503 if (sctx->chip_class <= GFX8)
3504 si_pm4_bind_state(sctx, ls, NULL);
3505 si_pm4_bind_state(sctx, hs, NULL);
3506 }
3507
3508 /* Update GS. */
3509 if (sctx->gs_shader.cso) {
3510 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
3511 if (r)
3512 return false;
3513 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3514 if (!key.u.ngg) {
3515 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3516
3517 if (!si_update_gs_ring_buffers(sctx))
3518 return false;
3519 } else {
3520 si_pm4_bind_state(sctx, vs, NULL);
3521 }
3522 } else {
3523 if (!key.u.ngg) {
3524 si_pm4_bind_state(sctx, gs, NULL);
3525 if (sctx->chip_class <= GFX8)
3526 si_pm4_bind_state(sctx, es, NULL);
3527 }
3528 }
3529
3530 /* Update VS. */
3531 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
3532 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
3533 if (r)
3534 return false;
3535
3536 if (!key.u.tess && !key.u.gs) {
3537 if (key.u.ngg) {
3538 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3539 si_pm4_bind_state(sctx, vs, NULL);
3540 } else {
3541 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3542 }
3543 } else if (sctx->tes_shader.cso) {
3544 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3545 } else {
3546 assert(sctx->gs_shader.cso);
3547 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3548 }
3549 }
3550
3551 si_update_vgt_shader_config(sctx, key);
3552
3553 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3554 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3555
3556 if (sctx->ps_shader.cso) {
3557 unsigned db_shader_control;
3558
3559 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
3560 if (r)
3561 return false;
3562 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3563
3564 db_shader_control =
3565 sctx->ps_shader.cso->db_shader_control |
3566 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3567
3568 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3569 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3570 sctx->flatshade != rs->flatshade) {
3571 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3572 sctx->flatshade = rs->flatshade;
3573 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3574 }
3575
3576 if (sctx->screen->rbplus_allowed &&
3577 si_pm4_state_changed(sctx, ps) &&
3578 (!old_ps ||
3579 old_spi_shader_col_format !=
3580 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3581 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3582
3583 if (sctx->ps_db_shader_control != db_shader_control) {
3584 sctx->ps_db_shader_control = db_shader_control;
3585 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3586 if (sctx->screen->dpbb_allowed)
3587 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3588 }
3589
3590 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3591 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3592 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3593
3594 if (sctx->chip_class == GFX6)
3595 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3596
3597 if (sctx->framebuffer.nr_samples <= 1)
3598 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3599 }
3600 }
3601
3602 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3603 si_pm4_state_enabled_and_changed(sctx, hs) ||
3604 si_pm4_state_enabled_and_changed(sctx, es) ||
3605 si_pm4_state_enabled_and_changed(sctx, gs) ||
3606 si_pm4_state_enabled_and_changed(sctx, vs) ||
3607 si_pm4_state_enabled_and_changed(sctx, ps)) {
3608 if (!si_update_spi_tmpring_size(sctx))
3609 return false;
3610 }
3611
3612 if (sctx->chip_class >= GFX7) {
3613 if (si_pm4_state_enabled_and_changed(sctx, ls))
3614 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3615 else if (!sctx->queued.named.ls)
3616 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3617
3618 if (si_pm4_state_enabled_and_changed(sctx, hs))
3619 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3620 else if (!sctx->queued.named.hs)
3621 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3622
3623 if (si_pm4_state_enabled_and_changed(sctx, es))
3624 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
3625 else if (!sctx->queued.named.es)
3626 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
3627
3628 if (si_pm4_state_enabled_and_changed(sctx, gs))
3629 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
3630 else if (!sctx->queued.named.gs)
3631 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
3632
3633 if (si_pm4_state_enabled_and_changed(sctx, vs))
3634 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
3635 else if (!sctx->queued.named.vs)
3636 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
3637
3638 if (si_pm4_state_enabled_and_changed(sctx, ps))
3639 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
3640 else if (!sctx->queued.named.ps)
3641 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
3642 }
3643
3644 sctx->do_update_shaders = false;
3645 return true;
3646 }
3647
3648 static void si_emit_scratch_state(struct si_context *sctx)
3649 {
3650 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3651
3652 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3653 sctx->spi_tmpring_size);
3654
3655 if (sctx->scratch_buffer) {
3656 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3657 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3658 RADEON_PRIO_SCRATCH_BUFFER);
3659 }
3660 }
3661
3662 void si_init_shader_functions(struct si_context *sctx)
3663 {
3664 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
3665 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
3666
3667 sctx->b.create_vs_state = si_create_shader_selector;
3668 sctx->b.create_tcs_state = si_create_shader_selector;
3669 sctx->b.create_tes_state = si_create_shader_selector;
3670 sctx->b.create_gs_state = si_create_shader_selector;
3671 sctx->b.create_fs_state = si_create_shader_selector;
3672
3673 sctx->b.bind_vs_state = si_bind_vs_shader;
3674 sctx->b.bind_tcs_state = si_bind_tcs_shader;
3675 sctx->b.bind_tes_state = si_bind_tes_shader;
3676 sctx->b.bind_gs_state = si_bind_gs_shader;
3677 sctx->b.bind_fs_state = si_bind_ps_shader;
3678
3679 sctx->b.delete_vs_state = si_delete_shader_selector;
3680 sctx->b.delete_tcs_state = si_delete_shader_selector;
3681 sctx->b.delete_tes_state = si_delete_shader_selector;
3682 sctx->b.delete_gs_state = si_delete_shader_selector;
3683 sctx->b.delete_fs_state = si_delete_shader_selector;
3684 }