2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_ureg.h"
31 #include "util/hash_table.h"
32 #include "util/crc32.h"
33 #include "util/u_async_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
37 #include "util/disk_cache.h"
38 #include "util/mesa-sha1.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
45 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
48 static void *si_get_ir_binary(struct si_shader_selector
*sel
)
55 ir_binary
= sel
->tokens
;
56 ir_size
= tgsi_num_tokens(sel
->tokens
) *
57 sizeof(struct tgsi_token
);
62 nir_serialize(&blob
, sel
->nir
);
63 ir_binary
= blob
.data
;
67 unsigned size
= 4 + ir_size
+ sizeof(sel
->so
);
68 char *result
= (char*)MALLOC(size
);
72 *((uint32_t*)result
) = size
;
73 memcpy(result
+ 4, ir_binary
, ir_size
);
74 memcpy(result
+ 4 + ir_size
, &sel
->so
, sizeof(sel
->so
));
82 /** Copy "data" to "ptr" and return the next dword following copied data. */
83 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
85 /* data may be NULL if size == 0 */
87 memcpy(ptr
, data
, size
);
88 ptr
+= DIV_ROUND_UP(size
, 4);
92 /** Read data from "ptr". Return the next dword following the data. */
93 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
95 memcpy(data
, ptr
, size
);
96 ptr
+= DIV_ROUND_UP(size
, 4);
101 * Write the size as uint followed by the data. Return the next dword
102 * following the copied data.
104 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
107 return write_data(ptr
, data
, size
);
111 * Read the size as uint followed by the data. Return both via parameters.
112 * Return the next dword following the data.
114 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
117 assert(*data
== NULL
);
120 *data
= malloc(*size
);
121 return read_data(ptr
, *data
, *size
);
125 * Return the shader binary in a buffer. The first 4 bytes contain its size
128 static void *si_get_shader_binary(struct si_shader
*shader
)
130 /* There is always a size of data followed by the data itself. */
131 unsigned relocs_size
= shader
->binary
.reloc_count
*
132 sizeof(shader
->binary
.relocs
[0]);
133 unsigned disasm_size
= shader
->binary
.disasm_string
?
134 strlen(shader
->binary
.disasm_string
) + 1 : 0;
135 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
136 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
139 4 + /* CRC32 of the data below */
140 align(sizeof(shader
->config
), 4) +
141 align(sizeof(shader
->info
), 4) +
142 4 + align(shader
->binary
.code_size
, 4) +
143 4 + align(shader
->binary
.rodata_size
, 4) +
144 4 + align(relocs_size
, 4) +
145 4 + align(disasm_size
, 4) +
146 4 + align(llvm_ir_size
, 4);
147 void *buffer
= CALLOC(1, size
);
148 uint32_t *ptr
= (uint32_t*)buffer
;
154 ptr
++; /* CRC32 is calculated at the end. */
156 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
157 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
158 ptr
= write_chunk(ptr
, shader
->binary
.code
, shader
->binary
.code_size
);
159 ptr
= write_chunk(ptr
, shader
->binary
.rodata
, shader
->binary
.rodata_size
);
160 ptr
= write_chunk(ptr
, shader
->binary
.relocs
, relocs_size
);
161 ptr
= write_chunk(ptr
, shader
->binary
.disasm_string
, disasm_size
);
162 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
163 assert((char *)ptr
- (char *)buffer
== size
);
166 ptr
= (uint32_t*)buffer
;
168 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
173 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
175 uint32_t *ptr
= (uint32_t*)binary
;
176 uint32_t size
= *ptr
++;
177 uint32_t crc32
= *ptr
++;
180 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
181 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
185 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
186 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
187 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.code
,
188 &shader
->binary
.code_size
);
189 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.rodata
,
190 &shader
->binary
.rodata_size
);
191 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.relocs
, &chunk_size
);
192 shader
->binary
.reloc_count
= chunk_size
/ sizeof(shader
->binary
.relocs
[0]);
193 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.disasm_string
, &chunk_size
);
194 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
200 * Insert a shader into the cache. It's assumed the shader is not in the cache.
201 * Use si_shader_cache_load_shader before calling this.
203 * Returns false on failure, in which case the ir_binary should be freed.
205 static bool si_shader_cache_insert_shader(struct si_screen
*sscreen
,
207 struct si_shader
*shader
,
208 bool insert_into_disk_cache
)
211 struct hash_entry
*entry
;
212 uint8_t key
[CACHE_KEY_SIZE
];
214 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
216 return false; /* already added */
218 hw_binary
= si_get_shader_binary(shader
);
222 if (_mesa_hash_table_insert(sscreen
->shader_cache
, ir_binary
,
223 hw_binary
) == NULL
) {
228 if (sscreen
->disk_shader_cache
&& insert_into_disk_cache
) {
229 disk_cache_compute_key(sscreen
->disk_shader_cache
, ir_binary
,
230 *((uint32_t *)ir_binary
), key
);
231 disk_cache_put(sscreen
->disk_shader_cache
, key
, hw_binary
,
232 *((uint32_t *) hw_binary
), NULL
);
238 static bool si_shader_cache_load_shader(struct si_screen
*sscreen
,
240 struct si_shader
*shader
)
242 struct hash_entry
*entry
=
243 _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
245 if (sscreen
->disk_shader_cache
) {
246 unsigned char sha1
[CACHE_KEY_SIZE
];
247 size_t tg_size
= *((uint32_t *) ir_binary
);
249 disk_cache_compute_key(sscreen
->disk_shader_cache
,
250 ir_binary
, tg_size
, sha1
);
254 disk_cache_get(sscreen
->disk_shader_cache
,
259 if (binary_size
< sizeof(uint32_t) ||
260 *((uint32_t*)buffer
) != binary_size
) {
261 /* Something has gone wrong discard the item
262 * from the cache and rebuild/link from
265 assert(!"Invalid radeonsi shader disk cache "
268 disk_cache_remove(sscreen
->disk_shader_cache
,
275 if (!si_load_shader_binary(shader
, buffer
)) {
281 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
,
288 if (si_load_shader_binary(shader
, entry
->data
))
293 p_atomic_inc(&sscreen
->num_shader_cache_hits
);
297 static uint32_t si_shader_cache_key_hash(const void *key
)
299 /* The first dword is the key size. */
300 return util_hash_crc32(key
, *(uint32_t*)key
);
303 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
305 uint32_t *keya
= (uint32_t*)a
;
306 uint32_t *keyb
= (uint32_t*)b
;
308 /* The first dword is the key size. */
312 return memcmp(keya
, keyb
, *keya
) == 0;
315 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
317 FREE((void*)entry
->key
);
321 bool si_init_shader_cache(struct si_screen
*sscreen
)
323 (void) mtx_init(&sscreen
->shader_cache_mutex
, mtx_plain
);
324 sscreen
->shader_cache
=
325 _mesa_hash_table_create(NULL
,
326 si_shader_cache_key_hash
,
327 si_shader_cache_key_equals
);
329 return sscreen
->shader_cache
!= NULL
;
332 void si_destroy_shader_cache(struct si_screen
*sscreen
)
334 if (sscreen
->shader_cache
)
335 _mesa_hash_table_destroy(sscreen
->shader_cache
,
336 si_destroy_shader_cache_entry
);
337 mtx_destroy(&sscreen
->shader_cache_mutex
);
342 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
343 struct si_shader_selector
*tes
,
344 struct si_pm4_state
*pm4
)
346 struct tgsi_shader_info
*info
= &tes
->info
;
347 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
348 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
349 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
350 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
351 unsigned type
, partitioning
, topology
, distribution_mode
;
353 switch (tes_prim_mode
) {
354 case PIPE_PRIM_LINES
:
355 type
= V_028B6C_TESS_ISOLINE
;
357 case PIPE_PRIM_TRIANGLES
:
358 type
= V_028B6C_TESS_TRIANGLE
;
360 case PIPE_PRIM_QUADS
:
361 type
= V_028B6C_TESS_QUAD
;
368 switch (tes_spacing
) {
369 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
370 partitioning
= V_028B6C_PART_FRAC_ODD
;
372 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
373 partitioning
= V_028B6C_PART_FRAC_EVEN
;
375 case PIPE_TESS_SPACING_EQUAL
:
376 partitioning
= V_028B6C_PART_INTEGER
;
384 topology
= V_028B6C_OUTPUT_POINT
;
385 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
386 topology
= V_028B6C_OUTPUT_LINE
;
387 else if (tes_vertex_order_cw
)
388 /* for some reason, this must be the other way around */
389 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
391 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
393 if (sscreen
->has_distributed_tess
) {
394 if (sscreen
->info
.family
== CHIP_FIJI
||
395 sscreen
->info
.family
>= CHIP_POLARIS10
)
396 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
398 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
400 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
402 si_pm4_set_reg(pm4
, R_028B6C_VGT_TF_PARAM
,
403 S_028B6C_TYPE(type
) |
404 S_028B6C_PARTITIONING(partitioning
) |
405 S_028B6C_TOPOLOGY(topology
) |
406 S_028B6C_DISTRIBUTION_MODE(distribution_mode
));
409 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
410 * whether the "fractional odd" tessellation spacing is used.
412 * Possible VGT configurations and which state should set the register:
414 * Reg set in | VGT shader configuration | Value
415 * ------------------------------------------------------
417 * VS as ES | ES -> GS -> VS | 30
418 * TES as VS | LS -> HS -> VS | 14 or 30
419 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
421 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
423 static void polaris_set_vgt_vertex_reuse(struct si_screen
*sscreen
,
424 struct si_shader_selector
*sel
,
425 struct si_shader
*shader
,
426 struct si_pm4_state
*pm4
)
428 unsigned type
= sel
->type
;
430 if (sscreen
->info
.family
< CHIP_POLARIS10
)
433 /* VS as VS, or VS as ES: */
434 if ((type
== PIPE_SHADER_VERTEX
&&
436 (!shader
->key
.as_ls
&& !shader
->is_gs_copy_shader
))) ||
437 /* TES as VS, or TES as ES: */
438 type
== PIPE_SHADER_TESS_EVAL
) {
439 unsigned vtx_reuse_depth
= 30;
441 if (type
== PIPE_SHADER_TESS_EVAL
&&
442 sel
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] ==
443 PIPE_TESS_SPACING_FRACTIONAL_ODD
)
444 vtx_reuse_depth
= 14;
446 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
451 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
454 si_pm4_clear_state(shader
->pm4
);
456 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
461 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs
)
463 /* Add the pointer to VBO descriptors. */
464 if (HAVE_32BIT_POINTERS
) {
465 return num_always_on_user_sgprs
+ 1;
467 assert(num_always_on_user_sgprs
% 2 == 0);
468 return num_always_on_user_sgprs
+ 2;
472 static void si_shader_ls(struct si_screen
*sscreen
, struct si_shader
*shader
)
474 struct si_pm4_state
*pm4
;
475 unsigned vgpr_comp_cnt
;
478 assert(sscreen
->info
.chip_class
<= VI
);
480 pm4
= si_get_shader_pm4_state(shader
);
484 va
= shader
->bo
->gpu_address
;
485 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
487 /* We need at least 2 components for LS.
488 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
489 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
491 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
493 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
494 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
496 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
497 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
498 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt
) |
499 S_00B528_DX10_CLAMP(1) |
500 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
501 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
)) |
502 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
505 static void si_shader_hs(struct si_screen
*sscreen
, struct si_shader
*shader
)
507 struct si_pm4_state
*pm4
;
509 unsigned ls_vgpr_comp_cnt
= 0;
511 pm4
= si_get_shader_pm4_state(shader
);
515 va
= shader
->bo
->gpu_address
;
516 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
518 if (sscreen
->info
.chip_class
>= GFX9
) {
519 si_pm4_set_reg(pm4
, R_00B410_SPI_SHADER_PGM_LO_LS
, va
>> 8);
520 si_pm4_set_reg(pm4
, R_00B414_SPI_SHADER_PGM_HI_LS
, S_00B414_MEM_BASE(va
>> 40));
522 /* We need at least 2 components for LS.
523 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
524 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
526 ls_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
528 unsigned num_user_sgprs
=
529 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR
);
531 shader
->config
.rsrc2
=
532 S_00B42C_USER_SGPR(num_user_sgprs
) |
533 S_00B42C_USER_SGPR_MSB(num_user_sgprs
>> 5) |
534 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
536 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
537 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, S_00B424_MEM_BASE(va
>> 40));
539 shader
->config
.rsrc2
=
540 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR
) |
541 S_00B42C_OC_LDS_EN(1) |
542 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
545 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
546 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
547 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
548 S_00B428_DX10_CLAMP(1) |
549 S_00B428_FLOAT_MODE(shader
->config
.float_mode
) |
550 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt
));
552 if (sscreen
->info
.chip_class
<= VI
) {
553 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
554 shader
->config
.rsrc2
);
558 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
560 struct si_pm4_state
*pm4
;
561 unsigned num_user_sgprs
;
562 unsigned vgpr_comp_cnt
;
566 assert(sscreen
->info
.chip_class
<= VI
);
568 pm4
= si_get_shader_pm4_state(shader
);
572 va
= shader
->bo
->gpu_address
;
573 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
575 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
576 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
577 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
578 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
579 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
580 vgpr_comp_cnt
= shader
->selector
->info
.uses_primid
? 3 : 2;
581 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
583 unreachable("invalid shader selector type");
585 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
587 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
588 shader
->selector
->esgs_itemsize
/ 4);
589 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
590 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
591 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
592 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
593 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
594 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
595 S_00B328_DX10_CLAMP(1) |
596 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
597 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
598 S_00B32C_USER_SGPR(num_user_sgprs
) |
599 S_00B32C_OC_LDS_EN(oc_lds_en
) |
600 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
602 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
603 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
605 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
608 static unsigned si_conv_prim_to_gs_out(unsigned mode
)
610 static const int prim_conv
[] = {
611 [PIPE_PRIM_POINTS
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
612 [PIPE_PRIM_LINES
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
613 [PIPE_PRIM_LINE_LOOP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
614 [PIPE_PRIM_LINE_STRIP
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
615 [PIPE_PRIM_TRIANGLES
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
616 [PIPE_PRIM_TRIANGLE_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
617 [PIPE_PRIM_TRIANGLE_FAN
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
618 [PIPE_PRIM_QUADS
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
619 [PIPE_PRIM_QUAD_STRIP
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
620 [PIPE_PRIM_POLYGON
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
621 [PIPE_PRIM_LINES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
622 [PIPE_PRIM_LINE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_LINESTRIP
,
623 [PIPE_PRIM_TRIANGLES_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
624 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
,
625 [PIPE_PRIM_PATCHES
] = V_028A6C_OUTPRIM_TYPE_POINTLIST
,
627 assert(mode
< ARRAY_SIZE(prim_conv
));
629 return prim_conv
[mode
];
632 struct gfx9_gs_info
{
633 unsigned es_verts_per_subgroup
;
634 unsigned gs_prims_per_subgroup
;
635 unsigned gs_inst_prims_in_subgroup
;
636 unsigned max_prims_per_subgroup
;
640 static void gfx9_get_gs_info(struct si_shader_selector
*es
,
641 struct si_shader_selector
*gs
,
642 struct gfx9_gs_info
*out
)
644 unsigned gs_num_invocations
= MAX2(gs
->gs_num_invocations
, 1);
645 unsigned input_prim
= gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
646 bool uses_adjacency
= input_prim
>= PIPE_PRIM_LINES_ADJACENCY
&&
647 input_prim
<= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
;
649 /* All these are in dwords: */
650 /* We can't allow using the whole LDS, because GS waves compete with
651 * other shader stages for LDS space. */
652 const unsigned max_lds_size
= 8 * 1024;
653 const unsigned esgs_itemsize
= es
->esgs_itemsize
/ 4;
654 unsigned esgs_lds_size
;
656 /* All these are per subgroup: */
657 const unsigned max_out_prims
= 32 * 1024;
658 const unsigned max_es_verts
= 255;
659 const unsigned ideal_gs_prims
= 64;
660 unsigned max_gs_prims
, gs_prims
;
661 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
663 assert(gs_num_invocations
<= 32); /* GL maximum */
665 if (uses_adjacency
|| gs_num_invocations
> 1)
666 max_gs_prims
= 127 / gs_num_invocations
;
670 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
671 * Make sure we don't go over the maximum value.
673 if (gs
->gs_max_out_vertices
> 0) {
674 max_gs_prims
= MIN2(max_gs_prims
,
676 (gs
->gs_max_out_vertices
* gs_num_invocations
));
678 assert(max_gs_prims
> 0);
680 /* If the primitive has adjacency, halve the number of vertices
681 * that will be reused in multiple primitives.
683 min_es_verts
= gs
->gs_input_verts_per_prim
/ (uses_adjacency
? 2 : 1);
685 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
686 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
688 /* Compute ESGS LDS size based on the worst case number of ES vertices
689 * needed to create the target number of GS prims per subgroup.
691 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
693 /* If total LDS usage is too big, refactor partitions based on ratio
694 * of ESGS item sizes.
696 if (esgs_lds_size
> max_lds_size
) {
697 /* Our target GS Prims Per Subgroup was too large. Calculate
698 * the maximum number of GS Prims Per Subgroup that will fit
699 * into LDS, capped by the maximum that the hardware can support.
701 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
703 assert(gs_prims
> 0);
704 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
707 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
708 assert(esgs_lds_size
<= max_lds_size
);
711 /* Now calculate remaining ESGS information. */
713 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
715 es_verts
= max_es_verts
;
717 /* Vertices for adjacency primitives are not always reused, so restore
718 * it for ES_VERTS_PER_SUBGRP.
720 min_es_verts
= gs
->gs_input_verts_per_prim
;
722 /* For normal primitives, the VGT only checks if they are past the ES
723 * verts per subgroup after allocating a full GS primitive and if they
724 * are, kick off a new subgroup. But if those additional ES verts are
725 * unique (e.g. not reused) we need to make sure there is enough LDS
726 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
728 es_verts
-= min_es_verts
- 1;
730 out
->es_verts_per_subgroup
= es_verts
;
731 out
->gs_prims_per_subgroup
= gs_prims
;
732 out
->gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
733 out
->max_prims_per_subgroup
= out
->gs_inst_prims_in_subgroup
*
734 gs
->gs_max_out_vertices
;
735 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
737 assert(out
->max_prims_per_subgroup
<= max_out_prims
);
740 static void si_shader_gs(struct si_screen
*sscreen
, struct si_shader
*shader
)
742 struct si_shader_selector
*sel
= shader
->selector
;
743 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
744 unsigned gs_num_invocations
= sel
->gs_num_invocations
;
745 struct si_pm4_state
*pm4
;
747 unsigned max_stream
= sel
->max_gs_stream
;
750 pm4
= si_get_shader_pm4_state(shader
);
754 offset
= num_components
[0] * sel
->gs_max_out_vertices
;
755 si_pm4_set_reg(pm4
, R_028A60_VGT_GSVS_RING_OFFSET_1
, offset
);
757 offset
+= num_components
[1] * sel
->gs_max_out_vertices
;
758 si_pm4_set_reg(pm4
, R_028A64_VGT_GSVS_RING_OFFSET_2
, offset
);
760 offset
+= num_components
[2] * sel
->gs_max_out_vertices
;
761 si_pm4_set_reg(pm4
, R_028A68_VGT_GSVS_RING_OFFSET_3
, offset
);
762 si_pm4_set_reg(pm4
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
,
763 si_conv_prim_to_gs_out(sel
->gs_output_prim
));
765 offset
+= num_components
[3] * sel
->gs_max_out_vertices
;
766 si_pm4_set_reg(pm4
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
768 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
769 assert(offset
< (1 << 15));
771 si_pm4_set_reg(pm4
, R_028B38_VGT_GS_MAX_VERT_OUT
, sel
->gs_max_out_vertices
);
773 si_pm4_set_reg(pm4
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, num_components
[0]);
774 si_pm4_set_reg(pm4
, R_028B60_VGT_GS_VERT_ITEMSIZE_1
, (max_stream
>= 1) ? num_components
[1] : 0);
775 si_pm4_set_reg(pm4
, R_028B64_VGT_GS_VERT_ITEMSIZE_2
, (max_stream
>= 2) ? num_components
[2] : 0);
776 si_pm4_set_reg(pm4
, R_028B68_VGT_GS_VERT_ITEMSIZE_3
, (max_stream
>= 3) ? num_components
[3] : 0);
778 si_pm4_set_reg(pm4
, R_028B90_VGT_GS_INSTANCE_CNT
,
779 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
780 S_028B90_ENABLE(gs_num_invocations
> 0));
782 va
= shader
->bo
->gpu_address
;
783 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
785 if (sscreen
->info
.chip_class
>= GFX9
) {
786 unsigned input_prim
= sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
787 unsigned es_type
= shader
->key
.part
.gs
.es
->type
;
788 unsigned es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
789 struct gfx9_gs_info gs_info
;
791 if (es_type
== PIPE_SHADER_VERTEX
)
792 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
793 es_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
794 else if (es_type
== PIPE_SHADER_TESS_EVAL
)
795 es_vgpr_comp_cnt
= shader
->key
.part
.gs
.es
->info
.uses_primid
? 3 : 2;
797 unreachable("invalid shader selector type");
799 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
800 * VGPR[0:4] are always loaded.
802 if (sel
->info
.uses_invocationid
)
803 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
804 else if (sel
->info
.uses_primid
)
805 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
806 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
807 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
809 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
811 unsigned num_user_sgprs
;
812 if (es_type
== PIPE_SHADER_VERTEX
)
813 num_user_sgprs
= si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR
);
815 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
817 gfx9_get_gs_info(shader
->key
.part
.gs
.es
, sel
, &gs_info
);
819 si_pm4_set_reg(pm4
, R_00B210_SPI_SHADER_PGM_LO_ES
, va
>> 8);
820 si_pm4_set_reg(pm4
, R_00B214_SPI_SHADER_PGM_HI_ES
, S_00B214_MEM_BASE(va
>> 40));
822 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
823 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
824 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
825 S_00B228_DX10_CLAMP(1) |
826 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
827 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
));
828 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
829 S_00B22C_USER_SGPR(num_user_sgprs
) |
830 S_00B22C_USER_SGPR_MSB(num_user_sgprs
>> 5) |
831 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
832 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
833 S_00B22C_LDS_SIZE(gs_info
.lds_size
) |
834 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
836 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
837 S_028A44_ES_VERTS_PER_SUBGRP(gs_info
.es_verts_per_subgroup
) |
838 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info
.gs_prims_per_subgroup
) |
839 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info
.gs_inst_prims_in_subgroup
));
840 si_pm4_set_reg(pm4
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
841 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info
.max_prims_per_subgroup
));
842 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
843 shader
->key
.part
.gs
.es
->esgs_itemsize
/ 4);
845 if (es_type
== PIPE_SHADER_TESS_EVAL
)
846 si_set_tesseval_regs(sscreen
, shader
->key
.part
.gs
.es
, pm4
);
848 polaris_set_vgt_vertex_reuse(sscreen
, shader
->key
.part
.gs
.es
,
851 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
852 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, S_00B224_MEM_BASE(va
>> 40));
854 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
855 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
856 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
857 S_00B228_DX10_CLAMP(1) |
858 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
859 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
860 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR
) |
861 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
866 * Compute the state for \p shader, which will run as a vertex shader on the
869 * If \p gs is non-NULL, it points to the geometry shader for which this shader
870 * is the copy shader.
872 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
873 struct si_shader_selector
*gs
)
875 const struct tgsi_shader_info
*info
= &shader
->selector
->info
;
876 struct si_pm4_state
*pm4
;
877 unsigned num_user_sgprs
;
878 unsigned nparams
, vgpr_comp_cnt
;
881 unsigned window_space
=
882 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
883 bool enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| info
->uses_primid
;
885 pm4
= si_get_shader_pm4_state(shader
);
889 /* We always write VGT_GS_MODE in the VS state, because every switch
890 * between different shader pipelines involving a different GS or no
891 * GS at all involves a switch of the VS (different GS use different
892 * copy shaders). On the other hand, when the API switches from a GS to
893 * no GS and then back to the same GS used originally, the GS state is
897 unsigned mode
= V_028A40_GS_OFF
;
899 /* PrimID needs GS scenario A. */
901 mode
= V_028A40_GS_SCENARIO_A
;
903 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, S_028A40_MODE(mode
));
904 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, enable_prim_id
);
906 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
,
907 ac_vgt_gs_mode(gs
->gs_max_out_vertices
,
908 sscreen
->info
.chip_class
));
909 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
912 if (sscreen
->info
.chip_class
<= VI
) {
913 /* Reuse needs to be set off if we write oViewport. */
914 si_pm4_set_reg(pm4
, R_028AB4_VGT_REUSE_OFF
,
915 S_028AB4_REUSE_OFF(info
->writes_viewport_index
));
918 va
= shader
->bo
->gpu_address
;
919 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
922 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
923 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
924 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
925 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
926 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
927 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
929 vgpr_comp_cnt
= enable_prim_id
? 2 : (shader
->info
.uses_instanceid
? 1 : 0);
931 if (info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
]) {
932 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
933 info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
935 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
937 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
938 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
939 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
941 unreachable("invalid shader selector type");
943 /* VS is required to export at least one param. */
944 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
945 si_pm4_set_reg(pm4
, R_0286C4_SPI_VS_OUT_CONFIG
,
946 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
948 si_pm4_set_reg(pm4
, R_02870C_SPI_SHADER_POS_FORMAT
,
949 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
950 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
951 V_02870C_SPI_SHADER_4COMP
:
952 V_02870C_SPI_SHADER_NONE
) |
953 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
954 V_02870C_SPI_SHADER_4COMP
:
955 V_02870C_SPI_SHADER_NONE
) |
956 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
957 V_02870C_SPI_SHADER_4COMP
:
958 V_02870C_SPI_SHADER_NONE
));
960 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
962 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
963 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, S_00B124_MEM_BASE(va
>> 40));
964 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
965 S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
966 S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
967 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
968 S_00B128_DX10_CLAMP(1) |
969 S_00B128_FLOAT_MODE(shader
->config
.float_mode
));
970 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
971 S_00B12C_USER_SGPR(num_user_sgprs
) |
972 S_00B12C_OC_LDS_EN(oc_lds_en
) |
973 S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
974 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
975 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
976 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
977 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
) |
978 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
980 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
981 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
983 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
984 S_028818_VTX_W0_FMT(1) |
985 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
986 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
987 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
989 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
990 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
992 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
995 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
997 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
998 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
999 !!(info
->colors_read
& 0xf0);
1000 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
1001 (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
1003 assert(num_interp
<= 32);
1004 return MIN2(num_interp
, 32);
1007 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
1009 unsigned value
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
1010 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
1012 /* If the i-th target format is set, all previous target formats must
1013 * be non-zero to avoid hangs.
1015 for (i
= 0; i
< num_targets
; i
++)
1016 if (!(value
& (0xf << (i
* 4))))
1017 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
1022 static void si_shader_ps(struct si_shader
*shader
)
1024 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1025 struct si_pm4_state
*pm4
;
1026 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
1027 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
1029 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
1031 /* we need to enable at least one of them, otherwise we hang the GPU */
1032 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1033 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1034 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1035 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
1036 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
1037 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1038 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
1039 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
1040 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1041 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
1042 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1043 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1044 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1045 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
1047 /* Validate interpolation optimization flags (read as implications). */
1048 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1049 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1050 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1051 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1052 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1053 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1054 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
1055 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
1056 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1057 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
1058 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
1059 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1060 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
1061 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1062 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1063 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
1064 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1065 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1067 /* Validate cases when the optimizations are off (read as implications). */
1068 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1069 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1070 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
1071 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1072 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1073 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
1075 pm4
= si_get_shader_pm4_state(shader
);
1079 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1081 * 0 -> Position = pixel center
1082 * 1 -> Position = pixel centroid
1083 * 2 -> Position = at sample position
1085 * From GLSL 4.5 specification, section 7.1:
1086 * "The variable gl_FragCoord is available as an input variable from
1087 * within fragment shaders and it holds the window relative coordinates
1088 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1089 * value can be for any location within the pixel, or one of the
1090 * fragment samples. The use of centroid does not further restrict
1091 * this value to be inside the current primitive."
1093 * Meaning that centroid has no effect and we can return anything within
1094 * the pixel. Thus, return the value at sample position, because that's
1095 * the most accurate one shaders can get.
1097 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1099 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
1100 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
1101 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
1103 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
1104 cb_shader_mask
= ac_get_cb_shader_mask(spi_shader_col_format
);
1106 /* Ensure that some export memory is always allocated, for two reasons:
1108 * 1) Correctness: The hardware ignores the EXEC mask if no export
1109 * memory is allocated, so KILL and alpha test do not work correctly
1111 * 2) Performance: Every shader needs at least a NULL export, even when
1112 * it writes no color/depth output. The NULL export instruction
1113 * stalls without this setting.
1115 * Don't add this to CB_SHADER_MASK.
1117 if (!spi_shader_col_format
&&
1118 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
1119 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
1121 si_pm4_set_reg(pm4
, R_0286CC_SPI_PS_INPUT_ENA
, input_ena
);
1122 si_pm4_set_reg(pm4
, R_0286D0_SPI_PS_INPUT_ADDR
,
1123 shader
->config
.spi_ps_input_addr
);
1125 /* Set interpolation controls. */
1126 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
));
1128 /* Set registers. */
1129 si_pm4_set_reg(pm4
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
1130 si_pm4_set_reg(pm4
, R_0286D8_SPI_PS_IN_CONTROL
, spi_ps_in_control
);
1132 si_pm4_set_reg(pm4
, R_028710_SPI_SHADER_Z_FORMAT
,
1133 ac_get_spi_shader_z_format(info
->writes_z
,
1134 info
->writes_stencil
,
1135 info
->writes_samplemask
));
1137 si_pm4_set_reg(pm4
, R_028714_SPI_SHADER_COL_FORMAT
, spi_shader_col_format
);
1138 si_pm4_set_reg(pm4
, R_02823C_CB_SHADER_MASK
, cb_shader_mask
);
1140 va
= shader
->bo
->gpu_address
;
1141 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1142 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
1143 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, S_00B024_MEM_BASE(va
>> 40));
1145 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
,
1146 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1147 S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
1148 S_00B028_DX10_CLAMP(1) |
1149 S_00B028_FLOAT_MODE(shader
->config
.float_mode
));
1150 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
1151 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
1152 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
1153 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1156 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
1157 struct si_shader
*shader
)
1159 switch (shader
->selector
->type
) {
1160 case PIPE_SHADER_VERTEX
:
1161 if (shader
->key
.as_ls
)
1162 si_shader_ls(sscreen
, shader
);
1163 else if (shader
->key
.as_es
)
1164 si_shader_es(sscreen
, shader
);
1166 si_shader_vs(sscreen
, shader
, NULL
);
1168 case PIPE_SHADER_TESS_CTRL
:
1169 si_shader_hs(sscreen
, shader
);
1171 case PIPE_SHADER_TESS_EVAL
:
1172 if (shader
->key
.as_es
)
1173 si_shader_es(sscreen
, shader
);
1175 si_shader_vs(sscreen
, shader
, NULL
);
1177 case PIPE_SHADER_GEOMETRY
:
1178 si_shader_gs(sscreen
, shader
);
1180 case PIPE_SHADER_FRAGMENT
:
1181 si_shader_ps(shader
);
1188 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
1190 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1191 if (sctx
->queued
.named
.dsa
)
1192 return sctx
->queued
.named
.dsa
->alpha_func
;
1194 return PIPE_FUNC_ALWAYS
;
1197 static void si_shader_selector_key_vs(struct si_context
*sctx
,
1198 struct si_shader_selector
*vs
,
1199 struct si_shader_key
*key
,
1200 struct si_vs_prolog_bits
*prolog_key
)
1202 if (!sctx
->vertex_elements
)
1205 prolog_key
->instance_divisor_is_one
=
1206 sctx
->vertex_elements
->instance_divisor_is_one
;
1207 prolog_key
->instance_divisor_is_fetched
=
1208 sctx
->vertex_elements
->instance_divisor_is_fetched
;
1210 /* Prefer a monolithic shader to allow scheduling divisions around
1212 if (prolog_key
->instance_divisor_is_fetched
)
1213 key
->opt
.prefer_mono
= 1;
1215 unsigned count
= MIN2(vs
->info
.num_inputs
,
1216 sctx
->vertex_elements
->count
);
1217 memcpy(key
->mono
.vs_fix_fetch
, sctx
->vertex_elements
->fix_fetch
, count
);
1220 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
,
1221 struct si_shader_selector
*vs
,
1222 struct si_shader_key
*key
)
1224 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1226 key
->opt
.clip_disable
=
1227 sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
1228 (vs
->info
.clipdist_writemask
||
1229 vs
->info
.writes_clipvertex
) &&
1230 !vs
->info
.culldist_writemask
;
1232 /* Find out if PS is disabled. */
1233 bool ps_disabled
= true;
1235 const struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1236 bool alpha_to_coverage
= blend
&& blend
->alpha_to_coverage
;
1237 bool ps_modifies_zs
= ps
->info
.uses_kill
||
1238 ps
->info
.writes_z
||
1239 ps
->info
.writes_stencil
||
1240 ps
->info
.writes_samplemask
||
1241 alpha_to_coverage
||
1242 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
1243 unsigned ps_colormask
= si_get_total_colormask(sctx
);
1245 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
1248 !ps
->info
.writes_memory
);
1251 /* Find out which VS outputs aren't used by the PS. */
1252 uint64_t outputs_written
= vs
->outputs_written_before_ps
;
1253 uint64_t inputs_read
= 0;
1255 /* Ignore outputs that are not passed from VS to PS. */
1256 outputs_written
&= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION
, 0, true)) |
1257 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE
, 0, true)) |
1258 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX
, 0, true)));
1261 inputs_read
= ps
->inputs_read
;
1264 uint64_t linked
= outputs_written
& inputs_read
;
1266 key
->opt
.kill_outputs
= ~linked
& outputs_written
;
1269 /* Compute the key for the hw shader variant */
1270 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
1271 struct si_shader_selector
*sel
,
1272 struct si_shader_key
*key
)
1274 struct si_context
*sctx
= (struct si_context
*)ctx
;
1276 memset(key
, 0, sizeof(*key
));
1278 switch (sel
->type
) {
1279 case PIPE_SHADER_VERTEX
:
1280 si_shader_selector_key_vs(sctx
, sel
, key
, &key
->part
.vs
.prolog
);
1282 if (sctx
->tes_shader
.cso
)
1284 else if (sctx
->gs_shader
.cso
)
1287 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1289 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1290 key
->mono
.u
.vs_export_prim_id
= 1;
1293 case PIPE_SHADER_TESS_CTRL
:
1294 if (sctx
->chip_class
>= GFX9
) {
1295 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1296 key
, &key
->part
.tcs
.ls_prolog
);
1297 key
->part
.tcs
.ls
= sctx
->vs_shader
.cso
;
1299 /* When the LS VGPR fix is needed, monolithic shaders
1301 * - avoid initializing EXEC in both the LS prolog
1302 * and the LS main part when !vs_needs_prolog
1303 * - remove the fixup for unused input VGPRs
1305 key
->part
.tcs
.ls_prolog
.ls_vgpr_fix
= sctx
->ls_vgpr_fix
;
1307 /* The LS output / HS input layout can be communicated
1308 * directly instead of via user SGPRs for merged LS-HS.
1309 * The LS VGPR fix prefers this too.
1311 key
->opt
.prefer_mono
= 1;
1314 key
->part
.tcs
.epilog
.prim_mode
=
1315 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1316 key
->part
.tcs
.epilog
.invoc0_tess_factors_are_def
=
1317 sel
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1318 key
->part
.tcs
.epilog
.tes_reads_tess_factors
=
1319 sctx
->tes_shader
.cso
->info
.reads_tess_factors
;
1321 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
1322 key
->mono
.u
.ff_tcs_inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
1324 case PIPE_SHADER_TESS_EVAL
:
1325 if (sctx
->gs_shader
.cso
)
1328 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1330 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1331 key
->mono
.u
.vs_export_prim_id
= 1;
1334 case PIPE_SHADER_GEOMETRY
:
1335 if (sctx
->chip_class
>= GFX9
) {
1336 if (sctx
->tes_shader
.cso
) {
1337 key
->part
.gs
.es
= sctx
->tes_shader
.cso
;
1339 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1340 key
, &key
->part
.gs
.vs_prolog
);
1341 key
->part
.gs
.es
= sctx
->vs_shader
.cso
;
1342 key
->part
.gs
.prolog
.gfx9_prev_is_vs
= 1;
1345 /* Merged ES-GS can have unbalanced wave usage.
1347 * ES threads are per-vertex, while GS threads are
1348 * per-primitive. So without any amplification, there
1349 * are fewer GS threads than ES threads, which can result
1350 * in empty (no-op) GS waves. With too much amplification,
1351 * there are more GS threads than ES threads, which
1352 * can result in empty (no-op) ES waves.
1354 * Non-monolithic shaders are implemented by setting EXEC
1355 * at the beginning of shader parts, and don't jump to
1356 * the end if EXEC is 0.
1358 * Monolithic shaders use conditional blocks, so they can
1359 * jump and skip empty waves of ES or GS. So set this to
1360 * always use optimized variants, which are monolithic.
1362 key
->opt
.prefer_mono
= 1;
1364 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
1366 case PIPE_SHADER_FRAGMENT
: {
1367 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1368 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1370 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
1371 sel
->info
.colors_written
== 0x1)
1372 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
1375 /* Select the shader color format based on whether
1376 * blending or alpha are needed.
1378 key
->part
.ps
.epilog
.spi_shader_col_format
=
1379 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1380 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
1381 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1382 sctx
->framebuffer
.spi_shader_col_format_blend
) |
1383 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1384 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
1385 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1386 sctx
->framebuffer
.spi_shader_col_format
);
1387 key
->part
.ps
.epilog
.spi_shader_col_format
&= blend
->cb_target_enabled_4bit
;
1389 /* The output for dual source blending should have
1390 * the same format as the first output.
1392 if (blend
->dual_src_blend
)
1393 key
->part
.ps
.epilog
.spi_shader_col_format
|=
1394 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
1396 key
->part
.ps
.epilog
.spi_shader_col_format
= sctx
->framebuffer
.spi_shader_col_format
;
1398 /* If alpha-to-coverage is enabled, we have to export alpha
1399 * even if there is no color buffer.
1401 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) &&
1402 blend
&& blend
->alpha_to_coverage
)
1403 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
1405 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1406 * to the range supported by the type if a channel has less
1407 * than 16 bits and the export format is 16_ABGR.
1409 if (sctx
->chip_class
<= CIK
&& sctx
->family
!= CHIP_HAWAII
) {
1410 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
1411 key
->part
.ps
.epilog
.color_is_int10
= sctx
->framebuffer
.color_is_int10
;
1414 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1415 if (!key
->part
.ps
.epilog
.last_cbuf
) {
1416 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
1417 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
1418 key
->part
.ps
.epilog
.color_is_int10
&= sel
->info
.colors_written
;
1422 bool is_poly
= (sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES
&&
1423 sctx
->current_rast_prim
<= PIPE_PRIM_POLYGON
) ||
1424 sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES_ADJACENCY
;
1425 bool is_line
= !is_poly
&& sctx
->current_rast_prim
!= PIPE_PRIM_POINTS
;
1427 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
1428 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
1430 if (sctx
->queued
.named
.blend
) {
1431 key
->part
.ps
.epilog
.alpha_to_one
= sctx
->queued
.named
.blend
->alpha_to_one
&&
1432 rs
->multisample_enable
;
1435 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
1436 key
->part
.ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
1437 (is_line
&& rs
->line_smooth
)) &&
1438 sctx
->framebuffer
.nr_samples
<= 1;
1439 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
1441 if (sctx
->ps_iter_samples
> 1 &&
1442 sel
->info
.reads_samplemask
) {
1443 key
->part
.ps
.prolog
.samplemask_log_ps_iter
=
1444 util_logbase2(sctx
->ps_iter_samples
);
1447 if (rs
->force_persample_interp
&&
1448 rs
->multisample_enable
&&
1449 sctx
->framebuffer
.nr_samples
> 1 &&
1450 sctx
->ps_iter_samples
> 1) {
1451 key
->part
.ps
.prolog
.force_persp_sample_interp
=
1452 sel
->info
.uses_persp_center
||
1453 sel
->info
.uses_persp_centroid
;
1455 key
->part
.ps
.prolog
.force_linear_sample_interp
=
1456 sel
->info
.uses_linear_center
||
1457 sel
->info
.uses_linear_centroid
;
1458 } else if (rs
->multisample_enable
&&
1459 sctx
->framebuffer
.nr_samples
> 1) {
1460 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
1461 sel
->info
.uses_persp_center
&&
1462 sel
->info
.uses_persp_centroid
;
1463 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
1464 sel
->info
.uses_linear_center
&&
1465 sel
->info
.uses_linear_centroid
;
1467 /* Make sure SPI doesn't compute more than 1 pair
1468 * of (i,j), which is the optimization here. */
1469 key
->part
.ps
.prolog
.force_persp_center_interp
=
1470 sel
->info
.uses_persp_center
+
1471 sel
->info
.uses_persp_centroid
+
1472 sel
->info
.uses_persp_sample
> 1;
1474 key
->part
.ps
.prolog
.force_linear_center_interp
=
1475 sel
->info
.uses_linear_center
+
1476 sel
->info
.uses_linear_centroid
+
1477 sel
->info
.uses_linear_sample
> 1;
1479 if (sel
->info
.opcode_count
[TGSI_OPCODE_INTERP_SAMPLE
])
1480 key
->mono
.u
.ps
.interpolate_at_sample_force_center
= 1;
1484 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
1486 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1487 if (sctx
->ps_uses_fbfetch
) {
1488 struct pipe_surface
*cb0
= sctx
->framebuffer
.state
.cbufs
[0];
1489 struct pipe_resource
*tex
= cb0
->texture
;
1491 /* 1D textures are allocated and used as 2D on GFX9. */
1492 key
->mono
.u
.ps
.fbfetch_msaa
= sctx
->framebuffer
.nr_samples
> 1;
1493 key
->mono
.u
.ps
.fbfetch_is_1D
= sctx
->chip_class
!= GFX9
&&
1494 (tex
->target
== PIPE_TEXTURE_1D
||
1495 tex
->target
== PIPE_TEXTURE_1D_ARRAY
);
1496 key
->mono
.u
.ps
.fbfetch_layered
= tex
->target
== PIPE_TEXTURE_1D_ARRAY
||
1497 tex
->target
== PIPE_TEXTURE_2D_ARRAY
||
1498 tex
->target
== PIPE_TEXTURE_CUBE
||
1499 tex
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
1500 tex
->target
== PIPE_TEXTURE_3D
;
1508 if (unlikely(sctx
->screen
->debug_flags
& DBG(NO_OPT_VARIANT
)))
1509 memset(&key
->opt
, 0, sizeof(key
->opt
));
1512 static void si_build_shader_variant(struct si_shader
*shader
,
1516 struct si_shader_selector
*sel
= shader
->selector
;
1517 struct si_screen
*sscreen
= sel
->screen
;
1518 struct si_compiler
*compiler
;
1519 struct pipe_debug_callback
*debug
= &shader
->compiler_ctx_state
.debug
;
1522 if (thread_index
>= 0) {
1524 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler_lowp
));
1525 compiler
= &sscreen
->compiler_lowp
[thread_index
];
1527 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
1528 compiler
= &sscreen
->compiler
[thread_index
];
1533 assert(!low_priority
);
1534 compiler
= shader
->compiler_ctx_state
.compiler
;
1537 r
= si_shader_create(sscreen
, compiler
, shader
, debug
);
1539 PRINT_ERR("Failed to build shader variant (type=%u) %d\n",
1541 shader
->compilation_failed
= true;
1545 if (shader
->compiler_ctx_state
.is_debug_context
) {
1546 FILE *f
= open_memstream(&shader
->shader_log
,
1547 &shader
->shader_log_size
);
1549 si_shader_dump(sscreen
, shader
, NULL
, sel
->type
, f
, false);
1554 si_shader_init_pm4_state(sscreen
, shader
);
1557 static void si_build_shader_variant_low_priority(void *job
, int thread_index
)
1559 struct si_shader
*shader
= (struct si_shader
*)job
;
1561 assert(thread_index
>= 0);
1563 si_build_shader_variant(shader
, thread_index
, true);
1566 static const struct si_shader_key zeroed
;
1568 static bool si_check_missing_main_part(struct si_screen
*sscreen
,
1569 struct si_shader_selector
*sel
,
1570 struct si_compiler_ctx_state
*compiler_state
,
1571 struct si_shader_key
*key
)
1573 struct si_shader
**mainp
= si_get_main_shader_part(sel
, key
);
1576 struct si_shader
*main_part
= CALLOC_STRUCT(si_shader
);
1581 /* We can leave the fence as permanently signaled because the
1582 * main part becomes visible globally only after it has been
1584 util_queue_fence_init(&main_part
->ready
);
1586 main_part
->selector
= sel
;
1587 main_part
->key
.as_es
= key
->as_es
;
1588 main_part
->key
.as_ls
= key
->as_ls
;
1590 if (si_compile_tgsi_shader(sscreen
, compiler_state
->compiler
,
1592 &compiler_state
->debug
) != 0) {
1601 /* Select the hw shader variant depending on the current state. */
1602 static int si_shader_select_with_key(struct si_screen
*sscreen
,
1603 struct si_shader_ctx_state
*state
,
1604 struct si_compiler_ctx_state
*compiler_state
,
1605 struct si_shader_key
*key
,
1608 struct si_shader_selector
*sel
= state
->cso
;
1609 struct si_shader_selector
*previous_stage_sel
= NULL
;
1610 struct si_shader
*current
= state
->current
;
1611 struct si_shader
*iter
, *shader
= NULL
;
1614 /* Check if we don't need to change anything.
1615 * This path is also used for most shaders that don't need multiple
1616 * variants, it will cost just a computation of the key and this
1618 if (likely(current
&&
1619 memcmp(¤t
->key
, key
, sizeof(*key
)) == 0)) {
1620 if (unlikely(!util_queue_fence_is_signalled(¤t
->ready
))) {
1621 if (current
->is_optimized
) {
1622 memset(&key
->opt
, 0, sizeof(key
->opt
));
1623 goto current_not_ready
;
1626 util_queue_fence_wait(¤t
->ready
);
1629 return current
->compilation_failed
? -1 : 0;
1633 /* This must be done before the mutex is locked, because async GS
1634 * compilation calls this function too, and therefore must enter
1637 * Only wait if we are in a draw call. Don't wait if we are
1638 * in a compiler thread.
1640 if (thread_index
< 0)
1641 util_queue_fence_wait(&sel
->ready
);
1643 mtx_lock(&sel
->mutex
);
1645 /* Find the shader variant. */
1646 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
1647 /* Don't check the "current" shader. We checked it above. */
1648 if (current
!= iter
&&
1649 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
1650 mtx_unlock(&sel
->mutex
);
1652 if (unlikely(!util_queue_fence_is_signalled(&iter
->ready
))) {
1653 /* If it's an optimized shader and its compilation has
1654 * been started but isn't done, use the unoptimized
1655 * shader so as not to cause a stall due to compilation.
1657 if (iter
->is_optimized
) {
1658 memset(&key
->opt
, 0, sizeof(key
->opt
));
1662 util_queue_fence_wait(&iter
->ready
);
1665 if (iter
->compilation_failed
) {
1666 return -1; /* skip the draw call */
1669 state
->current
= iter
;
1674 /* Build a new shader. */
1675 shader
= CALLOC_STRUCT(si_shader
);
1677 mtx_unlock(&sel
->mutex
);
1681 util_queue_fence_init(&shader
->ready
);
1683 shader
->selector
= sel
;
1685 shader
->compiler_ctx_state
= *compiler_state
;
1687 /* If this is a merged shader, get the first shader's selector. */
1688 if (sscreen
->info
.chip_class
>= GFX9
) {
1689 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
1690 previous_stage_sel
= key
->part
.tcs
.ls
;
1691 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
1692 previous_stage_sel
= key
->part
.gs
.es
;
1694 /* We need to wait for the previous shader. */
1695 if (previous_stage_sel
&& thread_index
< 0)
1696 util_queue_fence_wait(&previous_stage_sel
->ready
);
1699 /* Compile the main shader part if it doesn't exist. This can happen
1700 * if the initial guess was wrong. */
1701 bool is_pure_monolithic
=
1702 sscreen
->use_monolithic_shaders
||
1703 memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
1705 if (!is_pure_monolithic
) {
1708 /* Make sure the main shader part is present. This is needed
1709 * for shaders that can be compiled as VS, LS, or ES, and only
1710 * one of them is compiled at creation.
1712 * For merged shaders, check that the starting shader's main
1715 if (previous_stage_sel
) {
1716 struct si_shader_key shader1_key
= zeroed
;
1718 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
1719 shader1_key
.as_ls
= 1;
1720 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
1721 shader1_key
.as_es
= 1;
1725 mtx_lock(&previous_stage_sel
->mutex
);
1726 ok
= si_check_missing_main_part(sscreen
,
1728 compiler_state
, &shader1_key
);
1729 mtx_unlock(&previous_stage_sel
->mutex
);
1731 ok
= si_check_missing_main_part(sscreen
, sel
,
1732 compiler_state
, key
);
1736 mtx_unlock(&sel
->mutex
);
1737 return -ENOMEM
; /* skip the draw call */
1741 /* Keep the reference to the 1st shader of merged shaders, so that
1742 * Gallium can't destroy it before we destroy the 2nd shader.
1744 * Set sctx = NULL, because it's unused if we're not releasing
1745 * the shader, and we don't have any sctx here.
1747 si_shader_selector_reference(NULL
, &shader
->previous_stage_sel
,
1748 previous_stage_sel
);
1750 /* Monolithic-only shaders don't make a distinction between optimized
1751 * and unoptimized. */
1752 shader
->is_monolithic
=
1753 is_pure_monolithic
||
1754 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1756 shader
->is_optimized
=
1757 !is_pure_monolithic
&&
1758 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
1760 /* If it's an optimized shader, compile it asynchronously. */
1761 if (shader
->is_optimized
&&
1762 !is_pure_monolithic
&&
1764 /* Compile it asynchronously. */
1765 util_queue_add_job(&sscreen
->shader_compiler_queue_low_priority
,
1766 shader
, &shader
->ready
,
1767 si_build_shader_variant_low_priority
, NULL
);
1769 /* Add only after the ready fence was reset, to guard against a
1770 * race with si_bind_XX_shader. */
1771 if (!sel
->last_variant
) {
1772 sel
->first_variant
= shader
;
1773 sel
->last_variant
= shader
;
1775 sel
->last_variant
->next_variant
= shader
;
1776 sel
->last_variant
= shader
;
1779 /* Use the default (unoptimized) shader for now. */
1780 memset(&key
->opt
, 0, sizeof(key
->opt
));
1781 mtx_unlock(&sel
->mutex
);
1785 /* Reset the fence before adding to the variant list. */
1786 util_queue_fence_reset(&shader
->ready
);
1788 if (!sel
->last_variant
) {
1789 sel
->first_variant
= shader
;
1790 sel
->last_variant
= shader
;
1792 sel
->last_variant
->next_variant
= shader
;
1793 sel
->last_variant
= shader
;
1796 mtx_unlock(&sel
->mutex
);
1798 assert(!shader
->is_optimized
);
1799 si_build_shader_variant(shader
, thread_index
, false);
1801 util_queue_fence_signal(&shader
->ready
);
1803 if (!shader
->compilation_failed
)
1804 state
->current
= shader
;
1806 return shader
->compilation_failed
? -1 : 0;
1809 static int si_shader_select(struct pipe_context
*ctx
,
1810 struct si_shader_ctx_state
*state
,
1811 struct si_compiler_ctx_state
*compiler_state
)
1813 struct si_context
*sctx
= (struct si_context
*)ctx
;
1814 struct si_shader_key key
;
1816 si_shader_selector_key(ctx
, state
->cso
, &key
);
1817 return si_shader_select_with_key(sctx
->screen
, state
, compiler_state
,
1821 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
1823 struct si_shader_key
*key
)
1825 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
1827 switch (info
->processor
) {
1828 case PIPE_SHADER_VERTEX
:
1829 switch (next_shader
) {
1830 case PIPE_SHADER_GEOMETRY
:
1833 case PIPE_SHADER_TESS_CTRL
:
1834 case PIPE_SHADER_TESS_EVAL
:
1838 /* If POSITION isn't written, it can only be a HW VS
1839 * if streamout is used. If streamout isn't used,
1840 * assume that it's a HW LS. (the next shader is TCS)
1841 * This heuristic is needed for separate shader objects.
1843 if (!info
->writes_position
&& !streamout
)
1848 case PIPE_SHADER_TESS_EVAL
:
1849 if (next_shader
== PIPE_SHADER_GEOMETRY
||
1850 !info
->writes_position
)
1857 * Compile the main shader part or the monolithic shader as part of
1858 * si_shader_selector initialization. Since it can be done asynchronously,
1859 * there is no way to report compile failures to applications.
1861 static void si_init_shader_selector_async(void *job
, int thread_index
)
1863 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
1864 struct si_screen
*sscreen
= sel
->screen
;
1865 struct si_compiler
*compiler
;
1866 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
1868 assert(!debug
->debug_message
|| debug
->async
);
1869 assert(thread_index
>= 0);
1870 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
1871 compiler
= &sscreen
->compiler
[thread_index
];
1873 /* Compile the main shader part for use with a prolog and/or epilog.
1874 * If this fails, the driver will try to compile a monolithic shader
1877 if (!sscreen
->use_monolithic_shaders
) {
1878 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
1879 void *ir_binary
= NULL
;
1882 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
1886 /* We can leave the fence signaled because use of the default
1887 * main part is guarded by the selector's ready fence. */
1888 util_queue_fence_init(&shader
->ready
);
1890 shader
->selector
= sel
;
1891 si_parse_next_shader_property(&sel
->info
,
1892 sel
->so
.num_outputs
!= 0,
1895 if (sel
->tokens
|| sel
->nir
)
1896 ir_binary
= si_get_ir_binary(sel
);
1898 /* Try to load the shader from the shader cache. */
1899 mtx_lock(&sscreen
->shader_cache_mutex
);
1902 si_shader_cache_load_shader(sscreen
, ir_binary
, shader
)) {
1903 mtx_unlock(&sscreen
->shader_cache_mutex
);
1904 si_shader_dump_stats_for_shader_db(shader
, debug
);
1906 mtx_unlock(&sscreen
->shader_cache_mutex
);
1908 /* Compile the shader if it hasn't been loaded from the cache. */
1909 if (si_compile_tgsi_shader(sscreen
, compiler
, shader
, false,
1913 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
1918 mtx_lock(&sscreen
->shader_cache_mutex
);
1919 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
, shader
, true))
1921 mtx_unlock(&sscreen
->shader_cache_mutex
);
1925 *si_get_main_shader_part(sel
, &shader
->key
) = shader
;
1927 /* Unset "outputs_written" flags for outputs converted to
1928 * DEFAULT_VAL, so that later inter-shader optimizations don't
1929 * try to eliminate outputs that don't exist in the final
1932 * This is only done if non-monolithic shaders are enabled.
1934 if ((sel
->type
== PIPE_SHADER_VERTEX
||
1935 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
1936 !shader
->key
.as_ls
&&
1937 !shader
->key
.as_es
) {
1940 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
1941 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
1943 if (offset
<= AC_EXP_PARAM_OFFSET_31
)
1946 unsigned name
= sel
->info
.output_semantic_name
[i
];
1947 unsigned index
= sel
->info
.output_semantic_index
[i
];
1951 case TGSI_SEMANTIC_GENERIC
:
1952 /* don't process indices the function can't handle */
1953 if (index
>= SI_MAX_IO_GENERIC
)
1957 id
= si_shader_io_get_unique_index(name
, index
, true);
1958 sel
->outputs_written_before_ps
&= ~(1ull << id
);
1960 case TGSI_SEMANTIC_POSITION
: /* ignore these */
1961 case TGSI_SEMANTIC_PSIZE
:
1962 case TGSI_SEMANTIC_CLIPVERTEX
:
1963 case TGSI_SEMANTIC_EDGEFLAG
:
1970 /* The GS copy shader is always pre-compiled. */
1971 if (sel
->type
== PIPE_SHADER_GEOMETRY
) {
1972 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, compiler
, sel
, debug
);
1973 if (!sel
->gs_copy_shader
) {
1974 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
1978 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
1982 /* Return descriptor slot usage masks from the given shader info. */
1983 void si_get_active_slot_masks(const struct tgsi_shader_info
*info
,
1984 uint32_t *const_and_shader_buffers
,
1985 uint64_t *samplers_and_images
)
1987 unsigned start
, num_shaderbufs
, num_constbufs
, num_images
, num_samplers
;
1989 num_shaderbufs
= util_last_bit(info
->shader_buffers_declared
);
1990 num_constbufs
= util_last_bit(info
->const_buffers_declared
);
1991 /* two 8-byte images share one 16-byte slot */
1992 num_images
= align(util_last_bit(info
->images_declared
), 2);
1993 num_samplers
= util_last_bit(info
->samplers_declared
);
1995 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
1996 start
= si_get_shaderbuf_slot(num_shaderbufs
- 1);
1997 *const_and_shader_buffers
=
1998 u_bit_consecutive(start
, num_shaderbufs
+ num_constbufs
);
2000 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2001 start
= si_get_image_slot(num_images
- 1) / 2;
2002 *samplers_and_images
=
2003 u_bit_consecutive64(start
, num_images
/ 2 + num_samplers
);
2006 static void *si_create_shader_selector(struct pipe_context
*ctx
,
2007 const struct pipe_shader_state
*state
)
2009 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
2010 struct si_context
*sctx
= (struct si_context
*)ctx
;
2011 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
2017 pipe_reference_init(&sel
->reference
, 1);
2018 sel
->screen
= sscreen
;
2019 sel
->compiler_ctx_state
.debug
= sctx
->debug
;
2020 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
2022 sel
->so
= state
->stream_output
;
2024 if (state
->type
== PIPE_SHADER_IR_TGSI
) {
2025 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
2031 tgsi_scan_shader(state
->tokens
, &sel
->info
);
2032 tgsi_scan_tess_ctrl(state
->tokens
, &sel
->info
, &sel
->tcs_info
);
2034 assert(state
->type
== PIPE_SHADER_IR_NIR
);
2036 sel
->nir
= state
->ir
.nir
;
2038 si_nir_scan_shader(sel
->nir
, &sel
->info
);
2039 si_nir_scan_tess_ctrl(sel
->nir
, &sel
->info
, &sel
->tcs_info
);
2044 sel
->type
= sel
->info
.processor
;
2045 p_atomic_inc(&sscreen
->num_shaders_created
);
2046 si_get_active_slot_masks(&sel
->info
,
2047 &sel
->active_const_and_shader_buffers
,
2048 &sel
->active_samplers_and_images
);
2050 /* Record which streamout buffers are enabled. */
2051 for (i
= 0; i
< sel
->so
.num_outputs
; i
++) {
2052 sel
->enabled_streamout_buffer_mask
|=
2053 (1 << sel
->so
.output
[i
].output_buffer
) <<
2054 (sel
->so
.output
[i
].stream
* 4);
2057 /* The prolog is a no-op if there are no inputs. */
2058 sel
->vs_needs_prolog
= sel
->type
== PIPE_SHADER_VERTEX
&&
2059 sel
->info
.num_inputs
&&
2060 !sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
2062 sel
->force_correct_derivs_after_kill
=
2063 sel
->type
== PIPE_SHADER_FRAGMENT
&&
2064 sel
->info
.uses_derivatives
&&
2065 sel
->info
.uses_kill
&&
2066 sctx
->screen
->debug_flags
& DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
2068 /* Set which opcode uses which (i,j) pair. */
2069 if (sel
->info
.uses_persp_opcode_interp_centroid
)
2070 sel
->info
.uses_persp_centroid
= true;
2072 if (sel
->info
.uses_linear_opcode_interp_centroid
)
2073 sel
->info
.uses_linear_centroid
= true;
2075 if (sel
->info
.uses_persp_opcode_interp_offset
||
2076 sel
->info
.uses_persp_opcode_interp_sample
)
2077 sel
->info
.uses_persp_center
= true;
2079 if (sel
->info
.uses_linear_opcode_interp_offset
||
2080 sel
->info
.uses_linear_opcode_interp_sample
)
2081 sel
->info
.uses_linear_center
= true;
2083 switch (sel
->type
) {
2084 case PIPE_SHADER_GEOMETRY
:
2085 sel
->gs_output_prim
=
2086 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
2087 sel
->gs_max_out_vertices
=
2088 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
2089 sel
->gs_num_invocations
=
2090 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
2091 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
2092 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
2093 sel
->gs_max_out_vertices
;
2095 sel
->max_gs_stream
= 0;
2096 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
2097 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
2098 sel
->so
.output
[i
].stream
);
2100 sel
->gs_input_verts_per_prim
=
2101 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
2104 case PIPE_SHADER_TESS_CTRL
:
2105 /* Always reserve space for these. */
2106 sel
->patch_outputs_written
|=
2107 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0)) |
2108 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0));
2110 case PIPE_SHADER_VERTEX
:
2111 case PIPE_SHADER_TESS_EVAL
:
2112 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2113 unsigned name
= sel
->info
.output_semantic_name
[i
];
2114 unsigned index
= sel
->info
.output_semantic_index
[i
];
2117 case TGSI_SEMANTIC_TESSINNER
:
2118 case TGSI_SEMANTIC_TESSOUTER
:
2119 case TGSI_SEMANTIC_PATCH
:
2120 sel
->patch_outputs_written
|=
2121 1ull << si_shader_io_get_unique_index_patch(name
, index
);
2124 case TGSI_SEMANTIC_GENERIC
:
2125 /* don't process indices the function can't handle */
2126 if (index
>= SI_MAX_IO_GENERIC
)
2130 sel
->outputs_written
|=
2131 1ull << si_shader_io_get_unique_index(name
, index
, false);
2132 sel
->outputs_written_before_ps
|=
2133 1ull << si_shader_io_get_unique_index(name
, index
, true);
2135 case TGSI_SEMANTIC_EDGEFLAG
:
2139 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
2141 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2142 * conflicts, i.e. each vertex will start at a different bank.
2144 if (sctx
->chip_class
>= GFX9
)
2145 sel
->esgs_itemsize
+= 4;
2147 assert(((sel
->esgs_itemsize
/ 4) & C_028AAC_ITEMSIZE
) == 0);
2150 case PIPE_SHADER_FRAGMENT
:
2151 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2152 unsigned name
= sel
->info
.input_semantic_name
[i
];
2153 unsigned index
= sel
->info
.input_semantic_index
[i
];
2156 case TGSI_SEMANTIC_GENERIC
:
2157 /* don't process indices the function can't handle */
2158 if (index
>= SI_MAX_IO_GENERIC
)
2163 1ull << si_shader_io_get_unique_index(name
, index
, true);
2165 case TGSI_SEMANTIC_PCOORD
: /* ignore this */
2170 for (i
= 0; i
< 8; i
++)
2171 if (sel
->info
.colors_written
& (1 << i
))
2172 sel
->colors_written_4bit
|= 0xf << (4 * i
);
2174 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2175 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
2176 int index
= sel
->info
.input_semantic_index
[i
];
2177 sel
->color_attr_index
[index
] = i
;
2183 /* PA_CL_VS_OUT_CNTL */
2185 sel
->info
.writes_psize
|| sel
->info
.writes_edgeflag
||
2186 sel
->info
.writes_layer
|| sel
->info
.writes_viewport_index
;
2187 sel
->pa_cl_vs_out_cntl
=
2188 S_02881C_USE_VTX_POINT_SIZE(sel
->info
.writes_psize
) |
2189 S_02881C_USE_VTX_EDGE_FLAG(sel
->info
.writes_edgeflag
) |
2190 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel
->info
.writes_layer
) |
2191 S_02881C_USE_VTX_VIEWPORT_INDX(sel
->info
.writes_viewport_index
) |
2192 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
2193 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
);
2194 sel
->clipdist_mask
= sel
->info
.writes_clipvertex
?
2195 SIX_BITS
: sel
->info
.clipdist_writemask
;
2196 sel
->culldist_mask
= sel
->info
.culldist_writemask
<<
2197 sel
->info
.num_written_clipdistance
;
2199 /* DB_SHADER_CONTROL */
2200 sel
->db_shader_control
=
2201 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
2202 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
2203 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
2204 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
2206 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
2207 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2208 sel
->db_shader_control
|=
2209 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2211 case TGSI_FS_DEPTH_LAYOUT_LESS
:
2212 sel
->db_shader_control
|=
2213 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2217 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2219 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2220 * --|-----------|------------|------------|--------------------|-------------------|-------------
2221 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2222 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2223 * 2 | false | true | n/a | LateZ | 1 | 0
2224 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2225 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2227 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2228 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2230 * Don't use ReZ without profiling !!!
2232 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2235 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
2237 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
2238 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
2239 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
2240 } else if (sel
->info
.writes_memory
) {
2242 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) |
2243 S_02880C_EXEC_ON_HIER_FAIL(1);
2246 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2249 (void) mtx_init(&sel
->mutex
, mtx_plain
);
2250 util_queue_fence_init(&sel
->ready
);
2252 struct util_async_debug_callback async_debug
;
2254 (sctx
->debug
.debug_message
&& !sctx
->debug
.async
) ||
2256 si_can_dump_shader(sscreen
, sel
->info
.processor
);
2259 u_async_debug_init(&async_debug
);
2260 sel
->compiler_ctx_state
.debug
= async_debug
.base
;
2263 util_queue_add_job(&sscreen
->shader_compiler_queue
, sel
,
2264 &sel
->ready
, si_init_shader_selector_async
,
2268 util_queue_fence_wait(&sel
->ready
);
2269 u_async_debug_drain(&async_debug
, &sctx
->debug
);
2270 u_async_debug_cleanup(&async_debug
);
2276 static void si_update_streamout_state(struct si_context
*sctx
)
2278 struct si_shader_selector
*shader_with_so
= si_get_vs(sctx
)->cso
;
2280 if (!shader_with_so
)
2283 sctx
->streamout
.enabled_stream_buffers_mask
=
2284 shader_with_so
->enabled_streamout_buffer_mask
;
2285 sctx
->streamout
.stride_in_dw
= shader_with_so
->so
.stride
;
2288 static void si_update_clip_regs(struct si_context
*sctx
,
2289 struct si_shader_selector
*old_hw_vs
,
2290 struct si_shader
*old_hw_vs_variant
,
2291 struct si_shader_selector
*next_hw_vs
,
2292 struct si_shader
*next_hw_vs_variant
)
2296 old_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] !=
2297 next_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] ||
2298 old_hw_vs
->pa_cl_vs_out_cntl
!= next_hw_vs
->pa_cl_vs_out_cntl
||
2299 old_hw_vs
->clipdist_mask
!= next_hw_vs
->clipdist_mask
||
2300 old_hw_vs
->culldist_mask
!= next_hw_vs
->culldist_mask
||
2301 !old_hw_vs_variant
||
2302 !next_hw_vs_variant
||
2303 old_hw_vs_variant
->key
.opt
.clip_disable
!=
2304 next_hw_vs_variant
->key
.opt
.clip_disable
))
2305 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
2308 static void si_update_common_shader_state(struct si_context
*sctx
)
2310 sctx
->uses_bindless_samplers
=
2311 si_shader_uses_bindless_samplers(sctx
->vs_shader
.cso
) ||
2312 si_shader_uses_bindless_samplers(sctx
->gs_shader
.cso
) ||
2313 si_shader_uses_bindless_samplers(sctx
->ps_shader
.cso
) ||
2314 si_shader_uses_bindless_samplers(sctx
->tcs_shader
.cso
) ||
2315 si_shader_uses_bindless_samplers(sctx
->tes_shader
.cso
);
2316 sctx
->uses_bindless_images
=
2317 si_shader_uses_bindless_images(sctx
->vs_shader
.cso
) ||
2318 si_shader_uses_bindless_images(sctx
->gs_shader
.cso
) ||
2319 si_shader_uses_bindless_images(sctx
->ps_shader
.cso
) ||
2320 si_shader_uses_bindless_images(sctx
->tcs_shader
.cso
) ||
2321 si_shader_uses_bindless_images(sctx
->tes_shader
.cso
);
2322 sctx
->do_update_shaders
= true;
2325 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
2327 struct si_context
*sctx
= (struct si_context
*)ctx
;
2328 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2329 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2330 struct si_shader_selector
*sel
= state
;
2332 if (sctx
->vs_shader
.cso
== sel
)
2335 sctx
->vs_shader
.cso
= sel
;
2336 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2337 sctx
->num_vs_blit_sgprs
= sel
? sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
] : 0;
2339 si_update_common_shader_state(sctx
);
2340 si_update_vs_viewport_state(sctx
);
2341 si_set_active_descriptors_for_shader(sctx
, sel
);
2342 si_update_streamout_state(sctx
);
2343 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2344 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2347 static void si_update_tess_uses_prim_id(struct si_context
*sctx
)
2349 sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
=
2350 (sctx
->tes_shader
.cso
&&
2351 sctx
->tes_shader
.cso
->info
.uses_primid
) ||
2352 (sctx
->tcs_shader
.cso
&&
2353 sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
2354 (sctx
->gs_shader
.cso
&&
2355 sctx
->gs_shader
.cso
->info
.uses_primid
) ||
2356 (sctx
->ps_shader
.cso
&& !sctx
->gs_shader
.cso
&&
2357 sctx
->ps_shader
.cso
->info
.uses_primid
);
2360 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
2362 struct si_context
*sctx
= (struct si_context
*)ctx
;
2363 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2364 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2365 struct si_shader_selector
*sel
= state
;
2366 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
2368 if (sctx
->gs_shader
.cso
== sel
)
2371 sctx
->gs_shader
.cso
= sel
;
2372 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2373 sctx
->ia_multi_vgt_param_key
.u
.uses_gs
= sel
!= NULL
;
2375 si_update_common_shader_state(sctx
);
2376 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2378 if (enable_changed
) {
2379 si_shader_change_notify(sctx
);
2380 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2381 si_update_tess_uses_prim_id(sctx
);
2383 si_update_vs_viewport_state(sctx
);
2384 si_set_active_descriptors_for_shader(sctx
, sel
);
2385 si_update_streamout_state(sctx
);
2386 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2387 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2390 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
2392 struct si_context
*sctx
= (struct si_context
*)ctx
;
2393 struct si_shader_selector
*sel
= state
;
2394 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
2396 if (sctx
->tcs_shader
.cso
== sel
)
2399 sctx
->tcs_shader
.cso
= sel
;
2400 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2401 si_update_tess_uses_prim_id(sctx
);
2403 si_update_common_shader_state(sctx
);
2406 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
2408 si_set_active_descriptors_for_shader(sctx
, sel
);
2411 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
2413 struct si_context
*sctx
= (struct si_context
*)ctx
;
2414 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2415 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2416 struct si_shader_selector
*sel
= state
;
2417 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
2419 if (sctx
->tes_shader
.cso
== sel
)
2422 sctx
->tes_shader
.cso
= sel
;
2423 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
2424 sctx
->ia_multi_vgt_param_key
.u
.uses_tess
= sel
!= NULL
;
2425 si_update_tess_uses_prim_id(sctx
);
2427 si_update_common_shader_state(sctx
);
2428 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
2430 if (enable_changed
) {
2431 si_shader_change_notify(sctx
);
2432 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
2434 si_update_vs_viewport_state(sctx
);
2435 si_set_active_descriptors_for_shader(sctx
, sel
);
2436 si_update_streamout_state(sctx
);
2437 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2438 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2441 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
2443 struct si_context
*sctx
= (struct si_context
*)ctx
;
2444 struct si_shader_selector
*old_sel
= sctx
->ps_shader
.cso
;
2445 struct si_shader_selector
*sel
= state
;
2447 /* skip if supplied shader is one already in use */
2451 sctx
->ps_shader
.cso
= sel
;
2452 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
2454 si_update_common_shader_state(sctx
);
2456 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2457 si_update_tess_uses_prim_id(sctx
);
2460 old_sel
->info
.colors_written
!= sel
->info
.colors_written
)
2461 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
2463 if (sctx
->screen
->has_out_of_order_rast
&&
2465 old_sel
->info
.writes_memory
!= sel
->info
.writes_memory
||
2466 old_sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] !=
2467 sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]))
2468 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2470 si_set_active_descriptors_for_shader(sctx
, sel
);
2471 si_update_ps_colorbuf0_slot(sctx
);
2474 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
2476 if (shader
->is_optimized
) {
2477 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue_low_priority
,
2481 util_queue_fence_destroy(&shader
->ready
);
2484 switch (shader
->selector
->type
) {
2485 case PIPE_SHADER_VERTEX
:
2486 if (shader
->key
.as_ls
) {
2487 assert(sctx
->chip_class
<= VI
);
2488 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
2489 } else if (shader
->key
.as_es
) {
2490 assert(sctx
->chip_class
<= VI
);
2491 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2493 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2496 case PIPE_SHADER_TESS_CTRL
:
2497 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
2499 case PIPE_SHADER_TESS_EVAL
:
2500 if (shader
->key
.as_es
) {
2501 assert(sctx
->chip_class
<= VI
);
2502 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
2504 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2507 case PIPE_SHADER_GEOMETRY
:
2508 if (shader
->is_gs_copy_shader
)
2509 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
2511 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
2513 case PIPE_SHADER_FRAGMENT
:
2514 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
2519 si_shader_selector_reference(sctx
, &shader
->previous_stage_sel
, NULL
);
2520 si_shader_destroy(shader
);
2524 void si_destroy_shader_selector(struct si_context
*sctx
,
2525 struct si_shader_selector
*sel
)
2527 struct si_shader
*p
= sel
->first_variant
, *c
;
2528 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
2529 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
2530 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
2531 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
2532 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
2533 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
2536 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue
, &sel
->ready
);
2538 if (current_shader
[sel
->type
]->cso
== sel
) {
2539 current_shader
[sel
->type
]->cso
= NULL
;
2540 current_shader
[sel
->type
]->current
= NULL
;
2544 c
= p
->next_variant
;
2545 si_delete_shader(sctx
, p
);
2549 if (sel
->main_shader_part
)
2550 si_delete_shader(sctx
, sel
->main_shader_part
);
2551 if (sel
->main_shader_part_ls
)
2552 si_delete_shader(sctx
, sel
->main_shader_part_ls
);
2553 if (sel
->main_shader_part_es
)
2554 si_delete_shader(sctx
, sel
->main_shader_part_es
);
2555 if (sel
->gs_copy_shader
)
2556 si_delete_shader(sctx
, sel
->gs_copy_shader
);
2558 util_queue_fence_destroy(&sel
->ready
);
2559 mtx_destroy(&sel
->mutex
);
2561 ralloc_free(sel
->nir
);
2565 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
2567 struct si_context
*sctx
= (struct si_context
*)ctx
;
2568 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
2570 si_shader_selector_reference(sctx
, &sel
, NULL
);
2573 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
2574 struct si_shader
*vs
, unsigned name
,
2575 unsigned index
, unsigned interpolate
)
2577 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
2578 unsigned j
, offset
, ps_input_cntl
= 0;
2580 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
2581 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
))
2582 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
2584 if (name
== TGSI_SEMANTIC_PCOORD
||
2585 (name
== TGSI_SEMANTIC_TEXCOORD
&&
2586 sctx
->sprite_coord_enable
& (1 << index
))) {
2587 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
2590 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
2591 if (name
== vsinfo
->output_semantic_name
[j
] &&
2592 index
== vsinfo
->output_semantic_index
[j
]) {
2593 offset
= vs
->info
.vs_output_param_offset
[j
];
2595 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
2596 /* The input is loaded from parameter memory. */
2597 ps_input_cntl
|= S_028644_OFFSET(offset
);
2598 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2599 if (offset
== AC_EXP_PARAM_UNDEFINED
) {
2600 /* This can happen with depth-only rendering. */
2603 /* The input is a DEFAULT_VAL constant. */
2604 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
2605 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
2606 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
2609 ps_input_cntl
= S_028644_OFFSET(0x20) |
2610 S_028644_DEFAULT_VAL(offset
);
2616 if (name
== TGSI_SEMANTIC_PRIMID
)
2617 /* PrimID is written after the last output. */
2618 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
2619 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
2620 /* No corresponding output found, load defaults into input.
2621 * Don't set any other bits.
2622 * (FLAT_SHADE=1 completely changes behavior) */
2623 ps_input_cntl
= S_028644_OFFSET(0x20);
2624 /* D3D 9 behaviour. GL is undefined */
2625 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
2626 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
2628 return ps_input_cntl
;
2631 static void si_emit_spi_map(struct si_context
*sctx
)
2633 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
2634 struct si_shader
*ps
= sctx
->ps_shader
.current
;
2635 struct si_shader
*vs
= si_get_vs_state(sctx
);
2636 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
2637 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
2639 if (!ps
|| !ps
->selector
->info
.num_inputs
)
2642 num_interp
= si_get_ps_num_interp(ps
);
2643 assert(num_interp
> 0);
2644 radeon_set_context_reg_seq(cs
, R_028644_SPI_PS_INPUT_CNTL_0
, num_interp
);
2646 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
2647 unsigned name
= psinfo
->input_semantic_name
[i
];
2648 unsigned index
= psinfo
->input_semantic_index
[i
];
2649 unsigned interpolate
= psinfo
->input_interpolate
[i
];
2651 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, name
, index
,
2655 if (name
== TGSI_SEMANTIC_COLOR
) {
2656 assert(index
< ARRAY_SIZE(bcol_interp
));
2657 bcol_interp
[index
] = interpolate
;
2661 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
2662 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
2664 for (i
= 0; i
< 2; i
++) {
2665 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
2668 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, bcol
,
2669 i
, bcol_interp
[i
]));
2673 assert(num_interp
== num_written
);
2677 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2679 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
2681 if (sctx
->init_config_has_vgt_flush
)
2684 /* Done by Vulkan before VGT_FLUSH. */
2685 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2686 si_pm4_cmd_add(sctx
->init_config
,
2687 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2688 si_pm4_cmd_end(sctx
->init_config
, false);
2690 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2691 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
2692 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
2693 si_pm4_cmd_end(sctx
->init_config
, false);
2694 sctx
->init_config_has_vgt_flush
= true;
2697 /* Initialize state related to ESGS / GSVS ring buffers */
2698 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
2700 struct si_shader_selector
*es
=
2701 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
2702 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
2703 struct si_pm4_state
*pm4
;
2705 /* Chip constants. */
2706 unsigned num_se
= sctx
->screen
->info
.max_se
;
2707 unsigned wave_size
= 64;
2708 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
2709 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2710 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2712 unsigned gs_vertex_reuse
= (sctx
->chip_class
>= VI
? 32 : 16) * num_se
;
2713 unsigned alignment
= 256 * num_se
;
2714 /* The maximum size is 63.999 MB per SE. */
2715 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
2717 /* Calculate the minimum size. */
2718 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
2719 wave_size
, alignment
);
2721 /* These are recommended sizes, not minimum sizes. */
2722 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
2723 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
2724 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
2725 gs
->max_gsvs_emit_size
;
2727 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
2728 esgs_ring_size
= align(esgs_ring_size
, alignment
);
2729 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
2731 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
2732 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
2734 /* Some rings don't have to be allocated if shaders don't use them.
2735 * (e.g. no varyings between ES and GS or GS and VS)
2737 * GFX9 doesn't have the ESGS ring.
2739 bool update_esgs
= sctx
->chip_class
<= VI
&&
2741 (!sctx
->esgs_ring
||
2742 sctx
->esgs_ring
->width0
< esgs_ring_size
);
2743 bool update_gsvs
= gsvs_ring_size
&&
2744 (!sctx
->gsvs_ring
||
2745 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
2747 if (!update_esgs
&& !update_gsvs
)
2751 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
2753 pipe_aligned_buffer_create(sctx
->b
.screen
,
2754 SI_RESOURCE_FLAG_UNMAPPABLE
,
2756 esgs_ring_size
, alignment
);
2757 if (!sctx
->esgs_ring
)
2762 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
2764 pipe_aligned_buffer_create(sctx
->b
.screen
,
2765 SI_RESOURCE_FLAG_UNMAPPABLE
,
2767 gsvs_ring_size
, alignment
);
2768 if (!sctx
->gsvs_ring
)
2772 /* Create the "init_config_gs_rings" state. */
2773 pm4
= CALLOC_STRUCT(si_pm4_state
);
2777 if (sctx
->chip_class
>= CIK
) {
2778 if (sctx
->esgs_ring
) {
2779 assert(sctx
->chip_class
<= VI
);
2780 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
2781 sctx
->esgs_ring
->width0
/ 256);
2783 if (sctx
->gsvs_ring
)
2784 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
2785 sctx
->gsvs_ring
->width0
/ 256);
2787 if (sctx
->esgs_ring
)
2788 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
2789 sctx
->esgs_ring
->width0
/ 256);
2790 if (sctx
->gsvs_ring
)
2791 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
2792 sctx
->gsvs_ring
->width0
/ 256);
2795 /* Set the state. */
2796 if (sctx
->init_config_gs_rings
)
2797 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
2798 sctx
->init_config_gs_rings
= pm4
;
2800 if (!sctx
->init_config_has_vgt_flush
) {
2801 si_init_config_add_vgt_flush(sctx
);
2802 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
2805 /* Flush the context to re-emit both init_config states. */
2806 sctx
->initial_gfx_cs_size
= 0; /* force flush */
2807 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
2809 /* Set ring bindings. */
2810 if (sctx
->esgs_ring
) {
2811 assert(sctx
->chip_class
<= VI
);
2812 si_set_ring_buffer(sctx
, SI_ES_RING_ESGS
,
2813 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
2814 true, true, 4, 64, 0);
2815 si_set_ring_buffer(sctx
, SI_GS_RING_ESGS
,
2816 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
2817 false, false, 0, 0, 0);
2819 if (sctx
->gsvs_ring
) {
2820 si_set_ring_buffer(sctx
, SI_RING_GSVS
,
2821 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
2822 false, false, 0, 0, 0);
2828 static void si_shader_lock(struct si_shader
*shader
)
2830 mtx_lock(&shader
->selector
->mutex
);
2831 if (shader
->previous_stage_sel
) {
2832 assert(shader
->previous_stage_sel
!= shader
->selector
);
2833 mtx_lock(&shader
->previous_stage_sel
->mutex
);
2837 static void si_shader_unlock(struct si_shader
*shader
)
2839 if (shader
->previous_stage_sel
)
2840 mtx_unlock(&shader
->previous_stage_sel
->mutex
);
2841 mtx_unlock(&shader
->selector
->mutex
);
2845 * @returns 1 if \p sel has been updated to use a new scratch buffer
2847 * < 0 if there was a failure
2849 static int si_update_scratch_buffer(struct si_context
*sctx
,
2850 struct si_shader
*shader
)
2852 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
2858 /* This shader doesn't need a scratch buffer */
2859 if (shader
->config
.scratch_bytes_per_wave
== 0)
2862 /* Prevent race conditions when updating:
2863 * - si_shader::scratch_bo
2864 * - si_shader::binary::code
2865 * - si_shader::previous_stage::binary::code.
2867 si_shader_lock(shader
);
2869 /* This shader is already configured to use the current
2870 * scratch buffer. */
2871 if (shader
->scratch_bo
== sctx
->scratch_buffer
) {
2872 si_shader_unlock(shader
);
2876 assert(sctx
->scratch_buffer
);
2878 if (shader
->previous_stage
)
2879 si_shader_apply_scratch_relocs(shader
->previous_stage
, scratch_va
);
2881 si_shader_apply_scratch_relocs(shader
, scratch_va
);
2883 /* Replace the shader bo with a new bo that has the relocs applied. */
2884 r
= si_shader_binary_upload(sctx
->screen
, shader
);
2886 si_shader_unlock(shader
);
2890 /* Update the shader state to use the new shader bo. */
2891 si_shader_init_pm4_state(sctx
->screen
, shader
);
2893 r600_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
2895 si_shader_unlock(shader
);
2899 static unsigned si_get_current_scratch_buffer_size(struct si_context
*sctx
)
2901 return sctx
->scratch_buffer
? sctx
->scratch_buffer
->b
.b
.width0
: 0;
2904 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
2906 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
2909 static struct si_shader
*si_get_tcs_current(struct si_context
*sctx
)
2911 if (!sctx
->tes_shader
.cso
)
2912 return NULL
; /* tessellation disabled */
2914 return sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.current
:
2915 sctx
->fixed_func_tcs_shader
.current
;
2918 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context
*sctx
)
2922 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
2923 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
2924 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
2925 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
2927 if (sctx
->tes_shader
.cso
) {
2928 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
2930 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(tcs
));
2935 static bool si_update_scratch_relocs(struct si_context
*sctx
)
2937 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
2940 /* Update the shaders, so that they are using the latest scratch.
2941 * The scratch buffer may have been changed since these shaders were
2942 * last used, so we still need to try to update them, even if they
2943 * require scratch buffers smaller than the current size.
2945 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
2949 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
2951 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
2955 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
2957 r
= si_update_scratch_buffer(sctx
, tcs
);
2961 si_pm4_bind_state(sctx
, hs
, tcs
->pm4
);
2963 /* VS can be bound as LS, ES, or VS. */
2964 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
2968 if (sctx
->tes_shader
.current
)
2969 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
2970 else if (sctx
->gs_shader
.current
)
2971 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
2973 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
2976 /* TES can be bound as ES or VS. */
2977 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
2981 if (sctx
->gs_shader
.current
)
2982 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
2984 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
2990 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
2992 unsigned current_scratch_buffer_size
=
2993 si_get_current_scratch_buffer_size(sctx
);
2994 unsigned scratch_bytes_per_wave
=
2995 si_get_max_scratch_bytes_per_wave(sctx
);
2996 unsigned scratch_needed_size
= scratch_bytes_per_wave
*
2997 sctx
->scratch_waves
;
2998 unsigned spi_tmpring_size
;
3000 if (scratch_needed_size
> 0) {
3001 if (scratch_needed_size
> current_scratch_buffer_size
) {
3002 /* Create a bigger scratch buffer */
3003 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
3005 sctx
->scratch_buffer
=
3006 si_aligned_buffer_create(&sctx
->screen
->b
,
3007 SI_RESOURCE_FLAG_UNMAPPABLE
,
3009 scratch_needed_size
, 256);
3010 if (!sctx
->scratch_buffer
)
3013 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3014 si_context_add_resource_size(sctx
,
3015 &sctx
->scratch_buffer
->b
.b
);
3018 if (!si_update_scratch_relocs(sctx
))
3022 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3023 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
3024 "scratch size should already be aligned correctly.");
3026 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
3027 S_0286E8_WAVESIZE(scratch_bytes_per_wave
>> 10);
3028 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
3029 sctx
->spi_tmpring_size
= spi_tmpring_size
;
3030 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3035 static void si_init_tess_factor_ring(struct si_context
*sctx
)
3037 assert(!sctx
->tess_rings
);
3039 /* The address must be aligned to 2^19, because the shader only
3040 * receives the high 13 bits.
3042 sctx
->tess_rings
= pipe_aligned_buffer_create(sctx
->b
.screen
,
3043 SI_RESOURCE_FLAG_32BIT
,
3045 sctx
->screen
->tess_offchip_ring_size
+
3046 sctx
->screen
->tess_factor_ring_size
,
3048 if (!sctx
->tess_rings
)
3051 si_init_config_add_vgt_flush(sctx
);
3053 si_pm4_add_bo(sctx
->init_config
, r600_resource(sctx
->tess_rings
),
3054 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
3056 uint64_t factor_va
= r600_resource(sctx
->tess_rings
)->gpu_address
+
3057 sctx
->screen
->tess_offchip_ring_size
;
3059 /* Append these registers to the init config state. */
3060 if (sctx
->chip_class
>= CIK
) {
3061 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
3062 S_030938_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3063 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
3065 if (sctx
->chip_class
>= GFX9
)
3066 si_pm4_set_reg(sctx
->init_config
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3067 S_030944_BASE_HI(factor_va
>> 40));
3068 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3069 sctx
->screen
->vgt_hs_offchip_param
);
3071 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
3072 S_008988_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3073 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
3075 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3076 sctx
->screen
->vgt_hs_offchip_param
);
3079 /* Flush the context to re-emit the init_config state.
3080 * This is done only once in a lifetime of a context.
3082 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3083 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3084 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3088 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
3089 * VS passes its outputs to TES directly, so the fixed-function shader only
3090 * has to write TESSOUTER and TESSINNER.
3092 static void si_generate_fixed_func_tcs(struct si_context
*sctx
)
3094 struct ureg_src outer
, inner
;
3095 struct ureg_dst tessouter
, tessinner
;
3096 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_TESS_CTRL
);
3099 return; /* if we get here, we're screwed */
3101 assert(!sctx
->fixed_func_tcs_shader
.cso
);
3103 outer
= ureg_DECL_system_value(ureg
,
3104 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
, 0);
3105 inner
= ureg_DECL_system_value(ureg
,
3106 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
, 0);
3108 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
3109 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
3111 ureg_MOV(ureg
, tessouter
, outer
);
3112 ureg_MOV(ureg
, tessinner
, inner
);
3115 sctx
->fixed_func_tcs_shader
.cso
=
3116 ureg_create_shader_and_destroy(ureg
, &sctx
->b
);
3119 static void si_update_vgt_shader_config(struct si_context
*sctx
)
3121 /* Calculate the index of the config.
3122 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3123 unsigned index
= 2*!!sctx
->tes_shader
.cso
+ !!sctx
->gs_shader
.cso
;
3124 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[index
];
3127 uint32_t stages
= 0;
3129 *pm4
= CALLOC_STRUCT(si_pm4_state
);
3131 if (sctx
->tes_shader
.cso
) {
3132 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3133 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3135 if (sctx
->gs_shader
.cso
)
3136 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3138 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3140 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3141 } else if (sctx
->gs_shader
.cso
) {
3142 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3144 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3147 if (sctx
->chip_class
>= GFX9
)
3148 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3150 si_pm4_set_reg(*pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
3152 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
3155 bool si_update_shaders(struct si_context
*sctx
)
3157 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
3158 struct si_compiler_ctx_state compiler_state
;
3159 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3160 struct si_shader
*old_vs
= si_get_vs_state(sctx
);
3161 bool old_clip_disable
= old_vs
? old_vs
->key
.opt
.clip_disable
: false;
3162 struct si_shader
*old_ps
= sctx
->ps_shader
.current
;
3163 unsigned old_spi_shader_col_format
=
3164 old_ps
? old_ps
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
3167 compiler_state
.compiler
= &sctx
->compiler
;
3168 compiler_state
.debug
= sctx
->debug
;
3169 compiler_state
.is_debug_context
= sctx
->is_debug
;
3171 /* Update stages before GS. */
3172 if (sctx
->tes_shader
.cso
) {
3173 if (!sctx
->tess_rings
) {
3174 si_init_tess_factor_ring(sctx
);
3175 if (!sctx
->tess_rings
)
3180 if (sctx
->chip_class
<= VI
) {
3181 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
3185 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3188 if (sctx
->tcs_shader
.cso
) {
3189 r
= si_shader_select(ctx
, &sctx
->tcs_shader
,
3193 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
3195 if (!sctx
->fixed_func_tcs_shader
.cso
) {
3196 si_generate_fixed_func_tcs(sctx
);
3197 if (!sctx
->fixed_func_tcs_shader
.cso
)
3201 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
,
3205 si_pm4_bind_state(sctx
, hs
,
3206 sctx
->fixed_func_tcs_shader
.current
->pm4
);
3209 if (sctx
->gs_shader
.cso
) {
3211 if (sctx
->chip_class
<= VI
) {
3212 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
3216 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3220 r
= si_shader_select(ctx
, &sctx
->tes_shader
,
3224 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3226 } else if (sctx
->gs_shader
.cso
) {
3227 if (sctx
->chip_class
<= VI
) {
3229 r
= si_shader_select(ctx
, &sctx
->vs_shader
,
3233 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3235 si_pm4_bind_state(sctx
, ls
, NULL
);
3236 si_pm4_bind_state(sctx
, hs
, NULL
);
3240 r
= si_shader_select(ctx
, &sctx
->vs_shader
, &compiler_state
);
3243 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3244 si_pm4_bind_state(sctx
, ls
, NULL
);
3245 si_pm4_bind_state(sctx
, hs
, NULL
);
3249 if (sctx
->gs_shader
.cso
) {
3250 r
= si_shader_select(ctx
, &sctx
->gs_shader
, &compiler_state
);
3253 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3254 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
3256 if (!si_update_gs_ring_buffers(sctx
))
3259 si_pm4_bind_state(sctx
, gs
, NULL
);
3260 if (sctx
->chip_class
<= VI
)
3261 si_pm4_bind_state(sctx
, es
, NULL
);
3264 si_update_vgt_shader_config(sctx
);
3266 if (old_clip_disable
!= si_get_vs_state(sctx
)->key
.opt
.clip_disable
)
3267 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
3269 if (sctx
->ps_shader
.cso
) {
3270 unsigned db_shader_control
;
3272 r
= si_shader_select(ctx
, &sctx
->ps_shader
, &compiler_state
);
3275 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3278 sctx
->ps_shader
.cso
->db_shader_control
|
3279 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
3281 if (si_pm4_state_changed(sctx
, ps
) || si_pm4_state_changed(sctx
, vs
) ||
3282 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
3283 sctx
->flatshade
!= rs
->flatshade
) {
3284 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
3285 sctx
->flatshade
= rs
->flatshade
;
3286 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.spi_map
);
3289 if (sctx
->screen
->rbplus_allowed
&&
3290 si_pm4_state_changed(sctx
, ps
) &&
3292 old_spi_shader_col_format
!=
3293 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
))
3294 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3296 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
3297 sctx
->ps_db_shader_control
= db_shader_control
;
3298 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3299 if (sctx
->screen
->dpbb_allowed
)
3300 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3303 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
3304 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
3305 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3307 if (sctx
->chip_class
== SI
)
3308 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3310 if (sctx
->framebuffer
.nr_samples
<= 1)
3311 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
3315 if (si_pm4_state_enabled_and_changed(sctx
, ls
) ||
3316 si_pm4_state_enabled_and_changed(sctx
, hs
) ||
3317 si_pm4_state_enabled_and_changed(sctx
, es
) ||
3318 si_pm4_state_enabled_and_changed(sctx
, gs
) ||
3319 si_pm4_state_enabled_and_changed(sctx
, vs
) ||
3320 si_pm4_state_enabled_and_changed(sctx
, ps
)) {
3321 if (!si_update_spi_tmpring_size(sctx
))
3325 if (sctx
->chip_class
>= CIK
) {
3326 if (si_pm4_state_enabled_and_changed(sctx
, ls
))
3327 sctx
->prefetch_L2_mask
|= SI_PREFETCH_LS
;
3328 else if (!sctx
->queued
.named
.ls
)
3329 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_LS
;
3331 if (si_pm4_state_enabled_and_changed(sctx
, hs
))
3332 sctx
->prefetch_L2_mask
|= SI_PREFETCH_HS
;
3333 else if (!sctx
->queued
.named
.hs
)
3334 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_HS
;
3336 if (si_pm4_state_enabled_and_changed(sctx
, es
))
3337 sctx
->prefetch_L2_mask
|= SI_PREFETCH_ES
;
3338 else if (!sctx
->queued
.named
.es
)
3339 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_ES
;
3341 if (si_pm4_state_enabled_and_changed(sctx
, gs
))
3342 sctx
->prefetch_L2_mask
|= SI_PREFETCH_GS
;
3343 else if (!sctx
->queued
.named
.gs
)
3344 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_GS
;
3346 if (si_pm4_state_enabled_and_changed(sctx
, vs
))
3347 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VS
;
3348 else if (!sctx
->queued
.named
.vs
)
3349 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_VS
;
3351 if (si_pm4_state_enabled_and_changed(sctx
, ps
))
3352 sctx
->prefetch_L2_mask
|= SI_PREFETCH_PS
;
3353 else if (!sctx
->queued
.named
.ps
)
3354 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_PS
;
3357 sctx
->do_update_shaders
= false;
3361 static void si_emit_scratch_state(struct si_context
*sctx
)
3363 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
3365 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
3366 sctx
->spi_tmpring_size
);
3368 if (sctx
->scratch_buffer
) {
3369 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3370 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
3371 RADEON_PRIO_SCRATCH_BUFFER
);
3375 void *si_get_blit_vs(struct si_context
*sctx
, enum blitter_attrib_type type
,
3376 unsigned num_layers
)
3378 unsigned vs_blit_property
;
3382 case UTIL_BLITTER_ATTRIB_NONE
:
3383 vs
= num_layers
> 1 ? &sctx
->vs_blit_pos_layered
:
3385 vs_blit_property
= SI_VS_BLIT_SGPRS_POS
;
3387 case UTIL_BLITTER_ATTRIB_COLOR
:
3388 vs
= num_layers
> 1 ? &sctx
->vs_blit_color_layered
:
3389 &sctx
->vs_blit_color
;
3390 vs_blit_property
= SI_VS_BLIT_SGPRS_POS_COLOR
;
3392 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY
:
3393 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW
:
3394 assert(num_layers
== 1);
3395 vs
= &sctx
->vs_blit_texcoord
;
3396 vs_blit_property
= SI_VS_BLIT_SGPRS_POS_TEXCOORD
;
3405 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_VERTEX
);
3409 /* Tell the shader to load VS inputs from SGPRs: */
3410 ureg_property(ureg
, TGSI_PROPERTY_VS_BLIT_SGPRS
, vs_blit_property
);
3411 ureg_property(ureg
, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
, true);
3413 /* This is just a pass-through shader with 1-3 MOV instructions. */
3415 ureg_DECL_output(ureg
, TGSI_SEMANTIC_POSITION
, 0),
3416 ureg_DECL_vs_input(ureg
, 0));
3418 if (type
!= UTIL_BLITTER_ATTRIB_NONE
) {
3420 ureg_DECL_output(ureg
, TGSI_SEMANTIC_GENERIC
, 0),
3421 ureg_DECL_vs_input(ureg
, 1));
3424 if (num_layers
> 1) {
3425 struct ureg_src instance_id
=
3426 ureg_DECL_system_value(ureg
, TGSI_SEMANTIC_INSTANCEID
, 0);
3427 struct ureg_dst layer
=
3428 ureg_DECL_output(ureg
, TGSI_SEMANTIC_LAYER
, 0);
3430 ureg_MOV(ureg
, ureg_writemask(layer
, TGSI_WRITEMASK_X
),
3431 ureg_scalar(instance_id
, TGSI_SWIZZLE_X
));
3435 *vs
= ureg_create_shader_and_destroy(ureg
, &sctx
->b
);
3439 void si_init_shader_functions(struct si_context
*sctx
)
3441 sctx
->atoms
.s
.spi_map
.emit
= si_emit_spi_map
;
3442 sctx
->atoms
.s
.scratch_state
.emit
= si_emit_scratch_state
;
3444 sctx
->b
.create_vs_state
= si_create_shader_selector
;
3445 sctx
->b
.create_tcs_state
= si_create_shader_selector
;
3446 sctx
->b
.create_tes_state
= si_create_shader_selector
;
3447 sctx
->b
.create_gs_state
= si_create_shader_selector
;
3448 sctx
->b
.create_fs_state
= si_create_shader_selector
;
3450 sctx
->b
.bind_vs_state
= si_bind_vs_shader
;
3451 sctx
->b
.bind_tcs_state
= si_bind_tcs_shader
;
3452 sctx
->b
.bind_tes_state
= si_bind_tes_shader
;
3453 sctx
->b
.bind_gs_state
= si_bind_gs_shader
;
3454 sctx
->b
.bind_fs_state
= si_bind_ps_shader
;
3456 sctx
->b
.delete_vs_state
= si_delete_shader_selector
;
3457 sctx
->b
.delete_tcs_state
= si_delete_shader_selector
;
3458 sctx
->b
.delete_tes_state
= si_delete_shader_selector
;
3459 sctx
->b
.delete_gs_state
= si_delete_shader_selector
;
3460 sctx
->b
.delete_fs_state
= si_delete_shader_selector
;