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radeonsi: rename flush flags, split the TC flag into L1 and L2
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "si_shader.h"
30 #include "sid.h"
31
32 #include "tgsi/tgsi_parse.h"
33 #include "util/u_memory.h"
34 #include "util/u_simple_shaders.h"
35
36 static void si_shader_es(struct si_shader *shader)
37 {
38 struct si_pm4_state *pm4;
39 unsigned num_sgprs, num_user_sgprs;
40 unsigned vgpr_comp_cnt;
41 uint64_t va;
42
43 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
44
45 if (pm4 == NULL)
46 return;
47
48 va = shader->bo->gpu_address;
49 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
50
51 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
52
53 num_user_sgprs = SI_VS_NUM_USER_SGPR;
54 num_sgprs = shader->num_sgprs;
55 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
56 if ((num_user_sgprs + 1) > num_sgprs) {
57 /* Last 2 reserved SGPRs are used for VCC */
58 num_sgprs = num_user_sgprs + 1 + 2;
59 }
60 assert(num_sgprs <= 104);
61
62 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
63 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
64 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
65 S_00B328_VGPRS((shader->num_vgprs - 1) / 4) |
66 S_00B328_SGPRS((num_sgprs - 1) / 8) |
67 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
68 S_00B328_DX10_CLAMP(1));
69 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
70 S_00B32C_USER_SGPR(num_user_sgprs));
71 }
72
73 static void si_shader_gs(struct si_shader *shader)
74 {
75 unsigned gs_vert_itemsize = shader->selector->info.num_outputs * (16 >> 2);
76 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
77 unsigned gsvs_itemsize = gs_vert_itemsize * gs_max_vert_out;
78 unsigned cut_mode;
79 struct si_pm4_state *pm4;
80 unsigned num_sgprs, num_user_sgprs;
81 uint64_t va;
82
83 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
84 assert(gsvs_itemsize < (1 << 15));
85
86 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
87
88 if (pm4 == NULL)
89 return;
90
91 if (gs_max_vert_out <= 128) {
92 cut_mode = V_028A40_GS_CUT_128;
93 } else if (gs_max_vert_out <= 256) {
94 cut_mode = V_028A40_GS_CUT_256;
95 } else if (gs_max_vert_out <= 512) {
96 cut_mode = V_028A40_GS_CUT_512;
97 } else {
98 assert(gs_max_vert_out <= 1024);
99 cut_mode = V_028A40_GS_CUT_1024;
100 }
101
102 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
103 S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
104 S_028A40_CUT_MODE(cut_mode)|
105 S_028A40_ES_WRITE_OPTIMIZE(1) |
106 S_028A40_GS_WRITE_OPTIMIZE(1));
107
108 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
109 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize);
110 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize);
111
112 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
113 util_bitcount64(shader->selector->gs_used_inputs) * (16 >> 2));
114 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize);
115
116 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, gs_max_vert_out);
117
118 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize);
119
120 va = shader->bo->gpu_address;
121 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
122 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
123 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
124
125 num_user_sgprs = SI_GS_NUM_USER_SGPR;
126 num_sgprs = shader->num_sgprs;
127 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
128 if ((num_user_sgprs + 2) > num_sgprs) {
129 /* Last 2 reserved SGPRs are used for VCC */
130 num_sgprs = num_user_sgprs + 2 + 2;
131 }
132 assert(num_sgprs <= 104);
133
134 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
135 S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
136 S_00B228_SGPRS((num_sgprs - 1) / 8) |
137 S_00B228_DX10_CLAMP(1));
138 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
139 S_00B22C_USER_SGPR(num_user_sgprs));
140 }
141
142 static void si_shader_vs(struct si_shader *shader)
143 {
144 struct tgsi_shader_info *info = &shader->selector->info;
145 struct si_pm4_state *pm4;
146 unsigned num_sgprs, num_user_sgprs;
147 unsigned nparams, i, vgpr_comp_cnt;
148 uint64_t va;
149 unsigned window_space =
150 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
151
152 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
153
154 if (pm4 == NULL)
155 return;
156
157 va = shader->bo->gpu_address;
158 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
159
160 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
161
162 if (shader->is_gs_copy_shader)
163 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
164 else
165 num_user_sgprs = SI_VS_NUM_USER_SGPR;
166
167 num_sgprs = shader->num_sgprs;
168 if (num_user_sgprs > num_sgprs) {
169 /* Last 2 reserved SGPRs are used for VCC */
170 num_sgprs = num_user_sgprs + 2;
171 }
172 assert(num_sgprs <= 104);
173
174 /* Certain attributes (position, psize, etc.) don't count as params.
175 * VS is required to export at least one param and r600_shader_from_tgsi()
176 * takes care of adding a dummy export.
177 */
178 for (nparams = 0, i = 0 ; i < info->num_outputs; i++) {
179 switch (info->output_semantic_name[i]) {
180 case TGSI_SEMANTIC_CLIPVERTEX:
181 case TGSI_SEMANTIC_POSITION:
182 case TGSI_SEMANTIC_PSIZE:
183 break;
184 default:
185 nparams++;
186 }
187 }
188 if (nparams < 1)
189 nparams = 1;
190
191 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
192 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
193
194 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
195 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
196 S_02870C_POS1_EXPORT_FORMAT(shader->nr_pos_exports > 1 ?
197 V_02870C_SPI_SHADER_4COMP :
198 V_02870C_SPI_SHADER_NONE) |
199 S_02870C_POS2_EXPORT_FORMAT(shader->nr_pos_exports > 2 ?
200 V_02870C_SPI_SHADER_4COMP :
201 V_02870C_SPI_SHADER_NONE) |
202 S_02870C_POS3_EXPORT_FORMAT(shader->nr_pos_exports > 3 ?
203 V_02870C_SPI_SHADER_4COMP :
204 V_02870C_SPI_SHADER_NONE));
205
206 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
207 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
208 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
209 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
210 S_00B128_SGPRS((num_sgprs - 1) / 8) |
211 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
212 S_00B128_DX10_CLAMP(1));
213 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
214 S_00B12C_USER_SGPR(num_user_sgprs) |
215 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
216 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
217 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
218 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
219 S_00B12C_SO_EN(!!shader->selector->so.num_outputs));
220 if (window_space)
221 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
222 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
223 else
224 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
225 S_028818_VTX_W0_FMT(1) |
226 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
227 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
228 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
229 }
230
231 static void si_shader_ps(struct si_shader *shader)
232 {
233 struct tgsi_shader_info *info = &shader->selector->info;
234 struct si_pm4_state *pm4;
235 unsigned i;
236 unsigned num_sgprs, num_user_sgprs;
237 unsigned spi_baryc_cntl = 0, spi_ps_input_ena;
238 uint64_t va;
239
240 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
241
242 if (pm4 == NULL)
243 return;
244
245 for (i = 0; i < info->num_inputs; i++) {
246 switch (info->input_semantic_name[i]) {
247 case TGSI_SEMANTIC_POSITION:
248 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
249 * Possible vaules:
250 * 0 -> Position = pixel center (default)
251 * 1 -> Position = pixel centroid
252 * 2 -> Position = at sample position
253 */
254 switch (info->input_interpolate_loc[i]) {
255 case TGSI_INTERPOLATE_LOC_CENTROID:
256 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
257 break;
258 case TGSI_INTERPOLATE_LOC_SAMPLE:
259 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
260 break;
261 }
262
263 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
264 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
265 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
266 break;
267 }
268 }
269
270 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
271 spi_ps_input_ena = shader->spi_ps_input_ena;
272 /* we need to enable at least one of them, otherwise we hang the GPU */
273 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
274 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
275 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
276 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
277 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
278 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
279 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
280 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
281
282 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
283 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
284
285 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
286 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
287 shader->spi_shader_col_format);
288 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
289
290 va = shader->bo->gpu_address;
291 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
292 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
293 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
294
295 num_user_sgprs = SI_PS_NUM_USER_SGPR;
296 num_sgprs = shader->num_sgprs;
297 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
298 if ((num_user_sgprs + 1) > num_sgprs) {
299 /* Last 2 reserved SGPRs are used for VCC */
300 num_sgprs = num_user_sgprs + 1 + 2;
301 }
302 assert(num_sgprs <= 104);
303
304 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
305 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
306 S_00B028_SGPRS((num_sgprs - 1) / 8) |
307 S_00B028_DX10_CLAMP(1));
308 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
309 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
310 S_00B02C_USER_SGPR(num_user_sgprs));
311 }
312
313 static void si_shader_init_pm4_state(struct si_shader *shader)
314 {
315 switch (shader->selector->type) {
316 case PIPE_SHADER_VERTEX:
317 if (shader->key.vs.as_es)
318 si_shader_es(shader);
319 else
320 si_shader_vs(shader);
321 break;
322 case PIPE_SHADER_GEOMETRY:
323 si_shader_gs(shader);
324 si_shader_vs(shader->gs_copy_shader);
325 break;
326 case PIPE_SHADER_FRAGMENT:
327 si_shader_ps(shader);
328 break;
329 default:
330 assert(0);
331 }
332 }
333
334 /* Compute the key for the hw shader variant */
335 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
336 struct si_shader_selector *sel,
337 union si_shader_key *key)
338 {
339 struct si_context *sctx = (struct si_context *)ctx;
340 memset(key, 0, sizeof(*key));
341
342 if (sel->type == PIPE_SHADER_VERTEX) {
343 unsigned i;
344 if (!sctx->vertex_elements)
345 return;
346
347 for (i = 0; i < sctx->vertex_elements->count; ++i)
348 key->vs.instance_divisors[i] = sctx->vertex_elements->elements[i].instance_divisor;
349
350 if (sctx->gs_shader) {
351 key->vs.as_es = 1;
352 key->vs.gs_used_inputs = sctx->gs_shader->gs_used_inputs;
353 }
354 } else if (sel->type == PIPE_SHADER_FRAGMENT) {
355 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
356 key->ps.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
357 key->ps.export_16bpc = sctx->framebuffer.export_16bpc;
358
359 if (sctx->queued.named.rasterizer) {
360 key->ps.color_two_side = sctx->queued.named.rasterizer->two_side;
361
362 if (sctx->queued.named.blend) {
363 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
364 sctx->queued.named.rasterizer->multisample_enable &&
365 !sctx->framebuffer.cb0_is_integer;
366 }
367 }
368 if (sctx->queued.named.dsa) {
369 key->ps.alpha_func = sctx->queued.named.dsa->alpha_func;
370
371 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
372 if (sctx->framebuffer.cb0_is_integer)
373 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
374 } else {
375 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
376 }
377 }
378 }
379
380 /* Select the hw shader variant depending on the current state. */
381 static int si_shader_select(struct pipe_context *ctx,
382 struct si_shader_selector *sel)
383 {
384 union si_shader_key key;
385 struct si_shader * shader = NULL;
386 int r;
387
388 si_shader_selector_key(ctx, sel, &key);
389
390 /* Check if we don't need to change anything.
391 * This path is also used for most shaders that don't need multiple
392 * variants, it will cost just a computation of the key and this
393 * test. */
394 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
395 return 0;
396 }
397
398 /* lookup if we have other variants in the list */
399 if (sel->num_shaders > 1) {
400 struct si_shader *p = sel->current, *c = p->next_variant;
401
402 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
403 p = c;
404 c = c->next_variant;
405 }
406
407 if (c) {
408 p->next_variant = c->next_variant;
409 shader = c;
410 }
411 }
412
413 if (shader) {
414 shader->next_variant = sel->current;
415 sel->current = shader;
416 } else {
417 shader = CALLOC(1, sizeof(struct si_shader));
418 shader->selector = sel;
419 shader->key = key;
420
421 shader->next_variant = sel->current;
422 sel->current = shader;
423 r = si_shader_create((struct si_screen*)ctx->screen, shader);
424 if (unlikely(r)) {
425 R600_ERR("Failed to build shader variant (type=%u) %d\n",
426 sel->type, r);
427 sel->current = NULL;
428 FREE(shader);
429 return r;
430 }
431 si_shader_init_pm4_state(shader);
432 sel->num_shaders++;
433 }
434
435 return 0;
436 }
437
438 static void *si_create_shader_state(struct pipe_context *ctx,
439 const struct pipe_shader_state *state,
440 unsigned pipe_shader_type)
441 {
442 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
443 int i;
444
445 sel->type = pipe_shader_type;
446 sel->tokens = tgsi_dup_tokens(state->tokens);
447 sel->so = state->stream_output;
448 tgsi_scan_shader(state->tokens, &sel->info);
449
450 switch (pipe_shader_type) {
451 case PIPE_SHADER_GEOMETRY:
452 sel->gs_output_prim =
453 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
454 sel->gs_max_out_vertices =
455 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
456
457 for (i = 0; i < sel->info.num_inputs; i++) {
458 unsigned name = sel->info.input_semantic_name[i];
459 unsigned index = sel->info.input_semantic_index[i];
460
461 switch (name) {
462 case TGSI_SEMANTIC_PRIMID:
463 break;
464 default:
465 sel->gs_used_inputs |=
466 1llu << si_shader_io_get_unique_index(name, index);
467 }
468 }
469 }
470
471 return sel;
472 }
473
474 static void *si_create_fs_state(struct pipe_context *ctx,
475 const struct pipe_shader_state *state)
476 {
477 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
478 }
479
480 static void *si_create_gs_state(struct pipe_context *ctx,
481 const struct pipe_shader_state *state)
482 {
483 return si_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
484 }
485
486 static void *si_create_vs_state(struct pipe_context *ctx,
487 const struct pipe_shader_state *state)
488 {
489 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
490 }
491
492 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
493 {
494 struct si_context *sctx = (struct si_context *)ctx;
495 struct si_shader_selector *sel = state;
496
497 if (sctx->vs_shader == sel || !sel)
498 return;
499
500 sctx->vs_shader = sel;
501 sctx->clip_regs.dirty = true;
502 }
503
504 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
505 {
506 struct si_context *sctx = (struct si_context *)ctx;
507 struct si_shader_selector *sel = state;
508
509 if (sctx->gs_shader == sel)
510 return;
511
512 sctx->gs_shader = sel;
513 sctx->clip_regs.dirty = true;
514 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
515 }
516
517 static void si_make_dummy_ps(struct si_context *sctx)
518 {
519 if (!sctx->dummy_pixel_shader) {
520 sctx->dummy_pixel_shader =
521 util_make_fragment_cloneinput_shader(&sctx->b.b, 0,
522 TGSI_SEMANTIC_GENERIC,
523 TGSI_INTERPOLATE_CONSTANT);
524 }
525 }
526
527 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
528 {
529 struct si_context *sctx = (struct si_context *)ctx;
530 struct si_shader_selector *sel = state;
531
532 /* skip if supplied shader is one already in use */
533 if (sctx->ps_shader == sel)
534 return;
535
536 /* use a dummy shader if binding a NULL shader */
537 if (!sel) {
538 si_make_dummy_ps(sctx);
539 sel = sctx->dummy_pixel_shader;
540 }
541
542 sctx->ps_shader = sel;
543 }
544
545 static void si_delete_shader_selector(struct pipe_context *ctx,
546 struct si_shader_selector *sel)
547 {
548 struct si_context *sctx = (struct si_context *)ctx;
549 struct si_shader *p = sel->current, *c;
550
551 while (p) {
552 c = p->next_variant;
553 if (sel->type == PIPE_SHADER_GEOMETRY) {
554 si_pm4_delete_state(sctx, gs, p->pm4);
555 si_pm4_delete_state(sctx, vs, p->gs_copy_shader->pm4);
556 } else if (sel->type == PIPE_SHADER_FRAGMENT)
557 si_pm4_delete_state(sctx, ps, p->pm4);
558 else if (p->key.vs.as_es)
559 si_pm4_delete_state(sctx, es, p->pm4);
560 else
561 si_pm4_delete_state(sctx, vs, p->pm4);
562 si_shader_destroy(ctx, p);
563 free(p);
564 p = c;
565 }
566
567 free(sel->tokens);
568 free(sel);
569 }
570
571 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
572 {
573 struct si_context *sctx = (struct si_context *)ctx;
574 struct si_shader_selector *sel = (struct si_shader_selector *)state;
575
576 if (sctx->vs_shader == sel) {
577 sctx->vs_shader = NULL;
578 }
579
580 si_delete_shader_selector(ctx, sel);
581 }
582
583 static void si_delete_gs_shader(struct pipe_context *ctx, void *state)
584 {
585 struct si_context *sctx = (struct si_context *)ctx;
586 struct si_shader_selector *sel = (struct si_shader_selector *)state;
587
588 if (sctx->gs_shader == sel) {
589 sctx->gs_shader = NULL;
590 }
591
592 si_delete_shader_selector(ctx, sel);
593 }
594
595 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
596 {
597 struct si_context *sctx = (struct si_context *)ctx;
598 struct si_shader_selector *sel = (struct si_shader_selector *)state;
599
600 if (sctx->ps_shader == sel) {
601 sctx->ps_shader = NULL;
602 }
603
604 si_delete_shader_selector(ctx, sel);
605 }
606
607 static void si_update_spi_map(struct si_context *sctx)
608 {
609 struct si_shader *ps = sctx->ps_shader->current;
610 struct si_shader *vs = si_get_vs_state(sctx);
611 struct tgsi_shader_info *psinfo = &ps->selector->info;
612 struct tgsi_shader_info *vsinfo = &vs->selector->info;
613 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
614 unsigned i, j, tmp;
615
616 for (i = 0; i < psinfo->num_inputs; i++) {
617 unsigned name = psinfo->input_semantic_name[i];
618 unsigned index = psinfo->input_semantic_index[i];
619 unsigned interpolate = psinfo->input_interpolate[i];
620 unsigned param_offset = ps->ps_input_param_offset[i];
621
622 if (name == TGSI_SEMANTIC_POSITION ||
623 name == TGSI_SEMANTIC_FACE)
624 /* Read from preloaded VGPRs, not parameters */
625 continue;
626
627 bcolor:
628 tmp = 0;
629
630 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
631 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
632 tmp |= S_028644_FLAT_SHADE(1);
633
634 if (name == TGSI_SEMANTIC_GENERIC &&
635 sctx->sprite_coord_enable & (1 << index)) {
636 tmp |= S_028644_PT_SPRITE_TEX(1);
637 }
638
639 for (j = 0; j < vsinfo->num_outputs; j++) {
640 if (name == vsinfo->output_semantic_name[j] &&
641 index == vsinfo->output_semantic_index[j]) {
642 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[j]);
643 break;
644 }
645 }
646
647 if (j == vsinfo->num_outputs) {
648 /* No corresponding output found, load defaults into input */
649 tmp |= S_028644_OFFSET(0x20);
650 }
651
652 si_pm4_set_reg(pm4,
653 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
654 tmp);
655
656 if (name == TGSI_SEMANTIC_COLOR &&
657 ps->key.ps.color_two_side) {
658 name = TGSI_SEMANTIC_BCOLOR;
659 param_offset++;
660 goto bcolor;
661 }
662 }
663
664 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL,
665 S_0286D8_NUM_INTERP(ps->nparam) |
666 S_0286D8_BC_OPTIMIZE_DISABLE(sctx->bc_optimize_disable));
667
668 si_pm4_set_state(sctx, spi, pm4);
669 }
670
671 /* Initialize state related to ESGS / GSVS ring buffers */
672 static void si_init_gs_rings(struct si_context *sctx)
673 {
674 unsigned esgs_ring_size = 128 * 1024;
675 unsigned gsvs_ring_size = 64 * 1024 * 1024;
676
677 assert(!sctx->gs_rings);
678 sctx->gs_rings = CALLOC_STRUCT(si_pm4_state);
679
680 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
681 PIPE_USAGE_DEFAULT, esgs_ring_size);
682
683 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
684 PIPE_USAGE_DEFAULT, gsvs_ring_size);
685
686 if (sctx->b.chip_class >= CIK) {
687 si_pm4_set_reg(sctx->gs_rings, R_030900_VGT_ESGS_RING_SIZE,
688 esgs_ring_size / 256);
689 si_pm4_set_reg(sctx->gs_rings, R_030904_VGT_GSVS_RING_SIZE,
690 gsvs_ring_size / 256);
691 } else {
692 si_pm4_set_reg(sctx->gs_rings, R_0088C8_VGT_ESGS_RING_SIZE,
693 esgs_ring_size / 256);
694 si_pm4_set_reg(sctx->gs_rings, R_0088CC_VGT_GSVS_RING_SIZE,
695 gsvs_ring_size / 256);
696 }
697
698 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
699 sctx->esgs_ring, 0, esgs_ring_size,
700 true, true, 4, 64);
701 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
702 sctx->esgs_ring, 0, esgs_ring_size,
703 false, false, 0, 0);
704 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
705 sctx->gsvs_ring, 0, gsvs_ring_size,
706 false, false, 0, 0);
707 }
708
709 void si_update_shaders(struct si_context *sctx)
710 {
711 struct pipe_context *ctx = (struct pipe_context*)sctx;
712 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
713 bool bc_optimize_disable;
714
715 if (sctx->gs_shader) {
716 si_shader_select(ctx, sctx->gs_shader);
717 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
718 si_pm4_bind_state(sctx, vs, sctx->gs_shader->current->gs_copy_shader->pm4);
719
720 sctx->b.streamout.stride_in_dw = sctx->gs_shader->so.stride;
721
722 si_shader_select(ctx, sctx->vs_shader);
723 si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
724
725 if (!sctx->gs_rings)
726 si_init_gs_rings(sctx);
727 if (sctx->emitted.named.gs_rings != sctx->gs_rings)
728 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
729 si_pm4_bind_state(sctx, gs_rings, sctx->gs_rings);
730
731 si_set_ring_buffer(ctx, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
732 sctx->gsvs_ring,
733 sctx->gs_shader->gs_max_out_vertices *
734 sctx->gs_shader->info.num_outputs * 16,
735 64, true, true, 4, 16);
736
737 if (!sctx->gs_on) {
738 sctx->gs_on = CALLOC_STRUCT(si_pm4_state);
739
740 si_pm4_set_reg(sctx->gs_on, R_028B54_VGT_SHADER_STAGES_EN,
741 S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
742 S_028B54_GS_EN(1) |
743 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER));
744 }
745 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_on);
746 } else {
747 si_shader_select(ctx, sctx->vs_shader);
748 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
749
750 sctx->b.streamout.stride_in_dw = sctx->vs_shader->so.stride;
751
752 if (!sctx->gs_off) {
753 sctx->gs_off = CALLOC_STRUCT(si_pm4_state);
754
755 si_pm4_set_reg(sctx->gs_off, R_028A40_VGT_GS_MODE, 0);
756 si_pm4_set_reg(sctx->gs_off, R_028B54_VGT_SHADER_STAGES_EN, 0);
757 }
758 si_pm4_bind_state(sctx, gs_onoff, sctx->gs_off);
759 si_pm4_bind_state(sctx, gs_rings, NULL);
760 si_pm4_bind_state(sctx, gs, NULL);
761 si_pm4_bind_state(sctx, es, NULL);
762 }
763
764 si_shader_select(ctx, sctx->ps_shader);
765
766 if (!sctx->ps_shader->current) {
767 struct si_shader_selector *sel;
768
769 /* use a dummy shader if compiling the shader (variant) failed */
770 si_make_dummy_ps(sctx);
771 sel = sctx->dummy_pixel_shader;
772 si_shader_select(ctx, sel);
773 sctx->ps_shader->current = sel->current;
774 }
775
776 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
777
778 /* Whether CENTER != CENTROID. */
779 bc_optimize_disable = sctx->framebuffer.nr_samples > 1 &&
780 rs->multisample_enable &&
781 sctx->ps_shader->info.uses_centroid;
782
783 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
784 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
785 sctx->flatshade != rs->flatshade ||
786 sctx->bc_optimize_disable != bc_optimize_disable) {
787 sctx->sprite_coord_enable = rs->sprite_coord_enable;
788 sctx->flatshade = rs->flatshade;
789 sctx->bc_optimize_disable = bc_optimize_disable;
790 si_update_spi_map(sctx);
791 }
792
793 if (sctx->ps_db_shader_control != sctx->ps_shader->current->db_shader_control) {
794 sctx->ps_db_shader_control = sctx->ps_shader->current->db_shader_control;
795 sctx->db_render_state.dirty = true;
796 }
797 }
798
799 void si_init_shader_functions(struct si_context *sctx)
800 {
801 sctx->b.b.create_vs_state = si_create_vs_state;
802 sctx->b.b.create_gs_state = si_create_gs_state;
803 sctx->b.b.create_fs_state = si_create_fs_state;
804
805 sctx->b.b.bind_vs_state = si_bind_vs_shader;
806 sctx->b.b.bind_gs_state = si_bind_gs_shader;
807 sctx->b.b.bind_fs_state = si_bind_ps_shader;
808
809 sctx->b.b.delete_vs_state = si_delete_vs_shader;
810 sctx->b.b.delete_gs_state = si_delete_gs_shader;
811 sctx->b.b.delete_fs_state = si_delete_ps_shader;
812 }