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radeonsi: mask out high VM address bits in registers where needed
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "sid.h"
26 #include "gfx9d.h"
27 #include "radeon/r600_cs.h"
28
29 #include "compiler/nir/nir_serialize.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "tgsi/tgsi_ureg.h"
32 #include "util/hash_table.h"
33 #include "util/crc32.h"
34 #include "util/u_async_debug.h"
35 #include "util/u_memory.h"
36 #include "util/u_prim.h"
37
38 #include "util/disk_cache.h"
39 #include "util/mesa-sha1.h"
40 #include "ac_exp_param.h"
41 #include "ac_shader_util.h"
42
43 /* SHADER_CACHE */
44
45 /**
46 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
47 * size as integer.
48 */
49 static void *si_get_ir_binary(struct si_shader_selector *sel)
50 {
51 struct blob blob;
52 unsigned ir_size;
53 void *ir_binary;
54
55 if (sel->tokens) {
56 ir_binary = sel->tokens;
57 ir_size = tgsi_num_tokens(sel->tokens) *
58 sizeof(struct tgsi_token);
59 } else {
60 assert(sel->nir);
61
62 blob_init(&blob);
63 nir_serialize(&blob, sel->nir);
64 ir_binary = blob.data;
65 ir_size = blob.size;
66 }
67
68 unsigned size = 4 + ir_size + sizeof(sel->so);
69 char *result = (char*)MALLOC(size);
70 if (!result)
71 return NULL;
72
73 *((uint32_t*)result) = size;
74 memcpy(result + 4, ir_binary, ir_size);
75 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
76
77 if (sel->nir)
78 blob_finish(&blob);
79
80 return result;
81 }
82
83 /** Copy "data" to "ptr" and return the next dword following copied data. */
84 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
85 {
86 /* data may be NULL if size == 0 */
87 if (size)
88 memcpy(ptr, data, size);
89 ptr += DIV_ROUND_UP(size, 4);
90 return ptr;
91 }
92
93 /** Read data from "ptr". Return the next dword following the data. */
94 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
95 {
96 memcpy(data, ptr, size);
97 ptr += DIV_ROUND_UP(size, 4);
98 return ptr;
99 }
100
101 /**
102 * Write the size as uint followed by the data. Return the next dword
103 * following the copied data.
104 */
105 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
106 {
107 *ptr++ = size;
108 return write_data(ptr, data, size);
109 }
110
111 /**
112 * Read the size as uint followed by the data. Return both via parameters.
113 * Return the next dword following the data.
114 */
115 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
116 {
117 *size = *ptr++;
118 assert(*data == NULL);
119 if (!*size)
120 return ptr;
121 *data = malloc(*size);
122 return read_data(ptr, *data, *size);
123 }
124
125 /**
126 * Return the shader binary in a buffer. The first 4 bytes contain its size
127 * as integer.
128 */
129 static void *si_get_shader_binary(struct si_shader *shader)
130 {
131 /* There is always a size of data followed by the data itself. */
132 unsigned relocs_size = shader->binary.reloc_count *
133 sizeof(shader->binary.relocs[0]);
134 unsigned disasm_size = shader->binary.disasm_string ?
135 strlen(shader->binary.disasm_string) + 1 : 0;
136 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
137 strlen(shader->binary.llvm_ir_string) + 1 : 0;
138 unsigned size =
139 4 + /* total size */
140 4 + /* CRC32 of the data below */
141 align(sizeof(shader->config), 4) +
142 align(sizeof(shader->info), 4) +
143 4 + align(shader->binary.code_size, 4) +
144 4 + align(shader->binary.rodata_size, 4) +
145 4 + align(relocs_size, 4) +
146 4 + align(disasm_size, 4) +
147 4 + align(llvm_ir_size, 4);
148 void *buffer = CALLOC(1, size);
149 uint32_t *ptr = (uint32_t*)buffer;
150
151 if (!buffer)
152 return NULL;
153
154 *ptr++ = size;
155 ptr++; /* CRC32 is calculated at the end. */
156
157 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
158 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
159 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
160 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
161 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
162 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
163 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
164 assert((char *)ptr - (char *)buffer == size);
165
166 /* Compute CRC32. */
167 ptr = (uint32_t*)buffer;
168 ptr++;
169 *ptr = util_hash_crc32(ptr + 1, size - 8);
170
171 return buffer;
172 }
173
174 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
175 {
176 uint32_t *ptr = (uint32_t*)binary;
177 uint32_t size = *ptr++;
178 uint32_t crc32 = *ptr++;
179 unsigned chunk_size;
180
181 if (util_hash_crc32(ptr, size - 8) != crc32) {
182 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
183 return false;
184 }
185
186 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
187 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
188 ptr = read_chunk(ptr, (void**)&shader->binary.code,
189 &shader->binary.code_size);
190 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
191 &shader->binary.rodata_size);
192 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
193 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
194 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
195 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
196
197 return true;
198 }
199
200 /**
201 * Insert a shader into the cache. It's assumed the shader is not in the cache.
202 * Use si_shader_cache_load_shader before calling this.
203 *
204 * Returns false on failure, in which case the ir_binary should be freed.
205 */
206 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
207 void *ir_binary,
208 struct si_shader *shader,
209 bool insert_into_disk_cache)
210 {
211 void *hw_binary;
212 struct hash_entry *entry;
213 uint8_t key[CACHE_KEY_SIZE];
214
215 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
216 if (entry)
217 return false; /* already added */
218
219 hw_binary = si_get_shader_binary(shader);
220 if (!hw_binary)
221 return false;
222
223 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
224 hw_binary) == NULL) {
225 FREE(hw_binary);
226 return false;
227 }
228
229 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
230 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
231 *((uint32_t *)ir_binary), key);
232 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
233 *((uint32_t *) hw_binary), NULL);
234 }
235
236 return true;
237 }
238
239 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
240 void *ir_binary,
241 struct si_shader *shader)
242 {
243 struct hash_entry *entry =
244 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
245 if (!entry) {
246 if (sscreen->disk_shader_cache) {
247 unsigned char sha1[CACHE_KEY_SIZE];
248 size_t tg_size = *((uint32_t *) ir_binary);
249
250 disk_cache_compute_key(sscreen->disk_shader_cache,
251 ir_binary, tg_size, sha1);
252
253 size_t binary_size;
254 uint8_t *buffer =
255 disk_cache_get(sscreen->disk_shader_cache,
256 sha1, &binary_size);
257 if (!buffer)
258 return false;
259
260 if (binary_size < sizeof(uint32_t) ||
261 *((uint32_t*)buffer) != binary_size) {
262 /* Something has gone wrong discard the item
263 * from the cache and rebuild/link from
264 * source.
265 */
266 assert(!"Invalid radeonsi shader disk cache "
267 "item!");
268
269 disk_cache_remove(sscreen->disk_shader_cache,
270 sha1);
271 free(buffer);
272
273 return false;
274 }
275
276 if (!si_load_shader_binary(shader, buffer)) {
277 free(buffer);
278 return false;
279 }
280 free(buffer);
281
282 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
283 shader, false))
284 FREE(ir_binary);
285 } else {
286 return false;
287 }
288 } else {
289 if (si_load_shader_binary(shader, entry->data))
290 FREE(ir_binary);
291 else
292 return false;
293 }
294 p_atomic_inc(&sscreen->num_shader_cache_hits);
295 return true;
296 }
297
298 static uint32_t si_shader_cache_key_hash(const void *key)
299 {
300 /* The first dword is the key size. */
301 return util_hash_crc32(key, *(uint32_t*)key);
302 }
303
304 static bool si_shader_cache_key_equals(const void *a, const void *b)
305 {
306 uint32_t *keya = (uint32_t*)a;
307 uint32_t *keyb = (uint32_t*)b;
308
309 /* The first dword is the key size. */
310 if (*keya != *keyb)
311 return false;
312
313 return memcmp(keya, keyb, *keya) == 0;
314 }
315
316 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
317 {
318 FREE((void*)entry->key);
319 FREE(entry->data);
320 }
321
322 bool si_init_shader_cache(struct si_screen *sscreen)
323 {
324 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
325 sscreen->shader_cache =
326 _mesa_hash_table_create(NULL,
327 si_shader_cache_key_hash,
328 si_shader_cache_key_equals);
329
330 return sscreen->shader_cache != NULL;
331 }
332
333 void si_destroy_shader_cache(struct si_screen *sscreen)
334 {
335 if (sscreen->shader_cache)
336 _mesa_hash_table_destroy(sscreen->shader_cache,
337 si_destroy_shader_cache_entry);
338 mtx_destroy(&sscreen->shader_cache_mutex);
339 }
340
341 /* SHADER STATES */
342
343 static void si_set_tesseval_regs(struct si_screen *sscreen,
344 struct si_shader_selector *tes,
345 struct si_pm4_state *pm4)
346 {
347 struct tgsi_shader_info *info = &tes->info;
348 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
349 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
350 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
351 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
352 unsigned type, partitioning, topology, distribution_mode;
353
354 switch (tes_prim_mode) {
355 case PIPE_PRIM_LINES:
356 type = V_028B6C_TESS_ISOLINE;
357 break;
358 case PIPE_PRIM_TRIANGLES:
359 type = V_028B6C_TESS_TRIANGLE;
360 break;
361 case PIPE_PRIM_QUADS:
362 type = V_028B6C_TESS_QUAD;
363 break;
364 default:
365 assert(0);
366 return;
367 }
368
369 switch (tes_spacing) {
370 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
371 partitioning = V_028B6C_PART_FRAC_ODD;
372 break;
373 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
374 partitioning = V_028B6C_PART_FRAC_EVEN;
375 break;
376 case PIPE_TESS_SPACING_EQUAL:
377 partitioning = V_028B6C_PART_INTEGER;
378 break;
379 default:
380 assert(0);
381 return;
382 }
383
384 if (tes_point_mode)
385 topology = V_028B6C_OUTPUT_POINT;
386 else if (tes_prim_mode == PIPE_PRIM_LINES)
387 topology = V_028B6C_OUTPUT_LINE;
388 else if (tes_vertex_order_cw)
389 /* for some reason, this must be the other way around */
390 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
391 else
392 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
393
394 if (sscreen->has_distributed_tess) {
395 if (sscreen->info.family == CHIP_FIJI ||
396 sscreen->info.family >= CHIP_POLARIS10)
397 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
398 else
399 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
400 } else
401 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
402
403 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
404 S_028B6C_TYPE(type) |
405 S_028B6C_PARTITIONING(partitioning) |
406 S_028B6C_TOPOLOGY(topology) |
407 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
408 }
409
410 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
411 * whether the "fractional odd" tessellation spacing is used.
412 *
413 * Possible VGT configurations and which state should set the register:
414 *
415 * Reg set in | VGT shader configuration | Value
416 * ------------------------------------------------------
417 * VS as VS | VS | 30
418 * VS as ES | ES -> GS -> VS | 30
419 * TES as VS | LS -> HS -> VS | 14 or 30
420 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
421 *
422 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
423 */
424 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
425 struct si_shader_selector *sel,
426 struct si_shader *shader,
427 struct si_pm4_state *pm4)
428 {
429 unsigned type = sel->type;
430
431 if (sscreen->info.family < CHIP_POLARIS10)
432 return;
433
434 /* VS as VS, or VS as ES: */
435 if ((type == PIPE_SHADER_VERTEX &&
436 (!shader ||
437 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
438 /* TES as VS, or TES as ES: */
439 type == PIPE_SHADER_TESS_EVAL) {
440 unsigned vtx_reuse_depth = 30;
441
442 if (type == PIPE_SHADER_TESS_EVAL &&
443 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
444 PIPE_TESS_SPACING_FRACTIONAL_ODD)
445 vtx_reuse_depth = 14;
446
447 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
448 vtx_reuse_depth);
449 }
450 }
451
452 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
453 {
454 if (shader->pm4)
455 si_pm4_clear_state(shader->pm4);
456 else
457 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
458
459 return shader->pm4;
460 }
461
462 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
463 {
464 /* Add the pointer to VBO descriptors. */
465 if (HAVE_32BIT_POINTERS) {
466 return num_always_on_user_sgprs + 1;
467 } else {
468 assert(num_always_on_user_sgprs % 2 == 0);
469 return num_always_on_user_sgprs + 2;
470 }
471 }
472
473 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
474 {
475 struct si_pm4_state *pm4;
476 unsigned vgpr_comp_cnt;
477 uint64_t va;
478
479 assert(sscreen->info.chip_class <= VI);
480
481 pm4 = si_get_shader_pm4_state(shader);
482 if (!pm4)
483 return;
484
485 va = shader->bo->gpu_address;
486 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
487
488 /* We need at least 2 components for LS.
489 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
490 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
491 */
492 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
493
494 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
495 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
496
497 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
498 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
499 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
500 S_00B528_DX10_CLAMP(1) |
501 S_00B528_FLOAT_MODE(shader->config.float_mode);
502 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
503 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
504 }
505
506 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
507 {
508 struct si_pm4_state *pm4;
509 uint64_t va;
510 unsigned ls_vgpr_comp_cnt = 0;
511
512 pm4 = si_get_shader_pm4_state(shader);
513 if (!pm4)
514 return;
515
516 va = shader->bo->gpu_address;
517 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
518
519 if (sscreen->info.chip_class >= GFX9) {
520 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
521 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
522
523 /* We need at least 2 components for LS.
524 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
525 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
526 */
527 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
528
529 unsigned num_user_sgprs =
530 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
531
532 shader->config.rsrc2 =
533 S_00B42C_USER_SGPR(num_user_sgprs) |
534 S_00B42C_USER_SGPR_MSB(num_user_sgprs >> 5) |
535 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
536 } else {
537 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
538 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
539
540 shader->config.rsrc2 =
541 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
542 S_00B42C_OC_LDS_EN(1) |
543 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
544 }
545
546 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
547 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
548 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
549 S_00B428_DX10_CLAMP(1) |
550 S_00B428_FLOAT_MODE(shader->config.float_mode) |
551 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
552
553 if (sscreen->info.chip_class <= VI) {
554 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
555 shader->config.rsrc2);
556 }
557 }
558
559 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
560 {
561 struct si_pm4_state *pm4;
562 unsigned num_user_sgprs;
563 unsigned vgpr_comp_cnt;
564 uint64_t va;
565 unsigned oc_lds_en;
566
567 assert(sscreen->info.chip_class <= VI);
568
569 pm4 = si_get_shader_pm4_state(shader);
570 if (!pm4)
571 return;
572
573 va = shader->bo->gpu_address;
574 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
575
576 if (shader->selector->type == PIPE_SHADER_VERTEX) {
577 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
578 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
579 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
580 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
581 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
582 num_user_sgprs = SI_TES_NUM_USER_SGPR;
583 } else
584 unreachable("invalid shader selector type");
585
586 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
587
588 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
589 shader->selector->esgs_itemsize / 4);
590 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
591 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
592 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
593 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
594 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
595 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
596 S_00B328_DX10_CLAMP(1) |
597 S_00B328_FLOAT_MODE(shader->config.float_mode));
598 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
599 S_00B32C_USER_SGPR(num_user_sgprs) |
600 S_00B32C_OC_LDS_EN(oc_lds_en) |
601 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
602
603 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
604 si_set_tesseval_regs(sscreen, shader->selector, pm4);
605
606 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
607 }
608
609 struct gfx9_gs_info {
610 unsigned es_verts_per_subgroup;
611 unsigned gs_prims_per_subgroup;
612 unsigned gs_inst_prims_in_subgroup;
613 unsigned max_prims_per_subgroup;
614 unsigned lds_size;
615 };
616
617 static void gfx9_get_gs_info(struct si_shader_selector *es,
618 struct si_shader_selector *gs,
619 struct gfx9_gs_info *out)
620 {
621 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
622 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
623 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
624 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
625
626 /* All these are in dwords: */
627 /* We can't allow using the whole LDS, because GS waves compete with
628 * other shader stages for LDS space. */
629 const unsigned max_lds_size = 8 * 1024;
630 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
631 unsigned esgs_lds_size;
632
633 /* All these are per subgroup: */
634 const unsigned max_out_prims = 32 * 1024;
635 const unsigned max_es_verts = 255;
636 const unsigned ideal_gs_prims = 64;
637 unsigned max_gs_prims, gs_prims;
638 unsigned min_es_verts, es_verts, worst_case_es_verts;
639
640 assert(gs_num_invocations <= 32); /* GL maximum */
641
642 if (uses_adjacency || gs_num_invocations > 1)
643 max_gs_prims = 127 / gs_num_invocations;
644 else
645 max_gs_prims = 255;
646
647 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
648 * Make sure we don't go over the maximum value.
649 */
650 if (gs->gs_max_out_vertices > 0) {
651 max_gs_prims = MIN2(max_gs_prims,
652 max_out_prims /
653 (gs->gs_max_out_vertices * gs_num_invocations));
654 }
655 assert(max_gs_prims > 0);
656
657 /* If the primitive has adjacency, halve the number of vertices
658 * that will be reused in multiple primitives.
659 */
660 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
661
662 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
663 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
664
665 /* Compute ESGS LDS size based on the worst case number of ES vertices
666 * needed to create the target number of GS prims per subgroup.
667 */
668 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
669
670 /* If total LDS usage is too big, refactor partitions based on ratio
671 * of ESGS item sizes.
672 */
673 if (esgs_lds_size > max_lds_size) {
674 /* Our target GS Prims Per Subgroup was too large. Calculate
675 * the maximum number of GS Prims Per Subgroup that will fit
676 * into LDS, capped by the maximum that the hardware can support.
677 */
678 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
679 max_gs_prims);
680 assert(gs_prims > 0);
681 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
682 max_es_verts);
683
684 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
685 assert(esgs_lds_size <= max_lds_size);
686 }
687
688 /* Now calculate remaining ESGS information. */
689 if (esgs_lds_size)
690 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
691 else
692 es_verts = max_es_verts;
693
694 /* Vertices for adjacency primitives are not always reused, so restore
695 * it for ES_VERTS_PER_SUBGRP.
696 */
697 min_es_verts = gs->gs_input_verts_per_prim;
698
699 /* For normal primitives, the VGT only checks if they are past the ES
700 * verts per subgroup after allocating a full GS primitive and if they
701 * are, kick off a new subgroup. But if those additional ES verts are
702 * unique (e.g. not reused) we need to make sure there is enough LDS
703 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
704 */
705 es_verts -= min_es_verts - 1;
706
707 out->es_verts_per_subgroup = es_verts;
708 out->gs_prims_per_subgroup = gs_prims;
709 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
710 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
711 gs->gs_max_out_vertices;
712 out->lds_size = align(esgs_lds_size, 128) / 128;
713
714 assert(out->max_prims_per_subgroup <= max_out_prims);
715 }
716
717 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
718 {
719 struct si_shader_selector *sel = shader->selector;
720 const ubyte *num_components = sel->info.num_stream_output_components;
721 unsigned gs_num_invocations = sel->gs_num_invocations;
722 struct si_pm4_state *pm4;
723 uint64_t va;
724 unsigned max_stream = sel->max_gs_stream;
725 unsigned offset;
726
727 pm4 = si_get_shader_pm4_state(shader);
728 if (!pm4)
729 return;
730
731 offset = num_components[0] * sel->gs_max_out_vertices;
732 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, offset);
733 if (max_stream >= 1)
734 offset += num_components[1] * sel->gs_max_out_vertices;
735 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, offset);
736 if (max_stream >= 2)
737 offset += num_components[2] * sel->gs_max_out_vertices;
738 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, offset);
739 if (max_stream >= 3)
740 offset += num_components[3] * sel->gs_max_out_vertices;
741 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
742
743 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
744 assert(offset < (1 << 15));
745
746 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, sel->gs_max_out_vertices);
747
748 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, num_components[0]);
749 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? num_components[1] : 0);
750 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? num_components[2] : 0);
751 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? num_components[3] : 0);
752
753 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
754 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
755 S_028B90_ENABLE(gs_num_invocations > 0));
756
757 va = shader->bo->gpu_address;
758 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
759
760 if (sscreen->info.chip_class >= GFX9) {
761 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
762 unsigned es_type = shader->key.part.gs.es->type;
763 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
764 struct gfx9_gs_info gs_info;
765
766 if (es_type == PIPE_SHADER_VERTEX)
767 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
768 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
769 else if (es_type == PIPE_SHADER_TESS_EVAL)
770 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
771 else
772 unreachable("invalid shader selector type");
773
774 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
775 * VGPR[0:4] are always loaded.
776 */
777 if (sel->info.uses_invocationid)
778 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
779 else if (sel->info.uses_primid)
780 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
781 else if (input_prim >= PIPE_PRIM_TRIANGLES)
782 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
783 else
784 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
785
786 unsigned num_user_sgprs;
787 if (es_type == PIPE_SHADER_VERTEX)
788 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
789 else
790 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
791
792 gfx9_get_gs_info(shader->key.part.gs.es, sel, &gs_info);
793
794 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
795 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
796
797 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
798 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
799 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
800 S_00B228_DX10_CLAMP(1) |
801 S_00B228_FLOAT_MODE(shader->config.float_mode) |
802 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
803 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
804 S_00B22C_USER_SGPR(num_user_sgprs) |
805 S_00B22C_USER_SGPR_MSB(num_user_sgprs >> 5) |
806 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
807 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
808 S_00B22C_LDS_SIZE(gs_info.lds_size) |
809 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
810
811 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
812 S_028A44_ES_VERTS_PER_SUBGRP(gs_info.es_verts_per_subgroup) |
813 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info.gs_prims_per_subgroup) |
814 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info.gs_inst_prims_in_subgroup));
815 si_pm4_set_reg(pm4, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
816 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info.max_prims_per_subgroup));
817 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
818 shader->key.part.gs.es->esgs_itemsize / 4);
819
820 if (es_type == PIPE_SHADER_TESS_EVAL)
821 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
822
823 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
824 NULL, pm4);
825 } else {
826 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
827 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
828
829 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
830 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
831 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
832 S_00B228_DX10_CLAMP(1) |
833 S_00B228_FLOAT_MODE(shader->config.float_mode));
834 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
835 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
836 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
837 }
838 }
839
840 /**
841 * Compute the state for \p shader, which will run as a vertex shader on the
842 * hardware.
843 *
844 * If \p gs is non-NULL, it points to the geometry shader for which this shader
845 * is the copy shader.
846 */
847 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
848 struct si_shader_selector *gs)
849 {
850 const struct tgsi_shader_info *info = &shader->selector->info;
851 struct si_pm4_state *pm4;
852 unsigned num_user_sgprs;
853 unsigned nparams, vgpr_comp_cnt;
854 uint64_t va;
855 unsigned oc_lds_en;
856 unsigned window_space =
857 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
858 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
859
860 pm4 = si_get_shader_pm4_state(shader);
861 if (!pm4)
862 return;
863
864 /* We always write VGT_GS_MODE in the VS state, because every switch
865 * between different shader pipelines involving a different GS or no
866 * GS at all involves a switch of the VS (different GS use different
867 * copy shaders). On the other hand, when the API switches from a GS to
868 * no GS and then back to the same GS used originally, the GS state is
869 * not sent again.
870 */
871 if (!gs) {
872 unsigned mode = V_028A40_GS_OFF;
873
874 /* PrimID needs GS scenario A. */
875 if (enable_prim_id)
876 mode = V_028A40_GS_SCENARIO_A;
877
878 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, S_028A40_MODE(mode));
879 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
880 } else {
881 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
882 ac_vgt_gs_mode(gs->gs_max_out_vertices,
883 sscreen->info.chip_class));
884 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
885 }
886
887 if (sscreen->info.chip_class <= VI) {
888 /* Reuse needs to be set off if we write oViewport. */
889 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF,
890 S_028AB4_REUSE_OFF(info->writes_viewport_index));
891 }
892
893 va = shader->bo->gpu_address;
894 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
895
896 if (gs) {
897 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
898 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
899 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
900 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
901 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
902 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
903 */
904 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
905
906 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
907 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
908 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
909 } else {
910 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
911 }
912 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
913 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
914 num_user_sgprs = SI_TES_NUM_USER_SGPR;
915 } else
916 unreachable("invalid shader selector type");
917
918 /* VS is required to export at least one param. */
919 nparams = MAX2(shader->info.nr_param_exports, 1);
920 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
921 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
922
923 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
924 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
925 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
926 V_02870C_SPI_SHADER_4COMP :
927 V_02870C_SPI_SHADER_NONE) |
928 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
929 V_02870C_SPI_SHADER_4COMP :
930 V_02870C_SPI_SHADER_NONE) |
931 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
932 V_02870C_SPI_SHADER_4COMP :
933 V_02870C_SPI_SHADER_NONE));
934
935 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
936
937 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
938 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
939 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
940 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
941 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
942 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
943 S_00B128_DX10_CLAMP(1) |
944 S_00B128_FLOAT_MODE(shader->config.float_mode));
945 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
946 S_00B12C_USER_SGPR(num_user_sgprs) |
947 S_00B12C_OC_LDS_EN(oc_lds_en) |
948 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
949 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
950 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
951 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
952 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
953 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
954 if (window_space)
955 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
956 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
957 else
958 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
959 S_028818_VTX_W0_FMT(1) |
960 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
961 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
962 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
963
964 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
965 si_set_tesseval_regs(sscreen, shader->selector, pm4);
966
967 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
968 }
969
970 static unsigned si_get_ps_num_interp(struct si_shader *ps)
971 {
972 struct tgsi_shader_info *info = &ps->selector->info;
973 unsigned num_colors = !!(info->colors_read & 0x0f) +
974 !!(info->colors_read & 0xf0);
975 unsigned num_interp = ps->selector->info.num_inputs +
976 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
977
978 assert(num_interp <= 32);
979 return MIN2(num_interp, 32);
980 }
981
982 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
983 {
984 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
985 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
986
987 /* If the i-th target format is set, all previous target formats must
988 * be non-zero to avoid hangs.
989 */
990 for (i = 0; i < num_targets; i++)
991 if (!(value & (0xf << (i * 4))))
992 value |= V_028714_SPI_SHADER_32_R << (i * 4);
993
994 return value;
995 }
996
997 static void si_shader_ps(struct si_shader *shader)
998 {
999 struct tgsi_shader_info *info = &shader->selector->info;
1000 struct si_pm4_state *pm4;
1001 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1002 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1003 uint64_t va;
1004 unsigned input_ena = shader->config.spi_ps_input_ena;
1005
1006 /* we need to enable at least one of them, otherwise we hang the GPU */
1007 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1008 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1009 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1010 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1011 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1012 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1013 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1014 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1015 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1016 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1017 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1018 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1019 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1020 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1021
1022 /* Validate interpolation optimization flags (read as implications). */
1023 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1024 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1025 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1026 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1027 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1028 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1029 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1030 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1031 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1032 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1033 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1034 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1035 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1036 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1037 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1038 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1039 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1040 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1041
1042 /* Validate cases when the optimizations are off (read as implications). */
1043 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1044 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1045 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1046 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1047 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1048 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1049
1050 pm4 = si_get_shader_pm4_state(shader);
1051 if (!pm4)
1052 return;
1053
1054 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1055 * Possible vaules:
1056 * 0 -> Position = pixel center
1057 * 1 -> Position = pixel centroid
1058 * 2 -> Position = at sample position
1059 *
1060 * From GLSL 4.5 specification, section 7.1:
1061 * "The variable gl_FragCoord is available as an input variable from
1062 * within fragment shaders and it holds the window relative coordinates
1063 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1064 * value can be for any location within the pixel, or one of the
1065 * fragment samples. The use of centroid does not further restrict
1066 * this value to be inside the current primitive."
1067 *
1068 * Meaning that centroid has no effect and we can return anything within
1069 * the pixel. Thus, return the value at sample position, because that's
1070 * the most accurate one shaders can get.
1071 */
1072 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1073
1074 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1075 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1076 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1077
1078 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1079 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1080
1081 /* Ensure that some export memory is always allocated, for two reasons:
1082 *
1083 * 1) Correctness: The hardware ignores the EXEC mask if no export
1084 * memory is allocated, so KILL and alpha test do not work correctly
1085 * without this.
1086 * 2) Performance: Every shader needs at least a NULL export, even when
1087 * it writes no color/depth output. The NULL export instruction
1088 * stalls without this setting.
1089 *
1090 * Don't add this to CB_SHADER_MASK.
1091 */
1092 if (!spi_shader_col_format &&
1093 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1094 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1095
1096 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
1097 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
1098 shader->config.spi_ps_input_addr);
1099
1100 /* Set interpolation controls. */
1101 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1102
1103 /* Set registers. */
1104 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1105 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
1106
1107 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
1108 ac_get_spi_shader_z_format(info->writes_z,
1109 info->writes_stencil,
1110 info->writes_samplemask));
1111
1112 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
1113 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
1114
1115 va = shader->bo->gpu_address;
1116 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1117 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1118 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1119
1120 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
1121 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1122 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
1123 S_00B028_DX10_CLAMP(1) |
1124 S_00B028_FLOAT_MODE(shader->config.float_mode));
1125 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1126 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1127 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1128 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1129 }
1130
1131 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1132 struct si_shader *shader)
1133 {
1134 switch (shader->selector->type) {
1135 case PIPE_SHADER_VERTEX:
1136 if (shader->key.as_ls)
1137 si_shader_ls(sscreen, shader);
1138 else if (shader->key.as_es)
1139 si_shader_es(sscreen, shader);
1140 else
1141 si_shader_vs(sscreen, shader, NULL);
1142 break;
1143 case PIPE_SHADER_TESS_CTRL:
1144 si_shader_hs(sscreen, shader);
1145 break;
1146 case PIPE_SHADER_TESS_EVAL:
1147 if (shader->key.as_es)
1148 si_shader_es(sscreen, shader);
1149 else
1150 si_shader_vs(sscreen, shader, NULL);
1151 break;
1152 case PIPE_SHADER_GEOMETRY:
1153 si_shader_gs(sscreen, shader);
1154 break;
1155 case PIPE_SHADER_FRAGMENT:
1156 si_shader_ps(shader);
1157 break;
1158 default:
1159 assert(0);
1160 }
1161 }
1162
1163 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1164 {
1165 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1166 if (sctx->queued.named.dsa)
1167 return sctx->queued.named.dsa->alpha_func;
1168
1169 return PIPE_FUNC_ALWAYS;
1170 }
1171
1172 static void si_shader_selector_key_vs(struct si_context *sctx,
1173 struct si_shader_selector *vs,
1174 struct si_shader_key *key,
1175 struct si_vs_prolog_bits *prolog_key)
1176 {
1177 if (!sctx->vertex_elements)
1178 return;
1179
1180 prolog_key->instance_divisor_is_one =
1181 sctx->vertex_elements->instance_divisor_is_one;
1182 prolog_key->instance_divisor_is_fetched =
1183 sctx->vertex_elements->instance_divisor_is_fetched;
1184
1185 /* Prefer a monolithic shader to allow scheduling divisions around
1186 * VBO loads. */
1187 if (prolog_key->instance_divisor_is_fetched)
1188 key->opt.prefer_mono = 1;
1189
1190 unsigned count = MIN2(vs->info.num_inputs,
1191 sctx->vertex_elements->count);
1192 memcpy(key->mono.vs_fix_fetch, sctx->vertex_elements->fix_fetch, count);
1193 }
1194
1195 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1196 struct si_shader_selector *vs,
1197 struct si_shader_key *key)
1198 {
1199 struct si_shader_selector *ps = sctx->ps_shader.cso;
1200
1201 key->opt.clip_disable =
1202 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1203 (vs->info.clipdist_writemask ||
1204 vs->info.writes_clipvertex) &&
1205 !vs->info.culldist_writemask;
1206
1207 /* Find out if PS is disabled. */
1208 bool ps_disabled = true;
1209 if (ps) {
1210 const struct si_state_blend *blend = sctx->queued.named.blend;
1211 bool alpha_to_coverage = blend && blend->alpha_to_coverage;
1212 bool ps_modifies_zs = ps->info.uses_kill ||
1213 ps->info.writes_z ||
1214 ps->info.writes_stencil ||
1215 ps->info.writes_samplemask ||
1216 alpha_to_coverage ||
1217 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1218
1219 unsigned ps_colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1220 sctx->queued.named.blend->cb_target_mask;
1221 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1222 ps_colormask &= ps->colors_written_4bit;
1223
1224 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1225 (!ps_colormask &&
1226 !ps_modifies_zs &&
1227 !ps->info.writes_memory);
1228 }
1229
1230 /* Find out which VS outputs aren't used by the PS. */
1231 uint64_t outputs_written = vs->outputs_written;
1232 uint64_t inputs_read = 0;
1233
1234 /* ignore POSITION, PSIZE */
1235 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0) |
1236 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0))));
1237
1238 if (!ps_disabled) {
1239 inputs_read = ps->inputs_read;
1240 }
1241
1242 uint64_t linked = outputs_written & inputs_read;
1243
1244 key->opt.kill_outputs = ~linked & outputs_written;
1245 }
1246
1247 /* Compute the key for the hw shader variant */
1248 static inline void si_shader_selector_key(struct pipe_context *ctx,
1249 struct si_shader_selector *sel,
1250 struct si_shader_key *key)
1251 {
1252 struct si_context *sctx = (struct si_context *)ctx;
1253
1254 memset(key, 0, sizeof(*key));
1255
1256 switch (sel->type) {
1257 case PIPE_SHADER_VERTEX:
1258 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1259
1260 if (sctx->tes_shader.cso)
1261 key->as_ls = 1;
1262 else if (sctx->gs_shader.cso)
1263 key->as_es = 1;
1264 else {
1265 si_shader_selector_key_hw_vs(sctx, sel, key);
1266
1267 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1268 key->mono.u.vs_export_prim_id = 1;
1269 }
1270 break;
1271 case PIPE_SHADER_TESS_CTRL:
1272 if (sctx->b.chip_class >= GFX9) {
1273 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1274 key, &key->part.tcs.ls_prolog);
1275 key->part.tcs.ls = sctx->vs_shader.cso;
1276
1277 /* When the LS VGPR fix is needed, monolithic shaders
1278 * can:
1279 * - avoid initializing EXEC in both the LS prolog
1280 * and the LS main part when !vs_needs_prolog
1281 * - remove the fixup for unused input VGPRs
1282 */
1283 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1284
1285 /* The LS output / HS input layout can be communicated
1286 * directly instead of via user SGPRs for merged LS-HS.
1287 * The LS VGPR fix prefers this too.
1288 */
1289 key->opt.prefer_mono = 1;
1290 }
1291
1292 key->part.tcs.epilog.prim_mode =
1293 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1294 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1295 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1296 key->part.tcs.epilog.tes_reads_tess_factors =
1297 sctx->tes_shader.cso->info.reads_tess_factors;
1298
1299 if (sel == sctx->fixed_func_tcs_shader.cso)
1300 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1301 break;
1302 case PIPE_SHADER_TESS_EVAL:
1303 if (sctx->gs_shader.cso)
1304 key->as_es = 1;
1305 else {
1306 si_shader_selector_key_hw_vs(sctx, sel, key);
1307
1308 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1309 key->mono.u.vs_export_prim_id = 1;
1310 }
1311 break;
1312 case PIPE_SHADER_GEOMETRY:
1313 if (sctx->b.chip_class >= GFX9) {
1314 if (sctx->tes_shader.cso) {
1315 key->part.gs.es = sctx->tes_shader.cso;
1316 } else {
1317 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1318 key, &key->part.gs.vs_prolog);
1319 key->part.gs.es = sctx->vs_shader.cso;
1320 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1321 }
1322
1323 /* Merged ES-GS can have unbalanced wave usage.
1324 *
1325 * ES threads are per-vertex, while GS threads are
1326 * per-primitive. So without any amplification, there
1327 * are fewer GS threads than ES threads, which can result
1328 * in empty (no-op) GS waves. With too much amplification,
1329 * there are more GS threads than ES threads, which
1330 * can result in empty (no-op) ES waves.
1331 *
1332 * Non-monolithic shaders are implemented by setting EXEC
1333 * at the beginning of shader parts, and don't jump to
1334 * the end if EXEC is 0.
1335 *
1336 * Monolithic shaders use conditional blocks, so they can
1337 * jump and skip empty waves of ES or GS. So set this to
1338 * always use optimized variants, which are monolithic.
1339 */
1340 key->opt.prefer_mono = 1;
1341 }
1342 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1343 break;
1344 case PIPE_SHADER_FRAGMENT: {
1345 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1346 struct si_state_blend *blend = sctx->queued.named.blend;
1347
1348 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1349 sel->info.colors_written == 0x1)
1350 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1351
1352 if (blend) {
1353 /* Select the shader color format based on whether
1354 * blending or alpha are needed.
1355 */
1356 key->part.ps.epilog.spi_shader_col_format =
1357 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1358 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1359 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1360 sctx->framebuffer.spi_shader_col_format_blend) |
1361 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1362 sctx->framebuffer.spi_shader_col_format_alpha) |
1363 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1364 sctx->framebuffer.spi_shader_col_format);
1365 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1366
1367 /* The output for dual source blending should have
1368 * the same format as the first output.
1369 */
1370 if (blend->dual_src_blend)
1371 key->part.ps.epilog.spi_shader_col_format |=
1372 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1373 } else
1374 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1375
1376 /* If alpha-to-coverage is enabled, we have to export alpha
1377 * even if there is no color buffer.
1378 */
1379 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1380 blend && blend->alpha_to_coverage)
1381 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1382
1383 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1384 * to the range supported by the type if a channel has less
1385 * than 16 bits and the export format is 16_ABGR.
1386 */
1387 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII) {
1388 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1389 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1390 }
1391
1392 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1393 if (!key->part.ps.epilog.last_cbuf) {
1394 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1395 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1396 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1397 }
1398
1399 if (rs) {
1400 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
1401 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
1402 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
1403 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
1404
1405 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1406 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1407
1408 if (sctx->queued.named.blend) {
1409 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1410 rs->multisample_enable;
1411 }
1412
1413 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1414 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1415 (is_line && rs->line_smooth)) &&
1416 sctx->framebuffer.nr_samples <= 1;
1417 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1418
1419 if (sctx->ps_iter_samples > 1 &&
1420 sel->info.reads_samplemask) {
1421 key->part.ps.prolog.samplemask_log_ps_iter =
1422 util_logbase2(util_next_power_of_two(sctx->ps_iter_samples));
1423 }
1424
1425 if (rs->force_persample_interp &&
1426 rs->multisample_enable &&
1427 sctx->framebuffer.nr_samples > 1 &&
1428 sctx->ps_iter_samples > 1) {
1429 key->part.ps.prolog.force_persp_sample_interp =
1430 sel->info.uses_persp_center ||
1431 sel->info.uses_persp_centroid;
1432
1433 key->part.ps.prolog.force_linear_sample_interp =
1434 sel->info.uses_linear_center ||
1435 sel->info.uses_linear_centroid;
1436 } else if (rs->multisample_enable &&
1437 sctx->framebuffer.nr_samples > 1) {
1438 key->part.ps.prolog.bc_optimize_for_persp =
1439 sel->info.uses_persp_center &&
1440 sel->info.uses_persp_centroid;
1441 key->part.ps.prolog.bc_optimize_for_linear =
1442 sel->info.uses_linear_center &&
1443 sel->info.uses_linear_centroid;
1444 } else {
1445 /* Make sure SPI doesn't compute more than 1 pair
1446 * of (i,j), which is the optimization here. */
1447 key->part.ps.prolog.force_persp_center_interp =
1448 sel->info.uses_persp_center +
1449 sel->info.uses_persp_centroid +
1450 sel->info.uses_persp_sample > 1;
1451
1452 key->part.ps.prolog.force_linear_center_interp =
1453 sel->info.uses_linear_center +
1454 sel->info.uses_linear_centroid +
1455 sel->info.uses_linear_sample > 1;
1456
1457 if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
1458 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1459 }
1460 }
1461
1462 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1463 break;
1464 }
1465 default:
1466 assert(0);
1467 }
1468
1469 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
1470 memset(&key->opt, 0, sizeof(key->opt));
1471 }
1472
1473 static void si_build_shader_variant(struct si_shader *shader,
1474 int thread_index,
1475 bool low_priority)
1476 {
1477 struct si_shader_selector *sel = shader->selector;
1478 struct si_screen *sscreen = sel->screen;
1479 LLVMTargetMachineRef tm;
1480 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1481 int r;
1482
1483 if (thread_index >= 0) {
1484 if (low_priority) {
1485 assert(thread_index < ARRAY_SIZE(sscreen->tm_low_priority));
1486 tm = sscreen->tm_low_priority[thread_index];
1487 } else {
1488 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1489 tm = sscreen->tm[thread_index];
1490 }
1491 if (!debug->async)
1492 debug = NULL;
1493 } else {
1494 assert(!low_priority);
1495 tm = shader->compiler_ctx_state.tm;
1496 }
1497
1498 r = si_shader_create(sscreen, tm, shader, debug);
1499 if (unlikely(r)) {
1500 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1501 sel->type, r);
1502 shader->compilation_failed = true;
1503 return;
1504 }
1505
1506 if (shader->compiler_ctx_state.is_debug_context) {
1507 FILE *f = open_memstream(&shader->shader_log,
1508 &shader->shader_log_size);
1509 if (f) {
1510 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1511 fclose(f);
1512 }
1513 }
1514
1515 si_shader_init_pm4_state(sscreen, shader);
1516 }
1517
1518 static void si_build_shader_variant_low_priority(void *job, int thread_index)
1519 {
1520 struct si_shader *shader = (struct si_shader *)job;
1521
1522 assert(thread_index >= 0);
1523
1524 si_build_shader_variant(shader, thread_index, true);
1525 }
1526
1527 static const struct si_shader_key zeroed;
1528
1529 static bool si_check_missing_main_part(struct si_screen *sscreen,
1530 struct si_shader_selector *sel,
1531 struct si_compiler_ctx_state *compiler_state,
1532 struct si_shader_key *key)
1533 {
1534 struct si_shader **mainp = si_get_main_shader_part(sel, key);
1535
1536 if (!*mainp) {
1537 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1538
1539 if (!main_part)
1540 return false;
1541
1542 /* We can leave the fence as permanently signaled because the
1543 * main part becomes visible globally only after it has been
1544 * compiled. */
1545 util_queue_fence_init(&main_part->ready);
1546
1547 main_part->selector = sel;
1548 main_part->key.as_es = key->as_es;
1549 main_part->key.as_ls = key->as_ls;
1550
1551 if (si_compile_tgsi_shader(sscreen, compiler_state->tm,
1552 main_part, false,
1553 &compiler_state->debug) != 0) {
1554 FREE(main_part);
1555 return false;
1556 }
1557 *mainp = main_part;
1558 }
1559 return true;
1560 }
1561
1562 /* Select the hw shader variant depending on the current state. */
1563 static int si_shader_select_with_key(struct si_screen *sscreen,
1564 struct si_shader_ctx_state *state,
1565 struct si_compiler_ctx_state *compiler_state,
1566 struct si_shader_key *key,
1567 int thread_index)
1568 {
1569 struct si_shader_selector *sel = state->cso;
1570 struct si_shader_selector *previous_stage_sel = NULL;
1571 struct si_shader *current = state->current;
1572 struct si_shader *iter, *shader = NULL;
1573
1574 again:
1575 /* Check if we don't need to change anything.
1576 * This path is also used for most shaders that don't need multiple
1577 * variants, it will cost just a computation of the key and this
1578 * test. */
1579 if (likely(current &&
1580 memcmp(&current->key, key, sizeof(*key)) == 0)) {
1581 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
1582 if (current->is_optimized) {
1583 memset(&key->opt, 0, sizeof(key->opt));
1584 goto current_not_ready;
1585 }
1586
1587 util_queue_fence_wait(&current->ready);
1588 }
1589
1590 return current->compilation_failed ? -1 : 0;
1591 }
1592 current_not_ready:
1593
1594 /* This must be done before the mutex is locked, because async GS
1595 * compilation calls this function too, and therefore must enter
1596 * the mutex first.
1597 *
1598 * Only wait if we are in a draw call. Don't wait if we are
1599 * in a compiler thread.
1600 */
1601 if (thread_index < 0)
1602 util_queue_fence_wait(&sel->ready);
1603
1604 mtx_lock(&sel->mutex);
1605
1606 /* Find the shader variant. */
1607 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1608 /* Don't check the "current" shader. We checked it above. */
1609 if (current != iter &&
1610 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1611 mtx_unlock(&sel->mutex);
1612
1613 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
1614 /* If it's an optimized shader and its compilation has
1615 * been started but isn't done, use the unoptimized
1616 * shader so as not to cause a stall due to compilation.
1617 */
1618 if (iter->is_optimized) {
1619 memset(&key->opt, 0, sizeof(key->opt));
1620 goto again;
1621 }
1622
1623 util_queue_fence_wait(&iter->ready);
1624 }
1625
1626 if (iter->compilation_failed) {
1627 return -1; /* skip the draw call */
1628 }
1629
1630 state->current = iter;
1631 return 0;
1632 }
1633 }
1634
1635 /* Build a new shader. */
1636 shader = CALLOC_STRUCT(si_shader);
1637 if (!shader) {
1638 mtx_unlock(&sel->mutex);
1639 return -ENOMEM;
1640 }
1641
1642 util_queue_fence_init(&shader->ready);
1643
1644 shader->selector = sel;
1645 shader->key = *key;
1646 shader->compiler_ctx_state = *compiler_state;
1647
1648 /* If this is a merged shader, get the first shader's selector. */
1649 if (sscreen->info.chip_class >= GFX9) {
1650 if (sel->type == PIPE_SHADER_TESS_CTRL)
1651 previous_stage_sel = key->part.tcs.ls;
1652 else if (sel->type == PIPE_SHADER_GEOMETRY)
1653 previous_stage_sel = key->part.gs.es;
1654
1655 /* We need to wait for the previous shader. */
1656 if (previous_stage_sel && thread_index < 0)
1657 util_queue_fence_wait(&previous_stage_sel->ready);
1658 }
1659
1660 /* Compile the main shader part if it doesn't exist. This can happen
1661 * if the initial guess was wrong. */
1662 bool is_pure_monolithic =
1663 sscreen->use_monolithic_shaders ||
1664 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1665
1666 if (!is_pure_monolithic) {
1667 bool ok;
1668
1669 /* Make sure the main shader part is present. This is needed
1670 * for shaders that can be compiled as VS, LS, or ES, and only
1671 * one of them is compiled at creation.
1672 *
1673 * For merged shaders, check that the starting shader's main
1674 * part is present.
1675 */
1676 if (previous_stage_sel) {
1677 struct si_shader_key shader1_key = zeroed;
1678
1679 if (sel->type == PIPE_SHADER_TESS_CTRL)
1680 shader1_key.as_ls = 1;
1681 else if (sel->type == PIPE_SHADER_GEOMETRY)
1682 shader1_key.as_es = 1;
1683 else
1684 assert(0);
1685
1686 mtx_lock(&previous_stage_sel->mutex);
1687 ok = si_check_missing_main_part(sscreen,
1688 previous_stage_sel,
1689 compiler_state, &shader1_key);
1690 mtx_unlock(&previous_stage_sel->mutex);
1691 } else {
1692 ok = si_check_missing_main_part(sscreen, sel,
1693 compiler_state, key);
1694 }
1695 if (!ok) {
1696 FREE(shader);
1697 mtx_unlock(&sel->mutex);
1698 return -ENOMEM; /* skip the draw call */
1699 }
1700 }
1701
1702 /* Keep the reference to the 1st shader of merged shaders, so that
1703 * Gallium can't destroy it before we destroy the 2nd shader.
1704 *
1705 * Set sctx = NULL, because it's unused if we're not releasing
1706 * the shader, and we don't have any sctx here.
1707 */
1708 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
1709 previous_stage_sel);
1710
1711 /* Monolithic-only shaders don't make a distinction between optimized
1712 * and unoptimized. */
1713 shader->is_monolithic =
1714 is_pure_monolithic ||
1715 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1716
1717 shader->is_optimized =
1718 !is_pure_monolithic &&
1719 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1720
1721 /* If it's an optimized shader, compile it asynchronously. */
1722 if (shader->is_optimized &&
1723 !is_pure_monolithic &&
1724 thread_index < 0) {
1725 /* Compile it asynchronously. */
1726 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
1727 shader, &shader->ready,
1728 si_build_shader_variant_low_priority, NULL);
1729
1730 /* Add only after the ready fence was reset, to guard against a
1731 * race with si_bind_XX_shader. */
1732 if (!sel->last_variant) {
1733 sel->first_variant = shader;
1734 sel->last_variant = shader;
1735 } else {
1736 sel->last_variant->next_variant = shader;
1737 sel->last_variant = shader;
1738 }
1739
1740 /* Use the default (unoptimized) shader for now. */
1741 memset(&key->opt, 0, sizeof(key->opt));
1742 mtx_unlock(&sel->mutex);
1743 goto again;
1744 }
1745
1746 /* Reset the fence before adding to the variant list. */
1747 util_queue_fence_reset(&shader->ready);
1748
1749 if (!sel->last_variant) {
1750 sel->first_variant = shader;
1751 sel->last_variant = shader;
1752 } else {
1753 sel->last_variant->next_variant = shader;
1754 sel->last_variant = shader;
1755 }
1756
1757 mtx_unlock(&sel->mutex);
1758
1759 assert(!shader->is_optimized);
1760 si_build_shader_variant(shader, thread_index, false);
1761
1762 util_queue_fence_signal(&shader->ready);
1763
1764 if (!shader->compilation_failed)
1765 state->current = shader;
1766
1767 return shader->compilation_failed ? -1 : 0;
1768 }
1769
1770 static int si_shader_select(struct pipe_context *ctx,
1771 struct si_shader_ctx_state *state,
1772 struct si_compiler_ctx_state *compiler_state)
1773 {
1774 struct si_context *sctx = (struct si_context *)ctx;
1775 struct si_shader_key key;
1776
1777 si_shader_selector_key(ctx, state->cso, &key);
1778 return si_shader_select_with_key(sctx->screen, state, compiler_state,
1779 &key, -1);
1780 }
1781
1782 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1783 bool streamout,
1784 struct si_shader_key *key)
1785 {
1786 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1787
1788 switch (info->processor) {
1789 case PIPE_SHADER_VERTEX:
1790 switch (next_shader) {
1791 case PIPE_SHADER_GEOMETRY:
1792 key->as_es = 1;
1793 break;
1794 case PIPE_SHADER_TESS_CTRL:
1795 case PIPE_SHADER_TESS_EVAL:
1796 key->as_ls = 1;
1797 break;
1798 default:
1799 /* If POSITION isn't written, it can only be a HW VS
1800 * if streamout is used. If streamout isn't used,
1801 * assume that it's a HW LS. (the next shader is TCS)
1802 * This heuristic is needed for separate shader objects.
1803 */
1804 if (!info->writes_position && !streamout)
1805 key->as_ls = 1;
1806 }
1807 break;
1808
1809 case PIPE_SHADER_TESS_EVAL:
1810 if (next_shader == PIPE_SHADER_GEOMETRY ||
1811 !info->writes_position)
1812 key->as_es = 1;
1813 break;
1814 }
1815 }
1816
1817 /**
1818 * Compile the main shader part or the monolithic shader as part of
1819 * si_shader_selector initialization. Since it can be done asynchronously,
1820 * there is no way to report compile failures to applications.
1821 */
1822 static void si_init_shader_selector_async(void *job, int thread_index)
1823 {
1824 struct si_shader_selector *sel = (struct si_shader_selector *)job;
1825 struct si_screen *sscreen = sel->screen;
1826 LLVMTargetMachineRef tm;
1827 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
1828
1829 assert(!debug->debug_message || debug->async);
1830 assert(thread_index >= 0);
1831 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1832 tm = sscreen->tm[thread_index];
1833
1834 /* Compile the main shader part for use with a prolog and/or epilog.
1835 * If this fails, the driver will try to compile a monolithic shader
1836 * on demand.
1837 */
1838 if (!sscreen->use_monolithic_shaders) {
1839 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1840 void *ir_binary = NULL;
1841
1842 if (!shader) {
1843 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
1844 return;
1845 }
1846
1847 /* We can leave the fence signaled because use of the default
1848 * main part is guarded by the selector's ready fence. */
1849 util_queue_fence_init(&shader->ready);
1850
1851 shader->selector = sel;
1852 si_parse_next_shader_property(&sel->info,
1853 sel->so.num_outputs != 0,
1854 &shader->key);
1855
1856 if (sel->tokens || sel->nir)
1857 ir_binary = si_get_ir_binary(sel);
1858
1859 /* Try to load the shader from the shader cache. */
1860 mtx_lock(&sscreen->shader_cache_mutex);
1861
1862 if (ir_binary &&
1863 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
1864 mtx_unlock(&sscreen->shader_cache_mutex);
1865 si_shader_dump_stats_for_shader_db(shader, debug);
1866 } else {
1867 mtx_unlock(&sscreen->shader_cache_mutex);
1868
1869 /* Compile the shader if it hasn't been loaded from the cache. */
1870 if (si_compile_tgsi_shader(sscreen, tm, shader, false,
1871 debug) != 0) {
1872 FREE(shader);
1873 FREE(ir_binary);
1874 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
1875 return;
1876 }
1877
1878 if (ir_binary) {
1879 mtx_lock(&sscreen->shader_cache_mutex);
1880 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
1881 FREE(ir_binary);
1882 mtx_unlock(&sscreen->shader_cache_mutex);
1883 }
1884 }
1885
1886 *si_get_main_shader_part(sel, &shader->key) = shader;
1887
1888 /* Unset "outputs_written" flags for outputs converted to
1889 * DEFAULT_VAL, so that later inter-shader optimizations don't
1890 * try to eliminate outputs that don't exist in the final
1891 * shader.
1892 *
1893 * This is only done if non-monolithic shaders are enabled.
1894 */
1895 if ((sel->type == PIPE_SHADER_VERTEX ||
1896 sel->type == PIPE_SHADER_TESS_EVAL) &&
1897 !shader->key.as_ls &&
1898 !shader->key.as_es) {
1899 unsigned i;
1900
1901 for (i = 0; i < sel->info.num_outputs; i++) {
1902 unsigned offset = shader->info.vs_output_param_offset[i];
1903
1904 if (offset <= AC_EXP_PARAM_OFFSET_31)
1905 continue;
1906
1907 unsigned name = sel->info.output_semantic_name[i];
1908 unsigned index = sel->info.output_semantic_index[i];
1909 unsigned id;
1910
1911 switch (name) {
1912 case TGSI_SEMANTIC_GENERIC:
1913 /* don't process indices the function can't handle */
1914 if (index >= SI_MAX_IO_GENERIC)
1915 break;
1916 /* fall through */
1917 default:
1918 id = si_shader_io_get_unique_index(name, index);
1919 sel->outputs_written &= ~(1ull << id);
1920 break;
1921 case TGSI_SEMANTIC_POSITION: /* ignore these */
1922 case TGSI_SEMANTIC_PSIZE:
1923 case TGSI_SEMANTIC_CLIPVERTEX:
1924 case TGSI_SEMANTIC_EDGEFLAG:
1925 break;
1926 }
1927 }
1928 }
1929 }
1930
1931 /* The GS copy shader is always pre-compiled. */
1932 if (sel->type == PIPE_SHADER_GEOMETRY) {
1933 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, tm, sel, debug);
1934 if (!sel->gs_copy_shader) {
1935 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
1936 return;
1937 }
1938
1939 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
1940 }
1941 }
1942
1943 /* Return descriptor slot usage masks from the given shader info. */
1944 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
1945 uint32_t *const_and_shader_buffers,
1946 uint64_t *samplers_and_images)
1947 {
1948 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
1949
1950 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
1951 num_constbufs = util_last_bit(info->const_buffers_declared);
1952 /* two 8-byte images share one 16-byte slot */
1953 num_images = align(util_last_bit(info->images_declared), 2);
1954 num_samplers = util_last_bit(info->samplers_declared);
1955
1956 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
1957 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
1958 *const_and_shader_buffers =
1959 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
1960
1961 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
1962 start = si_get_image_slot(num_images - 1) / 2;
1963 *samplers_and_images =
1964 u_bit_consecutive64(start, num_images / 2 + num_samplers);
1965 }
1966
1967 static void *si_create_shader_selector(struct pipe_context *ctx,
1968 const struct pipe_shader_state *state)
1969 {
1970 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
1971 struct si_context *sctx = (struct si_context*)ctx;
1972 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
1973 int i;
1974
1975 if (!sel)
1976 return NULL;
1977
1978 pipe_reference_init(&sel->reference, 1);
1979 sel->screen = sscreen;
1980 sel->compiler_ctx_state.debug = sctx->debug;
1981 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
1982
1983 sel->so = state->stream_output;
1984
1985 if (state->type == PIPE_SHADER_IR_TGSI) {
1986 sel->tokens = tgsi_dup_tokens(state->tokens);
1987 if (!sel->tokens) {
1988 FREE(sel);
1989 return NULL;
1990 }
1991
1992 tgsi_scan_shader(state->tokens, &sel->info);
1993 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
1994 } else {
1995 assert(state->type == PIPE_SHADER_IR_NIR);
1996
1997 sel->nir = state->ir.nir;
1998
1999 si_nir_scan_shader(sel->nir, &sel->info);
2000 si_nir_scan_tess_ctrl(sel->nir, &sel->info, &sel->tcs_info);
2001
2002 si_lower_nir(sel, sctx->b.chip_class);
2003 }
2004
2005 sel->type = sel->info.processor;
2006 p_atomic_inc(&sscreen->num_shaders_created);
2007 si_get_active_slot_masks(&sel->info,
2008 &sel->active_const_and_shader_buffers,
2009 &sel->active_samplers_and_images);
2010
2011 /* Record which streamout buffers are enabled. */
2012 for (i = 0; i < sel->so.num_outputs; i++) {
2013 sel->enabled_streamout_buffer_mask |=
2014 (1 << sel->so.output[i].output_buffer) <<
2015 (sel->so.output[i].stream * 4);
2016 }
2017
2018 /* The prolog is a no-op if there are no inputs. */
2019 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2020 sel->info.num_inputs &&
2021 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2022
2023 sel->force_correct_derivs_after_kill =
2024 sel->type == PIPE_SHADER_FRAGMENT &&
2025 sel->info.uses_derivatives &&
2026 sel->info.uses_kill &&
2027 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2028
2029 /* Set which opcode uses which (i,j) pair. */
2030 if (sel->info.uses_persp_opcode_interp_centroid)
2031 sel->info.uses_persp_centroid = true;
2032
2033 if (sel->info.uses_linear_opcode_interp_centroid)
2034 sel->info.uses_linear_centroid = true;
2035
2036 if (sel->info.uses_persp_opcode_interp_offset ||
2037 sel->info.uses_persp_opcode_interp_sample)
2038 sel->info.uses_persp_center = true;
2039
2040 if (sel->info.uses_linear_opcode_interp_offset ||
2041 sel->info.uses_linear_opcode_interp_sample)
2042 sel->info.uses_linear_center = true;
2043
2044 switch (sel->type) {
2045 case PIPE_SHADER_GEOMETRY:
2046 sel->gs_output_prim =
2047 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2048 sel->gs_max_out_vertices =
2049 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2050 sel->gs_num_invocations =
2051 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2052 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2053 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2054 sel->gs_max_out_vertices;
2055
2056 sel->max_gs_stream = 0;
2057 for (i = 0; i < sel->so.num_outputs; i++)
2058 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2059 sel->so.output[i].stream);
2060
2061 sel->gs_input_verts_per_prim =
2062 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2063 break;
2064
2065 case PIPE_SHADER_TESS_CTRL:
2066 /* Always reserve space for these. */
2067 sel->patch_outputs_written |=
2068 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2069 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2070 /* fall through */
2071 case PIPE_SHADER_VERTEX:
2072 case PIPE_SHADER_TESS_EVAL:
2073 for (i = 0; i < sel->info.num_outputs; i++) {
2074 unsigned name = sel->info.output_semantic_name[i];
2075 unsigned index = sel->info.output_semantic_index[i];
2076
2077 switch (name) {
2078 case TGSI_SEMANTIC_TESSINNER:
2079 case TGSI_SEMANTIC_TESSOUTER:
2080 case TGSI_SEMANTIC_PATCH:
2081 sel->patch_outputs_written |=
2082 1ull << si_shader_io_get_unique_index_patch(name, index);
2083 break;
2084
2085 case TGSI_SEMANTIC_GENERIC:
2086 /* don't process indices the function can't handle */
2087 if (index >= SI_MAX_IO_GENERIC)
2088 break;
2089 /* fall through */
2090 default:
2091 sel->outputs_written |=
2092 1ull << si_shader_io_get_unique_index(name, index);
2093 break;
2094 case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */
2095 case TGSI_SEMANTIC_EDGEFLAG:
2096 break;
2097 }
2098 }
2099 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2100
2101 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2102 * conflicts, i.e. each vertex will start at a different bank.
2103 */
2104 if (sctx->b.chip_class >= GFX9)
2105 sel->esgs_itemsize += 4;
2106 break;
2107
2108 case PIPE_SHADER_FRAGMENT:
2109 for (i = 0; i < sel->info.num_inputs; i++) {
2110 unsigned name = sel->info.input_semantic_name[i];
2111 unsigned index = sel->info.input_semantic_index[i];
2112
2113 switch (name) {
2114 case TGSI_SEMANTIC_GENERIC:
2115 /* don't process indices the function can't handle */
2116 if (index >= SI_MAX_IO_GENERIC)
2117 break;
2118 /* fall through */
2119 default:
2120 sel->inputs_read |=
2121 1ull << si_shader_io_get_unique_index(name, index);
2122 break;
2123 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2124 break;
2125 }
2126 }
2127
2128 for (i = 0; i < 8; i++)
2129 if (sel->info.colors_written & (1 << i))
2130 sel->colors_written_4bit |= 0xf << (4 * i);
2131
2132 for (i = 0; i < sel->info.num_inputs; i++) {
2133 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2134 int index = sel->info.input_semantic_index[i];
2135 sel->color_attr_index[index] = i;
2136 }
2137 }
2138 break;
2139 }
2140
2141 /* PA_CL_VS_OUT_CNTL */
2142 bool misc_vec_ena =
2143 sel->info.writes_psize || sel->info.writes_edgeflag ||
2144 sel->info.writes_layer || sel->info.writes_viewport_index;
2145 sel->pa_cl_vs_out_cntl =
2146 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2147 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2148 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2149 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2150 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2151 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2152 sel->clipdist_mask = sel->info.writes_clipvertex ?
2153 SIX_BITS : sel->info.clipdist_writemask;
2154 sel->culldist_mask = sel->info.culldist_writemask <<
2155 sel->info.num_written_clipdistance;
2156
2157 /* DB_SHADER_CONTROL */
2158 sel->db_shader_control =
2159 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2160 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2161 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2162 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2163
2164 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2165 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2166 sel->db_shader_control |=
2167 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2168 break;
2169 case TGSI_FS_DEPTH_LAYOUT_LESS:
2170 sel->db_shader_control |=
2171 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2172 break;
2173 }
2174
2175 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2176 *
2177 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2178 * --|-----------|------------|------------|--------------------|-------------------|-------------
2179 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2180 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2181 * 2 | false | true | n/a | LateZ | 1 | 0
2182 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2183 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2184 *
2185 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2186 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2187 *
2188 * Don't use ReZ without profiling !!!
2189 *
2190 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2191 * shaders.
2192 */
2193 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2194 /* Cases 3, 4. */
2195 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2196 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2197 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2198 } else if (sel->info.writes_memory) {
2199 /* Case 2. */
2200 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2201 S_02880C_EXEC_ON_HIER_FAIL(1);
2202 } else {
2203 /* Case 1. */
2204 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2205 }
2206
2207 (void) mtx_init(&sel->mutex, mtx_plain);
2208 util_queue_fence_init(&sel->ready);
2209
2210 struct util_async_debug_callback async_debug;
2211 bool wait =
2212 (sctx->debug.debug_message && !sctx->debug.async) ||
2213 sctx->is_debug ||
2214 si_can_dump_shader(sscreen, sel->info.processor);
2215
2216 if (wait) {
2217 u_async_debug_init(&async_debug);
2218 sel->compiler_ctx_state.debug = async_debug.base;
2219 }
2220
2221 util_queue_add_job(&sscreen->shader_compiler_queue, sel,
2222 &sel->ready, si_init_shader_selector_async,
2223 NULL);
2224
2225 if (wait) {
2226 util_queue_fence_wait(&sel->ready);
2227 u_async_debug_drain(&async_debug, &sctx->debug);
2228 u_async_debug_cleanup(&async_debug);
2229 }
2230
2231 return sel;
2232 }
2233
2234 static void si_update_streamout_state(struct si_context *sctx)
2235 {
2236 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2237
2238 if (!shader_with_so)
2239 return;
2240
2241 sctx->streamout.enabled_stream_buffers_mask =
2242 shader_with_so->enabled_streamout_buffer_mask;
2243 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2244 }
2245
2246 static void si_update_clip_regs(struct si_context *sctx,
2247 struct si_shader_selector *old_hw_vs,
2248 struct si_shader *old_hw_vs_variant,
2249 struct si_shader_selector *next_hw_vs,
2250 struct si_shader *next_hw_vs_variant)
2251 {
2252 if (next_hw_vs &&
2253 (!old_hw_vs ||
2254 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2255 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2256 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2257 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2258 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2259 !old_hw_vs_variant ||
2260 !next_hw_vs_variant ||
2261 old_hw_vs_variant->key.opt.clip_disable !=
2262 next_hw_vs_variant->key.opt.clip_disable))
2263 si_mark_atom_dirty(sctx, &sctx->clip_regs);
2264 }
2265
2266 static void si_update_common_shader_state(struct si_context *sctx)
2267 {
2268 sctx->uses_bindless_samplers =
2269 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2270 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2271 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2272 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2273 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2274 sctx->uses_bindless_images =
2275 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2276 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2277 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2278 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2279 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2280 sctx->do_update_shaders = true;
2281 }
2282
2283 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2284 {
2285 struct si_context *sctx = (struct si_context *)ctx;
2286 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2287 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2288 struct si_shader_selector *sel = state;
2289
2290 if (sctx->vs_shader.cso == sel)
2291 return;
2292
2293 sctx->vs_shader.cso = sel;
2294 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2295 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2296
2297 si_update_common_shader_state(sctx);
2298 si_update_vs_viewport_state(sctx);
2299 si_set_active_descriptors_for_shader(sctx, sel);
2300 si_update_streamout_state(sctx);
2301 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2302 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2303 }
2304
2305 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2306 {
2307 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2308 (sctx->tes_shader.cso &&
2309 sctx->tes_shader.cso->info.uses_primid) ||
2310 (sctx->tcs_shader.cso &&
2311 sctx->tcs_shader.cso->info.uses_primid) ||
2312 (sctx->gs_shader.cso &&
2313 sctx->gs_shader.cso->info.uses_primid) ||
2314 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2315 sctx->ps_shader.cso->info.uses_primid);
2316 }
2317
2318 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2319 {
2320 struct si_context *sctx = (struct si_context *)ctx;
2321 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2322 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2323 struct si_shader_selector *sel = state;
2324 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2325
2326 if (sctx->gs_shader.cso == sel)
2327 return;
2328
2329 sctx->gs_shader.cso = sel;
2330 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2331 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2332
2333 si_update_common_shader_state(sctx);
2334 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2335
2336 if (enable_changed) {
2337 si_shader_change_notify(sctx);
2338 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2339 si_update_tess_uses_prim_id(sctx);
2340 }
2341 si_update_vs_viewport_state(sctx);
2342 si_set_active_descriptors_for_shader(sctx, sel);
2343 si_update_streamout_state(sctx);
2344 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2345 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2346 }
2347
2348 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2349 {
2350 struct si_context *sctx = (struct si_context *)ctx;
2351 struct si_shader_selector *sel = state;
2352 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2353
2354 if (sctx->tcs_shader.cso == sel)
2355 return;
2356
2357 sctx->tcs_shader.cso = sel;
2358 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
2359 si_update_tess_uses_prim_id(sctx);
2360
2361 si_update_common_shader_state(sctx);
2362
2363 if (enable_changed)
2364 sctx->last_tcs = NULL; /* invalidate derived tess state */
2365
2366 si_set_active_descriptors_for_shader(sctx, sel);
2367 }
2368
2369 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
2370 {
2371 struct si_context *sctx = (struct si_context *)ctx;
2372 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2373 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2374 struct si_shader_selector *sel = state;
2375 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
2376
2377 if (sctx->tes_shader.cso == sel)
2378 return;
2379
2380 sctx->tes_shader.cso = sel;
2381 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
2382 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
2383 si_update_tess_uses_prim_id(sctx);
2384
2385 si_update_common_shader_state(sctx);
2386 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2387
2388 if (enable_changed) {
2389 si_shader_change_notify(sctx);
2390 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
2391 }
2392 si_update_vs_viewport_state(sctx);
2393 si_set_active_descriptors_for_shader(sctx, sel);
2394 si_update_streamout_state(sctx);
2395 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2396 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2397 }
2398
2399 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2400 {
2401 struct si_context *sctx = (struct si_context *)ctx;
2402 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
2403 struct si_shader_selector *sel = state;
2404
2405 /* skip if supplied shader is one already in use */
2406 if (old_sel == sel)
2407 return;
2408
2409 sctx->ps_shader.cso = sel;
2410 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
2411
2412 si_update_common_shader_state(sctx);
2413 if (sel) {
2414 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2415 si_update_tess_uses_prim_id(sctx);
2416
2417 if (!old_sel ||
2418 old_sel->info.colors_written != sel->info.colors_written)
2419 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2420
2421 if (sctx->screen->has_out_of_order_rast &&
2422 (!old_sel ||
2423 old_sel->info.writes_memory != sel->info.writes_memory ||
2424 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
2425 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
2426 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2427 }
2428 si_set_active_descriptors_for_shader(sctx, sel);
2429 }
2430
2431 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
2432 {
2433 if (shader->is_optimized) {
2434 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
2435 &shader->ready);
2436 }
2437
2438 util_queue_fence_destroy(&shader->ready);
2439
2440 if (shader->pm4) {
2441 switch (shader->selector->type) {
2442 case PIPE_SHADER_VERTEX:
2443 if (shader->key.as_ls) {
2444 assert(sctx->b.chip_class <= VI);
2445 si_pm4_delete_state(sctx, ls, shader->pm4);
2446 } else if (shader->key.as_es) {
2447 assert(sctx->b.chip_class <= VI);
2448 si_pm4_delete_state(sctx, es, shader->pm4);
2449 } else {
2450 si_pm4_delete_state(sctx, vs, shader->pm4);
2451 }
2452 break;
2453 case PIPE_SHADER_TESS_CTRL:
2454 si_pm4_delete_state(sctx, hs, shader->pm4);
2455 break;
2456 case PIPE_SHADER_TESS_EVAL:
2457 if (shader->key.as_es) {
2458 assert(sctx->b.chip_class <= VI);
2459 si_pm4_delete_state(sctx, es, shader->pm4);
2460 } else {
2461 si_pm4_delete_state(sctx, vs, shader->pm4);
2462 }
2463 break;
2464 case PIPE_SHADER_GEOMETRY:
2465 if (shader->is_gs_copy_shader)
2466 si_pm4_delete_state(sctx, vs, shader->pm4);
2467 else
2468 si_pm4_delete_state(sctx, gs, shader->pm4);
2469 break;
2470 case PIPE_SHADER_FRAGMENT:
2471 si_pm4_delete_state(sctx, ps, shader->pm4);
2472 break;
2473 }
2474 }
2475
2476 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
2477 si_shader_destroy(shader);
2478 free(shader);
2479 }
2480
2481 void si_destroy_shader_selector(struct si_context *sctx,
2482 struct si_shader_selector *sel)
2483 {
2484 struct si_shader *p = sel->first_variant, *c;
2485 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
2486 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
2487 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
2488 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
2489 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
2490 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
2491 };
2492
2493 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
2494
2495 if (current_shader[sel->type]->cso == sel) {
2496 current_shader[sel->type]->cso = NULL;
2497 current_shader[sel->type]->current = NULL;
2498 }
2499
2500 while (p) {
2501 c = p->next_variant;
2502 si_delete_shader(sctx, p);
2503 p = c;
2504 }
2505
2506 if (sel->main_shader_part)
2507 si_delete_shader(sctx, sel->main_shader_part);
2508 if (sel->main_shader_part_ls)
2509 si_delete_shader(sctx, sel->main_shader_part_ls);
2510 if (sel->main_shader_part_es)
2511 si_delete_shader(sctx, sel->main_shader_part_es);
2512 if (sel->gs_copy_shader)
2513 si_delete_shader(sctx, sel->gs_copy_shader);
2514
2515 util_queue_fence_destroy(&sel->ready);
2516 mtx_destroy(&sel->mutex);
2517 free(sel->tokens);
2518 ralloc_free(sel->nir);
2519 free(sel);
2520 }
2521
2522 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
2523 {
2524 struct si_context *sctx = (struct si_context *)ctx;
2525 struct si_shader_selector *sel = (struct si_shader_selector *)state;
2526
2527 si_shader_selector_reference(sctx, &sel, NULL);
2528 }
2529
2530 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
2531 struct si_shader *vs, unsigned name,
2532 unsigned index, unsigned interpolate)
2533 {
2534 struct tgsi_shader_info *vsinfo = &vs->selector->info;
2535 unsigned j, offset, ps_input_cntl = 0;
2536
2537 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
2538 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
2539 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2540
2541 if (name == TGSI_SEMANTIC_PCOORD ||
2542 (name == TGSI_SEMANTIC_TEXCOORD &&
2543 sctx->sprite_coord_enable & (1 << index))) {
2544 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
2545 }
2546
2547 for (j = 0; j < vsinfo->num_outputs; j++) {
2548 if (name == vsinfo->output_semantic_name[j] &&
2549 index == vsinfo->output_semantic_index[j]) {
2550 offset = vs->info.vs_output_param_offset[j];
2551
2552 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2553 /* The input is loaded from parameter memory. */
2554 ps_input_cntl |= S_028644_OFFSET(offset);
2555 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2556 if (offset == AC_EXP_PARAM_UNDEFINED) {
2557 /* This can happen with depth-only rendering. */
2558 offset = 0;
2559 } else {
2560 /* The input is a DEFAULT_VAL constant. */
2561 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2562 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2563 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2564 }
2565
2566 ps_input_cntl = S_028644_OFFSET(0x20) |
2567 S_028644_DEFAULT_VAL(offset);
2568 }
2569 break;
2570 }
2571 }
2572
2573 if (name == TGSI_SEMANTIC_PRIMID)
2574 /* PrimID is written after the last output. */
2575 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
2576 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2577 /* No corresponding output found, load defaults into input.
2578 * Don't set any other bits.
2579 * (FLAT_SHADE=1 completely changes behavior) */
2580 ps_input_cntl = S_028644_OFFSET(0x20);
2581 /* D3D 9 behaviour. GL is undefined */
2582 if (name == TGSI_SEMANTIC_COLOR && index == 0)
2583 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
2584 }
2585 return ps_input_cntl;
2586 }
2587
2588 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
2589 {
2590 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2591 struct si_shader *ps = sctx->ps_shader.current;
2592 struct si_shader *vs = si_get_vs_state(sctx);
2593 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
2594 unsigned i, num_interp, num_written = 0, bcol_interp[2];
2595
2596 if (!ps || !ps->selector->info.num_inputs)
2597 return;
2598
2599 num_interp = si_get_ps_num_interp(ps);
2600 assert(num_interp > 0);
2601 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
2602
2603 for (i = 0; i < psinfo->num_inputs; i++) {
2604 unsigned name = psinfo->input_semantic_name[i];
2605 unsigned index = psinfo->input_semantic_index[i];
2606 unsigned interpolate = psinfo->input_interpolate[i];
2607
2608 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
2609 interpolate));
2610 num_written++;
2611
2612 if (name == TGSI_SEMANTIC_COLOR) {
2613 assert(index < ARRAY_SIZE(bcol_interp));
2614 bcol_interp[index] = interpolate;
2615 }
2616 }
2617
2618 if (ps->key.part.ps.prolog.color_two_side) {
2619 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
2620
2621 for (i = 0; i < 2; i++) {
2622 if (!(psinfo->colors_read & (0xf << (i * 4))))
2623 continue;
2624
2625 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
2626 i, bcol_interp[i]));
2627 num_written++;
2628 }
2629 }
2630 assert(num_interp == num_written);
2631 }
2632
2633 /**
2634 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2635 */
2636 static void si_init_config_add_vgt_flush(struct si_context *sctx)
2637 {
2638 if (sctx->init_config_has_vgt_flush)
2639 return;
2640
2641 /* Done by Vulkan before VGT_FLUSH. */
2642 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2643 si_pm4_cmd_add(sctx->init_config,
2644 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2645 si_pm4_cmd_end(sctx->init_config, false);
2646
2647 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2648 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2649 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2650 si_pm4_cmd_end(sctx->init_config, false);
2651 sctx->init_config_has_vgt_flush = true;
2652 }
2653
2654 /* Initialize state related to ESGS / GSVS ring buffers */
2655 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2656 {
2657 struct si_shader_selector *es =
2658 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2659 struct si_shader_selector *gs = sctx->gs_shader.cso;
2660 struct si_pm4_state *pm4;
2661
2662 /* Chip constants. */
2663 unsigned num_se = sctx->screen->info.max_se;
2664 unsigned wave_size = 64;
2665 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2666 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2667 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2668 */
2669 unsigned gs_vertex_reuse = (sctx->b.chip_class >= VI ? 32 : 16) * num_se;
2670 unsigned alignment = 256 * num_se;
2671 /* The maximum size is 63.999 MB per SE. */
2672 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2673
2674 /* Calculate the minimum size. */
2675 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
2676 wave_size, alignment);
2677
2678 /* These are recommended sizes, not minimum sizes. */
2679 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2680 es->esgs_itemsize * gs->gs_input_verts_per_prim;
2681 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2682 gs->max_gsvs_emit_size;
2683
2684 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2685 esgs_ring_size = align(esgs_ring_size, alignment);
2686 gsvs_ring_size = align(gsvs_ring_size, alignment);
2687
2688 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2689 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2690
2691 /* Some rings don't have to be allocated if shaders don't use them.
2692 * (e.g. no varyings between ES and GS or GS and VS)
2693 *
2694 * GFX9 doesn't have the ESGS ring.
2695 */
2696 bool update_esgs = sctx->b.chip_class <= VI &&
2697 esgs_ring_size &&
2698 (!sctx->esgs_ring ||
2699 sctx->esgs_ring->width0 < esgs_ring_size);
2700 bool update_gsvs = gsvs_ring_size &&
2701 (!sctx->gsvs_ring ||
2702 sctx->gsvs_ring->width0 < gsvs_ring_size);
2703
2704 if (!update_esgs && !update_gsvs)
2705 return true;
2706
2707 if (update_esgs) {
2708 pipe_resource_reference(&sctx->esgs_ring, NULL);
2709 sctx->esgs_ring =
2710 si_aligned_buffer_create(sctx->b.b.screen,
2711 R600_RESOURCE_FLAG_UNMAPPABLE,
2712 PIPE_USAGE_DEFAULT,
2713 esgs_ring_size, alignment);
2714 if (!sctx->esgs_ring)
2715 return false;
2716 }
2717
2718 if (update_gsvs) {
2719 pipe_resource_reference(&sctx->gsvs_ring, NULL);
2720 sctx->gsvs_ring =
2721 si_aligned_buffer_create(sctx->b.b.screen,
2722 R600_RESOURCE_FLAG_UNMAPPABLE,
2723 PIPE_USAGE_DEFAULT,
2724 gsvs_ring_size, alignment);
2725 if (!sctx->gsvs_ring)
2726 return false;
2727 }
2728
2729 /* Create the "init_config_gs_rings" state. */
2730 pm4 = CALLOC_STRUCT(si_pm4_state);
2731 if (!pm4)
2732 return false;
2733
2734 if (sctx->b.chip_class >= CIK) {
2735 if (sctx->esgs_ring) {
2736 assert(sctx->b.chip_class <= VI);
2737 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2738 sctx->esgs_ring->width0 / 256);
2739 }
2740 if (sctx->gsvs_ring)
2741 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2742 sctx->gsvs_ring->width0 / 256);
2743 } else {
2744 if (sctx->esgs_ring)
2745 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2746 sctx->esgs_ring->width0 / 256);
2747 if (sctx->gsvs_ring)
2748 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2749 sctx->gsvs_ring->width0 / 256);
2750 }
2751
2752 /* Set the state. */
2753 if (sctx->init_config_gs_rings)
2754 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
2755 sctx->init_config_gs_rings = pm4;
2756
2757 if (!sctx->init_config_has_vgt_flush) {
2758 si_init_config_add_vgt_flush(sctx);
2759 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2760 }
2761
2762 /* Flush the context to re-emit both init_config states. */
2763 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2764 si_context_gfx_flush(sctx, PIPE_FLUSH_ASYNC, NULL);
2765
2766 /* Set ring bindings. */
2767 if (sctx->esgs_ring) {
2768 assert(sctx->b.chip_class <= VI);
2769 si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
2770 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2771 true, true, 4, 64, 0);
2772 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
2773 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2774 false, false, 0, 0, 0);
2775 }
2776 if (sctx->gsvs_ring) {
2777 si_set_ring_buffer(&sctx->b.b, SI_RING_GSVS,
2778 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
2779 false, false, 0, 0, 0);
2780 }
2781
2782 return true;
2783 }
2784
2785 static void si_shader_lock(struct si_shader *shader)
2786 {
2787 mtx_lock(&shader->selector->mutex);
2788 if (shader->previous_stage_sel) {
2789 assert(shader->previous_stage_sel != shader->selector);
2790 mtx_lock(&shader->previous_stage_sel->mutex);
2791 }
2792 }
2793
2794 static void si_shader_unlock(struct si_shader *shader)
2795 {
2796 if (shader->previous_stage_sel)
2797 mtx_unlock(&shader->previous_stage_sel->mutex);
2798 mtx_unlock(&shader->selector->mutex);
2799 }
2800
2801 /**
2802 * @returns 1 if \p sel has been updated to use a new scratch buffer
2803 * 0 if not
2804 * < 0 if there was a failure
2805 */
2806 static int si_update_scratch_buffer(struct si_context *sctx,
2807 struct si_shader *shader)
2808 {
2809 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
2810 int r;
2811
2812 if (!shader)
2813 return 0;
2814
2815 /* This shader doesn't need a scratch buffer */
2816 if (shader->config.scratch_bytes_per_wave == 0)
2817 return 0;
2818
2819 /* Prevent race conditions when updating:
2820 * - si_shader::scratch_bo
2821 * - si_shader::binary::code
2822 * - si_shader::previous_stage::binary::code.
2823 */
2824 si_shader_lock(shader);
2825
2826 /* This shader is already configured to use the current
2827 * scratch buffer. */
2828 if (shader->scratch_bo == sctx->scratch_buffer) {
2829 si_shader_unlock(shader);
2830 return 0;
2831 }
2832
2833 assert(sctx->scratch_buffer);
2834
2835 if (shader->previous_stage)
2836 si_shader_apply_scratch_relocs(shader->previous_stage, scratch_va);
2837
2838 si_shader_apply_scratch_relocs(shader, scratch_va);
2839
2840 /* Replace the shader bo with a new bo that has the relocs applied. */
2841 r = si_shader_binary_upload(sctx->screen, shader);
2842 if (r) {
2843 si_shader_unlock(shader);
2844 return r;
2845 }
2846
2847 /* Update the shader state to use the new shader bo. */
2848 si_shader_init_pm4_state(sctx->screen, shader);
2849
2850 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
2851
2852 si_shader_unlock(shader);
2853 return 1;
2854 }
2855
2856 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
2857 {
2858 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
2859 }
2860
2861 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
2862 {
2863 return shader ? shader->config.scratch_bytes_per_wave : 0;
2864 }
2865
2866 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
2867 {
2868 if (!sctx->tes_shader.cso)
2869 return NULL; /* tessellation disabled */
2870
2871 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
2872 sctx->fixed_func_tcs_shader.current;
2873 }
2874
2875 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
2876 {
2877 unsigned bytes = 0;
2878
2879 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
2880 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
2881 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
2882 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
2883
2884 if (sctx->tes_shader.cso) {
2885 struct si_shader *tcs = si_get_tcs_current(sctx);
2886
2887 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
2888 }
2889 return bytes;
2890 }
2891
2892 static bool si_update_scratch_relocs(struct si_context *sctx)
2893 {
2894 struct si_shader *tcs = si_get_tcs_current(sctx);
2895 int r;
2896
2897 /* Update the shaders, so that they are using the latest scratch.
2898 * The scratch buffer may have been changed since these shaders were
2899 * last used, so we still need to try to update them, even if they
2900 * require scratch buffers smaller than the current size.
2901 */
2902 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
2903 if (r < 0)
2904 return false;
2905 if (r == 1)
2906 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2907
2908 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
2909 if (r < 0)
2910 return false;
2911 if (r == 1)
2912 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2913
2914 r = si_update_scratch_buffer(sctx, tcs);
2915 if (r < 0)
2916 return false;
2917 if (r == 1)
2918 si_pm4_bind_state(sctx, hs, tcs->pm4);
2919
2920 /* VS can be bound as LS, ES, or VS. */
2921 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
2922 if (r < 0)
2923 return false;
2924 if (r == 1) {
2925 if (sctx->tes_shader.current)
2926 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2927 else if (sctx->gs_shader.current)
2928 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2929 else
2930 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2931 }
2932
2933 /* TES can be bound as ES or VS. */
2934 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
2935 if (r < 0)
2936 return false;
2937 if (r == 1) {
2938 if (sctx->gs_shader.current)
2939 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2940 else
2941 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2942 }
2943
2944 return true;
2945 }
2946
2947 static bool si_update_spi_tmpring_size(struct si_context *sctx)
2948 {
2949 unsigned current_scratch_buffer_size =
2950 si_get_current_scratch_buffer_size(sctx);
2951 unsigned scratch_bytes_per_wave =
2952 si_get_max_scratch_bytes_per_wave(sctx);
2953 unsigned scratch_needed_size = scratch_bytes_per_wave *
2954 sctx->scratch_waves;
2955 unsigned spi_tmpring_size;
2956
2957 if (scratch_needed_size > 0) {
2958 if (scratch_needed_size > current_scratch_buffer_size) {
2959 /* Create a bigger scratch buffer */
2960 r600_resource_reference(&sctx->scratch_buffer, NULL);
2961
2962 sctx->scratch_buffer = (struct r600_resource*)
2963 si_aligned_buffer_create(&sctx->screen->b,
2964 R600_RESOURCE_FLAG_UNMAPPABLE,
2965 PIPE_USAGE_DEFAULT,
2966 scratch_needed_size, 256);
2967 if (!sctx->scratch_buffer)
2968 return false;
2969
2970 si_mark_atom_dirty(sctx, &sctx->scratch_state);
2971 si_context_add_resource_size(&sctx->b.b,
2972 &sctx->scratch_buffer->b.b);
2973 }
2974
2975 if (!si_update_scratch_relocs(sctx))
2976 return false;
2977 }
2978
2979 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
2980 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
2981 "scratch size should already be aligned correctly.");
2982
2983 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
2984 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
2985 if (spi_tmpring_size != sctx->spi_tmpring_size) {
2986 sctx->spi_tmpring_size = spi_tmpring_size;
2987 si_mark_atom_dirty(sctx, &sctx->scratch_state);
2988 }
2989 return true;
2990 }
2991
2992 static void si_init_tess_factor_ring(struct si_context *sctx)
2993 {
2994 assert(!sctx->tess_rings);
2995
2996 /* The address must be aligned to 2^19, because the shader only
2997 * receives the high 13 bits.
2998 */
2999 sctx->tess_rings = si_aligned_buffer_create(sctx->b.b.screen,
3000 R600_RESOURCE_FLAG_32BIT,
3001 PIPE_USAGE_DEFAULT,
3002 sctx->screen->tess_offchip_ring_size +
3003 sctx->screen->tess_factor_ring_size,
3004 1 << 19);
3005 if (!sctx->tess_rings)
3006 return;
3007
3008 si_init_config_add_vgt_flush(sctx);
3009
3010 si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_rings),
3011 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3012
3013 uint64_t factor_va = r600_resource(sctx->tess_rings)->gpu_address +
3014 sctx->screen->tess_offchip_ring_size;
3015
3016 /* Append these registers to the init config state. */
3017 if (sctx->b.chip_class >= CIK) {
3018 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3019 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3020 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3021 factor_va >> 8);
3022 if (sctx->b.chip_class >= GFX9)
3023 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3024 S_030944_BASE_HI(factor_va >> 40));
3025 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3026 sctx->screen->vgt_hs_offchip_param);
3027 } else {
3028 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3029 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3030 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3031 factor_va >> 8);
3032 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3033 sctx->screen->vgt_hs_offchip_param);
3034 }
3035
3036 /* Flush the context to re-emit the init_config state.
3037 * This is done only once in a lifetime of a context.
3038 */
3039 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3040 sctx->b.initial_gfx_cs_size = 0; /* force flush */
3041 si_context_gfx_flush(sctx, PIPE_FLUSH_ASYNC, NULL);
3042 }
3043
3044 /**
3045 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
3046 * VS passes its outputs to TES directly, so the fixed-function shader only
3047 * has to write TESSOUTER and TESSINNER.
3048 */
3049 static void si_generate_fixed_func_tcs(struct si_context *sctx)
3050 {
3051 struct ureg_src outer, inner;
3052 struct ureg_dst tessouter, tessinner;
3053 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
3054
3055 if (!ureg)
3056 return; /* if we get here, we're screwed */
3057
3058 assert(!sctx->fixed_func_tcs_shader.cso);
3059
3060 outer = ureg_DECL_system_value(ureg,
3061 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
3062 inner = ureg_DECL_system_value(ureg,
3063 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
3064
3065 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
3066 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
3067
3068 ureg_MOV(ureg, tessouter, outer);
3069 ureg_MOV(ureg, tessinner, inner);
3070 ureg_END(ureg);
3071
3072 sctx->fixed_func_tcs_shader.cso =
3073 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
3074 }
3075
3076 static void si_update_vgt_shader_config(struct si_context *sctx)
3077 {
3078 /* Calculate the index of the config.
3079 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3080 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
3081 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
3082
3083 if (!*pm4) {
3084 uint32_t stages = 0;
3085
3086 *pm4 = CALLOC_STRUCT(si_pm4_state);
3087
3088 if (sctx->tes_shader.cso) {
3089 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3090 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3091
3092 if (sctx->gs_shader.cso)
3093 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3094 S_028B54_GS_EN(1) |
3095 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3096 else
3097 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3098 } else if (sctx->gs_shader.cso) {
3099 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3100 S_028B54_GS_EN(1) |
3101 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3102 }
3103
3104 if (sctx->b.chip_class >= GFX9)
3105 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3106
3107 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3108 }
3109 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3110 }
3111
3112 bool si_update_shaders(struct si_context *sctx)
3113 {
3114 struct pipe_context *ctx = (struct pipe_context*)sctx;
3115 struct si_compiler_ctx_state compiler_state;
3116 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3117 struct si_shader *old_vs = si_get_vs_state(sctx);
3118 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3119 struct si_shader *old_ps = sctx->ps_shader.current;
3120 unsigned old_spi_shader_col_format =
3121 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3122 int r;
3123
3124 compiler_state.chip_class = sctx->b.chip_class;
3125 compiler_state.tm = sctx->tm;
3126 compiler_state.debug = sctx->debug;
3127 compiler_state.is_debug_context = sctx->is_debug;
3128
3129 /* Update stages before GS. */
3130 if (sctx->tes_shader.cso) {
3131 if (!sctx->tess_rings) {
3132 si_init_tess_factor_ring(sctx);
3133 if (!sctx->tess_rings)
3134 return false;
3135 }
3136
3137 /* VS as LS */
3138 if (sctx->b.chip_class <= VI) {
3139 r = si_shader_select(ctx, &sctx->vs_shader,
3140 &compiler_state);
3141 if (r)
3142 return false;
3143 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3144 }
3145
3146 if (sctx->tcs_shader.cso) {
3147 r = si_shader_select(ctx, &sctx->tcs_shader,
3148 &compiler_state);
3149 if (r)
3150 return false;
3151 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3152 } else {
3153 if (!sctx->fixed_func_tcs_shader.cso) {
3154 si_generate_fixed_func_tcs(sctx);
3155 if (!sctx->fixed_func_tcs_shader.cso)
3156 return false;
3157 }
3158
3159 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3160 &compiler_state);
3161 if (r)
3162 return false;
3163 si_pm4_bind_state(sctx, hs,
3164 sctx->fixed_func_tcs_shader.current->pm4);
3165 }
3166
3167 if (sctx->gs_shader.cso) {
3168 /* TES as ES */
3169 if (sctx->b.chip_class <= VI) {
3170 r = si_shader_select(ctx, &sctx->tes_shader,
3171 &compiler_state);
3172 if (r)
3173 return false;
3174 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3175 }
3176 } else {
3177 /* TES as VS */
3178 r = si_shader_select(ctx, &sctx->tes_shader,
3179 &compiler_state);
3180 if (r)
3181 return false;
3182 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3183 }
3184 } else if (sctx->gs_shader.cso) {
3185 if (sctx->b.chip_class <= VI) {
3186 /* VS as ES */
3187 r = si_shader_select(ctx, &sctx->vs_shader,
3188 &compiler_state);
3189 if (r)
3190 return false;
3191 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3192
3193 si_pm4_bind_state(sctx, ls, NULL);
3194 si_pm4_bind_state(sctx, hs, NULL);
3195 }
3196 } else {
3197 /* VS as VS */
3198 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
3199 if (r)
3200 return false;
3201 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3202 si_pm4_bind_state(sctx, ls, NULL);
3203 si_pm4_bind_state(sctx, hs, NULL);
3204 }
3205
3206 /* Update GS. */
3207 if (sctx->gs_shader.cso) {
3208 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
3209 if (r)
3210 return false;
3211 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3212 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3213
3214 if (!si_update_gs_ring_buffers(sctx))
3215 return false;
3216 } else {
3217 si_pm4_bind_state(sctx, gs, NULL);
3218 if (sctx->b.chip_class <= VI)
3219 si_pm4_bind_state(sctx, es, NULL);
3220 }
3221
3222 si_update_vgt_shader_config(sctx);
3223
3224 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3225 si_mark_atom_dirty(sctx, &sctx->clip_regs);
3226
3227 if (sctx->ps_shader.cso) {
3228 unsigned db_shader_control;
3229
3230 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
3231 if (r)
3232 return false;
3233 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3234
3235 db_shader_control =
3236 sctx->ps_shader.cso->db_shader_control |
3237 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3238
3239 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3240 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3241 sctx->flatshade != rs->flatshade) {
3242 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3243 sctx->flatshade = rs->flatshade;
3244 si_mark_atom_dirty(sctx, &sctx->spi_map);
3245 }
3246
3247 if (sctx->screen->rbplus_allowed &&
3248 si_pm4_state_changed(sctx, ps) &&
3249 (!old_ps ||
3250 old_spi_shader_col_format !=
3251 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3252 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
3253
3254 if (sctx->ps_db_shader_control != db_shader_control) {
3255 sctx->ps_db_shader_control = db_shader_control;
3256 si_mark_atom_dirty(sctx, &sctx->db_render_state);
3257 if (sctx->screen->dpbb_allowed)
3258 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
3259 }
3260
3261 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3262 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3263 si_mark_atom_dirty(sctx, &sctx->msaa_config);
3264
3265 if (sctx->b.chip_class == SI)
3266 si_mark_atom_dirty(sctx, &sctx->db_render_state);
3267
3268 if (sctx->framebuffer.nr_samples <= 1)
3269 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
3270 }
3271 }
3272
3273 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3274 si_pm4_state_enabled_and_changed(sctx, hs) ||
3275 si_pm4_state_enabled_and_changed(sctx, es) ||
3276 si_pm4_state_enabled_and_changed(sctx, gs) ||
3277 si_pm4_state_enabled_and_changed(sctx, vs) ||
3278 si_pm4_state_enabled_and_changed(sctx, ps)) {
3279 if (!si_update_spi_tmpring_size(sctx))
3280 return false;
3281 }
3282
3283 if (sctx->b.chip_class >= CIK) {
3284 if (si_pm4_state_enabled_and_changed(sctx, ls))
3285 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3286 else if (!sctx->queued.named.ls)
3287 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3288
3289 if (si_pm4_state_enabled_and_changed(sctx, hs))
3290 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3291 else if (!sctx->queued.named.hs)
3292 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3293
3294 if (si_pm4_state_enabled_and_changed(sctx, es))
3295 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
3296 else if (!sctx->queued.named.es)
3297 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
3298
3299 if (si_pm4_state_enabled_and_changed(sctx, gs))
3300 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
3301 else if (!sctx->queued.named.gs)
3302 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
3303
3304 if (si_pm4_state_enabled_and_changed(sctx, vs))
3305 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
3306 else if (!sctx->queued.named.vs)
3307 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
3308
3309 if (si_pm4_state_enabled_and_changed(sctx, ps))
3310 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
3311 else if (!sctx->queued.named.ps)
3312 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
3313 }
3314
3315 sctx->do_update_shaders = false;
3316 return true;
3317 }
3318
3319 static void si_emit_scratch_state(struct si_context *sctx,
3320 struct r600_atom *atom)
3321 {
3322 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3323
3324 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3325 sctx->spi_tmpring_size);
3326
3327 if (sctx->scratch_buffer) {
3328 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
3329 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3330 RADEON_PRIO_SCRATCH_BUFFER);
3331 }
3332 }
3333
3334 void *si_get_blit_vs(struct si_context *sctx, enum blitter_attrib_type type,
3335 unsigned num_layers)
3336 {
3337 struct pipe_context *pipe = &sctx->b.b;
3338 unsigned vs_blit_property;
3339 void **vs;
3340
3341 switch (type) {
3342 case UTIL_BLITTER_ATTRIB_NONE:
3343 vs = num_layers > 1 ? &sctx->vs_blit_pos_layered :
3344 &sctx->vs_blit_pos;
3345 vs_blit_property = SI_VS_BLIT_SGPRS_POS;
3346 break;
3347 case UTIL_BLITTER_ATTRIB_COLOR:
3348 vs = num_layers > 1 ? &sctx->vs_blit_color_layered :
3349 &sctx->vs_blit_color;
3350 vs_blit_property = SI_VS_BLIT_SGPRS_POS_COLOR;
3351 break;
3352 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
3353 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
3354 assert(num_layers == 1);
3355 vs = &sctx->vs_blit_texcoord;
3356 vs_blit_property = SI_VS_BLIT_SGPRS_POS_TEXCOORD;
3357 break;
3358 default:
3359 assert(0);
3360 return NULL;
3361 }
3362 if (*vs)
3363 return *vs;
3364
3365 struct ureg_program *ureg = ureg_create(PIPE_SHADER_VERTEX);
3366 if (!ureg)
3367 return NULL;
3368
3369 /* Tell the shader to load VS inputs from SGPRs: */
3370 ureg_property(ureg, TGSI_PROPERTY_VS_BLIT_SGPRS, vs_blit_property);
3371 ureg_property(ureg, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION, true);
3372
3373 /* This is just a pass-through shader with 1-3 MOV instructions. */
3374 ureg_MOV(ureg,
3375 ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0),
3376 ureg_DECL_vs_input(ureg, 0));
3377
3378 if (type != UTIL_BLITTER_ATTRIB_NONE) {
3379 ureg_MOV(ureg,
3380 ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, 0),
3381 ureg_DECL_vs_input(ureg, 1));
3382 }
3383
3384 if (num_layers > 1) {
3385 struct ureg_src instance_id =
3386 ureg_DECL_system_value(ureg, TGSI_SEMANTIC_INSTANCEID, 0);
3387 struct ureg_dst layer =
3388 ureg_DECL_output(ureg, TGSI_SEMANTIC_LAYER, 0);
3389
3390 ureg_MOV(ureg, ureg_writemask(layer, TGSI_WRITEMASK_X),
3391 ureg_scalar(instance_id, TGSI_SWIZZLE_X));
3392 }
3393 ureg_END(ureg);
3394
3395 *vs = ureg_create_shader_and_destroy(ureg, pipe);
3396 return *vs;
3397 }
3398
3399 void si_init_shader_functions(struct si_context *sctx)
3400 {
3401 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
3402 si_init_atom(sctx, &sctx->scratch_state, &sctx->atoms.s.scratch_state,
3403 si_emit_scratch_state);
3404
3405 sctx->b.b.create_vs_state = si_create_shader_selector;
3406 sctx->b.b.create_tcs_state = si_create_shader_selector;
3407 sctx->b.b.create_tes_state = si_create_shader_selector;
3408 sctx->b.b.create_gs_state = si_create_shader_selector;
3409 sctx->b.b.create_fs_state = si_create_shader_selector;
3410
3411 sctx->b.b.bind_vs_state = si_bind_vs_shader;
3412 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
3413 sctx->b.b.bind_tes_state = si_bind_tes_shader;
3414 sctx->b.b.bind_gs_state = si_bind_gs_shader;
3415 sctx->b.b.bind_fs_state = si_bind_ps_shader;
3416
3417 sctx->b.b.delete_vs_state = si_delete_shader_selector;
3418 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
3419 sctx->b.b.delete_tes_state = si_delete_shader_selector;
3420 sctx->b.b.delete_gs_state = si_delete_shader_selector;
3421 sctx->b.b.delete_fs_state = si_delete_shader_selector;
3422 }