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radeonsi/gfx10: set GE_PC_ALLOC
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
45 * size as integer.
46 */
47 void *si_get_ir_binary(struct si_shader_selector *sel)
48 {
49 struct blob blob;
50 unsigned ir_size;
51 void *ir_binary;
52
53 if (sel->tokens) {
54 ir_binary = sel->tokens;
55 ir_size = tgsi_num_tokens(sel->tokens) *
56 sizeof(struct tgsi_token);
57 } else {
58 assert(sel->nir);
59
60 blob_init(&blob);
61 nir_serialize(&blob, sel->nir);
62 ir_binary = blob.data;
63 ir_size = blob.size;
64 }
65
66 unsigned size = 4 + ir_size + sizeof(sel->so);
67 char *result = (char*)MALLOC(size);
68 if (!result)
69 return NULL;
70
71 *((uint32_t*)result) = size;
72 memcpy(result + 4, ir_binary, ir_size);
73 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
74
75 if (sel->nir)
76 blob_finish(&blob);
77
78 return result;
79 }
80
81 /** Copy "data" to "ptr" and return the next dword following copied data. */
82 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
83 {
84 /* data may be NULL if size == 0 */
85 if (size)
86 memcpy(ptr, data, size);
87 ptr += DIV_ROUND_UP(size, 4);
88 return ptr;
89 }
90
91 /** Read data from "ptr". Return the next dword following the data. */
92 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
93 {
94 memcpy(data, ptr, size);
95 ptr += DIV_ROUND_UP(size, 4);
96 return ptr;
97 }
98
99 /**
100 * Write the size as uint followed by the data. Return the next dword
101 * following the copied data.
102 */
103 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
104 {
105 *ptr++ = size;
106 return write_data(ptr, data, size);
107 }
108
109 /**
110 * Read the size as uint followed by the data. Return both via parameters.
111 * Return the next dword following the data.
112 */
113 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
114 {
115 *size = *ptr++;
116 assert(*data == NULL);
117 if (!*size)
118 return ptr;
119 *data = malloc(*size);
120 return read_data(ptr, *data, *size);
121 }
122
123 /**
124 * Return the shader binary in a buffer. The first 4 bytes contain its size
125 * as integer.
126 */
127 static void *si_get_shader_binary(struct si_shader *shader)
128 {
129 /* There is always a size of data followed by the data itself. */
130 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
131 strlen(shader->binary.llvm_ir_string) + 1 : 0;
132
133 /* Refuse to allocate overly large buffers and guard against integer
134 * overflow. */
135 if (shader->binary.elf_size > UINT_MAX / 4 ||
136 llvm_ir_size > UINT_MAX / 4)
137 return NULL;
138
139 unsigned size =
140 4 + /* total size */
141 4 + /* CRC32 of the data below */
142 align(sizeof(shader->config), 4) +
143 align(sizeof(shader->info), 4) +
144 4 + align(shader->binary.elf_size, 4) +
145 4 + align(llvm_ir_size, 4);
146 void *buffer = CALLOC(1, size);
147 uint32_t *ptr = (uint32_t*)buffer;
148
149 if (!buffer)
150 return NULL;
151
152 *ptr++ = size;
153 ptr++; /* CRC32 is calculated at the end. */
154
155 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
156 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
157 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
158 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
159 assert((char *)ptr - (char *)buffer == size);
160
161 /* Compute CRC32. */
162 ptr = (uint32_t*)buffer;
163 ptr++;
164 *ptr = util_hash_crc32(ptr + 1, size - 8);
165
166 return buffer;
167 }
168
169 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
170 {
171 uint32_t *ptr = (uint32_t*)binary;
172 uint32_t size = *ptr++;
173 uint32_t crc32 = *ptr++;
174 unsigned chunk_size;
175 unsigned elf_size;
176
177 if (util_hash_crc32(ptr, size - 8) != crc32) {
178 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
179 return false;
180 }
181
182 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
183 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
184 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
185 &elf_size);
186 shader->binary.elf_size = elf_size;
187 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
188
189 return true;
190 }
191
192 /**
193 * Insert a shader into the cache. It's assumed the shader is not in the cache.
194 * Use si_shader_cache_load_shader before calling this.
195 *
196 * Returns false on failure, in which case the ir_binary should be freed.
197 */
198 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
199 struct si_shader *shader,
200 bool insert_into_disk_cache)
201 {
202 void *hw_binary;
203 struct hash_entry *entry;
204 uint8_t key[CACHE_KEY_SIZE];
205
206 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
207 if (entry)
208 return false; /* already added */
209
210 hw_binary = si_get_shader_binary(shader);
211 if (!hw_binary)
212 return false;
213
214 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
215 hw_binary) == NULL) {
216 FREE(hw_binary);
217 return false;
218 }
219
220 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
221 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
222 *((uint32_t *)ir_binary), key);
223 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
224 *((uint32_t *) hw_binary), NULL);
225 }
226
227 return true;
228 }
229
230 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
231 struct si_shader *shader)
232 {
233 struct hash_entry *entry =
234 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
235 if (!entry) {
236 if (sscreen->disk_shader_cache) {
237 unsigned char sha1[CACHE_KEY_SIZE];
238 size_t tg_size = *((uint32_t *) ir_binary);
239
240 disk_cache_compute_key(sscreen->disk_shader_cache,
241 ir_binary, tg_size, sha1);
242
243 size_t binary_size;
244 uint8_t *buffer =
245 disk_cache_get(sscreen->disk_shader_cache,
246 sha1, &binary_size);
247 if (!buffer)
248 return false;
249
250 if (binary_size < sizeof(uint32_t) ||
251 *((uint32_t*)buffer) != binary_size) {
252 /* Something has gone wrong discard the item
253 * from the cache and rebuild/link from
254 * source.
255 */
256 assert(!"Invalid radeonsi shader disk cache "
257 "item!");
258
259 disk_cache_remove(sscreen->disk_shader_cache,
260 sha1);
261 free(buffer);
262
263 return false;
264 }
265
266 if (!si_load_shader_binary(shader, buffer)) {
267 free(buffer);
268 return false;
269 }
270 free(buffer);
271
272 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
273 shader, false))
274 FREE(ir_binary);
275 } else {
276 return false;
277 }
278 } else {
279 if (si_load_shader_binary(shader, entry->data))
280 FREE(ir_binary);
281 else
282 return false;
283 }
284 p_atomic_inc(&sscreen->num_shader_cache_hits);
285 return true;
286 }
287
288 static uint32_t si_shader_cache_key_hash(const void *key)
289 {
290 /* The first dword is the key size. */
291 return util_hash_crc32(key, *(uint32_t*)key);
292 }
293
294 static bool si_shader_cache_key_equals(const void *a, const void *b)
295 {
296 uint32_t *keya = (uint32_t*)a;
297 uint32_t *keyb = (uint32_t*)b;
298
299 /* The first dword is the key size. */
300 if (*keya != *keyb)
301 return false;
302
303 return memcmp(keya, keyb, *keya) == 0;
304 }
305
306 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
307 {
308 FREE((void*)entry->key);
309 FREE(entry->data);
310 }
311
312 bool si_init_shader_cache(struct si_screen *sscreen)
313 {
314 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
315 sscreen->shader_cache =
316 _mesa_hash_table_create(NULL,
317 si_shader_cache_key_hash,
318 si_shader_cache_key_equals);
319
320 return sscreen->shader_cache != NULL;
321 }
322
323 void si_destroy_shader_cache(struct si_screen *sscreen)
324 {
325 if (sscreen->shader_cache)
326 _mesa_hash_table_destroy(sscreen->shader_cache,
327 si_destroy_shader_cache_entry);
328 mtx_destroy(&sscreen->shader_cache_mutex);
329 }
330
331 /* SHADER STATES */
332
333 static void si_set_tesseval_regs(struct si_screen *sscreen,
334 const struct si_shader_selector *tes,
335 struct si_pm4_state *pm4)
336 {
337 const struct tgsi_shader_info *info = &tes->info;
338 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
339 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
340 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
341 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
342 unsigned type, partitioning, topology, distribution_mode;
343
344 switch (tes_prim_mode) {
345 case PIPE_PRIM_LINES:
346 type = V_028B6C_TESS_ISOLINE;
347 break;
348 case PIPE_PRIM_TRIANGLES:
349 type = V_028B6C_TESS_TRIANGLE;
350 break;
351 case PIPE_PRIM_QUADS:
352 type = V_028B6C_TESS_QUAD;
353 break;
354 default:
355 assert(0);
356 return;
357 }
358
359 switch (tes_spacing) {
360 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
361 partitioning = V_028B6C_PART_FRAC_ODD;
362 break;
363 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
364 partitioning = V_028B6C_PART_FRAC_EVEN;
365 break;
366 case PIPE_TESS_SPACING_EQUAL:
367 partitioning = V_028B6C_PART_INTEGER;
368 break;
369 default:
370 assert(0);
371 return;
372 }
373
374 if (tes_point_mode)
375 topology = V_028B6C_OUTPUT_POINT;
376 else if (tes_prim_mode == PIPE_PRIM_LINES)
377 topology = V_028B6C_OUTPUT_LINE;
378 else if (tes_vertex_order_cw)
379 /* for some reason, this must be the other way around */
380 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
381 else
382 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
383
384 if (sscreen->has_distributed_tess) {
385 if (sscreen->info.family == CHIP_FIJI ||
386 sscreen->info.family >= CHIP_POLARIS10)
387 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
388 else
389 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
390 } else
391 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
392
393 assert(pm4->shader);
394 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
395 S_028B6C_PARTITIONING(partitioning) |
396 S_028B6C_TOPOLOGY(topology) |
397 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
398 }
399
400 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
401 * whether the "fractional odd" tessellation spacing is used.
402 *
403 * Possible VGT configurations and which state should set the register:
404 *
405 * Reg set in | VGT shader configuration | Value
406 * ------------------------------------------------------
407 * VS as VS | VS | 30
408 * VS as ES | ES -> GS -> VS | 30
409 * TES as VS | LS -> HS -> VS | 14 or 30
410 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
411 *
412 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
413 */
414 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
415 struct si_shader_selector *sel,
416 struct si_shader *shader,
417 struct si_pm4_state *pm4)
418 {
419 unsigned type = sel->type;
420
421 if (sscreen->info.family < CHIP_POLARIS10 ||
422 sscreen->info.chip_class >= GFX10)
423 return;
424
425 /* VS as VS, or VS as ES: */
426 if ((type == PIPE_SHADER_VERTEX &&
427 (!shader ||
428 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
429 /* TES as VS, or TES as ES: */
430 type == PIPE_SHADER_TESS_EVAL) {
431 unsigned vtx_reuse_depth = 30;
432
433 if (type == PIPE_SHADER_TESS_EVAL &&
434 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
435 PIPE_TESS_SPACING_FRACTIONAL_ODD)
436 vtx_reuse_depth = 14;
437
438 assert(pm4->shader);
439 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
440 }
441 }
442
443 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
444 {
445 if (shader->pm4)
446 si_pm4_clear_state(shader->pm4);
447 else
448 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
449
450 if (shader->pm4) {
451 shader->pm4->shader = shader;
452 return shader->pm4;
453 } else {
454 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
455 return NULL;
456 }
457 }
458
459 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
460 {
461 /* Add the pointer to VBO descriptors. */
462 return num_always_on_user_sgprs + 1;
463 }
464
465 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
466 {
467 struct si_pm4_state *pm4;
468 unsigned vgpr_comp_cnt;
469 uint64_t va;
470
471 assert(sscreen->info.chip_class <= GFX8);
472
473 pm4 = si_get_shader_pm4_state(shader);
474 if (!pm4)
475 return;
476
477 va = shader->bo->gpu_address;
478 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
479
480 /* We need at least 2 components for LS.
481 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
482 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
483 */
484 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
485
486 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
487 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
488
489 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
490 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
491 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
492 S_00B528_DX10_CLAMP(1) |
493 S_00B528_FLOAT_MODE(shader->config.float_mode);
494 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
495 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
496 }
497
498 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
499 {
500 struct si_pm4_state *pm4;
501 uint64_t va;
502 unsigned ls_vgpr_comp_cnt = 0;
503
504 pm4 = si_get_shader_pm4_state(shader);
505 if (!pm4)
506 return;
507
508 va = shader->bo->gpu_address;
509 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
510
511 if (sscreen->info.chip_class >= GFX9) {
512 if (sscreen->info.chip_class >= GFX10) {
513 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
514 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
515 } else {
516 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
517 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
518 }
519
520 /* We need at least 2 components for LS.
521 * GFX9 VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
522 * GFX10 VGPR0-3: (VertexID, RelAutoindex, UserVGPR1, InstanceID).
523 * On gfx9, StepRate0 is set to 1 so that VGPR3 doesn't have to
524 * be loaded.
525 */
526 ls_vgpr_comp_cnt = 1;
527 if (shader->info.uses_instanceid) {
528 if (sscreen->info.chip_class >= GFX10)
529 ls_vgpr_comp_cnt = 3;
530 else
531 ls_vgpr_comp_cnt = 2;
532 }
533
534 unsigned num_user_sgprs =
535 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
536
537 shader->config.rsrc2 =
538 S_00B42C_USER_SGPR(num_user_sgprs) |
539 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
540
541 if (sscreen->info.chip_class >= GFX10)
542 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
543 else
544 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
545 } else {
546 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
547 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
548
549 shader->config.rsrc2 =
550 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
551 S_00B42C_OC_LDS_EN(1) |
552 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
553 }
554
555 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
556 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
557 (sscreen->info.chip_class <= GFX9 ?
558 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
559 S_00B428_DX10_CLAMP(1) |
560 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
561 S_00B428_FLOAT_MODE(shader->config.float_mode) |
562 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
563
564 if (sscreen->info.chip_class <= GFX8) {
565 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
566 shader->config.rsrc2);
567 }
568 }
569
570 static void si_emit_shader_es(struct si_context *sctx)
571 {
572 struct si_shader *shader = sctx->queued.named.es->shader;
573 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
574
575 if (!shader)
576 return;
577
578 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
579 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
580 shader->selector->esgs_itemsize / 4);
581
582 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
583 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
584 SI_TRACKED_VGT_TF_PARAM,
585 shader->vgt_tf_param);
586
587 if (shader->vgt_vertex_reuse_block_cntl)
588 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
589 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
590 shader->vgt_vertex_reuse_block_cntl);
591
592 if (initial_cdw != sctx->gfx_cs->current.cdw)
593 sctx->context_roll = true;
594 }
595
596 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
597 {
598 struct si_pm4_state *pm4;
599 unsigned num_user_sgprs;
600 unsigned vgpr_comp_cnt;
601 uint64_t va;
602 unsigned oc_lds_en;
603
604 assert(sscreen->info.chip_class <= GFX8);
605
606 pm4 = si_get_shader_pm4_state(shader);
607 if (!pm4)
608 return;
609
610 pm4->atom.emit = si_emit_shader_es;
611 va = shader->bo->gpu_address;
612 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
613
614 if (shader->selector->type == PIPE_SHADER_VERTEX) {
615 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
616 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
617 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
618 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
619 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
620 num_user_sgprs = SI_TES_NUM_USER_SGPR;
621 } else
622 unreachable("invalid shader selector type");
623
624 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
625
626 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
627 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
628 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
629 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
630 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
631 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
632 S_00B328_DX10_CLAMP(1) |
633 S_00B328_FLOAT_MODE(shader->config.float_mode));
634 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
635 S_00B32C_USER_SGPR(num_user_sgprs) |
636 S_00B32C_OC_LDS_EN(oc_lds_en) |
637 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
638
639 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
640 si_set_tesseval_regs(sscreen, shader->selector, pm4);
641
642 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
643 }
644
645 void gfx9_get_gs_info(struct si_shader_selector *es,
646 struct si_shader_selector *gs,
647 struct gfx9_gs_info *out)
648 {
649 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
650 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
651 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
652 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
653
654 /* All these are in dwords: */
655 /* We can't allow using the whole LDS, because GS waves compete with
656 * other shader stages for LDS space. */
657 const unsigned max_lds_size = 8 * 1024;
658 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
659 unsigned esgs_lds_size;
660
661 /* All these are per subgroup: */
662 const unsigned max_out_prims = 32 * 1024;
663 const unsigned max_es_verts = 255;
664 const unsigned ideal_gs_prims = 64;
665 unsigned max_gs_prims, gs_prims;
666 unsigned min_es_verts, es_verts, worst_case_es_verts;
667
668 if (uses_adjacency || gs_num_invocations > 1)
669 max_gs_prims = 127 / gs_num_invocations;
670 else
671 max_gs_prims = 255;
672
673 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
674 * Make sure we don't go over the maximum value.
675 */
676 if (gs->gs_max_out_vertices > 0) {
677 max_gs_prims = MIN2(max_gs_prims,
678 max_out_prims /
679 (gs->gs_max_out_vertices * gs_num_invocations));
680 }
681 assert(max_gs_prims > 0);
682
683 /* If the primitive has adjacency, halve the number of vertices
684 * that will be reused in multiple primitives.
685 */
686 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
687
688 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
689 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
690
691 /* Compute ESGS LDS size based on the worst case number of ES vertices
692 * needed to create the target number of GS prims per subgroup.
693 */
694 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
695
696 /* If total LDS usage is too big, refactor partitions based on ratio
697 * of ESGS item sizes.
698 */
699 if (esgs_lds_size > max_lds_size) {
700 /* Our target GS Prims Per Subgroup was too large. Calculate
701 * the maximum number of GS Prims Per Subgroup that will fit
702 * into LDS, capped by the maximum that the hardware can support.
703 */
704 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
705 max_gs_prims);
706 assert(gs_prims > 0);
707 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
708 max_es_verts);
709
710 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
711 assert(esgs_lds_size <= max_lds_size);
712 }
713
714 /* Now calculate remaining ESGS information. */
715 if (esgs_lds_size)
716 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
717 else
718 es_verts = max_es_verts;
719
720 /* Vertices for adjacency primitives are not always reused, so restore
721 * it for ES_VERTS_PER_SUBGRP.
722 */
723 min_es_verts = gs->gs_input_verts_per_prim;
724
725 /* For normal primitives, the VGT only checks if they are past the ES
726 * verts per subgroup after allocating a full GS primitive and if they
727 * are, kick off a new subgroup. But if those additional ES verts are
728 * unique (e.g. not reused) we need to make sure there is enough LDS
729 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
730 */
731 es_verts -= min_es_verts - 1;
732
733 out->es_verts_per_subgroup = es_verts;
734 out->gs_prims_per_subgroup = gs_prims;
735 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
736 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
737 gs->gs_max_out_vertices;
738 out->esgs_ring_size = 4 * esgs_lds_size;
739
740 assert(out->max_prims_per_subgroup <= max_out_prims);
741 }
742
743 static void si_emit_shader_gs(struct si_context *sctx)
744 {
745 struct si_shader *shader = sctx->queued.named.gs->shader;
746 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
747
748 if (!shader)
749 return;
750
751 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
752 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
753 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
754 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
755 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
756 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
757 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
758
759 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
760 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
761 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
762 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
763
764 /* R_028B38_VGT_GS_MAX_VERT_OUT */
765 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
766 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
767 shader->ctx_reg.gs.vgt_gs_max_vert_out);
768
769 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
770 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
771 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
772 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
773 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
774 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
775 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
776 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
777
778 /* R_028B90_VGT_GS_INSTANCE_CNT */
779 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
780 SI_TRACKED_VGT_GS_INSTANCE_CNT,
781 shader->ctx_reg.gs.vgt_gs_instance_cnt);
782
783 if (sctx->chip_class >= GFX9) {
784 /* R_028A44_VGT_GS_ONCHIP_CNTL */
785 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
786 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
787 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
788 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
789 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
790 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
791 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
792 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
793 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
794 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
795 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
796
797 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
798 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
799 SI_TRACKED_VGT_TF_PARAM,
800 shader->vgt_tf_param);
801 if (shader->vgt_vertex_reuse_block_cntl)
802 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
803 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
804 shader->vgt_vertex_reuse_block_cntl);
805 }
806
807 if (initial_cdw != sctx->gfx_cs->current.cdw)
808 sctx->context_roll = true;
809 }
810
811 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
812 {
813 struct si_shader_selector *sel = shader->selector;
814 const ubyte *num_components = sel->info.num_stream_output_components;
815 unsigned gs_num_invocations = sel->gs_num_invocations;
816 struct si_pm4_state *pm4;
817 uint64_t va;
818 unsigned max_stream = sel->max_gs_stream;
819 unsigned offset;
820
821 pm4 = si_get_shader_pm4_state(shader);
822 if (!pm4)
823 return;
824
825 pm4->atom.emit = si_emit_shader_gs;
826
827 offset = num_components[0] * sel->gs_max_out_vertices;
828 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
829
830 if (max_stream >= 1)
831 offset += num_components[1] * sel->gs_max_out_vertices;
832 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
833
834 if (max_stream >= 2)
835 offset += num_components[2] * sel->gs_max_out_vertices;
836 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
837
838 if (max_stream >= 3)
839 offset += num_components[3] * sel->gs_max_out_vertices;
840 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
841
842 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
843 assert(offset < (1 << 15));
844
845 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
846
847 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
848 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
849 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
850 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
851
852 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
853 S_028B90_ENABLE(gs_num_invocations > 0);
854
855 va = shader->bo->gpu_address;
856 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
857
858 if (sscreen->info.chip_class >= GFX9) {
859 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
860 unsigned es_type = shader->key.part.gs.es->type;
861 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
862
863 if (es_type == PIPE_SHADER_VERTEX)
864 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
865 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
866 else if (es_type == PIPE_SHADER_TESS_EVAL)
867 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
868 else
869 unreachable("invalid shader selector type");
870
871 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
872 * VGPR[0:4] are always loaded.
873 */
874 if (sel->info.uses_invocationid)
875 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
876 else if (sel->info.uses_primid)
877 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
878 else if (input_prim >= PIPE_PRIM_TRIANGLES)
879 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
880 else
881 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
882
883 unsigned num_user_sgprs;
884 if (es_type == PIPE_SHADER_VERTEX)
885 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
886 else
887 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
888
889 if (sscreen->info.chip_class >= GFX10) {
890 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
891 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
892 } else {
893 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
894 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
895 }
896
897 uint32_t rsrc1 =
898 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
899 S_00B228_DX10_CLAMP(1) |
900 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
901 S_00B228_FLOAT_MODE(shader->config.float_mode) |
902 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
903 uint32_t rsrc2 =
904 S_00B22C_USER_SGPR(num_user_sgprs) |
905 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
906 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
907 S_00B22C_LDS_SIZE(shader->config.lds_size) |
908 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
909
910 if (sscreen->info.chip_class >= GFX10) {
911 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
912 } else {
913 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
914 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
915 }
916
917 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
918 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
919
920 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
921 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
922 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
923 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
924 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
925 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
926 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
927 shader->key.part.gs.es->esgs_itemsize / 4;
928
929 if (es_type == PIPE_SHADER_TESS_EVAL)
930 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
931
932 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
933 NULL, pm4);
934 } else {
935 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
936 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
937
938 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
939 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
940 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
941 S_00B228_DX10_CLAMP(1) |
942 S_00B228_FLOAT_MODE(shader->config.float_mode));
943 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
944 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
945 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
946 }
947 }
948
949 /* Common tail code for NGG primitive shaders. */
950 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
951 struct si_shader *shader,
952 unsigned initial_cdw)
953 {
954 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
955 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
956 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
957 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
958 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
959 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
960 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
961 SI_TRACKED_VGT_PRIMITIVEID_EN,
962 shader->ctx_reg.ngg.vgt_primitiveid_en);
963 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
964 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
965 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
966 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
967 SI_TRACKED_VGT_GS_INSTANCE_CNT,
968 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
969 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
970 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
971 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
972 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
973 SI_TRACKED_VGT_REUSE_OFF,
974 shader->ctx_reg.ngg.vgt_reuse_off);
975 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
976 SI_TRACKED_SPI_VS_OUT_CONFIG,
977 shader->ctx_reg.ngg.spi_vs_out_config);
978 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
979 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
980 shader->ctx_reg.ngg.spi_shader_idx_format,
981 shader->ctx_reg.ngg.spi_shader_pos_format);
982 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
983 SI_TRACKED_PA_CL_VTE_CNTL,
984 shader->ctx_reg.ngg.pa_cl_vte_cntl);
985 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
986 SI_TRACKED_PA_CL_NGG_CNTL,
987 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
988
989 if (initial_cdw != sctx->gfx_cs->current.cdw)
990 sctx->context_roll = true;
991
992 if (shader->ge_cntl != sctx->last_multi_vgt_param) {
993 radeon_set_uconfig_reg(sctx->gfx_cs, R_03096C_GE_CNTL, shader->ge_cntl);
994 sctx->last_multi_vgt_param = shader->ge_cntl;
995 }
996 }
997
998 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
999 {
1000 struct si_shader *shader = sctx->queued.named.gs->shader;
1001 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1002
1003 if (!shader)
1004 return;
1005
1006 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1007 }
1008
1009 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1010 {
1011 struct si_shader *shader = sctx->queued.named.gs->shader;
1012 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1013
1014 if (!shader)
1015 return;
1016
1017 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1018 SI_TRACKED_VGT_TF_PARAM,
1019 shader->vgt_tf_param);
1020
1021 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1022 }
1023
1024 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1025 {
1026 struct si_shader *shader = sctx->queued.named.gs->shader;
1027 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1028
1029 if (!shader)
1030 return;
1031
1032 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1033 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1034 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1035
1036 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1037 }
1038
1039 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1040 {
1041 struct si_shader *shader = sctx->queued.named.gs->shader;
1042 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1043
1044 if (!shader)
1045 return;
1046
1047 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1048 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1049 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1050 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1051 SI_TRACKED_VGT_TF_PARAM,
1052 shader->vgt_tf_param);
1053
1054 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1055 }
1056
1057 static void si_set_ge_pc_alloc(struct si_screen *sscreen,
1058 struct si_pm4_state *pm4, bool culling)
1059 {
1060 si_pm4_set_reg(pm4, R_030980_GE_PC_ALLOC,
1061 S_030980_OVERSUB_EN(1) |
1062 S_030980_NUM_PC_LINES((culling ? 256 : 128) * sscreen->info.max_se - 1));
1063 }
1064
1065 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1066 {
1067 if (gs->type == PIPE_SHADER_GEOMETRY)
1068 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1069
1070 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1071 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1072 return PIPE_PRIM_POINTS;
1073 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1074 return PIPE_PRIM_LINES;
1075 return PIPE_PRIM_TRIANGLES;
1076 }
1077
1078 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1079 return PIPE_PRIM_TRIANGLES;
1080 }
1081
1082 /**
1083 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1084 * in NGG mode.
1085 */
1086 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1087 {
1088 const struct si_shader_selector *gs_sel = shader->selector;
1089 const struct tgsi_shader_info *gs_info = &gs_sel->info;
1090 enum pipe_shader_type gs_type = shader->selector->type;
1091 const struct si_shader_selector *es_sel =
1092 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1093 const struct tgsi_shader_info *es_info = &es_sel->info;
1094 enum pipe_shader_type es_type = es_sel->type;
1095 unsigned num_user_sgprs;
1096 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1097 uint64_t va;
1098 unsigned window_space =
1099 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1100 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1101 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1102 unsigned input_prim = si_get_input_prim(gs_sel);
1103 bool break_wave_at_eoi = false;
1104 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1105 if (!pm4)
1106 return;
1107
1108 if (es_type == PIPE_SHADER_TESS_EVAL) {
1109 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1110 : gfx10_emit_shader_ngg_tess_nogs;
1111 } else {
1112 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1113 : gfx10_emit_shader_ngg_notess_nogs;
1114 }
1115
1116 va = shader->bo->gpu_address;
1117 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1118
1119 if (es_type == PIPE_SHADER_VERTEX) {
1120 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
1121 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
1122
1123 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1124 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1125 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1126 } else {
1127 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
1128 }
1129 } else {
1130 assert(es_type == PIPE_SHADER_TESS_EVAL);
1131 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1132 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1133
1134 if (es_enable_prim_id || gs_info->uses_primid)
1135 break_wave_at_eoi = true;
1136 }
1137
1138 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1139 * VGPR[0:4] are always loaded.
1140 *
1141 * Vertex shaders always need to load VGPR3, because they need to
1142 * pass edge flags for decomposed primitives (such as quads) to the PA
1143 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1144 */
1145 if (gs_info->uses_invocationid || gs_type == PIPE_SHADER_VERTEX)
1146 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1147 else if (gs_info->uses_primid)
1148 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1149 else if (input_prim >= PIPE_PRIM_TRIANGLES)
1150 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1151 else
1152 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1153
1154 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1155 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1156 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1157 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
1158 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1159 S_00B228_DX10_CLAMP(1) |
1160 S_00B228_MEM_ORDERED(1) |
1161 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1162 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1163 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1164 S_00B22C_USER_SGPR(num_user_sgprs) |
1165 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1166 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1167 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1168 S_00B22C_LDS_SIZE(shader->config.lds_size));
1169 si_set_ge_pc_alloc(sscreen, pm4, false);
1170
1171 nparams = MAX2(shader->info.nr_param_exports, 1);
1172 shader->ctx_reg.ngg.spi_vs_out_config =
1173 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1174 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1175
1176 shader->ctx_reg.ngg.spi_shader_idx_format =
1177 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1178 shader->ctx_reg.ngg.spi_shader_pos_format =
1179 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1180 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1181 V_02870C_SPI_SHADER_4COMP :
1182 V_02870C_SPI_SHADER_NONE) |
1183 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1184 V_02870C_SPI_SHADER_4COMP :
1185 V_02870C_SPI_SHADER_NONE) |
1186 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1187 V_02870C_SPI_SHADER_4COMP :
1188 V_02870C_SPI_SHADER_NONE);
1189
1190 shader->ctx_reg.ngg.vgt_primitiveid_en =
1191 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1192 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id);
1193
1194 if (gs_type == PIPE_SHADER_GEOMETRY) {
1195 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1196 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1197 } else {
1198 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1199 }
1200
1201 if (es_type == PIPE_SHADER_TESS_EVAL)
1202 si_set_tesseval_regs(sscreen, es_sel, pm4);
1203
1204 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1205 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1206 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1207 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1208 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1209 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1210 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1211 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1212 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1213 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1214 S_028B90_CNT(gs_num_invocations) |
1215 S_028B90_ENABLE(gs_num_invocations > 1) |
1216 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1217 shader->ngg.max_vert_out_per_gs_instance);
1218
1219 /* User edge flags are set by the pos exports. If user edge flags are
1220 * not used, we must use hw-generated edge flags and pass them via
1221 * the prim export to prevent drawing lines on internal edges of
1222 * decomposed primitives (such as quads) with polygon mode = lines.
1223 *
1224 * TODO: We should combine hw-generated edge flags with user edge
1225 * flags in the shader.
1226 */
1227 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1228 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX &&
1229 !gs_info->writes_edgeflag);
1230
1231 shader->ge_cntl =
1232 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1233 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts) |
1234 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1235
1236 if (window_space) {
1237 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1238 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1239 } else {
1240 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1241 S_028818_VTX_W0_FMT(1) |
1242 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1243 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1244 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1245 }
1246
1247 shader->ctx_reg.ngg.vgt_reuse_off =
1248 S_028AB4_REUSE_OFF(sscreen->info.family == CHIP_NAVI10 &&
1249 sscreen->info.chip_external_rev == 0x1 &&
1250 es_type == PIPE_SHADER_TESS_EVAL);
1251 }
1252
1253 static void si_emit_shader_vs(struct si_context *sctx)
1254 {
1255 struct si_shader *shader = sctx->queued.named.vs->shader;
1256 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1257
1258 if (!shader)
1259 return;
1260
1261 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1262 SI_TRACKED_VGT_GS_MODE,
1263 shader->ctx_reg.vs.vgt_gs_mode);
1264 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1265 SI_TRACKED_VGT_PRIMITIVEID_EN,
1266 shader->ctx_reg.vs.vgt_primitiveid_en);
1267
1268 if (sctx->chip_class <= GFX8) {
1269 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1270 SI_TRACKED_VGT_REUSE_OFF,
1271 shader->ctx_reg.vs.vgt_reuse_off);
1272 }
1273
1274 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1275 SI_TRACKED_SPI_VS_OUT_CONFIG,
1276 shader->ctx_reg.vs.spi_vs_out_config);
1277
1278 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1279 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1280 shader->ctx_reg.vs.spi_shader_pos_format);
1281
1282 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1283 SI_TRACKED_PA_CL_VTE_CNTL,
1284 shader->ctx_reg.vs.pa_cl_vte_cntl);
1285
1286 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1287 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1288 SI_TRACKED_VGT_TF_PARAM,
1289 shader->vgt_tf_param);
1290
1291 if (shader->vgt_vertex_reuse_block_cntl)
1292 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1293 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1294 shader->vgt_vertex_reuse_block_cntl);
1295
1296 if (initial_cdw != sctx->gfx_cs->current.cdw)
1297 sctx->context_roll = true;
1298 }
1299
1300 /**
1301 * Compute the state for \p shader, which will run as a vertex shader on the
1302 * hardware.
1303 *
1304 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1305 * is the copy shader.
1306 */
1307 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1308 struct si_shader_selector *gs)
1309 {
1310 const struct tgsi_shader_info *info = &shader->selector->info;
1311 struct si_pm4_state *pm4;
1312 unsigned num_user_sgprs, vgpr_comp_cnt;
1313 uint64_t va;
1314 unsigned nparams, oc_lds_en;
1315 unsigned window_space =
1316 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1317 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1318
1319 pm4 = si_get_shader_pm4_state(shader);
1320 if (!pm4)
1321 return;
1322
1323 pm4->atom.emit = si_emit_shader_vs;
1324
1325 /* We always write VGT_GS_MODE in the VS state, because every switch
1326 * between different shader pipelines involving a different GS or no
1327 * GS at all involves a switch of the VS (different GS use different
1328 * copy shaders). On the other hand, when the API switches from a GS to
1329 * no GS and then back to the same GS used originally, the GS state is
1330 * not sent again.
1331 */
1332 if (!gs) {
1333 unsigned mode = V_028A40_GS_OFF;
1334
1335 /* PrimID needs GS scenario A. */
1336 if (enable_prim_id)
1337 mode = V_028A40_GS_SCENARIO_A;
1338
1339 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1340 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1341 } else {
1342 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1343 sscreen->info.chip_class);
1344 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1345 }
1346
1347 if (sscreen->info.chip_class <= GFX8) {
1348 /* Reuse needs to be set off if we write oViewport. */
1349 shader->ctx_reg.vs.vgt_reuse_off =
1350 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1351 }
1352
1353 va = shader->bo->gpu_address;
1354 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1355
1356 if (gs) {
1357 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1358 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1359 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1360 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1361 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1362 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1363 */
1364 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
1365
1366 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1367 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1368 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1369 } else {
1370 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1371 }
1372 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1373 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1374 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1375 } else
1376 unreachable("invalid shader selector type");
1377
1378 /* VS is required to export at least one param. */
1379 nparams = MAX2(shader->info.nr_param_exports, 1);
1380 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1381
1382 if (sscreen->info.chip_class >= GFX10) {
1383 shader->ctx_reg.vs.spi_vs_out_config |=
1384 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1385 }
1386
1387 shader->ctx_reg.vs.spi_shader_pos_format =
1388 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1389 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1390 V_02870C_SPI_SHADER_4COMP :
1391 V_02870C_SPI_SHADER_NONE) |
1392 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1393 V_02870C_SPI_SHADER_4COMP :
1394 V_02870C_SPI_SHADER_NONE) |
1395 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1396 V_02870C_SPI_SHADER_4COMP :
1397 V_02870C_SPI_SHADER_NONE);
1398
1399 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1400
1401 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1402 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1403 if (sscreen->info.chip_class >= GFX10)
1404 si_set_ge_pc_alloc(sscreen, pm4, false);
1405
1406 uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
1407 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1408 S_00B128_DX10_CLAMP(1) |
1409 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1410 S_00B128_FLOAT_MODE(shader->config.float_mode);
1411 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
1412 S_00B12C_OC_LDS_EN(oc_lds_en) |
1413 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1414
1415 if (sscreen->info.chip_class <= GFX9) {
1416 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1417 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1418 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1419 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1420 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1421 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1422 }
1423
1424 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1425 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1426
1427 if (window_space)
1428 shader->ctx_reg.vs.pa_cl_vte_cntl =
1429 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1430 else
1431 shader->ctx_reg.vs.pa_cl_vte_cntl =
1432 S_028818_VTX_W0_FMT(1) |
1433 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1434 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1435 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1436
1437 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1438 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1439
1440 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1441 }
1442
1443 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1444 {
1445 struct tgsi_shader_info *info = &ps->selector->info;
1446 unsigned num_colors = !!(info->colors_read & 0x0f) +
1447 !!(info->colors_read & 0xf0);
1448 unsigned num_interp = ps->selector->info.num_inputs +
1449 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1450
1451 assert(num_interp <= 32);
1452 return MIN2(num_interp, 32);
1453 }
1454
1455 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1456 {
1457 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1458 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1459
1460 /* If the i-th target format is set, all previous target formats must
1461 * be non-zero to avoid hangs.
1462 */
1463 for (i = 0; i < num_targets; i++)
1464 if (!(value & (0xf << (i * 4))))
1465 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1466
1467 return value;
1468 }
1469
1470 static void si_emit_shader_ps(struct si_context *sctx)
1471 {
1472 struct si_shader *shader = sctx->queued.named.ps->shader;
1473 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1474
1475 if (!shader)
1476 return;
1477
1478 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1479 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1480 SI_TRACKED_SPI_PS_INPUT_ENA,
1481 shader->ctx_reg.ps.spi_ps_input_ena,
1482 shader->ctx_reg.ps.spi_ps_input_addr);
1483
1484 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1485 SI_TRACKED_SPI_BARYC_CNTL,
1486 shader->ctx_reg.ps.spi_baryc_cntl);
1487 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1488 SI_TRACKED_SPI_PS_IN_CONTROL,
1489 shader->ctx_reg.ps.spi_ps_in_control);
1490
1491 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1492 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1493 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1494 shader->ctx_reg.ps.spi_shader_z_format,
1495 shader->ctx_reg.ps.spi_shader_col_format);
1496
1497 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1498 SI_TRACKED_CB_SHADER_MASK,
1499 shader->ctx_reg.ps.cb_shader_mask);
1500
1501 if (initial_cdw != sctx->gfx_cs->current.cdw)
1502 sctx->context_roll = true;
1503 }
1504
1505 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1506 {
1507 struct tgsi_shader_info *info = &shader->selector->info;
1508 struct si_pm4_state *pm4;
1509 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1510 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1511 uint64_t va;
1512 unsigned input_ena = shader->config.spi_ps_input_ena;
1513
1514 /* we need to enable at least one of them, otherwise we hang the GPU */
1515 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1516 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1517 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1518 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1519 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1520 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1521 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1522 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1523 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1524 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1525 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1526 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1527 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1528 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1529
1530 /* Validate interpolation optimization flags (read as implications). */
1531 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1532 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1533 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1534 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1535 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1536 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1537 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1538 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1539 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1540 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1541 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1542 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1543 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1544 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1545 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1546 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1547 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1548 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1549
1550 /* Validate cases when the optimizations are off (read as implications). */
1551 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1552 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1553 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1554 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1555 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1556 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1557
1558 pm4 = si_get_shader_pm4_state(shader);
1559 if (!pm4)
1560 return;
1561
1562 pm4->atom.emit = si_emit_shader_ps;
1563
1564 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1565 * Possible vaules:
1566 * 0 -> Position = pixel center
1567 * 1 -> Position = pixel centroid
1568 * 2 -> Position = at sample position
1569 *
1570 * From GLSL 4.5 specification, section 7.1:
1571 * "The variable gl_FragCoord is available as an input variable from
1572 * within fragment shaders and it holds the window relative coordinates
1573 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1574 * value can be for any location within the pixel, or one of the
1575 * fragment samples. The use of centroid does not further restrict
1576 * this value to be inside the current primitive."
1577 *
1578 * Meaning that centroid has no effect and we can return anything within
1579 * the pixel. Thus, return the value at sample position, because that's
1580 * the most accurate one shaders can get.
1581 */
1582 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1583
1584 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1585 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1586 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1587
1588 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1589 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1590
1591 /* Ensure that some export memory is always allocated, for two reasons:
1592 *
1593 * 1) Correctness: The hardware ignores the EXEC mask if no export
1594 * memory is allocated, so KILL and alpha test do not work correctly
1595 * without this.
1596 * 2) Performance: Every shader needs at least a NULL export, even when
1597 * it writes no color/depth output. The NULL export instruction
1598 * stalls without this setting.
1599 *
1600 * Don't add this to CB_SHADER_MASK.
1601 *
1602 * GFX10 supports pixel shaders without exports by setting both
1603 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1604 * instructions if any are present.
1605 */
1606 if ((sscreen->info.chip_class <= GFX9 ||
1607 info->uses_kill ||
1608 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1609 !spi_shader_col_format &&
1610 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1611 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1612
1613 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1614 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1615
1616 /* Set interpolation controls. */
1617 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1618
1619 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1620 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1621 shader->ctx_reg.ps.spi_shader_z_format =
1622 ac_get_spi_shader_z_format(info->writes_z,
1623 info->writes_stencil,
1624 info->writes_samplemask);
1625 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1626 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1627
1628 va = shader->bo->gpu_address;
1629 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1630 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1631 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1632
1633 uint32_t rsrc1 =
1634 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1635 S_00B028_DX10_CLAMP(1) |
1636 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1637 S_00B028_FLOAT_MODE(shader->config.float_mode);
1638
1639 if (sscreen->info.chip_class < GFX10) {
1640 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1641 }
1642
1643 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1644 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1645 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1646 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1647 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1648 }
1649
1650 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1651 struct si_shader *shader)
1652 {
1653 switch (shader->selector->type) {
1654 case PIPE_SHADER_VERTEX:
1655 if (shader->key.as_ls)
1656 si_shader_ls(sscreen, shader);
1657 else if (shader->key.as_es)
1658 si_shader_es(sscreen, shader);
1659 else if (shader->key.as_ngg)
1660 gfx10_shader_ngg(sscreen, shader);
1661 else
1662 si_shader_vs(sscreen, shader, NULL);
1663 break;
1664 case PIPE_SHADER_TESS_CTRL:
1665 si_shader_hs(sscreen, shader);
1666 break;
1667 case PIPE_SHADER_TESS_EVAL:
1668 if (shader->key.as_es)
1669 si_shader_es(sscreen, shader);
1670 else if (shader->key.as_ngg)
1671 gfx10_shader_ngg(sscreen, shader);
1672 else
1673 si_shader_vs(sscreen, shader, NULL);
1674 break;
1675 case PIPE_SHADER_GEOMETRY:
1676 if (shader->key.as_ngg)
1677 gfx10_shader_ngg(sscreen, shader);
1678 else
1679 si_shader_gs(sscreen, shader);
1680 break;
1681 case PIPE_SHADER_FRAGMENT:
1682 si_shader_ps(sscreen, shader);
1683 break;
1684 default:
1685 assert(0);
1686 }
1687 }
1688
1689 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1690 {
1691 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1692 if (sctx->queued.named.dsa)
1693 return sctx->queued.named.dsa->alpha_func;
1694
1695 return PIPE_FUNC_ALWAYS;
1696 }
1697
1698 void si_shader_selector_key_vs(struct si_context *sctx,
1699 struct si_shader_selector *vs,
1700 struct si_shader_key *key,
1701 struct si_vs_prolog_bits *prolog_key)
1702 {
1703 if (!sctx->vertex_elements ||
1704 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS])
1705 return;
1706
1707 struct si_vertex_elements *elts = sctx->vertex_elements;
1708
1709 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1710 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1711 prolog_key->unpack_instance_id_from_vertex_id =
1712 sctx->prim_discard_cs_instancing;
1713
1714 /* Prefer a monolithic shader to allow scheduling divisions around
1715 * VBO loads. */
1716 if (prolog_key->instance_divisor_is_fetched)
1717 key->opt.prefer_mono = 1;
1718
1719 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1720 unsigned count_mask = (1 << count) - 1;
1721 unsigned fix = elts->fix_fetch_always & count_mask;
1722 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1723
1724 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1725 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1726 while (mask) {
1727 unsigned i = u_bit_scan(&mask);
1728 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1729 unsigned vbidx = elts->vertex_buffer_index[i];
1730 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1731 unsigned align_mask = (1 << log_hw_load_size) - 1;
1732 if (vb->buffer_offset & align_mask ||
1733 vb->stride & align_mask) {
1734 fix |= 1 << i;
1735 opencode |= 1 << i;
1736 }
1737 }
1738 }
1739
1740 while (fix) {
1741 unsigned i = u_bit_scan(&fix);
1742 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1743 }
1744 key->mono.vs_fetch_opencode = opencode;
1745 }
1746
1747 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1748 struct si_shader_selector *vs,
1749 struct si_shader_key *key)
1750 {
1751 struct si_shader_selector *ps = sctx->ps_shader.cso;
1752
1753 key->opt.clip_disable =
1754 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1755 (vs->info.clipdist_writemask ||
1756 vs->info.writes_clipvertex) &&
1757 !vs->info.culldist_writemask;
1758
1759 /* Find out if PS is disabled. */
1760 bool ps_disabled = true;
1761 if (ps) {
1762 const struct si_state_blend *blend = sctx->queued.named.blend;
1763 bool alpha_to_coverage = blend && blend->alpha_to_coverage;
1764 bool ps_modifies_zs = ps->info.uses_kill ||
1765 ps->info.writes_z ||
1766 ps->info.writes_stencil ||
1767 ps->info.writes_samplemask ||
1768 alpha_to_coverage ||
1769 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1770 unsigned ps_colormask = si_get_total_colormask(sctx);
1771
1772 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1773 (!ps_colormask &&
1774 !ps_modifies_zs &&
1775 !ps->info.writes_memory);
1776 }
1777
1778 /* Find out which VS outputs aren't used by the PS. */
1779 uint64_t outputs_written = vs->outputs_written_before_ps;
1780 uint64_t inputs_read = 0;
1781
1782 /* Ignore outputs that are not passed from VS to PS. */
1783 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1784 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1785 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1786
1787 if (!ps_disabled) {
1788 inputs_read = ps->inputs_read;
1789 }
1790
1791 uint64_t linked = outputs_written & inputs_read;
1792
1793 key->opt.kill_outputs = ~linked & outputs_written;
1794 }
1795
1796 /* Compute the key for the hw shader variant */
1797 static inline void si_shader_selector_key(struct pipe_context *ctx,
1798 struct si_shader_selector *sel,
1799 union si_vgt_stages_key stages_key,
1800 struct si_shader_key *key)
1801 {
1802 struct si_context *sctx = (struct si_context *)ctx;
1803
1804 memset(key, 0, sizeof(*key));
1805
1806 switch (sel->type) {
1807 case PIPE_SHADER_VERTEX:
1808 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1809
1810 if (sctx->tes_shader.cso)
1811 key->as_ls = 1;
1812 else if (sctx->gs_shader.cso)
1813 key->as_es = 1;
1814 else {
1815 key->as_ngg = stages_key.u.ngg;
1816 si_shader_selector_key_hw_vs(sctx, sel, key);
1817
1818 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1819 key->mono.u.vs_export_prim_id = 1;
1820 }
1821 break;
1822 case PIPE_SHADER_TESS_CTRL:
1823 if (sctx->chip_class >= GFX9) {
1824 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1825 key, &key->part.tcs.ls_prolog);
1826 key->part.tcs.ls = sctx->vs_shader.cso;
1827
1828 /* When the LS VGPR fix is needed, monolithic shaders
1829 * can:
1830 * - avoid initializing EXEC in both the LS prolog
1831 * and the LS main part when !vs_needs_prolog
1832 * - remove the fixup for unused input VGPRs
1833 */
1834 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1835
1836 /* The LS output / HS input layout can be communicated
1837 * directly instead of via user SGPRs for merged LS-HS.
1838 * The LS VGPR fix prefers this too.
1839 */
1840 key->opt.prefer_mono = 1;
1841 }
1842
1843 key->part.tcs.epilog.prim_mode =
1844 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1845 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1846 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1847 key->part.tcs.epilog.tes_reads_tess_factors =
1848 sctx->tes_shader.cso->info.reads_tess_factors;
1849
1850 if (sel == sctx->fixed_func_tcs_shader.cso)
1851 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1852 break;
1853 case PIPE_SHADER_TESS_EVAL:
1854 if (sctx->gs_shader.cso)
1855 key->as_es = 1;
1856 else {
1857 key->as_ngg = stages_key.u.ngg;
1858 si_shader_selector_key_hw_vs(sctx, sel, key);
1859
1860 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1861 key->mono.u.vs_export_prim_id = 1;
1862 }
1863 break;
1864 case PIPE_SHADER_GEOMETRY:
1865 if (sctx->chip_class >= GFX9) {
1866 if (sctx->tes_shader.cso) {
1867 key->part.gs.es = sctx->tes_shader.cso;
1868 } else {
1869 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1870 key, &key->part.gs.vs_prolog);
1871 key->part.gs.es = sctx->vs_shader.cso;
1872 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1873 }
1874
1875 key->as_ngg = stages_key.u.ngg;
1876
1877 /* Merged ES-GS can have unbalanced wave usage.
1878 *
1879 * ES threads are per-vertex, while GS threads are
1880 * per-primitive. So without any amplification, there
1881 * are fewer GS threads than ES threads, which can result
1882 * in empty (no-op) GS waves. With too much amplification,
1883 * there are more GS threads than ES threads, which
1884 * can result in empty (no-op) ES waves.
1885 *
1886 * Non-monolithic shaders are implemented by setting EXEC
1887 * at the beginning of shader parts, and don't jump to
1888 * the end if EXEC is 0.
1889 *
1890 * Monolithic shaders use conditional blocks, so they can
1891 * jump and skip empty waves of ES or GS. So set this to
1892 * always use optimized variants, which are monolithic.
1893 */
1894 key->opt.prefer_mono = 1;
1895 }
1896 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1897 break;
1898 case PIPE_SHADER_FRAGMENT: {
1899 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1900 struct si_state_blend *blend = sctx->queued.named.blend;
1901
1902 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1903 sel->info.colors_written == 0x1)
1904 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1905
1906 if (blend) {
1907 /* Select the shader color format based on whether
1908 * blending or alpha are needed.
1909 */
1910 key->part.ps.epilog.spi_shader_col_format =
1911 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1912 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1913 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1914 sctx->framebuffer.spi_shader_col_format_blend) |
1915 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1916 sctx->framebuffer.spi_shader_col_format_alpha) |
1917 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1918 sctx->framebuffer.spi_shader_col_format);
1919 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1920
1921 /* The output for dual source blending should have
1922 * the same format as the first output.
1923 */
1924 if (blend->dual_src_blend)
1925 key->part.ps.epilog.spi_shader_col_format |=
1926 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1927 } else
1928 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1929
1930 /* If alpha-to-coverage is enabled, we have to export alpha
1931 * even if there is no color buffer.
1932 */
1933 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1934 blend && blend->alpha_to_coverage)
1935 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1936
1937 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1938 * to the range supported by the type if a channel has less
1939 * than 16 bits and the export format is 16_ABGR.
1940 */
1941 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1942 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1943 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1944 }
1945
1946 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1947 if (!key->part.ps.epilog.last_cbuf) {
1948 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1949 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1950 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1951 }
1952
1953 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1954 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1955
1956 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1957 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1958
1959 if (sctx->queued.named.blend) {
1960 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1961 rs->multisample_enable;
1962 }
1963
1964 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1965 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1966 (is_line && rs->line_smooth)) &&
1967 sctx->framebuffer.nr_samples <= 1;
1968 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1969
1970 if (sctx->ps_iter_samples > 1 &&
1971 sel->info.reads_samplemask) {
1972 key->part.ps.prolog.samplemask_log_ps_iter =
1973 util_logbase2(sctx->ps_iter_samples);
1974 }
1975
1976 if (rs->force_persample_interp &&
1977 rs->multisample_enable &&
1978 sctx->framebuffer.nr_samples > 1 &&
1979 sctx->ps_iter_samples > 1) {
1980 key->part.ps.prolog.force_persp_sample_interp =
1981 sel->info.uses_persp_center ||
1982 sel->info.uses_persp_centroid;
1983
1984 key->part.ps.prolog.force_linear_sample_interp =
1985 sel->info.uses_linear_center ||
1986 sel->info.uses_linear_centroid;
1987 } else if (rs->multisample_enable &&
1988 sctx->framebuffer.nr_samples > 1) {
1989 key->part.ps.prolog.bc_optimize_for_persp =
1990 sel->info.uses_persp_center &&
1991 sel->info.uses_persp_centroid;
1992 key->part.ps.prolog.bc_optimize_for_linear =
1993 sel->info.uses_linear_center &&
1994 sel->info.uses_linear_centroid;
1995 } else {
1996 /* Make sure SPI doesn't compute more than 1 pair
1997 * of (i,j), which is the optimization here. */
1998 key->part.ps.prolog.force_persp_center_interp =
1999 sel->info.uses_persp_center +
2000 sel->info.uses_persp_centroid +
2001 sel->info.uses_persp_sample > 1;
2002
2003 key->part.ps.prolog.force_linear_center_interp =
2004 sel->info.uses_linear_center +
2005 sel->info.uses_linear_centroid +
2006 sel->info.uses_linear_sample > 1;
2007
2008 if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
2009 key->mono.u.ps.interpolate_at_sample_force_center = 1;
2010 }
2011
2012 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
2013
2014 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2015 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
2016 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2017 struct pipe_resource *tex = cb0->texture;
2018
2019 /* 1D textures are allocated and used as 2D on GFX9. */
2020 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2021 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
2022 (tex->target == PIPE_TEXTURE_1D ||
2023 tex->target == PIPE_TEXTURE_1D_ARRAY);
2024 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
2025 tex->target == PIPE_TEXTURE_2D_ARRAY ||
2026 tex->target == PIPE_TEXTURE_CUBE ||
2027 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2028 tex->target == PIPE_TEXTURE_3D;
2029 }
2030 break;
2031 }
2032 default:
2033 assert(0);
2034 }
2035
2036 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2037 memset(&key->opt, 0, sizeof(key->opt));
2038 }
2039
2040 static void si_build_shader_variant(struct si_shader *shader,
2041 int thread_index,
2042 bool low_priority)
2043 {
2044 struct si_shader_selector *sel = shader->selector;
2045 struct si_screen *sscreen = sel->screen;
2046 struct ac_llvm_compiler *compiler;
2047 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2048
2049 if (thread_index >= 0) {
2050 if (low_priority) {
2051 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2052 compiler = &sscreen->compiler_lowp[thread_index];
2053 } else {
2054 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2055 compiler = &sscreen->compiler[thread_index];
2056 }
2057 if (!debug->async)
2058 debug = NULL;
2059 } else {
2060 assert(!low_priority);
2061 compiler = shader->compiler_ctx_state.compiler;
2062 }
2063
2064 if (unlikely(!si_shader_create(sscreen, compiler, shader, debug))) {
2065 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2066 sel->type);
2067 shader->compilation_failed = true;
2068 return;
2069 }
2070
2071 if (shader->compiler_ctx_state.is_debug_context) {
2072 FILE *f = open_memstream(&shader->shader_log,
2073 &shader->shader_log_size);
2074 if (f) {
2075 si_shader_dump(sscreen, shader, NULL, f, false);
2076 fclose(f);
2077 }
2078 }
2079
2080 si_shader_init_pm4_state(sscreen, shader);
2081 }
2082
2083 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2084 {
2085 struct si_shader *shader = (struct si_shader *)job;
2086
2087 assert(thread_index >= 0);
2088
2089 si_build_shader_variant(shader, thread_index, true);
2090 }
2091
2092 static const struct si_shader_key zeroed;
2093
2094 static bool si_check_missing_main_part(struct si_screen *sscreen,
2095 struct si_shader_selector *sel,
2096 struct si_compiler_ctx_state *compiler_state,
2097 struct si_shader_key *key)
2098 {
2099 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2100
2101 if (!*mainp) {
2102 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2103
2104 if (!main_part)
2105 return false;
2106
2107 /* We can leave the fence as permanently signaled because the
2108 * main part becomes visible globally only after it has been
2109 * compiled. */
2110 util_queue_fence_init(&main_part->ready);
2111
2112 main_part->selector = sel;
2113 main_part->key.as_es = key->as_es;
2114 main_part->key.as_ls = key->as_ls;
2115 main_part->key.as_ngg = key->as_ngg;
2116 main_part->is_monolithic = false;
2117
2118 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
2119 main_part, &compiler_state->debug) != 0) {
2120 FREE(main_part);
2121 return false;
2122 }
2123 *mainp = main_part;
2124 }
2125 return true;
2126 }
2127
2128 /**
2129 * Select a shader variant according to the shader key.
2130 *
2131 * \param optimized_or_none If the key describes an optimized shader variant and
2132 * the compilation isn't finished, don't select any
2133 * shader and return an error.
2134 */
2135 int si_shader_select_with_key(struct si_screen *sscreen,
2136 struct si_shader_ctx_state *state,
2137 struct si_compiler_ctx_state *compiler_state,
2138 struct si_shader_key *key,
2139 int thread_index,
2140 bool optimized_or_none)
2141 {
2142 struct si_shader_selector *sel = state->cso;
2143 struct si_shader_selector *previous_stage_sel = NULL;
2144 struct si_shader *current = state->current;
2145 struct si_shader *iter, *shader = NULL;
2146
2147 again:
2148 /* Check if we don't need to change anything.
2149 * This path is also used for most shaders that don't need multiple
2150 * variants, it will cost just a computation of the key and this
2151 * test. */
2152 if (likely(current &&
2153 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2154 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2155 if (current->is_optimized) {
2156 if (optimized_or_none)
2157 return -1;
2158
2159 memset(&key->opt, 0, sizeof(key->opt));
2160 goto current_not_ready;
2161 }
2162
2163 util_queue_fence_wait(&current->ready);
2164 }
2165
2166 return current->compilation_failed ? -1 : 0;
2167 }
2168 current_not_ready:
2169
2170 /* This must be done before the mutex is locked, because async GS
2171 * compilation calls this function too, and therefore must enter
2172 * the mutex first.
2173 *
2174 * Only wait if we are in a draw call. Don't wait if we are
2175 * in a compiler thread.
2176 */
2177 if (thread_index < 0)
2178 util_queue_fence_wait(&sel->ready);
2179
2180 mtx_lock(&sel->mutex);
2181
2182 /* Find the shader variant. */
2183 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2184 /* Don't check the "current" shader. We checked it above. */
2185 if (current != iter &&
2186 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2187 mtx_unlock(&sel->mutex);
2188
2189 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2190 /* If it's an optimized shader and its compilation has
2191 * been started but isn't done, use the unoptimized
2192 * shader so as not to cause a stall due to compilation.
2193 */
2194 if (iter->is_optimized) {
2195 if (optimized_or_none)
2196 return -1;
2197 memset(&key->opt, 0, sizeof(key->opt));
2198 goto again;
2199 }
2200
2201 util_queue_fence_wait(&iter->ready);
2202 }
2203
2204 if (iter->compilation_failed) {
2205 return -1; /* skip the draw call */
2206 }
2207
2208 state->current = iter;
2209 return 0;
2210 }
2211 }
2212
2213 /* Build a new shader. */
2214 shader = CALLOC_STRUCT(si_shader);
2215 if (!shader) {
2216 mtx_unlock(&sel->mutex);
2217 return -ENOMEM;
2218 }
2219
2220 util_queue_fence_init(&shader->ready);
2221
2222 shader->selector = sel;
2223 shader->key = *key;
2224 shader->compiler_ctx_state = *compiler_state;
2225
2226 /* If this is a merged shader, get the first shader's selector. */
2227 if (sscreen->info.chip_class >= GFX9) {
2228 if (sel->type == PIPE_SHADER_TESS_CTRL)
2229 previous_stage_sel = key->part.tcs.ls;
2230 else if (sel->type == PIPE_SHADER_GEOMETRY)
2231 previous_stage_sel = key->part.gs.es;
2232
2233 /* We need to wait for the previous shader. */
2234 if (previous_stage_sel && thread_index < 0)
2235 util_queue_fence_wait(&previous_stage_sel->ready);
2236 }
2237
2238 bool is_pure_monolithic =
2239 sscreen->use_monolithic_shaders ||
2240 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2241
2242 /* Compile the main shader part if it doesn't exist. This can happen
2243 * if the initial guess was wrong.
2244 *
2245 * The prim discard CS doesn't need the main shader part.
2246 */
2247 if (!is_pure_monolithic &&
2248 !key->opt.vs_as_prim_discard_cs) {
2249 bool ok = true;
2250
2251 /* Make sure the main shader part is present. This is needed
2252 * for shaders that can be compiled as VS, LS, or ES, and only
2253 * one of them is compiled at creation.
2254 *
2255 * It is also needed for GS, which can be compiled as non-NGG
2256 * and NGG.
2257 *
2258 * For merged shaders, check that the starting shader's main
2259 * part is present.
2260 */
2261 if (previous_stage_sel) {
2262 struct si_shader_key shader1_key = zeroed;
2263
2264 if (sel->type == PIPE_SHADER_TESS_CTRL)
2265 shader1_key.as_ls = 1;
2266 else if (sel->type == PIPE_SHADER_GEOMETRY)
2267 shader1_key.as_es = 1;
2268 else
2269 assert(0);
2270
2271 mtx_lock(&previous_stage_sel->mutex);
2272 ok = si_check_missing_main_part(sscreen,
2273 previous_stage_sel,
2274 compiler_state, &shader1_key);
2275 mtx_unlock(&previous_stage_sel->mutex);
2276 }
2277
2278 if (ok) {
2279 ok = si_check_missing_main_part(sscreen, sel,
2280 compiler_state, key);
2281 }
2282
2283 if (!ok) {
2284 FREE(shader);
2285 mtx_unlock(&sel->mutex);
2286 return -ENOMEM; /* skip the draw call */
2287 }
2288 }
2289
2290 /* Keep the reference to the 1st shader of merged shaders, so that
2291 * Gallium can't destroy it before we destroy the 2nd shader.
2292 *
2293 * Set sctx = NULL, because it's unused if we're not releasing
2294 * the shader, and we don't have any sctx here.
2295 */
2296 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2297 previous_stage_sel);
2298
2299 /* Monolithic-only shaders don't make a distinction between optimized
2300 * and unoptimized. */
2301 shader->is_monolithic =
2302 is_pure_monolithic ||
2303 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2304
2305 /* The prim discard CS is always optimized. */
2306 shader->is_optimized =
2307 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2308 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2309
2310 /* If it's an optimized shader, compile it asynchronously. */
2311 if (shader->is_optimized && thread_index < 0) {
2312 /* Compile it asynchronously. */
2313 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2314 shader, &shader->ready,
2315 si_build_shader_variant_low_priority, NULL);
2316
2317 /* Add only after the ready fence was reset, to guard against a
2318 * race with si_bind_XX_shader. */
2319 if (!sel->last_variant) {
2320 sel->first_variant = shader;
2321 sel->last_variant = shader;
2322 } else {
2323 sel->last_variant->next_variant = shader;
2324 sel->last_variant = shader;
2325 }
2326
2327 /* Use the default (unoptimized) shader for now. */
2328 memset(&key->opt, 0, sizeof(key->opt));
2329 mtx_unlock(&sel->mutex);
2330
2331 if (sscreen->options.sync_compile)
2332 util_queue_fence_wait(&shader->ready);
2333
2334 if (optimized_or_none)
2335 return -1;
2336 goto again;
2337 }
2338
2339 /* Reset the fence before adding to the variant list. */
2340 util_queue_fence_reset(&shader->ready);
2341
2342 if (!sel->last_variant) {
2343 sel->first_variant = shader;
2344 sel->last_variant = shader;
2345 } else {
2346 sel->last_variant->next_variant = shader;
2347 sel->last_variant = shader;
2348 }
2349
2350 mtx_unlock(&sel->mutex);
2351
2352 assert(!shader->is_optimized);
2353 si_build_shader_variant(shader, thread_index, false);
2354
2355 util_queue_fence_signal(&shader->ready);
2356
2357 if (!shader->compilation_failed)
2358 state->current = shader;
2359
2360 return shader->compilation_failed ? -1 : 0;
2361 }
2362
2363 static int si_shader_select(struct pipe_context *ctx,
2364 struct si_shader_ctx_state *state,
2365 union si_vgt_stages_key stages_key,
2366 struct si_compiler_ctx_state *compiler_state)
2367 {
2368 struct si_context *sctx = (struct si_context *)ctx;
2369 struct si_shader_key key;
2370
2371 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2372 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2373 &key, -1, false);
2374 }
2375
2376 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
2377 bool streamout,
2378 struct si_shader_key *key)
2379 {
2380 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2381
2382 switch (info->processor) {
2383 case PIPE_SHADER_VERTEX:
2384 switch (next_shader) {
2385 case PIPE_SHADER_GEOMETRY:
2386 key->as_es = 1;
2387 break;
2388 case PIPE_SHADER_TESS_CTRL:
2389 case PIPE_SHADER_TESS_EVAL:
2390 key->as_ls = 1;
2391 break;
2392 default:
2393 /* If POSITION isn't written, it can only be a HW VS
2394 * if streamout is used. If streamout isn't used,
2395 * assume that it's a HW LS. (the next shader is TCS)
2396 * This heuristic is needed for separate shader objects.
2397 */
2398 if (!info->writes_position && !streamout)
2399 key->as_ls = 1;
2400 }
2401 break;
2402
2403 case PIPE_SHADER_TESS_EVAL:
2404 if (next_shader == PIPE_SHADER_GEOMETRY ||
2405 !info->writes_position)
2406 key->as_es = 1;
2407 break;
2408 }
2409 }
2410
2411 /**
2412 * Compile the main shader part or the monolithic shader as part of
2413 * si_shader_selector initialization. Since it can be done asynchronously,
2414 * there is no way to report compile failures to applications.
2415 */
2416 static void si_init_shader_selector_async(void *job, int thread_index)
2417 {
2418 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2419 struct si_screen *sscreen = sel->screen;
2420 struct ac_llvm_compiler *compiler;
2421 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2422
2423 assert(!debug->debug_message || debug->async);
2424 assert(thread_index >= 0);
2425 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2426 compiler = &sscreen->compiler[thread_index];
2427
2428 if (sel->nir)
2429 si_lower_nir(sel);
2430
2431 /* Compile the main shader part for use with a prolog and/or epilog.
2432 * If this fails, the driver will try to compile a monolithic shader
2433 * on demand.
2434 */
2435 if (!sscreen->use_monolithic_shaders) {
2436 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2437 void *ir_binary = NULL;
2438
2439 if (!shader) {
2440 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2441 return;
2442 }
2443
2444 /* We can leave the fence signaled because use of the default
2445 * main part is guarded by the selector's ready fence. */
2446 util_queue_fence_init(&shader->ready);
2447
2448 shader->selector = sel;
2449 shader->is_monolithic = false;
2450 si_parse_next_shader_property(&sel->info,
2451 sel->so.num_outputs != 0,
2452 &shader->key);
2453 if (sscreen->info.chip_class >= GFX10 &&
2454 !sscreen->options.disable_ngg &&
2455 (((sel->type == PIPE_SHADER_VERTEX ||
2456 sel->type == PIPE_SHADER_TESS_EVAL) &&
2457 !shader->key.as_ls && !shader->key.as_es) ||
2458 sel->type == PIPE_SHADER_GEOMETRY))
2459 shader->key.as_ngg = 1;
2460
2461 if (sel->tokens || sel->nir)
2462 ir_binary = si_get_ir_binary(sel);
2463
2464 /* Try to load the shader from the shader cache. */
2465 mtx_lock(&sscreen->shader_cache_mutex);
2466
2467 if (ir_binary &&
2468 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
2469 mtx_unlock(&sscreen->shader_cache_mutex);
2470 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2471 } else {
2472 mtx_unlock(&sscreen->shader_cache_mutex);
2473
2474 /* Compile the shader if it hasn't been loaded from the cache. */
2475 if (si_compile_tgsi_shader(sscreen, compiler, shader,
2476 debug) != 0) {
2477 FREE(shader);
2478 FREE(ir_binary);
2479 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2480 return;
2481 }
2482
2483 if (ir_binary) {
2484 mtx_lock(&sscreen->shader_cache_mutex);
2485 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
2486 FREE(ir_binary);
2487 mtx_unlock(&sscreen->shader_cache_mutex);
2488 }
2489 }
2490
2491 *si_get_main_shader_part(sel, &shader->key) = shader;
2492
2493 /* Unset "outputs_written" flags for outputs converted to
2494 * DEFAULT_VAL, so that later inter-shader optimizations don't
2495 * try to eliminate outputs that don't exist in the final
2496 * shader.
2497 *
2498 * This is only done if non-monolithic shaders are enabled.
2499 */
2500 if ((sel->type == PIPE_SHADER_VERTEX ||
2501 sel->type == PIPE_SHADER_TESS_EVAL) &&
2502 !shader->key.as_ls &&
2503 !shader->key.as_es) {
2504 unsigned i;
2505
2506 for (i = 0; i < sel->info.num_outputs; i++) {
2507 unsigned offset = shader->info.vs_output_param_offset[i];
2508
2509 if (offset <= AC_EXP_PARAM_OFFSET_31)
2510 continue;
2511
2512 unsigned name = sel->info.output_semantic_name[i];
2513 unsigned index = sel->info.output_semantic_index[i];
2514 unsigned id;
2515
2516 switch (name) {
2517 case TGSI_SEMANTIC_GENERIC:
2518 /* don't process indices the function can't handle */
2519 if (index >= SI_MAX_IO_GENERIC)
2520 break;
2521 /* fall through */
2522 default:
2523 id = si_shader_io_get_unique_index(name, index, true);
2524 sel->outputs_written_before_ps &= ~(1ull << id);
2525 break;
2526 case TGSI_SEMANTIC_POSITION: /* ignore these */
2527 case TGSI_SEMANTIC_PSIZE:
2528 case TGSI_SEMANTIC_CLIPVERTEX:
2529 case TGSI_SEMANTIC_EDGEFLAG:
2530 break;
2531 }
2532 }
2533 }
2534 }
2535
2536 /* The GS copy shader is always pre-compiled.
2537 *
2538 * TODO-GFX10: We could compile the GS copy shader on demand, since it
2539 * is only used in the (rare) non-NGG case.
2540 */
2541 if (sel->type == PIPE_SHADER_GEOMETRY) {
2542 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2543 if (!sel->gs_copy_shader) {
2544 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2545 return;
2546 }
2547
2548 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2549 }
2550 }
2551
2552 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2553 struct util_queue_fence *ready_fence,
2554 struct si_compiler_ctx_state *compiler_ctx_state,
2555 void *job, util_queue_execute_func execute)
2556 {
2557 util_queue_fence_init(ready_fence);
2558
2559 struct util_async_debug_callback async_debug;
2560 bool debug =
2561 (sctx->debug.debug_message && !sctx->debug.async) ||
2562 sctx->is_debug ||
2563 si_can_dump_shader(sctx->screen, processor);
2564
2565 if (debug) {
2566 u_async_debug_init(&async_debug);
2567 compiler_ctx_state->debug = async_debug.base;
2568 }
2569
2570 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2571 ready_fence, execute, NULL);
2572
2573 if (debug) {
2574 util_queue_fence_wait(ready_fence);
2575 u_async_debug_drain(&async_debug, &sctx->debug);
2576 u_async_debug_cleanup(&async_debug);
2577 }
2578
2579 if (sctx->screen->options.sync_compile)
2580 util_queue_fence_wait(ready_fence);
2581 }
2582
2583 /* Return descriptor slot usage masks from the given shader info. */
2584 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2585 uint32_t *const_and_shader_buffers,
2586 uint64_t *samplers_and_images)
2587 {
2588 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2589
2590 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2591 num_constbufs = util_last_bit(info->const_buffers_declared);
2592 /* two 8-byte images share one 16-byte slot */
2593 num_images = align(util_last_bit(info->images_declared), 2);
2594 num_samplers = util_last_bit(info->samplers_declared);
2595
2596 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2597 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2598 *const_and_shader_buffers =
2599 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2600
2601 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2602 start = si_get_image_slot(num_images - 1) / 2;
2603 *samplers_and_images =
2604 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2605 }
2606
2607 static void *si_create_shader_selector(struct pipe_context *ctx,
2608 const struct pipe_shader_state *state)
2609 {
2610 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2611 struct si_context *sctx = (struct si_context*)ctx;
2612 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2613 int i;
2614
2615 if (!sel)
2616 return NULL;
2617
2618 pipe_reference_init(&sel->reference, 1);
2619 sel->screen = sscreen;
2620 sel->compiler_ctx_state.debug = sctx->debug;
2621 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2622
2623 sel->so = state->stream_output;
2624
2625 if (state->type == PIPE_SHADER_IR_TGSI) {
2626 sel->tokens = tgsi_dup_tokens(state->tokens);
2627 if (!sel->tokens) {
2628 FREE(sel);
2629 return NULL;
2630 }
2631
2632 tgsi_scan_shader(state->tokens, &sel->info);
2633 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2634 } else {
2635 assert(state->type == PIPE_SHADER_IR_NIR);
2636
2637 sel->nir = state->ir.nir;
2638
2639 si_nir_opts(sel->nir);
2640 si_nir_scan_shader(sel->nir, &sel->info);
2641 si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
2642 }
2643
2644 sel->type = sel->info.processor;
2645 p_atomic_inc(&sscreen->num_shaders_created);
2646 si_get_active_slot_masks(&sel->info,
2647 &sel->active_const_and_shader_buffers,
2648 &sel->active_samplers_and_images);
2649
2650 /* Record which streamout buffers are enabled. */
2651 for (i = 0; i < sel->so.num_outputs; i++) {
2652 sel->enabled_streamout_buffer_mask |=
2653 (1 << sel->so.output[i].output_buffer) <<
2654 (sel->so.output[i].stream * 4);
2655 }
2656
2657 /* The prolog is a no-op if there are no inputs. */
2658 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2659 sel->info.num_inputs &&
2660 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2661
2662 sel->force_correct_derivs_after_kill =
2663 sel->type == PIPE_SHADER_FRAGMENT &&
2664 sel->info.uses_derivatives &&
2665 sel->info.uses_kill &&
2666 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2667
2668 sel->prim_discard_cs_allowed =
2669 sel->type == PIPE_SHADER_VERTEX &&
2670 !sel->info.uses_bindless_images &&
2671 !sel->info.uses_bindless_samplers &&
2672 !sel->info.writes_memory &&
2673 !sel->info.writes_viewport_index &&
2674 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2675 !sel->so.num_outputs;
2676
2677 /* Set which opcode uses which (i,j) pair. */
2678 if (sel->info.uses_persp_opcode_interp_centroid)
2679 sel->info.uses_persp_centroid = true;
2680
2681 if (sel->info.uses_linear_opcode_interp_centroid)
2682 sel->info.uses_linear_centroid = true;
2683
2684 if (sel->info.uses_persp_opcode_interp_offset ||
2685 sel->info.uses_persp_opcode_interp_sample)
2686 sel->info.uses_persp_center = true;
2687
2688 if (sel->info.uses_linear_opcode_interp_offset ||
2689 sel->info.uses_linear_opcode_interp_sample)
2690 sel->info.uses_linear_center = true;
2691
2692 switch (sel->type) {
2693 case PIPE_SHADER_GEOMETRY:
2694 sel->gs_output_prim =
2695 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2696
2697 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2698 sel->rast_prim = sel->gs_output_prim;
2699 if (util_rast_prim_is_triangles(sel->rast_prim))
2700 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2701
2702 sel->gs_max_out_vertices =
2703 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2704 sel->gs_num_invocations =
2705 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2706 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2707 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2708 sel->gs_max_out_vertices;
2709
2710 sel->max_gs_stream = 0;
2711 for (i = 0; i < sel->so.num_outputs; i++)
2712 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2713 sel->so.output[i].stream);
2714
2715 sel->gs_input_verts_per_prim =
2716 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2717 break;
2718
2719 case PIPE_SHADER_TESS_CTRL:
2720 /* Always reserve space for these. */
2721 sel->patch_outputs_written |=
2722 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2723 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2724 /* fall through */
2725 case PIPE_SHADER_VERTEX:
2726 case PIPE_SHADER_TESS_EVAL:
2727 for (i = 0; i < sel->info.num_outputs; i++) {
2728 unsigned name = sel->info.output_semantic_name[i];
2729 unsigned index = sel->info.output_semantic_index[i];
2730
2731 switch (name) {
2732 case TGSI_SEMANTIC_TESSINNER:
2733 case TGSI_SEMANTIC_TESSOUTER:
2734 case TGSI_SEMANTIC_PATCH:
2735 sel->patch_outputs_written |=
2736 1ull << si_shader_io_get_unique_index_patch(name, index);
2737 break;
2738
2739 case TGSI_SEMANTIC_GENERIC:
2740 /* don't process indices the function can't handle */
2741 if (index >= SI_MAX_IO_GENERIC)
2742 break;
2743 /* fall through */
2744 default:
2745 sel->outputs_written |=
2746 1ull << si_shader_io_get_unique_index(name, index, false);
2747 sel->outputs_written_before_ps |=
2748 1ull << si_shader_io_get_unique_index(name, index, true);
2749 break;
2750 case TGSI_SEMANTIC_EDGEFLAG:
2751 break;
2752 }
2753 }
2754 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2755 sel->lshs_vertex_stride = sel->esgs_itemsize;
2756
2757 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2758 * will start on a different bank. (except for the maximum 32*16).
2759 */
2760 if (sel->lshs_vertex_stride < 32*16)
2761 sel->lshs_vertex_stride += 4;
2762
2763 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2764 * conflicts, i.e. each vertex will start at a different bank.
2765 */
2766 if (sctx->chip_class >= GFX9)
2767 sel->esgs_itemsize += 4;
2768
2769 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2770
2771 /* Only for TES: */
2772 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2773 sel->rast_prim = PIPE_PRIM_POINTS;
2774 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2775 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2776 else
2777 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2778 break;
2779
2780 case PIPE_SHADER_FRAGMENT:
2781 for (i = 0; i < sel->info.num_inputs; i++) {
2782 unsigned name = sel->info.input_semantic_name[i];
2783 unsigned index = sel->info.input_semantic_index[i];
2784
2785 switch (name) {
2786 case TGSI_SEMANTIC_GENERIC:
2787 /* don't process indices the function can't handle */
2788 if (index >= SI_MAX_IO_GENERIC)
2789 break;
2790 /* fall through */
2791 default:
2792 sel->inputs_read |=
2793 1ull << si_shader_io_get_unique_index(name, index, true);
2794 break;
2795 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2796 break;
2797 }
2798 }
2799
2800 for (i = 0; i < 8; i++)
2801 if (sel->info.colors_written & (1 << i))
2802 sel->colors_written_4bit |= 0xf << (4 * i);
2803
2804 for (i = 0; i < sel->info.num_inputs; i++) {
2805 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2806 int index = sel->info.input_semantic_index[i];
2807 sel->color_attr_index[index] = i;
2808 }
2809 }
2810 break;
2811 default:;
2812 }
2813
2814 /* PA_CL_VS_OUT_CNTL */
2815 bool misc_vec_ena =
2816 sel->info.writes_psize || sel->info.writes_edgeflag ||
2817 sel->info.writes_layer || sel->info.writes_viewport_index;
2818 sel->pa_cl_vs_out_cntl =
2819 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2820 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2821 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2822 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2823 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2824 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2825 sel->clipdist_mask = sel->info.writes_clipvertex ?
2826 SIX_BITS : sel->info.clipdist_writemask;
2827 sel->culldist_mask = sel->info.culldist_writemask <<
2828 sel->info.num_written_clipdistance;
2829
2830 /* DB_SHADER_CONTROL */
2831 sel->db_shader_control =
2832 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2833 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2834 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2835 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2836
2837 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2838 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2839 sel->db_shader_control |=
2840 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2841 break;
2842 case TGSI_FS_DEPTH_LAYOUT_LESS:
2843 sel->db_shader_control |=
2844 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2845 break;
2846 }
2847
2848 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2849 *
2850 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2851 * --|-----------|------------|------------|--------------------|-------------------|-------------
2852 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2853 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2854 * 2 | false | true | n/a | LateZ | 1 | 0
2855 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2856 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2857 *
2858 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2859 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2860 *
2861 * Don't use ReZ without profiling !!!
2862 *
2863 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2864 * shaders.
2865 */
2866 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2867 /* Cases 3, 4. */
2868 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2869 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2870 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2871 } else if (sel->info.writes_memory) {
2872 /* Case 2. */
2873 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2874 S_02880C_EXEC_ON_HIER_FAIL(1);
2875 } else {
2876 /* Case 1. */
2877 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2878 }
2879
2880 (void) mtx_init(&sel->mutex, mtx_plain);
2881
2882 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2883 &sel->compiler_ctx_state, sel,
2884 si_init_shader_selector_async);
2885 return sel;
2886 }
2887
2888 static void si_update_streamout_state(struct si_context *sctx)
2889 {
2890 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2891
2892 if (!shader_with_so)
2893 return;
2894
2895 sctx->streamout.enabled_stream_buffers_mask =
2896 shader_with_so->enabled_streamout_buffer_mask;
2897 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2898 }
2899
2900 static void si_update_clip_regs(struct si_context *sctx,
2901 struct si_shader_selector *old_hw_vs,
2902 struct si_shader *old_hw_vs_variant,
2903 struct si_shader_selector *next_hw_vs,
2904 struct si_shader *next_hw_vs_variant)
2905 {
2906 if (next_hw_vs &&
2907 (!old_hw_vs ||
2908 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2909 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2910 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2911 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2912 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2913 !old_hw_vs_variant ||
2914 !next_hw_vs_variant ||
2915 old_hw_vs_variant->key.opt.clip_disable !=
2916 next_hw_vs_variant->key.opt.clip_disable))
2917 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2918 }
2919
2920 static void si_update_common_shader_state(struct si_context *sctx)
2921 {
2922 sctx->uses_bindless_samplers =
2923 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2924 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2925 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2926 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2927 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2928 sctx->uses_bindless_images =
2929 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2930 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2931 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2932 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2933 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2934 sctx->do_update_shaders = true;
2935 }
2936
2937 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2938 {
2939 struct si_context *sctx = (struct si_context *)ctx;
2940 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2941 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2942 struct si_shader_selector *sel = state;
2943
2944 if (sctx->vs_shader.cso == sel)
2945 return;
2946
2947 sctx->vs_shader.cso = sel;
2948 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2949 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2950
2951 si_update_common_shader_state(sctx);
2952 si_update_vs_viewport_state(sctx);
2953 si_set_active_descriptors_for_shader(sctx, sel);
2954 si_update_streamout_state(sctx);
2955 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2956 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2957 }
2958
2959 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2960 {
2961 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2962 (sctx->tes_shader.cso &&
2963 sctx->tes_shader.cso->info.uses_primid) ||
2964 (sctx->tcs_shader.cso &&
2965 sctx->tcs_shader.cso->info.uses_primid) ||
2966 (sctx->gs_shader.cso &&
2967 sctx->gs_shader.cso->info.uses_primid) ||
2968 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2969 sctx->ps_shader.cso->info.uses_primid);
2970 }
2971
2972 static bool si_update_ngg(struct si_context *sctx)
2973 {
2974 if (sctx->chip_class <= GFX9 ||
2975 sctx->screen->options.disable_ngg)
2976 return false;
2977
2978 bool new_ngg = true;
2979
2980 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2981 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
2982 sctx->gs_shader.cso->gs_num_invocations * sctx->gs_shader.cso->gs_max_out_vertices > 256)
2983 new_ngg = false;
2984
2985 if (new_ngg != sctx->ngg) {
2986 sctx->ngg = new_ngg;
2987 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2988 return true;
2989 }
2990 return false;
2991 }
2992
2993 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2994 {
2995 struct si_context *sctx = (struct si_context *)ctx;
2996 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2997 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2998 struct si_shader_selector *sel = state;
2999 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
3000 bool ngg_changed;
3001
3002 if (sctx->gs_shader.cso == sel)
3003 return;
3004
3005 sctx->gs_shader.cso = sel;
3006 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
3007 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
3008
3009 si_update_common_shader_state(sctx);
3010 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3011
3012 ngg_changed = si_update_ngg(sctx);
3013 if (ngg_changed || enable_changed)
3014 si_shader_change_notify(sctx);
3015 if (enable_changed) {
3016 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3017 si_update_tess_uses_prim_id(sctx);
3018 }
3019 si_update_vs_viewport_state(sctx);
3020 si_set_active_descriptors_for_shader(sctx, sel);
3021 si_update_streamout_state(sctx);
3022 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3023 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3024 }
3025
3026 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3027 {
3028 struct si_context *sctx = (struct si_context *)ctx;
3029 struct si_shader_selector *sel = state;
3030 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3031
3032 if (sctx->tcs_shader.cso == sel)
3033 return;
3034
3035 sctx->tcs_shader.cso = sel;
3036 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3037 si_update_tess_uses_prim_id(sctx);
3038
3039 si_update_common_shader_state(sctx);
3040
3041 if (enable_changed)
3042 sctx->last_tcs = NULL; /* invalidate derived tess state */
3043
3044 si_set_active_descriptors_for_shader(sctx, sel);
3045 }
3046
3047 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3048 {
3049 struct si_context *sctx = (struct si_context *)ctx;
3050 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3051 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3052 struct si_shader_selector *sel = state;
3053 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3054
3055 if (sctx->tes_shader.cso == sel)
3056 return;
3057
3058 sctx->tes_shader.cso = sel;
3059 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3060 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3061 si_update_tess_uses_prim_id(sctx);
3062
3063 si_update_common_shader_state(sctx);
3064 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3065
3066 if (enable_changed) {
3067 si_update_ngg(sctx);
3068 si_shader_change_notify(sctx);
3069 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3070 }
3071 si_update_vs_viewport_state(sctx);
3072 si_set_active_descriptors_for_shader(sctx, sel);
3073 si_update_streamout_state(sctx);
3074 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3075 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3076 }
3077
3078 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3079 {
3080 struct si_context *sctx = (struct si_context *)ctx;
3081 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3082 struct si_shader_selector *sel = state;
3083
3084 /* skip if supplied shader is one already in use */
3085 if (old_sel == sel)
3086 return;
3087
3088 sctx->ps_shader.cso = sel;
3089 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3090
3091 si_update_common_shader_state(sctx);
3092 if (sel) {
3093 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3094 si_update_tess_uses_prim_id(sctx);
3095
3096 if (!old_sel ||
3097 old_sel->info.colors_written != sel->info.colors_written)
3098 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3099
3100 if (sctx->screen->has_out_of_order_rast &&
3101 (!old_sel ||
3102 old_sel->info.writes_memory != sel->info.writes_memory ||
3103 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3104 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3105 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3106 }
3107 si_set_active_descriptors_for_shader(sctx, sel);
3108 si_update_ps_colorbuf0_slot(sctx);
3109 }
3110
3111 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3112 {
3113 if (shader->is_optimized) {
3114 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3115 &shader->ready);
3116 }
3117
3118 util_queue_fence_destroy(&shader->ready);
3119
3120 if (shader->pm4) {
3121 /* If destroyed shaders were not unbound, the next compiled
3122 * shader variant could get the same pointer address and so
3123 * binding it to the same shader stage would be considered
3124 * a no-op, causing random behavior.
3125 */
3126 switch (shader->selector->type) {
3127 case PIPE_SHADER_VERTEX:
3128 if (shader->key.as_ls) {
3129 assert(sctx->chip_class <= GFX8);
3130 si_pm4_delete_state(sctx, ls, shader->pm4);
3131 } else if (shader->key.as_es) {
3132 assert(sctx->chip_class <= GFX8);
3133 si_pm4_delete_state(sctx, es, shader->pm4);
3134 } else if (shader->key.as_ngg) {
3135 si_pm4_delete_state(sctx, gs, shader->pm4);
3136 } else {
3137 si_pm4_delete_state(sctx, vs, shader->pm4);
3138 }
3139 break;
3140 case PIPE_SHADER_TESS_CTRL:
3141 si_pm4_delete_state(sctx, hs, shader->pm4);
3142 break;
3143 case PIPE_SHADER_TESS_EVAL:
3144 if (shader->key.as_es) {
3145 assert(sctx->chip_class <= GFX8);
3146 si_pm4_delete_state(sctx, es, shader->pm4);
3147 } else if (shader->key.as_ngg) {
3148 si_pm4_delete_state(sctx, gs, shader->pm4);
3149 } else {
3150 si_pm4_delete_state(sctx, vs, shader->pm4);
3151 }
3152 break;
3153 case PIPE_SHADER_GEOMETRY:
3154 if (shader->is_gs_copy_shader)
3155 si_pm4_delete_state(sctx, vs, shader->pm4);
3156 else
3157 si_pm4_delete_state(sctx, gs, shader->pm4);
3158 break;
3159 case PIPE_SHADER_FRAGMENT:
3160 si_pm4_delete_state(sctx, ps, shader->pm4);
3161 break;
3162 default:;
3163 }
3164 }
3165
3166 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3167 si_shader_destroy(shader);
3168 free(shader);
3169 }
3170
3171 void si_destroy_shader_selector(struct si_context *sctx,
3172 struct si_shader_selector *sel)
3173 {
3174 struct si_shader *p = sel->first_variant, *c;
3175 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3176 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3177 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3178 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3179 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3180 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3181 };
3182
3183 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3184
3185 if (current_shader[sel->type]->cso == sel) {
3186 current_shader[sel->type]->cso = NULL;
3187 current_shader[sel->type]->current = NULL;
3188 }
3189
3190 while (p) {
3191 c = p->next_variant;
3192 si_delete_shader(sctx, p);
3193 p = c;
3194 }
3195
3196 if (sel->main_shader_part)
3197 si_delete_shader(sctx, sel->main_shader_part);
3198 if (sel->main_shader_part_ls)
3199 si_delete_shader(sctx, sel->main_shader_part_ls);
3200 if (sel->main_shader_part_es)
3201 si_delete_shader(sctx, sel->main_shader_part_es);
3202 if (sel->main_shader_part_ngg)
3203 si_delete_shader(sctx, sel->main_shader_part_ngg);
3204 if (sel->gs_copy_shader)
3205 si_delete_shader(sctx, sel->gs_copy_shader);
3206
3207 util_queue_fence_destroy(&sel->ready);
3208 mtx_destroy(&sel->mutex);
3209 free(sel->tokens);
3210 ralloc_free(sel->nir);
3211 free(sel);
3212 }
3213
3214 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3215 {
3216 struct si_context *sctx = (struct si_context *)ctx;
3217 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3218
3219 si_shader_selector_reference(sctx, &sel, NULL);
3220 }
3221
3222 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3223 struct si_shader *vs, unsigned name,
3224 unsigned index, unsigned interpolate)
3225 {
3226 struct tgsi_shader_info *vsinfo = &vs->selector->info;
3227 unsigned j, offset, ps_input_cntl = 0;
3228
3229 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3230 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3231 name == TGSI_SEMANTIC_PRIMID)
3232 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3233
3234 if (name == TGSI_SEMANTIC_PCOORD ||
3235 (name == TGSI_SEMANTIC_TEXCOORD &&
3236 sctx->sprite_coord_enable & (1 << index))) {
3237 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3238 }
3239
3240 for (j = 0; j < vsinfo->num_outputs; j++) {
3241 if (name == vsinfo->output_semantic_name[j] &&
3242 index == vsinfo->output_semantic_index[j]) {
3243 offset = vs->info.vs_output_param_offset[j];
3244
3245 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3246 /* The input is loaded from parameter memory. */
3247 ps_input_cntl |= S_028644_OFFSET(offset);
3248 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3249 if (offset == AC_EXP_PARAM_UNDEFINED) {
3250 /* This can happen with depth-only rendering. */
3251 offset = 0;
3252 } else {
3253 /* The input is a DEFAULT_VAL constant. */
3254 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3255 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3256 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3257 }
3258
3259 ps_input_cntl = S_028644_OFFSET(0x20) |
3260 S_028644_DEFAULT_VAL(offset);
3261 }
3262 break;
3263 }
3264 }
3265
3266 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3267 /* PrimID is written after the last output when HW VS is used. */
3268 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3269 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3270 /* No corresponding output found, load defaults into input.
3271 * Don't set any other bits.
3272 * (FLAT_SHADE=1 completely changes behavior) */
3273 ps_input_cntl = S_028644_OFFSET(0x20);
3274 /* D3D 9 behaviour. GL is undefined */
3275 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3276 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3277 }
3278 return ps_input_cntl;
3279 }
3280
3281 static void si_emit_spi_map(struct si_context *sctx)
3282 {
3283 struct si_shader *ps = sctx->ps_shader.current;
3284 struct si_shader *vs = si_get_vs_state(sctx);
3285 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3286 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3287 unsigned spi_ps_input_cntl[32];
3288
3289 if (!ps || !ps->selector->info.num_inputs)
3290 return;
3291
3292 num_interp = si_get_ps_num_interp(ps);
3293 assert(num_interp > 0);
3294
3295 for (i = 0; i < psinfo->num_inputs; i++) {
3296 unsigned name = psinfo->input_semantic_name[i];
3297 unsigned index = psinfo->input_semantic_index[i];
3298 unsigned interpolate = psinfo->input_interpolate[i];
3299
3300 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3301 index, interpolate);
3302
3303 if (name == TGSI_SEMANTIC_COLOR) {
3304 assert(index < ARRAY_SIZE(bcol_interp));
3305 bcol_interp[index] = interpolate;
3306 }
3307 }
3308
3309 if (ps->key.part.ps.prolog.color_two_side) {
3310 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3311
3312 for (i = 0; i < 2; i++) {
3313 if (!(psinfo->colors_read & (0xf << (i * 4))))
3314 continue;
3315
3316 spi_ps_input_cntl[num_written++] =
3317 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3318
3319 }
3320 }
3321 assert(num_interp == num_written);
3322
3323 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3324 /* Dota 2: Only ~16% of SPI map updates set different values. */
3325 /* Talos: Only ~9% of SPI map updates set different values. */
3326 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3327 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3328 spi_ps_input_cntl,
3329 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3330
3331 if (initial_cdw != sctx->gfx_cs->current.cdw)
3332 sctx->context_roll = true;
3333 }
3334
3335 /**
3336 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3337 */
3338 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3339 {
3340 if (sctx->init_config_has_vgt_flush)
3341 return;
3342
3343 /* Done by Vulkan before VGT_FLUSH. */
3344 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3345 si_pm4_cmd_add(sctx->init_config,
3346 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3347 si_pm4_cmd_end(sctx->init_config, false);
3348
3349 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3350 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3351 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3352 si_pm4_cmd_end(sctx->init_config, false);
3353 sctx->init_config_has_vgt_flush = true;
3354 }
3355
3356 /* Initialize state related to ESGS / GSVS ring buffers */
3357 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3358 {
3359 struct si_shader_selector *es =
3360 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3361 struct si_shader_selector *gs = sctx->gs_shader.cso;
3362 struct si_pm4_state *pm4;
3363
3364 /* Chip constants. */
3365 unsigned num_se = sctx->screen->info.max_se;
3366 unsigned wave_size = 64;
3367 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3368 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3369 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3370 */
3371 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3372 unsigned alignment = 256 * num_se;
3373 /* The maximum size is 63.999 MB per SE. */
3374 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3375
3376 /* Calculate the minimum size. */
3377 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3378 wave_size, alignment);
3379
3380 /* These are recommended sizes, not minimum sizes. */
3381 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3382 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3383 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3384 gs->max_gsvs_emit_size;
3385
3386 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3387 esgs_ring_size = align(esgs_ring_size, alignment);
3388 gsvs_ring_size = align(gsvs_ring_size, alignment);
3389
3390 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3391 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3392
3393 /* Some rings don't have to be allocated if shaders don't use them.
3394 * (e.g. no varyings between ES and GS or GS and VS)
3395 *
3396 * GFX9 doesn't have the ESGS ring.
3397 */
3398 bool update_esgs = sctx->chip_class <= GFX8 &&
3399 esgs_ring_size &&
3400 (!sctx->esgs_ring ||
3401 sctx->esgs_ring->width0 < esgs_ring_size);
3402 bool update_gsvs = gsvs_ring_size &&
3403 (!sctx->gsvs_ring ||
3404 sctx->gsvs_ring->width0 < gsvs_ring_size);
3405
3406 if (!update_esgs && !update_gsvs)
3407 return true;
3408
3409 if (update_esgs) {
3410 pipe_resource_reference(&sctx->esgs_ring, NULL);
3411 sctx->esgs_ring =
3412 pipe_aligned_buffer_create(sctx->b.screen,
3413 SI_RESOURCE_FLAG_UNMAPPABLE,
3414 PIPE_USAGE_DEFAULT,
3415 esgs_ring_size, alignment);
3416 if (!sctx->esgs_ring)
3417 return false;
3418 }
3419
3420 if (update_gsvs) {
3421 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3422 sctx->gsvs_ring =
3423 pipe_aligned_buffer_create(sctx->b.screen,
3424 SI_RESOURCE_FLAG_UNMAPPABLE,
3425 PIPE_USAGE_DEFAULT,
3426 gsvs_ring_size, alignment);
3427 if (!sctx->gsvs_ring)
3428 return false;
3429 }
3430
3431 /* Create the "init_config_gs_rings" state. */
3432 pm4 = CALLOC_STRUCT(si_pm4_state);
3433 if (!pm4)
3434 return false;
3435
3436 if (sctx->chip_class >= GFX7) {
3437 if (sctx->esgs_ring) {
3438 assert(sctx->chip_class <= GFX8);
3439 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3440 sctx->esgs_ring->width0 / 256);
3441 }
3442 if (sctx->gsvs_ring)
3443 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3444 sctx->gsvs_ring->width0 / 256);
3445 } else {
3446 if (sctx->esgs_ring)
3447 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3448 sctx->esgs_ring->width0 / 256);
3449 if (sctx->gsvs_ring)
3450 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3451 sctx->gsvs_ring->width0 / 256);
3452 }
3453
3454 /* Set the state. */
3455 if (sctx->init_config_gs_rings)
3456 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3457 sctx->init_config_gs_rings = pm4;
3458
3459 if (!sctx->init_config_has_vgt_flush) {
3460 si_init_config_add_vgt_flush(sctx);
3461 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3462 }
3463
3464 /* Flush the context to re-emit both init_config states. */
3465 sctx->initial_gfx_cs_size = 0; /* force flush */
3466 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3467
3468 /* Set ring bindings. */
3469 if (sctx->esgs_ring) {
3470 assert(sctx->chip_class <= GFX8);
3471 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3472 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3473 true, true, 4, 64, 0);
3474 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3475 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3476 false, false, 0, 0, 0);
3477 }
3478 if (sctx->gsvs_ring) {
3479 si_set_ring_buffer(sctx, SI_RING_GSVS,
3480 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3481 false, false, 0, 0, 0);
3482 }
3483
3484 return true;
3485 }
3486
3487 static void si_shader_lock(struct si_shader *shader)
3488 {
3489 mtx_lock(&shader->selector->mutex);
3490 if (shader->previous_stage_sel) {
3491 assert(shader->previous_stage_sel != shader->selector);
3492 mtx_lock(&shader->previous_stage_sel->mutex);
3493 }
3494 }
3495
3496 static void si_shader_unlock(struct si_shader *shader)
3497 {
3498 if (shader->previous_stage_sel)
3499 mtx_unlock(&shader->previous_stage_sel->mutex);
3500 mtx_unlock(&shader->selector->mutex);
3501 }
3502
3503 /**
3504 * @returns 1 if \p sel has been updated to use a new scratch buffer
3505 * 0 if not
3506 * < 0 if there was a failure
3507 */
3508 static int si_update_scratch_buffer(struct si_context *sctx,
3509 struct si_shader *shader)
3510 {
3511 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3512
3513 if (!shader)
3514 return 0;
3515
3516 /* This shader doesn't need a scratch buffer */
3517 if (shader->config.scratch_bytes_per_wave == 0)
3518 return 0;
3519
3520 /* Prevent race conditions when updating:
3521 * - si_shader::scratch_bo
3522 * - si_shader::binary::code
3523 * - si_shader::previous_stage::binary::code.
3524 */
3525 si_shader_lock(shader);
3526
3527 /* This shader is already configured to use the current
3528 * scratch buffer. */
3529 if (shader->scratch_bo == sctx->scratch_buffer) {
3530 si_shader_unlock(shader);
3531 return 0;
3532 }
3533
3534 assert(sctx->scratch_buffer);
3535
3536 /* Replace the shader bo with a new bo that has the relocs applied. */
3537 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3538 si_shader_unlock(shader);
3539 return -1;
3540 }
3541
3542 /* Update the shader state to use the new shader bo. */
3543 si_shader_init_pm4_state(sctx->screen, shader);
3544
3545 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3546
3547 si_shader_unlock(shader);
3548 return 1;
3549 }
3550
3551 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
3552 {
3553 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
3554 }
3555
3556 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3557 {
3558 return shader ? shader->config.scratch_bytes_per_wave : 0;
3559 }
3560
3561 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3562 {
3563 if (!sctx->tes_shader.cso)
3564 return NULL; /* tessellation disabled */
3565
3566 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3567 sctx->fixed_func_tcs_shader.current;
3568 }
3569
3570 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
3571 {
3572 unsigned bytes = 0;
3573
3574 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3575 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3576 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3577 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3578
3579 if (sctx->tes_shader.cso) {
3580 struct si_shader *tcs = si_get_tcs_current(sctx);
3581
3582 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
3583 }
3584 return bytes;
3585 }
3586
3587 static bool si_update_scratch_relocs(struct si_context *sctx)
3588 {
3589 struct si_shader *tcs = si_get_tcs_current(sctx);
3590 int r;
3591
3592 /* Update the shaders, so that they are using the latest scratch.
3593 * The scratch buffer may have been changed since these shaders were
3594 * last used, so we still need to try to update them, even if they
3595 * require scratch buffers smaller than the current size.
3596 */
3597 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3598 if (r < 0)
3599 return false;
3600 if (r == 1)
3601 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3602
3603 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3604 if (r < 0)
3605 return false;
3606 if (r == 1)
3607 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3608
3609 r = si_update_scratch_buffer(sctx, tcs);
3610 if (r < 0)
3611 return false;
3612 if (r == 1)
3613 si_pm4_bind_state(sctx, hs, tcs->pm4);
3614
3615 /* VS can be bound as LS, ES, or VS. */
3616 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3617 if (r < 0)
3618 return false;
3619 if (r == 1) {
3620 if (sctx->vs_shader.current->key.as_ls)
3621 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3622 else if (sctx->vs_shader.current->key.as_es)
3623 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3624 else if (sctx->vs_shader.current->key.as_ngg)
3625 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3626 else
3627 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3628 }
3629
3630 /* TES can be bound as ES or VS. */
3631 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3632 if (r < 0)
3633 return false;
3634 if (r == 1) {
3635 if (sctx->tes_shader.current->key.as_es)
3636 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3637 else if (sctx->tes_shader.current->key.as_ngg)
3638 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3639 else
3640 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3641 }
3642
3643 return true;
3644 }
3645
3646 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3647 {
3648 unsigned current_scratch_buffer_size =
3649 si_get_current_scratch_buffer_size(sctx);
3650 unsigned scratch_bytes_per_wave =
3651 si_get_max_scratch_bytes_per_wave(sctx);
3652 unsigned scratch_needed_size = scratch_bytes_per_wave *
3653 sctx->scratch_waves;
3654 unsigned spi_tmpring_size;
3655
3656 if (scratch_needed_size > 0) {
3657 if (scratch_needed_size > current_scratch_buffer_size) {
3658 /* Create a bigger scratch buffer */
3659 si_resource_reference(&sctx->scratch_buffer, NULL);
3660
3661 sctx->scratch_buffer =
3662 si_aligned_buffer_create(&sctx->screen->b,
3663 SI_RESOURCE_FLAG_UNMAPPABLE,
3664 PIPE_USAGE_DEFAULT,
3665 scratch_needed_size, 256);
3666 if (!sctx->scratch_buffer)
3667 return false;
3668
3669 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3670 si_context_add_resource_size(sctx,
3671 &sctx->scratch_buffer->b.b);
3672 }
3673
3674 if (!si_update_scratch_relocs(sctx))
3675 return false;
3676 }
3677
3678 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3679 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3680 "scratch size should already be aligned correctly.");
3681
3682 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3683 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3684 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3685 sctx->spi_tmpring_size = spi_tmpring_size;
3686 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3687 }
3688 return true;
3689 }
3690
3691 static void si_init_tess_factor_ring(struct si_context *sctx)
3692 {
3693 assert(!sctx->tess_rings);
3694
3695 /* The address must be aligned to 2^19, because the shader only
3696 * receives the high 13 bits.
3697 */
3698 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3699 SI_RESOURCE_FLAG_32BIT,
3700 PIPE_USAGE_DEFAULT,
3701 sctx->screen->tess_offchip_ring_size +
3702 sctx->screen->tess_factor_ring_size,
3703 1 << 19);
3704 if (!sctx->tess_rings)
3705 return;
3706
3707 si_init_config_add_vgt_flush(sctx);
3708
3709 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3710 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3711
3712 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3713 sctx->screen->tess_offchip_ring_size;
3714
3715 /* Append these registers to the init config state. */
3716 if (sctx->chip_class >= GFX7) {
3717 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3718 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3719 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3720 factor_va >> 8);
3721 if (sctx->chip_class >= GFX10)
3722 si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3723 S_030984_BASE_HI(factor_va >> 40));
3724 else if (sctx->chip_class == GFX9)
3725 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3726 S_030944_BASE_HI(factor_va >> 40));
3727 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3728 sctx->screen->vgt_hs_offchip_param);
3729 } else {
3730 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3731 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3732 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3733 factor_va >> 8);
3734 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3735 sctx->screen->vgt_hs_offchip_param);
3736 }
3737
3738 /* Flush the context to re-emit the init_config state.
3739 * This is done only once in a lifetime of a context.
3740 */
3741 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3742 sctx->initial_gfx_cs_size = 0; /* force flush */
3743 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3744 }
3745
3746 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3747 union si_vgt_stages_key key)
3748 {
3749 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3750 uint32_t stages = 0;
3751
3752 if (key.u.tess) {
3753 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3754 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3755
3756 if (key.u.gs)
3757 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3758 S_028B54_GS_EN(1);
3759 else if (key.u.ngg)
3760 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3761 else
3762 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3763 } else if (key.u.gs) {
3764 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3765 S_028B54_GS_EN(1);
3766 } else if (key.u.ngg) {
3767 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3768 }
3769
3770 if (key.u.ngg) {
3771 stages |= S_028B54_PRIMGEN_EN(1);
3772 if (key.u.streamout)
3773 stages |= S_028B54_NGG_WAVE_ID_EN(1);
3774 } else if (key.u.gs)
3775 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3776
3777 if (screen->info.chip_class >= GFX9)
3778 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3779
3780 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3781 return pm4;
3782 }
3783
3784 static void si_update_vgt_shader_config(struct si_context *sctx,
3785 union si_vgt_stages_key key)
3786 {
3787 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3788
3789 if (unlikely(!*pm4))
3790 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3791 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3792 }
3793
3794 bool si_update_shaders(struct si_context *sctx)
3795 {
3796 struct pipe_context *ctx = (struct pipe_context*)sctx;
3797 struct si_compiler_ctx_state compiler_state;
3798 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3799 struct si_shader *old_vs = si_get_vs_state(sctx);
3800 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3801 struct si_shader *old_ps = sctx->ps_shader.current;
3802 union si_vgt_stages_key key;
3803 unsigned old_spi_shader_col_format =
3804 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3805 int r;
3806
3807 compiler_state.compiler = &sctx->compiler;
3808 compiler_state.debug = sctx->debug;
3809 compiler_state.is_debug_context = sctx->is_debug;
3810
3811 key.index = 0;
3812
3813 if (sctx->tes_shader.cso)
3814 key.u.tess = 1;
3815 if (sctx->gs_shader.cso)
3816 key.u.gs = 1;
3817
3818 if (sctx->chip_class >= GFX10) {
3819 key.u.ngg = sctx->ngg;
3820
3821 if (sctx->gs_shader.cso)
3822 key.u.streamout = !!sctx->gs_shader.cso->so.num_outputs;
3823 else if (sctx->tes_shader.cso)
3824 key.u.streamout = !!sctx->tes_shader.cso->so.num_outputs;
3825 else
3826 key.u.streamout = !!sctx->vs_shader.cso->so.num_outputs;
3827 }
3828
3829 /* Update TCS and TES. */
3830 if (sctx->tes_shader.cso) {
3831 if (!sctx->tess_rings) {
3832 si_init_tess_factor_ring(sctx);
3833 if (!sctx->tess_rings)
3834 return false;
3835 }
3836
3837 if (sctx->tcs_shader.cso) {
3838 r = si_shader_select(ctx, &sctx->tcs_shader, key,
3839 &compiler_state);
3840 if (r)
3841 return false;
3842 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3843 } else {
3844 if (!sctx->fixed_func_tcs_shader.cso) {
3845 sctx->fixed_func_tcs_shader.cso =
3846 si_create_fixed_func_tcs(sctx);
3847 if (!sctx->fixed_func_tcs_shader.cso)
3848 return false;
3849 }
3850
3851 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3852 key, &compiler_state);
3853 if (r)
3854 return false;
3855 si_pm4_bind_state(sctx, hs,
3856 sctx->fixed_func_tcs_shader.current->pm4);
3857 }
3858
3859 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3860 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3861 if (r)
3862 return false;
3863
3864 if (sctx->gs_shader.cso) {
3865 /* TES as ES */
3866 assert(sctx->chip_class <= GFX8);
3867 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3868 } else if (key.u.ngg) {
3869 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3870 } else {
3871 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3872 }
3873 }
3874 } else {
3875 if (sctx->chip_class <= GFX8)
3876 si_pm4_bind_state(sctx, ls, NULL);
3877 si_pm4_bind_state(sctx, hs, NULL);
3878 }
3879
3880 /* Update GS. */
3881 if (sctx->gs_shader.cso) {
3882 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
3883 if (r)
3884 return false;
3885 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3886 if (!key.u.ngg) {
3887 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3888
3889 if (!si_update_gs_ring_buffers(sctx))
3890 return false;
3891 } else {
3892 si_pm4_bind_state(sctx, vs, NULL);
3893 }
3894 } else {
3895 if (!key.u.ngg) {
3896 si_pm4_bind_state(sctx, gs, NULL);
3897 if (sctx->chip_class <= GFX8)
3898 si_pm4_bind_state(sctx, es, NULL);
3899 }
3900 }
3901
3902 /* Update VS. */
3903 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
3904 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
3905 if (r)
3906 return false;
3907
3908 if (!key.u.tess && !key.u.gs) {
3909 if (key.u.ngg) {
3910 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3911 si_pm4_bind_state(sctx, vs, NULL);
3912 } else {
3913 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3914 }
3915 } else if (sctx->tes_shader.cso) {
3916 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3917 } else {
3918 assert(sctx->gs_shader.cso);
3919 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3920 }
3921 }
3922
3923 si_update_vgt_shader_config(sctx, key);
3924
3925 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3926 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3927
3928 if (sctx->ps_shader.cso) {
3929 unsigned db_shader_control;
3930
3931 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
3932 if (r)
3933 return false;
3934 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3935
3936 db_shader_control =
3937 sctx->ps_shader.cso->db_shader_control |
3938 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3939
3940 if (si_pm4_state_changed(sctx, ps) ||
3941 si_pm4_state_changed(sctx, vs) ||
3942 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
3943 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3944 sctx->flatshade != rs->flatshade) {
3945 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3946 sctx->flatshade = rs->flatshade;
3947 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3948 }
3949
3950 if (sctx->screen->rbplus_allowed &&
3951 si_pm4_state_changed(sctx, ps) &&
3952 (!old_ps ||
3953 old_spi_shader_col_format !=
3954 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3955 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3956
3957 if (sctx->ps_db_shader_control != db_shader_control) {
3958 sctx->ps_db_shader_control = db_shader_control;
3959 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3960 if (sctx->screen->dpbb_allowed)
3961 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3962 }
3963
3964 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3965 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3966 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3967
3968 if (sctx->chip_class == GFX6)
3969 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3970
3971 if (sctx->framebuffer.nr_samples <= 1)
3972 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3973 }
3974 }
3975
3976 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3977 si_pm4_state_enabled_and_changed(sctx, hs) ||
3978 si_pm4_state_enabled_and_changed(sctx, es) ||
3979 si_pm4_state_enabled_and_changed(sctx, gs) ||
3980 si_pm4_state_enabled_and_changed(sctx, vs) ||
3981 si_pm4_state_enabled_and_changed(sctx, ps)) {
3982 if (!si_update_spi_tmpring_size(sctx))
3983 return false;
3984 }
3985
3986 if (sctx->chip_class >= GFX7) {
3987 if (si_pm4_state_enabled_and_changed(sctx, ls))
3988 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3989 else if (!sctx->queued.named.ls)
3990 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3991
3992 if (si_pm4_state_enabled_and_changed(sctx, hs))
3993 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3994 else if (!sctx->queued.named.hs)
3995 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3996
3997 if (si_pm4_state_enabled_and_changed(sctx, es))
3998 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
3999 else if (!sctx->queued.named.es)
4000 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
4001
4002 if (si_pm4_state_enabled_and_changed(sctx, gs))
4003 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
4004 else if (!sctx->queued.named.gs)
4005 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
4006
4007 if (si_pm4_state_enabled_and_changed(sctx, vs))
4008 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
4009 else if (!sctx->queued.named.vs)
4010 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
4011
4012 if (si_pm4_state_enabled_and_changed(sctx, ps))
4013 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
4014 else if (!sctx->queued.named.ps)
4015 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
4016 }
4017
4018 sctx->do_update_shaders = false;
4019 return true;
4020 }
4021
4022 static void si_emit_scratch_state(struct si_context *sctx)
4023 {
4024 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4025
4026 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
4027 sctx->spi_tmpring_size);
4028
4029 if (sctx->scratch_buffer) {
4030 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
4031 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
4032 RADEON_PRIO_SCRATCH_BUFFER);
4033 }
4034 }
4035
4036 void si_init_shader_functions(struct si_context *sctx)
4037 {
4038 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
4039 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
4040
4041 sctx->b.create_vs_state = si_create_shader_selector;
4042 sctx->b.create_tcs_state = si_create_shader_selector;
4043 sctx->b.create_tes_state = si_create_shader_selector;
4044 sctx->b.create_gs_state = si_create_shader_selector;
4045 sctx->b.create_fs_state = si_create_shader_selector;
4046
4047 sctx->b.bind_vs_state = si_bind_vs_shader;
4048 sctx->b.bind_tcs_state = si_bind_tcs_shader;
4049 sctx->b.bind_tes_state = si_bind_tes_shader;
4050 sctx->b.bind_gs_state = si_bind_gs_shader;
4051 sctx->b.bind_fs_state = si_bind_ps_shader;
4052
4053 sctx->b.delete_vs_state = si_delete_shader_selector;
4054 sctx->b.delete_tcs_state = si_delete_shader_selector;
4055 sctx->b.delete_tes_state = si_delete_shader_selector;
4056 sctx->b.delete_gs_state = si_delete_shader_selector;
4057 sctx->b.delete_fs_state = si_delete_shader_selector;
4058 }