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radeonsi:optimizing SET_CONTEXT_REG for shaders GS
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
45 * size as integer.
46 */
47 void *si_get_ir_binary(struct si_shader_selector *sel)
48 {
49 struct blob blob;
50 unsigned ir_size;
51 void *ir_binary;
52
53 if (sel->tokens) {
54 ir_binary = sel->tokens;
55 ir_size = tgsi_num_tokens(sel->tokens) *
56 sizeof(struct tgsi_token);
57 } else {
58 assert(sel->nir);
59
60 blob_init(&blob);
61 nir_serialize(&blob, sel->nir);
62 ir_binary = blob.data;
63 ir_size = blob.size;
64 }
65
66 unsigned size = 4 + ir_size + sizeof(sel->so);
67 char *result = (char*)MALLOC(size);
68 if (!result)
69 return NULL;
70
71 *((uint32_t*)result) = size;
72 memcpy(result + 4, ir_binary, ir_size);
73 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
74
75 if (sel->nir)
76 blob_finish(&blob);
77
78 return result;
79 }
80
81 /** Copy "data" to "ptr" and return the next dword following copied data. */
82 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
83 {
84 /* data may be NULL if size == 0 */
85 if (size)
86 memcpy(ptr, data, size);
87 ptr += DIV_ROUND_UP(size, 4);
88 return ptr;
89 }
90
91 /** Read data from "ptr". Return the next dword following the data. */
92 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
93 {
94 memcpy(data, ptr, size);
95 ptr += DIV_ROUND_UP(size, 4);
96 return ptr;
97 }
98
99 /**
100 * Write the size as uint followed by the data. Return the next dword
101 * following the copied data.
102 */
103 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
104 {
105 *ptr++ = size;
106 return write_data(ptr, data, size);
107 }
108
109 /**
110 * Read the size as uint followed by the data. Return both via parameters.
111 * Return the next dword following the data.
112 */
113 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
114 {
115 *size = *ptr++;
116 assert(*data == NULL);
117 if (!*size)
118 return ptr;
119 *data = malloc(*size);
120 return read_data(ptr, *data, *size);
121 }
122
123 /**
124 * Return the shader binary in a buffer. The first 4 bytes contain its size
125 * as integer.
126 */
127 static void *si_get_shader_binary(struct si_shader *shader)
128 {
129 /* There is always a size of data followed by the data itself. */
130 unsigned relocs_size = shader->binary.reloc_count *
131 sizeof(shader->binary.relocs[0]);
132 unsigned disasm_size = shader->binary.disasm_string ?
133 strlen(shader->binary.disasm_string) + 1 : 0;
134 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
135 strlen(shader->binary.llvm_ir_string) + 1 : 0;
136 unsigned size =
137 4 + /* total size */
138 4 + /* CRC32 of the data below */
139 align(sizeof(shader->config), 4) +
140 align(sizeof(shader->info), 4) +
141 4 + align(shader->binary.code_size, 4) +
142 4 + align(shader->binary.rodata_size, 4) +
143 4 + align(relocs_size, 4) +
144 4 + align(disasm_size, 4) +
145 4 + align(llvm_ir_size, 4);
146 void *buffer = CALLOC(1, size);
147 uint32_t *ptr = (uint32_t*)buffer;
148
149 if (!buffer)
150 return NULL;
151
152 *ptr++ = size;
153 ptr++; /* CRC32 is calculated at the end. */
154
155 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
156 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
157 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
158 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
159 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
160 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
161 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
162 assert((char *)ptr - (char *)buffer == size);
163
164 /* Compute CRC32. */
165 ptr = (uint32_t*)buffer;
166 ptr++;
167 *ptr = util_hash_crc32(ptr + 1, size - 8);
168
169 return buffer;
170 }
171
172 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
173 {
174 uint32_t *ptr = (uint32_t*)binary;
175 uint32_t size = *ptr++;
176 uint32_t crc32 = *ptr++;
177 unsigned chunk_size;
178
179 if (util_hash_crc32(ptr, size - 8) != crc32) {
180 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
181 return false;
182 }
183
184 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
185 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
186 ptr = read_chunk(ptr, (void**)&shader->binary.code,
187 &shader->binary.code_size);
188 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
189 &shader->binary.rodata_size);
190 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
191 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
192 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
193 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
194
195 return true;
196 }
197
198 /**
199 * Insert a shader into the cache. It's assumed the shader is not in the cache.
200 * Use si_shader_cache_load_shader before calling this.
201 *
202 * Returns false on failure, in which case the ir_binary should be freed.
203 */
204 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
205 struct si_shader *shader,
206 bool insert_into_disk_cache)
207 {
208 void *hw_binary;
209 struct hash_entry *entry;
210 uint8_t key[CACHE_KEY_SIZE];
211
212 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
213 if (entry)
214 return false; /* already added */
215
216 hw_binary = si_get_shader_binary(shader);
217 if (!hw_binary)
218 return false;
219
220 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
221 hw_binary) == NULL) {
222 FREE(hw_binary);
223 return false;
224 }
225
226 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
227 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
228 *((uint32_t *)ir_binary), key);
229 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
230 *((uint32_t *) hw_binary), NULL);
231 }
232
233 return true;
234 }
235
236 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
237 struct si_shader *shader)
238 {
239 struct hash_entry *entry =
240 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
241 if (!entry) {
242 if (sscreen->disk_shader_cache) {
243 unsigned char sha1[CACHE_KEY_SIZE];
244 size_t tg_size = *((uint32_t *) ir_binary);
245
246 disk_cache_compute_key(sscreen->disk_shader_cache,
247 ir_binary, tg_size, sha1);
248
249 size_t binary_size;
250 uint8_t *buffer =
251 disk_cache_get(sscreen->disk_shader_cache,
252 sha1, &binary_size);
253 if (!buffer)
254 return false;
255
256 if (binary_size < sizeof(uint32_t) ||
257 *((uint32_t*)buffer) != binary_size) {
258 /* Something has gone wrong discard the item
259 * from the cache and rebuild/link from
260 * source.
261 */
262 assert(!"Invalid radeonsi shader disk cache "
263 "item!");
264
265 disk_cache_remove(sscreen->disk_shader_cache,
266 sha1);
267 free(buffer);
268
269 return false;
270 }
271
272 if (!si_load_shader_binary(shader, buffer)) {
273 free(buffer);
274 return false;
275 }
276 free(buffer);
277
278 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
279 shader, false))
280 FREE(ir_binary);
281 } else {
282 return false;
283 }
284 } else {
285 if (si_load_shader_binary(shader, entry->data))
286 FREE(ir_binary);
287 else
288 return false;
289 }
290 p_atomic_inc(&sscreen->num_shader_cache_hits);
291 return true;
292 }
293
294 static uint32_t si_shader_cache_key_hash(const void *key)
295 {
296 /* The first dword is the key size. */
297 return util_hash_crc32(key, *(uint32_t*)key);
298 }
299
300 static bool si_shader_cache_key_equals(const void *a, const void *b)
301 {
302 uint32_t *keya = (uint32_t*)a;
303 uint32_t *keyb = (uint32_t*)b;
304
305 /* The first dword is the key size. */
306 if (*keya != *keyb)
307 return false;
308
309 return memcmp(keya, keyb, *keya) == 0;
310 }
311
312 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
313 {
314 FREE((void*)entry->key);
315 FREE(entry->data);
316 }
317
318 bool si_init_shader_cache(struct si_screen *sscreen)
319 {
320 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
321 sscreen->shader_cache =
322 _mesa_hash_table_create(NULL,
323 si_shader_cache_key_hash,
324 si_shader_cache_key_equals);
325
326 return sscreen->shader_cache != NULL;
327 }
328
329 void si_destroy_shader_cache(struct si_screen *sscreen)
330 {
331 if (sscreen->shader_cache)
332 _mesa_hash_table_destroy(sscreen->shader_cache,
333 si_destroy_shader_cache_entry);
334 mtx_destroy(&sscreen->shader_cache_mutex);
335 }
336
337 /* SHADER STATES */
338
339 static void si_set_tesseval_regs(struct si_screen *sscreen,
340 struct si_shader_selector *tes,
341 struct si_pm4_state *pm4)
342 {
343 struct tgsi_shader_info *info = &tes->info;
344 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
345 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
346 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
347 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
348 unsigned type, partitioning, topology, distribution_mode;
349
350 switch (tes_prim_mode) {
351 case PIPE_PRIM_LINES:
352 type = V_028B6C_TESS_ISOLINE;
353 break;
354 case PIPE_PRIM_TRIANGLES:
355 type = V_028B6C_TESS_TRIANGLE;
356 break;
357 case PIPE_PRIM_QUADS:
358 type = V_028B6C_TESS_QUAD;
359 break;
360 default:
361 assert(0);
362 return;
363 }
364
365 switch (tes_spacing) {
366 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
367 partitioning = V_028B6C_PART_FRAC_ODD;
368 break;
369 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
370 partitioning = V_028B6C_PART_FRAC_EVEN;
371 break;
372 case PIPE_TESS_SPACING_EQUAL:
373 partitioning = V_028B6C_PART_INTEGER;
374 break;
375 default:
376 assert(0);
377 return;
378 }
379
380 if (tes_point_mode)
381 topology = V_028B6C_OUTPUT_POINT;
382 else if (tes_prim_mode == PIPE_PRIM_LINES)
383 topology = V_028B6C_OUTPUT_LINE;
384 else if (tes_vertex_order_cw)
385 /* for some reason, this must be the other way around */
386 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
387 else
388 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
389
390 if (sscreen->has_distributed_tess) {
391 if (sscreen->info.family == CHIP_FIJI ||
392 sscreen->info.family >= CHIP_POLARIS10)
393 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
394 else
395 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
396 } else
397 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
398
399 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
400 S_028B6C_TYPE(type) |
401 S_028B6C_PARTITIONING(partitioning) |
402 S_028B6C_TOPOLOGY(topology) |
403 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
404 }
405
406 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
407 * whether the "fractional odd" tessellation spacing is used.
408 *
409 * Possible VGT configurations and which state should set the register:
410 *
411 * Reg set in | VGT shader configuration | Value
412 * ------------------------------------------------------
413 * VS as VS | VS | 30
414 * VS as ES | ES -> GS -> VS | 30
415 * TES as VS | LS -> HS -> VS | 14 or 30
416 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
417 *
418 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
419 */
420 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
421 struct si_shader_selector *sel,
422 struct si_shader *shader,
423 struct si_pm4_state *pm4)
424 {
425 unsigned type = sel->type;
426
427 if (sscreen->info.family < CHIP_POLARIS10)
428 return;
429
430 /* VS as VS, or VS as ES: */
431 if ((type == PIPE_SHADER_VERTEX &&
432 (!shader ||
433 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
434 /* TES as VS, or TES as ES: */
435 type == PIPE_SHADER_TESS_EVAL) {
436 unsigned vtx_reuse_depth = 30;
437
438 if (type == PIPE_SHADER_TESS_EVAL &&
439 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
440 PIPE_TESS_SPACING_FRACTIONAL_ODD)
441 vtx_reuse_depth = 14;
442
443 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
444 vtx_reuse_depth);
445 }
446 }
447
448 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
449 {
450 if (shader->pm4)
451 si_pm4_clear_state(shader->pm4);
452 else
453 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
454
455 if (shader->pm4) {
456 shader->pm4->shader = shader;
457 return shader->pm4;
458 } else {
459 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
460 return NULL;
461 }
462 }
463
464 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
465 {
466 /* Add the pointer to VBO descriptors. */
467 if (HAVE_32BIT_POINTERS) {
468 return num_always_on_user_sgprs + 1;
469 } else {
470 assert(num_always_on_user_sgprs % 2 == 0);
471 return num_always_on_user_sgprs + 2;
472 }
473 }
474
475 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
476 {
477 struct si_pm4_state *pm4;
478 unsigned vgpr_comp_cnt;
479 uint64_t va;
480
481 assert(sscreen->info.chip_class <= VI);
482
483 pm4 = si_get_shader_pm4_state(shader);
484 if (!pm4)
485 return;
486
487 va = shader->bo->gpu_address;
488 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
489
490 /* We need at least 2 components for LS.
491 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
492 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
493 */
494 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
495
496 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
497 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
498
499 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
500 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
501 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
502 S_00B528_DX10_CLAMP(1) |
503 S_00B528_FLOAT_MODE(shader->config.float_mode);
504 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
505 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
506 }
507
508 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
509 {
510 struct si_pm4_state *pm4;
511 uint64_t va;
512 unsigned ls_vgpr_comp_cnt = 0;
513
514 pm4 = si_get_shader_pm4_state(shader);
515 if (!pm4)
516 return;
517
518 va = shader->bo->gpu_address;
519 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
520
521 if (sscreen->info.chip_class >= GFX9) {
522 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
523 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
524
525 /* We need at least 2 components for LS.
526 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
527 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
528 */
529 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
530
531 unsigned num_user_sgprs =
532 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
533
534 shader->config.rsrc2 =
535 S_00B42C_USER_SGPR(num_user_sgprs) |
536 S_00B42C_USER_SGPR_MSB(num_user_sgprs >> 5) |
537 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
538 } else {
539 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
540 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
541
542 shader->config.rsrc2 =
543 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
544 S_00B42C_OC_LDS_EN(1) |
545 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
546 }
547
548 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
549 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
550 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
551 S_00B428_DX10_CLAMP(1) |
552 S_00B428_FLOAT_MODE(shader->config.float_mode) |
553 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
554
555 if (sscreen->info.chip_class <= VI) {
556 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
557 shader->config.rsrc2);
558 }
559 }
560
561 static void si_emit_shader_es(struct si_context *sctx)
562 {
563 struct si_shader *shader = sctx->queued.named.es->shader;
564
565 if (!shader)
566 return;
567
568 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
569 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
570 shader->selector->esgs_itemsize / 4);
571 }
572
573 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
574 {
575 struct si_pm4_state *pm4;
576 unsigned num_user_sgprs;
577 unsigned vgpr_comp_cnt;
578 uint64_t va;
579 unsigned oc_lds_en;
580
581 assert(sscreen->info.chip_class <= VI);
582
583 pm4 = si_get_shader_pm4_state(shader);
584 if (!pm4)
585 return;
586
587 pm4->atom.emit = si_emit_shader_es;
588 va = shader->bo->gpu_address;
589 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
590
591 if (shader->selector->type == PIPE_SHADER_VERTEX) {
592 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
593 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
594 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
595 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
596 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
597 num_user_sgprs = SI_TES_NUM_USER_SGPR;
598 } else
599 unreachable("invalid shader selector type");
600
601 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
602
603 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
604 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
605 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
606 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
607 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
608 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
609 S_00B328_DX10_CLAMP(1) |
610 S_00B328_FLOAT_MODE(shader->config.float_mode));
611 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
612 S_00B32C_USER_SGPR(num_user_sgprs) |
613 S_00B32C_OC_LDS_EN(oc_lds_en) |
614 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
615
616 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
617 si_set_tesseval_regs(sscreen, shader->selector, pm4);
618
619 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
620 }
621
622 static unsigned si_conv_prim_to_gs_out(unsigned mode)
623 {
624 static const int prim_conv[] = {
625 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
626 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
627 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
628 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
629 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
630 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
631 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
632 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
633 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
634 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
635 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
636 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
637 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
638 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
639 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
640 };
641 assert(mode < ARRAY_SIZE(prim_conv));
642
643 return prim_conv[mode];
644 }
645
646 struct gfx9_gs_info {
647 unsigned es_verts_per_subgroup;
648 unsigned gs_prims_per_subgroup;
649 unsigned gs_inst_prims_in_subgroup;
650 unsigned max_prims_per_subgroup;
651 unsigned lds_size;
652 };
653
654 static void gfx9_get_gs_info(struct si_shader_selector *es,
655 struct si_shader_selector *gs,
656 struct gfx9_gs_info *out)
657 {
658 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
659 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
660 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
661 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
662
663 /* All these are in dwords: */
664 /* We can't allow using the whole LDS, because GS waves compete with
665 * other shader stages for LDS space. */
666 const unsigned max_lds_size = 8 * 1024;
667 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
668 unsigned esgs_lds_size;
669
670 /* All these are per subgroup: */
671 const unsigned max_out_prims = 32 * 1024;
672 const unsigned max_es_verts = 255;
673 const unsigned ideal_gs_prims = 64;
674 unsigned max_gs_prims, gs_prims;
675 unsigned min_es_verts, es_verts, worst_case_es_verts;
676
677 if (uses_adjacency || gs_num_invocations > 1)
678 max_gs_prims = 127 / gs_num_invocations;
679 else
680 max_gs_prims = 255;
681
682 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
683 * Make sure we don't go over the maximum value.
684 */
685 if (gs->gs_max_out_vertices > 0) {
686 max_gs_prims = MIN2(max_gs_prims,
687 max_out_prims /
688 (gs->gs_max_out_vertices * gs_num_invocations));
689 }
690 assert(max_gs_prims > 0);
691
692 /* If the primitive has adjacency, halve the number of vertices
693 * that will be reused in multiple primitives.
694 */
695 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
696
697 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
698 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
699
700 /* Compute ESGS LDS size based on the worst case number of ES vertices
701 * needed to create the target number of GS prims per subgroup.
702 */
703 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
704
705 /* If total LDS usage is too big, refactor partitions based on ratio
706 * of ESGS item sizes.
707 */
708 if (esgs_lds_size > max_lds_size) {
709 /* Our target GS Prims Per Subgroup was too large. Calculate
710 * the maximum number of GS Prims Per Subgroup that will fit
711 * into LDS, capped by the maximum that the hardware can support.
712 */
713 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
714 max_gs_prims);
715 assert(gs_prims > 0);
716 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
717 max_es_verts);
718
719 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
720 assert(esgs_lds_size <= max_lds_size);
721 }
722
723 /* Now calculate remaining ESGS information. */
724 if (esgs_lds_size)
725 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
726 else
727 es_verts = max_es_verts;
728
729 /* Vertices for adjacency primitives are not always reused, so restore
730 * it for ES_VERTS_PER_SUBGRP.
731 */
732 min_es_verts = gs->gs_input_verts_per_prim;
733
734 /* For normal primitives, the VGT only checks if they are past the ES
735 * verts per subgroup after allocating a full GS primitive and if they
736 * are, kick off a new subgroup. But if those additional ES verts are
737 * unique (e.g. not reused) we need to make sure there is enough LDS
738 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
739 */
740 es_verts -= min_es_verts - 1;
741
742 out->es_verts_per_subgroup = es_verts;
743 out->gs_prims_per_subgroup = gs_prims;
744 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
745 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
746 gs->gs_max_out_vertices;
747 out->lds_size = align(esgs_lds_size, 128) / 128;
748
749 assert(out->max_prims_per_subgroup <= max_out_prims);
750 }
751
752 static void si_emit_shader_gs(struct si_context *sctx)
753 {
754 struct si_shader *shader = sctx->queued.named.gs->shader;
755 if (!shader)
756 return;
757
758 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
759 * R_028A68_VGT_GSVS_RING_OFFSET_3, R_028A6C_VGT_GS_OUT_PRIM_TYPE */
760 radeon_opt_set_context_reg4(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
761 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
762 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
763 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
764 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3,
765 shader->ctx_reg.gs.vgt_gs_out_prim_type);
766
767
768 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
769 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
770 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
771 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
772
773 /* R_028B38_VGT_GS_MAX_VERT_OUT */
774 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
775 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
776 shader->ctx_reg.gs.vgt_gs_max_vert_out);
777
778 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
779 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
780 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
781 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
782 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
783 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
784 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
785 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
786
787 /* R_028B90_VGT_GS_INSTANCE_CNT */
788 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
789 SI_TRACKED_VGT_GS_INSTANCE_CNT,
790 shader->ctx_reg.gs.vgt_gs_instance_cnt);
791
792 if (sctx->chip_class >= GFX9) {
793 /* R_028A44_VGT_GS_ONCHIP_CNTL */
794 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
795 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
796 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
797 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
798 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
799 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
800 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
801 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
802 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
803 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
804 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
805 }
806 }
807
808 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
809 {
810 struct si_shader_selector *sel = shader->selector;
811 const ubyte *num_components = sel->info.num_stream_output_components;
812 unsigned gs_num_invocations = sel->gs_num_invocations;
813 struct si_pm4_state *pm4;
814 uint64_t va;
815 unsigned max_stream = sel->max_gs_stream;
816 unsigned offset;
817
818 pm4 = si_get_shader_pm4_state(shader);
819 if (!pm4)
820 return;
821
822 pm4->atom.emit = si_emit_shader_gs;
823
824 offset = num_components[0] * sel->gs_max_out_vertices;
825 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
826
827 if (max_stream >= 1)
828 offset += num_components[1] * sel->gs_max_out_vertices;
829 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
830
831 if (max_stream >= 2)
832 offset += num_components[2] * sel->gs_max_out_vertices;
833 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
834
835 shader->ctx_reg.gs.vgt_gs_out_prim_type =
836 si_conv_prim_to_gs_out(sel->gs_output_prim);
837
838 if (max_stream >= 3)
839 offset += num_components[3] * sel->gs_max_out_vertices;
840 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
841
842 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
843 assert(offset < (1 << 15));
844
845 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
846
847 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
848 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
849 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
850 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
851
852 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
853 S_028B90_ENABLE(gs_num_invocations > 0);
854
855 va = shader->bo->gpu_address;
856 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
857
858 if (sscreen->info.chip_class >= GFX9) {
859 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
860 unsigned es_type = shader->key.part.gs.es->type;
861 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
862 struct gfx9_gs_info gs_info;
863
864 if (es_type == PIPE_SHADER_VERTEX)
865 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
866 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
867 else if (es_type == PIPE_SHADER_TESS_EVAL)
868 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
869 else
870 unreachable("invalid shader selector type");
871
872 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
873 * VGPR[0:4] are always loaded.
874 */
875 if (sel->info.uses_invocationid)
876 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
877 else if (sel->info.uses_primid)
878 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
879 else if (input_prim >= PIPE_PRIM_TRIANGLES)
880 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
881 else
882 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
883
884 unsigned num_user_sgprs;
885 if (es_type == PIPE_SHADER_VERTEX)
886 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
887 else
888 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
889
890 gfx9_get_gs_info(shader->key.part.gs.es, sel, &gs_info);
891
892 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
893 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
894
895 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
896 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
897 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
898 S_00B228_DX10_CLAMP(1) |
899 S_00B228_FLOAT_MODE(shader->config.float_mode) |
900 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
901 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
902 S_00B22C_USER_SGPR(num_user_sgprs) |
903 S_00B22C_USER_SGPR_MSB(num_user_sgprs >> 5) |
904 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
905 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
906 S_00B22C_LDS_SIZE(gs_info.lds_size) |
907 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
908
909 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
910 S_028A44_ES_VERTS_PER_SUBGRP(gs_info.es_verts_per_subgroup) |
911 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info.gs_prims_per_subgroup) |
912 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info.gs_inst_prims_in_subgroup);
913 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
914 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info.max_prims_per_subgroup);
915 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
916 shader->key.part.gs.es->esgs_itemsize / 4;
917
918 if (es_type == PIPE_SHADER_TESS_EVAL)
919 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
920
921 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
922 NULL, pm4);
923 } else {
924 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
925 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
926
927 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
928 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
929 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
930 S_00B228_DX10_CLAMP(1) |
931 S_00B228_FLOAT_MODE(shader->config.float_mode));
932 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
933 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
934 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
935 }
936 }
937
938 /**
939 * Compute the state for \p shader, which will run as a vertex shader on the
940 * hardware.
941 *
942 * If \p gs is non-NULL, it points to the geometry shader for which this shader
943 * is the copy shader.
944 */
945 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
946 struct si_shader_selector *gs)
947 {
948 const struct tgsi_shader_info *info = &shader->selector->info;
949 struct si_pm4_state *pm4;
950 unsigned num_user_sgprs;
951 unsigned nparams, vgpr_comp_cnt;
952 uint64_t va;
953 unsigned oc_lds_en;
954 unsigned window_space =
955 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
956 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
957
958 pm4 = si_get_shader_pm4_state(shader);
959 if (!pm4)
960 return;
961
962 /* We always write VGT_GS_MODE in the VS state, because every switch
963 * between different shader pipelines involving a different GS or no
964 * GS at all involves a switch of the VS (different GS use different
965 * copy shaders). On the other hand, when the API switches from a GS to
966 * no GS and then back to the same GS used originally, the GS state is
967 * not sent again.
968 */
969 if (!gs) {
970 unsigned mode = V_028A40_GS_OFF;
971
972 /* PrimID needs GS scenario A. */
973 if (enable_prim_id)
974 mode = V_028A40_GS_SCENARIO_A;
975
976 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, S_028A40_MODE(mode));
977 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
978 } else {
979 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
980 ac_vgt_gs_mode(gs->gs_max_out_vertices,
981 sscreen->info.chip_class));
982 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
983 }
984
985 if (sscreen->info.chip_class <= VI) {
986 /* Reuse needs to be set off if we write oViewport. */
987 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF,
988 S_028AB4_REUSE_OFF(info->writes_viewport_index));
989 }
990
991 va = shader->bo->gpu_address;
992 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
993
994 if (gs) {
995 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
996 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
997 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
998 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
999 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1000 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1001 */
1002 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
1003
1004 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1005 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1006 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1007 } else {
1008 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1009 }
1010 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1011 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1012 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1013 } else
1014 unreachable("invalid shader selector type");
1015
1016 /* VS is required to export at least one param. */
1017 nparams = MAX2(shader->info.nr_param_exports, 1);
1018 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
1019 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
1020
1021 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
1022 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1023 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1024 V_02870C_SPI_SHADER_4COMP :
1025 V_02870C_SPI_SHADER_NONE) |
1026 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1027 V_02870C_SPI_SHADER_4COMP :
1028 V_02870C_SPI_SHADER_NONE) |
1029 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1030 V_02870C_SPI_SHADER_4COMP :
1031 V_02870C_SPI_SHADER_NONE));
1032
1033 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1034
1035 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1036 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1037 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
1038 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
1039 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
1040 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1041 S_00B128_DX10_CLAMP(1) |
1042 S_00B128_FLOAT_MODE(shader->config.float_mode));
1043 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
1044 S_00B12C_USER_SGPR(num_user_sgprs) |
1045 S_00B12C_OC_LDS_EN(oc_lds_en) |
1046 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1047 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1048 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1049 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1050 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
1051 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1052 if (window_space)
1053 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
1054 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
1055 else
1056 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
1057 S_028818_VTX_W0_FMT(1) |
1058 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1059 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1060 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
1061
1062 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1063 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1064
1065 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1066 }
1067
1068 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1069 {
1070 struct tgsi_shader_info *info = &ps->selector->info;
1071 unsigned num_colors = !!(info->colors_read & 0x0f) +
1072 !!(info->colors_read & 0xf0);
1073 unsigned num_interp = ps->selector->info.num_inputs +
1074 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1075
1076 assert(num_interp <= 32);
1077 return MIN2(num_interp, 32);
1078 }
1079
1080 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1081 {
1082 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1083 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1084
1085 /* If the i-th target format is set, all previous target formats must
1086 * be non-zero to avoid hangs.
1087 */
1088 for (i = 0; i < num_targets; i++)
1089 if (!(value & (0xf << (i * 4))))
1090 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1091
1092 return value;
1093 }
1094
1095 static void si_shader_ps(struct si_shader *shader)
1096 {
1097 struct tgsi_shader_info *info = &shader->selector->info;
1098 struct si_pm4_state *pm4;
1099 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1100 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1101 uint64_t va;
1102 unsigned input_ena = shader->config.spi_ps_input_ena;
1103
1104 /* we need to enable at least one of them, otherwise we hang the GPU */
1105 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1106 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1107 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1108 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1109 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1110 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1111 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1112 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1113 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1114 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1115 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1116 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1117 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1118 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1119
1120 /* Validate interpolation optimization flags (read as implications). */
1121 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1122 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1123 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1124 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1125 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1126 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1127 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1128 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1129 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1130 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1131 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1132 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1133 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1134 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1135 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1136 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1137 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1138 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1139
1140 /* Validate cases when the optimizations are off (read as implications). */
1141 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1142 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1143 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1144 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1145 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1146 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1147
1148 pm4 = si_get_shader_pm4_state(shader);
1149 if (!pm4)
1150 return;
1151
1152 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1153 * Possible vaules:
1154 * 0 -> Position = pixel center
1155 * 1 -> Position = pixel centroid
1156 * 2 -> Position = at sample position
1157 *
1158 * From GLSL 4.5 specification, section 7.1:
1159 * "The variable gl_FragCoord is available as an input variable from
1160 * within fragment shaders and it holds the window relative coordinates
1161 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1162 * value can be for any location within the pixel, or one of the
1163 * fragment samples. The use of centroid does not further restrict
1164 * this value to be inside the current primitive."
1165 *
1166 * Meaning that centroid has no effect and we can return anything within
1167 * the pixel. Thus, return the value at sample position, because that's
1168 * the most accurate one shaders can get.
1169 */
1170 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1171
1172 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1173 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1174 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1175
1176 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1177 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1178
1179 /* Ensure that some export memory is always allocated, for two reasons:
1180 *
1181 * 1) Correctness: The hardware ignores the EXEC mask if no export
1182 * memory is allocated, so KILL and alpha test do not work correctly
1183 * without this.
1184 * 2) Performance: Every shader needs at least a NULL export, even when
1185 * it writes no color/depth output. The NULL export instruction
1186 * stalls without this setting.
1187 *
1188 * Don't add this to CB_SHADER_MASK.
1189 */
1190 if (!spi_shader_col_format &&
1191 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1192 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1193
1194 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
1195 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
1196 shader->config.spi_ps_input_addr);
1197
1198 /* Set interpolation controls. */
1199 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1200
1201 /* Set registers. */
1202 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1203 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
1204
1205 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
1206 ac_get_spi_shader_z_format(info->writes_z,
1207 info->writes_stencil,
1208 info->writes_samplemask));
1209
1210 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
1211 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
1212
1213 va = shader->bo->gpu_address;
1214 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1215 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1216 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1217
1218 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
1219 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1220 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
1221 S_00B028_DX10_CLAMP(1) |
1222 S_00B028_FLOAT_MODE(shader->config.float_mode));
1223 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1224 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1225 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1226 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1227 }
1228
1229 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1230 struct si_shader *shader)
1231 {
1232 switch (shader->selector->type) {
1233 case PIPE_SHADER_VERTEX:
1234 if (shader->key.as_ls)
1235 si_shader_ls(sscreen, shader);
1236 else if (shader->key.as_es)
1237 si_shader_es(sscreen, shader);
1238 else
1239 si_shader_vs(sscreen, shader, NULL);
1240 break;
1241 case PIPE_SHADER_TESS_CTRL:
1242 si_shader_hs(sscreen, shader);
1243 break;
1244 case PIPE_SHADER_TESS_EVAL:
1245 if (shader->key.as_es)
1246 si_shader_es(sscreen, shader);
1247 else
1248 si_shader_vs(sscreen, shader, NULL);
1249 break;
1250 case PIPE_SHADER_GEOMETRY:
1251 si_shader_gs(sscreen, shader);
1252 break;
1253 case PIPE_SHADER_FRAGMENT:
1254 si_shader_ps(shader);
1255 break;
1256 default:
1257 assert(0);
1258 }
1259 }
1260
1261 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1262 {
1263 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1264 if (sctx->queued.named.dsa)
1265 return sctx->queued.named.dsa->alpha_func;
1266
1267 return PIPE_FUNC_ALWAYS;
1268 }
1269
1270 static void si_shader_selector_key_vs(struct si_context *sctx,
1271 struct si_shader_selector *vs,
1272 struct si_shader_key *key,
1273 struct si_vs_prolog_bits *prolog_key)
1274 {
1275 if (!sctx->vertex_elements ||
1276 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS])
1277 return;
1278
1279 prolog_key->instance_divisor_is_one =
1280 sctx->vertex_elements->instance_divisor_is_one;
1281 prolog_key->instance_divisor_is_fetched =
1282 sctx->vertex_elements->instance_divisor_is_fetched;
1283
1284 /* Prefer a monolithic shader to allow scheduling divisions around
1285 * VBO loads. */
1286 if (prolog_key->instance_divisor_is_fetched)
1287 key->opt.prefer_mono = 1;
1288
1289 unsigned count = MIN2(vs->info.num_inputs,
1290 sctx->vertex_elements->count);
1291 memcpy(key->mono.vs_fix_fetch, sctx->vertex_elements->fix_fetch, count);
1292 }
1293
1294 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1295 struct si_shader_selector *vs,
1296 struct si_shader_key *key)
1297 {
1298 struct si_shader_selector *ps = sctx->ps_shader.cso;
1299
1300 key->opt.clip_disable =
1301 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1302 (vs->info.clipdist_writemask ||
1303 vs->info.writes_clipvertex) &&
1304 !vs->info.culldist_writemask;
1305
1306 /* Find out if PS is disabled. */
1307 bool ps_disabled = true;
1308 if (ps) {
1309 const struct si_state_blend *blend = sctx->queued.named.blend;
1310 bool alpha_to_coverage = blend && blend->alpha_to_coverage;
1311 bool ps_modifies_zs = ps->info.uses_kill ||
1312 ps->info.writes_z ||
1313 ps->info.writes_stencil ||
1314 ps->info.writes_samplemask ||
1315 alpha_to_coverage ||
1316 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1317 unsigned ps_colormask = si_get_total_colormask(sctx);
1318
1319 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1320 (!ps_colormask &&
1321 !ps_modifies_zs &&
1322 !ps->info.writes_memory);
1323 }
1324
1325 /* Find out which VS outputs aren't used by the PS. */
1326 uint64_t outputs_written = vs->outputs_written_before_ps;
1327 uint64_t inputs_read = 0;
1328
1329 /* Ignore outputs that are not passed from VS to PS. */
1330 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1331 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1332 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1333
1334 if (!ps_disabled) {
1335 inputs_read = ps->inputs_read;
1336 }
1337
1338 uint64_t linked = outputs_written & inputs_read;
1339
1340 key->opt.kill_outputs = ~linked & outputs_written;
1341 }
1342
1343 /* Compute the key for the hw shader variant */
1344 static inline void si_shader_selector_key(struct pipe_context *ctx,
1345 struct si_shader_selector *sel,
1346 struct si_shader_key *key)
1347 {
1348 struct si_context *sctx = (struct si_context *)ctx;
1349
1350 memset(key, 0, sizeof(*key));
1351
1352 switch (sel->type) {
1353 case PIPE_SHADER_VERTEX:
1354 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1355
1356 if (sctx->tes_shader.cso)
1357 key->as_ls = 1;
1358 else if (sctx->gs_shader.cso)
1359 key->as_es = 1;
1360 else {
1361 si_shader_selector_key_hw_vs(sctx, sel, key);
1362
1363 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1364 key->mono.u.vs_export_prim_id = 1;
1365 }
1366 break;
1367 case PIPE_SHADER_TESS_CTRL:
1368 if (sctx->chip_class >= GFX9) {
1369 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1370 key, &key->part.tcs.ls_prolog);
1371 key->part.tcs.ls = sctx->vs_shader.cso;
1372
1373 /* When the LS VGPR fix is needed, monolithic shaders
1374 * can:
1375 * - avoid initializing EXEC in both the LS prolog
1376 * and the LS main part when !vs_needs_prolog
1377 * - remove the fixup for unused input VGPRs
1378 */
1379 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1380
1381 /* The LS output / HS input layout can be communicated
1382 * directly instead of via user SGPRs for merged LS-HS.
1383 * The LS VGPR fix prefers this too.
1384 */
1385 key->opt.prefer_mono = 1;
1386 }
1387
1388 key->part.tcs.epilog.prim_mode =
1389 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1390 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1391 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1392 key->part.tcs.epilog.tes_reads_tess_factors =
1393 sctx->tes_shader.cso->info.reads_tess_factors;
1394
1395 if (sel == sctx->fixed_func_tcs_shader.cso)
1396 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1397 break;
1398 case PIPE_SHADER_TESS_EVAL:
1399 if (sctx->gs_shader.cso)
1400 key->as_es = 1;
1401 else {
1402 si_shader_selector_key_hw_vs(sctx, sel, key);
1403
1404 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1405 key->mono.u.vs_export_prim_id = 1;
1406 }
1407 break;
1408 case PIPE_SHADER_GEOMETRY:
1409 if (sctx->chip_class >= GFX9) {
1410 if (sctx->tes_shader.cso) {
1411 key->part.gs.es = sctx->tes_shader.cso;
1412 } else {
1413 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1414 key, &key->part.gs.vs_prolog);
1415 key->part.gs.es = sctx->vs_shader.cso;
1416 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1417 }
1418
1419 /* Merged ES-GS can have unbalanced wave usage.
1420 *
1421 * ES threads are per-vertex, while GS threads are
1422 * per-primitive. So without any amplification, there
1423 * are fewer GS threads than ES threads, which can result
1424 * in empty (no-op) GS waves. With too much amplification,
1425 * there are more GS threads than ES threads, which
1426 * can result in empty (no-op) ES waves.
1427 *
1428 * Non-monolithic shaders are implemented by setting EXEC
1429 * at the beginning of shader parts, and don't jump to
1430 * the end if EXEC is 0.
1431 *
1432 * Monolithic shaders use conditional blocks, so they can
1433 * jump and skip empty waves of ES or GS. So set this to
1434 * always use optimized variants, which are monolithic.
1435 */
1436 key->opt.prefer_mono = 1;
1437 }
1438 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1439 break;
1440 case PIPE_SHADER_FRAGMENT: {
1441 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1442 struct si_state_blend *blend = sctx->queued.named.blend;
1443
1444 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1445 sel->info.colors_written == 0x1)
1446 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1447
1448 if (blend) {
1449 /* Select the shader color format based on whether
1450 * blending or alpha are needed.
1451 */
1452 key->part.ps.epilog.spi_shader_col_format =
1453 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1454 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1455 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1456 sctx->framebuffer.spi_shader_col_format_blend) |
1457 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1458 sctx->framebuffer.spi_shader_col_format_alpha) |
1459 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1460 sctx->framebuffer.spi_shader_col_format);
1461 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1462
1463 /* The output for dual source blending should have
1464 * the same format as the first output.
1465 */
1466 if (blend->dual_src_blend)
1467 key->part.ps.epilog.spi_shader_col_format |=
1468 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1469 } else
1470 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1471
1472 /* If alpha-to-coverage is enabled, we have to export alpha
1473 * even if there is no color buffer.
1474 */
1475 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1476 blend && blend->alpha_to_coverage)
1477 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1478
1479 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1480 * to the range supported by the type if a channel has less
1481 * than 16 bits and the export format is 16_ABGR.
1482 */
1483 if (sctx->chip_class <= CIK && sctx->family != CHIP_HAWAII) {
1484 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1485 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1486 }
1487
1488 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1489 if (!key->part.ps.epilog.last_cbuf) {
1490 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1491 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1492 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1493 }
1494
1495 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1496 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1497
1498 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1499 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1500
1501 if (sctx->queued.named.blend) {
1502 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1503 rs->multisample_enable;
1504 }
1505
1506 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1507 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1508 (is_line && rs->line_smooth)) &&
1509 sctx->framebuffer.nr_samples <= 1;
1510 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1511
1512 if (sctx->ps_iter_samples > 1 &&
1513 sel->info.reads_samplemask) {
1514 key->part.ps.prolog.samplemask_log_ps_iter =
1515 util_logbase2(sctx->ps_iter_samples);
1516 }
1517
1518 if (rs->force_persample_interp &&
1519 rs->multisample_enable &&
1520 sctx->framebuffer.nr_samples > 1 &&
1521 sctx->ps_iter_samples > 1) {
1522 key->part.ps.prolog.force_persp_sample_interp =
1523 sel->info.uses_persp_center ||
1524 sel->info.uses_persp_centroid;
1525
1526 key->part.ps.prolog.force_linear_sample_interp =
1527 sel->info.uses_linear_center ||
1528 sel->info.uses_linear_centroid;
1529 } else if (rs->multisample_enable &&
1530 sctx->framebuffer.nr_samples > 1) {
1531 key->part.ps.prolog.bc_optimize_for_persp =
1532 sel->info.uses_persp_center &&
1533 sel->info.uses_persp_centroid;
1534 key->part.ps.prolog.bc_optimize_for_linear =
1535 sel->info.uses_linear_center &&
1536 sel->info.uses_linear_centroid;
1537 } else {
1538 /* Make sure SPI doesn't compute more than 1 pair
1539 * of (i,j), which is the optimization here. */
1540 key->part.ps.prolog.force_persp_center_interp =
1541 sel->info.uses_persp_center +
1542 sel->info.uses_persp_centroid +
1543 sel->info.uses_persp_sample > 1;
1544
1545 key->part.ps.prolog.force_linear_center_interp =
1546 sel->info.uses_linear_center +
1547 sel->info.uses_linear_centroid +
1548 sel->info.uses_linear_sample > 1;
1549
1550 if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
1551 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1552 }
1553
1554 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1555
1556 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1557 if (sctx->ps_uses_fbfetch) {
1558 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
1559 struct pipe_resource *tex = cb0->texture;
1560
1561 /* 1D textures are allocated and used as 2D on GFX9. */
1562 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
1563 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
1564 (tex->target == PIPE_TEXTURE_1D ||
1565 tex->target == PIPE_TEXTURE_1D_ARRAY);
1566 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
1567 tex->target == PIPE_TEXTURE_2D_ARRAY ||
1568 tex->target == PIPE_TEXTURE_CUBE ||
1569 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
1570 tex->target == PIPE_TEXTURE_3D;
1571 }
1572 break;
1573 }
1574 default:
1575 assert(0);
1576 }
1577
1578 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
1579 memset(&key->opt, 0, sizeof(key->opt));
1580 }
1581
1582 static void si_build_shader_variant(struct si_shader *shader,
1583 int thread_index,
1584 bool low_priority)
1585 {
1586 struct si_shader_selector *sel = shader->selector;
1587 struct si_screen *sscreen = sel->screen;
1588 struct ac_llvm_compiler *compiler;
1589 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1590 int r;
1591
1592 if (thread_index >= 0) {
1593 if (low_priority) {
1594 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
1595 compiler = &sscreen->compiler_lowp[thread_index];
1596 } else {
1597 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
1598 compiler = &sscreen->compiler[thread_index];
1599 }
1600 if (!debug->async)
1601 debug = NULL;
1602 } else {
1603 assert(!low_priority);
1604 compiler = shader->compiler_ctx_state.compiler;
1605 }
1606
1607 r = si_shader_create(sscreen, compiler, shader, debug);
1608 if (unlikely(r)) {
1609 PRINT_ERR("Failed to build shader variant (type=%u) %d\n",
1610 sel->type, r);
1611 shader->compilation_failed = true;
1612 return;
1613 }
1614
1615 if (shader->compiler_ctx_state.is_debug_context) {
1616 FILE *f = open_memstream(&shader->shader_log,
1617 &shader->shader_log_size);
1618 if (f) {
1619 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1620 fclose(f);
1621 }
1622 }
1623
1624 si_shader_init_pm4_state(sscreen, shader);
1625 }
1626
1627 static void si_build_shader_variant_low_priority(void *job, int thread_index)
1628 {
1629 struct si_shader *shader = (struct si_shader *)job;
1630
1631 assert(thread_index >= 0);
1632
1633 si_build_shader_variant(shader, thread_index, true);
1634 }
1635
1636 static const struct si_shader_key zeroed;
1637
1638 static bool si_check_missing_main_part(struct si_screen *sscreen,
1639 struct si_shader_selector *sel,
1640 struct si_compiler_ctx_state *compiler_state,
1641 struct si_shader_key *key)
1642 {
1643 struct si_shader **mainp = si_get_main_shader_part(sel, key);
1644
1645 if (!*mainp) {
1646 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1647
1648 if (!main_part)
1649 return false;
1650
1651 /* We can leave the fence as permanently signaled because the
1652 * main part becomes visible globally only after it has been
1653 * compiled. */
1654 util_queue_fence_init(&main_part->ready);
1655
1656 main_part->selector = sel;
1657 main_part->key.as_es = key->as_es;
1658 main_part->key.as_ls = key->as_ls;
1659 main_part->is_monolithic = false;
1660
1661 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
1662 main_part, &compiler_state->debug) != 0) {
1663 FREE(main_part);
1664 return false;
1665 }
1666 *mainp = main_part;
1667 }
1668 return true;
1669 }
1670
1671 /* Select the hw shader variant depending on the current state. */
1672 static int si_shader_select_with_key(struct si_screen *sscreen,
1673 struct si_shader_ctx_state *state,
1674 struct si_compiler_ctx_state *compiler_state,
1675 struct si_shader_key *key,
1676 int thread_index)
1677 {
1678 struct si_shader_selector *sel = state->cso;
1679 struct si_shader_selector *previous_stage_sel = NULL;
1680 struct si_shader *current = state->current;
1681 struct si_shader *iter, *shader = NULL;
1682
1683 again:
1684 /* Check if we don't need to change anything.
1685 * This path is also used for most shaders that don't need multiple
1686 * variants, it will cost just a computation of the key and this
1687 * test. */
1688 if (likely(current &&
1689 memcmp(&current->key, key, sizeof(*key)) == 0)) {
1690 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
1691 if (current->is_optimized) {
1692 memset(&key->opt, 0, sizeof(key->opt));
1693 goto current_not_ready;
1694 }
1695
1696 util_queue_fence_wait(&current->ready);
1697 }
1698
1699 return current->compilation_failed ? -1 : 0;
1700 }
1701 current_not_ready:
1702
1703 /* This must be done before the mutex is locked, because async GS
1704 * compilation calls this function too, and therefore must enter
1705 * the mutex first.
1706 *
1707 * Only wait if we are in a draw call. Don't wait if we are
1708 * in a compiler thread.
1709 */
1710 if (thread_index < 0)
1711 util_queue_fence_wait(&sel->ready);
1712
1713 mtx_lock(&sel->mutex);
1714
1715 /* Find the shader variant. */
1716 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1717 /* Don't check the "current" shader. We checked it above. */
1718 if (current != iter &&
1719 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1720 mtx_unlock(&sel->mutex);
1721
1722 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
1723 /* If it's an optimized shader and its compilation has
1724 * been started but isn't done, use the unoptimized
1725 * shader so as not to cause a stall due to compilation.
1726 */
1727 if (iter->is_optimized) {
1728 memset(&key->opt, 0, sizeof(key->opt));
1729 goto again;
1730 }
1731
1732 util_queue_fence_wait(&iter->ready);
1733 }
1734
1735 if (iter->compilation_failed) {
1736 return -1; /* skip the draw call */
1737 }
1738
1739 state->current = iter;
1740 return 0;
1741 }
1742 }
1743
1744 /* Build a new shader. */
1745 shader = CALLOC_STRUCT(si_shader);
1746 if (!shader) {
1747 mtx_unlock(&sel->mutex);
1748 return -ENOMEM;
1749 }
1750
1751 util_queue_fence_init(&shader->ready);
1752
1753 shader->selector = sel;
1754 shader->key = *key;
1755 shader->compiler_ctx_state = *compiler_state;
1756
1757 /* If this is a merged shader, get the first shader's selector. */
1758 if (sscreen->info.chip_class >= GFX9) {
1759 if (sel->type == PIPE_SHADER_TESS_CTRL)
1760 previous_stage_sel = key->part.tcs.ls;
1761 else if (sel->type == PIPE_SHADER_GEOMETRY)
1762 previous_stage_sel = key->part.gs.es;
1763
1764 /* We need to wait for the previous shader. */
1765 if (previous_stage_sel && thread_index < 0)
1766 util_queue_fence_wait(&previous_stage_sel->ready);
1767 }
1768
1769 /* Compile the main shader part if it doesn't exist. This can happen
1770 * if the initial guess was wrong. */
1771 bool is_pure_monolithic =
1772 sscreen->use_monolithic_shaders ||
1773 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1774
1775 if (!is_pure_monolithic) {
1776 bool ok;
1777
1778 /* Make sure the main shader part is present. This is needed
1779 * for shaders that can be compiled as VS, LS, or ES, and only
1780 * one of them is compiled at creation.
1781 *
1782 * For merged shaders, check that the starting shader's main
1783 * part is present.
1784 */
1785 if (previous_stage_sel) {
1786 struct si_shader_key shader1_key = zeroed;
1787
1788 if (sel->type == PIPE_SHADER_TESS_CTRL)
1789 shader1_key.as_ls = 1;
1790 else if (sel->type == PIPE_SHADER_GEOMETRY)
1791 shader1_key.as_es = 1;
1792 else
1793 assert(0);
1794
1795 mtx_lock(&previous_stage_sel->mutex);
1796 ok = si_check_missing_main_part(sscreen,
1797 previous_stage_sel,
1798 compiler_state, &shader1_key);
1799 mtx_unlock(&previous_stage_sel->mutex);
1800 } else {
1801 ok = si_check_missing_main_part(sscreen, sel,
1802 compiler_state, key);
1803 }
1804 if (!ok) {
1805 FREE(shader);
1806 mtx_unlock(&sel->mutex);
1807 return -ENOMEM; /* skip the draw call */
1808 }
1809 }
1810
1811 /* Keep the reference to the 1st shader of merged shaders, so that
1812 * Gallium can't destroy it before we destroy the 2nd shader.
1813 *
1814 * Set sctx = NULL, because it's unused if we're not releasing
1815 * the shader, and we don't have any sctx here.
1816 */
1817 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
1818 previous_stage_sel);
1819
1820 /* Monolithic-only shaders don't make a distinction between optimized
1821 * and unoptimized. */
1822 shader->is_monolithic =
1823 is_pure_monolithic ||
1824 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1825
1826 shader->is_optimized =
1827 !is_pure_monolithic &&
1828 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1829
1830 /* If it's an optimized shader, compile it asynchronously. */
1831 if (shader->is_optimized &&
1832 !is_pure_monolithic &&
1833 thread_index < 0) {
1834 /* Compile it asynchronously. */
1835 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
1836 shader, &shader->ready,
1837 si_build_shader_variant_low_priority, NULL);
1838
1839 /* Add only after the ready fence was reset, to guard against a
1840 * race with si_bind_XX_shader. */
1841 if (!sel->last_variant) {
1842 sel->first_variant = shader;
1843 sel->last_variant = shader;
1844 } else {
1845 sel->last_variant->next_variant = shader;
1846 sel->last_variant = shader;
1847 }
1848
1849 /* Use the default (unoptimized) shader for now. */
1850 memset(&key->opt, 0, sizeof(key->opt));
1851 mtx_unlock(&sel->mutex);
1852 goto again;
1853 }
1854
1855 /* Reset the fence before adding to the variant list. */
1856 util_queue_fence_reset(&shader->ready);
1857
1858 if (!sel->last_variant) {
1859 sel->first_variant = shader;
1860 sel->last_variant = shader;
1861 } else {
1862 sel->last_variant->next_variant = shader;
1863 sel->last_variant = shader;
1864 }
1865
1866 mtx_unlock(&sel->mutex);
1867
1868 assert(!shader->is_optimized);
1869 si_build_shader_variant(shader, thread_index, false);
1870
1871 util_queue_fence_signal(&shader->ready);
1872
1873 if (!shader->compilation_failed)
1874 state->current = shader;
1875
1876 return shader->compilation_failed ? -1 : 0;
1877 }
1878
1879 static int si_shader_select(struct pipe_context *ctx,
1880 struct si_shader_ctx_state *state,
1881 struct si_compiler_ctx_state *compiler_state)
1882 {
1883 struct si_context *sctx = (struct si_context *)ctx;
1884 struct si_shader_key key;
1885
1886 si_shader_selector_key(ctx, state->cso, &key);
1887 return si_shader_select_with_key(sctx->screen, state, compiler_state,
1888 &key, -1);
1889 }
1890
1891 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1892 bool streamout,
1893 struct si_shader_key *key)
1894 {
1895 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1896
1897 switch (info->processor) {
1898 case PIPE_SHADER_VERTEX:
1899 switch (next_shader) {
1900 case PIPE_SHADER_GEOMETRY:
1901 key->as_es = 1;
1902 break;
1903 case PIPE_SHADER_TESS_CTRL:
1904 case PIPE_SHADER_TESS_EVAL:
1905 key->as_ls = 1;
1906 break;
1907 default:
1908 /* If POSITION isn't written, it can only be a HW VS
1909 * if streamout is used. If streamout isn't used,
1910 * assume that it's a HW LS. (the next shader is TCS)
1911 * This heuristic is needed for separate shader objects.
1912 */
1913 if (!info->writes_position && !streamout)
1914 key->as_ls = 1;
1915 }
1916 break;
1917
1918 case PIPE_SHADER_TESS_EVAL:
1919 if (next_shader == PIPE_SHADER_GEOMETRY ||
1920 !info->writes_position)
1921 key->as_es = 1;
1922 break;
1923 }
1924 }
1925
1926 /**
1927 * Compile the main shader part or the monolithic shader as part of
1928 * si_shader_selector initialization. Since it can be done asynchronously,
1929 * there is no way to report compile failures to applications.
1930 */
1931 static void si_init_shader_selector_async(void *job, int thread_index)
1932 {
1933 struct si_shader_selector *sel = (struct si_shader_selector *)job;
1934 struct si_screen *sscreen = sel->screen;
1935 struct ac_llvm_compiler *compiler;
1936 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
1937
1938 assert(!debug->debug_message || debug->async);
1939 assert(thread_index >= 0);
1940 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
1941 compiler = &sscreen->compiler[thread_index];
1942
1943 /* Compile the main shader part for use with a prolog and/or epilog.
1944 * If this fails, the driver will try to compile a monolithic shader
1945 * on demand.
1946 */
1947 if (!sscreen->use_monolithic_shaders) {
1948 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1949 void *ir_binary = NULL;
1950
1951 if (!shader) {
1952 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
1953 return;
1954 }
1955
1956 /* We can leave the fence signaled because use of the default
1957 * main part is guarded by the selector's ready fence. */
1958 util_queue_fence_init(&shader->ready);
1959
1960 shader->selector = sel;
1961 shader->is_monolithic = false;
1962 si_parse_next_shader_property(&sel->info,
1963 sel->so.num_outputs != 0,
1964 &shader->key);
1965
1966 if (sel->tokens || sel->nir)
1967 ir_binary = si_get_ir_binary(sel);
1968
1969 /* Try to load the shader from the shader cache. */
1970 mtx_lock(&sscreen->shader_cache_mutex);
1971
1972 if (ir_binary &&
1973 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
1974 mtx_unlock(&sscreen->shader_cache_mutex);
1975 si_shader_dump_stats_for_shader_db(shader, debug);
1976 } else {
1977 mtx_unlock(&sscreen->shader_cache_mutex);
1978
1979 /* Compile the shader if it hasn't been loaded from the cache. */
1980 if (si_compile_tgsi_shader(sscreen, compiler, shader,
1981 debug) != 0) {
1982 FREE(shader);
1983 FREE(ir_binary);
1984 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
1985 return;
1986 }
1987
1988 if (ir_binary) {
1989 mtx_lock(&sscreen->shader_cache_mutex);
1990 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
1991 FREE(ir_binary);
1992 mtx_unlock(&sscreen->shader_cache_mutex);
1993 }
1994 }
1995
1996 *si_get_main_shader_part(sel, &shader->key) = shader;
1997
1998 /* Unset "outputs_written" flags for outputs converted to
1999 * DEFAULT_VAL, so that later inter-shader optimizations don't
2000 * try to eliminate outputs that don't exist in the final
2001 * shader.
2002 *
2003 * This is only done if non-monolithic shaders are enabled.
2004 */
2005 if ((sel->type == PIPE_SHADER_VERTEX ||
2006 sel->type == PIPE_SHADER_TESS_EVAL) &&
2007 !shader->key.as_ls &&
2008 !shader->key.as_es) {
2009 unsigned i;
2010
2011 for (i = 0; i < sel->info.num_outputs; i++) {
2012 unsigned offset = shader->info.vs_output_param_offset[i];
2013
2014 if (offset <= AC_EXP_PARAM_OFFSET_31)
2015 continue;
2016
2017 unsigned name = sel->info.output_semantic_name[i];
2018 unsigned index = sel->info.output_semantic_index[i];
2019 unsigned id;
2020
2021 switch (name) {
2022 case TGSI_SEMANTIC_GENERIC:
2023 /* don't process indices the function can't handle */
2024 if (index >= SI_MAX_IO_GENERIC)
2025 break;
2026 /* fall through */
2027 default:
2028 id = si_shader_io_get_unique_index(name, index, true);
2029 sel->outputs_written_before_ps &= ~(1ull << id);
2030 break;
2031 case TGSI_SEMANTIC_POSITION: /* ignore these */
2032 case TGSI_SEMANTIC_PSIZE:
2033 case TGSI_SEMANTIC_CLIPVERTEX:
2034 case TGSI_SEMANTIC_EDGEFLAG:
2035 break;
2036 }
2037 }
2038 }
2039 }
2040
2041 /* The GS copy shader is always pre-compiled. */
2042 if (sel->type == PIPE_SHADER_GEOMETRY) {
2043 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2044 if (!sel->gs_copy_shader) {
2045 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2046 return;
2047 }
2048
2049 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2050 }
2051 }
2052
2053 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2054 struct util_queue_fence *ready_fence,
2055 struct si_compiler_ctx_state *compiler_ctx_state,
2056 void *job, util_queue_execute_func execute)
2057 {
2058 util_queue_fence_init(ready_fence);
2059
2060 struct util_async_debug_callback async_debug;
2061 bool wait =
2062 (sctx->debug.debug_message && !sctx->debug.async) ||
2063 sctx->is_debug ||
2064 si_can_dump_shader(sctx->screen, processor);
2065
2066 if (wait) {
2067 u_async_debug_init(&async_debug);
2068 compiler_ctx_state->debug = async_debug.base;
2069 }
2070
2071 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2072 ready_fence, execute, NULL);
2073
2074 if (wait) {
2075 util_queue_fence_wait(ready_fence);
2076 u_async_debug_drain(&async_debug, &sctx->debug);
2077 u_async_debug_cleanup(&async_debug);
2078 }
2079 }
2080
2081 /* Return descriptor slot usage masks from the given shader info. */
2082 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2083 uint32_t *const_and_shader_buffers,
2084 uint64_t *samplers_and_images)
2085 {
2086 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2087
2088 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2089 num_constbufs = util_last_bit(info->const_buffers_declared);
2090 /* two 8-byte images share one 16-byte slot */
2091 num_images = align(util_last_bit(info->images_declared), 2);
2092 num_samplers = util_last_bit(info->samplers_declared);
2093
2094 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2095 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2096 *const_and_shader_buffers =
2097 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2098
2099 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2100 start = si_get_image_slot(num_images - 1) / 2;
2101 *samplers_and_images =
2102 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2103 }
2104
2105 static void *si_create_shader_selector(struct pipe_context *ctx,
2106 const struct pipe_shader_state *state)
2107 {
2108 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2109 struct si_context *sctx = (struct si_context*)ctx;
2110 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2111 int i;
2112
2113 if (!sel)
2114 return NULL;
2115
2116 pipe_reference_init(&sel->reference, 1);
2117 sel->screen = sscreen;
2118 sel->compiler_ctx_state.debug = sctx->debug;
2119 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2120
2121 sel->so = state->stream_output;
2122
2123 if (state->type == PIPE_SHADER_IR_TGSI) {
2124 sel->tokens = tgsi_dup_tokens(state->tokens);
2125 if (!sel->tokens) {
2126 FREE(sel);
2127 return NULL;
2128 }
2129
2130 tgsi_scan_shader(state->tokens, &sel->info);
2131 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2132 } else {
2133 assert(state->type == PIPE_SHADER_IR_NIR);
2134
2135 sel->nir = state->ir.nir;
2136
2137 si_nir_scan_shader(sel->nir, &sel->info);
2138 si_nir_scan_tess_ctrl(sel->nir, &sel->info, &sel->tcs_info);
2139
2140 si_lower_nir(sel);
2141 }
2142
2143 sel->type = sel->info.processor;
2144 p_atomic_inc(&sscreen->num_shaders_created);
2145 si_get_active_slot_masks(&sel->info,
2146 &sel->active_const_and_shader_buffers,
2147 &sel->active_samplers_and_images);
2148
2149 /* Record which streamout buffers are enabled. */
2150 for (i = 0; i < sel->so.num_outputs; i++) {
2151 sel->enabled_streamout_buffer_mask |=
2152 (1 << sel->so.output[i].output_buffer) <<
2153 (sel->so.output[i].stream * 4);
2154 }
2155
2156 /* The prolog is a no-op if there are no inputs. */
2157 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2158 sel->info.num_inputs &&
2159 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2160
2161 sel->force_correct_derivs_after_kill =
2162 sel->type == PIPE_SHADER_FRAGMENT &&
2163 sel->info.uses_derivatives &&
2164 sel->info.uses_kill &&
2165 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2166
2167 /* Set which opcode uses which (i,j) pair. */
2168 if (sel->info.uses_persp_opcode_interp_centroid)
2169 sel->info.uses_persp_centroid = true;
2170
2171 if (sel->info.uses_linear_opcode_interp_centroid)
2172 sel->info.uses_linear_centroid = true;
2173
2174 if (sel->info.uses_persp_opcode_interp_offset ||
2175 sel->info.uses_persp_opcode_interp_sample)
2176 sel->info.uses_persp_center = true;
2177
2178 if (sel->info.uses_linear_opcode_interp_offset ||
2179 sel->info.uses_linear_opcode_interp_sample)
2180 sel->info.uses_linear_center = true;
2181
2182 switch (sel->type) {
2183 case PIPE_SHADER_GEOMETRY:
2184 sel->gs_output_prim =
2185 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2186 sel->gs_max_out_vertices =
2187 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2188 sel->gs_num_invocations =
2189 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2190 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2191 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2192 sel->gs_max_out_vertices;
2193
2194 sel->max_gs_stream = 0;
2195 for (i = 0; i < sel->so.num_outputs; i++)
2196 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2197 sel->so.output[i].stream);
2198
2199 sel->gs_input_verts_per_prim =
2200 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2201 break;
2202
2203 case PIPE_SHADER_TESS_CTRL:
2204 /* Always reserve space for these. */
2205 sel->patch_outputs_written |=
2206 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2207 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2208 /* fall through */
2209 case PIPE_SHADER_VERTEX:
2210 case PIPE_SHADER_TESS_EVAL:
2211 for (i = 0; i < sel->info.num_outputs; i++) {
2212 unsigned name = sel->info.output_semantic_name[i];
2213 unsigned index = sel->info.output_semantic_index[i];
2214
2215 switch (name) {
2216 case TGSI_SEMANTIC_TESSINNER:
2217 case TGSI_SEMANTIC_TESSOUTER:
2218 case TGSI_SEMANTIC_PATCH:
2219 sel->patch_outputs_written |=
2220 1ull << si_shader_io_get_unique_index_patch(name, index);
2221 break;
2222
2223 case TGSI_SEMANTIC_GENERIC:
2224 /* don't process indices the function can't handle */
2225 if (index >= SI_MAX_IO_GENERIC)
2226 break;
2227 /* fall through */
2228 default:
2229 sel->outputs_written |=
2230 1ull << si_shader_io_get_unique_index(name, index, false);
2231 sel->outputs_written_before_ps |=
2232 1ull << si_shader_io_get_unique_index(name, index, true);
2233 break;
2234 case TGSI_SEMANTIC_EDGEFLAG:
2235 break;
2236 }
2237 }
2238 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2239 sel->lshs_vertex_stride = sel->esgs_itemsize;
2240
2241 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2242 * will start on a different bank. (except for the maximum 32*16).
2243 */
2244 if (sel->lshs_vertex_stride < 32*16)
2245 sel->lshs_vertex_stride += 4;
2246
2247 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2248 * conflicts, i.e. each vertex will start at a different bank.
2249 */
2250 if (sctx->chip_class >= GFX9)
2251 sel->esgs_itemsize += 4;
2252
2253 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2254 break;
2255
2256 case PIPE_SHADER_FRAGMENT:
2257 for (i = 0; i < sel->info.num_inputs; i++) {
2258 unsigned name = sel->info.input_semantic_name[i];
2259 unsigned index = sel->info.input_semantic_index[i];
2260
2261 switch (name) {
2262 case TGSI_SEMANTIC_GENERIC:
2263 /* don't process indices the function can't handle */
2264 if (index >= SI_MAX_IO_GENERIC)
2265 break;
2266 /* fall through */
2267 default:
2268 sel->inputs_read |=
2269 1ull << si_shader_io_get_unique_index(name, index, true);
2270 break;
2271 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2272 break;
2273 }
2274 }
2275
2276 for (i = 0; i < 8; i++)
2277 if (sel->info.colors_written & (1 << i))
2278 sel->colors_written_4bit |= 0xf << (4 * i);
2279
2280 for (i = 0; i < sel->info.num_inputs; i++) {
2281 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2282 int index = sel->info.input_semantic_index[i];
2283 sel->color_attr_index[index] = i;
2284 }
2285 }
2286 break;
2287 }
2288
2289 /* PA_CL_VS_OUT_CNTL */
2290 bool misc_vec_ena =
2291 sel->info.writes_psize || sel->info.writes_edgeflag ||
2292 sel->info.writes_layer || sel->info.writes_viewport_index;
2293 sel->pa_cl_vs_out_cntl =
2294 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2295 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2296 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2297 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2298 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2299 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2300 sel->clipdist_mask = sel->info.writes_clipvertex ?
2301 SIX_BITS : sel->info.clipdist_writemask;
2302 sel->culldist_mask = sel->info.culldist_writemask <<
2303 sel->info.num_written_clipdistance;
2304
2305 /* DB_SHADER_CONTROL */
2306 sel->db_shader_control =
2307 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2308 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2309 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2310 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2311
2312 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2313 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2314 sel->db_shader_control |=
2315 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2316 break;
2317 case TGSI_FS_DEPTH_LAYOUT_LESS:
2318 sel->db_shader_control |=
2319 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2320 break;
2321 }
2322
2323 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2324 *
2325 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2326 * --|-----------|------------|------------|--------------------|-------------------|-------------
2327 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2328 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2329 * 2 | false | true | n/a | LateZ | 1 | 0
2330 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2331 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2332 *
2333 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2334 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2335 *
2336 * Don't use ReZ without profiling !!!
2337 *
2338 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2339 * shaders.
2340 */
2341 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2342 /* Cases 3, 4. */
2343 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2344 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2345 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2346 } else if (sel->info.writes_memory) {
2347 /* Case 2. */
2348 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2349 S_02880C_EXEC_ON_HIER_FAIL(1);
2350 } else {
2351 /* Case 1. */
2352 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2353 }
2354
2355 (void) mtx_init(&sel->mutex, mtx_plain);
2356
2357 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2358 &sel->compiler_ctx_state, sel,
2359 si_init_shader_selector_async);
2360 return sel;
2361 }
2362
2363 static void si_update_streamout_state(struct si_context *sctx)
2364 {
2365 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2366
2367 if (!shader_with_so)
2368 return;
2369
2370 sctx->streamout.enabled_stream_buffers_mask =
2371 shader_with_so->enabled_streamout_buffer_mask;
2372 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2373 }
2374
2375 static void si_update_clip_regs(struct si_context *sctx,
2376 struct si_shader_selector *old_hw_vs,
2377 struct si_shader *old_hw_vs_variant,
2378 struct si_shader_selector *next_hw_vs,
2379 struct si_shader *next_hw_vs_variant)
2380 {
2381 if (next_hw_vs &&
2382 (!old_hw_vs ||
2383 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2384 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2385 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2386 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2387 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2388 !old_hw_vs_variant ||
2389 !next_hw_vs_variant ||
2390 old_hw_vs_variant->key.opt.clip_disable !=
2391 next_hw_vs_variant->key.opt.clip_disable))
2392 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2393 }
2394
2395 static void si_update_common_shader_state(struct si_context *sctx)
2396 {
2397 sctx->uses_bindless_samplers =
2398 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2399 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2400 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2401 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2402 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2403 sctx->uses_bindless_images =
2404 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2405 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2406 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2407 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2408 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2409 sctx->do_update_shaders = true;
2410 }
2411
2412 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2413 {
2414 struct si_context *sctx = (struct si_context *)ctx;
2415 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2416 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2417 struct si_shader_selector *sel = state;
2418
2419 if (sctx->vs_shader.cso == sel)
2420 return;
2421
2422 sctx->vs_shader.cso = sel;
2423 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2424 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2425
2426 si_update_common_shader_state(sctx);
2427 si_update_vs_viewport_state(sctx);
2428 si_set_active_descriptors_for_shader(sctx, sel);
2429 si_update_streamout_state(sctx);
2430 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2431 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2432 }
2433
2434 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2435 {
2436 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2437 (sctx->tes_shader.cso &&
2438 sctx->tes_shader.cso->info.uses_primid) ||
2439 (sctx->tcs_shader.cso &&
2440 sctx->tcs_shader.cso->info.uses_primid) ||
2441 (sctx->gs_shader.cso &&
2442 sctx->gs_shader.cso->info.uses_primid) ||
2443 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2444 sctx->ps_shader.cso->info.uses_primid);
2445 }
2446
2447 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2448 {
2449 struct si_context *sctx = (struct si_context *)ctx;
2450 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2451 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2452 struct si_shader_selector *sel = state;
2453 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2454
2455 if (sctx->gs_shader.cso == sel)
2456 return;
2457
2458 sctx->gs_shader.cso = sel;
2459 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2460 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2461
2462 si_update_common_shader_state(sctx);
2463 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2464
2465 if (enable_changed) {
2466 si_shader_change_notify(sctx);
2467 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2468 si_update_tess_uses_prim_id(sctx);
2469 }
2470 si_update_vs_viewport_state(sctx);
2471 si_set_active_descriptors_for_shader(sctx, sel);
2472 si_update_streamout_state(sctx);
2473 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2474 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2475 }
2476
2477 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2478 {
2479 struct si_context *sctx = (struct si_context *)ctx;
2480 struct si_shader_selector *sel = state;
2481 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2482
2483 if (sctx->tcs_shader.cso == sel)
2484 return;
2485
2486 sctx->tcs_shader.cso = sel;
2487 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
2488 si_update_tess_uses_prim_id(sctx);
2489
2490 si_update_common_shader_state(sctx);
2491
2492 if (enable_changed)
2493 sctx->last_tcs = NULL; /* invalidate derived tess state */
2494
2495 si_set_active_descriptors_for_shader(sctx, sel);
2496 }
2497
2498 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
2499 {
2500 struct si_context *sctx = (struct si_context *)ctx;
2501 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2502 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2503 struct si_shader_selector *sel = state;
2504 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
2505
2506 if (sctx->tes_shader.cso == sel)
2507 return;
2508
2509 sctx->tes_shader.cso = sel;
2510 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
2511 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
2512 si_update_tess_uses_prim_id(sctx);
2513
2514 si_update_common_shader_state(sctx);
2515 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2516
2517 if (enable_changed) {
2518 si_shader_change_notify(sctx);
2519 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
2520 }
2521 si_update_vs_viewport_state(sctx);
2522 si_set_active_descriptors_for_shader(sctx, sel);
2523 si_update_streamout_state(sctx);
2524 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2525 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2526 }
2527
2528 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2529 {
2530 struct si_context *sctx = (struct si_context *)ctx;
2531 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
2532 struct si_shader_selector *sel = state;
2533
2534 /* skip if supplied shader is one already in use */
2535 if (old_sel == sel)
2536 return;
2537
2538 sctx->ps_shader.cso = sel;
2539 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
2540
2541 si_update_common_shader_state(sctx);
2542 if (sel) {
2543 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2544 si_update_tess_uses_prim_id(sctx);
2545
2546 if (!old_sel ||
2547 old_sel->info.colors_written != sel->info.colors_written)
2548 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2549
2550 if (sctx->screen->has_out_of_order_rast &&
2551 (!old_sel ||
2552 old_sel->info.writes_memory != sel->info.writes_memory ||
2553 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
2554 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
2555 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2556 }
2557 si_set_active_descriptors_for_shader(sctx, sel);
2558 si_update_ps_colorbuf0_slot(sctx);
2559 }
2560
2561 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
2562 {
2563 if (shader->is_optimized) {
2564 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
2565 &shader->ready);
2566 }
2567
2568 util_queue_fence_destroy(&shader->ready);
2569
2570 if (shader->pm4) {
2571 switch (shader->selector->type) {
2572 case PIPE_SHADER_VERTEX:
2573 if (shader->key.as_ls) {
2574 assert(sctx->chip_class <= VI);
2575 si_pm4_delete_state(sctx, ls, shader->pm4);
2576 } else if (shader->key.as_es) {
2577 assert(sctx->chip_class <= VI);
2578 si_pm4_delete_state(sctx, es, shader->pm4);
2579 } else {
2580 si_pm4_delete_state(sctx, vs, shader->pm4);
2581 }
2582 break;
2583 case PIPE_SHADER_TESS_CTRL:
2584 si_pm4_delete_state(sctx, hs, shader->pm4);
2585 break;
2586 case PIPE_SHADER_TESS_EVAL:
2587 if (shader->key.as_es) {
2588 assert(sctx->chip_class <= VI);
2589 si_pm4_delete_state(sctx, es, shader->pm4);
2590 } else {
2591 si_pm4_delete_state(sctx, vs, shader->pm4);
2592 }
2593 break;
2594 case PIPE_SHADER_GEOMETRY:
2595 if (shader->is_gs_copy_shader)
2596 si_pm4_delete_state(sctx, vs, shader->pm4);
2597 else
2598 si_pm4_delete_state(sctx, gs, shader->pm4);
2599 break;
2600 case PIPE_SHADER_FRAGMENT:
2601 si_pm4_delete_state(sctx, ps, shader->pm4);
2602 break;
2603 }
2604 }
2605
2606 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
2607 si_shader_destroy(shader);
2608 free(shader);
2609 }
2610
2611 void si_destroy_shader_selector(struct si_context *sctx,
2612 struct si_shader_selector *sel)
2613 {
2614 struct si_shader *p = sel->first_variant, *c;
2615 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
2616 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
2617 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
2618 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
2619 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
2620 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
2621 };
2622
2623 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
2624
2625 if (current_shader[sel->type]->cso == sel) {
2626 current_shader[sel->type]->cso = NULL;
2627 current_shader[sel->type]->current = NULL;
2628 }
2629
2630 while (p) {
2631 c = p->next_variant;
2632 si_delete_shader(sctx, p);
2633 p = c;
2634 }
2635
2636 if (sel->main_shader_part)
2637 si_delete_shader(sctx, sel->main_shader_part);
2638 if (sel->main_shader_part_ls)
2639 si_delete_shader(sctx, sel->main_shader_part_ls);
2640 if (sel->main_shader_part_es)
2641 si_delete_shader(sctx, sel->main_shader_part_es);
2642 if (sel->gs_copy_shader)
2643 si_delete_shader(sctx, sel->gs_copy_shader);
2644
2645 util_queue_fence_destroy(&sel->ready);
2646 mtx_destroy(&sel->mutex);
2647 free(sel->tokens);
2648 ralloc_free(sel->nir);
2649 free(sel);
2650 }
2651
2652 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
2653 {
2654 struct si_context *sctx = (struct si_context *)ctx;
2655 struct si_shader_selector *sel = (struct si_shader_selector *)state;
2656
2657 si_shader_selector_reference(sctx, &sel, NULL);
2658 }
2659
2660 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
2661 struct si_shader *vs, unsigned name,
2662 unsigned index, unsigned interpolate)
2663 {
2664 struct tgsi_shader_info *vsinfo = &vs->selector->info;
2665 unsigned j, offset, ps_input_cntl = 0;
2666
2667 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
2668 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
2669 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2670
2671 if (name == TGSI_SEMANTIC_PCOORD ||
2672 (name == TGSI_SEMANTIC_TEXCOORD &&
2673 sctx->sprite_coord_enable & (1 << index))) {
2674 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
2675 }
2676
2677 for (j = 0; j < vsinfo->num_outputs; j++) {
2678 if (name == vsinfo->output_semantic_name[j] &&
2679 index == vsinfo->output_semantic_index[j]) {
2680 offset = vs->info.vs_output_param_offset[j];
2681
2682 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2683 /* The input is loaded from parameter memory. */
2684 ps_input_cntl |= S_028644_OFFSET(offset);
2685 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2686 if (offset == AC_EXP_PARAM_UNDEFINED) {
2687 /* This can happen with depth-only rendering. */
2688 offset = 0;
2689 } else {
2690 /* The input is a DEFAULT_VAL constant. */
2691 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2692 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2693 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2694 }
2695
2696 ps_input_cntl = S_028644_OFFSET(0x20) |
2697 S_028644_DEFAULT_VAL(offset);
2698 }
2699 break;
2700 }
2701 }
2702
2703 if (name == TGSI_SEMANTIC_PRIMID)
2704 /* PrimID is written after the last output. */
2705 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
2706 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2707 /* No corresponding output found, load defaults into input.
2708 * Don't set any other bits.
2709 * (FLAT_SHADE=1 completely changes behavior) */
2710 ps_input_cntl = S_028644_OFFSET(0x20);
2711 /* D3D 9 behaviour. GL is undefined */
2712 if (name == TGSI_SEMANTIC_COLOR && index == 0)
2713 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
2714 }
2715 return ps_input_cntl;
2716 }
2717
2718 static void si_emit_spi_map(struct si_context *sctx)
2719 {
2720 struct si_shader *ps = sctx->ps_shader.current;
2721 struct si_shader *vs = si_get_vs_state(sctx);
2722 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
2723 unsigned i, num_interp, num_written = 0, bcol_interp[2];
2724 unsigned spi_ps_input_cntl[32];
2725
2726 if (!ps || !ps->selector->info.num_inputs)
2727 return;
2728
2729 num_interp = si_get_ps_num_interp(ps);
2730 assert(num_interp > 0);
2731
2732 for (i = 0; i < psinfo->num_inputs; i++) {
2733 unsigned name = psinfo->input_semantic_name[i];
2734 unsigned index = psinfo->input_semantic_index[i];
2735 unsigned interpolate = psinfo->input_interpolate[i];
2736
2737 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
2738 index, interpolate);
2739
2740 if (name == TGSI_SEMANTIC_COLOR) {
2741 assert(index < ARRAY_SIZE(bcol_interp));
2742 bcol_interp[index] = interpolate;
2743 }
2744 }
2745
2746 if (ps->key.part.ps.prolog.color_two_side) {
2747 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
2748
2749 for (i = 0; i < 2; i++) {
2750 if (!(psinfo->colors_read & (0xf << (i * 4))))
2751 continue;
2752
2753 spi_ps_input_cntl[num_written++] =
2754 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
2755
2756 }
2757 }
2758 assert(num_interp == num_written);
2759
2760 /* R_028644_SPI_PS_INPUT_CNTL_0 */
2761 /* Dota 2: Only ~16% of SPI map updates set different values. */
2762 /* Talos: Only ~9% of SPI map updates set different values. */
2763 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
2764 spi_ps_input_cntl,
2765 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
2766 }
2767
2768 /**
2769 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2770 */
2771 static void si_init_config_add_vgt_flush(struct si_context *sctx)
2772 {
2773 if (sctx->init_config_has_vgt_flush)
2774 return;
2775
2776 /* Done by Vulkan before VGT_FLUSH. */
2777 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2778 si_pm4_cmd_add(sctx->init_config,
2779 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2780 si_pm4_cmd_end(sctx->init_config, false);
2781
2782 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2783 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2784 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2785 si_pm4_cmd_end(sctx->init_config, false);
2786 sctx->init_config_has_vgt_flush = true;
2787 }
2788
2789 /* Initialize state related to ESGS / GSVS ring buffers */
2790 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2791 {
2792 struct si_shader_selector *es =
2793 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2794 struct si_shader_selector *gs = sctx->gs_shader.cso;
2795 struct si_pm4_state *pm4;
2796
2797 /* Chip constants. */
2798 unsigned num_se = sctx->screen->info.max_se;
2799 unsigned wave_size = 64;
2800 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2801 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2802 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2803 */
2804 unsigned gs_vertex_reuse = (sctx->chip_class >= VI ? 32 : 16) * num_se;
2805 unsigned alignment = 256 * num_se;
2806 /* The maximum size is 63.999 MB per SE. */
2807 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2808
2809 /* Calculate the minimum size. */
2810 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
2811 wave_size, alignment);
2812
2813 /* These are recommended sizes, not minimum sizes. */
2814 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2815 es->esgs_itemsize * gs->gs_input_verts_per_prim;
2816 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2817 gs->max_gsvs_emit_size;
2818
2819 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2820 esgs_ring_size = align(esgs_ring_size, alignment);
2821 gsvs_ring_size = align(gsvs_ring_size, alignment);
2822
2823 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2824 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2825
2826 /* Some rings don't have to be allocated if shaders don't use them.
2827 * (e.g. no varyings between ES and GS or GS and VS)
2828 *
2829 * GFX9 doesn't have the ESGS ring.
2830 */
2831 bool update_esgs = sctx->chip_class <= VI &&
2832 esgs_ring_size &&
2833 (!sctx->esgs_ring ||
2834 sctx->esgs_ring->width0 < esgs_ring_size);
2835 bool update_gsvs = gsvs_ring_size &&
2836 (!sctx->gsvs_ring ||
2837 sctx->gsvs_ring->width0 < gsvs_ring_size);
2838
2839 if (!update_esgs && !update_gsvs)
2840 return true;
2841
2842 if (update_esgs) {
2843 pipe_resource_reference(&sctx->esgs_ring, NULL);
2844 sctx->esgs_ring =
2845 pipe_aligned_buffer_create(sctx->b.screen,
2846 SI_RESOURCE_FLAG_UNMAPPABLE,
2847 PIPE_USAGE_DEFAULT,
2848 esgs_ring_size, alignment);
2849 if (!sctx->esgs_ring)
2850 return false;
2851 }
2852
2853 if (update_gsvs) {
2854 pipe_resource_reference(&sctx->gsvs_ring, NULL);
2855 sctx->gsvs_ring =
2856 pipe_aligned_buffer_create(sctx->b.screen,
2857 SI_RESOURCE_FLAG_UNMAPPABLE,
2858 PIPE_USAGE_DEFAULT,
2859 gsvs_ring_size, alignment);
2860 if (!sctx->gsvs_ring)
2861 return false;
2862 }
2863
2864 /* Create the "init_config_gs_rings" state. */
2865 pm4 = CALLOC_STRUCT(si_pm4_state);
2866 if (!pm4)
2867 return false;
2868
2869 if (sctx->chip_class >= CIK) {
2870 if (sctx->esgs_ring) {
2871 assert(sctx->chip_class <= VI);
2872 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2873 sctx->esgs_ring->width0 / 256);
2874 }
2875 if (sctx->gsvs_ring)
2876 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2877 sctx->gsvs_ring->width0 / 256);
2878 } else {
2879 if (sctx->esgs_ring)
2880 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2881 sctx->esgs_ring->width0 / 256);
2882 if (sctx->gsvs_ring)
2883 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2884 sctx->gsvs_ring->width0 / 256);
2885 }
2886
2887 /* Set the state. */
2888 if (sctx->init_config_gs_rings)
2889 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
2890 sctx->init_config_gs_rings = pm4;
2891
2892 if (!sctx->init_config_has_vgt_flush) {
2893 si_init_config_add_vgt_flush(sctx);
2894 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2895 }
2896
2897 /* Flush the context to re-emit both init_config states. */
2898 sctx->initial_gfx_cs_size = 0; /* force flush */
2899 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
2900
2901 /* Set ring bindings. */
2902 if (sctx->esgs_ring) {
2903 assert(sctx->chip_class <= VI);
2904 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
2905 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2906 true, true, 4, 64, 0);
2907 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
2908 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2909 false, false, 0, 0, 0);
2910 }
2911 if (sctx->gsvs_ring) {
2912 si_set_ring_buffer(sctx, SI_RING_GSVS,
2913 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
2914 false, false, 0, 0, 0);
2915 }
2916
2917 return true;
2918 }
2919
2920 static void si_shader_lock(struct si_shader *shader)
2921 {
2922 mtx_lock(&shader->selector->mutex);
2923 if (shader->previous_stage_sel) {
2924 assert(shader->previous_stage_sel != shader->selector);
2925 mtx_lock(&shader->previous_stage_sel->mutex);
2926 }
2927 }
2928
2929 static void si_shader_unlock(struct si_shader *shader)
2930 {
2931 if (shader->previous_stage_sel)
2932 mtx_unlock(&shader->previous_stage_sel->mutex);
2933 mtx_unlock(&shader->selector->mutex);
2934 }
2935
2936 /**
2937 * @returns 1 if \p sel has been updated to use a new scratch buffer
2938 * 0 if not
2939 * < 0 if there was a failure
2940 */
2941 static int si_update_scratch_buffer(struct si_context *sctx,
2942 struct si_shader *shader)
2943 {
2944 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
2945 int r;
2946
2947 if (!shader)
2948 return 0;
2949
2950 /* This shader doesn't need a scratch buffer */
2951 if (shader->config.scratch_bytes_per_wave == 0)
2952 return 0;
2953
2954 /* Prevent race conditions when updating:
2955 * - si_shader::scratch_bo
2956 * - si_shader::binary::code
2957 * - si_shader::previous_stage::binary::code.
2958 */
2959 si_shader_lock(shader);
2960
2961 /* This shader is already configured to use the current
2962 * scratch buffer. */
2963 if (shader->scratch_bo == sctx->scratch_buffer) {
2964 si_shader_unlock(shader);
2965 return 0;
2966 }
2967
2968 assert(sctx->scratch_buffer);
2969
2970 if (shader->previous_stage)
2971 si_shader_apply_scratch_relocs(shader->previous_stage, scratch_va);
2972
2973 si_shader_apply_scratch_relocs(shader, scratch_va);
2974
2975 /* Replace the shader bo with a new bo that has the relocs applied. */
2976 r = si_shader_binary_upload(sctx->screen, shader);
2977 if (r) {
2978 si_shader_unlock(shader);
2979 return r;
2980 }
2981
2982 /* Update the shader state to use the new shader bo. */
2983 si_shader_init_pm4_state(sctx->screen, shader);
2984
2985 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
2986
2987 si_shader_unlock(shader);
2988 return 1;
2989 }
2990
2991 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
2992 {
2993 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
2994 }
2995
2996 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
2997 {
2998 return shader ? shader->config.scratch_bytes_per_wave : 0;
2999 }
3000
3001 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3002 {
3003 if (!sctx->tes_shader.cso)
3004 return NULL; /* tessellation disabled */
3005
3006 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3007 sctx->fixed_func_tcs_shader.current;
3008 }
3009
3010 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
3011 {
3012 unsigned bytes = 0;
3013
3014 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3015 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3016 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3017 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3018
3019 if (sctx->tes_shader.cso) {
3020 struct si_shader *tcs = si_get_tcs_current(sctx);
3021
3022 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
3023 }
3024 return bytes;
3025 }
3026
3027 static bool si_update_scratch_relocs(struct si_context *sctx)
3028 {
3029 struct si_shader *tcs = si_get_tcs_current(sctx);
3030 int r;
3031
3032 /* Update the shaders, so that they are using the latest scratch.
3033 * The scratch buffer may have been changed since these shaders were
3034 * last used, so we still need to try to update them, even if they
3035 * require scratch buffers smaller than the current size.
3036 */
3037 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3038 if (r < 0)
3039 return false;
3040 if (r == 1)
3041 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3042
3043 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3044 if (r < 0)
3045 return false;
3046 if (r == 1)
3047 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3048
3049 r = si_update_scratch_buffer(sctx, tcs);
3050 if (r < 0)
3051 return false;
3052 if (r == 1)
3053 si_pm4_bind_state(sctx, hs, tcs->pm4);
3054
3055 /* VS can be bound as LS, ES, or VS. */
3056 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3057 if (r < 0)
3058 return false;
3059 if (r == 1) {
3060 if (sctx->tes_shader.current)
3061 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3062 else if (sctx->gs_shader.current)
3063 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3064 else
3065 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3066 }
3067
3068 /* TES can be bound as ES or VS. */
3069 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3070 if (r < 0)
3071 return false;
3072 if (r == 1) {
3073 if (sctx->gs_shader.current)
3074 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3075 else
3076 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3077 }
3078
3079 return true;
3080 }
3081
3082 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3083 {
3084 unsigned current_scratch_buffer_size =
3085 si_get_current_scratch_buffer_size(sctx);
3086 unsigned scratch_bytes_per_wave =
3087 si_get_max_scratch_bytes_per_wave(sctx);
3088 unsigned scratch_needed_size = scratch_bytes_per_wave *
3089 sctx->scratch_waves;
3090 unsigned spi_tmpring_size;
3091
3092 if (scratch_needed_size > 0) {
3093 if (scratch_needed_size > current_scratch_buffer_size) {
3094 /* Create a bigger scratch buffer */
3095 r600_resource_reference(&sctx->scratch_buffer, NULL);
3096
3097 sctx->scratch_buffer =
3098 si_aligned_buffer_create(&sctx->screen->b,
3099 SI_RESOURCE_FLAG_UNMAPPABLE,
3100 PIPE_USAGE_DEFAULT,
3101 scratch_needed_size, 256);
3102 if (!sctx->scratch_buffer)
3103 return false;
3104
3105 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3106 si_context_add_resource_size(sctx,
3107 &sctx->scratch_buffer->b.b);
3108 }
3109
3110 if (!si_update_scratch_relocs(sctx))
3111 return false;
3112 }
3113
3114 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3115 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3116 "scratch size should already be aligned correctly.");
3117
3118 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3119 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3120 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3121 sctx->spi_tmpring_size = spi_tmpring_size;
3122 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3123 }
3124 return true;
3125 }
3126
3127 static void si_init_tess_factor_ring(struct si_context *sctx)
3128 {
3129 assert(!sctx->tess_rings);
3130
3131 /* The address must be aligned to 2^19, because the shader only
3132 * receives the high 13 bits.
3133 */
3134 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3135 SI_RESOURCE_FLAG_32BIT,
3136 PIPE_USAGE_DEFAULT,
3137 sctx->screen->tess_offchip_ring_size +
3138 sctx->screen->tess_factor_ring_size,
3139 1 << 19);
3140 if (!sctx->tess_rings)
3141 return;
3142
3143 si_init_config_add_vgt_flush(sctx);
3144
3145 si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_rings),
3146 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3147
3148 uint64_t factor_va = r600_resource(sctx->tess_rings)->gpu_address +
3149 sctx->screen->tess_offchip_ring_size;
3150
3151 /* Append these registers to the init config state. */
3152 if (sctx->chip_class >= CIK) {
3153 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3154 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3155 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3156 factor_va >> 8);
3157 if (sctx->chip_class >= GFX9)
3158 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3159 S_030944_BASE_HI(factor_va >> 40));
3160 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3161 sctx->screen->vgt_hs_offchip_param);
3162 } else {
3163 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3164 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3165 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3166 factor_va >> 8);
3167 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3168 sctx->screen->vgt_hs_offchip_param);
3169 }
3170
3171 /* Flush the context to re-emit the init_config state.
3172 * This is done only once in a lifetime of a context.
3173 */
3174 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3175 sctx->initial_gfx_cs_size = 0; /* force flush */
3176 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3177 }
3178
3179 static void si_update_vgt_shader_config(struct si_context *sctx)
3180 {
3181 /* Calculate the index of the config.
3182 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3183 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
3184 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
3185
3186 if (!*pm4) {
3187 uint32_t stages = 0;
3188
3189 *pm4 = CALLOC_STRUCT(si_pm4_state);
3190
3191 if (sctx->tes_shader.cso) {
3192 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3193 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3194
3195 if (sctx->gs_shader.cso)
3196 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3197 S_028B54_GS_EN(1) |
3198 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3199 else
3200 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3201 } else if (sctx->gs_shader.cso) {
3202 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3203 S_028B54_GS_EN(1) |
3204 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3205 }
3206
3207 if (sctx->chip_class >= GFX9)
3208 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3209
3210 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3211 }
3212 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3213 }
3214
3215 bool si_update_shaders(struct si_context *sctx)
3216 {
3217 struct pipe_context *ctx = (struct pipe_context*)sctx;
3218 struct si_compiler_ctx_state compiler_state;
3219 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3220 struct si_shader *old_vs = si_get_vs_state(sctx);
3221 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3222 struct si_shader *old_ps = sctx->ps_shader.current;
3223 unsigned old_spi_shader_col_format =
3224 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3225 int r;
3226
3227 compiler_state.compiler = &sctx->compiler;
3228 compiler_state.debug = sctx->debug;
3229 compiler_state.is_debug_context = sctx->is_debug;
3230
3231 /* Update stages before GS. */
3232 if (sctx->tes_shader.cso) {
3233 if (!sctx->tess_rings) {
3234 si_init_tess_factor_ring(sctx);
3235 if (!sctx->tess_rings)
3236 return false;
3237 }
3238
3239 /* VS as LS */
3240 if (sctx->chip_class <= VI) {
3241 r = si_shader_select(ctx, &sctx->vs_shader,
3242 &compiler_state);
3243 if (r)
3244 return false;
3245 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3246 }
3247
3248 if (sctx->tcs_shader.cso) {
3249 r = si_shader_select(ctx, &sctx->tcs_shader,
3250 &compiler_state);
3251 if (r)
3252 return false;
3253 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3254 } else {
3255 if (!sctx->fixed_func_tcs_shader.cso) {
3256 sctx->fixed_func_tcs_shader.cso =
3257 si_create_fixed_func_tcs(sctx);
3258 if (!sctx->fixed_func_tcs_shader.cso)
3259 return false;
3260 }
3261
3262 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3263 &compiler_state);
3264 if (r)
3265 return false;
3266 si_pm4_bind_state(sctx, hs,
3267 sctx->fixed_func_tcs_shader.current->pm4);
3268 }
3269
3270 if (sctx->gs_shader.cso) {
3271 /* TES as ES */
3272 if (sctx->chip_class <= VI) {
3273 r = si_shader_select(ctx, &sctx->tes_shader,
3274 &compiler_state);
3275 if (r)
3276 return false;
3277 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3278 }
3279 } else {
3280 /* TES as VS */
3281 r = si_shader_select(ctx, &sctx->tes_shader,
3282 &compiler_state);
3283 if (r)
3284 return false;
3285 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3286 }
3287 } else if (sctx->gs_shader.cso) {
3288 if (sctx->chip_class <= VI) {
3289 /* VS as ES */
3290 r = si_shader_select(ctx, &sctx->vs_shader,
3291 &compiler_state);
3292 if (r)
3293 return false;
3294 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3295
3296 si_pm4_bind_state(sctx, ls, NULL);
3297 si_pm4_bind_state(sctx, hs, NULL);
3298 }
3299 } else {
3300 /* VS as VS */
3301 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
3302 if (r)
3303 return false;
3304 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3305 si_pm4_bind_state(sctx, ls, NULL);
3306 si_pm4_bind_state(sctx, hs, NULL);
3307 }
3308
3309 /* Update GS. */
3310 if (sctx->gs_shader.cso) {
3311 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
3312 if (r)
3313 return false;
3314 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3315 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3316
3317 if (!si_update_gs_ring_buffers(sctx))
3318 return false;
3319 } else {
3320 si_pm4_bind_state(sctx, gs, NULL);
3321 if (sctx->chip_class <= VI)
3322 si_pm4_bind_state(sctx, es, NULL);
3323 }
3324
3325 si_update_vgt_shader_config(sctx);
3326
3327 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3328 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3329
3330 if (sctx->ps_shader.cso) {
3331 unsigned db_shader_control;
3332
3333 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
3334 if (r)
3335 return false;
3336 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3337
3338 db_shader_control =
3339 sctx->ps_shader.cso->db_shader_control |
3340 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3341
3342 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3343 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3344 sctx->flatshade != rs->flatshade) {
3345 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3346 sctx->flatshade = rs->flatshade;
3347 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3348 }
3349
3350 if (sctx->screen->rbplus_allowed &&
3351 si_pm4_state_changed(sctx, ps) &&
3352 (!old_ps ||
3353 old_spi_shader_col_format !=
3354 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3355 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3356
3357 if (sctx->ps_db_shader_control != db_shader_control) {
3358 sctx->ps_db_shader_control = db_shader_control;
3359 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3360 if (sctx->screen->dpbb_allowed)
3361 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3362 }
3363
3364 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3365 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3366 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3367
3368 if (sctx->chip_class == SI)
3369 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3370
3371 if (sctx->framebuffer.nr_samples <= 1)
3372 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3373 }
3374 }
3375
3376 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3377 si_pm4_state_enabled_and_changed(sctx, hs) ||
3378 si_pm4_state_enabled_and_changed(sctx, es) ||
3379 si_pm4_state_enabled_and_changed(sctx, gs) ||
3380 si_pm4_state_enabled_and_changed(sctx, vs) ||
3381 si_pm4_state_enabled_and_changed(sctx, ps)) {
3382 if (!si_update_spi_tmpring_size(sctx))
3383 return false;
3384 }
3385
3386 if (sctx->chip_class >= CIK) {
3387 if (si_pm4_state_enabled_and_changed(sctx, ls))
3388 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3389 else if (!sctx->queued.named.ls)
3390 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3391
3392 if (si_pm4_state_enabled_and_changed(sctx, hs))
3393 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3394 else if (!sctx->queued.named.hs)
3395 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3396
3397 if (si_pm4_state_enabled_and_changed(sctx, es))
3398 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
3399 else if (!sctx->queued.named.es)
3400 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
3401
3402 if (si_pm4_state_enabled_and_changed(sctx, gs))
3403 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
3404 else if (!sctx->queued.named.gs)
3405 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
3406
3407 if (si_pm4_state_enabled_and_changed(sctx, vs))
3408 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
3409 else if (!sctx->queued.named.vs)
3410 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
3411
3412 if (si_pm4_state_enabled_and_changed(sctx, ps))
3413 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
3414 else if (!sctx->queued.named.ps)
3415 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
3416 }
3417
3418 sctx->do_update_shaders = false;
3419 return true;
3420 }
3421
3422 static void si_emit_scratch_state(struct si_context *sctx)
3423 {
3424 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3425
3426 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3427 sctx->spi_tmpring_size);
3428
3429 if (sctx->scratch_buffer) {
3430 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3431 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3432 RADEON_PRIO_SCRATCH_BUFFER);
3433 }
3434 }
3435
3436 void si_init_shader_functions(struct si_context *sctx)
3437 {
3438 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
3439 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
3440
3441 sctx->b.create_vs_state = si_create_shader_selector;
3442 sctx->b.create_tcs_state = si_create_shader_selector;
3443 sctx->b.create_tes_state = si_create_shader_selector;
3444 sctx->b.create_gs_state = si_create_shader_selector;
3445 sctx->b.create_fs_state = si_create_shader_selector;
3446
3447 sctx->b.bind_vs_state = si_bind_vs_shader;
3448 sctx->b.bind_tcs_state = si_bind_tcs_shader;
3449 sctx->b.bind_tes_state = si_bind_tes_shader;
3450 sctx->b.bind_gs_state = si_bind_gs_shader;
3451 sctx->b.bind_fs_state = si_bind_ps_shader;
3452
3453 sctx->b.delete_vs_state = si_delete_shader_selector;
3454 sctx->b.delete_tcs_state = si_delete_shader_selector;
3455 sctx->b.delete_tes_state = si_delete_shader_selector;
3456 sctx->b.delete_gs_state = si_delete_shader_selector;
3457 sctx->b.delete_fs_state = si_delete_shader_selector;
3458 }