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radeonsi: convert CB_TARGET_MASK setup to an atom
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "si_shader.h"
30 #include "sid.h"
31
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_ureg.h"
34 #include "util/u_memory.h"
35 #include "util/u_simple_shaders.h"
36
37 static void si_set_tesseval_regs(struct si_shader *shader,
38 struct si_pm4_state *pm4)
39 {
40 struct tgsi_shader_info *info = &shader->selector->info;
41 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
42 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
43 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
44 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
45 unsigned type, partitioning, topology;
46
47 switch (tes_prim_mode) {
48 case PIPE_PRIM_LINES:
49 type = V_028B6C_TESS_ISOLINE;
50 break;
51 case PIPE_PRIM_TRIANGLES:
52 type = V_028B6C_TESS_TRIANGLE;
53 break;
54 case PIPE_PRIM_QUADS:
55 type = V_028B6C_TESS_QUAD;
56 break;
57 default:
58 assert(0);
59 return;
60 }
61
62 switch (tes_spacing) {
63 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
64 partitioning = V_028B6C_PART_FRAC_ODD;
65 break;
66 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
67 partitioning = V_028B6C_PART_FRAC_EVEN;
68 break;
69 case PIPE_TESS_SPACING_EQUAL:
70 partitioning = V_028B6C_PART_INTEGER;
71 break;
72 default:
73 assert(0);
74 return;
75 }
76
77 if (tes_point_mode)
78 topology = V_028B6C_OUTPUT_POINT;
79 else if (tes_prim_mode == PIPE_PRIM_LINES)
80 topology = V_028B6C_OUTPUT_LINE;
81 else if (tes_vertex_order_cw)
82 /* for some reason, this must be the other way around */
83 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
84 else
85 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
86
87 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
88 S_028B6C_TYPE(type) |
89 S_028B6C_PARTITIONING(partitioning) |
90 S_028B6C_TOPOLOGY(topology));
91 }
92
93 static void si_shader_ls(struct si_shader *shader)
94 {
95 struct si_pm4_state *pm4;
96 unsigned num_sgprs, num_user_sgprs;
97 unsigned vgpr_comp_cnt;
98 uint64_t va;
99
100 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
101 if (pm4 == NULL)
102 return;
103
104 va = shader->bo->gpu_address;
105 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
106
107 /* We need at least 2 components for LS.
108 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
109 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 1;
110
111 num_user_sgprs = SI_LS_NUM_USER_SGPR;
112 num_sgprs = shader->num_sgprs;
113 if (num_user_sgprs > num_sgprs) {
114 /* Last 2 reserved SGPRs are used for VCC */
115 num_sgprs = num_user_sgprs + 2;
116 }
117 assert(num_sgprs <= 104);
118
119 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
120 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
121
122 shader->ls_rsrc1 = S_00B528_VGPRS((shader->num_vgprs - 1) / 4) |
123 S_00B528_SGPRS((num_sgprs - 1) / 8) |
124 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt);
125 shader->ls_rsrc2 = S_00B52C_USER_SGPR(num_user_sgprs) |
126 S_00B52C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0);
127 }
128
129 static void si_shader_hs(struct si_shader *shader)
130 {
131 struct si_pm4_state *pm4;
132 unsigned num_sgprs, num_user_sgprs;
133 uint64_t va;
134
135 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
136 if (pm4 == NULL)
137 return;
138
139 va = shader->bo->gpu_address;
140 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
141
142 num_user_sgprs = SI_TCS_NUM_USER_SGPR;
143 num_sgprs = shader->num_sgprs;
144 /* One SGPR after user SGPRs is pre-loaded with tessellation factor
145 * buffer offset. */
146 if ((num_user_sgprs + 1) > num_sgprs) {
147 /* Last 2 reserved SGPRs are used for VCC */
148 num_sgprs = num_user_sgprs + 1 + 2;
149 }
150 assert(num_sgprs <= 104);
151
152 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
153 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
154 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
155 S_00B428_VGPRS((shader->num_vgprs - 1) / 4) |
156 S_00B428_SGPRS((num_sgprs - 1) / 8));
157 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
158 S_00B42C_USER_SGPR(num_user_sgprs) |
159 S_00B42C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
160 }
161
162 static void si_shader_es(struct si_shader *shader)
163 {
164 struct si_pm4_state *pm4;
165 unsigned num_sgprs, num_user_sgprs;
166 unsigned vgpr_comp_cnt;
167 uint64_t va;
168
169 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
170
171 if (pm4 == NULL)
172 return;
173
174 va = shader->bo->gpu_address;
175 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
176
177 if (shader->selector->type == PIPE_SHADER_VERTEX) {
178 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
179 num_user_sgprs = SI_VS_NUM_USER_SGPR;
180 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
181 vgpr_comp_cnt = 3; /* all components are needed for TES */
182 num_user_sgprs = SI_TES_NUM_USER_SGPR;
183 } else
184 unreachable("invalid shader selector type");
185
186 num_sgprs = shader->num_sgprs;
187 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
188 if ((num_user_sgprs + 1) > num_sgprs) {
189 /* Last 2 reserved SGPRs are used for VCC */
190 num_sgprs = num_user_sgprs + 1 + 2;
191 }
192 assert(num_sgprs <= 104);
193
194 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
195 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
196 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
197 S_00B328_VGPRS((shader->num_vgprs - 1) / 4) |
198 S_00B328_SGPRS((num_sgprs - 1) / 8) |
199 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
200 S_00B328_DX10_CLAMP(shader->dx10_clamp_mode));
201 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
202 S_00B32C_USER_SGPR(num_user_sgprs) |
203 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
204
205 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
206 si_set_tesseval_regs(shader, pm4);
207 }
208
209 static unsigned si_gs_get_max_stream(struct si_shader *shader)
210 {
211 struct pipe_stream_output_info *so = &shader->selector->so;
212 unsigned max_stream = 0, i;
213
214 if (so->num_outputs == 0)
215 return 0;
216
217 for (i = 0; i < so->num_outputs; i++) {
218 if (so->output[i].stream > max_stream)
219 max_stream = so->output[i].stream;
220 }
221 return max_stream;
222 }
223
224 static void si_shader_gs(struct si_shader *shader)
225 {
226 unsigned gs_vert_itemsize = shader->selector->info.num_outputs * 16;
227 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
228 unsigned gsvs_itemsize = (gs_vert_itemsize * gs_max_vert_out) >> 2;
229 unsigned gs_num_invocations = shader->selector->gs_num_invocations;
230 unsigned cut_mode;
231 struct si_pm4_state *pm4;
232 unsigned num_sgprs, num_user_sgprs;
233 uint64_t va;
234 unsigned max_stream = si_gs_get_max_stream(shader);
235
236 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
237 assert(gsvs_itemsize < (1 << 15));
238
239 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
240
241 if (pm4 == NULL)
242 return;
243
244 if (gs_max_vert_out <= 128) {
245 cut_mode = V_028A40_GS_CUT_128;
246 } else if (gs_max_vert_out <= 256) {
247 cut_mode = V_028A40_GS_CUT_256;
248 } else if (gs_max_vert_out <= 512) {
249 cut_mode = V_028A40_GS_CUT_512;
250 } else {
251 assert(gs_max_vert_out <= 1024);
252 cut_mode = V_028A40_GS_CUT_1024;
253 }
254
255 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
256 S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
257 S_028A40_CUT_MODE(cut_mode)|
258 S_028A40_ES_WRITE_OPTIMIZE(1) |
259 S_028A40_GS_WRITE_OPTIMIZE(1));
260
261 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
262 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize * ((max_stream >= 2) ? 2 : 1));
263 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize * ((max_stream >= 3) ? 3 : 1));
264
265 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
266 util_bitcount64(shader->selector->inputs_read) * (16 >> 2));
267 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize * (max_stream + 1));
268
269 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, gs_max_vert_out);
270
271 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize >> 2);
272 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? gs_vert_itemsize >> 2 : 0);
273 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? gs_vert_itemsize >> 2 : 0);
274 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? gs_vert_itemsize >> 2 : 0);
275
276 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
277 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
278 S_028B90_ENABLE(gs_num_invocations > 0));
279
280 va = shader->bo->gpu_address;
281 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
282 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
283 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
284
285 num_user_sgprs = SI_GS_NUM_USER_SGPR;
286 num_sgprs = shader->num_sgprs;
287 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
288 if ((num_user_sgprs + 2) > num_sgprs) {
289 /* Last 2 reserved SGPRs are used for VCC */
290 num_sgprs = num_user_sgprs + 2 + 2;
291 }
292 assert(num_sgprs <= 104);
293
294 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
295 S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
296 S_00B228_SGPRS((num_sgprs - 1) / 8) |
297 S_00B228_DX10_CLAMP(shader->dx10_clamp_mode));
298 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
299 S_00B22C_USER_SGPR(num_user_sgprs) |
300 S_00B22C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
301 }
302
303 static void si_shader_vs(struct si_shader *shader)
304 {
305 struct si_pm4_state *pm4;
306 unsigned num_sgprs, num_user_sgprs;
307 unsigned nparams, vgpr_comp_cnt;
308 uint64_t va;
309 unsigned window_space =
310 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
311 bool enable_prim_id = si_vs_exports_prim_id(shader);
312
313 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
314
315 if (pm4 == NULL)
316 return;
317
318 /* If this is the GS copy shader, the GS state writes this register.
319 * Otherwise, the VS state writes it.
320 */
321 if (!shader->is_gs_copy_shader) {
322 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
323 S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
324 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
325 } else
326 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
327
328 va = shader->bo->gpu_address;
329 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
330
331 if (shader->is_gs_copy_shader) {
332 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
333 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
334 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
335 vgpr_comp_cnt = shader->uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
336 num_user_sgprs = SI_VS_NUM_USER_SGPR;
337 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
338 vgpr_comp_cnt = 3; /* all components are needed for TES */
339 num_user_sgprs = SI_TES_NUM_USER_SGPR;
340 } else
341 unreachable("invalid shader selector type");
342
343 num_sgprs = shader->num_sgprs;
344 if (num_user_sgprs > num_sgprs) {
345 /* Last 2 reserved SGPRs are used for VCC */
346 num_sgprs = num_user_sgprs + 2;
347 }
348 assert(num_sgprs <= 104);
349
350 /* VS is required to export at least one param. */
351 nparams = MAX2(shader->nr_param_exports, 1);
352 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
353 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
354
355 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
356 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
357 S_02870C_POS1_EXPORT_FORMAT(shader->nr_pos_exports > 1 ?
358 V_02870C_SPI_SHADER_4COMP :
359 V_02870C_SPI_SHADER_NONE) |
360 S_02870C_POS2_EXPORT_FORMAT(shader->nr_pos_exports > 2 ?
361 V_02870C_SPI_SHADER_4COMP :
362 V_02870C_SPI_SHADER_NONE) |
363 S_02870C_POS3_EXPORT_FORMAT(shader->nr_pos_exports > 3 ?
364 V_02870C_SPI_SHADER_4COMP :
365 V_02870C_SPI_SHADER_NONE));
366
367 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
368 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
369 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
370 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
371 S_00B128_SGPRS((num_sgprs - 1) / 8) |
372 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
373 S_00B128_DX10_CLAMP(shader->dx10_clamp_mode));
374 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
375 S_00B12C_USER_SGPR(num_user_sgprs) |
376 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
377 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
378 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
379 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
380 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
381 S_00B12C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
382 if (window_space)
383 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
384 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
385 else
386 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
387 S_028818_VTX_W0_FMT(1) |
388 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
389 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
390 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
391
392 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
393 si_set_tesseval_regs(shader, pm4);
394 }
395
396 static void si_shader_ps(struct si_shader *shader)
397 {
398 struct tgsi_shader_info *info = &shader->selector->info;
399 struct si_pm4_state *pm4;
400 unsigned i, spi_ps_in_control;
401 unsigned num_sgprs, num_user_sgprs;
402 unsigned spi_baryc_cntl = 0, spi_ps_input_ena;
403 uint64_t va;
404
405 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
406
407 if (pm4 == NULL)
408 return;
409
410 for (i = 0; i < info->num_inputs; i++) {
411 switch (info->input_semantic_name[i]) {
412 case TGSI_SEMANTIC_POSITION:
413 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
414 * Possible vaules:
415 * 0 -> Position = pixel center (default)
416 * 1 -> Position = pixel centroid
417 * 2 -> Position = at sample position
418 */
419 switch (info->input_interpolate_loc[i]) {
420 case TGSI_INTERPOLATE_LOC_CENTROID:
421 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
422 break;
423 case TGSI_INTERPOLATE_LOC_SAMPLE:
424 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
425 break;
426 }
427
428 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
429 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
430 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
431 break;
432 }
433 }
434
435 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->nparam) |
436 S_0286D8_BC_OPTIMIZE_DISABLE(1);
437
438 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
439 spi_ps_input_ena = shader->spi_ps_input_ena;
440 /* we need to enable at least one of them, otherwise we hang the GPU */
441 assert(G_0286CC_PERSP_SAMPLE_ENA(spi_ps_input_ena) ||
442 G_0286CC_PERSP_CENTER_ENA(spi_ps_input_ena) ||
443 G_0286CC_PERSP_CENTROID_ENA(spi_ps_input_ena) ||
444 G_0286CC_PERSP_PULL_MODEL_ENA(spi_ps_input_ena) ||
445 G_0286CC_LINEAR_SAMPLE_ENA(spi_ps_input_ena) ||
446 G_0286CC_LINEAR_CENTER_ENA(spi_ps_input_ena) ||
447 G_0286CC_LINEAR_CENTROID_ENA(spi_ps_input_ena) ||
448 G_0286CC_LINE_STIPPLE_TEX_ENA(spi_ps_input_ena));
449
450 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, spi_ps_input_ena);
451 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR, spi_ps_input_ena);
452 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
453
454 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
455 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
456 shader->spi_shader_col_format);
457 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
458
459 va = shader->bo->gpu_address;
460 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_DATA);
461 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
462 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
463
464 num_user_sgprs = SI_PS_NUM_USER_SGPR;
465 num_sgprs = shader->num_sgprs;
466 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
467 if ((num_user_sgprs + 1) > num_sgprs) {
468 /* Last 2 reserved SGPRs are used for VCC */
469 num_sgprs = num_user_sgprs + 1 + 2;
470 }
471 assert(num_sgprs <= 104);
472
473 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
474 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
475 S_00B028_SGPRS((num_sgprs - 1) / 8) |
476 S_00B028_DX10_CLAMP(shader->dx10_clamp_mode));
477 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
478 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
479 S_00B02C_USER_SGPR(num_user_sgprs) |
480 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
481 }
482
483 static void si_shader_init_pm4_state(struct si_shader *shader)
484 {
485
486 if (shader->pm4)
487 si_pm4_free_state_simple(shader->pm4);
488
489 switch (shader->selector->type) {
490 case PIPE_SHADER_VERTEX:
491 if (shader->key.vs.as_ls)
492 si_shader_ls(shader);
493 else if (shader->key.vs.as_es)
494 si_shader_es(shader);
495 else
496 si_shader_vs(shader);
497 break;
498 case PIPE_SHADER_TESS_CTRL:
499 si_shader_hs(shader);
500 break;
501 case PIPE_SHADER_TESS_EVAL:
502 if (shader->key.tes.as_es)
503 si_shader_es(shader);
504 else
505 si_shader_vs(shader);
506 break;
507 case PIPE_SHADER_GEOMETRY:
508 si_shader_gs(shader);
509 si_shader_vs(shader->gs_copy_shader);
510 break;
511 case PIPE_SHADER_FRAGMENT:
512 si_shader_ps(shader);
513 break;
514 default:
515 assert(0);
516 }
517 }
518
519 /* Compute the key for the hw shader variant */
520 static inline void si_shader_selector_key(struct pipe_context *ctx,
521 struct si_shader_selector *sel,
522 union si_shader_key *key)
523 {
524 struct si_context *sctx = (struct si_context *)ctx;
525 unsigned i;
526
527 memset(key, 0, sizeof(*key));
528
529 switch (sel->type) {
530 case PIPE_SHADER_VERTEX:
531 if (sctx->vertex_elements)
532 for (i = 0; i < sctx->vertex_elements->count; ++i)
533 key->vs.instance_divisors[i] =
534 sctx->vertex_elements->elements[i].instance_divisor;
535
536 if (sctx->tes_shader)
537 key->vs.as_ls = 1;
538 else if (sctx->gs_shader) {
539 key->vs.as_es = 1;
540 key->vs.es_enabled_outputs = sctx->gs_shader->inputs_read;
541 }
542
543 if (!sctx->gs_shader && sctx->ps_shader &&
544 sctx->ps_shader->info.uses_primid)
545 key->vs.export_prim_id = 1;
546 break;
547 case PIPE_SHADER_TESS_CTRL:
548 key->tcs.prim_mode =
549 sctx->tes_shader->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
550 break;
551 case PIPE_SHADER_TESS_EVAL:
552 if (sctx->gs_shader) {
553 key->tes.as_es = 1;
554 key->tes.es_enabled_outputs = sctx->gs_shader->inputs_read;
555 } else if (sctx->ps_shader && sctx->ps_shader->info.uses_primid)
556 key->tes.export_prim_id = 1;
557 break;
558 case PIPE_SHADER_GEOMETRY:
559 break;
560 case PIPE_SHADER_FRAGMENT: {
561 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
562
563 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
564 key->ps.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
565 key->ps.export_16bpc = sctx->framebuffer.export_16bpc;
566
567 if (rs) {
568 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
569 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
570 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
571 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
572
573 key->ps.color_two_side = rs->two_side;
574
575 if (sctx->queued.named.blend) {
576 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
577 rs->multisample_enable &&
578 !sctx->framebuffer.cb0_is_integer;
579 }
580
581 key->ps.poly_stipple = rs->poly_stipple_enable && is_poly;
582 key->ps.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
583 (is_line && rs->line_smooth)) &&
584 sctx->framebuffer.nr_samples <= 1;
585 }
586
587 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
588 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
589 if (sctx->queued.named.dsa &&
590 !sctx->framebuffer.cb0_is_integer)
591 key->ps.alpha_func = sctx->queued.named.dsa->alpha_func;
592 break;
593 }
594 default:
595 assert(0);
596 }
597 }
598
599 /* Select the hw shader variant depending on the current state. */
600 static int si_shader_select(struct pipe_context *ctx,
601 struct si_shader_selector *sel)
602 {
603 struct si_context *sctx = (struct si_context *)ctx;
604 union si_shader_key key;
605 struct si_shader * shader = NULL;
606 int r;
607
608 si_shader_selector_key(ctx, sel, &key);
609
610 /* Check if we don't need to change anything.
611 * This path is also used for most shaders that don't need multiple
612 * variants, it will cost just a computation of the key and this
613 * test. */
614 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
615 return 0;
616 }
617
618 /* lookup if we have other variants in the list */
619 if (sel->num_shaders > 1) {
620 struct si_shader *p = sel->current, *c = p->next_variant;
621
622 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
623 p = c;
624 c = c->next_variant;
625 }
626
627 if (c) {
628 p->next_variant = c->next_variant;
629 shader = c;
630 }
631 }
632
633 if (shader) {
634 shader->next_variant = sel->current;
635 sel->current = shader;
636 } else {
637 shader = CALLOC(1, sizeof(struct si_shader));
638 shader->selector = sel;
639 shader->key = key;
640
641 shader->next_variant = sel->current;
642 sel->current = shader;
643 r = si_shader_create((struct si_screen*)ctx->screen, sctx->tm,
644 shader);
645 if (unlikely(r)) {
646 R600_ERR("Failed to build shader variant (type=%u) %d\n",
647 sel->type, r);
648 sel->current = NULL;
649 FREE(shader);
650 return r;
651 }
652 si_shader_init_pm4_state(shader);
653 sel->num_shaders++;
654 p_atomic_inc(&sctx->screen->b.num_compilations);
655 }
656
657 return 0;
658 }
659
660 static void *si_create_shader_state(struct pipe_context *ctx,
661 const struct pipe_shader_state *state,
662 unsigned pipe_shader_type)
663 {
664 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
665 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
666 int i;
667
668 sel->type = pipe_shader_type;
669 sel->tokens = tgsi_dup_tokens(state->tokens);
670 sel->so = state->stream_output;
671 tgsi_scan_shader(state->tokens, &sel->info);
672 p_atomic_inc(&sscreen->b.num_shaders_created);
673
674 switch (pipe_shader_type) {
675 case PIPE_SHADER_GEOMETRY:
676 sel->gs_output_prim =
677 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
678 sel->gs_max_out_vertices =
679 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
680 sel->gs_num_invocations =
681 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
682 sel->gsvs_itemsize = sel->info.num_outputs * 16 *
683 sel->gs_max_out_vertices;
684
685 for (i = 0; i < sel->info.num_inputs; i++) {
686 unsigned name = sel->info.input_semantic_name[i];
687 unsigned index = sel->info.input_semantic_index[i];
688
689 switch (name) {
690 case TGSI_SEMANTIC_PRIMID:
691 break;
692 default:
693 sel->inputs_read |=
694 1llu << si_shader_io_get_unique_index(name, index);
695 }
696 }
697 break;
698
699 case PIPE_SHADER_VERTEX:
700 case PIPE_SHADER_TESS_CTRL:
701 for (i = 0; i < sel->info.num_outputs; i++) {
702 unsigned name = sel->info.output_semantic_name[i];
703 unsigned index = sel->info.output_semantic_index[i];
704
705 switch (name) {
706 case TGSI_SEMANTIC_TESSINNER:
707 case TGSI_SEMANTIC_TESSOUTER:
708 case TGSI_SEMANTIC_PATCH:
709 sel->patch_outputs_written |=
710 1llu << si_shader_io_get_unique_index(name, index);
711 break;
712 default:
713 sel->outputs_written |=
714 1llu << si_shader_io_get_unique_index(name, index);
715 }
716 }
717 break;
718 case PIPE_SHADER_FRAGMENT:
719 for (i = 0; i < sel->info.num_outputs; i++) {
720 unsigned name = sel->info.output_semantic_name[i];
721 unsigned index = sel->info.output_semantic_index[i];
722
723 if (name == TGSI_SEMANTIC_COLOR)
724 sel->ps_colors_written |= 1 << index;
725 }
726 break;
727 }
728
729 if (sscreen->b.debug_flags & DBG_PRECOMPILE)
730 si_shader_select(ctx, sel);
731
732 return sel;
733 }
734
735 static void *si_create_fs_state(struct pipe_context *ctx,
736 const struct pipe_shader_state *state)
737 {
738 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
739 }
740
741 static void *si_create_gs_state(struct pipe_context *ctx,
742 const struct pipe_shader_state *state)
743 {
744 return si_create_shader_state(ctx, state, PIPE_SHADER_GEOMETRY);
745 }
746
747 static void *si_create_vs_state(struct pipe_context *ctx,
748 const struct pipe_shader_state *state)
749 {
750 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
751 }
752
753 static void *si_create_tcs_state(struct pipe_context *ctx,
754 const struct pipe_shader_state *state)
755 {
756 return si_create_shader_state(ctx, state, PIPE_SHADER_TESS_CTRL);
757 }
758
759 static void *si_create_tes_state(struct pipe_context *ctx,
760 const struct pipe_shader_state *state)
761 {
762 return si_create_shader_state(ctx, state, PIPE_SHADER_TESS_EVAL);
763 }
764
765 /**
766 * Normally, we only emit 1 viewport and 1 scissor if no shader is using
767 * the VIEWPORT_INDEX output, and emitting the other viewports and scissors
768 * is delayed. When a shader with VIEWPORT_INDEX appears, this should be
769 * called to emit the rest.
770 */
771 static void si_update_viewports_and_scissors(struct si_context *sctx)
772 {
773 struct tgsi_shader_info *info = si_get_vs_info(sctx);
774
775 if (!info || !info->writes_viewport_index)
776 return;
777
778 if (sctx->scissors.dirty_mask)
779 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
780 if (sctx->viewports.dirty_mask)
781 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
782 }
783
784 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
785 {
786 struct si_context *sctx = (struct si_context *)ctx;
787 struct si_shader_selector *sel = state;
788
789 if (sctx->vs_shader == sel || !sel)
790 return;
791
792 sctx->vs_shader = sel;
793 si_mark_atom_dirty(sctx, &sctx->clip_regs);
794 si_update_viewports_and_scissors(sctx);
795 }
796
797 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
798 {
799 struct si_context *sctx = (struct si_context *)ctx;
800 struct si_shader_selector *sel = state;
801 bool enable_changed = !!sctx->gs_shader != !!sel;
802
803 if (sctx->gs_shader == sel)
804 return;
805
806 sctx->gs_shader = sel;
807 si_mark_atom_dirty(sctx, &sctx->clip_regs);
808 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
809
810 if (enable_changed)
811 si_shader_change_notify(sctx);
812 si_update_viewports_and_scissors(sctx);
813 }
814
815 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
816 {
817 struct si_context *sctx = (struct si_context *)ctx;
818 struct si_shader_selector *sel = state;
819 bool enable_changed = !!sctx->tcs_shader != !!sel;
820
821 if (sctx->tcs_shader == sel)
822 return;
823
824 sctx->tcs_shader = sel;
825
826 if (enable_changed)
827 sctx->last_tcs = NULL; /* invalidate derived tess state */
828 }
829
830 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
831 {
832 struct si_context *sctx = (struct si_context *)ctx;
833 struct si_shader_selector *sel = state;
834 bool enable_changed = !!sctx->tes_shader != !!sel;
835
836 if (sctx->tes_shader == sel)
837 return;
838
839 sctx->tes_shader = sel;
840 si_mark_atom_dirty(sctx, &sctx->clip_regs);
841 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
842
843 if (enable_changed) {
844 si_shader_change_notify(sctx);
845 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
846 }
847 si_update_viewports_and_scissors(sctx);
848 }
849
850 static void si_make_dummy_ps(struct si_context *sctx)
851 {
852 if (!sctx->dummy_pixel_shader) {
853 sctx->dummy_pixel_shader =
854 util_make_fragment_cloneinput_shader(&sctx->b.b, 0,
855 TGSI_SEMANTIC_GENERIC,
856 TGSI_INTERPOLATE_CONSTANT);
857 }
858 }
859
860 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
861 {
862 struct si_context *sctx = (struct si_context *)ctx;
863 struct si_shader_selector *sel = state;
864
865 /* skip if supplied shader is one already in use */
866 if (sctx->ps_shader == sel)
867 return;
868
869 /* use a dummy shader if binding a NULL shader */
870 if (!sel) {
871 si_make_dummy_ps(sctx);
872 sel = sctx->dummy_pixel_shader;
873 }
874
875 sctx->ps_shader = sel;
876 si_mark_atom_dirty(sctx, &sctx->cb_target_mask);
877 }
878
879 static void si_delete_shader_selector(struct pipe_context *ctx,
880 struct si_shader_selector *sel)
881 {
882 struct si_context *sctx = (struct si_context *)ctx;
883 struct si_shader *p = sel->current, *c;
884
885 while (p) {
886 c = p->next_variant;
887 switch (sel->type) {
888 case PIPE_SHADER_VERTEX:
889 if (p->key.vs.as_ls)
890 si_pm4_delete_state(sctx, ls, p->pm4);
891 else if (p->key.vs.as_es)
892 si_pm4_delete_state(sctx, es, p->pm4);
893 else
894 si_pm4_delete_state(sctx, vs, p->pm4);
895 break;
896 case PIPE_SHADER_TESS_CTRL:
897 si_pm4_delete_state(sctx, hs, p->pm4);
898 break;
899 case PIPE_SHADER_TESS_EVAL:
900 if (p->key.tes.as_es)
901 si_pm4_delete_state(sctx, es, p->pm4);
902 else
903 si_pm4_delete_state(sctx, vs, p->pm4);
904 break;
905 case PIPE_SHADER_GEOMETRY:
906 si_pm4_delete_state(sctx, gs, p->pm4);
907 si_pm4_delete_state(sctx, vs, p->gs_copy_shader->pm4);
908 break;
909 case PIPE_SHADER_FRAGMENT:
910 si_pm4_delete_state(sctx, ps, p->pm4);
911 break;
912 }
913
914 si_shader_destroy(ctx, p);
915 free(p);
916 p = c;
917 }
918
919 free(sel->tokens);
920 free(sel);
921 }
922
923 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
924 {
925 struct si_context *sctx = (struct si_context *)ctx;
926 struct si_shader_selector *sel = (struct si_shader_selector *)state;
927
928 if (sctx->vs_shader == sel) {
929 sctx->vs_shader = NULL;
930 }
931
932 si_delete_shader_selector(ctx, sel);
933 }
934
935 static void si_delete_gs_shader(struct pipe_context *ctx, void *state)
936 {
937 struct si_context *sctx = (struct si_context *)ctx;
938 struct si_shader_selector *sel = (struct si_shader_selector *)state;
939
940 if (sctx->gs_shader == sel) {
941 sctx->gs_shader = NULL;
942 }
943
944 si_delete_shader_selector(ctx, sel);
945 }
946
947 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
948 {
949 struct si_context *sctx = (struct si_context *)ctx;
950 struct si_shader_selector *sel = (struct si_shader_selector *)state;
951
952 if (sctx->ps_shader == sel) {
953 sctx->ps_shader = NULL;
954 }
955
956 si_delete_shader_selector(ctx, sel);
957 }
958
959 static void si_delete_tcs_shader(struct pipe_context *ctx, void *state)
960 {
961 struct si_context *sctx = (struct si_context *)ctx;
962 struct si_shader_selector *sel = (struct si_shader_selector *)state;
963
964 if (sctx->tcs_shader == sel) {
965 sctx->tcs_shader = NULL;
966 }
967
968 si_delete_shader_selector(ctx, sel);
969 }
970
971 static void si_delete_tes_shader(struct pipe_context *ctx, void *state)
972 {
973 struct si_context *sctx = (struct si_context *)ctx;
974 struct si_shader_selector *sel = (struct si_shader_selector *)state;
975
976 if (sctx->tes_shader == sel) {
977 sctx->tes_shader = NULL;
978 }
979
980 si_delete_shader_selector(ctx, sel);
981 }
982
983 static void si_update_spi_map(struct si_context *sctx)
984 {
985 struct si_shader *ps = sctx->ps_shader->current;
986 struct si_shader *vs = si_get_vs_state(sctx);
987 struct tgsi_shader_info *psinfo = &ps->selector->info;
988 struct tgsi_shader_info *vsinfo = &vs->selector->info;
989 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
990 unsigned i, j, tmp;
991
992 for (i = 0; i < psinfo->num_inputs; i++) {
993 unsigned name = psinfo->input_semantic_name[i];
994 unsigned index = psinfo->input_semantic_index[i];
995 unsigned interpolate = psinfo->input_interpolate[i];
996 unsigned param_offset = ps->ps_input_param_offset[i];
997
998 if (name == TGSI_SEMANTIC_POSITION ||
999 name == TGSI_SEMANTIC_FACE)
1000 /* Read from preloaded VGPRs, not parameters */
1001 continue;
1002
1003 bcolor:
1004 tmp = 0;
1005
1006 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
1007 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
1008 tmp |= S_028644_FLAT_SHADE(1);
1009
1010 if (name == TGSI_SEMANTIC_PCOORD ||
1011 (name == TGSI_SEMANTIC_TEXCOORD &&
1012 sctx->sprite_coord_enable & (1 << index))) {
1013 tmp |= S_028644_PT_SPRITE_TEX(1);
1014 }
1015
1016 for (j = 0; j < vsinfo->num_outputs; j++) {
1017 if (name == vsinfo->output_semantic_name[j] &&
1018 index == vsinfo->output_semantic_index[j]) {
1019 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[j]);
1020 break;
1021 }
1022 }
1023
1024 if (name == TGSI_SEMANTIC_PRIMID)
1025 /* PrimID is written after the last output. */
1026 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[vsinfo->num_outputs]);
1027 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(tmp)) {
1028 /* No corresponding output found, load defaults into input.
1029 * Don't set any other bits.
1030 * (FLAT_SHADE=1 completely changes behavior) */
1031 tmp = S_028644_OFFSET(0x20);
1032 }
1033
1034 si_pm4_set_reg(pm4,
1035 R_028644_SPI_PS_INPUT_CNTL_0 + param_offset * 4,
1036 tmp);
1037
1038 if (name == TGSI_SEMANTIC_COLOR &&
1039 ps->key.ps.color_two_side) {
1040 name = TGSI_SEMANTIC_BCOLOR;
1041 param_offset++;
1042 goto bcolor;
1043 }
1044 }
1045
1046 si_pm4_set_state(sctx, spi, pm4);
1047 }
1048
1049 /* Initialize state related to ESGS / GSVS ring buffers */
1050 static void si_init_gs_rings(struct si_context *sctx)
1051 {
1052 unsigned esgs_ring_size = 128 * 1024;
1053 unsigned gsvs_ring_size = 60 * 1024 * 1024;
1054
1055 assert(!sctx->esgs_ring && !sctx->gsvs_ring);
1056
1057 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1058 PIPE_USAGE_DEFAULT, esgs_ring_size);
1059
1060 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1061 PIPE_USAGE_DEFAULT, gsvs_ring_size);
1062
1063 /* Append these registers to the init config state. */
1064 if (sctx->b.chip_class >= CIK) {
1065 if (sctx->b.chip_class >= VI) {
1066 /* The maximum sizes are 63.999 MB on VI, because
1067 * the register fields only have 18 bits. */
1068 assert(esgs_ring_size / 256 < (1 << 18));
1069 assert(gsvs_ring_size / 256 < (1 << 18));
1070 }
1071 si_pm4_set_reg(sctx->init_config, R_030900_VGT_ESGS_RING_SIZE,
1072 esgs_ring_size / 256);
1073 si_pm4_set_reg(sctx->init_config, R_030904_VGT_GSVS_RING_SIZE,
1074 gsvs_ring_size / 256);
1075 } else {
1076 si_pm4_set_reg(sctx->init_config, R_0088C8_VGT_ESGS_RING_SIZE,
1077 esgs_ring_size / 256);
1078 si_pm4_set_reg(sctx->init_config, R_0088CC_VGT_GSVS_RING_SIZE,
1079 gsvs_ring_size / 256);
1080 }
1081
1082 /* Flush the context to re-emit the init_config state.
1083 * This is done only once in a lifetime of a context.
1084 */
1085 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1086 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1087
1088 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
1089 sctx->esgs_ring, 0, esgs_ring_size,
1090 true, true, 4, 64, 0);
1091 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
1092 sctx->esgs_ring, 0, esgs_ring_size,
1093 false, false, 0, 0, 0);
1094 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
1095 sctx->gsvs_ring, 0, gsvs_ring_size,
1096 false, false, 0, 0, 0);
1097 }
1098
1099 static void si_update_gs_rings(struct si_context *sctx)
1100 {
1101 unsigned gsvs_itemsize = sctx->gs_shader->gsvs_itemsize;
1102 uint64_t offset;
1103
1104 if (gsvs_itemsize == sctx->last_gsvs_itemsize)
1105 return;
1106
1107 sctx->last_gsvs_itemsize = gsvs_itemsize;
1108
1109 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
1110 sctx->gsvs_ring, gsvs_itemsize,
1111 64, true, true, 4, 16, 0);
1112
1113 offset = gsvs_itemsize * 64;
1114 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_1,
1115 sctx->gsvs_ring, gsvs_itemsize,
1116 64, true, true, 4, 16, offset);
1117
1118 offset = (gsvs_itemsize * 2) * 64;
1119 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_2,
1120 sctx->gsvs_ring, gsvs_itemsize,
1121 64, true, true, 4, 16, offset);
1122
1123 offset = (gsvs_itemsize * 3) * 64;
1124 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_3,
1125 sctx->gsvs_ring, gsvs_itemsize,
1126 64, true, true, 4, 16, offset);
1127 }
1128
1129 /**
1130 * @returns 1 if \p sel has been updated to use a new scratch buffer and 0
1131 * otherwise.
1132 */
1133 static unsigned si_update_scratch_buffer(struct si_context *sctx,
1134 struct si_shader_selector *sel)
1135 {
1136 struct si_shader *shader;
1137 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
1138
1139 if (!sel)
1140 return 0;
1141
1142 shader = sel->current;
1143
1144 /* This shader doesn't need a scratch buffer */
1145 if (shader->scratch_bytes_per_wave == 0)
1146 return 0;
1147
1148 /* This shader is already configured to use the current
1149 * scratch buffer. */
1150 if (shader->scratch_bo == sctx->scratch_buffer)
1151 return 0;
1152
1153 assert(sctx->scratch_buffer);
1154
1155 si_shader_apply_scratch_relocs(sctx, shader, scratch_va);
1156
1157 /* Replace the shader bo with a new bo that has the relocs applied. */
1158 si_shader_binary_upload(sctx->screen, shader);
1159
1160 /* Update the shader state to use the new shader bo. */
1161 si_shader_init_pm4_state(shader);
1162
1163 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
1164
1165 return 1;
1166 }
1167
1168 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
1169 {
1170 if (!sctx->scratch_buffer)
1171 return 0;
1172
1173 return sctx->scratch_buffer->b.b.width0;
1174 }
1175
1176 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_context *sctx,
1177 struct si_shader_selector *sel)
1178 {
1179 if (!sel)
1180 return 0;
1181
1182 return sel->current->scratch_bytes_per_wave;
1183 }
1184
1185 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
1186 {
1187 unsigned bytes = 0;
1188
1189 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx, sctx->ps_shader));
1190 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx, sctx->gs_shader));
1191 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx, sctx->vs_shader));
1192 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx, sctx->tcs_shader));
1193 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx, sctx->tes_shader));
1194 return bytes;
1195 }
1196
1197 static void si_update_spi_tmpring_size(struct si_context *sctx)
1198 {
1199 unsigned current_scratch_buffer_size =
1200 si_get_current_scratch_buffer_size(sctx);
1201 unsigned scratch_bytes_per_wave =
1202 si_get_max_scratch_bytes_per_wave(sctx);
1203 unsigned scratch_needed_size = scratch_bytes_per_wave *
1204 sctx->scratch_waves;
1205
1206 if (scratch_needed_size > 0) {
1207
1208 if (scratch_needed_size > current_scratch_buffer_size) {
1209 /* Create a bigger scratch buffer */
1210 pipe_resource_reference(
1211 (struct pipe_resource**)&sctx->scratch_buffer,
1212 NULL);
1213
1214 sctx->scratch_buffer =
1215 si_resource_create_custom(&sctx->screen->b.b,
1216 PIPE_USAGE_DEFAULT, scratch_needed_size);
1217 }
1218
1219 /* Update the shaders, so they are using the latest scratch. The
1220 * scratch buffer may have been changed since these shaders were
1221 * last used, so we still need to try to update them, even if
1222 * they require scratch buffers smaller than the current size.
1223 */
1224 if (si_update_scratch_buffer(sctx, sctx->ps_shader))
1225 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
1226 if (si_update_scratch_buffer(sctx, sctx->gs_shader))
1227 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
1228 if (si_update_scratch_buffer(sctx, sctx->tcs_shader))
1229 si_pm4_bind_state(sctx, hs, sctx->tcs_shader->current->pm4);
1230
1231 /* VS can be bound as LS, ES, or VS. */
1232 if (sctx->tes_shader) {
1233 if (si_update_scratch_buffer(sctx, sctx->vs_shader))
1234 si_pm4_bind_state(sctx, ls, sctx->vs_shader->current->pm4);
1235 } else if (sctx->gs_shader) {
1236 if (si_update_scratch_buffer(sctx, sctx->vs_shader))
1237 si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
1238 } else {
1239 if (si_update_scratch_buffer(sctx, sctx->vs_shader))
1240 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
1241 }
1242
1243 /* TES can be bound as ES or VS. */
1244 if (sctx->gs_shader) {
1245 if (si_update_scratch_buffer(sctx, sctx->tes_shader))
1246 si_pm4_bind_state(sctx, es, sctx->tes_shader->current->pm4);
1247 } else {
1248 if (si_update_scratch_buffer(sctx, sctx->tes_shader))
1249 si_pm4_bind_state(sctx, vs, sctx->tes_shader->current->pm4);
1250 }
1251 }
1252
1253 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
1254 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
1255 "scratch size should already be aligned correctly.");
1256
1257 sctx->spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
1258 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
1259 }
1260
1261 static void si_init_tess_factor_ring(struct si_context *sctx)
1262 {
1263 assert(!sctx->tf_ring);
1264
1265 sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1266 PIPE_USAGE_DEFAULT,
1267 32768 * sctx->screen->b.info.max_se);
1268 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
1269
1270 /* Append these registers to the init config state. */
1271 if (sctx->b.chip_class >= CIK) {
1272 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
1273 S_030938_SIZE(sctx->tf_ring->width0 / 4));
1274 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
1275 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1276 } else {
1277 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
1278 S_008988_SIZE(sctx->tf_ring->width0 / 4));
1279 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
1280 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1281 }
1282
1283 /* Flush the context to re-emit the init_config state.
1284 * This is done only once in a lifetime of a context.
1285 */
1286 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1287 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1288
1289 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_TESS_CTRL,
1290 SI_RING_TESS_FACTOR, sctx->tf_ring, 0,
1291 sctx->tf_ring->width0, false, false, 0, 0, 0);
1292 }
1293
1294 /**
1295 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
1296 * VS passes its outputs to TES directly, so the fixed-function shader only
1297 * has to write TESSOUTER and TESSINNER.
1298 */
1299 static void si_generate_fixed_func_tcs(struct si_context *sctx)
1300 {
1301 struct ureg_src const0, const1;
1302 struct ureg_dst tessouter, tessinner;
1303 struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
1304
1305 if (!ureg)
1306 return; /* if we get here, we're screwed */
1307
1308 assert(!sctx->fixed_func_tcs_shader);
1309
1310 ureg_DECL_constant2D(ureg, 0, 1, SI_DRIVER_STATE_CONST_BUF);
1311 const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 0),
1312 SI_DRIVER_STATE_CONST_BUF);
1313 const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 1),
1314 SI_DRIVER_STATE_CONST_BUF);
1315
1316 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1317 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1318
1319 ureg_MOV(ureg, tessouter, const0);
1320 ureg_MOV(ureg, tessinner, const1);
1321 ureg_END(ureg);
1322
1323 sctx->fixed_func_tcs_shader =
1324 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
1325 assert(sctx->fixed_func_tcs_shader);
1326 }
1327
1328 static void si_update_vgt_shader_config(struct si_context *sctx)
1329 {
1330 /* Calculate the index of the config.
1331 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
1332 unsigned index = 2*!!sctx->tes_shader + !!sctx->gs_shader;
1333 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
1334
1335 if (!*pm4) {
1336 uint32_t stages = 0;
1337
1338 *pm4 = CALLOC_STRUCT(si_pm4_state);
1339
1340 if (sctx->tes_shader) {
1341 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
1342 S_028B54_HS_EN(1);
1343
1344 if (sctx->gs_shader)
1345 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
1346 S_028B54_GS_EN(1) |
1347 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1348 else
1349 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
1350 } else if (sctx->gs_shader) {
1351 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1352 S_028B54_GS_EN(1) |
1353 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1354 }
1355
1356 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
1357 }
1358 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
1359 }
1360
1361 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
1362 {
1363 struct pipe_stream_output_info *so = &shader->so;
1364 uint32_t enabled_stream_buffers_mask = 0;
1365 int i;
1366
1367 for (i = 0; i < so->num_outputs; i++)
1368 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
1369 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
1370 sctx->b.streamout.stride_in_dw = shader->so.stride;
1371 }
1372
1373 void si_update_shaders(struct si_context *sctx)
1374 {
1375 struct pipe_context *ctx = (struct pipe_context*)sctx;
1376 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1377
1378 /* Update stages before GS. */
1379 if (sctx->tes_shader) {
1380 if (!sctx->tf_ring)
1381 si_init_tess_factor_ring(sctx);
1382
1383 /* VS as LS */
1384 si_shader_select(ctx, sctx->vs_shader);
1385 si_pm4_bind_state(sctx, ls, sctx->vs_shader->current->pm4);
1386
1387 if (sctx->tcs_shader) {
1388 si_shader_select(ctx, sctx->tcs_shader);
1389 si_pm4_bind_state(sctx, hs, sctx->tcs_shader->current->pm4);
1390 } else {
1391 if (!sctx->fixed_func_tcs_shader)
1392 si_generate_fixed_func_tcs(sctx);
1393 si_shader_select(ctx, sctx->fixed_func_tcs_shader);
1394 si_pm4_bind_state(sctx, hs,
1395 sctx->fixed_func_tcs_shader->current->pm4);
1396 }
1397
1398 si_shader_select(ctx, sctx->tes_shader);
1399 if (sctx->gs_shader) {
1400 /* TES as ES */
1401 si_pm4_bind_state(sctx, es, sctx->tes_shader->current->pm4);
1402 } else {
1403 /* TES as VS */
1404 si_pm4_bind_state(sctx, vs, sctx->tes_shader->current->pm4);
1405 si_update_so(sctx, sctx->tes_shader);
1406 }
1407 } else if (sctx->gs_shader) {
1408 /* VS as ES */
1409 si_shader_select(ctx, sctx->vs_shader);
1410 si_pm4_bind_state(sctx, es, sctx->vs_shader->current->pm4);
1411 } else {
1412 /* VS as VS */
1413 si_shader_select(ctx, sctx->vs_shader);
1414 si_pm4_bind_state(sctx, vs, sctx->vs_shader->current->pm4);
1415 si_update_so(sctx, sctx->vs_shader);
1416 }
1417
1418 /* Update GS. */
1419 if (sctx->gs_shader) {
1420 si_shader_select(ctx, sctx->gs_shader);
1421 si_pm4_bind_state(sctx, gs, sctx->gs_shader->current->pm4);
1422 si_pm4_bind_state(sctx, vs, sctx->gs_shader->current->gs_copy_shader->pm4);
1423 si_update_so(sctx, sctx->gs_shader);
1424
1425 if (!sctx->gsvs_ring)
1426 si_init_gs_rings(sctx);
1427
1428 si_update_gs_rings(sctx);
1429 } else {
1430 si_pm4_bind_state(sctx, gs, NULL);
1431 si_pm4_bind_state(sctx, es, NULL);
1432 }
1433
1434 si_update_vgt_shader_config(sctx);
1435
1436 si_shader_select(ctx, sctx->ps_shader);
1437
1438 if (!sctx->ps_shader->current) {
1439 struct si_shader_selector *sel;
1440
1441 /* use a dummy shader if compiling the shader (variant) failed */
1442 si_make_dummy_ps(sctx);
1443 sel = sctx->dummy_pixel_shader;
1444 si_shader_select(ctx, sel);
1445 sctx->ps_shader->current = sel->current;
1446 }
1447
1448 si_pm4_bind_state(sctx, ps, sctx->ps_shader->current->pm4);
1449
1450 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
1451 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
1452 sctx->flatshade != rs->flatshade) {
1453 sctx->sprite_coord_enable = rs->sprite_coord_enable;
1454 sctx->flatshade = rs->flatshade;
1455 si_update_spi_map(sctx);
1456 }
1457
1458 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
1459 si_pm4_state_changed(sctx, gs)) {
1460 si_update_spi_tmpring_size(sctx);
1461 }
1462
1463 if (sctx->ps_db_shader_control != sctx->ps_shader->current->db_shader_control) {
1464 sctx->ps_db_shader_control = sctx->ps_shader->current->db_shader_control;
1465 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1466 }
1467
1468 if (sctx->smoothing_enabled != sctx->ps_shader->current->key.ps.poly_line_smoothing) {
1469 sctx->smoothing_enabled = sctx->ps_shader->current->key.ps.poly_line_smoothing;
1470 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1471
1472 if (sctx->b.chip_class == SI)
1473 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1474 }
1475 }
1476
1477 void si_init_shader_functions(struct si_context *sctx)
1478 {
1479 sctx->b.b.create_vs_state = si_create_vs_state;
1480 sctx->b.b.create_tcs_state = si_create_tcs_state;
1481 sctx->b.b.create_tes_state = si_create_tes_state;
1482 sctx->b.b.create_gs_state = si_create_gs_state;
1483 sctx->b.b.create_fs_state = si_create_fs_state;
1484
1485 sctx->b.b.bind_vs_state = si_bind_vs_shader;
1486 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
1487 sctx->b.b.bind_tes_state = si_bind_tes_shader;
1488 sctx->b.b.bind_gs_state = si_bind_gs_shader;
1489 sctx->b.b.bind_fs_state = si_bind_ps_shader;
1490
1491 sctx->b.b.delete_vs_state = si_delete_vs_shader;
1492 sctx->b.b.delete_tcs_state = si_delete_tcs_shader;
1493 sctx->b.b.delete_tes_state = si_delete_tes_shader;
1494 sctx->b.b.delete_gs_state = si_delete_gs_shader;
1495 sctx->b.b.delete_fs_state = si_delete_ps_shader;
1496 }