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radeonsi: make si_init_shader_selector_async static
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "sid.h"
30 #include "gfx9d.h"
31 #include "radeon/r600_cs.h"
32
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/hash_table.h"
36 #include "util/crc32.h"
37 #include "util/u_memory.h"
38 #include "util/u_prim.h"
39
40 #include "util/disk_cache.h"
41 #include "util/mesa-sha1.h"
42 #include "ac_exp_param.h"
43
44 /* SHADER_CACHE */
45
46 /**
47 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
48 * integer.
49 */
50 static void *si_get_tgsi_binary(struct si_shader_selector *sel)
51 {
52 unsigned tgsi_size = tgsi_num_tokens(sel->tokens) *
53 sizeof(struct tgsi_token);
54 unsigned size = 4 + tgsi_size + sizeof(sel->so);
55 char *result = (char*)MALLOC(size);
56
57 if (!result)
58 return NULL;
59
60 *((uint32_t*)result) = size;
61 memcpy(result + 4, sel->tokens, tgsi_size);
62 memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so));
63 return result;
64 }
65
66 /** Copy "data" to "ptr" and return the next dword following copied data. */
67 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
68 {
69 /* data may be NULL if size == 0 */
70 if (size)
71 memcpy(ptr, data, size);
72 ptr += DIV_ROUND_UP(size, 4);
73 return ptr;
74 }
75
76 /** Read data from "ptr". Return the next dword following the data. */
77 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
78 {
79 memcpy(data, ptr, size);
80 ptr += DIV_ROUND_UP(size, 4);
81 return ptr;
82 }
83
84 /**
85 * Write the size as uint followed by the data. Return the next dword
86 * following the copied data.
87 */
88 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
89 {
90 *ptr++ = size;
91 return write_data(ptr, data, size);
92 }
93
94 /**
95 * Read the size as uint followed by the data. Return both via parameters.
96 * Return the next dword following the data.
97 */
98 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
99 {
100 *size = *ptr++;
101 assert(*data == NULL);
102 if (!*size)
103 return ptr;
104 *data = malloc(*size);
105 return read_data(ptr, *data, *size);
106 }
107
108 /**
109 * Return the shader binary in a buffer. The first 4 bytes contain its size
110 * as integer.
111 */
112 static void *si_get_shader_binary(struct si_shader *shader)
113 {
114 /* There is always a size of data followed by the data itself. */
115 unsigned relocs_size = shader->binary.reloc_count *
116 sizeof(shader->binary.relocs[0]);
117 unsigned disasm_size = shader->binary.disasm_string ?
118 strlen(shader->binary.disasm_string) + 1 : 0;
119 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
120 strlen(shader->binary.llvm_ir_string) + 1 : 0;
121 unsigned size =
122 4 + /* total size */
123 4 + /* CRC32 of the data below */
124 align(sizeof(shader->config), 4) +
125 align(sizeof(shader->info), 4) +
126 4 + align(shader->binary.code_size, 4) +
127 4 + align(shader->binary.rodata_size, 4) +
128 4 + align(relocs_size, 4) +
129 4 + align(disasm_size, 4) +
130 4 + align(llvm_ir_size, 4);
131 void *buffer = CALLOC(1, size);
132 uint32_t *ptr = (uint32_t*)buffer;
133
134 if (!buffer)
135 return NULL;
136
137 *ptr++ = size;
138 ptr++; /* CRC32 is calculated at the end. */
139
140 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
141 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
142 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
143 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
144 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
145 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
146 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
147 assert((char *)ptr - (char *)buffer == size);
148
149 /* Compute CRC32. */
150 ptr = (uint32_t*)buffer;
151 ptr++;
152 *ptr = util_hash_crc32(ptr + 1, size - 8);
153
154 return buffer;
155 }
156
157 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
158 {
159 uint32_t *ptr = (uint32_t*)binary;
160 uint32_t size = *ptr++;
161 uint32_t crc32 = *ptr++;
162 unsigned chunk_size;
163
164 if (util_hash_crc32(ptr, size - 8) != crc32) {
165 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
166 return false;
167 }
168
169 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
170 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
171 ptr = read_chunk(ptr, (void**)&shader->binary.code,
172 &shader->binary.code_size);
173 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
174 &shader->binary.rodata_size);
175 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
176 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
177 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
178 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
179
180 return true;
181 }
182
183 /**
184 * Insert a shader into the cache. It's assumed the shader is not in the cache.
185 * Use si_shader_cache_load_shader before calling this.
186 *
187 * Returns false on failure, in which case the tgsi_binary should be freed.
188 */
189 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
190 void *tgsi_binary,
191 struct si_shader *shader,
192 bool insert_into_disk_cache)
193 {
194 void *hw_binary;
195 struct hash_entry *entry;
196 uint8_t key[CACHE_KEY_SIZE];
197
198 entry = _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
199 if (entry)
200 return false; /* already added */
201
202 hw_binary = si_get_shader_binary(shader);
203 if (!hw_binary)
204 return false;
205
206 if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
207 hw_binary) == NULL) {
208 FREE(hw_binary);
209 return false;
210 }
211
212 if (sscreen->b.disk_shader_cache && insert_into_disk_cache) {
213 disk_cache_compute_key(sscreen->b.disk_shader_cache, tgsi_binary,
214 *((uint32_t *)tgsi_binary), key);
215 disk_cache_put(sscreen->b.disk_shader_cache, key, hw_binary,
216 *((uint32_t *) hw_binary), NULL);
217 }
218
219 return true;
220 }
221
222 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
223 void *tgsi_binary,
224 struct si_shader *shader)
225 {
226 struct hash_entry *entry =
227 _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
228 if (!entry) {
229 if (sscreen->b.disk_shader_cache) {
230 unsigned char sha1[CACHE_KEY_SIZE];
231 size_t tg_size = *((uint32_t *) tgsi_binary);
232
233 disk_cache_compute_key(sscreen->b.disk_shader_cache,
234 tgsi_binary, tg_size, sha1);
235
236 size_t binary_size;
237 uint8_t *buffer =
238 disk_cache_get(sscreen->b.disk_shader_cache,
239 sha1, &binary_size);
240 if (!buffer)
241 return false;
242
243 if (binary_size < sizeof(uint32_t) ||
244 *((uint32_t*)buffer) != binary_size) {
245 /* Something has gone wrong discard the item
246 * from the cache and rebuild/link from
247 * source.
248 */
249 assert(!"Invalid radeonsi shader disk cache "
250 "item!");
251
252 disk_cache_remove(sscreen->b.disk_shader_cache,
253 sha1);
254 free(buffer);
255
256 return false;
257 }
258
259 if (!si_load_shader_binary(shader, buffer)) {
260 free(buffer);
261 return false;
262 }
263 free(buffer);
264
265 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary,
266 shader, false))
267 FREE(tgsi_binary);
268 } else {
269 return false;
270 }
271 } else {
272 if (si_load_shader_binary(shader, entry->data))
273 FREE(tgsi_binary);
274 else
275 return false;
276 }
277 p_atomic_inc(&sscreen->b.num_shader_cache_hits);
278 return true;
279 }
280
281 static uint32_t si_shader_cache_key_hash(const void *key)
282 {
283 /* The first dword is the key size. */
284 return util_hash_crc32(key, *(uint32_t*)key);
285 }
286
287 static bool si_shader_cache_key_equals(const void *a, const void *b)
288 {
289 uint32_t *keya = (uint32_t*)a;
290 uint32_t *keyb = (uint32_t*)b;
291
292 /* The first dword is the key size. */
293 if (*keya != *keyb)
294 return false;
295
296 return memcmp(keya, keyb, *keya) == 0;
297 }
298
299 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
300 {
301 FREE((void*)entry->key);
302 FREE(entry->data);
303 }
304
305 bool si_init_shader_cache(struct si_screen *sscreen)
306 {
307 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
308 sscreen->shader_cache =
309 _mesa_hash_table_create(NULL,
310 si_shader_cache_key_hash,
311 si_shader_cache_key_equals);
312
313 return sscreen->shader_cache != NULL;
314 }
315
316 void si_destroy_shader_cache(struct si_screen *sscreen)
317 {
318 if (sscreen->shader_cache)
319 _mesa_hash_table_destroy(sscreen->shader_cache,
320 si_destroy_shader_cache_entry);
321 mtx_destroy(&sscreen->shader_cache_mutex);
322 }
323
324 /* SHADER STATES */
325
326 static void si_set_tesseval_regs(struct si_screen *sscreen,
327 struct si_shader_selector *tes,
328 struct si_pm4_state *pm4)
329 {
330 struct tgsi_shader_info *info = &tes->info;
331 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
332 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
333 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
334 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
335 unsigned type, partitioning, topology, distribution_mode;
336
337 switch (tes_prim_mode) {
338 case PIPE_PRIM_LINES:
339 type = V_028B6C_TESS_ISOLINE;
340 break;
341 case PIPE_PRIM_TRIANGLES:
342 type = V_028B6C_TESS_TRIANGLE;
343 break;
344 case PIPE_PRIM_QUADS:
345 type = V_028B6C_TESS_QUAD;
346 break;
347 default:
348 assert(0);
349 return;
350 }
351
352 switch (tes_spacing) {
353 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
354 partitioning = V_028B6C_PART_FRAC_ODD;
355 break;
356 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
357 partitioning = V_028B6C_PART_FRAC_EVEN;
358 break;
359 case PIPE_TESS_SPACING_EQUAL:
360 partitioning = V_028B6C_PART_INTEGER;
361 break;
362 default:
363 assert(0);
364 return;
365 }
366
367 if (tes_point_mode)
368 topology = V_028B6C_OUTPUT_POINT;
369 else if (tes_prim_mode == PIPE_PRIM_LINES)
370 topology = V_028B6C_OUTPUT_LINE;
371 else if (tes_vertex_order_cw)
372 /* for some reason, this must be the other way around */
373 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
374 else
375 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
376
377 if (sscreen->has_distributed_tess) {
378 if (sscreen->b.family == CHIP_FIJI ||
379 sscreen->b.family >= CHIP_POLARIS10)
380 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
381 else
382 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
383 } else
384 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
385
386 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
387 S_028B6C_TYPE(type) |
388 S_028B6C_PARTITIONING(partitioning) |
389 S_028B6C_TOPOLOGY(topology) |
390 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
391 }
392
393 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
394 * whether the "fractional odd" tessellation spacing is used.
395 *
396 * Possible VGT configurations and which state should set the register:
397 *
398 * Reg set in | VGT shader configuration | Value
399 * ------------------------------------------------------
400 * VS as VS | VS | 30
401 * VS as ES | ES -> GS -> VS | 30
402 * TES as VS | LS -> HS -> VS | 14 or 30
403 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
404 *
405 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
406 */
407 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
408 struct si_shader_selector *sel,
409 struct si_shader *shader,
410 struct si_pm4_state *pm4)
411 {
412 unsigned type = sel->type;
413
414 if (sscreen->b.family < CHIP_POLARIS10)
415 return;
416
417 /* VS as VS, or VS as ES: */
418 if ((type == PIPE_SHADER_VERTEX &&
419 (!shader ||
420 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
421 /* TES as VS, or TES as ES: */
422 type == PIPE_SHADER_TESS_EVAL) {
423 unsigned vtx_reuse_depth = 30;
424
425 if (type == PIPE_SHADER_TESS_EVAL &&
426 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
427 PIPE_TESS_SPACING_FRACTIONAL_ODD)
428 vtx_reuse_depth = 14;
429
430 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
431 vtx_reuse_depth);
432 }
433 }
434
435 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
436 {
437 if (shader->pm4)
438 si_pm4_clear_state(shader->pm4);
439 else
440 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
441
442 return shader->pm4;
443 }
444
445 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
446 {
447 struct si_pm4_state *pm4;
448 unsigned vgpr_comp_cnt;
449 uint64_t va;
450
451 assert(sscreen->b.chip_class <= VI);
452
453 pm4 = si_get_shader_pm4_state(shader);
454 if (!pm4)
455 return;
456
457 va = shader->bo->gpu_address;
458 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
459
460 /* We need at least 2 components for LS.
461 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
462 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
463 */
464 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
465
466 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
467 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
468
469 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
470 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
471 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
472 S_00B528_DX10_CLAMP(1) |
473 S_00B528_FLOAT_MODE(shader->config.float_mode);
474 shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_VS_NUM_USER_SGPR) |
475 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
476 }
477
478 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
479 {
480 struct si_pm4_state *pm4;
481 uint64_t va;
482 unsigned ls_vgpr_comp_cnt = 0;
483
484 pm4 = si_get_shader_pm4_state(shader);
485 if (!pm4)
486 return;
487
488 va = shader->bo->gpu_address;
489 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
490
491 if (sscreen->b.chip_class >= GFX9) {
492 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
493 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, va >> 40);
494
495 /* We need at least 2 components for LS.
496 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
497 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
498 */
499 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
500
501 shader->config.rsrc2 =
502 S_00B42C_USER_SGPR(GFX9_TCS_NUM_USER_SGPR) |
503 S_00B42C_USER_SGPR_MSB(GFX9_TCS_NUM_USER_SGPR >> 5) |
504 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
505 } else {
506 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
507 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
508
509 shader->config.rsrc2 =
510 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
511 S_00B42C_OC_LDS_EN(1) |
512 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
513 }
514
515 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
516 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
517 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
518 S_00B428_DX10_CLAMP(1) |
519 S_00B428_FLOAT_MODE(shader->config.float_mode) |
520 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
521
522 if (sscreen->b.chip_class <= VI) {
523 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
524 shader->config.rsrc2);
525 }
526 }
527
528 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
529 {
530 struct si_pm4_state *pm4;
531 unsigned num_user_sgprs;
532 unsigned vgpr_comp_cnt;
533 uint64_t va;
534 unsigned oc_lds_en;
535
536 assert(sscreen->b.chip_class <= VI);
537
538 pm4 = si_get_shader_pm4_state(shader);
539 if (!pm4)
540 return;
541
542 va = shader->bo->gpu_address;
543 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
544
545 if (shader->selector->type == PIPE_SHADER_VERTEX) {
546 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
547 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
548 num_user_sgprs = SI_VS_NUM_USER_SGPR;
549 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
550 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
551 num_user_sgprs = SI_TES_NUM_USER_SGPR;
552 } else
553 unreachable("invalid shader selector type");
554
555 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
556
557 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
558 shader->selector->esgs_itemsize / 4);
559 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
560 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
561 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
562 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
563 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
564 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
565 S_00B328_DX10_CLAMP(1) |
566 S_00B328_FLOAT_MODE(shader->config.float_mode));
567 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
568 S_00B32C_USER_SGPR(num_user_sgprs) |
569 S_00B32C_OC_LDS_EN(oc_lds_en) |
570 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
571
572 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
573 si_set_tesseval_regs(sscreen, shader->selector, pm4);
574
575 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
576 }
577
578 /**
579 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
580 * geometry shader.
581 */
582 static uint32_t si_vgt_gs_mode(struct si_shader_selector *sel)
583 {
584 enum chip_class chip_class = sel->screen->b.chip_class;
585 unsigned gs_max_vert_out = sel->gs_max_out_vertices;
586 unsigned cut_mode;
587
588 if (gs_max_vert_out <= 128) {
589 cut_mode = V_028A40_GS_CUT_128;
590 } else if (gs_max_vert_out <= 256) {
591 cut_mode = V_028A40_GS_CUT_256;
592 } else if (gs_max_vert_out <= 512) {
593 cut_mode = V_028A40_GS_CUT_512;
594 } else {
595 assert(gs_max_vert_out <= 1024);
596 cut_mode = V_028A40_GS_CUT_1024;
597 }
598
599 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
600 S_028A40_CUT_MODE(cut_mode)|
601 S_028A40_ES_WRITE_OPTIMIZE(chip_class <= VI) |
602 S_028A40_GS_WRITE_OPTIMIZE(1) |
603 S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0);
604 }
605
606 struct gfx9_gs_info {
607 unsigned es_verts_per_subgroup;
608 unsigned gs_prims_per_subgroup;
609 unsigned gs_inst_prims_in_subgroup;
610 unsigned max_prims_per_subgroup;
611 unsigned lds_size;
612 };
613
614 static void gfx9_get_gs_info(struct si_shader_selector *es,
615 struct si_shader_selector *gs,
616 struct gfx9_gs_info *out)
617 {
618 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
619 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
620 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
621 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
622
623 /* All these are in dwords: */
624 /* We can't allow using the whole LDS, because GS waves compete with
625 * other shader stages for LDS space. */
626 const unsigned max_lds_size = 8 * 1024;
627 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
628 unsigned esgs_lds_size;
629
630 /* All these are per subgroup: */
631 const unsigned max_out_prims = 32 * 1024;
632 const unsigned max_es_verts = 255;
633 const unsigned ideal_gs_prims = 64;
634 unsigned max_gs_prims, gs_prims;
635 unsigned min_es_verts, es_verts, worst_case_es_verts;
636
637 assert(gs_num_invocations <= 32); /* GL maximum */
638
639 if (uses_adjacency || gs_num_invocations > 1)
640 max_gs_prims = 127 / gs_num_invocations;
641 else
642 max_gs_prims = 255;
643
644 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
645 * Make sure we don't go over the maximum value.
646 */
647 max_gs_prims = MIN2(max_gs_prims,
648 max_out_prims /
649 (gs->gs_max_out_vertices * gs_num_invocations));
650 assert(max_gs_prims > 0);
651
652 /* If the primitive has adjacency, halve the number of vertices
653 * that will be reused in multiple primitives.
654 */
655 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
656
657 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
658 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
659
660 /* Compute ESGS LDS size based on the worst case number of ES vertices
661 * needed to create the target number of GS prims per subgroup.
662 */
663 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
664
665 /* If total LDS usage is too big, refactor partitions based on ratio
666 * of ESGS item sizes.
667 */
668 if (esgs_lds_size > max_lds_size) {
669 /* Our target GS Prims Per Subgroup was too large. Calculate
670 * the maximum number of GS Prims Per Subgroup that will fit
671 * into LDS, capped by the maximum that the hardware can support.
672 */
673 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
674 max_gs_prims);
675 assert(gs_prims > 0);
676 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
677 max_es_verts);
678
679 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
680 assert(esgs_lds_size <= max_lds_size);
681 }
682
683 /* Now calculate remaining ESGS information. */
684 if (esgs_lds_size)
685 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
686 else
687 es_verts = max_es_verts;
688
689 /* Vertices for adjacency primitives are not always reused, so restore
690 * it for ES_VERTS_PER_SUBGRP.
691 */
692 min_es_verts = gs->gs_input_verts_per_prim;
693
694 /* For normal primitives, the VGT only checks if they are past the ES
695 * verts per subgroup after allocating a full GS primitive and if they
696 * are, kick off a new subgroup. But if those additional ES verts are
697 * unique (e.g. not reused) we need to make sure there is enough LDS
698 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
699 */
700 es_verts -= min_es_verts - 1;
701
702 out->es_verts_per_subgroup = es_verts;
703 out->gs_prims_per_subgroup = gs_prims;
704 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
705 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
706 gs->gs_max_out_vertices;
707 out->lds_size = align(esgs_lds_size, 128) / 128;
708
709 assert(out->max_prims_per_subgroup <= max_out_prims);
710 }
711
712 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
713 {
714 struct si_shader_selector *sel = shader->selector;
715 const ubyte *num_components = sel->info.num_stream_output_components;
716 unsigned gs_num_invocations = sel->gs_num_invocations;
717 struct si_pm4_state *pm4;
718 uint64_t va;
719 unsigned max_stream = sel->max_gs_stream;
720 unsigned offset;
721
722 pm4 = si_get_shader_pm4_state(shader);
723 if (!pm4)
724 return;
725
726 offset = num_components[0] * sel->gs_max_out_vertices;
727 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, offset);
728 if (max_stream >= 1)
729 offset += num_components[1] * sel->gs_max_out_vertices;
730 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, offset);
731 if (max_stream >= 2)
732 offset += num_components[2] * sel->gs_max_out_vertices;
733 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, offset);
734 if (max_stream >= 3)
735 offset += num_components[3] * sel->gs_max_out_vertices;
736 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
737
738 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
739 assert(offset < (1 << 15));
740
741 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, sel->gs_max_out_vertices);
742
743 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, num_components[0]);
744 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? num_components[1] : 0);
745 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? num_components[2] : 0);
746 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? num_components[3] : 0);
747
748 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
749 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
750 S_028B90_ENABLE(gs_num_invocations > 0));
751
752 va = shader->bo->gpu_address;
753 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
754
755 if (sscreen->b.chip_class >= GFX9) {
756 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
757 unsigned es_type = shader->key.part.gs.es->type;
758 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
759 struct gfx9_gs_info gs_info;
760
761 if (es_type == PIPE_SHADER_VERTEX)
762 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
763 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
764 else if (es_type == PIPE_SHADER_TESS_EVAL)
765 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
766 else
767 unreachable("invalid shader selector type");
768
769 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
770 * VGPR[0:4] are always loaded.
771 */
772 if (sel->info.uses_invocationid)
773 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
774 else if (sel->info.uses_primid)
775 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
776 else if (input_prim >= PIPE_PRIM_TRIANGLES)
777 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
778 else
779 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
780
781 gfx9_get_gs_info(shader->key.part.gs.es, sel, &gs_info);
782
783 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
784 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, va >> 40);
785
786 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
787 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
788 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
789 S_00B228_DX10_CLAMP(1) |
790 S_00B228_FLOAT_MODE(shader->config.float_mode) |
791 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
792 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
793 S_00B22C_USER_SGPR(GFX9_GS_NUM_USER_SGPR) |
794 S_00B22C_USER_SGPR_MSB(GFX9_GS_NUM_USER_SGPR >> 5) |
795 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
796 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
797 S_00B22C_LDS_SIZE(gs_info.lds_size) |
798 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
799
800 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
801 S_028A44_ES_VERTS_PER_SUBGRP(gs_info.es_verts_per_subgroup) |
802 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info.gs_prims_per_subgroup) |
803 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info.gs_inst_prims_in_subgroup));
804 si_pm4_set_reg(pm4, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
805 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info.max_prims_per_subgroup));
806 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
807 shader->key.part.gs.es->esgs_itemsize / 4);
808
809 if (es_type == PIPE_SHADER_TESS_EVAL)
810 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
811
812 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
813 NULL, pm4);
814 } else {
815 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
816 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
817
818 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
819 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
820 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
821 S_00B228_DX10_CLAMP(1) |
822 S_00B228_FLOAT_MODE(shader->config.float_mode));
823 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
824 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
825 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
826 }
827 }
828
829 /**
830 * Compute the state for \p shader, which will run as a vertex shader on the
831 * hardware.
832 *
833 * If \p gs is non-NULL, it points to the geometry shader for which this shader
834 * is the copy shader.
835 */
836 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
837 struct si_shader_selector *gs)
838 {
839 const struct tgsi_shader_info *info = &shader->selector->info;
840 struct si_pm4_state *pm4;
841 unsigned num_user_sgprs;
842 unsigned nparams, vgpr_comp_cnt;
843 uint64_t va;
844 unsigned oc_lds_en;
845 unsigned window_space =
846 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
847 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
848
849 pm4 = si_get_shader_pm4_state(shader);
850 if (!pm4)
851 return;
852
853 /* We always write VGT_GS_MODE in the VS state, because every switch
854 * between different shader pipelines involving a different GS or no
855 * GS at all involves a switch of the VS (different GS use different
856 * copy shaders). On the other hand, when the API switches from a GS to
857 * no GS and then back to the same GS used originally, the GS state is
858 * not sent again.
859 */
860 if (!gs) {
861 unsigned mode = V_028A40_GS_OFF;
862
863 /* PrimID needs GS scenario A. */
864 if (enable_prim_id)
865 mode = V_028A40_GS_SCENARIO_A;
866
867 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, S_028A40_MODE(mode));
868 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
869 } else {
870 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
871 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
872 }
873
874 if (sscreen->b.chip_class <= VI) {
875 /* Reuse needs to be set off if we write oViewport. */
876 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF,
877 S_028AB4_REUSE_OFF(info->writes_viewport_index));
878 }
879
880 va = shader->bo->gpu_address;
881 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
882
883 if (gs) {
884 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
885 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
886 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
887 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
888 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
889 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
890 */
891 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
892 num_user_sgprs = SI_VS_NUM_USER_SGPR;
893 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
894 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
895 num_user_sgprs = SI_TES_NUM_USER_SGPR;
896 } else
897 unreachable("invalid shader selector type");
898
899 /* VS is required to export at least one param. */
900 nparams = MAX2(shader->info.nr_param_exports, 1);
901 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
902 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
903
904 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
905 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
906 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
907 V_02870C_SPI_SHADER_4COMP :
908 V_02870C_SPI_SHADER_NONE) |
909 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
910 V_02870C_SPI_SHADER_4COMP :
911 V_02870C_SPI_SHADER_NONE) |
912 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
913 V_02870C_SPI_SHADER_4COMP :
914 V_02870C_SPI_SHADER_NONE));
915
916 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
917
918 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
919 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
920 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
921 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
922 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
923 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
924 S_00B128_DX10_CLAMP(1) |
925 S_00B128_FLOAT_MODE(shader->config.float_mode));
926 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
927 S_00B12C_USER_SGPR(num_user_sgprs) |
928 S_00B12C_OC_LDS_EN(oc_lds_en) |
929 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
930 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
931 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
932 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
933 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
934 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
935 if (window_space)
936 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
937 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
938 else
939 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
940 S_028818_VTX_W0_FMT(1) |
941 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
942 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
943 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
944
945 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
946 si_set_tesseval_regs(sscreen, shader->selector, pm4);
947
948 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
949 }
950
951 static unsigned si_get_ps_num_interp(struct si_shader *ps)
952 {
953 struct tgsi_shader_info *info = &ps->selector->info;
954 unsigned num_colors = !!(info->colors_read & 0x0f) +
955 !!(info->colors_read & 0xf0);
956 unsigned num_interp = ps->selector->info.num_inputs +
957 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
958
959 assert(num_interp <= 32);
960 return MIN2(num_interp, 32);
961 }
962
963 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
964 {
965 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
966 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
967
968 /* If the i-th target format is set, all previous target formats must
969 * be non-zero to avoid hangs.
970 */
971 for (i = 0; i < num_targets; i++)
972 if (!(value & (0xf << (i * 4))))
973 value |= V_028714_SPI_SHADER_32_R << (i * 4);
974
975 return value;
976 }
977
978 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
979 {
980 unsigned i, cb_shader_mask = 0;
981
982 for (i = 0; i < 8; i++) {
983 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
984 case V_028714_SPI_SHADER_ZERO:
985 break;
986 case V_028714_SPI_SHADER_32_R:
987 cb_shader_mask |= 0x1 << (i * 4);
988 break;
989 case V_028714_SPI_SHADER_32_GR:
990 cb_shader_mask |= 0x3 << (i * 4);
991 break;
992 case V_028714_SPI_SHADER_32_AR:
993 cb_shader_mask |= 0x9 << (i * 4);
994 break;
995 case V_028714_SPI_SHADER_FP16_ABGR:
996 case V_028714_SPI_SHADER_UNORM16_ABGR:
997 case V_028714_SPI_SHADER_SNORM16_ABGR:
998 case V_028714_SPI_SHADER_UINT16_ABGR:
999 case V_028714_SPI_SHADER_SINT16_ABGR:
1000 case V_028714_SPI_SHADER_32_ABGR:
1001 cb_shader_mask |= 0xf << (i * 4);
1002 break;
1003 default:
1004 assert(0);
1005 }
1006 }
1007 return cb_shader_mask;
1008 }
1009
1010 static void si_shader_ps(struct si_shader *shader)
1011 {
1012 struct tgsi_shader_info *info = &shader->selector->info;
1013 struct si_pm4_state *pm4;
1014 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1015 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1016 uint64_t va;
1017 unsigned input_ena = shader->config.spi_ps_input_ena;
1018
1019 /* we need to enable at least one of them, otherwise we hang the GPU */
1020 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1021 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1022 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1023 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1024 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1025 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1026 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1027 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1028 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1029 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1030 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1031 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1032 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1033 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1034
1035 /* Validate interpolation optimization flags (read as implications). */
1036 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1037 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1038 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1039 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1040 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1041 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1042 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1043 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1044 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1045 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1046 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1047 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1048 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1049 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1050 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1051 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1052 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1053 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1054
1055 /* Validate cases when the optimizations are off (read as implications). */
1056 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1057 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1058 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1059 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1060 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1061 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1062
1063 pm4 = si_get_shader_pm4_state(shader);
1064 if (!pm4)
1065 return;
1066
1067 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1068 * Possible vaules:
1069 * 0 -> Position = pixel center
1070 * 1 -> Position = pixel centroid
1071 * 2 -> Position = at sample position
1072 *
1073 * From GLSL 4.5 specification, section 7.1:
1074 * "The variable gl_FragCoord is available as an input variable from
1075 * within fragment shaders and it holds the window relative coordinates
1076 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1077 * value can be for any location within the pixel, or one of the
1078 * fragment samples. The use of centroid does not further restrict
1079 * this value to be inside the current primitive."
1080 *
1081 * Meaning that centroid has no effect and we can return anything within
1082 * the pixel. Thus, return the value at sample position, because that's
1083 * the most accurate one shaders can get.
1084 */
1085 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1086
1087 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1088 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1089 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1090
1091 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1092 cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
1093
1094 /* Ensure that some export memory is always allocated, for two reasons:
1095 *
1096 * 1) Correctness: The hardware ignores the EXEC mask if no export
1097 * memory is allocated, so KILL and alpha test do not work correctly
1098 * without this.
1099 * 2) Performance: Every shader needs at least a NULL export, even when
1100 * it writes no color/depth output. The NULL export instruction
1101 * stalls without this setting.
1102 *
1103 * Don't add this to CB_SHADER_MASK.
1104 */
1105 if (!spi_shader_col_format &&
1106 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1107 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1108
1109 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
1110 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
1111 shader->config.spi_ps_input_addr);
1112
1113 /* Set interpolation controls. */
1114 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1115
1116 /* Set registers. */
1117 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1118 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
1119
1120 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
1121 si_get_spi_shader_z_format(info->writes_z,
1122 info->writes_stencil,
1123 info->writes_samplemask));
1124
1125 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
1126 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
1127
1128 va = shader->bo->gpu_address;
1129 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1130 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1131 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
1132
1133 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
1134 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1135 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
1136 S_00B028_DX10_CLAMP(1) |
1137 S_00B028_FLOAT_MODE(shader->config.float_mode));
1138 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1139 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1140 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1141 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1142 }
1143
1144 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1145 struct si_shader *shader)
1146 {
1147 switch (shader->selector->type) {
1148 case PIPE_SHADER_VERTEX:
1149 if (shader->key.as_ls)
1150 si_shader_ls(sscreen, shader);
1151 else if (shader->key.as_es)
1152 si_shader_es(sscreen, shader);
1153 else
1154 si_shader_vs(sscreen, shader, NULL);
1155 break;
1156 case PIPE_SHADER_TESS_CTRL:
1157 si_shader_hs(sscreen, shader);
1158 break;
1159 case PIPE_SHADER_TESS_EVAL:
1160 if (shader->key.as_es)
1161 si_shader_es(sscreen, shader);
1162 else
1163 si_shader_vs(sscreen, shader, NULL);
1164 break;
1165 case PIPE_SHADER_GEOMETRY:
1166 si_shader_gs(sscreen, shader);
1167 break;
1168 case PIPE_SHADER_FRAGMENT:
1169 si_shader_ps(shader);
1170 break;
1171 default:
1172 assert(0);
1173 }
1174 }
1175
1176 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1177 {
1178 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1179 if (sctx->queued.named.dsa)
1180 return sctx->queued.named.dsa->alpha_func;
1181
1182 return PIPE_FUNC_ALWAYS;
1183 }
1184
1185 static void si_shader_selector_key_vs(struct si_context *sctx,
1186 struct si_shader_selector *vs,
1187 struct si_shader_key *key,
1188 struct si_vs_prolog_bits *prolog_key)
1189 {
1190 if (!sctx->vertex_elements)
1191 return;
1192
1193 prolog_key->instance_divisor_is_one =
1194 sctx->vertex_elements->instance_divisor_is_one;
1195 prolog_key->instance_divisor_is_fetched =
1196 sctx->vertex_elements->instance_divisor_is_fetched;
1197
1198 /* Prefer a monolithic shader to allow scheduling divisions around
1199 * VBO loads. */
1200 if (prolog_key->instance_divisor_is_fetched)
1201 key->opt.prefer_mono = 1;
1202
1203 unsigned count = MIN2(vs->info.num_inputs,
1204 sctx->vertex_elements->count);
1205 memcpy(key->mono.vs_fix_fetch, sctx->vertex_elements->fix_fetch, count);
1206 }
1207
1208 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1209 struct si_shader_selector *vs,
1210 struct si_shader_key *key)
1211 {
1212 struct si_shader_selector *ps = sctx->ps_shader.cso;
1213
1214 key->opt.clip_disable =
1215 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1216 (vs->info.clipdist_writemask ||
1217 vs->info.writes_clipvertex) &&
1218 !vs->info.culldist_writemask;
1219
1220 /* Find out if PS is disabled. */
1221 bool ps_disabled = true;
1222 if (ps) {
1223 bool ps_modifies_zs = ps->info.uses_kill ||
1224 ps->info.writes_z ||
1225 ps->info.writes_stencil ||
1226 ps->info.writes_samplemask ||
1227 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1228
1229 unsigned ps_colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1230 sctx->queued.named.blend->cb_target_mask;
1231 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1232 ps_colormask &= ps->colors_written_4bit;
1233
1234 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1235 (!ps_colormask &&
1236 !ps_modifies_zs &&
1237 !ps->info.writes_memory);
1238 }
1239
1240 /* Find out which VS outputs aren't used by the PS. */
1241 uint64_t outputs_written = vs->outputs_written;
1242 uint64_t inputs_read = 0;
1243
1244 /* ignore POSITION, PSIZE */
1245 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0) |
1246 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0))));
1247
1248 if (!ps_disabled) {
1249 inputs_read = ps->inputs_read;
1250 }
1251
1252 uint64_t linked = outputs_written & inputs_read;
1253
1254 key->opt.kill_outputs = ~linked & outputs_written;
1255 }
1256
1257 /* Compute the key for the hw shader variant */
1258 static inline void si_shader_selector_key(struct pipe_context *ctx,
1259 struct si_shader_selector *sel,
1260 struct si_shader_key *key)
1261 {
1262 struct si_context *sctx = (struct si_context *)ctx;
1263
1264 memset(key, 0, sizeof(*key));
1265
1266 switch (sel->type) {
1267 case PIPE_SHADER_VERTEX:
1268 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1269
1270 if (sctx->tes_shader.cso)
1271 key->as_ls = 1;
1272 else if (sctx->gs_shader.cso)
1273 key->as_es = 1;
1274 else {
1275 si_shader_selector_key_hw_vs(sctx, sel, key);
1276
1277 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1278 key->mono.u.vs_export_prim_id = 1;
1279 }
1280 break;
1281 case PIPE_SHADER_TESS_CTRL:
1282 if (sctx->b.chip_class >= GFX9) {
1283 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1284 key, &key->part.tcs.ls_prolog);
1285 key->part.tcs.ls = sctx->vs_shader.cso;
1286
1287 /* When the LS VGPR fix is needed, monolithic shaders
1288 * can:
1289 * - avoid initializing EXEC in both the LS prolog
1290 * and the LS main part when !vs_needs_prolog
1291 * - remove the fixup for unused input VGPRs
1292 */
1293 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1294
1295 /* The LS output / HS input layout can be communicated
1296 * directly instead of via user SGPRs for merged LS-HS.
1297 * The LS VGPR fix prefers this too.
1298 */
1299 key->opt.prefer_mono = 1;
1300 }
1301
1302 key->part.tcs.epilog.prim_mode =
1303 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1304 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1305 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1306 key->part.tcs.epilog.tes_reads_tess_factors =
1307 sctx->tes_shader.cso->info.reads_tess_factors;
1308
1309 if (sel == sctx->fixed_func_tcs_shader.cso)
1310 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1311 break;
1312 case PIPE_SHADER_TESS_EVAL:
1313 if (sctx->gs_shader.cso)
1314 key->as_es = 1;
1315 else {
1316 si_shader_selector_key_hw_vs(sctx, sel, key);
1317
1318 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1319 key->mono.u.vs_export_prim_id = 1;
1320 }
1321 break;
1322 case PIPE_SHADER_GEOMETRY:
1323 if (sctx->b.chip_class >= GFX9) {
1324 if (sctx->tes_shader.cso) {
1325 key->part.gs.es = sctx->tes_shader.cso;
1326 } else {
1327 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1328 key, &key->part.gs.vs_prolog);
1329 key->part.gs.es = sctx->vs_shader.cso;
1330 }
1331
1332 /* Merged ES-GS can have unbalanced wave usage.
1333 *
1334 * ES threads are per-vertex, while GS threads are
1335 * per-primitive. So without any amplification, there
1336 * are fewer GS threads than ES threads, which can result
1337 * in empty (no-op) GS waves. With too much amplification,
1338 * there are more GS threads than ES threads, which
1339 * can result in empty (no-op) ES waves.
1340 *
1341 * Non-monolithic shaders are implemented by setting EXEC
1342 * at the beginning of shader parts, and don't jump to
1343 * the end if EXEC is 0.
1344 *
1345 * Monolithic shaders use conditional blocks, so they can
1346 * jump and skip empty waves of ES or GS. So set this to
1347 * always use optimized variants, which are monolithic.
1348 */
1349 key->opt.prefer_mono = 1;
1350 }
1351 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1352 break;
1353 case PIPE_SHADER_FRAGMENT: {
1354 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1355 struct si_state_blend *blend = sctx->queued.named.blend;
1356
1357 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1358 sel->info.colors_written == 0x1)
1359 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1360
1361 if (blend) {
1362 /* Select the shader color format based on whether
1363 * blending or alpha are needed.
1364 */
1365 key->part.ps.epilog.spi_shader_col_format =
1366 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1367 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1368 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1369 sctx->framebuffer.spi_shader_col_format_blend) |
1370 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1371 sctx->framebuffer.spi_shader_col_format_alpha) |
1372 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1373 sctx->framebuffer.spi_shader_col_format);
1374 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1375
1376 /* The output for dual source blending should have
1377 * the same format as the first output.
1378 */
1379 if (blend->dual_src_blend)
1380 key->part.ps.epilog.spi_shader_col_format |=
1381 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1382 } else
1383 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1384
1385 /* If alpha-to-coverage is enabled, we have to export alpha
1386 * even if there is no color buffer.
1387 */
1388 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1389 blend && blend->alpha_to_coverage)
1390 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1391
1392 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1393 * to the range supported by the type if a channel has less
1394 * than 16 bits and the export format is 16_ABGR.
1395 */
1396 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII) {
1397 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1398 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1399 }
1400
1401 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1402 if (!key->part.ps.epilog.last_cbuf) {
1403 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1404 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1405 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1406 }
1407
1408 if (rs) {
1409 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
1410 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
1411 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
1412 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
1413
1414 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1415 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1416
1417 if (sctx->queued.named.blend) {
1418 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1419 rs->multisample_enable;
1420 }
1421
1422 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1423 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1424 (is_line && rs->line_smooth)) &&
1425 sctx->framebuffer.nr_samples <= 1;
1426 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1427
1428 if (rs->force_persample_interp &&
1429 rs->multisample_enable &&
1430 sctx->framebuffer.nr_samples > 1 &&
1431 sctx->ps_iter_samples > 1) {
1432 key->part.ps.prolog.force_persp_sample_interp =
1433 sel->info.uses_persp_center ||
1434 sel->info.uses_persp_centroid;
1435
1436 key->part.ps.prolog.force_linear_sample_interp =
1437 sel->info.uses_linear_center ||
1438 sel->info.uses_linear_centroid;
1439 } else if (rs->multisample_enable &&
1440 sctx->framebuffer.nr_samples > 1) {
1441 key->part.ps.prolog.bc_optimize_for_persp =
1442 sel->info.uses_persp_center &&
1443 sel->info.uses_persp_centroid;
1444 key->part.ps.prolog.bc_optimize_for_linear =
1445 sel->info.uses_linear_center &&
1446 sel->info.uses_linear_centroid;
1447 } else {
1448 /* Make sure SPI doesn't compute more than 1 pair
1449 * of (i,j), which is the optimization here. */
1450 key->part.ps.prolog.force_persp_center_interp =
1451 sel->info.uses_persp_center +
1452 sel->info.uses_persp_centroid +
1453 sel->info.uses_persp_sample > 1;
1454
1455 key->part.ps.prolog.force_linear_center_interp =
1456 sel->info.uses_linear_center +
1457 sel->info.uses_linear_centroid +
1458 sel->info.uses_linear_sample > 1;
1459 }
1460 }
1461
1462 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1463 break;
1464 }
1465 default:
1466 assert(0);
1467 }
1468
1469 if (unlikely(sctx->screen->b.debug_flags & DBG_NO_OPT_VARIANT))
1470 memset(&key->opt, 0, sizeof(key->opt));
1471 }
1472
1473 static void si_build_shader_variant(struct si_shader *shader,
1474 int thread_index,
1475 bool low_priority)
1476 {
1477 struct si_shader_selector *sel = shader->selector;
1478 struct si_screen *sscreen = sel->screen;
1479 LLVMTargetMachineRef tm;
1480 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1481 int r;
1482
1483 if (thread_index >= 0) {
1484 if (low_priority) {
1485 assert(thread_index < ARRAY_SIZE(sscreen->tm_low_priority));
1486 tm = sscreen->tm_low_priority[thread_index];
1487 } else {
1488 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1489 tm = sscreen->tm[thread_index];
1490 }
1491 if (!debug->async)
1492 debug = NULL;
1493 } else {
1494 assert(!low_priority);
1495 tm = shader->compiler_ctx_state.tm;
1496 }
1497
1498 r = si_shader_create(sscreen, tm, shader, debug);
1499 if (unlikely(r)) {
1500 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1501 sel->type, r);
1502 shader->compilation_failed = true;
1503 return;
1504 }
1505
1506 if (shader->compiler_ctx_state.is_debug_context) {
1507 FILE *f = open_memstream(&shader->shader_log,
1508 &shader->shader_log_size);
1509 if (f) {
1510 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1511 fclose(f);
1512 }
1513 }
1514
1515 si_shader_init_pm4_state(sscreen, shader);
1516 }
1517
1518 static void si_build_shader_variant_low_priority(void *job, int thread_index)
1519 {
1520 struct si_shader *shader = (struct si_shader *)job;
1521
1522 assert(thread_index >= 0);
1523
1524 si_build_shader_variant(shader, thread_index, true);
1525 }
1526
1527 static const struct si_shader_key zeroed;
1528
1529 static bool si_check_missing_main_part(struct si_screen *sscreen,
1530 struct si_shader_selector *sel,
1531 struct si_compiler_ctx_state *compiler_state,
1532 struct si_shader_key *key)
1533 {
1534 struct si_shader **mainp = si_get_main_shader_part(sel, key);
1535
1536 if (!*mainp) {
1537 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1538
1539 if (!main_part)
1540 return false;
1541
1542 main_part->selector = sel;
1543 main_part->key.as_es = key->as_es;
1544 main_part->key.as_ls = key->as_ls;
1545
1546 if (si_compile_tgsi_shader(sscreen, compiler_state->tm,
1547 main_part, false,
1548 &compiler_state->debug) != 0) {
1549 FREE(main_part);
1550 return false;
1551 }
1552 *mainp = main_part;
1553 }
1554 return true;
1555 }
1556
1557 /* Select the hw shader variant depending on the current state. */
1558 static int si_shader_select_with_key(struct si_screen *sscreen,
1559 struct si_shader_ctx_state *state,
1560 struct si_compiler_ctx_state *compiler_state,
1561 struct si_shader_key *key,
1562 int thread_index)
1563 {
1564 struct si_shader_selector *sel = state->cso;
1565 struct si_shader_selector *previous_stage_sel = NULL;
1566 struct si_shader *current = state->current;
1567 struct si_shader *iter, *shader = NULL;
1568
1569 again:
1570 /* Check if we don't need to change anything.
1571 * This path is also used for most shaders that don't need multiple
1572 * variants, it will cost just a computation of the key and this
1573 * test. */
1574 if (likely(current &&
1575 memcmp(&current->key, key, sizeof(*key)) == 0 &&
1576 (!current->is_optimized ||
1577 util_queue_fence_is_signalled(&current->optimized_ready))))
1578 return current->compilation_failed ? -1 : 0;
1579
1580 /* This must be done before the mutex is locked, because async GS
1581 * compilation calls this function too, and therefore must enter
1582 * the mutex first.
1583 *
1584 * Only wait if we are in a draw call. Don't wait if we are
1585 * in a compiler thread.
1586 */
1587 if (thread_index < 0)
1588 util_queue_fence_wait(&sel->ready);
1589
1590 mtx_lock(&sel->mutex);
1591
1592 /* Find the shader variant. */
1593 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1594 /* Don't check the "current" shader. We checked it above. */
1595 if (current != iter &&
1596 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1597 /* If it's an optimized shader and its compilation has
1598 * been started but isn't done, use the unoptimized
1599 * shader so as not to cause a stall due to compilation.
1600 */
1601 if (iter->is_optimized &&
1602 !util_queue_fence_is_signalled(&iter->optimized_ready)) {
1603 memset(&key->opt, 0, sizeof(key->opt));
1604 mtx_unlock(&sel->mutex);
1605 goto again;
1606 }
1607
1608 if (iter->compilation_failed) {
1609 mtx_unlock(&sel->mutex);
1610 return -1; /* skip the draw call */
1611 }
1612
1613 state->current = iter;
1614 mtx_unlock(&sel->mutex);
1615 return 0;
1616 }
1617 }
1618
1619 /* Build a new shader. */
1620 shader = CALLOC_STRUCT(si_shader);
1621 if (!shader) {
1622 mtx_unlock(&sel->mutex);
1623 return -ENOMEM;
1624 }
1625 shader->selector = sel;
1626 shader->key = *key;
1627 shader->compiler_ctx_state = *compiler_state;
1628
1629 /* If this is a merged shader, get the first shader's selector. */
1630 if (sscreen->b.chip_class >= GFX9) {
1631 if (sel->type == PIPE_SHADER_TESS_CTRL)
1632 previous_stage_sel = key->part.tcs.ls;
1633 else if (sel->type == PIPE_SHADER_GEOMETRY)
1634 previous_stage_sel = key->part.gs.es;
1635
1636 /* We need to wait for the previous shader. */
1637 if (previous_stage_sel && thread_index < 0)
1638 util_queue_fence_wait(&previous_stage_sel->ready);
1639 }
1640
1641 /* Compile the main shader part if it doesn't exist. This can happen
1642 * if the initial guess was wrong. */
1643 bool is_pure_monolithic =
1644 sscreen->use_monolithic_shaders ||
1645 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1646
1647 if (!is_pure_monolithic) {
1648 bool ok;
1649
1650 /* Make sure the main shader part is present. This is needed
1651 * for shaders that can be compiled as VS, LS, or ES, and only
1652 * one of them is compiled at creation.
1653 *
1654 * For merged shaders, check that the starting shader's main
1655 * part is present.
1656 */
1657 if (previous_stage_sel) {
1658 struct si_shader_key shader1_key = zeroed;
1659
1660 if (sel->type == PIPE_SHADER_TESS_CTRL)
1661 shader1_key.as_ls = 1;
1662 else if (sel->type == PIPE_SHADER_GEOMETRY)
1663 shader1_key.as_es = 1;
1664 else
1665 assert(0);
1666
1667 mtx_lock(&previous_stage_sel->mutex);
1668 ok = si_check_missing_main_part(sscreen,
1669 previous_stage_sel,
1670 compiler_state, &shader1_key);
1671 mtx_unlock(&previous_stage_sel->mutex);
1672 } else {
1673 ok = si_check_missing_main_part(sscreen, sel,
1674 compiler_state, key);
1675 }
1676 if (!ok) {
1677 FREE(shader);
1678 mtx_unlock(&sel->mutex);
1679 return -ENOMEM; /* skip the draw call */
1680 }
1681 }
1682
1683 /* Keep the reference to the 1st shader of merged shaders, so that
1684 * Gallium can't destroy it before we destroy the 2nd shader.
1685 *
1686 * Set sctx = NULL, because it's unused if we're not releasing
1687 * the shader, and we don't have any sctx here.
1688 */
1689 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
1690 previous_stage_sel);
1691
1692 /* Monolithic-only shaders don't make a distinction between optimized
1693 * and unoptimized. */
1694 shader->is_monolithic =
1695 is_pure_monolithic ||
1696 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1697
1698 shader->is_optimized =
1699 !is_pure_monolithic &&
1700 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1701 if (shader->is_optimized)
1702 util_queue_fence_init(&shader->optimized_ready);
1703
1704 if (!sel->last_variant) {
1705 sel->first_variant = shader;
1706 sel->last_variant = shader;
1707 } else {
1708 sel->last_variant->next_variant = shader;
1709 sel->last_variant = shader;
1710 }
1711
1712 /* If it's an optimized shader, compile it asynchronously. */
1713 if (shader->is_optimized &&
1714 !is_pure_monolithic &&
1715 thread_index < 0) {
1716 /* Compile it asynchronously. */
1717 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
1718 shader, &shader->optimized_ready,
1719 si_build_shader_variant_low_priority, NULL);
1720
1721 /* Use the default (unoptimized) shader for now. */
1722 memset(&key->opt, 0, sizeof(key->opt));
1723 mtx_unlock(&sel->mutex);
1724 goto again;
1725 }
1726
1727 assert(!shader->is_optimized);
1728 si_build_shader_variant(shader, thread_index, false);
1729
1730 if (!shader->compilation_failed)
1731 state->current = shader;
1732
1733 mtx_unlock(&sel->mutex);
1734 return shader->compilation_failed ? -1 : 0;
1735 }
1736
1737 static int si_shader_select(struct pipe_context *ctx,
1738 struct si_shader_ctx_state *state,
1739 struct si_compiler_ctx_state *compiler_state)
1740 {
1741 struct si_context *sctx = (struct si_context *)ctx;
1742 struct si_shader_key key;
1743
1744 si_shader_selector_key(ctx, state->cso, &key);
1745 return si_shader_select_with_key(sctx->screen, state, compiler_state,
1746 &key, -1);
1747 }
1748
1749 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1750 bool streamout,
1751 struct si_shader_key *key)
1752 {
1753 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1754
1755 switch (info->processor) {
1756 case PIPE_SHADER_VERTEX:
1757 switch (next_shader) {
1758 case PIPE_SHADER_GEOMETRY:
1759 key->as_es = 1;
1760 break;
1761 case PIPE_SHADER_TESS_CTRL:
1762 case PIPE_SHADER_TESS_EVAL:
1763 key->as_ls = 1;
1764 break;
1765 default:
1766 /* If POSITION isn't written, it can only be a HW VS
1767 * if streamout is used. If streamout isn't used,
1768 * assume that it's a HW LS. (the next shader is TCS)
1769 * This heuristic is needed for separate shader objects.
1770 */
1771 if (!info->writes_position && !streamout)
1772 key->as_ls = 1;
1773 }
1774 break;
1775
1776 case PIPE_SHADER_TESS_EVAL:
1777 if (next_shader == PIPE_SHADER_GEOMETRY ||
1778 !info->writes_position)
1779 key->as_es = 1;
1780 break;
1781 }
1782 }
1783
1784 /**
1785 * Compile the main shader part or the monolithic shader as part of
1786 * si_shader_selector initialization. Since it can be done asynchronously,
1787 * there is no way to report compile failures to applications.
1788 */
1789 static void si_init_shader_selector_async(void *job, int thread_index)
1790 {
1791 struct si_shader_selector *sel = (struct si_shader_selector *)job;
1792 struct si_screen *sscreen = sel->screen;
1793 LLVMTargetMachineRef tm;
1794 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
1795 unsigned i;
1796
1797 if (thread_index >= 0) {
1798 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1799 tm = sscreen->tm[thread_index];
1800 if (!debug->async)
1801 debug = NULL;
1802 } else {
1803 tm = sel->compiler_ctx_state.tm;
1804 }
1805
1806 /* Compile the main shader part for use with a prolog and/or epilog.
1807 * If this fails, the driver will try to compile a monolithic shader
1808 * on demand.
1809 */
1810 if (!sscreen->use_monolithic_shaders) {
1811 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1812 void *tgsi_binary = NULL;
1813
1814 if (!shader) {
1815 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
1816 return;
1817 }
1818
1819 shader->selector = sel;
1820 si_parse_next_shader_property(&sel->info,
1821 sel->so.num_outputs != 0,
1822 &shader->key);
1823
1824 if (sel->tokens)
1825 tgsi_binary = si_get_tgsi_binary(sel);
1826
1827 /* Try to load the shader from the shader cache. */
1828 mtx_lock(&sscreen->shader_cache_mutex);
1829
1830 if (tgsi_binary &&
1831 si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
1832 mtx_unlock(&sscreen->shader_cache_mutex);
1833 } else {
1834 mtx_unlock(&sscreen->shader_cache_mutex);
1835
1836 /* Compile the shader if it hasn't been loaded from the cache. */
1837 if (si_compile_tgsi_shader(sscreen, tm, shader, false,
1838 debug) != 0) {
1839 FREE(shader);
1840 FREE(tgsi_binary);
1841 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
1842 return;
1843 }
1844
1845 if (tgsi_binary) {
1846 mtx_lock(&sscreen->shader_cache_mutex);
1847 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary, shader, true))
1848 FREE(tgsi_binary);
1849 mtx_unlock(&sscreen->shader_cache_mutex);
1850 }
1851 }
1852
1853 *si_get_main_shader_part(sel, &shader->key) = shader;
1854
1855 /* Unset "outputs_written" flags for outputs converted to
1856 * DEFAULT_VAL, so that later inter-shader optimizations don't
1857 * try to eliminate outputs that don't exist in the final
1858 * shader.
1859 *
1860 * This is only done if non-monolithic shaders are enabled.
1861 */
1862 if ((sel->type == PIPE_SHADER_VERTEX ||
1863 sel->type == PIPE_SHADER_TESS_EVAL) &&
1864 !shader->key.as_ls &&
1865 !shader->key.as_es) {
1866 unsigned i;
1867
1868 for (i = 0; i < sel->info.num_outputs; i++) {
1869 unsigned offset = shader->info.vs_output_param_offset[i];
1870
1871 if (offset <= AC_EXP_PARAM_OFFSET_31)
1872 continue;
1873
1874 unsigned name = sel->info.output_semantic_name[i];
1875 unsigned index = sel->info.output_semantic_index[i];
1876 unsigned id;
1877
1878 switch (name) {
1879 case TGSI_SEMANTIC_GENERIC:
1880 /* don't process indices the function can't handle */
1881 if (index >= SI_MAX_IO_GENERIC)
1882 break;
1883 /* fall through */
1884 default:
1885 id = si_shader_io_get_unique_index(name, index);
1886 sel->outputs_written &= ~(1ull << id);
1887 break;
1888 case TGSI_SEMANTIC_POSITION: /* ignore these */
1889 case TGSI_SEMANTIC_PSIZE:
1890 case TGSI_SEMANTIC_CLIPVERTEX:
1891 case TGSI_SEMANTIC_EDGEFLAG:
1892 break;
1893 }
1894 }
1895 }
1896 }
1897
1898 /* Pre-compilation. */
1899 if (sscreen->b.debug_flags & DBG_PRECOMPILE &&
1900 /* GFX9 needs LS or ES for compilation, which we don't have here. */
1901 (sscreen->b.chip_class <= VI ||
1902 (sel->type != PIPE_SHADER_TESS_CTRL &&
1903 sel->type != PIPE_SHADER_GEOMETRY))) {
1904 struct si_shader_ctx_state state = {sel};
1905 struct si_shader_key key;
1906
1907 memset(&key, 0, sizeof(key));
1908 si_parse_next_shader_property(&sel->info,
1909 sel->so.num_outputs != 0,
1910 &key);
1911
1912 /* GFX9 doesn't have LS and ES. */
1913 if (sscreen->b.chip_class >= GFX9) {
1914 key.as_ls = 0;
1915 key.as_es = 0;
1916 }
1917
1918 /* Set reasonable defaults, so that the shader key doesn't
1919 * cause any code to be eliminated.
1920 */
1921 switch (sel->type) {
1922 case PIPE_SHADER_TESS_CTRL:
1923 key.part.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
1924 break;
1925 case PIPE_SHADER_FRAGMENT:
1926 key.part.ps.prolog.bc_optimize_for_persp =
1927 sel->info.uses_persp_center &&
1928 sel->info.uses_persp_centroid;
1929 key.part.ps.prolog.bc_optimize_for_linear =
1930 sel->info.uses_linear_center &&
1931 sel->info.uses_linear_centroid;
1932 key.part.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
1933 for (i = 0; i < 8; i++)
1934 if (sel->info.colors_written & (1 << i))
1935 key.part.ps.epilog.spi_shader_col_format |=
1936 V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
1937 break;
1938 }
1939
1940 if (si_shader_select_with_key(sscreen, &state,
1941 &sel->compiler_ctx_state, &key,
1942 thread_index))
1943 fprintf(stderr, "radeonsi: can't create a monolithic shader\n");
1944 }
1945
1946 /* The GS copy shader is always pre-compiled. */
1947 if (sel->type == PIPE_SHADER_GEOMETRY) {
1948 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, tm, sel, debug);
1949 if (!sel->gs_copy_shader) {
1950 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
1951 return;
1952 }
1953
1954 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
1955 }
1956 }
1957
1958 /* Return descriptor slot usage masks from the given shader info. */
1959 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
1960 uint32_t *const_and_shader_buffers,
1961 uint64_t *samplers_and_images)
1962 {
1963 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
1964
1965 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
1966 num_constbufs = util_last_bit(info->const_buffers_declared);
1967 /* two 8-byte images share one 16-byte slot */
1968 num_images = align(util_last_bit(info->images_declared), 2);
1969 num_samplers = util_last_bit(info->samplers_declared);
1970
1971 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
1972 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
1973 *const_and_shader_buffers =
1974 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
1975
1976 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
1977 start = si_get_image_slot(num_images - 1) / 2;
1978 *samplers_and_images =
1979 u_bit_consecutive64(start, num_images / 2 + num_samplers);
1980 }
1981
1982 static void *si_create_shader_selector(struct pipe_context *ctx,
1983 const struct pipe_shader_state *state)
1984 {
1985 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
1986 struct si_context *sctx = (struct si_context*)ctx;
1987 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
1988 int i;
1989
1990 if (!sel)
1991 return NULL;
1992
1993 pipe_reference_init(&sel->reference, 1);
1994 sel->screen = sscreen;
1995 sel->compiler_ctx_state.tm = sctx->tm;
1996 sel->compiler_ctx_state.debug = sctx->b.debug;
1997 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
1998
1999 sel->so = state->stream_output;
2000
2001 if (state->type == PIPE_SHADER_IR_TGSI) {
2002 sel->tokens = tgsi_dup_tokens(state->tokens);
2003 if (!sel->tokens) {
2004 FREE(sel);
2005 return NULL;
2006 }
2007
2008 tgsi_scan_shader(state->tokens, &sel->info);
2009 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2010 } else {
2011 assert(state->type == PIPE_SHADER_IR_NIR);
2012
2013 sel->nir = state->ir.nir;
2014
2015 si_nir_scan_shader(sel->nir, &sel->info);
2016
2017 si_lower_nir(sel);
2018 }
2019
2020 sel->type = sel->info.processor;
2021 p_atomic_inc(&sscreen->b.num_shaders_created);
2022 si_get_active_slot_masks(&sel->info,
2023 &sel->active_const_and_shader_buffers,
2024 &sel->active_samplers_and_images);
2025
2026 /* Record which streamout buffers are enabled. */
2027 for (i = 0; i < sel->so.num_outputs; i++) {
2028 sel->enabled_streamout_buffer_mask |=
2029 (1 << sel->so.output[i].output_buffer) <<
2030 (sel->so.output[i].stream * 4);
2031 }
2032
2033 /* The prolog is a no-op if there are no inputs. */
2034 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2035 sel->info.num_inputs;
2036
2037 /* Set which opcode uses which (i,j) pair. */
2038 if (sel->info.uses_persp_opcode_interp_centroid)
2039 sel->info.uses_persp_centroid = true;
2040
2041 if (sel->info.uses_linear_opcode_interp_centroid)
2042 sel->info.uses_linear_centroid = true;
2043
2044 if (sel->info.uses_persp_opcode_interp_offset ||
2045 sel->info.uses_persp_opcode_interp_sample)
2046 sel->info.uses_persp_center = true;
2047
2048 if (sel->info.uses_linear_opcode_interp_offset ||
2049 sel->info.uses_linear_opcode_interp_sample)
2050 sel->info.uses_linear_center = true;
2051
2052 switch (sel->type) {
2053 case PIPE_SHADER_GEOMETRY:
2054 sel->gs_output_prim =
2055 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2056 sel->gs_max_out_vertices =
2057 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2058 sel->gs_num_invocations =
2059 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2060 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2061 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2062 sel->gs_max_out_vertices;
2063
2064 sel->max_gs_stream = 0;
2065 for (i = 0; i < sel->so.num_outputs; i++)
2066 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2067 sel->so.output[i].stream);
2068
2069 sel->gs_input_verts_per_prim =
2070 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2071 break;
2072
2073 case PIPE_SHADER_TESS_CTRL:
2074 /* Always reserve space for these. */
2075 sel->patch_outputs_written |=
2076 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2077 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2078 /* fall through */
2079 case PIPE_SHADER_VERTEX:
2080 case PIPE_SHADER_TESS_EVAL:
2081 for (i = 0; i < sel->info.num_outputs; i++) {
2082 unsigned name = sel->info.output_semantic_name[i];
2083 unsigned index = sel->info.output_semantic_index[i];
2084
2085 switch (name) {
2086 case TGSI_SEMANTIC_TESSINNER:
2087 case TGSI_SEMANTIC_TESSOUTER:
2088 case TGSI_SEMANTIC_PATCH:
2089 sel->patch_outputs_written |=
2090 1ull << si_shader_io_get_unique_index_patch(name, index);
2091 break;
2092
2093 case TGSI_SEMANTIC_GENERIC:
2094 /* don't process indices the function can't handle */
2095 if (index >= SI_MAX_IO_GENERIC)
2096 break;
2097 /* fall through */
2098 default:
2099 sel->outputs_written |=
2100 1ull << si_shader_io_get_unique_index(name, index);
2101 break;
2102 case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */
2103 case TGSI_SEMANTIC_EDGEFLAG:
2104 break;
2105 }
2106 }
2107 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2108
2109 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2110 * conflicts, i.e. each vertex will start at a different bank.
2111 */
2112 if (sctx->b.chip_class >= GFX9)
2113 sel->esgs_itemsize += 4;
2114 break;
2115
2116 case PIPE_SHADER_FRAGMENT:
2117 for (i = 0; i < sel->info.num_inputs; i++) {
2118 unsigned name = sel->info.input_semantic_name[i];
2119 unsigned index = sel->info.input_semantic_index[i];
2120
2121 switch (name) {
2122 case TGSI_SEMANTIC_GENERIC:
2123 /* don't process indices the function can't handle */
2124 if (index >= SI_MAX_IO_GENERIC)
2125 break;
2126 /* fall through */
2127 default:
2128 sel->inputs_read |=
2129 1ull << si_shader_io_get_unique_index(name, index);
2130 break;
2131 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2132 break;
2133 }
2134 }
2135
2136 for (i = 0; i < 8; i++)
2137 if (sel->info.colors_written & (1 << i))
2138 sel->colors_written_4bit |= 0xf << (4 * i);
2139
2140 for (i = 0; i < sel->info.num_inputs; i++) {
2141 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2142 int index = sel->info.input_semantic_index[i];
2143 sel->color_attr_index[index] = i;
2144 }
2145 }
2146 break;
2147 }
2148
2149 /* PA_CL_VS_OUT_CNTL */
2150 bool misc_vec_ena =
2151 sel->info.writes_psize || sel->info.writes_edgeflag ||
2152 sel->info.writes_layer || sel->info.writes_viewport_index;
2153 sel->pa_cl_vs_out_cntl =
2154 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2155 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2156 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2157 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2158 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2159 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2160 sel->clipdist_mask = sel->info.writes_clipvertex ?
2161 SIX_BITS : sel->info.clipdist_writemask;
2162 sel->culldist_mask = sel->info.culldist_writemask <<
2163 sel->info.num_written_clipdistance;
2164
2165 /* DB_SHADER_CONTROL */
2166 sel->db_shader_control =
2167 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2168 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2169 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2170 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2171
2172 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2173 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2174 sel->db_shader_control |=
2175 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2176 break;
2177 case TGSI_FS_DEPTH_LAYOUT_LESS:
2178 sel->db_shader_control |=
2179 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2180 break;
2181 }
2182
2183 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2184 *
2185 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2186 * --|-----------|------------|------------|--------------------|-------------------|-------------
2187 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2188 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2189 * 2 | false | true | n/a | LateZ | 1 | 0
2190 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2191 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2192 *
2193 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2194 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2195 *
2196 * Don't use ReZ without profiling !!!
2197 *
2198 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2199 * shaders.
2200 */
2201 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2202 /* Cases 3, 4. */
2203 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2204 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2205 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2206 } else if (sel->info.writes_memory) {
2207 /* Case 2. */
2208 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2209 S_02880C_EXEC_ON_HIER_FAIL(1);
2210 } else {
2211 /* Case 1. */
2212 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2213 }
2214
2215 (void) mtx_init(&sel->mutex, mtx_plain);
2216 util_queue_fence_init(&sel->ready);
2217
2218 if ((sctx->b.debug.debug_message && !sctx->b.debug.async) ||
2219 sctx->is_debug ||
2220 r600_can_dump_shader(&sscreen->b, sel->info.processor))
2221 si_init_shader_selector_async(sel, -1);
2222 else
2223 util_queue_add_job(&sscreen->shader_compiler_queue, sel,
2224 &sel->ready, si_init_shader_selector_async,
2225 NULL);
2226
2227 return sel;
2228 }
2229
2230 static void si_update_streamout_state(struct si_context *sctx)
2231 {
2232 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2233
2234 if (!shader_with_so)
2235 return;
2236
2237 sctx->b.streamout.enabled_stream_buffers_mask =
2238 shader_with_so->enabled_streamout_buffer_mask;
2239 sctx->b.streamout.stride_in_dw = shader_with_so->so.stride;
2240 }
2241
2242 static void si_update_clip_regs(struct si_context *sctx,
2243 struct si_shader_selector *old_hw_vs,
2244 struct si_shader *old_hw_vs_variant,
2245 struct si_shader_selector *next_hw_vs,
2246 struct si_shader *next_hw_vs_variant)
2247 {
2248 if (next_hw_vs &&
2249 (!old_hw_vs ||
2250 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2251 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2252 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2253 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2254 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2255 !old_hw_vs_variant ||
2256 !next_hw_vs_variant ||
2257 old_hw_vs_variant->key.opt.clip_disable !=
2258 next_hw_vs_variant->key.opt.clip_disable))
2259 si_mark_atom_dirty(sctx, &sctx->clip_regs);
2260 }
2261
2262 static void si_update_common_shader_state(struct si_context *sctx)
2263 {
2264 sctx->uses_bindless_samplers =
2265 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2266 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2267 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2268 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2269 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2270 sctx->uses_bindless_images =
2271 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2272 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2273 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2274 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2275 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2276 sctx->do_update_shaders = true;
2277 }
2278
2279 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2280 {
2281 struct si_context *sctx = (struct si_context *)ctx;
2282 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2283 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2284 struct si_shader_selector *sel = state;
2285
2286 if (sctx->vs_shader.cso == sel)
2287 return;
2288
2289 sctx->vs_shader.cso = sel;
2290 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2291
2292 si_update_common_shader_state(sctx);
2293 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
2294 si_set_active_descriptors_for_shader(sctx, sel);
2295 si_update_streamout_state(sctx);
2296 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2297 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2298 }
2299
2300 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2301 {
2302 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2303 (sctx->tes_shader.cso &&
2304 sctx->tes_shader.cso->info.uses_primid) ||
2305 (sctx->tcs_shader.cso &&
2306 sctx->tcs_shader.cso->info.uses_primid) ||
2307 (sctx->gs_shader.cso &&
2308 sctx->gs_shader.cso->info.uses_primid) ||
2309 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2310 sctx->ps_shader.cso->info.uses_primid);
2311 }
2312
2313 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2314 {
2315 struct si_context *sctx = (struct si_context *)ctx;
2316 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2317 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2318 struct si_shader_selector *sel = state;
2319 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2320
2321 if (sctx->gs_shader.cso == sel)
2322 return;
2323
2324 sctx->gs_shader.cso = sel;
2325 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2326 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2327
2328 si_update_common_shader_state(sctx);
2329 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2330
2331 if (enable_changed) {
2332 si_shader_change_notify(sctx);
2333 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2334 si_update_tess_uses_prim_id(sctx);
2335 }
2336 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
2337 si_set_active_descriptors_for_shader(sctx, sel);
2338 si_update_streamout_state(sctx);
2339 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2340 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2341 }
2342
2343 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2344 {
2345 struct si_context *sctx = (struct si_context *)ctx;
2346 struct si_shader_selector *sel = state;
2347 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2348
2349 if (sctx->tcs_shader.cso == sel)
2350 return;
2351
2352 sctx->tcs_shader.cso = sel;
2353 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
2354 si_update_tess_uses_prim_id(sctx);
2355
2356 si_update_common_shader_state(sctx);
2357
2358 if (enable_changed)
2359 sctx->last_tcs = NULL; /* invalidate derived tess state */
2360
2361 si_set_active_descriptors_for_shader(sctx, sel);
2362 }
2363
2364 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
2365 {
2366 struct si_context *sctx = (struct si_context *)ctx;
2367 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2368 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2369 struct si_shader_selector *sel = state;
2370 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
2371
2372 if (sctx->tes_shader.cso == sel)
2373 return;
2374
2375 sctx->tes_shader.cso = sel;
2376 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
2377 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
2378 si_update_tess_uses_prim_id(sctx);
2379
2380 si_update_common_shader_state(sctx);
2381 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2382
2383 if (enable_changed) {
2384 si_shader_change_notify(sctx);
2385 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
2386 }
2387 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
2388 si_set_active_descriptors_for_shader(sctx, sel);
2389 si_update_streamout_state(sctx);
2390 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2391 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2392 }
2393
2394 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2395 {
2396 struct si_context *sctx = (struct si_context *)ctx;
2397 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
2398 struct si_shader_selector *sel = state;
2399
2400 /* skip if supplied shader is one already in use */
2401 if (old_sel == sel)
2402 return;
2403
2404 sctx->ps_shader.cso = sel;
2405 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
2406
2407 si_update_common_shader_state(sctx);
2408 if (sel) {
2409 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2410 si_update_tess_uses_prim_id(sctx);
2411
2412 if (!old_sel ||
2413 old_sel->info.colors_written != sel->info.colors_written)
2414 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2415 }
2416 si_set_active_descriptors_for_shader(sctx, sel);
2417 }
2418
2419 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
2420 {
2421 if (shader->is_optimized) {
2422 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
2423 &shader->optimized_ready);
2424 util_queue_fence_destroy(&shader->optimized_ready);
2425 }
2426
2427 if (shader->pm4) {
2428 switch (shader->selector->type) {
2429 case PIPE_SHADER_VERTEX:
2430 if (shader->key.as_ls) {
2431 assert(sctx->b.chip_class <= VI);
2432 si_pm4_delete_state(sctx, ls, shader->pm4);
2433 } else if (shader->key.as_es) {
2434 assert(sctx->b.chip_class <= VI);
2435 si_pm4_delete_state(sctx, es, shader->pm4);
2436 } else {
2437 si_pm4_delete_state(sctx, vs, shader->pm4);
2438 }
2439 break;
2440 case PIPE_SHADER_TESS_CTRL:
2441 si_pm4_delete_state(sctx, hs, shader->pm4);
2442 break;
2443 case PIPE_SHADER_TESS_EVAL:
2444 if (shader->key.as_es) {
2445 assert(sctx->b.chip_class <= VI);
2446 si_pm4_delete_state(sctx, es, shader->pm4);
2447 } else {
2448 si_pm4_delete_state(sctx, vs, shader->pm4);
2449 }
2450 break;
2451 case PIPE_SHADER_GEOMETRY:
2452 if (shader->is_gs_copy_shader)
2453 si_pm4_delete_state(sctx, vs, shader->pm4);
2454 else
2455 si_pm4_delete_state(sctx, gs, shader->pm4);
2456 break;
2457 case PIPE_SHADER_FRAGMENT:
2458 si_pm4_delete_state(sctx, ps, shader->pm4);
2459 break;
2460 }
2461 }
2462
2463 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
2464 si_shader_destroy(shader);
2465 free(shader);
2466 }
2467
2468 void si_destroy_shader_selector(struct si_context *sctx,
2469 struct si_shader_selector *sel)
2470 {
2471 struct si_shader *p = sel->first_variant, *c;
2472 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
2473 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
2474 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
2475 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
2476 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
2477 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
2478 };
2479
2480 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
2481
2482 if (current_shader[sel->type]->cso == sel) {
2483 current_shader[sel->type]->cso = NULL;
2484 current_shader[sel->type]->current = NULL;
2485 }
2486
2487 while (p) {
2488 c = p->next_variant;
2489 si_delete_shader(sctx, p);
2490 p = c;
2491 }
2492
2493 if (sel->main_shader_part)
2494 si_delete_shader(sctx, sel->main_shader_part);
2495 if (sel->main_shader_part_ls)
2496 si_delete_shader(sctx, sel->main_shader_part_ls);
2497 if (sel->main_shader_part_es)
2498 si_delete_shader(sctx, sel->main_shader_part_es);
2499 if (sel->gs_copy_shader)
2500 si_delete_shader(sctx, sel->gs_copy_shader);
2501
2502 util_queue_fence_destroy(&sel->ready);
2503 mtx_destroy(&sel->mutex);
2504 free(sel->tokens);
2505 ralloc_free(sel->nir);
2506 free(sel);
2507 }
2508
2509 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
2510 {
2511 struct si_context *sctx = (struct si_context *)ctx;
2512 struct si_shader_selector *sel = (struct si_shader_selector *)state;
2513
2514 si_shader_selector_reference(sctx, &sel, NULL);
2515 }
2516
2517 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
2518 struct si_shader *vs, unsigned name,
2519 unsigned index, unsigned interpolate)
2520 {
2521 struct tgsi_shader_info *vsinfo = &vs->selector->info;
2522 unsigned j, offset, ps_input_cntl = 0;
2523
2524 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
2525 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
2526 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2527
2528 if (name == TGSI_SEMANTIC_PCOORD ||
2529 (name == TGSI_SEMANTIC_TEXCOORD &&
2530 sctx->sprite_coord_enable & (1 << index))) {
2531 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
2532 }
2533
2534 for (j = 0; j < vsinfo->num_outputs; j++) {
2535 if (name == vsinfo->output_semantic_name[j] &&
2536 index == vsinfo->output_semantic_index[j]) {
2537 offset = vs->info.vs_output_param_offset[j];
2538
2539 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2540 /* The input is loaded from parameter memory. */
2541 ps_input_cntl |= S_028644_OFFSET(offset);
2542 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2543 if (offset == AC_EXP_PARAM_UNDEFINED) {
2544 /* This can happen with depth-only rendering. */
2545 offset = 0;
2546 } else {
2547 /* The input is a DEFAULT_VAL constant. */
2548 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2549 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2550 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2551 }
2552
2553 ps_input_cntl = S_028644_OFFSET(0x20) |
2554 S_028644_DEFAULT_VAL(offset);
2555 }
2556 break;
2557 }
2558 }
2559
2560 if (name == TGSI_SEMANTIC_PRIMID)
2561 /* PrimID is written after the last output. */
2562 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
2563 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2564 /* No corresponding output found, load defaults into input.
2565 * Don't set any other bits.
2566 * (FLAT_SHADE=1 completely changes behavior) */
2567 ps_input_cntl = S_028644_OFFSET(0x20);
2568 /* D3D 9 behaviour. GL is undefined */
2569 if (name == TGSI_SEMANTIC_COLOR && index == 0)
2570 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
2571 }
2572 return ps_input_cntl;
2573 }
2574
2575 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
2576 {
2577 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2578 struct si_shader *ps = sctx->ps_shader.current;
2579 struct si_shader *vs = si_get_vs_state(sctx);
2580 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
2581 unsigned i, num_interp, num_written = 0, bcol_interp[2];
2582
2583 if (!ps || !ps->selector->info.num_inputs)
2584 return;
2585
2586 num_interp = si_get_ps_num_interp(ps);
2587 assert(num_interp > 0);
2588 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
2589
2590 for (i = 0; i < psinfo->num_inputs; i++) {
2591 unsigned name = psinfo->input_semantic_name[i];
2592 unsigned index = psinfo->input_semantic_index[i];
2593 unsigned interpolate = psinfo->input_interpolate[i];
2594
2595 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
2596 interpolate));
2597 num_written++;
2598
2599 if (name == TGSI_SEMANTIC_COLOR) {
2600 assert(index < ARRAY_SIZE(bcol_interp));
2601 bcol_interp[index] = interpolate;
2602 }
2603 }
2604
2605 if (ps->key.part.ps.prolog.color_two_side) {
2606 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
2607
2608 for (i = 0; i < 2; i++) {
2609 if (!(psinfo->colors_read & (0xf << (i * 4))))
2610 continue;
2611
2612 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
2613 i, bcol_interp[i]));
2614 num_written++;
2615 }
2616 }
2617 assert(num_interp == num_written);
2618 }
2619
2620 /**
2621 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2622 */
2623 static void si_init_config_add_vgt_flush(struct si_context *sctx)
2624 {
2625 if (sctx->init_config_has_vgt_flush)
2626 return;
2627
2628 /* Done by Vulkan before VGT_FLUSH. */
2629 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2630 si_pm4_cmd_add(sctx->init_config,
2631 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2632 si_pm4_cmd_end(sctx->init_config, false);
2633
2634 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2635 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2636 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2637 si_pm4_cmd_end(sctx->init_config, false);
2638 sctx->init_config_has_vgt_flush = true;
2639 }
2640
2641 /* Initialize state related to ESGS / GSVS ring buffers */
2642 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2643 {
2644 struct si_shader_selector *es =
2645 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2646 struct si_shader_selector *gs = sctx->gs_shader.cso;
2647 struct si_pm4_state *pm4;
2648
2649 /* Chip constants. */
2650 unsigned num_se = sctx->screen->b.info.max_se;
2651 unsigned wave_size = 64;
2652 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2653 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2654 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2655 */
2656 unsigned gs_vertex_reuse = (sctx->b.chip_class >= VI ? 32 : 16) * num_se;
2657 unsigned alignment = 256 * num_se;
2658 /* The maximum size is 63.999 MB per SE. */
2659 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2660
2661 /* Calculate the minimum size. */
2662 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
2663 wave_size, alignment);
2664
2665 /* These are recommended sizes, not minimum sizes. */
2666 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2667 es->esgs_itemsize * gs->gs_input_verts_per_prim;
2668 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2669 gs->max_gsvs_emit_size;
2670
2671 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2672 esgs_ring_size = align(esgs_ring_size, alignment);
2673 gsvs_ring_size = align(gsvs_ring_size, alignment);
2674
2675 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2676 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2677
2678 /* Some rings don't have to be allocated if shaders don't use them.
2679 * (e.g. no varyings between ES and GS or GS and VS)
2680 *
2681 * GFX9 doesn't have the ESGS ring.
2682 */
2683 bool update_esgs = sctx->b.chip_class <= VI &&
2684 esgs_ring_size &&
2685 (!sctx->esgs_ring ||
2686 sctx->esgs_ring->width0 < esgs_ring_size);
2687 bool update_gsvs = gsvs_ring_size &&
2688 (!sctx->gsvs_ring ||
2689 sctx->gsvs_ring->width0 < gsvs_ring_size);
2690
2691 if (!update_esgs && !update_gsvs)
2692 return true;
2693
2694 if (update_esgs) {
2695 pipe_resource_reference(&sctx->esgs_ring, NULL);
2696 sctx->esgs_ring =
2697 r600_aligned_buffer_create(sctx->b.b.screen,
2698 R600_RESOURCE_FLAG_UNMAPPABLE,
2699 PIPE_USAGE_DEFAULT,
2700 esgs_ring_size, alignment);
2701 if (!sctx->esgs_ring)
2702 return false;
2703 }
2704
2705 if (update_gsvs) {
2706 pipe_resource_reference(&sctx->gsvs_ring, NULL);
2707 sctx->gsvs_ring =
2708 r600_aligned_buffer_create(sctx->b.b.screen,
2709 R600_RESOURCE_FLAG_UNMAPPABLE,
2710 PIPE_USAGE_DEFAULT,
2711 gsvs_ring_size, alignment);
2712 if (!sctx->gsvs_ring)
2713 return false;
2714 }
2715
2716 /* Create the "init_config_gs_rings" state. */
2717 pm4 = CALLOC_STRUCT(si_pm4_state);
2718 if (!pm4)
2719 return false;
2720
2721 if (sctx->b.chip_class >= CIK) {
2722 if (sctx->esgs_ring) {
2723 assert(sctx->b.chip_class <= VI);
2724 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2725 sctx->esgs_ring->width0 / 256);
2726 }
2727 if (sctx->gsvs_ring)
2728 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2729 sctx->gsvs_ring->width0 / 256);
2730 } else {
2731 if (sctx->esgs_ring)
2732 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2733 sctx->esgs_ring->width0 / 256);
2734 if (sctx->gsvs_ring)
2735 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2736 sctx->gsvs_ring->width0 / 256);
2737 }
2738
2739 /* Set the state. */
2740 if (sctx->init_config_gs_rings)
2741 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
2742 sctx->init_config_gs_rings = pm4;
2743
2744 if (!sctx->init_config_has_vgt_flush) {
2745 si_init_config_add_vgt_flush(sctx);
2746 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2747 }
2748
2749 /* Flush the context to re-emit both init_config states. */
2750 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2751 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2752
2753 /* Set ring bindings. */
2754 if (sctx->esgs_ring) {
2755 assert(sctx->b.chip_class <= VI);
2756 si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
2757 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2758 true, true, 4, 64, 0);
2759 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
2760 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2761 false, false, 0, 0, 0);
2762 }
2763 if (sctx->gsvs_ring) {
2764 si_set_ring_buffer(&sctx->b.b, SI_RING_GSVS,
2765 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
2766 false, false, 0, 0, 0);
2767 }
2768
2769 return true;
2770 }
2771
2772 static void si_shader_lock(struct si_shader *shader)
2773 {
2774 mtx_lock(&shader->selector->mutex);
2775 if (shader->previous_stage_sel) {
2776 assert(shader->previous_stage_sel != shader->selector);
2777 mtx_lock(&shader->previous_stage_sel->mutex);
2778 }
2779 }
2780
2781 static void si_shader_unlock(struct si_shader *shader)
2782 {
2783 if (shader->previous_stage_sel)
2784 mtx_unlock(&shader->previous_stage_sel->mutex);
2785 mtx_unlock(&shader->selector->mutex);
2786 }
2787
2788 /**
2789 * @returns 1 if \p sel has been updated to use a new scratch buffer
2790 * 0 if not
2791 * < 0 if there was a failure
2792 */
2793 static int si_update_scratch_buffer(struct si_context *sctx,
2794 struct si_shader *shader)
2795 {
2796 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
2797 int r;
2798
2799 if (!shader)
2800 return 0;
2801
2802 /* This shader doesn't need a scratch buffer */
2803 if (shader->config.scratch_bytes_per_wave == 0)
2804 return 0;
2805
2806 /* Prevent race conditions when updating:
2807 * - si_shader::scratch_bo
2808 * - si_shader::binary::code
2809 * - si_shader::previous_stage::binary::code.
2810 */
2811 si_shader_lock(shader);
2812
2813 /* This shader is already configured to use the current
2814 * scratch buffer. */
2815 if (shader->scratch_bo == sctx->scratch_buffer) {
2816 si_shader_unlock(shader);
2817 return 0;
2818 }
2819
2820 assert(sctx->scratch_buffer);
2821
2822 if (shader->previous_stage)
2823 si_shader_apply_scratch_relocs(shader->previous_stage, scratch_va);
2824
2825 si_shader_apply_scratch_relocs(shader, scratch_va);
2826
2827 /* Replace the shader bo with a new bo that has the relocs applied. */
2828 r = si_shader_binary_upload(sctx->screen, shader);
2829 if (r) {
2830 si_shader_unlock(shader);
2831 return r;
2832 }
2833
2834 /* Update the shader state to use the new shader bo. */
2835 si_shader_init_pm4_state(sctx->screen, shader);
2836
2837 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
2838
2839 si_shader_unlock(shader);
2840 return 1;
2841 }
2842
2843 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
2844 {
2845 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
2846 }
2847
2848 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
2849 {
2850 return shader ? shader->config.scratch_bytes_per_wave : 0;
2851 }
2852
2853 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
2854 {
2855 if (!sctx->tes_shader.cso)
2856 return NULL; /* tessellation disabled */
2857
2858 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
2859 sctx->fixed_func_tcs_shader.current;
2860 }
2861
2862 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
2863 {
2864 unsigned bytes = 0;
2865
2866 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
2867 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
2868 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
2869 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
2870
2871 if (sctx->tes_shader.cso) {
2872 struct si_shader *tcs = si_get_tcs_current(sctx);
2873
2874 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
2875 }
2876 return bytes;
2877 }
2878
2879 static bool si_update_scratch_relocs(struct si_context *sctx)
2880 {
2881 struct si_shader *tcs = si_get_tcs_current(sctx);
2882 int r;
2883
2884 /* Update the shaders, so that they are using the latest scratch.
2885 * The scratch buffer may have been changed since these shaders were
2886 * last used, so we still need to try to update them, even if they
2887 * require scratch buffers smaller than the current size.
2888 */
2889 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
2890 if (r < 0)
2891 return false;
2892 if (r == 1)
2893 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2894
2895 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
2896 if (r < 0)
2897 return false;
2898 if (r == 1)
2899 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2900
2901 r = si_update_scratch_buffer(sctx, tcs);
2902 if (r < 0)
2903 return false;
2904 if (r == 1)
2905 si_pm4_bind_state(sctx, hs, tcs->pm4);
2906
2907 /* VS can be bound as LS, ES, or VS. */
2908 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
2909 if (r < 0)
2910 return false;
2911 if (r == 1) {
2912 if (sctx->tes_shader.current)
2913 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2914 else if (sctx->gs_shader.current)
2915 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2916 else
2917 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2918 }
2919
2920 /* TES can be bound as ES or VS. */
2921 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
2922 if (r < 0)
2923 return false;
2924 if (r == 1) {
2925 if (sctx->gs_shader.current)
2926 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2927 else
2928 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2929 }
2930
2931 return true;
2932 }
2933
2934 static bool si_update_spi_tmpring_size(struct si_context *sctx)
2935 {
2936 unsigned current_scratch_buffer_size =
2937 si_get_current_scratch_buffer_size(sctx);
2938 unsigned scratch_bytes_per_wave =
2939 si_get_max_scratch_bytes_per_wave(sctx);
2940 unsigned scratch_needed_size = scratch_bytes_per_wave *
2941 sctx->scratch_waves;
2942 unsigned spi_tmpring_size;
2943
2944 if (scratch_needed_size > 0) {
2945 if (scratch_needed_size > current_scratch_buffer_size) {
2946 /* Create a bigger scratch buffer */
2947 r600_resource_reference(&sctx->scratch_buffer, NULL);
2948
2949 sctx->scratch_buffer = (struct r600_resource*)
2950 r600_aligned_buffer_create(&sctx->screen->b.b,
2951 R600_RESOURCE_FLAG_UNMAPPABLE,
2952 PIPE_USAGE_DEFAULT,
2953 scratch_needed_size, 256);
2954 if (!sctx->scratch_buffer)
2955 return false;
2956
2957 si_mark_atom_dirty(sctx, &sctx->scratch_state);
2958 r600_context_add_resource_size(&sctx->b.b,
2959 &sctx->scratch_buffer->b.b);
2960 }
2961
2962 if (!si_update_scratch_relocs(sctx))
2963 return false;
2964 }
2965
2966 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
2967 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
2968 "scratch size should already be aligned correctly.");
2969
2970 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
2971 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
2972 if (spi_tmpring_size != sctx->spi_tmpring_size) {
2973 sctx->spi_tmpring_size = spi_tmpring_size;
2974 si_mark_atom_dirty(sctx, &sctx->scratch_state);
2975 }
2976 return true;
2977 }
2978
2979 static void si_init_tess_factor_ring(struct si_context *sctx)
2980 {
2981 bool double_offchip_buffers = sctx->b.chip_class >= CIK &&
2982 sctx->b.family != CHIP_CARRIZO &&
2983 sctx->b.family != CHIP_STONEY;
2984 /* This must be one less than the maximum number due to a hw limitation.
2985 * Various hardware bugs in SI, CIK, and GFX9 need this.
2986 */
2987 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
2988 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
2989 sctx->screen->b.info.max_se;
2990 unsigned offchip_granularity;
2991
2992 switch (sctx->screen->tess_offchip_block_dw_size) {
2993 default:
2994 assert(0);
2995 /* fall through */
2996 case 8192:
2997 offchip_granularity = V_03093C_X_8K_DWORDS;
2998 break;
2999 case 4096:
3000 offchip_granularity = V_03093C_X_4K_DWORDS;
3001 break;
3002 }
3003
3004 assert(!sctx->tf_ring);
3005 /* Use 64K alignment for both rings, so that we can pass the address
3006 * to shaders as one SGPR containing bits [16:47].
3007 */
3008 sctx->tf_ring = r600_aligned_buffer_create(sctx->b.b.screen,
3009 R600_RESOURCE_FLAG_UNMAPPABLE,
3010 PIPE_USAGE_DEFAULT,
3011 32768 * sctx->screen->b.info.max_se,
3012 64 * 1024);
3013 if (!sctx->tf_ring)
3014 return;
3015
3016 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
3017
3018 sctx->tess_offchip_ring =
3019 r600_aligned_buffer_create(sctx->b.b.screen,
3020 R600_RESOURCE_FLAG_UNMAPPABLE,
3021 PIPE_USAGE_DEFAULT,
3022 max_offchip_buffers *
3023 sctx->screen->tess_offchip_block_dw_size * 4,
3024 64 * 1024);
3025 if (!sctx->tess_offchip_ring)
3026 return;
3027
3028 si_init_config_add_vgt_flush(sctx);
3029
3030 uint64_t offchip_va = r600_resource(sctx->tess_offchip_ring)->gpu_address;
3031 uint64_t factor_va = r600_resource(sctx->tf_ring)->gpu_address;
3032 assert((offchip_va & 0xffff) == 0);
3033 assert((factor_va & 0xffff) == 0);
3034
3035 si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_offchip_ring),
3036 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3037 si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tf_ring),
3038 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3039
3040 /* Append these registers to the init config state. */
3041 if (sctx->b.chip_class >= CIK) {
3042 if (sctx->b.chip_class >= VI)
3043 --max_offchip_buffers;
3044
3045 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3046 S_030938_SIZE(sctx->tf_ring->width0 / 4));
3047 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3048 factor_va >> 8);
3049 if (sctx->b.chip_class >= GFX9)
3050 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3051 factor_va >> 40);
3052 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3053 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
3054 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity));
3055 } else {
3056 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
3057 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3058 S_008988_SIZE(sctx->tf_ring->width0 / 4));
3059 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3060 factor_va >> 8);
3061 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3062 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers));
3063 }
3064
3065 if (sctx->b.chip_class >= GFX9) {
3066 si_pm4_set_reg(sctx->init_config,
3067 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
3068 GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K * 4,
3069 offchip_va >> 16);
3070 si_pm4_set_reg(sctx->init_config,
3071 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
3072 GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K * 4,
3073 factor_va >> 16);
3074 } else {
3075 si_pm4_set_reg(sctx->init_config,
3076 R_00B430_SPI_SHADER_USER_DATA_HS_0 +
3077 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K * 4,
3078 offchip_va >> 16);
3079 si_pm4_set_reg(sctx->init_config,
3080 R_00B430_SPI_SHADER_USER_DATA_HS_0 +
3081 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K * 4,
3082 factor_va >> 16);
3083 }
3084
3085 /* Flush the context to re-emit the init_config state.
3086 * This is done only once in a lifetime of a context.
3087 */
3088 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3089 sctx->b.initial_gfx_cs_size = 0; /* force flush */
3090 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
3091 }
3092
3093 /**
3094 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
3095 * VS passes its outputs to TES directly, so the fixed-function shader only
3096 * has to write TESSOUTER and TESSINNER.
3097 */
3098 static void si_generate_fixed_func_tcs(struct si_context *sctx)
3099 {
3100 struct ureg_src outer, inner;
3101 struct ureg_dst tessouter, tessinner;
3102 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
3103
3104 if (!ureg)
3105 return; /* if we get here, we're screwed */
3106
3107 assert(!sctx->fixed_func_tcs_shader.cso);
3108
3109 outer = ureg_DECL_system_value(ureg,
3110 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
3111 inner = ureg_DECL_system_value(ureg,
3112 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
3113
3114 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
3115 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
3116
3117 ureg_MOV(ureg, tessouter, outer);
3118 ureg_MOV(ureg, tessinner, inner);
3119 ureg_END(ureg);
3120
3121 sctx->fixed_func_tcs_shader.cso =
3122 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
3123 }
3124
3125 static void si_update_vgt_shader_config(struct si_context *sctx)
3126 {
3127 /* Calculate the index of the config.
3128 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3129 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
3130 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
3131
3132 if (!*pm4) {
3133 uint32_t stages = 0;
3134
3135 *pm4 = CALLOC_STRUCT(si_pm4_state);
3136
3137 if (sctx->tes_shader.cso) {
3138 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3139 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3140
3141 if (sctx->gs_shader.cso)
3142 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3143 S_028B54_GS_EN(1) |
3144 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3145 else
3146 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3147 } else if (sctx->gs_shader.cso) {
3148 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3149 S_028B54_GS_EN(1) |
3150 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3151 }
3152
3153 if (sctx->b.chip_class >= GFX9)
3154 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3155
3156 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3157 }
3158 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3159 }
3160
3161 bool si_update_shaders(struct si_context *sctx)
3162 {
3163 struct pipe_context *ctx = (struct pipe_context*)sctx;
3164 struct si_compiler_ctx_state compiler_state;
3165 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3166 struct si_shader *old_vs = si_get_vs_state(sctx);
3167 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3168 struct si_shader *old_ps = sctx->ps_shader.current;
3169 unsigned old_spi_shader_col_format =
3170 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3171 int r;
3172
3173 compiler_state.tm = sctx->tm;
3174 compiler_state.debug = sctx->b.debug;
3175 compiler_state.is_debug_context = sctx->is_debug;
3176
3177 /* Update stages before GS. */
3178 if (sctx->tes_shader.cso) {
3179 if (!sctx->tf_ring) {
3180 si_init_tess_factor_ring(sctx);
3181 if (!sctx->tf_ring)
3182 return false;
3183 }
3184
3185 /* VS as LS */
3186 if (sctx->b.chip_class <= VI) {
3187 r = si_shader_select(ctx, &sctx->vs_shader,
3188 &compiler_state);
3189 if (r)
3190 return false;
3191 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3192 }
3193
3194 if (sctx->tcs_shader.cso) {
3195 r = si_shader_select(ctx, &sctx->tcs_shader,
3196 &compiler_state);
3197 if (r)
3198 return false;
3199 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3200 } else {
3201 if (!sctx->fixed_func_tcs_shader.cso) {
3202 si_generate_fixed_func_tcs(sctx);
3203 if (!sctx->fixed_func_tcs_shader.cso)
3204 return false;
3205 }
3206
3207 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3208 &compiler_state);
3209 if (r)
3210 return false;
3211 si_pm4_bind_state(sctx, hs,
3212 sctx->fixed_func_tcs_shader.current->pm4);
3213 }
3214
3215 if (sctx->gs_shader.cso) {
3216 /* TES as ES */
3217 if (sctx->b.chip_class <= VI) {
3218 r = si_shader_select(ctx, &sctx->tes_shader,
3219 &compiler_state);
3220 if (r)
3221 return false;
3222 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3223 }
3224 } else {
3225 /* TES as VS */
3226 r = si_shader_select(ctx, &sctx->tes_shader,
3227 &compiler_state);
3228 if (r)
3229 return false;
3230 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3231 }
3232 } else if (sctx->gs_shader.cso) {
3233 if (sctx->b.chip_class <= VI) {
3234 /* VS as ES */
3235 r = si_shader_select(ctx, &sctx->vs_shader,
3236 &compiler_state);
3237 if (r)
3238 return false;
3239 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3240
3241 si_pm4_bind_state(sctx, ls, NULL);
3242 si_pm4_bind_state(sctx, hs, NULL);
3243 }
3244 } else {
3245 /* VS as VS */
3246 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
3247 if (r)
3248 return false;
3249 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3250 si_pm4_bind_state(sctx, ls, NULL);
3251 si_pm4_bind_state(sctx, hs, NULL);
3252 }
3253
3254 /* Update GS. */
3255 if (sctx->gs_shader.cso) {
3256 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
3257 if (r)
3258 return false;
3259 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3260 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3261
3262 if (!si_update_gs_ring_buffers(sctx))
3263 return false;
3264 } else {
3265 si_pm4_bind_state(sctx, gs, NULL);
3266 if (sctx->b.chip_class <= VI)
3267 si_pm4_bind_state(sctx, es, NULL);
3268 }
3269
3270 si_update_vgt_shader_config(sctx);
3271
3272 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3273 si_mark_atom_dirty(sctx, &sctx->clip_regs);
3274
3275 if (sctx->ps_shader.cso) {
3276 unsigned db_shader_control;
3277
3278 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
3279 if (r)
3280 return false;
3281 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3282
3283 db_shader_control =
3284 sctx->ps_shader.cso->db_shader_control |
3285 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3286
3287 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3288 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3289 sctx->flatshade != rs->flatshade) {
3290 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3291 sctx->flatshade = rs->flatshade;
3292 si_mark_atom_dirty(sctx, &sctx->spi_map);
3293 }
3294
3295 if (sctx->screen->b.rbplus_allowed &&
3296 si_pm4_state_changed(sctx, ps) &&
3297 (!old_ps ||
3298 old_spi_shader_col_format !=
3299 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3300 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
3301
3302 if (sctx->ps_db_shader_control != db_shader_control) {
3303 sctx->ps_db_shader_control = db_shader_control;
3304 si_mark_atom_dirty(sctx, &sctx->db_render_state);
3305 if (sctx->screen->dpbb_allowed)
3306 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
3307 }
3308
3309 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3310 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3311 si_mark_atom_dirty(sctx, &sctx->msaa_config);
3312
3313 if (sctx->b.chip_class == SI)
3314 si_mark_atom_dirty(sctx, &sctx->db_render_state);
3315
3316 if (sctx->framebuffer.nr_samples <= 1)
3317 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
3318 }
3319 }
3320
3321 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3322 si_pm4_state_enabled_and_changed(sctx, hs) ||
3323 si_pm4_state_enabled_and_changed(sctx, es) ||
3324 si_pm4_state_enabled_and_changed(sctx, gs) ||
3325 si_pm4_state_enabled_and_changed(sctx, vs) ||
3326 si_pm4_state_enabled_and_changed(sctx, ps)) {
3327 if (!si_update_spi_tmpring_size(sctx))
3328 return false;
3329 }
3330
3331 if (sctx->b.chip_class >= CIK) {
3332 if (si_pm4_state_enabled_and_changed(sctx, ls))
3333 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3334 else if (!sctx->queued.named.ls)
3335 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3336
3337 if (si_pm4_state_enabled_and_changed(sctx, hs))
3338 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3339 else if (!sctx->queued.named.hs)
3340 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3341
3342 if (si_pm4_state_enabled_and_changed(sctx, es))
3343 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
3344 else if (!sctx->queued.named.es)
3345 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
3346
3347 if (si_pm4_state_enabled_and_changed(sctx, gs))
3348 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
3349 else if (!sctx->queued.named.gs)
3350 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
3351
3352 if (si_pm4_state_enabled_and_changed(sctx, vs))
3353 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
3354 else if (!sctx->queued.named.vs)
3355 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
3356
3357 if (si_pm4_state_enabled_and_changed(sctx, ps))
3358 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
3359 else if (!sctx->queued.named.ps)
3360 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
3361 }
3362
3363 sctx->do_update_shaders = false;
3364 return true;
3365 }
3366
3367 static void si_emit_scratch_state(struct si_context *sctx,
3368 struct r600_atom *atom)
3369 {
3370 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3371
3372 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3373 sctx->spi_tmpring_size);
3374
3375 if (sctx->scratch_buffer) {
3376 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
3377 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3378 RADEON_PRIO_SCRATCH_BUFFER);
3379 }
3380 }
3381
3382 void si_init_shader_functions(struct si_context *sctx)
3383 {
3384 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
3385 si_init_atom(sctx, &sctx->scratch_state, &sctx->atoms.s.scratch_state,
3386 si_emit_scratch_state);
3387
3388 sctx->b.b.create_vs_state = si_create_shader_selector;
3389 sctx->b.b.create_tcs_state = si_create_shader_selector;
3390 sctx->b.b.create_tes_state = si_create_shader_selector;
3391 sctx->b.b.create_gs_state = si_create_shader_selector;
3392 sctx->b.b.create_fs_state = si_create_shader_selector;
3393
3394 sctx->b.b.bind_vs_state = si_bind_vs_shader;
3395 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
3396 sctx->b.b.bind_tes_state = si_bind_tes_shader;
3397 sctx->b.b.bind_gs_state = si_bind_gs_shader;
3398 sctx->b.b.bind_fs_state = si_bind_ps_shader;
3399
3400 sctx->b.b.delete_vs_state = si_delete_shader_selector;
3401 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
3402 sctx->b.b.delete_tes_state = si_delete_shader_selector;
3403 sctx->b.b.delete_gs_state = si_delete_shader_selector;
3404 sctx->b.b.delete_fs_state = si_delete_shader_selector;
3405 }