2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
29 #include "si_shader.h"
31 #include "radeon/r600_cs.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/hash_table.h"
36 #include "util/u_hash.h"
37 #include "util/u_memory.h"
38 #include "util/u_prim.h"
39 #include "util/u_simple_shaders.h"
44 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
47 static void *si_get_tgsi_binary(struct si_shader_selector
*sel
)
49 unsigned tgsi_size
= tgsi_num_tokens(sel
->tokens
) *
50 sizeof(struct tgsi_token
);
51 unsigned size
= 4 + tgsi_size
+ sizeof(sel
->so
);
52 char *result
= (char*)MALLOC(size
);
57 *((uint32_t*)result
) = size
;
58 memcpy(result
+ 4, sel
->tokens
, tgsi_size
);
59 memcpy(result
+ 4 + tgsi_size
, &sel
->so
, sizeof(sel
->so
));
63 /** Copy "data" to "ptr" and return the next dword following copied data. */
64 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
66 /* data may be NULL if size == 0 */
68 memcpy(ptr
, data
, size
);
69 ptr
+= DIV_ROUND_UP(size
, 4);
73 /** Read data from "ptr". Return the next dword following the data. */
74 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
76 memcpy(data
, ptr
, size
);
77 ptr
+= DIV_ROUND_UP(size
, 4);
82 * Write the size as uint followed by the data. Return the next dword
83 * following the copied data.
85 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
88 return write_data(ptr
, data
, size
);
92 * Read the size as uint followed by the data. Return both via parameters.
93 * Return the next dword following the data.
95 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
98 assert(*data
== NULL
);
99 *data
= malloc(*size
);
100 return read_data(ptr
, *data
, *size
);
104 * Return the shader binary in a buffer. The first 4 bytes contain its size
107 static void *si_get_shader_binary(struct si_shader
*shader
)
109 /* There is always a size of data followed by the data itself. */
110 unsigned relocs_size
= shader
->binary
.reloc_count
*
111 sizeof(shader
->binary
.relocs
[0]);
112 unsigned disasm_size
= strlen(shader
->binary
.disasm_string
) + 1;
115 4 + /* CRC32 of the data below */
116 align(sizeof(shader
->config
), 4) +
117 align(sizeof(shader
->info
), 4) +
118 4 + align(shader
->binary
.code_size
, 4) +
119 4 + align(shader
->binary
.rodata_size
, 4) +
120 4 + align(relocs_size
, 4) +
121 4 + align(disasm_size
, 4);
122 void *buffer
= CALLOC(1, size
);
123 uint32_t *ptr
= (uint32_t*)buffer
;
129 ptr
++; /* CRC32 is calculated at the end. */
131 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
132 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
133 ptr
= write_chunk(ptr
, shader
->binary
.code
, shader
->binary
.code_size
);
134 ptr
= write_chunk(ptr
, shader
->binary
.rodata
, shader
->binary
.rodata_size
);
135 ptr
= write_chunk(ptr
, shader
->binary
.relocs
, relocs_size
);
136 ptr
= write_chunk(ptr
, shader
->binary
.disasm_string
, disasm_size
);
137 assert((char *)ptr
- (char *)buffer
== size
);
140 ptr
= (uint32_t*)buffer
;
142 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
147 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
149 uint32_t *ptr
= (uint32_t*)binary
;
150 uint32_t size
= *ptr
++;
151 uint32_t crc32
= *ptr
++;
154 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
155 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
159 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
160 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
161 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.code
,
162 &shader
->binary
.code_size
);
163 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.rodata
,
164 &shader
->binary
.rodata_size
);
165 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.relocs
, &chunk_size
);
166 shader
->binary
.reloc_count
= chunk_size
/ sizeof(shader
->binary
.relocs
[0]);
167 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.disasm_string
, &chunk_size
);
173 * Insert a shader into the cache. It's assumed the shader is not in the cache.
174 * Use si_shader_cache_load_shader before calling this.
176 * Returns false on failure, in which case the tgsi_binary should be freed.
178 static bool si_shader_cache_insert_shader(struct si_screen
*sscreen
,
180 struct si_shader
*shader
)
182 void *hw_binary
= si_get_shader_binary(shader
);
187 if (_mesa_hash_table_insert(sscreen
->shader_cache
, tgsi_binary
,
188 hw_binary
) == NULL
) {
196 static bool si_shader_cache_load_shader(struct si_screen
*sscreen
,
198 struct si_shader
*shader
)
200 struct hash_entry
*entry
=
201 _mesa_hash_table_search(sscreen
->shader_cache
, tgsi_binary
);
205 return si_load_shader_binary(shader
, entry
->data
);
208 static uint32_t si_shader_cache_key_hash(const void *key
)
210 /* The first dword is the key size. */
211 return util_hash_crc32(key
, *(uint32_t*)key
);
214 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
216 uint32_t *keya
= (uint32_t*)a
;
217 uint32_t *keyb
= (uint32_t*)b
;
219 /* The first dword is the key size. */
223 return memcmp(keya
, keyb
, *keya
) == 0;
226 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
228 FREE((void*)entry
->key
);
232 bool si_init_shader_cache(struct si_screen
*sscreen
)
234 pipe_mutex_init(sscreen
->shader_cache_mutex
);
235 sscreen
->shader_cache
=
236 _mesa_hash_table_create(NULL
,
237 si_shader_cache_key_hash
,
238 si_shader_cache_key_equals
);
239 return sscreen
->shader_cache
!= NULL
;
242 void si_destroy_shader_cache(struct si_screen
*sscreen
)
244 if (sscreen
->shader_cache
)
245 _mesa_hash_table_destroy(sscreen
->shader_cache
,
246 si_destroy_shader_cache_entry
);
247 pipe_mutex_destroy(sscreen
->shader_cache_mutex
);
252 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
253 struct si_shader
*shader
,
254 struct si_pm4_state
*pm4
)
256 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
257 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
258 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
259 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
260 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
261 unsigned type
, partitioning
, topology
, distribution_mode
;
263 switch (tes_prim_mode
) {
264 case PIPE_PRIM_LINES
:
265 type
= V_028B6C_TESS_ISOLINE
;
267 case PIPE_PRIM_TRIANGLES
:
268 type
= V_028B6C_TESS_TRIANGLE
;
270 case PIPE_PRIM_QUADS
:
271 type
= V_028B6C_TESS_QUAD
;
278 switch (tes_spacing
) {
279 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
280 partitioning
= V_028B6C_PART_FRAC_ODD
;
282 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
283 partitioning
= V_028B6C_PART_FRAC_EVEN
;
285 case PIPE_TESS_SPACING_EQUAL
:
286 partitioning
= V_028B6C_PART_INTEGER
;
294 topology
= V_028B6C_OUTPUT_POINT
;
295 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
296 topology
= V_028B6C_OUTPUT_LINE
;
297 else if (tes_vertex_order_cw
)
298 /* for some reason, this must be the other way around */
299 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
301 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
303 if (sscreen
->has_distributed_tess
) {
304 if (sscreen
->b
.family
== CHIP_FIJI
||
305 sscreen
->b
.family
>= CHIP_POLARIS10
)
306 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
308 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
310 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
312 si_pm4_set_reg(pm4
, R_028B6C_VGT_TF_PARAM
,
313 S_028B6C_TYPE(type
) |
314 S_028B6C_PARTITIONING(partitioning
) |
315 S_028B6C_TOPOLOGY(topology
) |
316 S_028B6C_DISTRIBUTION_MODE(distribution_mode
));
319 static void si_shader_ls(struct si_shader
*shader
)
321 struct si_pm4_state
*pm4
;
322 unsigned vgpr_comp_cnt
;
325 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
329 va
= shader
->bo
->gpu_address
;
330 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_USER_SHADER
);
332 /* We need at least 2 components for LS.
333 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
334 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 3 : 1;
336 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
337 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, va
>> 40);
339 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
340 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
341 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt
) |
342 S_00B528_DX10_CLAMP(1) |
343 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
344 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(SI_LS_NUM_USER_SGPR
) |
345 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
348 static void si_shader_hs(struct si_shader
*shader
)
350 struct si_pm4_state
*pm4
;
353 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
357 va
= shader
->bo
->gpu_address
;
358 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_USER_SHADER
);
360 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
361 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, va
>> 40);
362 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
363 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
364 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
365 S_00B428_DX10_CLAMP(1) |
366 S_00B428_FLOAT_MODE(shader
->config
.float_mode
));
367 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
368 S_00B42C_USER_SGPR(SI_TCS_NUM_USER_SGPR
) |
369 S_00B42C_OC_LDS_EN(1) |
370 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
373 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
375 struct si_pm4_state
*pm4
;
376 unsigned num_user_sgprs
;
377 unsigned vgpr_comp_cnt
;
381 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
386 va
= shader
->bo
->gpu_address
;
387 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_USER_SHADER
);
389 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
390 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 3 : 0;
391 num_user_sgprs
= SI_ES_NUM_USER_SGPR
;
392 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
393 vgpr_comp_cnt
= 3; /* all components are needed for TES */
394 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
396 unreachable("invalid shader selector type");
398 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
400 si_pm4_set_reg(pm4
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
401 shader
->selector
->esgs_itemsize
/ 4);
402 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
403 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
404 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
405 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
406 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
407 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
408 S_00B328_DX10_CLAMP(1) |
409 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
410 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
411 S_00B32C_USER_SGPR(num_user_sgprs
) |
412 S_00B32C_OC_LDS_EN(oc_lds_en
) |
413 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
415 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
416 si_set_tesseval_regs(sscreen
, shader
, pm4
);
420 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
423 static uint32_t si_vgt_gs_mode(struct si_shader
*shader
)
425 unsigned gs_max_vert_out
= shader
->selector
->gs_max_out_vertices
;
428 if (gs_max_vert_out
<= 128) {
429 cut_mode
= V_028A40_GS_CUT_128
;
430 } else if (gs_max_vert_out
<= 256) {
431 cut_mode
= V_028A40_GS_CUT_256
;
432 } else if (gs_max_vert_out
<= 512) {
433 cut_mode
= V_028A40_GS_CUT_512
;
435 assert(gs_max_vert_out
<= 1024);
436 cut_mode
= V_028A40_GS_CUT_1024
;
439 return S_028A40_MODE(V_028A40_GS_SCENARIO_G
) |
440 S_028A40_CUT_MODE(cut_mode
)|
441 S_028A40_ES_WRITE_OPTIMIZE(1) |
442 S_028A40_GS_WRITE_OPTIMIZE(1);
445 static void si_shader_gs(struct si_shader
*shader
)
447 unsigned gs_vert_itemsize
= shader
->selector
->gsvs_vertex_size
;
448 unsigned gsvs_itemsize
= shader
->selector
->max_gsvs_emit_size
>> 2;
449 unsigned gs_num_invocations
= shader
->selector
->gs_num_invocations
;
450 struct si_pm4_state
*pm4
;
452 unsigned max_stream
= shader
->selector
->max_gs_stream
;
454 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
455 assert(gsvs_itemsize
< (1 << 15));
457 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
462 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, si_vgt_gs_mode(shader
));
464 si_pm4_set_reg(pm4
, R_028A60_VGT_GSVS_RING_OFFSET_1
, gsvs_itemsize
);
465 si_pm4_set_reg(pm4
, R_028A64_VGT_GSVS_RING_OFFSET_2
, gsvs_itemsize
* ((max_stream
>= 2) ? 2 : 1));
466 si_pm4_set_reg(pm4
, R_028A68_VGT_GSVS_RING_OFFSET_3
, gsvs_itemsize
* ((max_stream
>= 3) ? 3 : 1));
468 si_pm4_set_reg(pm4
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, gsvs_itemsize
* (max_stream
+ 1));
470 si_pm4_set_reg(pm4
, R_028B38_VGT_GS_MAX_VERT_OUT
, shader
->selector
->gs_max_out_vertices
);
472 si_pm4_set_reg(pm4
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, gs_vert_itemsize
>> 2);
473 si_pm4_set_reg(pm4
, R_028B60_VGT_GS_VERT_ITEMSIZE_1
, (max_stream
>= 1) ? gs_vert_itemsize
>> 2 : 0);
474 si_pm4_set_reg(pm4
, R_028B64_VGT_GS_VERT_ITEMSIZE_2
, (max_stream
>= 2) ? gs_vert_itemsize
>> 2 : 0);
475 si_pm4_set_reg(pm4
, R_028B68_VGT_GS_VERT_ITEMSIZE_3
, (max_stream
>= 3) ? gs_vert_itemsize
>> 2 : 0);
477 si_pm4_set_reg(pm4
, R_028B90_VGT_GS_INSTANCE_CNT
,
478 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
479 S_028B90_ENABLE(gs_num_invocations
> 0));
481 va
= shader
->bo
->gpu_address
;
482 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_USER_SHADER
);
483 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
484 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, va
>> 40);
486 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
487 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
488 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
489 S_00B228_DX10_CLAMP(1) |
490 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
491 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
492 S_00B22C_USER_SGPR(SI_GS_NUM_USER_SGPR
) |
493 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
497 * Compute the state for \p shader, which will run as a vertex shader on the
500 * If \p gs is non-NULL, it points to the geometry shader for which this shader
501 * is the copy shader.
503 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
504 struct si_shader
*gs
)
506 struct si_pm4_state
*pm4
;
507 unsigned num_user_sgprs
;
508 unsigned nparams
, vgpr_comp_cnt
;
511 unsigned window_space
=
512 shader
->selector
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
513 bool enable_prim_id
= si_vs_exports_prim_id(shader
);
515 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
520 /* We always write VGT_GS_MODE in the VS state, because every switch
521 * between different shader pipelines involving a different GS or no
522 * GS at all involves a switch of the VS (different GS use different
523 * copy shaders). On the other hand, when the API switches from a GS to
524 * no GS and then back to the same GS used originally, the GS state is
528 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
,
529 S_028A40_MODE(enable_prim_id
? V_028A40_GS_SCENARIO_A
: 0));
530 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, enable_prim_id
);
532 si_pm4_set_reg(pm4
, R_028A40_VGT_GS_MODE
, si_vgt_gs_mode(gs
));
533 si_pm4_set_reg(pm4
, R_028A84_VGT_PRIMITIVEID_EN
, 0);
536 va
= shader
->bo
->gpu_address
;
537 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_USER_SHADER
);
540 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
541 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
542 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
543 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 3 : (enable_prim_id
? 2 : 0);
544 num_user_sgprs
= SI_VS_NUM_USER_SGPR
;
545 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
546 vgpr_comp_cnt
= 3; /* all components are needed for TES */
547 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
549 unreachable("invalid shader selector type");
551 /* VS is required to export at least one param. */
552 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
553 si_pm4_set_reg(pm4
, R_0286C4_SPI_VS_OUT_CONFIG
,
554 S_0286C4_VS_EXPORT_COUNT(nparams
- 1));
556 si_pm4_set_reg(pm4
, R_02870C_SPI_SHADER_POS_FORMAT
,
557 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
558 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
559 V_02870C_SPI_SHADER_4COMP
:
560 V_02870C_SPI_SHADER_NONE
) |
561 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
562 V_02870C_SPI_SHADER_4COMP
:
563 V_02870C_SPI_SHADER_NONE
) |
564 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
565 V_02870C_SPI_SHADER_4COMP
:
566 V_02870C_SPI_SHADER_NONE
));
568 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
570 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
571 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, va
>> 40);
572 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
,
573 S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
574 S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
575 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
576 S_00B128_DX10_CLAMP(1) |
577 S_00B128_FLOAT_MODE(shader
->config
.float_mode
));
578 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
,
579 S_00B12C_USER_SGPR(num_user_sgprs
) |
580 S_00B12C_OC_LDS_EN(oc_lds_en
) |
581 S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
582 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
583 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
584 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
585 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
) |
586 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
588 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
589 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
591 si_pm4_set_reg(pm4
, R_028818_PA_CL_VTE_CNTL
,
592 S_028818_VTX_W0_FMT(1) |
593 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
594 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
595 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
597 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
598 si_set_tesseval_regs(sscreen
, shader
, pm4
);
601 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
603 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
604 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
605 !!(info
->colors_read
& 0xf0);
606 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
607 (ps
->key
.ps
.prolog
.color_two_side
? num_colors
: 0);
609 assert(num_interp
<= 32);
610 return MIN2(num_interp
, 32);
613 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
615 unsigned value
= shader
->key
.ps
.epilog
.spi_shader_col_format
;
616 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
618 /* If the i-th target format is set, all previous target formats must
619 * be non-zero to avoid hangs.
621 for (i
= 0; i
< num_targets
; i
++)
622 if (!(value
& (0xf << (i
* 4))))
623 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
628 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format
)
630 unsigned i
, cb_shader_mask
= 0;
632 for (i
= 0; i
< 8; i
++) {
633 switch ((spi_shader_col_format
>> (i
* 4)) & 0xf) {
634 case V_028714_SPI_SHADER_ZERO
:
636 case V_028714_SPI_SHADER_32_R
:
637 cb_shader_mask
|= 0x1 << (i
* 4);
639 case V_028714_SPI_SHADER_32_GR
:
640 cb_shader_mask
|= 0x3 << (i
* 4);
642 case V_028714_SPI_SHADER_32_AR
:
643 cb_shader_mask
|= 0x9 << (i
* 4);
645 case V_028714_SPI_SHADER_FP16_ABGR
:
646 case V_028714_SPI_SHADER_UNORM16_ABGR
:
647 case V_028714_SPI_SHADER_SNORM16_ABGR
:
648 case V_028714_SPI_SHADER_UINT16_ABGR
:
649 case V_028714_SPI_SHADER_SINT16_ABGR
:
650 case V_028714_SPI_SHADER_32_ABGR
:
651 cb_shader_mask
|= 0xf << (i
* 4);
657 return cb_shader_mask
;
660 static void si_shader_ps(struct si_shader
*shader
)
662 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
663 struct si_pm4_state
*pm4
;
664 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
665 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
667 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
669 /* we need to enable at least one of them, otherwise we hang the GPU */
670 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
671 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
672 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
673 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
674 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
675 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
676 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
677 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
679 pm4
= shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
684 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
686 * 0 -> Position = pixel center
687 * 1 -> Position = pixel centroid
688 * 2 -> Position = at sample position
690 * From GLSL 4.5 specification, section 7.1:
691 * "The variable gl_FragCoord is available as an input variable from
692 * within fragment shaders and it holds the window relative coordinates
693 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
694 * value can be for any location within the pixel, or one of the
695 * fragment samples. The use of centroid does not further restrict
696 * this value to be inside the current primitive."
698 * Meaning that centroid has no effect and we can return anything within
699 * the pixel. Thus, return the value at sample position, because that's
700 * the most accurate one shaders can get.
702 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
704 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
705 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
706 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
708 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
709 cb_shader_mask
= si_get_cb_shader_mask(spi_shader_col_format
);
711 /* Ensure that some export memory is always allocated, for two reasons:
713 * 1) Correctness: The hardware ignores the EXEC mask if no export
714 * memory is allocated, so KILL and alpha test do not work correctly
716 * 2) Performance: Every shader needs at least a NULL export, even when
717 * it writes no color/depth output. The NULL export instruction
718 * stalls without this setting.
720 * Don't add this to CB_SHADER_MASK.
722 if (!spi_shader_col_format
&&
723 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
724 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
726 si_pm4_set_reg(pm4
, R_0286CC_SPI_PS_INPUT_ENA
, input_ena
);
727 si_pm4_set_reg(pm4
, R_0286D0_SPI_PS_INPUT_ADDR
,
728 shader
->config
.spi_ps_input_addr
);
730 /* Set interpolation controls. */
731 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
));
734 si_pm4_set_reg(pm4
, R_0286E0_SPI_BARYC_CNTL
, spi_baryc_cntl
);
735 si_pm4_set_reg(pm4
, R_0286D8_SPI_PS_IN_CONTROL
, spi_ps_in_control
);
737 si_pm4_set_reg(pm4
, R_028710_SPI_SHADER_Z_FORMAT
,
738 info
->writes_samplemask
? V_028710_SPI_SHADER_32_ABGR
:
739 info
->writes_stencil
? V_028710_SPI_SHADER_32_GR
:
740 info
->writes_z
? V_028710_SPI_SHADER_32_R
:
741 V_028710_SPI_SHADER_ZERO
);
743 si_pm4_set_reg(pm4
, R_028714_SPI_SHADER_COL_FORMAT
, spi_shader_col_format
);
744 si_pm4_set_reg(pm4
, R_02823C_CB_SHADER_MASK
, cb_shader_mask
);
746 va
= shader
->bo
->gpu_address
;
747 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_USER_SHADER
);
748 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
749 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, va
>> 40);
751 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
,
752 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
753 S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
754 S_00B028_DX10_CLAMP(1) |
755 S_00B028_FLOAT_MODE(shader
->config
.float_mode
));
756 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
757 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
758 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
759 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
761 /* Prefer RE_Z if the shader is complex enough. The requirement is either:
762 * - the shader uses at least 2 VMEM instructions, or
763 * - the code size is at least 50 2-dword instructions or 100 1-dword
766 * Shaders with side effects that must execute independently of the
767 * depth test require LATE_Z.
769 if (info
->writes_memory
&&
770 !info
->properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
])
771 shader
->z_order
= V_02880C_LATE_Z
;
772 else if (info
->num_memory_instructions
>= 2 ||
773 shader
->binary
.code_size
> 100*4)
774 shader
->z_order
= V_02880C_EARLY_Z_THEN_RE_Z
;
776 shader
->z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
779 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
780 struct si_shader
*shader
)
784 si_pm4_free_state_simple(shader
->pm4
);
786 switch (shader
->selector
->type
) {
787 case PIPE_SHADER_VERTEX
:
788 if (shader
->key
.vs
.as_ls
)
789 si_shader_ls(shader
);
790 else if (shader
->key
.vs
.as_es
)
791 si_shader_es(sscreen
, shader
);
793 si_shader_vs(sscreen
, shader
, NULL
);
795 case PIPE_SHADER_TESS_CTRL
:
796 si_shader_hs(shader
);
798 case PIPE_SHADER_TESS_EVAL
:
799 if (shader
->key
.tes
.as_es
)
800 si_shader_es(sscreen
, shader
);
802 si_shader_vs(sscreen
, shader
, NULL
);
804 case PIPE_SHADER_GEOMETRY
:
805 si_shader_gs(shader
);
806 si_shader_vs(sscreen
, shader
->gs_copy_shader
, shader
);
808 case PIPE_SHADER_FRAGMENT
:
809 si_shader_ps(shader
);
816 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
818 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
819 if (sctx
->queued
.named
.dsa
&&
820 !sctx
->framebuffer
.cb0_is_integer
)
821 return sctx
->queued
.named
.dsa
->alpha_func
;
823 return PIPE_FUNC_ALWAYS
;
826 /* Compute the key for the hw shader variant */
827 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
828 struct si_shader_selector
*sel
,
829 union si_shader_key
*key
)
831 struct si_context
*sctx
= (struct si_context
*)ctx
;
834 memset(key
, 0, sizeof(*key
));
837 case PIPE_SHADER_VERTEX
:
838 if (sctx
->vertex_elements
) {
839 unsigned count
= MIN2(sel
->info
.num_inputs
,
840 sctx
->vertex_elements
->count
);
841 for (i
= 0; i
< count
; ++i
)
842 key
->vs
.prolog
.instance_divisors
[i
] =
843 sctx
->vertex_elements
->elements
[i
].instance_divisor
;
845 if (sctx
->tes_shader
.cso
)
847 else if (sctx
->gs_shader
.cso
)
850 if (!sctx
->gs_shader
.cso
&& sctx
->ps_shader
.cso
&&
851 sctx
->ps_shader
.cso
->info
.uses_primid
)
852 key
->vs
.epilog
.export_prim_id
= 1;
854 case PIPE_SHADER_TESS_CTRL
:
855 key
->tcs
.epilog
.prim_mode
=
856 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
858 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
859 key
->tcs
.epilog
.inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
861 case PIPE_SHADER_TESS_EVAL
:
862 if (sctx
->gs_shader
.cso
)
864 else if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
865 key
->tes
.epilog
.export_prim_id
= 1;
867 case PIPE_SHADER_GEOMETRY
:
869 case PIPE_SHADER_FRAGMENT
: {
870 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
871 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
873 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
874 sel
->info
.colors_written
== 0x1)
875 key
->ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
878 /* Select the shader color format based on whether
879 * blending or alpha are needed.
881 key
->ps
.epilog
.spi_shader_col_format
=
882 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
883 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
884 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
885 sctx
->framebuffer
.spi_shader_col_format_blend
) |
886 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
887 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
888 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
889 sctx
->framebuffer
.spi_shader_col_format
);
891 key
->ps
.epilog
.spi_shader_col_format
= sctx
->framebuffer
.spi_shader_col_format
;
893 /* If alpha-to-coverage is enabled, we have to export alpha
894 * even if there is no color buffer.
896 if (!(key
->ps
.epilog
.spi_shader_col_format
& 0xf) &&
897 blend
&& blend
->alpha_to_coverage
)
898 key
->ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
900 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
901 * to the range supported by the type if a channel has less
902 * than 16 bits and the export format is 16_ABGR.
904 if (sctx
->b
.chip_class
<= CIK
&& sctx
->b
.family
!= CHIP_HAWAII
)
905 key
->ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
907 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
908 if (!key
->ps
.epilog
.last_cbuf
) {
909 key
->ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
910 key
->ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
914 bool is_poly
= (sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES
&&
915 sctx
->current_rast_prim
<= PIPE_PRIM_POLYGON
) ||
916 sctx
->current_rast_prim
>= PIPE_PRIM_TRIANGLES_ADJACENCY
;
917 bool is_line
= !is_poly
&& sctx
->current_rast_prim
!= PIPE_PRIM_POINTS
;
919 key
->ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
920 key
->ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
922 if (sctx
->queued
.named
.blend
) {
923 key
->ps
.epilog
.alpha_to_one
= sctx
->queued
.named
.blend
->alpha_to_one
&&
924 rs
->multisample_enable
&&
925 !sctx
->framebuffer
.cb0_is_integer
;
928 key
->ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
929 key
->ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
930 (is_line
&& rs
->line_smooth
)) &&
931 sctx
->framebuffer
.nr_samples
<= 1;
932 key
->ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
934 if (rs
->force_persample_interp
&&
935 rs
->multisample_enable
&&
936 sctx
->framebuffer
.nr_samples
> 1 &&
937 sctx
->ps_iter_samples
> 1) {
938 key
->ps
.prolog
.force_persp_sample_interp
=
939 sel
->info
.uses_persp_center
||
940 sel
->info
.uses_persp_centroid
;
942 key
->ps
.prolog
.force_linear_sample_interp
=
943 sel
->info
.uses_linear_center
||
944 sel
->info
.uses_linear_centroid
;
945 } else if (rs
->multisample_enable
&&
946 sctx
->framebuffer
.nr_samples
> 1) {
947 key
->ps
.prolog
.bc_optimize_for_persp
=
948 sel
->info
.uses_persp_center
&&
949 sel
->info
.uses_persp_centroid
;
950 key
->ps
.prolog
.bc_optimize_for_linear
=
951 sel
->info
.uses_linear_center
&&
952 sel
->info
.uses_linear_centroid
;
954 /* Make sure SPI doesn't compute more than 1 pair
955 * of (i,j), which is the optimization here. */
956 key
->ps
.prolog
.force_persp_center_interp
=
957 sel
->info
.uses_persp_center
+
958 sel
->info
.uses_persp_centroid
+
959 sel
->info
.uses_persp_sample
> 1;
961 key
->ps
.prolog
.force_linear_center_interp
=
962 sel
->info
.uses_linear_center
+
963 sel
->info
.uses_linear_centroid
+
964 sel
->info
.uses_linear_sample
> 1;
968 key
->ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
976 /* Select the hw shader variant depending on the current state. */
977 static int si_shader_select_with_key(struct pipe_context
*ctx
,
978 struct si_shader_ctx_state
*state
,
979 union si_shader_key
*key
)
981 struct si_context
*sctx
= (struct si_context
*)ctx
;
982 struct si_shader_selector
*sel
= state
->cso
;
983 struct si_shader
*current
= state
->current
;
984 struct si_shader
*iter
, *shader
= NULL
;
987 /* Check if we don't need to change anything.
988 * This path is also used for most shaders that don't need multiple
989 * variants, it will cost just a computation of the key and this
991 if (likely(current
&& memcmp(¤t
->key
, key
, sizeof(*key
)) == 0))
994 pipe_mutex_lock(sel
->mutex
);
996 /* Find the shader variant. */
997 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
998 /* Don't check the "current" shader. We checked it above. */
999 if (current
!= iter
&&
1000 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
1001 state
->current
= iter
;
1002 pipe_mutex_unlock(sel
->mutex
);
1007 /* Build a new shader. */
1008 shader
= CALLOC_STRUCT(si_shader
);
1010 pipe_mutex_unlock(sel
->mutex
);
1013 shader
->selector
= sel
;
1016 r
= si_shader_create(sctx
->screen
, sctx
->tm
, shader
, &sctx
->b
.debug
);
1018 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1021 pipe_mutex_unlock(sel
->mutex
);
1024 si_shader_init_pm4_state(sctx
->screen
, shader
);
1026 if (!sel
->last_variant
) {
1027 sel
->first_variant
= shader
;
1028 sel
->last_variant
= shader
;
1030 sel
->last_variant
->next_variant
= shader
;
1031 sel
->last_variant
= shader
;
1033 state
->current
= shader
;
1034 pipe_mutex_unlock(sel
->mutex
);
1038 static int si_shader_select(struct pipe_context
*ctx
,
1039 struct si_shader_ctx_state
*state
)
1041 union si_shader_key key
;
1043 si_shader_selector_key(ctx
, state
->cso
, &key
);
1044 return si_shader_select_with_key(ctx
, state
, &key
);
1047 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
1048 union si_shader_key
*key
)
1050 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
1052 switch (info
->processor
) {
1053 case PIPE_SHADER_VERTEX
:
1054 switch (next_shader
) {
1055 case PIPE_SHADER_GEOMETRY
:
1058 case PIPE_SHADER_TESS_CTRL
:
1059 case PIPE_SHADER_TESS_EVAL
:
1065 case PIPE_SHADER_TESS_EVAL
:
1066 if (next_shader
== PIPE_SHADER_GEOMETRY
)
1072 static void *si_create_shader_selector(struct pipe_context
*ctx
,
1073 const struct pipe_shader_state
*state
)
1075 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
1076 struct si_context
*sctx
= (struct si_context
*)ctx
;
1077 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
1083 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
1089 sel
->so
= state
->stream_output
;
1090 tgsi_scan_shader(state
->tokens
, &sel
->info
);
1091 sel
->type
= sel
->info
.processor
;
1092 p_atomic_inc(&sscreen
->b
.num_shaders_created
);
1094 /* Set which opcode uses which (i,j) pair. */
1095 if (sel
->info
.uses_persp_opcode_interp_centroid
)
1096 sel
->info
.uses_persp_centroid
= true;
1098 if (sel
->info
.uses_linear_opcode_interp_centroid
)
1099 sel
->info
.uses_linear_centroid
= true;
1101 if (sel
->info
.uses_persp_opcode_interp_offset
||
1102 sel
->info
.uses_persp_opcode_interp_sample
)
1103 sel
->info
.uses_persp_center
= true;
1105 if (sel
->info
.uses_linear_opcode_interp_offset
||
1106 sel
->info
.uses_linear_opcode_interp_sample
)
1107 sel
->info
.uses_linear_center
= true;
1109 switch (sel
->type
) {
1110 case PIPE_SHADER_GEOMETRY
:
1111 sel
->gs_output_prim
=
1112 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
1113 sel
->gs_max_out_vertices
=
1114 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
1115 sel
->gs_num_invocations
=
1116 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
1117 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
1118 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
1119 sel
->gs_max_out_vertices
;
1121 sel
->max_gs_stream
= 0;
1122 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
1123 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
1124 sel
->so
.output
[i
].stream
);
1126 sel
->gs_input_verts_per_prim
=
1127 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
1130 case PIPE_SHADER_TESS_CTRL
:
1131 /* Always reserve space for these. */
1132 sel
->patch_outputs_written
|=
1133 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER
, 0)) |
1134 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER
, 0));
1136 case PIPE_SHADER_VERTEX
:
1137 case PIPE_SHADER_TESS_EVAL
:
1138 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
1139 unsigned name
= sel
->info
.output_semantic_name
[i
];
1140 unsigned index
= sel
->info
.output_semantic_index
[i
];
1143 case TGSI_SEMANTIC_TESSINNER
:
1144 case TGSI_SEMANTIC_TESSOUTER
:
1145 case TGSI_SEMANTIC_PATCH
:
1146 sel
->patch_outputs_written
|=
1147 1llu << si_shader_io_get_unique_index(name
, index
);
1150 sel
->outputs_written
|=
1151 1llu << si_shader_io_get_unique_index(name
, index
);
1154 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
1157 case PIPE_SHADER_FRAGMENT
:
1158 for (i
= 0; i
< 8; i
++)
1159 if (sel
->info
.colors_written
& (1 << i
))
1160 sel
->colors_written_4bit
|= 0xf << (4 * i
);
1162 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
1163 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
1164 int index
= sel
->info
.input_semantic_index
[i
];
1165 sel
->color_attr_index
[index
] = i
;
1171 /* DB_SHADER_CONTROL */
1172 sel
->db_shader_control
=
1173 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
1174 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
1175 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
1176 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
1178 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
1179 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
1180 sel
->db_shader_control
|=
1181 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
1183 case TGSI_FS_DEPTH_LAYOUT_LESS
:
1184 sel
->db_shader_control
|=
1185 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
1189 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
])
1190 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1);
1192 if (sel
->info
.writes_memory
)
1193 sel
->db_shader_control
|= S_02880C_EXEC_ON_HIER_FAIL(1) |
1194 S_02880C_EXEC_ON_NOOP(1);
1196 /* Compile the main shader part for use with a prolog and/or epilog. */
1197 if (sel
->type
!= PIPE_SHADER_GEOMETRY
&&
1198 !sscreen
->use_monolithic_shaders
) {
1199 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
1205 shader
->selector
= sel
;
1206 si_parse_next_shader_property(&sel
->info
, &shader
->key
);
1208 tgsi_binary
= si_get_tgsi_binary(sel
);
1210 /* Try to load the shader from the shader cache. */
1211 pipe_mutex_lock(sscreen
->shader_cache_mutex
);
1214 si_shader_cache_load_shader(sscreen
, tgsi_binary
, shader
)) {
1217 /* Compile the shader if it hasn't been loaded from the cache. */
1218 if (si_compile_tgsi_shader(sscreen
, sctx
->tm
, shader
, false,
1219 &sctx
->b
.debug
) != 0) {
1222 pipe_mutex_unlock(sscreen
->shader_cache_mutex
);
1227 !si_shader_cache_insert_shader(sscreen
, tgsi_binary
, shader
))
1230 pipe_mutex_unlock(sscreen
->shader_cache_mutex
);
1232 sel
->main_shader_part
= shader
;
1235 /* Pre-compilation. */
1236 if (sel
->type
== PIPE_SHADER_GEOMETRY
||
1237 sscreen
->b
.debug_flags
& DBG_PRECOMPILE
) {
1238 struct si_shader_ctx_state state
= {sel
};
1239 union si_shader_key key
;
1241 memset(&key
, 0, sizeof(key
));
1242 si_parse_next_shader_property(&sel
->info
, &key
);
1244 /* Set reasonable defaults, so that the shader key doesn't
1245 * cause any code to be eliminated.
1247 switch (sel
->type
) {
1248 case PIPE_SHADER_TESS_CTRL
:
1249 key
.tcs
.epilog
.prim_mode
= PIPE_PRIM_TRIANGLES
;
1251 case PIPE_SHADER_FRAGMENT
:
1252 key
.ps
.epilog
.alpha_func
= PIPE_FUNC_ALWAYS
;
1253 for (i
= 0; i
< 8; i
++)
1254 if (sel
->info
.colors_written
& (1 << i
))
1255 key
.ps
.epilog
.spi_shader_col_format
|=
1256 V_028710_SPI_SHADER_FP16_ABGR
<< (i
* 4);
1260 if (si_shader_select_with_key(ctx
, &state
, &key
))
1264 pipe_mutex_init(sel
->mutex
);
1268 fprintf(stderr
, "radeonsi: can't create a shader\n");
1269 tgsi_free_tokens(sel
->tokens
);
1274 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
1276 struct si_context
*sctx
= (struct si_context
*)ctx
;
1277 struct si_shader_selector
*sel
= state
;
1279 if (sctx
->vs_shader
.cso
== sel
)
1282 sctx
->vs_shader
.cso
= sel
;
1283 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
1284 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
1285 r600_update_vs_writes_viewport_index(&sctx
->b
, si_get_vs_info(sctx
));
1288 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
1290 struct si_context
*sctx
= (struct si_context
*)ctx
;
1291 struct si_shader_selector
*sel
= state
;
1292 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
1294 if (sctx
->gs_shader
.cso
== sel
)
1297 sctx
->gs_shader
.cso
= sel
;
1298 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
1299 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
1300 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
1303 si_shader_change_notify(sctx
);
1304 r600_update_vs_writes_viewport_index(&sctx
->b
, si_get_vs_info(sctx
));
1307 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
1309 struct si_context
*sctx
= (struct si_context
*)ctx
;
1310 struct si_shader_selector
*sel
= state
;
1311 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
1313 if (sctx
->tcs_shader
.cso
== sel
)
1316 sctx
->tcs_shader
.cso
= sel
;
1317 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
1320 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
1323 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
1325 struct si_context
*sctx
= (struct si_context
*)ctx
;
1326 struct si_shader_selector
*sel
= state
;
1327 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
1329 if (sctx
->tes_shader
.cso
== sel
)
1332 sctx
->tes_shader
.cso
= sel
;
1333 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
1334 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
1335 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
1337 if (enable_changed
) {
1338 si_shader_change_notify(sctx
);
1339 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
1341 r600_update_vs_writes_viewport_index(&sctx
->b
, si_get_vs_info(sctx
));
1344 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
1346 struct si_context
*sctx
= (struct si_context
*)ctx
;
1347 struct si_shader_selector
*sel
= state
;
1349 /* skip if supplied shader is one already in use */
1350 if (sctx
->ps_shader
.cso
== sel
)
1353 sctx
->ps_shader
.cso
= sel
;
1354 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
1355 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
1358 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
1361 switch (shader
->selector
->type
) {
1362 case PIPE_SHADER_VERTEX
:
1363 if (shader
->key
.vs
.as_ls
)
1364 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
1365 else if (shader
->key
.vs
.as_es
)
1366 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
1368 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
1370 case PIPE_SHADER_TESS_CTRL
:
1371 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
1373 case PIPE_SHADER_TESS_EVAL
:
1374 if (shader
->key
.tes
.as_es
)
1375 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
1377 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
1379 case PIPE_SHADER_GEOMETRY
:
1380 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
1381 si_pm4_delete_state(sctx
, vs
, shader
->gs_copy_shader
->pm4
);
1383 case PIPE_SHADER_FRAGMENT
:
1384 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
1389 si_shader_destroy(shader
);
1393 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
1395 struct si_context
*sctx
= (struct si_context
*)ctx
;
1396 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
1397 struct si_shader
*p
= sel
->first_variant
, *c
;
1398 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
1399 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
1400 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
1401 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
1402 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
1403 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
1406 if (current_shader
[sel
->type
]->cso
== sel
) {
1407 current_shader
[sel
->type
]->cso
= NULL
;
1408 current_shader
[sel
->type
]->current
= NULL
;
1412 c
= p
->next_variant
;
1413 si_delete_shader(sctx
, p
);
1417 if (sel
->main_shader_part
)
1418 si_delete_shader(sctx
, sel
->main_shader_part
);
1420 pipe_mutex_destroy(sel
->mutex
);
1425 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
1426 struct si_shader
*vs
, unsigned name
,
1427 unsigned index
, unsigned interpolate
)
1429 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
1430 unsigned j
, ps_input_cntl
= 0;
1432 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
1433 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
))
1434 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
1436 if (name
== TGSI_SEMANTIC_PCOORD
||
1437 (name
== TGSI_SEMANTIC_TEXCOORD
&&
1438 sctx
->sprite_coord_enable
& (1 << index
))) {
1439 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
1442 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
1443 if (name
== vsinfo
->output_semantic_name
[j
] &&
1444 index
== vsinfo
->output_semantic_index
[j
]) {
1445 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[j
]);
1450 if (name
== TGSI_SEMANTIC_PRIMID
)
1451 /* PrimID is written after the last output. */
1452 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
1453 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
1454 /* No corresponding output found, load defaults into input.
1455 * Don't set any other bits.
1456 * (FLAT_SHADE=1 completely changes behavior) */
1457 ps_input_cntl
= S_028644_OFFSET(0x20);
1458 /* D3D 9 behaviour. GL is undefined */
1459 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
1460 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
1462 return ps_input_cntl
;
1465 static void si_emit_spi_map(struct si_context
*sctx
, struct r600_atom
*atom
)
1467 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1468 struct si_shader
*ps
= sctx
->ps_shader
.current
;
1469 struct si_shader
*vs
= si_get_vs_state(sctx
);
1470 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
1471 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
1473 if (!ps
|| !ps
->selector
->info
.num_inputs
)
1476 num_interp
= si_get_ps_num_interp(ps
);
1477 assert(num_interp
> 0);
1478 radeon_set_context_reg_seq(cs
, R_028644_SPI_PS_INPUT_CNTL_0
, num_interp
);
1480 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
1481 unsigned name
= psinfo
->input_semantic_name
[i
];
1482 unsigned index
= psinfo
->input_semantic_index
[i
];
1483 unsigned interpolate
= psinfo
->input_interpolate
[i
];
1485 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, name
, index
,
1489 if (name
== TGSI_SEMANTIC_COLOR
) {
1490 assert(index
< ARRAY_SIZE(bcol_interp
));
1491 bcol_interp
[index
] = interpolate
;
1495 if (ps
->key
.ps
.prolog
.color_two_side
) {
1496 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
1498 for (i
= 0; i
< 2; i
++) {
1499 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
1502 radeon_emit(cs
, si_get_ps_input_cntl(sctx
, vs
, bcol
,
1503 i
, bcol_interp
[i
]));
1507 assert(num_interp
== num_written
);
1511 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
1513 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
1515 if (sctx
->init_config_has_vgt_flush
)
1518 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
1519 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
1520 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
1521 si_pm4_cmd_end(sctx
->init_config
, false);
1522 sctx
->init_config_has_vgt_flush
= true;
1525 /* Initialize state related to ESGS / GSVS ring buffers */
1526 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
1528 struct si_shader_selector
*es
=
1529 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
1530 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
1531 struct si_pm4_state
*pm4
;
1533 /* Chip constants. */
1534 unsigned num_se
= sctx
->screen
->b
.info
.max_se
;
1535 unsigned wave_size
= 64;
1536 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1537 unsigned gs_vertex_reuse
= 16 * num_se
; /* GS_VERTEX_REUSE register (per SE) */
1538 unsigned alignment
= 256 * num_se
;
1539 /* The maximum size is 63.999 MB per SE. */
1540 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1542 /* Calculate the minimum size. */
1543 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
1544 wave_size
, alignment
);
1546 /* These are recommended sizes, not minimum sizes. */
1547 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1548 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
1549 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1550 gs
->max_gsvs_emit_size
* (gs
->max_gs_stream
+ 1);
1552 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1553 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1554 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1556 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1557 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1559 /* Some rings don't have to be allocated if shaders don't use them.
1560 * (e.g. no varyings between ES and GS or GS and VS)
1562 bool update_esgs
= esgs_ring_size
&&
1563 (!sctx
->esgs_ring
||
1564 sctx
->esgs_ring
->width0
< esgs_ring_size
);
1565 bool update_gsvs
= gsvs_ring_size
&&
1566 (!sctx
->gsvs_ring
||
1567 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
1569 if (!update_esgs
&& !update_gsvs
)
1573 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
1574 sctx
->esgs_ring
= pipe_buffer_create(sctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1577 if (!sctx
->esgs_ring
)
1582 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
1583 sctx
->gsvs_ring
= pipe_buffer_create(sctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1586 if (!sctx
->gsvs_ring
)
1590 /* Create the "init_config_gs_rings" state. */
1591 pm4
= CALLOC_STRUCT(si_pm4_state
);
1595 if (sctx
->b
.chip_class
>= CIK
) {
1596 if (sctx
->esgs_ring
)
1597 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
1598 sctx
->esgs_ring
->width0
/ 256);
1599 if (sctx
->gsvs_ring
)
1600 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
1601 sctx
->gsvs_ring
->width0
/ 256);
1603 if (sctx
->esgs_ring
)
1604 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
1605 sctx
->esgs_ring
->width0
/ 256);
1606 if (sctx
->gsvs_ring
)
1607 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
1608 sctx
->gsvs_ring
->width0
/ 256);
1611 /* Set the state. */
1612 if (sctx
->init_config_gs_rings
)
1613 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
1614 sctx
->init_config_gs_rings
= pm4
;
1616 if (!sctx
->init_config_has_vgt_flush
) {
1617 si_init_config_add_vgt_flush(sctx
);
1618 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
1621 /* Flush the context to re-emit both init_config states. */
1622 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
1623 si_context_gfx_flush(sctx
, RADEON_FLUSH_ASYNC
, NULL
);
1625 /* Set ring bindings. */
1626 if (sctx
->esgs_ring
) {
1627 si_set_ring_buffer(&sctx
->b
.b
, SI_ES_RING_ESGS
,
1628 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
1629 true, true, 4, 64, 0);
1630 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_ESGS
,
1631 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
1632 false, false, 0, 0, 0);
1634 if (sctx
->gsvs_ring
)
1635 si_set_ring_buffer(&sctx
->b
.b
, SI_VS_RING_GSVS
,
1636 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
1637 false, false, 0, 0, 0);
1641 static void si_update_gsvs_ring_bindings(struct si_context
*sctx
)
1643 unsigned gsvs_itemsize
= sctx
->gs_shader
.cso
->max_gsvs_emit_size
;
1646 if (!sctx
->gsvs_ring
|| gsvs_itemsize
== sctx
->last_gsvs_itemsize
)
1649 sctx
->last_gsvs_itemsize
= gsvs_itemsize
;
1651 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_GSVS0
,
1652 sctx
->gsvs_ring
, gsvs_itemsize
,
1653 64, true, true, 4, 16, 0);
1655 offset
= gsvs_itemsize
* 64;
1656 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_GSVS1
,
1657 sctx
->gsvs_ring
, gsvs_itemsize
,
1658 64, true, true, 4, 16, offset
);
1660 offset
= (gsvs_itemsize
* 2) * 64;
1661 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_GSVS2
,
1662 sctx
->gsvs_ring
, gsvs_itemsize
,
1663 64, true, true, 4, 16, offset
);
1665 offset
= (gsvs_itemsize
* 3) * 64;
1666 si_set_ring_buffer(&sctx
->b
.b
, SI_GS_RING_GSVS3
,
1667 sctx
->gsvs_ring
, gsvs_itemsize
,
1668 64, true, true, 4, 16, offset
);
1672 * @returns 1 if \p sel has been updated to use a new scratch buffer
1674 * < 0 if there was a failure
1676 static int si_update_scratch_buffer(struct si_context
*sctx
,
1677 struct si_shader
*shader
)
1679 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
1685 /* This shader doesn't need a scratch buffer */
1686 if (shader
->config
.scratch_bytes_per_wave
== 0)
1689 /* This shader is already configured to use the current
1690 * scratch buffer. */
1691 if (shader
->scratch_bo
== sctx
->scratch_buffer
)
1694 assert(sctx
->scratch_buffer
);
1696 si_shader_apply_scratch_relocs(sctx
, shader
, &shader
->config
, scratch_va
);
1698 /* Replace the shader bo with a new bo that has the relocs applied. */
1699 r
= si_shader_binary_upload(sctx
->screen
, shader
);
1703 /* Update the shader state to use the new shader bo. */
1704 si_shader_init_pm4_state(sctx
->screen
, shader
);
1706 r600_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
1711 static unsigned si_get_current_scratch_buffer_size(struct si_context
*sctx
)
1713 return sctx
->scratch_buffer
? sctx
->scratch_buffer
->b
.b
.width0
: 0;
1716 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
1718 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
1721 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context
*sctx
)
1725 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
1726 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
1727 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
1728 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tcs_shader
.current
));
1729 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
1733 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
1735 unsigned current_scratch_buffer_size
=
1736 si_get_current_scratch_buffer_size(sctx
);
1737 unsigned scratch_bytes_per_wave
=
1738 si_get_max_scratch_bytes_per_wave(sctx
);
1739 unsigned scratch_needed_size
= scratch_bytes_per_wave
*
1740 sctx
->scratch_waves
;
1741 unsigned spi_tmpring_size
;
1744 if (scratch_needed_size
> 0) {
1745 if (scratch_needed_size
> current_scratch_buffer_size
) {
1746 /* Create a bigger scratch buffer */
1747 r600_resource_reference(&sctx
->scratch_buffer
, NULL
);
1749 sctx
->scratch_buffer
=
1750 si_resource_create_custom(&sctx
->screen
->b
.b
,
1751 PIPE_USAGE_DEFAULT
, scratch_needed_size
);
1752 if (!sctx
->scratch_buffer
)
1754 sctx
->emit_scratch_reloc
= true;
1757 /* Update the shaders, so they are using the latest scratch. The
1758 * scratch buffer may have been changed since these shaders were
1759 * last used, so we still need to try to update them, even if
1760 * they require scratch buffers smaller than the current size.
1762 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
1766 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
1768 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
1772 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
1774 r
= si_update_scratch_buffer(sctx
, sctx
->tcs_shader
.current
);
1778 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
1780 /* VS can be bound as LS, ES, or VS. */
1781 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
1785 if (sctx
->tes_shader
.current
)
1786 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
1787 else if (sctx
->gs_shader
.current
)
1788 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
1790 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
1793 /* TES can be bound as ES or VS. */
1794 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
1798 if (sctx
->gs_shader
.current
)
1799 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
1801 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
1805 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
1806 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
1807 "scratch size should already be aligned correctly.");
1809 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
1810 S_0286E8_WAVESIZE(scratch_bytes_per_wave
>> 10);
1811 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
1812 sctx
->spi_tmpring_size
= spi_tmpring_size
;
1813 sctx
->emit_scratch_reloc
= true;
1818 static void si_init_tess_factor_ring(struct si_context
*sctx
)
1820 bool double_offchip_buffers
= sctx
->b
.chip_class
>= CIK
;
1821 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
1822 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
1823 sctx
->screen
->b
.info
.max_se
;
1824 unsigned offchip_granularity
;
1826 switch (sctx
->screen
->tess_offchip_block_dw_size
) {
1831 offchip_granularity
= V_03093C_X_8K_DWORDS
;
1834 offchip_granularity
= V_03093C_X_4K_DWORDS
;
1838 switch (sctx
->b
.chip_class
) {
1840 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
1843 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
1847 max_offchip_buffers
= MIN2(max_offchip_buffers
, 512);
1851 assert(!sctx
->tf_ring
);
1852 sctx
->tf_ring
= pipe_buffer_create(sctx
->b
.b
.screen
, PIPE_BIND_CUSTOM
,
1854 32768 * sctx
->screen
->b
.info
.max_se
);
1858 assert(((sctx
->tf_ring
->width0
/ 4) & C_030938_SIZE
) == 0);
1860 sctx
->tess_offchip_ring
= pipe_buffer_create(sctx
->b
.b
.screen
,
1863 max_offchip_buffers
*
1864 sctx
->screen
->tess_offchip_block_dw_size
* 4);
1865 if (!sctx
->tess_offchip_ring
)
1868 si_init_config_add_vgt_flush(sctx
);
1870 /* Append these registers to the init config state. */
1871 if (sctx
->b
.chip_class
>= CIK
) {
1872 if (sctx
->b
.chip_class
>= VI
)
1873 --max_offchip_buffers
;
1875 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
1876 S_030938_SIZE(sctx
->tf_ring
->width0
/ 4));
1877 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
1878 r600_resource(sctx
->tf_ring
)->gpu_address
>> 8);
1879 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
1880 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
1881 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
));
1883 assert(offchip_granularity
== V_03093C_X_8K_DWORDS
);
1884 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
1885 S_008988_SIZE(sctx
->tf_ring
->width0
/ 4));
1886 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
1887 r600_resource(sctx
->tf_ring
)->gpu_address
>> 8);
1888 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
1889 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
));
1892 /* Flush the context to re-emit the init_config state.
1893 * This is done only once in a lifetime of a context.
1895 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
1896 sctx
->b
.initial_gfx_cs_size
= 0; /* force flush */
1897 si_context_gfx_flush(sctx
, RADEON_FLUSH_ASYNC
, NULL
);
1899 si_set_ring_buffer(&sctx
->b
.b
, SI_HS_RING_TESS_FACTOR
, sctx
->tf_ring
,
1900 0, sctx
->tf_ring
->width0
, false, false, 0, 0, 0);
1902 si_set_ring_buffer(&sctx
->b
.b
, SI_HS_RING_TESS_OFFCHIP
,
1903 sctx
->tess_offchip_ring
, 0,
1904 sctx
->tess_offchip_ring
->width0
, false, false, 0, 0, 0);
1908 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
1909 * VS passes its outputs to TES directly, so the fixed-function shader only
1910 * has to write TESSOUTER and TESSINNER.
1912 static void si_generate_fixed_func_tcs(struct si_context
*sctx
)
1914 struct ureg_src outer
, inner
;
1915 struct ureg_dst tessouter
, tessinner
;
1916 struct ureg_program
*ureg
= ureg_create(PIPE_SHADER_TESS_CTRL
);
1919 return; /* if we get here, we're screwed */
1921 assert(!sctx
->fixed_func_tcs_shader
.cso
);
1923 outer
= ureg_DECL_system_value(ureg
,
1924 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI
, 0);
1925 inner
= ureg_DECL_system_value(ureg
,
1926 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI
, 0);
1928 tessouter
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSOUTER
, 0);
1929 tessinner
= ureg_DECL_output(ureg
, TGSI_SEMANTIC_TESSINNER
, 0);
1931 ureg_MOV(ureg
, tessouter
, outer
);
1932 ureg_MOV(ureg
, tessinner
, inner
);
1935 sctx
->fixed_func_tcs_shader
.cso
=
1936 ureg_create_shader_and_destroy(ureg
, &sctx
->b
.b
);
1939 static void si_update_vgt_shader_config(struct si_context
*sctx
)
1941 /* Calculate the index of the config.
1942 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
1943 unsigned index
= 2*!!sctx
->tes_shader
.cso
+ !!sctx
->gs_shader
.cso
;
1944 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[index
];
1947 uint32_t stages
= 0;
1949 *pm4
= CALLOC_STRUCT(si_pm4_state
);
1951 if (sctx
->tes_shader
.cso
) {
1952 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
1953 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
1955 if (sctx
->gs_shader
.cso
)
1956 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
1958 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
1960 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
1961 } else if (sctx
->gs_shader
.cso
) {
1962 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
1964 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
1967 si_pm4_set_reg(*pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
1969 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
1972 static void si_update_so(struct si_context
*sctx
, struct si_shader_selector
*shader
)
1974 struct pipe_stream_output_info
*so
= &shader
->so
;
1975 uint32_t enabled_stream_buffers_mask
= 0;
1978 for (i
= 0; i
< so
->num_outputs
; i
++)
1979 enabled_stream_buffers_mask
|= (1 << so
->output
[i
].output_buffer
) << (so
->output
[i
].stream
* 4);
1980 sctx
->b
.streamout
.enabled_stream_buffers_mask
= enabled_stream_buffers_mask
;
1981 sctx
->b
.streamout
.stride_in_dw
= shader
->so
.stride
;
1984 bool si_update_shaders(struct si_context
*sctx
)
1986 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
1987 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1990 /* Update stages before GS. */
1991 if (sctx
->tes_shader
.cso
) {
1992 if (!sctx
->tf_ring
) {
1993 si_init_tess_factor_ring(sctx
);
1999 r
= si_shader_select(ctx
, &sctx
->vs_shader
);
2002 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
2004 if (sctx
->tcs_shader
.cso
) {
2005 r
= si_shader_select(ctx
, &sctx
->tcs_shader
);
2008 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
2010 if (!sctx
->fixed_func_tcs_shader
.cso
) {
2011 si_generate_fixed_func_tcs(sctx
);
2012 if (!sctx
->fixed_func_tcs_shader
.cso
)
2016 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
);
2019 si_pm4_bind_state(sctx
, hs
,
2020 sctx
->fixed_func_tcs_shader
.current
->pm4
);
2023 r
= si_shader_select(ctx
, &sctx
->tes_shader
);
2027 if (sctx
->gs_shader
.cso
) {
2029 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
2032 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
2033 si_update_so(sctx
, sctx
->tes_shader
.cso
);
2035 } else if (sctx
->gs_shader
.cso
) {
2037 r
= si_shader_select(ctx
, &sctx
->vs_shader
);
2040 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
2043 r
= si_shader_select(ctx
, &sctx
->vs_shader
);
2046 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
2047 si_update_so(sctx
, sctx
->vs_shader
.cso
);
2051 if (sctx
->gs_shader
.cso
) {
2052 r
= si_shader_select(ctx
, &sctx
->gs_shader
);
2055 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
2056 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.current
->gs_copy_shader
->pm4
);
2057 si_update_so(sctx
, sctx
->gs_shader
.cso
);
2059 if (!si_update_gs_ring_buffers(sctx
))
2062 si_update_gsvs_ring_bindings(sctx
);
2064 si_pm4_bind_state(sctx
, gs
, NULL
);
2065 si_pm4_bind_state(sctx
, es
, NULL
);
2068 si_update_vgt_shader_config(sctx
);
2070 if (sctx
->ps_shader
.cso
) {
2071 unsigned db_shader_control
;
2073 r
= si_shader_select(ctx
, &sctx
->ps_shader
);
2076 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
2079 sctx
->ps_shader
.cso
->db_shader_control
|
2080 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
) |
2081 S_02880C_Z_ORDER(sctx
->ps_shader
.current
->z_order
);
2083 if (si_pm4_state_changed(sctx
, ps
) || si_pm4_state_changed(sctx
, vs
) ||
2084 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
2085 sctx
->flatshade
!= rs
->flatshade
) {
2086 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
2087 sctx
->flatshade
= rs
->flatshade
;
2088 si_mark_atom_dirty(sctx
, &sctx
->spi_map
);
2091 if (sctx
->b
.family
== CHIP_STONEY
&& si_pm4_state_changed(sctx
, ps
))
2092 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
2094 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
2095 sctx
->ps_db_shader_control
= db_shader_control
;
2096 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
2099 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.ps
.epilog
.poly_line_smoothing
) {
2100 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.ps
.epilog
.poly_line_smoothing
;
2101 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2103 if (sctx
->b
.chip_class
== SI
)
2104 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
2108 if (si_pm4_state_changed(sctx
, ls
) ||
2109 si_pm4_state_changed(sctx
, hs
) ||
2110 si_pm4_state_changed(sctx
, es
) ||
2111 si_pm4_state_changed(sctx
, gs
) ||
2112 si_pm4_state_changed(sctx
, vs
) ||
2113 si_pm4_state_changed(sctx
, ps
)) {
2114 if (!si_update_spi_tmpring_size(sctx
))
2120 void si_init_shader_functions(struct si_context
*sctx
)
2122 si_init_atom(sctx
, &sctx
->spi_map
, &sctx
->atoms
.s
.spi_map
, si_emit_spi_map
);
2124 sctx
->b
.b
.create_vs_state
= si_create_shader_selector
;
2125 sctx
->b
.b
.create_tcs_state
= si_create_shader_selector
;
2126 sctx
->b
.b
.create_tes_state
= si_create_shader_selector
;
2127 sctx
->b
.b
.create_gs_state
= si_create_shader_selector
;
2128 sctx
->b
.b
.create_fs_state
= si_create_shader_selector
;
2130 sctx
->b
.b
.bind_vs_state
= si_bind_vs_shader
;
2131 sctx
->b
.b
.bind_tcs_state
= si_bind_tcs_shader
;
2132 sctx
->b
.b
.bind_tes_state
= si_bind_tes_shader
;
2133 sctx
->b
.b
.bind_gs_state
= si_bind_gs_shader
;
2134 sctx
->b
.b
.bind_fs_state
= si_bind_ps_shader
;
2136 sctx
->b
.b
.delete_vs_state
= si_delete_shader_selector
;
2137 sctx
->b
.b
.delete_tcs_state
= si_delete_shader_selector
;
2138 sctx
->b
.b
.delete_tes_state
= si_delete_shader_selector
;
2139 sctx
->b
.b
.delete_gs_state
= si_delete_shader_selector
;
2140 sctx
->b
.b
.delete_fs_state
= si_delete_shader_selector
;