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radeonsi:optimizing SET_CONTEXT_REG for shaders PS
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
45 * size as integer.
46 */
47 void *si_get_ir_binary(struct si_shader_selector *sel)
48 {
49 struct blob blob;
50 unsigned ir_size;
51 void *ir_binary;
52
53 if (sel->tokens) {
54 ir_binary = sel->tokens;
55 ir_size = tgsi_num_tokens(sel->tokens) *
56 sizeof(struct tgsi_token);
57 } else {
58 assert(sel->nir);
59
60 blob_init(&blob);
61 nir_serialize(&blob, sel->nir);
62 ir_binary = blob.data;
63 ir_size = blob.size;
64 }
65
66 unsigned size = 4 + ir_size + sizeof(sel->so);
67 char *result = (char*)MALLOC(size);
68 if (!result)
69 return NULL;
70
71 *((uint32_t*)result) = size;
72 memcpy(result + 4, ir_binary, ir_size);
73 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
74
75 if (sel->nir)
76 blob_finish(&blob);
77
78 return result;
79 }
80
81 /** Copy "data" to "ptr" and return the next dword following copied data. */
82 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
83 {
84 /* data may be NULL if size == 0 */
85 if (size)
86 memcpy(ptr, data, size);
87 ptr += DIV_ROUND_UP(size, 4);
88 return ptr;
89 }
90
91 /** Read data from "ptr". Return the next dword following the data. */
92 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
93 {
94 memcpy(data, ptr, size);
95 ptr += DIV_ROUND_UP(size, 4);
96 return ptr;
97 }
98
99 /**
100 * Write the size as uint followed by the data. Return the next dword
101 * following the copied data.
102 */
103 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
104 {
105 *ptr++ = size;
106 return write_data(ptr, data, size);
107 }
108
109 /**
110 * Read the size as uint followed by the data. Return both via parameters.
111 * Return the next dword following the data.
112 */
113 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
114 {
115 *size = *ptr++;
116 assert(*data == NULL);
117 if (!*size)
118 return ptr;
119 *data = malloc(*size);
120 return read_data(ptr, *data, *size);
121 }
122
123 /**
124 * Return the shader binary in a buffer. The first 4 bytes contain its size
125 * as integer.
126 */
127 static void *si_get_shader_binary(struct si_shader *shader)
128 {
129 /* There is always a size of data followed by the data itself. */
130 unsigned relocs_size = shader->binary.reloc_count *
131 sizeof(shader->binary.relocs[0]);
132 unsigned disasm_size = shader->binary.disasm_string ?
133 strlen(shader->binary.disasm_string) + 1 : 0;
134 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
135 strlen(shader->binary.llvm_ir_string) + 1 : 0;
136 unsigned size =
137 4 + /* total size */
138 4 + /* CRC32 of the data below */
139 align(sizeof(shader->config), 4) +
140 align(sizeof(shader->info), 4) +
141 4 + align(shader->binary.code_size, 4) +
142 4 + align(shader->binary.rodata_size, 4) +
143 4 + align(relocs_size, 4) +
144 4 + align(disasm_size, 4) +
145 4 + align(llvm_ir_size, 4);
146 void *buffer = CALLOC(1, size);
147 uint32_t *ptr = (uint32_t*)buffer;
148
149 if (!buffer)
150 return NULL;
151
152 *ptr++ = size;
153 ptr++; /* CRC32 is calculated at the end. */
154
155 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
156 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
157 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
158 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
159 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
160 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
161 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
162 assert((char *)ptr - (char *)buffer == size);
163
164 /* Compute CRC32. */
165 ptr = (uint32_t*)buffer;
166 ptr++;
167 *ptr = util_hash_crc32(ptr + 1, size - 8);
168
169 return buffer;
170 }
171
172 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
173 {
174 uint32_t *ptr = (uint32_t*)binary;
175 uint32_t size = *ptr++;
176 uint32_t crc32 = *ptr++;
177 unsigned chunk_size;
178
179 if (util_hash_crc32(ptr, size - 8) != crc32) {
180 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
181 return false;
182 }
183
184 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
185 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
186 ptr = read_chunk(ptr, (void**)&shader->binary.code,
187 &shader->binary.code_size);
188 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
189 &shader->binary.rodata_size);
190 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
191 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
192 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
193 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
194
195 return true;
196 }
197
198 /**
199 * Insert a shader into the cache. It's assumed the shader is not in the cache.
200 * Use si_shader_cache_load_shader before calling this.
201 *
202 * Returns false on failure, in which case the ir_binary should be freed.
203 */
204 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
205 struct si_shader *shader,
206 bool insert_into_disk_cache)
207 {
208 void *hw_binary;
209 struct hash_entry *entry;
210 uint8_t key[CACHE_KEY_SIZE];
211
212 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
213 if (entry)
214 return false; /* already added */
215
216 hw_binary = si_get_shader_binary(shader);
217 if (!hw_binary)
218 return false;
219
220 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
221 hw_binary) == NULL) {
222 FREE(hw_binary);
223 return false;
224 }
225
226 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
227 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
228 *((uint32_t *)ir_binary), key);
229 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
230 *((uint32_t *) hw_binary), NULL);
231 }
232
233 return true;
234 }
235
236 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
237 struct si_shader *shader)
238 {
239 struct hash_entry *entry =
240 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
241 if (!entry) {
242 if (sscreen->disk_shader_cache) {
243 unsigned char sha1[CACHE_KEY_SIZE];
244 size_t tg_size = *((uint32_t *) ir_binary);
245
246 disk_cache_compute_key(sscreen->disk_shader_cache,
247 ir_binary, tg_size, sha1);
248
249 size_t binary_size;
250 uint8_t *buffer =
251 disk_cache_get(sscreen->disk_shader_cache,
252 sha1, &binary_size);
253 if (!buffer)
254 return false;
255
256 if (binary_size < sizeof(uint32_t) ||
257 *((uint32_t*)buffer) != binary_size) {
258 /* Something has gone wrong discard the item
259 * from the cache and rebuild/link from
260 * source.
261 */
262 assert(!"Invalid radeonsi shader disk cache "
263 "item!");
264
265 disk_cache_remove(sscreen->disk_shader_cache,
266 sha1);
267 free(buffer);
268
269 return false;
270 }
271
272 if (!si_load_shader_binary(shader, buffer)) {
273 free(buffer);
274 return false;
275 }
276 free(buffer);
277
278 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
279 shader, false))
280 FREE(ir_binary);
281 } else {
282 return false;
283 }
284 } else {
285 if (si_load_shader_binary(shader, entry->data))
286 FREE(ir_binary);
287 else
288 return false;
289 }
290 p_atomic_inc(&sscreen->num_shader_cache_hits);
291 return true;
292 }
293
294 static uint32_t si_shader_cache_key_hash(const void *key)
295 {
296 /* The first dword is the key size. */
297 return util_hash_crc32(key, *(uint32_t*)key);
298 }
299
300 static bool si_shader_cache_key_equals(const void *a, const void *b)
301 {
302 uint32_t *keya = (uint32_t*)a;
303 uint32_t *keyb = (uint32_t*)b;
304
305 /* The first dword is the key size. */
306 if (*keya != *keyb)
307 return false;
308
309 return memcmp(keya, keyb, *keya) == 0;
310 }
311
312 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
313 {
314 FREE((void*)entry->key);
315 FREE(entry->data);
316 }
317
318 bool si_init_shader_cache(struct si_screen *sscreen)
319 {
320 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
321 sscreen->shader_cache =
322 _mesa_hash_table_create(NULL,
323 si_shader_cache_key_hash,
324 si_shader_cache_key_equals);
325
326 return sscreen->shader_cache != NULL;
327 }
328
329 void si_destroy_shader_cache(struct si_screen *sscreen)
330 {
331 if (sscreen->shader_cache)
332 _mesa_hash_table_destroy(sscreen->shader_cache,
333 si_destroy_shader_cache_entry);
334 mtx_destroy(&sscreen->shader_cache_mutex);
335 }
336
337 /* SHADER STATES */
338
339 static void si_set_tesseval_regs(struct si_screen *sscreen,
340 struct si_shader_selector *tes,
341 struct si_pm4_state *pm4)
342 {
343 struct tgsi_shader_info *info = &tes->info;
344 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
345 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
346 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
347 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
348 unsigned type, partitioning, topology, distribution_mode;
349
350 switch (tes_prim_mode) {
351 case PIPE_PRIM_LINES:
352 type = V_028B6C_TESS_ISOLINE;
353 break;
354 case PIPE_PRIM_TRIANGLES:
355 type = V_028B6C_TESS_TRIANGLE;
356 break;
357 case PIPE_PRIM_QUADS:
358 type = V_028B6C_TESS_QUAD;
359 break;
360 default:
361 assert(0);
362 return;
363 }
364
365 switch (tes_spacing) {
366 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
367 partitioning = V_028B6C_PART_FRAC_ODD;
368 break;
369 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
370 partitioning = V_028B6C_PART_FRAC_EVEN;
371 break;
372 case PIPE_TESS_SPACING_EQUAL:
373 partitioning = V_028B6C_PART_INTEGER;
374 break;
375 default:
376 assert(0);
377 return;
378 }
379
380 if (tes_point_mode)
381 topology = V_028B6C_OUTPUT_POINT;
382 else if (tes_prim_mode == PIPE_PRIM_LINES)
383 topology = V_028B6C_OUTPUT_LINE;
384 else if (tes_vertex_order_cw)
385 /* for some reason, this must be the other way around */
386 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
387 else
388 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
389
390 if (sscreen->has_distributed_tess) {
391 if (sscreen->info.family == CHIP_FIJI ||
392 sscreen->info.family >= CHIP_POLARIS10)
393 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
394 else
395 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
396 } else
397 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
398
399 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
400 S_028B6C_TYPE(type) |
401 S_028B6C_PARTITIONING(partitioning) |
402 S_028B6C_TOPOLOGY(topology) |
403 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
404 }
405
406 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
407 * whether the "fractional odd" tessellation spacing is used.
408 *
409 * Possible VGT configurations and which state should set the register:
410 *
411 * Reg set in | VGT shader configuration | Value
412 * ------------------------------------------------------
413 * VS as VS | VS | 30
414 * VS as ES | ES -> GS -> VS | 30
415 * TES as VS | LS -> HS -> VS | 14 or 30
416 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
417 *
418 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
419 */
420 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
421 struct si_shader_selector *sel,
422 struct si_shader *shader,
423 struct si_pm4_state *pm4)
424 {
425 unsigned type = sel->type;
426
427 if (sscreen->info.family < CHIP_POLARIS10)
428 return;
429
430 /* VS as VS, or VS as ES: */
431 if ((type == PIPE_SHADER_VERTEX &&
432 (!shader ||
433 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
434 /* TES as VS, or TES as ES: */
435 type == PIPE_SHADER_TESS_EVAL) {
436 unsigned vtx_reuse_depth = 30;
437
438 if (type == PIPE_SHADER_TESS_EVAL &&
439 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
440 PIPE_TESS_SPACING_FRACTIONAL_ODD)
441 vtx_reuse_depth = 14;
442
443 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
444 vtx_reuse_depth);
445 }
446 }
447
448 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
449 {
450 if (shader->pm4)
451 si_pm4_clear_state(shader->pm4);
452 else
453 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
454
455 if (shader->pm4) {
456 shader->pm4->shader = shader;
457 return shader->pm4;
458 } else {
459 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
460 return NULL;
461 }
462 }
463
464 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
465 {
466 /* Add the pointer to VBO descriptors. */
467 if (HAVE_32BIT_POINTERS) {
468 return num_always_on_user_sgprs + 1;
469 } else {
470 assert(num_always_on_user_sgprs % 2 == 0);
471 return num_always_on_user_sgprs + 2;
472 }
473 }
474
475 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
476 {
477 struct si_pm4_state *pm4;
478 unsigned vgpr_comp_cnt;
479 uint64_t va;
480
481 assert(sscreen->info.chip_class <= VI);
482
483 pm4 = si_get_shader_pm4_state(shader);
484 if (!pm4)
485 return;
486
487 va = shader->bo->gpu_address;
488 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
489
490 /* We need at least 2 components for LS.
491 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
492 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
493 */
494 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
495
496 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
497 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
498
499 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
500 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
501 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
502 S_00B528_DX10_CLAMP(1) |
503 S_00B528_FLOAT_MODE(shader->config.float_mode);
504 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
505 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
506 }
507
508 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
509 {
510 struct si_pm4_state *pm4;
511 uint64_t va;
512 unsigned ls_vgpr_comp_cnt = 0;
513
514 pm4 = si_get_shader_pm4_state(shader);
515 if (!pm4)
516 return;
517
518 va = shader->bo->gpu_address;
519 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
520
521 if (sscreen->info.chip_class >= GFX9) {
522 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
523 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
524
525 /* We need at least 2 components for LS.
526 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
527 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
528 */
529 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
530
531 unsigned num_user_sgprs =
532 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
533
534 shader->config.rsrc2 =
535 S_00B42C_USER_SGPR(num_user_sgprs) |
536 S_00B42C_USER_SGPR_MSB(num_user_sgprs >> 5) |
537 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
538 } else {
539 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
540 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
541
542 shader->config.rsrc2 =
543 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
544 S_00B42C_OC_LDS_EN(1) |
545 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
546 }
547
548 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
549 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
550 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
551 S_00B428_DX10_CLAMP(1) |
552 S_00B428_FLOAT_MODE(shader->config.float_mode) |
553 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
554
555 if (sscreen->info.chip_class <= VI) {
556 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
557 shader->config.rsrc2);
558 }
559 }
560
561 static void si_emit_shader_es(struct si_context *sctx)
562 {
563 struct si_shader *shader = sctx->queued.named.es->shader;
564
565 if (!shader)
566 return;
567
568 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
569 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
570 shader->selector->esgs_itemsize / 4);
571 }
572
573 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
574 {
575 struct si_pm4_state *pm4;
576 unsigned num_user_sgprs;
577 unsigned vgpr_comp_cnt;
578 uint64_t va;
579 unsigned oc_lds_en;
580
581 assert(sscreen->info.chip_class <= VI);
582
583 pm4 = si_get_shader_pm4_state(shader);
584 if (!pm4)
585 return;
586
587 pm4->atom.emit = si_emit_shader_es;
588 va = shader->bo->gpu_address;
589 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
590
591 if (shader->selector->type == PIPE_SHADER_VERTEX) {
592 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
593 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
594 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
595 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
596 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
597 num_user_sgprs = SI_TES_NUM_USER_SGPR;
598 } else
599 unreachable("invalid shader selector type");
600
601 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
602
603 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
604 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
605 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
606 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
607 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
608 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
609 S_00B328_DX10_CLAMP(1) |
610 S_00B328_FLOAT_MODE(shader->config.float_mode));
611 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
612 S_00B32C_USER_SGPR(num_user_sgprs) |
613 S_00B32C_OC_LDS_EN(oc_lds_en) |
614 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
615
616 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
617 si_set_tesseval_regs(sscreen, shader->selector, pm4);
618
619 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
620 }
621
622 static unsigned si_conv_prim_to_gs_out(unsigned mode)
623 {
624 static const int prim_conv[] = {
625 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
626 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
627 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
628 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
629 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
630 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
631 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
632 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
633 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
634 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
635 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
636 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
637 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
638 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
639 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
640 };
641 assert(mode < ARRAY_SIZE(prim_conv));
642
643 return prim_conv[mode];
644 }
645
646 struct gfx9_gs_info {
647 unsigned es_verts_per_subgroup;
648 unsigned gs_prims_per_subgroup;
649 unsigned gs_inst_prims_in_subgroup;
650 unsigned max_prims_per_subgroup;
651 unsigned lds_size;
652 };
653
654 static void gfx9_get_gs_info(struct si_shader_selector *es,
655 struct si_shader_selector *gs,
656 struct gfx9_gs_info *out)
657 {
658 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
659 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
660 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
661 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
662
663 /* All these are in dwords: */
664 /* We can't allow using the whole LDS, because GS waves compete with
665 * other shader stages for LDS space. */
666 const unsigned max_lds_size = 8 * 1024;
667 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
668 unsigned esgs_lds_size;
669
670 /* All these are per subgroup: */
671 const unsigned max_out_prims = 32 * 1024;
672 const unsigned max_es_verts = 255;
673 const unsigned ideal_gs_prims = 64;
674 unsigned max_gs_prims, gs_prims;
675 unsigned min_es_verts, es_verts, worst_case_es_verts;
676
677 if (uses_adjacency || gs_num_invocations > 1)
678 max_gs_prims = 127 / gs_num_invocations;
679 else
680 max_gs_prims = 255;
681
682 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
683 * Make sure we don't go over the maximum value.
684 */
685 if (gs->gs_max_out_vertices > 0) {
686 max_gs_prims = MIN2(max_gs_prims,
687 max_out_prims /
688 (gs->gs_max_out_vertices * gs_num_invocations));
689 }
690 assert(max_gs_prims > 0);
691
692 /* If the primitive has adjacency, halve the number of vertices
693 * that will be reused in multiple primitives.
694 */
695 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
696
697 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
698 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
699
700 /* Compute ESGS LDS size based on the worst case number of ES vertices
701 * needed to create the target number of GS prims per subgroup.
702 */
703 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
704
705 /* If total LDS usage is too big, refactor partitions based on ratio
706 * of ESGS item sizes.
707 */
708 if (esgs_lds_size > max_lds_size) {
709 /* Our target GS Prims Per Subgroup was too large. Calculate
710 * the maximum number of GS Prims Per Subgroup that will fit
711 * into LDS, capped by the maximum that the hardware can support.
712 */
713 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
714 max_gs_prims);
715 assert(gs_prims > 0);
716 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
717 max_es_verts);
718
719 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
720 assert(esgs_lds_size <= max_lds_size);
721 }
722
723 /* Now calculate remaining ESGS information. */
724 if (esgs_lds_size)
725 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
726 else
727 es_verts = max_es_verts;
728
729 /* Vertices for adjacency primitives are not always reused, so restore
730 * it for ES_VERTS_PER_SUBGRP.
731 */
732 min_es_verts = gs->gs_input_verts_per_prim;
733
734 /* For normal primitives, the VGT only checks if they are past the ES
735 * verts per subgroup after allocating a full GS primitive and if they
736 * are, kick off a new subgroup. But if those additional ES verts are
737 * unique (e.g. not reused) we need to make sure there is enough LDS
738 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
739 */
740 es_verts -= min_es_verts - 1;
741
742 out->es_verts_per_subgroup = es_verts;
743 out->gs_prims_per_subgroup = gs_prims;
744 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
745 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
746 gs->gs_max_out_vertices;
747 out->lds_size = align(esgs_lds_size, 128) / 128;
748
749 assert(out->max_prims_per_subgroup <= max_out_prims);
750 }
751
752 static void si_emit_shader_gs(struct si_context *sctx)
753 {
754 struct si_shader *shader = sctx->queued.named.gs->shader;
755 if (!shader)
756 return;
757
758 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
759 * R_028A68_VGT_GSVS_RING_OFFSET_3, R_028A6C_VGT_GS_OUT_PRIM_TYPE */
760 radeon_opt_set_context_reg4(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
761 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
762 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
763 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
764 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3,
765 shader->ctx_reg.gs.vgt_gs_out_prim_type);
766
767
768 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
769 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
770 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
771 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
772
773 /* R_028B38_VGT_GS_MAX_VERT_OUT */
774 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
775 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
776 shader->ctx_reg.gs.vgt_gs_max_vert_out);
777
778 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
779 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
780 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
781 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
782 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
783 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
784 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
785 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
786
787 /* R_028B90_VGT_GS_INSTANCE_CNT */
788 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
789 SI_TRACKED_VGT_GS_INSTANCE_CNT,
790 shader->ctx_reg.gs.vgt_gs_instance_cnt);
791
792 if (sctx->chip_class >= GFX9) {
793 /* R_028A44_VGT_GS_ONCHIP_CNTL */
794 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
795 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
796 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
797 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
798 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
799 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
800 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
801 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
802 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
803 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
804 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
805 }
806 }
807
808 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
809 {
810 struct si_shader_selector *sel = shader->selector;
811 const ubyte *num_components = sel->info.num_stream_output_components;
812 unsigned gs_num_invocations = sel->gs_num_invocations;
813 struct si_pm4_state *pm4;
814 uint64_t va;
815 unsigned max_stream = sel->max_gs_stream;
816 unsigned offset;
817
818 pm4 = si_get_shader_pm4_state(shader);
819 if (!pm4)
820 return;
821
822 pm4->atom.emit = si_emit_shader_gs;
823
824 offset = num_components[0] * sel->gs_max_out_vertices;
825 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
826
827 if (max_stream >= 1)
828 offset += num_components[1] * sel->gs_max_out_vertices;
829 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
830
831 if (max_stream >= 2)
832 offset += num_components[2] * sel->gs_max_out_vertices;
833 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
834
835 shader->ctx_reg.gs.vgt_gs_out_prim_type =
836 si_conv_prim_to_gs_out(sel->gs_output_prim);
837
838 if (max_stream >= 3)
839 offset += num_components[3] * sel->gs_max_out_vertices;
840 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
841
842 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
843 assert(offset < (1 << 15));
844
845 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
846
847 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
848 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
849 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
850 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
851
852 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
853 S_028B90_ENABLE(gs_num_invocations > 0);
854
855 va = shader->bo->gpu_address;
856 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
857
858 if (sscreen->info.chip_class >= GFX9) {
859 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
860 unsigned es_type = shader->key.part.gs.es->type;
861 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
862 struct gfx9_gs_info gs_info;
863
864 if (es_type == PIPE_SHADER_VERTEX)
865 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
866 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
867 else if (es_type == PIPE_SHADER_TESS_EVAL)
868 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
869 else
870 unreachable("invalid shader selector type");
871
872 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
873 * VGPR[0:4] are always loaded.
874 */
875 if (sel->info.uses_invocationid)
876 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
877 else if (sel->info.uses_primid)
878 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
879 else if (input_prim >= PIPE_PRIM_TRIANGLES)
880 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
881 else
882 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
883
884 unsigned num_user_sgprs;
885 if (es_type == PIPE_SHADER_VERTEX)
886 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
887 else
888 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
889
890 gfx9_get_gs_info(shader->key.part.gs.es, sel, &gs_info);
891
892 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
893 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
894
895 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
896 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
897 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
898 S_00B228_DX10_CLAMP(1) |
899 S_00B228_FLOAT_MODE(shader->config.float_mode) |
900 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
901 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
902 S_00B22C_USER_SGPR(num_user_sgprs) |
903 S_00B22C_USER_SGPR_MSB(num_user_sgprs >> 5) |
904 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
905 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
906 S_00B22C_LDS_SIZE(gs_info.lds_size) |
907 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
908
909 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
910 S_028A44_ES_VERTS_PER_SUBGRP(gs_info.es_verts_per_subgroup) |
911 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info.gs_prims_per_subgroup) |
912 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info.gs_inst_prims_in_subgroup);
913 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
914 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info.max_prims_per_subgroup);
915 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
916 shader->key.part.gs.es->esgs_itemsize / 4;
917
918 if (es_type == PIPE_SHADER_TESS_EVAL)
919 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
920
921 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
922 NULL, pm4);
923 } else {
924 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
925 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
926
927 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
928 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
929 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
930 S_00B228_DX10_CLAMP(1) |
931 S_00B228_FLOAT_MODE(shader->config.float_mode));
932 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
933 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
934 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
935 }
936 }
937
938 static void si_emit_shader_vs(struct si_context *sctx)
939 {
940 struct si_shader *shader = sctx->queued.named.vs->shader;
941 if (!shader)
942 return;
943
944 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
945 SI_TRACKED_VGT_GS_MODE,
946 shader->ctx_reg.vs.vgt_gs_mode);
947 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
948 SI_TRACKED_VGT_PRIMITIVEID_EN,
949 shader->ctx_reg.vs.vgt_primitiveid_en);
950
951 if (sctx->chip_class <= VI) {
952 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
953 SI_TRACKED_VGT_REUSE_OFF,
954 shader->ctx_reg.vs.vgt_reuse_off);
955 }
956
957 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
958 SI_TRACKED_SPI_VS_OUT_CONFIG,
959 shader->ctx_reg.vs.spi_vs_out_config);
960
961 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
962 SI_TRACKED_SPI_SHADER_POS_FORMAT,
963 shader->ctx_reg.vs.spi_shader_pos_format);
964
965 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
966 SI_TRACKED_PA_CL_VTE_CNTL,
967 shader->ctx_reg.vs.pa_cl_vte_cntl);
968 }
969
970 /**
971 * Compute the state for \p shader, which will run as a vertex shader on the
972 * hardware.
973 *
974 * If \p gs is non-NULL, it points to the geometry shader for which this shader
975 * is the copy shader.
976 */
977 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
978 struct si_shader_selector *gs)
979 {
980 const struct tgsi_shader_info *info = &shader->selector->info;
981 struct si_pm4_state *pm4;
982 unsigned num_user_sgprs, vgpr_comp_cnt;
983 uint64_t va;
984 unsigned nparams, oc_lds_en;
985 unsigned window_space =
986 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
987 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
988
989 pm4 = si_get_shader_pm4_state(shader);
990 if (!pm4)
991 return;
992
993 pm4->atom.emit = si_emit_shader_vs;
994
995 /* We always write VGT_GS_MODE in the VS state, because every switch
996 * between different shader pipelines involving a different GS or no
997 * GS at all involves a switch of the VS (different GS use different
998 * copy shaders). On the other hand, when the API switches from a GS to
999 * no GS and then back to the same GS used originally, the GS state is
1000 * not sent again.
1001 */
1002 if (!gs) {
1003 unsigned mode = V_028A40_GS_OFF;
1004
1005 /* PrimID needs GS scenario A. */
1006 if (enable_prim_id)
1007 mode = V_028A40_GS_SCENARIO_A;
1008
1009 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1010 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1011 } else {
1012 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1013 sscreen->info.chip_class);
1014 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1015 }
1016
1017 if (sscreen->info.chip_class <= VI) {
1018 /* Reuse needs to be set off if we write oViewport. */
1019 shader->ctx_reg.vs.vgt_reuse_off =
1020 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1021 }
1022
1023 va = shader->bo->gpu_address;
1024 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1025
1026 if (gs) {
1027 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1028 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1029 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1030 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1031 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1032 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1033 */
1034 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
1035
1036 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1037 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1038 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1039 } else {
1040 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1041 }
1042 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1043 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1044 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1045 } else
1046 unreachable("invalid shader selector type");
1047
1048 /* VS is required to export at least one param. */
1049 nparams = MAX2(shader->info.nr_param_exports, 1);
1050 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1051
1052 shader->ctx_reg.vs.spi_shader_pos_format =
1053 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1054 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1055 V_02870C_SPI_SHADER_4COMP :
1056 V_02870C_SPI_SHADER_NONE) |
1057 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1058 V_02870C_SPI_SHADER_4COMP :
1059 V_02870C_SPI_SHADER_NONE) |
1060 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1061 V_02870C_SPI_SHADER_4COMP :
1062 V_02870C_SPI_SHADER_NONE);
1063
1064 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1065
1066 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1067 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1068 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
1069 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
1070 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
1071 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1072 S_00B128_DX10_CLAMP(1) |
1073 S_00B128_FLOAT_MODE(shader->config.float_mode));
1074 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
1075 S_00B12C_USER_SGPR(num_user_sgprs) |
1076 S_00B12C_OC_LDS_EN(oc_lds_en) |
1077 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1078 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1079 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1080 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1081 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
1082 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1083
1084 if (window_space)
1085 shader->ctx_reg.vs.pa_cl_vte_cntl =
1086 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1087 else
1088 shader->ctx_reg.vs.pa_cl_vte_cntl =
1089 S_028818_VTX_W0_FMT(1) |
1090 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1091 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1092 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1093
1094 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1095 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1096
1097 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1098 }
1099
1100 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1101 {
1102 struct tgsi_shader_info *info = &ps->selector->info;
1103 unsigned num_colors = !!(info->colors_read & 0x0f) +
1104 !!(info->colors_read & 0xf0);
1105 unsigned num_interp = ps->selector->info.num_inputs +
1106 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1107
1108 assert(num_interp <= 32);
1109 return MIN2(num_interp, 32);
1110 }
1111
1112 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1113 {
1114 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1115 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1116
1117 /* If the i-th target format is set, all previous target formats must
1118 * be non-zero to avoid hangs.
1119 */
1120 for (i = 0; i < num_targets; i++)
1121 if (!(value & (0xf << (i * 4))))
1122 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1123
1124 return value;
1125 }
1126
1127 static void si_emit_shader_ps(struct si_context *sctx)
1128 {
1129 struct si_shader *shader = sctx->queued.named.ps->shader;
1130 if (!shader)
1131 return;
1132
1133 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1134 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1135 SI_TRACKED_SPI_PS_INPUT_ENA,
1136 shader->ctx_reg.ps.spi_ps_input_ena,
1137 shader->ctx_reg.ps.spi_ps_input_addr);
1138
1139 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1140 SI_TRACKED_SPI_BARYC_CNTL,
1141 shader->ctx_reg.ps.spi_baryc_cntl);
1142 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1143 SI_TRACKED_SPI_PS_IN_CONTROL,
1144 shader->ctx_reg.ps.spi_ps_in_control);
1145
1146 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1147 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1148 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1149 shader->ctx_reg.ps.spi_shader_z_format,
1150 shader->ctx_reg.ps.spi_shader_col_format);
1151
1152 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1153 SI_TRACKED_CB_SHADER_MASK,
1154 shader->ctx_reg.ps.cb_shader_mask);
1155 }
1156
1157 static void si_shader_ps(struct si_shader *shader)
1158 {
1159 struct tgsi_shader_info *info = &shader->selector->info;
1160 struct si_pm4_state *pm4;
1161 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1162 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1163 uint64_t va;
1164 unsigned input_ena = shader->config.spi_ps_input_ena;
1165
1166 /* we need to enable at least one of them, otherwise we hang the GPU */
1167 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1168 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1169 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1170 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1171 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1172 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1173 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1174 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1175 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1176 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1177 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1178 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1179 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1180 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1181
1182 /* Validate interpolation optimization flags (read as implications). */
1183 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1184 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1185 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1186 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1187 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1188 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1189 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1190 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1191 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1192 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1193 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1194 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1195 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1196 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1197 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1198 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1199 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1200 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1201
1202 /* Validate cases when the optimizations are off (read as implications). */
1203 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1204 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1205 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1206 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1207 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1208 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1209
1210 pm4 = si_get_shader_pm4_state(shader);
1211 if (!pm4)
1212 return;
1213
1214 pm4->atom.emit = si_emit_shader_ps;
1215
1216 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1217 * Possible vaules:
1218 * 0 -> Position = pixel center
1219 * 1 -> Position = pixel centroid
1220 * 2 -> Position = at sample position
1221 *
1222 * From GLSL 4.5 specification, section 7.1:
1223 * "The variable gl_FragCoord is available as an input variable from
1224 * within fragment shaders and it holds the window relative coordinates
1225 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1226 * value can be for any location within the pixel, or one of the
1227 * fragment samples. The use of centroid does not further restrict
1228 * this value to be inside the current primitive."
1229 *
1230 * Meaning that centroid has no effect and we can return anything within
1231 * the pixel. Thus, return the value at sample position, because that's
1232 * the most accurate one shaders can get.
1233 */
1234 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1235
1236 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1237 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1238 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1239
1240 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1241 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1242
1243 /* Ensure that some export memory is always allocated, for two reasons:
1244 *
1245 * 1) Correctness: The hardware ignores the EXEC mask if no export
1246 * memory is allocated, so KILL and alpha test do not work correctly
1247 * without this.
1248 * 2) Performance: Every shader needs at least a NULL export, even when
1249 * it writes no color/depth output. The NULL export instruction
1250 * stalls without this setting.
1251 *
1252 * Don't add this to CB_SHADER_MASK.
1253 */
1254 if (!spi_shader_col_format &&
1255 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1256 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1257
1258 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1259 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1260
1261 /* Set interpolation controls. */
1262 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1263
1264 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1265 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1266 shader->ctx_reg.ps.spi_shader_z_format =
1267 ac_get_spi_shader_z_format(info->writes_z,
1268 info->writes_stencil,
1269 info->writes_samplemask);
1270 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1271 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1272
1273 va = shader->bo->gpu_address;
1274 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1275 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1276 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1277
1278 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
1279 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1280 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
1281 S_00B028_DX10_CLAMP(1) |
1282 S_00B028_FLOAT_MODE(shader->config.float_mode));
1283 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1284 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1285 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1286 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1287 }
1288
1289 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1290 struct si_shader *shader)
1291 {
1292 switch (shader->selector->type) {
1293 case PIPE_SHADER_VERTEX:
1294 if (shader->key.as_ls)
1295 si_shader_ls(sscreen, shader);
1296 else if (shader->key.as_es)
1297 si_shader_es(sscreen, shader);
1298 else
1299 si_shader_vs(sscreen, shader, NULL);
1300 break;
1301 case PIPE_SHADER_TESS_CTRL:
1302 si_shader_hs(sscreen, shader);
1303 break;
1304 case PIPE_SHADER_TESS_EVAL:
1305 if (shader->key.as_es)
1306 si_shader_es(sscreen, shader);
1307 else
1308 si_shader_vs(sscreen, shader, NULL);
1309 break;
1310 case PIPE_SHADER_GEOMETRY:
1311 si_shader_gs(sscreen, shader);
1312 break;
1313 case PIPE_SHADER_FRAGMENT:
1314 si_shader_ps(shader);
1315 break;
1316 default:
1317 assert(0);
1318 }
1319 }
1320
1321 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1322 {
1323 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1324 if (sctx->queued.named.dsa)
1325 return sctx->queued.named.dsa->alpha_func;
1326
1327 return PIPE_FUNC_ALWAYS;
1328 }
1329
1330 static void si_shader_selector_key_vs(struct si_context *sctx,
1331 struct si_shader_selector *vs,
1332 struct si_shader_key *key,
1333 struct si_vs_prolog_bits *prolog_key)
1334 {
1335 if (!sctx->vertex_elements ||
1336 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS])
1337 return;
1338
1339 prolog_key->instance_divisor_is_one =
1340 sctx->vertex_elements->instance_divisor_is_one;
1341 prolog_key->instance_divisor_is_fetched =
1342 sctx->vertex_elements->instance_divisor_is_fetched;
1343
1344 /* Prefer a monolithic shader to allow scheduling divisions around
1345 * VBO loads. */
1346 if (prolog_key->instance_divisor_is_fetched)
1347 key->opt.prefer_mono = 1;
1348
1349 unsigned count = MIN2(vs->info.num_inputs,
1350 sctx->vertex_elements->count);
1351 memcpy(key->mono.vs_fix_fetch, sctx->vertex_elements->fix_fetch, count);
1352 }
1353
1354 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1355 struct si_shader_selector *vs,
1356 struct si_shader_key *key)
1357 {
1358 struct si_shader_selector *ps = sctx->ps_shader.cso;
1359
1360 key->opt.clip_disable =
1361 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1362 (vs->info.clipdist_writemask ||
1363 vs->info.writes_clipvertex) &&
1364 !vs->info.culldist_writemask;
1365
1366 /* Find out if PS is disabled. */
1367 bool ps_disabled = true;
1368 if (ps) {
1369 const struct si_state_blend *blend = sctx->queued.named.blend;
1370 bool alpha_to_coverage = blend && blend->alpha_to_coverage;
1371 bool ps_modifies_zs = ps->info.uses_kill ||
1372 ps->info.writes_z ||
1373 ps->info.writes_stencil ||
1374 ps->info.writes_samplemask ||
1375 alpha_to_coverage ||
1376 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1377 unsigned ps_colormask = si_get_total_colormask(sctx);
1378
1379 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1380 (!ps_colormask &&
1381 !ps_modifies_zs &&
1382 !ps->info.writes_memory);
1383 }
1384
1385 /* Find out which VS outputs aren't used by the PS. */
1386 uint64_t outputs_written = vs->outputs_written_before_ps;
1387 uint64_t inputs_read = 0;
1388
1389 /* Ignore outputs that are not passed from VS to PS. */
1390 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1391 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1392 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1393
1394 if (!ps_disabled) {
1395 inputs_read = ps->inputs_read;
1396 }
1397
1398 uint64_t linked = outputs_written & inputs_read;
1399
1400 key->opt.kill_outputs = ~linked & outputs_written;
1401 }
1402
1403 /* Compute the key for the hw shader variant */
1404 static inline void si_shader_selector_key(struct pipe_context *ctx,
1405 struct si_shader_selector *sel,
1406 struct si_shader_key *key)
1407 {
1408 struct si_context *sctx = (struct si_context *)ctx;
1409
1410 memset(key, 0, sizeof(*key));
1411
1412 switch (sel->type) {
1413 case PIPE_SHADER_VERTEX:
1414 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1415
1416 if (sctx->tes_shader.cso)
1417 key->as_ls = 1;
1418 else if (sctx->gs_shader.cso)
1419 key->as_es = 1;
1420 else {
1421 si_shader_selector_key_hw_vs(sctx, sel, key);
1422
1423 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1424 key->mono.u.vs_export_prim_id = 1;
1425 }
1426 break;
1427 case PIPE_SHADER_TESS_CTRL:
1428 if (sctx->chip_class >= GFX9) {
1429 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1430 key, &key->part.tcs.ls_prolog);
1431 key->part.tcs.ls = sctx->vs_shader.cso;
1432
1433 /* When the LS VGPR fix is needed, monolithic shaders
1434 * can:
1435 * - avoid initializing EXEC in both the LS prolog
1436 * and the LS main part when !vs_needs_prolog
1437 * - remove the fixup for unused input VGPRs
1438 */
1439 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1440
1441 /* The LS output / HS input layout can be communicated
1442 * directly instead of via user SGPRs for merged LS-HS.
1443 * The LS VGPR fix prefers this too.
1444 */
1445 key->opt.prefer_mono = 1;
1446 }
1447
1448 key->part.tcs.epilog.prim_mode =
1449 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1450 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1451 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1452 key->part.tcs.epilog.tes_reads_tess_factors =
1453 sctx->tes_shader.cso->info.reads_tess_factors;
1454
1455 if (sel == sctx->fixed_func_tcs_shader.cso)
1456 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1457 break;
1458 case PIPE_SHADER_TESS_EVAL:
1459 if (sctx->gs_shader.cso)
1460 key->as_es = 1;
1461 else {
1462 si_shader_selector_key_hw_vs(sctx, sel, key);
1463
1464 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1465 key->mono.u.vs_export_prim_id = 1;
1466 }
1467 break;
1468 case PIPE_SHADER_GEOMETRY:
1469 if (sctx->chip_class >= GFX9) {
1470 if (sctx->tes_shader.cso) {
1471 key->part.gs.es = sctx->tes_shader.cso;
1472 } else {
1473 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1474 key, &key->part.gs.vs_prolog);
1475 key->part.gs.es = sctx->vs_shader.cso;
1476 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1477 }
1478
1479 /* Merged ES-GS can have unbalanced wave usage.
1480 *
1481 * ES threads are per-vertex, while GS threads are
1482 * per-primitive. So without any amplification, there
1483 * are fewer GS threads than ES threads, which can result
1484 * in empty (no-op) GS waves. With too much amplification,
1485 * there are more GS threads than ES threads, which
1486 * can result in empty (no-op) ES waves.
1487 *
1488 * Non-monolithic shaders are implemented by setting EXEC
1489 * at the beginning of shader parts, and don't jump to
1490 * the end if EXEC is 0.
1491 *
1492 * Monolithic shaders use conditional blocks, so they can
1493 * jump and skip empty waves of ES or GS. So set this to
1494 * always use optimized variants, which are monolithic.
1495 */
1496 key->opt.prefer_mono = 1;
1497 }
1498 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1499 break;
1500 case PIPE_SHADER_FRAGMENT: {
1501 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1502 struct si_state_blend *blend = sctx->queued.named.blend;
1503
1504 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1505 sel->info.colors_written == 0x1)
1506 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1507
1508 if (blend) {
1509 /* Select the shader color format based on whether
1510 * blending or alpha are needed.
1511 */
1512 key->part.ps.epilog.spi_shader_col_format =
1513 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1514 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1515 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1516 sctx->framebuffer.spi_shader_col_format_blend) |
1517 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1518 sctx->framebuffer.spi_shader_col_format_alpha) |
1519 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1520 sctx->framebuffer.spi_shader_col_format);
1521 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1522
1523 /* The output for dual source blending should have
1524 * the same format as the first output.
1525 */
1526 if (blend->dual_src_blend)
1527 key->part.ps.epilog.spi_shader_col_format |=
1528 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1529 } else
1530 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1531
1532 /* If alpha-to-coverage is enabled, we have to export alpha
1533 * even if there is no color buffer.
1534 */
1535 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1536 blend && blend->alpha_to_coverage)
1537 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1538
1539 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1540 * to the range supported by the type if a channel has less
1541 * than 16 bits and the export format is 16_ABGR.
1542 */
1543 if (sctx->chip_class <= CIK && sctx->family != CHIP_HAWAII) {
1544 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1545 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1546 }
1547
1548 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1549 if (!key->part.ps.epilog.last_cbuf) {
1550 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1551 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1552 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1553 }
1554
1555 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1556 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1557
1558 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1559 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1560
1561 if (sctx->queued.named.blend) {
1562 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1563 rs->multisample_enable;
1564 }
1565
1566 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1567 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1568 (is_line && rs->line_smooth)) &&
1569 sctx->framebuffer.nr_samples <= 1;
1570 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1571
1572 if (sctx->ps_iter_samples > 1 &&
1573 sel->info.reads_samplemask) {
1574 key->part.ps.prolog.samplemask_log_ps_iter =
1575 util_logbase2(sctx->ps_iter_samples);
1576 }
1577
1578 if (rs->force_persample_interp &&
1579 rs->multisample_enable &&
1580 sctx->framebuffer.nr_samples > 1 &&
1581 sctx->ps_iter_samples > 1) {
1582 key->part.ps.prolog.force_persp_sample_interp =
1583 sel->info.uses_persp_center ||
1584 sel->info.uses_persp_centroid;
1585
1586 key->part.ps.prolog.force_linear_sample_interp =
1587 sel->info.uses_linear_center ||
1588 sel->info.uses_linear_centroid;
1589 } else if (rs->multisample_enable &&
1590 sctx->framebuffer.nr_samples > 1) {
1591 key->part.ps.prolog.bc_optimize_for_persp =
1592 sel->info.uses_persp_center &&
1593 sel->info.uses_persp_centroid;
1594 key->part.ps.prolog.bc_optimize_for_linear =
1595 sel->info.uses_linear_center &&
1596 sel->info.uses_linear_centroid;
1597 } else {
1598 /* Make sure SPI doesn't compute more than 1 pair
1599 * of (i,j), which is the optimization here. */
1600 key->part.ps.prolog.force_persp_center_interp =
1601 sel->info.uses_persp_center +
1602 sel->info.uses_persp_centroid +
1603 sel->info.uses_persp_sample > 1;
1604
1605 key->part.ps.prolog.force_linear_center_interp =
1606 sel->info.uses_linear_center +
1607 sel->info.uses_linear_centroid +
1608 sel->info.uses_linear_sample > 1;
1609
1610 if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
1611 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1612 }
1613
1614 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1615
1616 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1617 if (sctx->ps_uses_fbfetch) {
1618 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
1619 struct pipe_resource *tex = cb0->texture;
1620
1621 /* 1D textures are allocated and used as 2D on GFX9. */
1622 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
1623 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
1624 (tex->target == PIPE_TEXTURE_1D ||
1625 tex->target == PIPE_TEXTURE_1D_ARRAY);
1626 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
1627 tex->target == PIPE_TEXTURE_2D_ARRAY ||
1628 tex->target == PIPE_TEXTURE_CUBE ||
1629 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
1630 tex->target == PIPE_TEXTURE_3D;
1631 }
1632 break;
1633 }
1634 default:
1635 assert(0);
1636 }
1637
1638 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
1639 memset(&key->opt, 0, sizeof(key->opt));
1640 }
1641
1642 static void si_build_shader_variant(struct si_shader *shader,
1643 int thread_index,
1644 bool low_priority)
1645 {
1646 struct si_shader_selector *sel = shader->selector;
1647 struct si_screen *sscreen = sel->screen;
1648 struct ac_llvm_compiler *compiler;
1649 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1650 int r;
1651
1652 if (thread_index >= 0) {
1653 if (low_priority) {
1654 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
1655 compiler = &sscreen->compiler_lowp[thread_index];
1656 } else {
1657 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
1658 compiler = &sscreen->compiler[thread_index];
1659 }
1660 if (!debug->async)
1661 debug = NULL;
1662 } else {
1663 assert(!low_priority);
1664 compiler = shader->compiler_ctx_state.compiler;
1665 }
1666
1667 r = si_shader_create(sscreen, compiler, shader, debug);
1668 if (unlikely(r)) {
1669 PRINT_ERR("Failed to build shader variant (type=%u) %d\n",
1670 sel->type, r);
1671 shader->compilation_failed = true;
1672 return;
1673 }
1674
1675 if (shader->compiler_ctx_state.is_debug_context) {
1676 FILE *f = open_memstream(&shader->shader_log,
1677 &shader->shader_log_size);
1678 if (f) {
1679 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1680 fclose(f);
1681 }
1682 }
1683
1684 si_shader_init_pm4_state(sscreen, shader);
1685 }
1686
1687 static void si_build_shader_variant_low_priority(void *job, int thread_index)
1688 {
1689 struct si_shader *shader = (struct si_shader *)job;
1690
1691 assert(thread_index >= 0);
1692
1693 si_build_shader_variant(shader, thread_index, true);
1694 }
1695
1696 static const struct si_shader_key zeroed;
1697
1698 static bool si_check_missing_main_part(struct si_screen *sscreen,
1699 struct si_shader_selector *sel,
1700 struct si_compiler_ctx_state *compiler_state,
1701 struct si_shader_key *key)
1702 {
1703 struct si_shader **mainp = si_get_main_shader_part(sel, key);
1704
1705 if (!*mainp) {
1706 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1707
1708 if (!main_part)
1709 return false;
1710
1711 /* We can leave the fence as permanently signaled because the
1712 * main part becomes visible globally only after it has been
1713 * compiled. */
1714 util_queue_fence_init(&main_part->ready);
1715
1716 main_part->selector = sel;
1717 main_part->key.as_es = key->as_es;
1718 main_part->key.as_ls = key->as_ls;
1719 main_part->is_monolithic = false;
1720
1721 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
1722 main_part, &compiler_state->debug) != 0) {
1723 FREE(main_part);
1724 return false;
1725 }
1726 *mainp = main_part;
1727 }
1728 return true;
1729 }
1730
1731 /* Select the hw shader variant depending on the current state. */
1732 static int si_shader_select_with_key(struct si_screen *sscreen,
1733 struct si_shader_ctx_state *state,
1734 struct si_compiler_ctx_state *compiler_state,
1735 struct si_shader_key *key,
1736 int thread_index)
1737 {
1738 struct si_shader_selector *sel = state->cso;
1739 struct si_shader_selector *previous_stage_sel = NULL;
1740 struct si_shader *current = state->current;
1741 struct si_shader *iter, *shader = NULL;
1742
1743 again:
1744 /* Check if we don't need to change anything.
1745 * This path is also used for most shaders that don't need multiple
1746 * variants, it will cost just a computation of the key and this
1747 * test. */
1748 if (likely(current &&
1749 memcmp(&current->key, key, sizeof(*key)) == 0)) {
1750 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
1751 if (current->is_optimized) {
1752 memset(&key->opt, 0, sizeof(key->opt));
1753 goto current_not_ready;
1754 }
1755
1756 util_queue_fence_wait(&current->ready);
1757 }
1758
1759 return current->compilation_failed ? -1 : 0;
1760 }
1761 current_not_ready:
1762
1763 /* This must be done before the mutex is locked, because async GS
1764 * compilation calls this function too, and therefore must enter
1765 * the mutex first.
1766 *
1767 * Only wait if we are in a draw call. Don't wait if we are
1768 * in a compiler thread.
1769 */
1770 if (thread_index < 0)
1771 util_queue_fence_wait(&sel->ready);
1772
1773 mtx_lock(&sel->mutex);
1774
1775 /* Find the shader variant. */
1776 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1777 /* Don't check the "current" shader. We checked it above. */
1778 if (current != iter &&
1779 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1780 mtx_unlock(&sel->mutex);
1781
1782 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
1783 /* If it's an optimized shader and its compilation has
1784 * been started but isn't done, use the unoptimized
1785 * shader so as not to cause a stall due to compilation.
1786 */
1787 if (iter->is_optimized) {
1788 memset(&key->opt, 0, sizeof(key->opt));
1789 goto again;
1790 }
1791
1792 util_queue_fence_wait(&iter->ready);
1793 }
1794
1795 if (iter->compilation_failed) {
1796 return -1; /* skip the draw call */
1797 }
1798
1799 state->current = iter;
1800 return 0;
1801 }
1802 }
1803
1804 /* Build a new shader. */
1805 shader = CALLOC_STRUCT(si_shader);
1806 if (!shader) {
1807 mtx_unlock(&sel->mutex);
1808 return -ENOMEM;
1809 }
1810
1811 util_queue_fence_init(&shader->ready);
1812
1813 shader->selector = sel;
1814 shader->key = *key;
1815 shader->compiler_ctx_state = *compiler_state;
1816
1817 /* If this is a merged shader, get the first shader's selector. */
1818 if (sscreen->info.chip_class >= GFX9) {
1819 if (sel->type == PIPE_SHADER_TESS_CTRL)
1820 previous_stage_sel = key->part.tcs.ls;
1821 else if (sel->type == PIPE_SHADER_GEOMETRY)
1822 previous_stage_sel = key->part.gs.es;
1823
1824 /* We need to wait for the previous shader. */
1825 if (previous_stage_sel && thread_index < 0)
1826 util_queue_fence_wait(&previous_stage_sel->ready);
1827 }
1828
1829 /* Compile the main shader part if it doesn't exist. This can happen
1830 * if the initial guess was wrong. */
1831 bool is_pure_monolithic =
1832 sscreen->use_monolithic_shaders ||
1833 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1834
1835 if (!is_pure_monolithic) {
1836 bool ok;
1837
1838 /* Make sure the main shader part is present. This is needed
1839 * for shaders that can be compiled as VS, LS, or ES, and only
1840 * one of them is compiled at creation.
1841 *
1842 * For merged shaders, check that the starting shader's main
1843 * part is present.
1844 */
1845 if (previous_stage_sel) {
1846 struct si_shader_key shader1_key = zeroed;
1847
1848 if (sel->type == PIPE_SHADER_TESS_CTRL)
1849 shader1_key.as_ls = 1;
1850 else if (sel->type == PIPE_SHADER_GEOMETRY)
1851 shader1_key.as_es = 1;
1852 else
1853 assert(0);
1854
1855 mtx_lock(&previous_stage_sel->mutex);
1856 ok = si_check_missing_main_part(sscreen,
1857 previous_stage_sel,
1858 compiler_state, &shader1_key);
1859 mtx_unlock(&previous_stage_sel->mutex);
1860 } else {
1861 ok = si_check_missing_main_part(sscreen, sel,
1862 compiler_state, key);
1863 }
1864 if (!ok) {
1865 FREE(shader);
1866 mtx_unlock(&sel->mutex);
1867 return -ENOMEM; /* skip the draw call */
1868 }
1869 }
1870
1871 /* Keep the reference to the 1st shader of merged shaders, so that
1872 * Gallium can't destroy it before we destroy the 2nd shader.
1873 *
1874 * Set sctx = NULL, because it's unused if we're not releasing
1875 * the shader, and we don't have any sctx here.
1876 */
1877 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
1878 previous_stage_sel);
1879
1880 /* Monolithic-only shaders don't make a distinction between optimized
1881 * and unoptimized. */
1882 shader->is_monolithic =
1883 is_pure_monolithic ||
1884 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1885
1886 shader->is_optimized =
1887 !is_pure_monolithic &&
1888 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1889
1890 /* If it's an optimized shader, compile it asynchronously. */
1891 if (shader->is_optimized &&
1892 !is_pure_monolithic &&
1893 thread_index < 0) {
1894 /* Compile it asynchronously. */
1895 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
1896 shader, &shader->ready,
1897 si_build_shader_variant_low_priority, NULL);
1898
1899 /* Add only after the ready fence was reset, to guard against a
1900 * race with si_bind_XX_shader. */
1901 if (!sel->last_variant) {
1902 sel->first_variant = shader;
1903 sel->last_variant = shader;
1904 } else {
1905 sel->last_variant->next_variant = shader;
1906 sel->last_variant = shader;
1907 }
1908
1909 /* Use the default (unoptimized) shader for now. */
1910 memset(&key->opt, 0, sizeof(key->opt));
1911 mtx_unlock(&sel->mutex);
1912 goto again;
1913 }
1914
1915 /* Reset the fence before adding to the variant list. */
1916 util_queue_fence_reset(&shader->ready);
1917
1918 if (!sel->last_variant) {
1919 sel->first_variant = shader;
1920 sel->last_variant = shader;
1921 } else {
1922 sel->last_variant->next_variant = shader;
1923 sel->last_variant = shader;
1924 }
1925
1926 mtx_unlock(&sel->mutex);
1927
1928 assert(!shader->is_optimized);
1929 si_build_shader_variant(shader, thread_index, false);
1930
1931 util_queue_fence_signal(&shader->ready);
1932
1933 if (!shader->compilation_failed)
1934 state->current = shader;
1935
1936 return shader->compilation_failed ? -1 : 0;
1937 }
1938
1939 static int si_shader_select(struct pipe_context *ctx,
1940 struct si_shader_ctx_state *state,
1941 struct si_compiler_ctx_state *compiler_state)
1942 {
1943 struct si_context *sctx = (struct si_context *)ctx;
1944 struct si_shader_key key;
1945
1946 si_shader_selector_key(ctx, state->cso, &key);
1947 return si_shader_select_with_key(sctx->screen, state, compiler_state,
1948 &key, -1);
1949 }
1950
1951 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1952 bool streamout,
1953 struct si_shader_key *key)
1954 {
1955 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1956
1957 switch (info->processor) {
1958 case PIPE_SHADER_VERTEX:
1959 switch (next_shader) {
1960 case PIPE_SHADER_GEOMETRY:
1961 key->as_es = 1;
1962 break;
1963 case PIPE_SHADER_TESS_CTRL:
1964 case PIPE_SHADER_TESS_EVAL:
1965 key->as_ls = 1;
1966 break;
1967 default:
1968 /* If POSITION isn't written, it can only be a HW VS
1969 * if streamout is used. If streamout isn't used,
1970 * assume that it's a HW LS. (the next shader is TCS)
1971 * This heuristic is needed for separate shader objects.
1972 */
1973 if (!info->writes_position && !streamout)
1974 key->as_ls = 1;
1975 }
1976 break;
1977
1978 case PIPE_SHADER_TESS_EVAL:
1979 if (next_shader == PIPE_SHADER_GEOMETRY ||
1980 !info->writes_position)
1981 key->as_es = 1;
1982 break;
1983 }
1984 }
1985
1986 /**
1987 * Compile the main shader part or the monolithic shader as part of
1988 * si_shader_selector initialization. Since it can be done asynchronously,
1989 * there is no way to report compile failures to applications.
1990 */
1991 static void si_init_shader_selector_async(void *job, int thread_index)
1992 {
1993 struct si_shader_selector *sel = (struct si_shader_selector *)job;
1994 struct si_screen *sscreen = sel->screen;
1995 struct ac_llvm_compiler *compiler;
1996 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
1997
1998 assert(!debug->debug_message || debug->async);
1999 assert(thread_index >= 0);
2000 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2001 compiler = &sscreen->compiler[thread_index];
2002
2003 /* Compile the main shader part for use with a prolog and/or epilog.
2004 * If this fails, the driver will try to compile a monolithic shader
2005 * on demand.
2006 */
2007 if (!sscreen->use_monolithic_shaders) {
2008 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2009 void *ir_binary = NULL;
2010
2011 if (!shader) {
2012 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2013 return;
2014 }
2015
2016 /* We can leave the fence signaled because use of the default
2017 * main part is guarded by the selector's ready fence. */
2018 util_queue_fence_init(&shader->ready);
2019
2020 shader->selector = sel;
2021 shader->is_monolithic = false;
2022 si_parse_next_shader_property(&sel->info,
2023 sel->so.num_outputs != 0,
2024 &shader->key);
2025
2026 if (sel->tokens || sel->nir)
2027 ir_binary = si_get_ir_binary(sel);
2028
2029 /* Try to load the shader from the shader cache. */
2030 mtx_lock(&sscreen->shader_cache_mutex);
2031
2032 if (ir_binary &&
2033 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
2034 mtx_unlock(&sscreen->shader_cache_mutex);
2035 si_shader_dump_stats_for_shader_db(shader, debug);
2036 } else {
2037 mtx_unlock(&sscreen->shader_cache_mutex);
2038
2039 /* Compile the shader if it hasn't been loaded from the cache. */
2040 if (si_compile_tgsi_shader(sscreen, compiler, shader,
2041 debug) != 0) {
2042 FREE(shader);
2043 FREE(ir_binary);
2044 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2045 return;
2046 }
2047
2048 if (ir_binary) {
2049 mtx_lock(&sscreen->shader_cache_mutex);
2050 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
2051 FREE(ir_binary);
2052 mtx_unlock(&sscreen->shader_cache_mutex);
2053 }
2054 }
2055
2056 *si_get_main_shader_part(sel, &shader->key) = shader;
2057
2058 /* Unset "outputs_written" flags for outputs converted to
2059 * DEFAULT_VAL, so that later inter-shader optimizations don't
2060 * try to eliminate outputs that don't exist in the final
2061 * shader.
2062 *
2063 * This is only done if non-monolithic shaders are enabled.
2064 */
2065 if ((sel->type == PIPE_SHADER_VERTEX ||
2066 sel->type == PIPE_SHADER_TESS_EVAL) &&
2067 !shader->key.as_ls &&
2068 !shader->key.as_es) {
2069 unsigned i;
2070
2071 for (i = 0; i < sel->info.num_outputs; i++) {
2072 unsigned offset = shader->info.vs_output_param_offset[i];
2073
2074 if (offset <= AC_EXP_PARAM_OFFSET_31)
2075 continue;
2076
2077 unsigned name = sel->info.output_semantic_name[i];
2078 unsigned index = sel->info.output_semantic_index[i];
2079 unsigned id;
2080
2081 switch (name) {
2082 case TGSI_SEMANTIC_GENERIC:
2083 /* don't process indices the function can't handle */
2084 if (index >= SI_MAX_IO_GENERIC)
2085 break;
2086 /* fall through */
2087 default:
2088 id = si_shader_io_get_unique_index(name, index, true);
2089 sel->outputs_written_before_ps &= ~(1ull << id);
2090 break;
2091 case TGSI_SEMANTIC_POSITION: /* ignore these */
2092 case TGSI_SEMANTIC_PSIZE:
2093 case TGSI_SEMANTIC_CLIPVERTEX:
2094 case TGSI_SEMANTIC_EDGEFLAG:
2095 break;
2096 }
2097 }
2098 }
2099 }
2100
2101 /* The GS copy shader is always pre-compiled. */
2102 if (sel->type == PIPE_SHADER_GEOMETRY) {
2103 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2104 if (!sel->gs_copy_shader) {
2105 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2106 return;
2107 }
2108
2109 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2110 }
2111 }
2112
2113 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2114 struct util_queue_fence *ready_fence,
2115 struct si_compiler_ctx_state *compiler_ctx_state,
2116 void *job, util_queue_execute_func execute)
2117 {
2118 util_queue_fence_init(ready_fence);
2119
2120 struct util_async_debug_callback async_debug;
2121 bool wait =
2122 (sctx->debug.debug_message && !sctx->debug.async) ||
2123 sctx->is_debug ||
2124 si_can_dump_shader(sctx->screen, processor);
2125
2126 if (wait) {
2127 u_async_debug_init(&async_debug);
2128 compiler_ctx_state->debug = async_debug.base;
2129 }
2130
2131 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2132 ready_fence, execute, NULL);
2133
2134 if (wait) {
2135 util_queue_fence_wait(ready_fence);
2136 u_async_debug_drain(&async_debug, &sctx->debug);
2137 u_async_debug_cleanup(&async_debug);
2138 }
2139 }
2140
2141 /* Return descriptor slot usage masks from the given shader info. */
2142 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2143 uint32_t *const_and_shader_buffers,
2144 uint64_t *samplers_and_images)
2145 {
2146 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2147
2148 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2149 num_constbufs = util_last_bit(info->const_buffers_declared);
2150 /* two 8-byte images share one 16-byte slot */
2151 num_images = align(util_last_bit(info->images_declared), 2);
2152 num_samplers = util_last_bit(info->samplers_declared);
2153
2154 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2155 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2156 *const_and_shader_buffers =
2157 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2158
2159 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2160 start = si_get_image_slot(num_images - 1) / 2;
2161 *samplers_and_images =
2162 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2163 }
2164
2165 static void *si_create_shader_selector(struct pipe_context *ctx,
2166 const struct pipe_shader_state *state)
2167 {
2168 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2169 struct si_context *sctx = (struct si_context*)ctx;
2170 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2171 int i;
2172
2173 if (!sel)
2174 return NULL;
2175
2176 pipe_reference_init(&sel->reference, 1);
2177 sel->screen = sscreen;
2178 sel->compiler_ctx_state.debug = sctx->debug;
2179 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2180
2181 sel->so = state->stream_output;
2182
2183 if (state->type == PIPE_SHADER_IR_TGSI) {
2184 sel->tokens = tgsi_dup_tokens(state->tokens);
2185 if (!sel->tokens) {
2186 FREE(sel);
2187 return NULL;
2188 }
2189
2190 tgsi_scan_shader(state->tokens, &sel->info);
2191 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2192 } else {
2193 assert(state->type == PIPE_SHADER_IR_NIR);
2194
2195 sel->nir = state->ir.nir;
2196
2197 si_nir_scan_shader(sel->nir, &sel->info);
2198 si_nir_scan_tess_ctrl(sel->nir, &sel->info, &sel->tcs_info);
2199
2200 si_lower_nir(sel);
2201 }
2202
2203 sel->type = sel->info.processor;
2204 p_atomic_inc(&sscreen->num_shaders_created);
2205 si_get_active_slot_masks(&sel->info,
2206 &sel->active_const_and_shader_buffers,
2207 &sel->active_samplers_and_images);
2208
2209 /* Record which streamout buffers are enabled. */
2210 for (i = 0; i < sel->so.num_outputs; i++) {
2211 sel->enabled_streamout_buffer_mask |=
2212 (1 << sel->so.output[i].output_buffer) <<
2213 (sel->so.output[i].stream * 4);
2214 }
2215
2216 /* The prolog is a no-op if there are no inputs. */
2217 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2218 sel->info.num_inputs &&
2219 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2220
2221 sel->force_correct_derivs_after_kill =
2222 sel->type == PIPE_SHADER_FRAGMENT &&
2223 sel->info.uses_derivatives &&
2224 sel->info.uses_kill &&
2225 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2226
2227 /* Set which opcode uses which (i,j) pair. */
2228 if (sel->info.uses_persp_opcode_interp_centroid)
2229 sel->info.uses_persp_centroid = true;
2230
2231 if (sel->info.uses_linear_opcode_interp_centroid)
2232 sel->info.uses_linear_centroid = true;
2233
2234 if (sel->info.uses_persp_opcode_interp_offset ||
2235 sel->info.uses_persp_opcode_interp_sample)
2236 sel->info.uses_persp_center = true;
2237
2238 if (sel->info.uses_linear_opcode_interp_offset ||
2239 sel->info.uses_linear_opcode_interp_sample)
2240 sel->info.uses_linear_center = true;
2241
2242 switch (sel->type) {
2243 case PIPE_SHADER_GEOMETRY:
2244 sel->gs_output_prim =
2245 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2246 sel->gs_max_out_vertices =
2247 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2248 sel->gs_num_invocations =
2249 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2250 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2251 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2252 sel->gs_max_out_vertices;
2253
2254 sel->max_gs_stream = 0;
2255 for (i = 0; i < sel->so.num_outputs; i++)
2256 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2257 sel->so.output[i].stream);
2258
2259 sel->gs_input_verts_per_prim =
2260 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2261 break;
2262
2263 case PIPE_SHADER_TESS_CTRL:
2264 /* Always reserve space for these. */
2265 sel->patch_outputs_written |=
2266 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2267 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2268 /* fall through */
2269 case PIPE_SHADER_VERTEX:
2270 case PIPE_SHADER_TESS_EVAL:
2271 for (i = 0; i < sel->info.num_outputs; i++) {
2272 unsigned name = sel->info.output_semantic_name[i];
2273 unsigned index = sel->info.output_semantic_index[i];
2274
2275 switch (name) {
2276 case TGSI_SEMANTIC_TESSINNER:
2277 case TGSI_SEMANTIC_TESSOUTER:
2278 case TGSI_SEMANTIC_PATCH:
2279 sel->patch_outputs_written |=
2280 1ull << si_shader_io_get_unique_index_patch(name, index);
2281 break;
2282
2283 case TGSI_SEMANTIC_GENERIC:
2284 /* don't process indices the function can't handle */
2285 if (index >= SI_MAX_IO_GENERIC)
2286 break;
2287 /* fall through */
2288 default:
2289 sel->outputs_written |=
2290 1ull << si_shader_io_get_unique_index(name, index, false);
2291 sel->outputs_written_before_ps |=
2292 1ull << si_shader_io_get_unique_index(name, index, true);
2293 break;
2294 case TGSI_SEMANTIC_EDGEFLAG:
2295 break;
2296 }
2297 }
2298 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2299 sel->lshs_vertex_stride = sel->esgs_itemsize;
2300
2301 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2302 * will start on a different bank. (except for the maximum 32*16).
2303 */
2304 if (sel->lshs_vertex_stride < 32*16)
2305 sel->lshs_vertex_stride += 4;
2306
2307 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2308 * conflicts, i.e. each vertex will start at a different bank.
2309 */
2310 if (sctx->chip_class >= GFX9)
2311 sel->esgs_itemsize += 4;
2312
2313 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2314 break;
2315
2316 case PIPE_SHADER_FRAGMENT:
2317 for (i = 0; i < sel->info.num_inputs; i++) {
2318 unsigned name = sel->info.input_semantic_name[i];
2319 unsigned index = sel->info.input_semantic_index[i];
2320
2321 switch (name) {
2322 case TGSI_SEMANTIC_GENERIC:
2323 /* don't process indices the function can't handle */
2324 if (index >= SI_MAX_IO_GENERIC)
2325 break;
2326 /* fall through */
2327 default:
2328 sel->inputs_read |=
2329 1ull << si_shader_io_get_unique_index(name, index, true);
2330 break;
2331 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2332 break;
2333 }
2334 }
2335
2336 for (i = 0; i < 8; i++)
2337 if (sel->info.colors_written & (1 << i))
2338 sel->colors_written_4bit |= 0xf << (4 * i);
2339
2340 for (i = 0; i < sel->info.num_inputs; i++) {
2341 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2342 int index = sel->info.input_semantic_index[i];
2343 sel->color_attr_index[index] = i;
2344 }
2345 }
2346 break;
2347 }
2348
2349 /* PA_CL_VS_OUT_CNTL */
2350 bool misc_vec_ena =
2351 sel->info.writes_psize || sel->info.writes_edgeflag ||
2352 sel->info.writes_layer || sel->info.writes_viewport_index;
2353 sel->pa_cl_vs_out_cntl =
2354 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2355 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2356 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2357 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2358 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2359 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2360 sel->clipdist_mask = sel->info.writes_clipvertex ?
2361 SIX_BITS : sel->info.clipdist_writemask;
2362 sel->culldist_mask = sel->info.culldist_writemask <<
2363 sel->info.num_written_clipdistance;
2364
2365 /* DB_SHADER_CONTROL */
2366 sel->db_shader_control =
2367 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2368 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2369 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2370 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2371
2372 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2373 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2374 sel->db_shader_control |=
2375 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2376 break;
2377 case TGSI_FS_DEPTH_LAYOUT_LESS:
2378 sel->db_shader_control |=
2379 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2380 break;
2381 }
2382
2383 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2384 *
2385 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2386 * --|-----------|------------|------------|--------------------|-------------------|-------------
2387 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2388 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2389 * 2 | false | true | n/a | LateZ | 1 | 0
2390 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2391 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2392 *
2393 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2394 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2395 *
2396 * Don't use ReZ without profiling !!!
2397 *
2398 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2399 * shaders.
2400 */
2401 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2402 /* Cases 3, 4. */
2403 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2404 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2405 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2406 } else if (sel->info.writes_memory) {
2407 /* Case 2. */
2408 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2409 S_02880C_EXEC_ON_HIER_FAIL(1);
2410 } else {
2411 /* Case 1. */
2412 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2413 }
2414
2415 (void) mtx_init(&sel->mutex, mtx_plain);
2416
2417 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2418 &sel->compiler_ctx_state, sel,
2419 si_init_shader_selector_async);
2420 return sel;
2421 }
2422
2423 static void si_update_streamout_state(struct si_context *sctx)
2424 {
2425 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2426
2427 if (!shader_with_so)
2428 return;
2429
2430 sctx->streamout.enabled_stream_buffers_mask =
2431 shader_with_so->enabled_streamout_buffer_mask;
2432 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2433 }
2434
2435 static void si_update_clip_regs(struct si_context *sctx,
2436 struct si_shader_selector *old_hw_vs,
2437 struct si_shader *old_hw_vs_variant,
2438 struct si_shader_selector *next_hw_vs,
2439 struct si_shader *next_hw_vs_variant)
2440 {
2441 if (next_hw_vs &&
2442 (!old_hw_vs ||
2443 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2444 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2445 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2446 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2447 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2448 !old_hw_vs_variant ||
2449 !next_hw_vs_variant ||
2450 old_hw_vs_variant->key.opt.clip_disable !=
2451 next_hw_vs_variant->key.opt.clip_disable))
2452 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2453 }
2454
2455 static void si_update_common_shader_state(struct si_context *sctx)
2456 {
2457 sctx->uses_bindless_samplers =
2458 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2459 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2460 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2461 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2462 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2463 sctx->uses_bindless_images =
2464 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2465 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2466 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2467 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2468 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2469 sctx->do_update_shaders = true;
2470 }
2471
2472 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2473 {
2474 struct si_context *sctx = (struct si_context *)ctx;
2475 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2476 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2477 struct si_shader_selector *sel = state;
2478
2479 if (sctx->vs_shader.cso == sel)
2480 return;
2481
2482 sctx->vs_shader.cso = sel;
2483 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2484 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2485
2486 si_update_common_shader_state(sctx);
2487 si_update_vs_viewport_state(sctx);
2488 si_set_active_descriptors_for_shader(sctx, sel);
2489 si_update_streamout_state(sctx);
2490 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2491 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2492 }
2493
2494 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2495 {
2496 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2497 (sctx->tes_shader.cso &&
2498 sctx->tes_shader.cso->info.uses_primid) ||
2499 (sctx->tcs_shader.cso &&
2500 sctx->tcs_shader.cso->info.uses_primid) ||
2501 (sctx->gs_shader.cso &&
2502 sctx->gs_shader.cso->info.uses_primid) ||
2503 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2504 sctx->ps_shader.cso->info.uses_primid);
2505 }
2506
2507 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2508 {
2509 struct si_context *sctx = (struct si_context *)ctx;
2510 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2511 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2512 struct si_shader_selector *sel = state;
2513 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2514
2515 if (sctx->gs_shader.cso == sel)
2516 return;
2517
2518 sctx->gs_shader.cso = sel;
2519 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2520 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2521
2522 si_update_common_shader_state(sctx);
2523 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2524
2525 if (enable_changed) {
2526 si_shader_change_notify(sctx);
2527 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2528 si_update_tess_uses_prim_id(sctx);
2529 }
2530 si_update_vs_viewport_state(sctx);
2531 si_set_active_descriptors_for_shader(sctx, sel);
2532 si_update_streamout_state(sctx);
2533 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2534 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2535 }
2536
2537 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2538 {
2539 struct si_context *sctx = (struct si_context *)ctx;
2540 struct si_shader_selector *sel = state;
2541 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2542
2543 if (sctx->tcs_shader.cso == sel)
2544 return;
2545
2546 sctx->tcs_shader.cso = sel;
2547 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
2548 si_update_tess_uses_prim_id(sctx);
2549
2550 si_update_common_shader_state(sctx);
2551
2552 if (enable_changed)
2553 sctx->last_tcs = NULL; /* invalidate derived tess state */
2554
2555 si_set_active_descriptors_for_shader(sctx, sel);
2556 }
2557
2558 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
2559 {
2560 struct si_context *sctx = (struct si_context *)ctx;
2561 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2562 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2563 struct si_shader_selector *sel = state;
2564 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
2565
2566 if (sctx->tes_shader.cso == sel)
2567 return;
2568
2569 sctx->tes_shader.cso = sel;
2570 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
2571 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
2572 si_update_tess_uses_prim_id(sctx);
2573
2574 si_update_common_shader_state(sctx);
2575 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2576
2577 if (enable_changed) {
2578 si_shader_change_notify(sctx);
2579 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
2580 }
2581 si_update_vs_viewport_state(sctx);
2582 si_set_active_descriptors_for_shader(sctx, sel);
2583 si_update_streamout_state(sctx);
2584 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2585 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2586 }
2587
2588 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2589 {
2590 struct si_context *sctx = (struct si_context *)ctx;
2591 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
2592 struct si_shader_selector *sel = state;
2593
2594 /* skip if supplied shader is one already in use */
2595 if (old_sel == sel)
2596 return;
2597
2598 sctx->ps_shader.cso = sel;
2599 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
2600
2601 si_update_common_shader_state(sctx);
2602 if (sel) {
2603 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2604 si_update_tess_uses_prim_id(sctx);
2605
2606 if (!old_sel ||
2607 old_sel->info.colors_written != sel->info.colors_written)
2608 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2609
2610 if (sctx->screen->has_out_of_order_rast &&
2611 (!old_sel ||
2612 old_sel->info.writes_memory != sel->info.writes_memory ||
2613 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
2614 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
2615 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2616 }
2617 si_set_active_descriptors_for_shader(sctx, sel);
2618 si_update_ps_colorbuf0_slot(sctx);
2619 }
2620
2621 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
2622 {
2623 if (shader->is_optimized) {
2624 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
2625 &shader->ready);
2626 }
2627
2628 util_queue_fence_destroy(&shader->ready);
2629
2630 if (shader->pm4) {
2631 switch (shader->selector->type) {
2632 case PIPE_SHADER_VERTEX:
2633 if (shader->key.as_ls) {
2634 assert(sctx->chip_class <= VI);
2635 si_pm4_delete_state(sctx, ls, shader->pm4);
2636 } else if (shader->key.as_es) {
2637 assert(sctx->chip_class <= VI);
2638 si_pm4_delete_state(sctx, es, shader->pm4);
2639 } else {
2640 si_pm4_delete_state(sctx, vs, shader->pm4);
2641 }
2642 break;
2643 case PIPE_SHADER_TESS_CTRL:
2644 si_pm4_delete_state(sctx, hs, shader->pm4);
2645 break;
2646 case PIPE_SHADER_TESS_EVAL:
2647 if (shader->key.as_es) {
2648 assert(sctx->chip_class <= VI);
2649 si_pm4_delete_state(sctx, es, shader->pm4);
2650 } else {
2651 si_pm4_delete_state(sctx, vs, shader->pm4);
2652 }
2653 break;
2654 case PIPE_SHADER_GEOMETRY:
2655 if (shader->is_gs_copy_shader)
2656 si_pm4_delete_state(sctx, vs, shader->pm4);
2657 else
2658 si_pm4_delete_state(sctx, gs, shader->pm4);
2659 break;
2660 case PIPE_SHADER_FRAGMENT:
2661 si_pm4_delete_state(sctx, ps, shader->pm4);
2662 break;
2663 }
2664 }
2665
2666 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
2667 si_shader_destroy(shader);
2668 free(shader);
2669 }
2670
2671 void si_destroy_shader_selector(struct si_context *sctx,
2672 struct si_shader_selector *sel)
2673 {
2674 struct si_shader *p = sel->first_variant, *c;
2675 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
2676 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
2677 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
2678 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
2679 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
2680 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
2681 };
2682
2683 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
2684
2685 if (current_shader[sel->type]->cso == sel) {
2686 current_shader[sel->type]->cso = NULL;
2687 current_shader[sel->type]->current = NULL;
2688 }
2689
2690 while (p) {
2691 c = p->next_variant;
2692 si_delete_shader(sctx, p);
2693 p = c;
2694 }
2695
2696 if (sel->main_shader_part)
2697 si_delete_shader(sctx, sel->main_shader_part);
2698 if (sel->main_shader_part_ls)
2699 si_delete_shader(sctx, sel->main_shader_part_ls);
2700 if (sel->main_shader_part_es)
2701 si_delete_shader(sctx, sel->main_shader_part_es);
2702 if (sel->gs_copy_shader)
2703 si_delete_shader(sctx, sel->gs_copy_shader);
2704
2705 util_queue_fence_destroy(&sel->ready);
2706 mtx_destroy(&sel->mutex);
2707 free(sel->tokens);
2708 ralloc_free(sel->nir);
2709 free(sel);
2710 }
2711
2712 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
2713 {
2714 struct si_context *sctx = (struct si_context *)ctx;
2715 struct si_shader_selector *sel = (struct si_shader_selector *)state;
2716
2717 si_shader_selector_reference(sctx, &sel, NULL);
2718 }
2719
2720 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
2721 struct si_shader *vs, unsigned name,
2722 unsigned index, unsigned interpolate)
2723 {
2724 struct tgsi_shader_info *vsinfo = &vs->selector->info;
2725 unsigned j, offset, ps_input_cntl = 0;
2726
2727 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
2728 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
2729 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2730
2731 if (name == TGSI_SEMANTIC_PCOORD ||
2732 (name == TGSI_SEMANTIC_TEXCOORD &&
2733 sctx->sprite_coord_enable & (1 << index))) {
2734 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
2735 }
2736
2737 for (j = 0; j < vsinfo->num_outputs; j++) {
2738 if (name == vsinfo->output_semantic_name[j] &&
2739 index == vsinfo->output_semantic_index[j]) {
2740 offset = vs->info.vs_output_param_offset[j];
2741
2742 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2743 /* The input is loaded from parameter memory. */
2744 ps_input_cntl |= S_028644_OFFSET(offset);
2745 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2746 if (offset == AC_EXP_PARAM_UNDEFINED) {
2747 /* This can happen with depth-only rendering. */
2748 offset = 0;
2749 } else {
2750 /* The input is a DEFAULT_VAL constant. */
2751 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2752 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2753 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2754 }
2755
2756 ps_input_cntl = S_028644_OFFSET(0x20) |
2757 S_028644_DEFAULT_VAL(offset);
2758 }
2759 break;
2760 }
2761 }
2762
2763 if (name == TGSI_SEMANTIC_PRIMID)
2764 /* PrimID is written after the last output. */
2765 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
2766 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2767 /* No corresponding output found, load defaults into input.
2768 * Don't set any other bits.
2769 * (FLAT_SHADE=1 completely changes behavior) */
2770 ps_input_cntl = S_028644_OFFSET(0x20);
2771 /* D3D 9 behaviour. GL is undefined */
2772 if (name == TGSI_SEMANTIC_COLOR && index == 0)
2773 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
2774 }
2775 return ps_input_cntl;
2776 }
2777
2778 static void si_emit_spi_map(struct si_context *sctx)
2779 {
2780 struct si_shader *ps = sctx->ps_shader.current;
2781 struct si_shader *vs = si_get_vs_state(sctx);
2782 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
2783 unsigned i, num_interp, num_written = 0, bcol_interp[2];
2784 unsigned spi_ps_input_cntl[32];
2785
2786 if (!ps || !ps->selector->info.num_inputs)
2787 return;
2788
2789 num_interp = si_get_ps_num_interp(ps);
2790 assert(num_interp > 0);
2791
2792 for (i = 0; i < psinfo->num_inputs; i++) {
2793 unsigned name = psinfo->input_semantic_name[i];
2794 unsigned index = psinfo->input_semantic_index[i];
2795 unsigned interpolate = psinfo->input_interpolate[i];
2796
2797 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
2798 index, interpolate);
2799
2800 if (name == TGSI_SEMANTIC_COLOR) {
2801 assert(index < ARRAY_SIZE(bcol_interp));
2802 bcol_interp[index] = interpolate;
2803 }
2804 }
2805
2806 if (ps->key.part.ps.prolog.color_two_side) {
2807 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
2808
2809 for (i = 0; i < 2; i++) {
2810 if (!(psinfo->colors_read & (0xf << (i * 4))))
2811 continue;
2812
2813 spi_ps_input_cntl[num_written++] =
2814 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
2815
2816 }
2817 }
2818 assert(num_interp == num_written);
2819
2820 /* R_028644_SPI_PS_INPUT_CNTL_0 */
2821 /* Dota 2: Only ~16% of SPI map updates set different values. */
2822 /* Talos: Only ~9% of SPI map updates set different values. */
2823 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
2824 spi_ps_input_cntl,
2825 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
2826 }
2827
2828 /**
2829 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2830 */
2831 static void si_init_config_add_vgt_flush(struct si_context *sctx)
2832 {
2833 if (sctx->init_config_has_vgt_flush)
2834 return;
2835
2836 /* Done by Vulkan before VGT_FLUSH. */
2837 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2838 si_pm4_cmd_add(sctx->init_config,
2839 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2840 si_pm4_cmd_end(sctx->init_config, false);
2841
2842 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2843 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2844 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2845 si_pm4_cmd_end(sctx->init_config, false);
2846 sctx->init_config_has_vgt_flush = true;
2847 }
2848
2849 /* Initialize state related to ESGS / GSVS ring buffers */
2850 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2851 {
2852 struct si_shader_selector *es =
2853 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2854 struct si_shader_selector *gs = sctx->gs_shader.cso;
2855 struct si_pm4_state *pm4;
2856
2857 /* Chip constants. */
2858 unsigned num_se = sctx->screen->info.max_se;
2859 unsigned wave_size = 64;
2860 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2861 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2862 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2863 */
2864 unsigned gs_vertex_reuse = (sctx->chip_class >= VI ? 32 : 16) * num_se;
2865 unsigned alignment = 256 * num_se;
2866 /* The maximum size is 63.999 MB per SE. */
2867 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2868
2869 /* Calculate the minimum size. */
2870 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
2871 wave_size, alignment);
2872
2873 /* These are recommended sizes, not minimum sizes. */
2874 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2875 es->esgs_itemsize * gs->gs_input_verts_per_prim;
2876 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2877 gs->max_gsvs_emit_size;
2878
2879 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2880 esgs_ring_size = align(esgs_ring_size, alignment);
2881 gsvs_ring_size = align(gsvs_ring_size, alignment);
2882
2883 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2884 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2885
2886 /* Some rings don't have to be allocated if shaders don't use them.
2887 * (e.g. no varyings between ES and GS or GS and VS)
2888 *
2889 * GFX9 doesn't have the ESGS ring.
2890 */
2891 bool update_esgs = sctx->chip_class <= VI &&
2892 esgs_ring_size &&
2893 (!sctx->esgs_ring ||
2894 sctx->esgs_ring->width0 < esgs_ring_size);
2895 bool update_gsvs = gsvs_ring_size &&
2896 (!sctx->gsvs_ring ||
2897 sctx->gsvs_ring->width0 < gsvs_ring_size);
2898
2899 if (!update_esgs && !update_gsvs)
2900 return true;
2901
2902 if (update_esgs) {
2903 pipe_resource_reference(&sctx->esgs_ring, NULL);
2904 sctx->esgs_ring =
2905 pipe_aligned_buffer_create(sctx->b.screen,
2906 SI_RESOURCE_FLAG_UNMAPPABLE,
2907 PIPE_USAGE_DEFAULT,
2908 esgs_ring_size, alignment);
2909 if (!sctx->esgs_ring)
2910 return false;
2911 }
2912
2913 if (update_gsvs) {
2914 pipe_resource_reference(&sctx->gsvs_ring, NULL);
2915 sctx->gsvs_ring =
2916 pipe_aligned_buffer_create(sctx->b.screen,
2917 SI_RESOURCE_FLAG_UNMAPPABLE,
2918 PIPE_USAGE_DEFAULT,
2919 gsvs_ring_size, alignment);
2920 if (!sctx->gsvs_ring)
2921 return false;
2922 }
2923
2924 /* Create the "init_config_gs_rings" state. */
2925 pm4 = CALLOC_STRUCT(si_pm4_state);
2926 if (!pm4)
2927 return false;
2928
2929 if (sctx->chip_class >= CIK) {
2930 if (sctx->esgs_ring) {
2931 assert(sctx->chip_class <= VI);
2932 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2933 sctx->esgs_ring->width0 / 256);
2934 }
2935 if (sctx->gsvs_ring)
2936 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2937 sctx->gsvs_ring->width0 / 256);
2938 } else {
2939 if (sctx->esgs_ring)
2940 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2941 sctx->esgs_ring->width0 / 256);
2942 if (sctx->gsvs_ring)
2943 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2944 sctx->gsvs_ring->width0 / 256);
2945 }
2946
2947 /* Set the state. */
2948 if (sctx->init_config_gs_rings)
2949 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
2950 sctx->init_config_gs_rings = pm4;
2951
2952 if (!sctx->init_config_has_vgt_flush) {
2953 si_init_config_add_vgt_flush(sctx);
2954 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2955 }
2956
2957 /* Flush the context to re-emit both init_config states. */
2958 sctx->initial_gfx_cs_size = 0; /* force flush */
2959 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
2960
2961 /* Set ring bindings. */
2962 if (sctx->esgs_ring) {
2963 assert(sctx->chip_class <= VI);
2964 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
2965 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2966 true, true, 4, 64, 0);
2967 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
2968 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2969 false, false, 0, 0, 0);
2970 }
2971 if (sctx->gsvs_ring) {
2972 si_set_ring_buffer(sctx, SI_RING_GSVS,
2973 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
2974 false, false, 0, 0, 0);
2975 }
2976
2977 return true;
2978 }
2979
2980 static void si_shader_lock(struct si_shader *shader)
2981 {
2982 mtx_lock(&shader->selector->mutex);
2983 if (shader->previous_stage_sel) {
2984 assert(shader->previous_stage_sel != shader->selector);
2985 mtx_lock(&shader->previous_stage_sel->mutex);
2986 }
2987 }
2988
2989 static void si_shader_unlock(struct si_shader *shader)
2990 {
2991 if (shader->previous_stage_sel)
2992 mtx_unlock(&shader->previous_stage_sel->mutex);
2993 mtx_unlock(&shader->selector->mutex);
2994 }
2995
2996 /**
2997 * @returns 1 if \p sel has been updated to use a new scratch buffer
2998 * 0 if not
2999 * < 0 if there was a failure
3000 */
3001 static int si_update_scratch_buffer(struct si_context *sctx,
3002 struct si_shader *shader)
3003 {
3004 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3005 int r;
3006
3007 if (!shader)
3008 return 0;
3009
3010 /* This shader doesn't need a scratch buffer */
3011 if (shader->config.scratch_bytes_per_wave == 0)
3012 return 0;
3013
3014 /* Prevent race conditions when updating:
3015 * - si_shader::scratch_bo
3016 * - si_shader::binary::code
3017 * - si_shader::previous_stage::binary::code.
3018 */
3019 si_shader_lock(shader);
3020
3021 /* This shader is already configured to use the current
3022 * scratch buffer. */
3023 if (shader->scratch_bo == sctx->scratch_buffer) {
3024 si_shader_unlock(shader);
3025 return 0;
3026 }
3027
3028 assert(sctx->scratch_buffer);
3029
3030 if (shader->previous_stage)
3031 si_shader_apply_scratch_relocs(shader->previous_stage, scratch_va);
3032
3033 si_shader_apply_scratch_relocs(shader, scratch_va);
3034
3035 /* Replace the shader bo with a new bo that has the relocs applied. */
3036 r = si_shader_binary_upload(sctx->screen, shader);
3037 if (r) {
3038 si_shader_unlock(shader);
3039 return r;
3040 }
3041
3042 /* Update the shader state to use the new shader bo. */
3043 si_shader_init_pm4_state(sctx->screen, shader);
3044
3045 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3046
3047 si_shader_unlock(shader);
3048 return 1;
3049 }
3050
3051 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
3052 {
3053 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
3054 }
3055
3056 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3057 {
3058 return shader ? shader->config.scratch_bytes_per_wave : 0;
3059 }
3060
3061 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3062 {
3063 if (!sctx->tes_shader.cso)
3064 return NULL; /* tessellation disabled */
3065
3066 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3067 sctx->fixed_func_tcs_shader.current;
3068 }
3069
3070 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
3071 {
3072 unsigned bytes = 0;
3073
3074 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3075 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3076 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3077 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3078
3079 if (sctx->tes_shader.cso) {
3080 struct si_shader *tcs = si_get_tcs_current(sctx);
3081
3082 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
3083 }
3084 return bytes;
3085 }
3086
3087 static bool si_update_scratch_relocs(struct si_context *sctx)
3088 {
3089 struct si_shader *tcs = si_get_tcs_current(sctx);
3090 int r;
3091
3092 /* Update the shaders, so that they are using the latest scratch.
3093 * The scratch buffer may have been changed since these shaders were
3094 * last used, so we still need to try to update them, even if they
3095 * require scratch buffers smaller than the current size.
3096 */
3097 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3098 if (r < 0)
3099 return false;
3100 if (r == 1)
3101 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3102
3103 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3104 if (r < 0)
3105 return false;
3106 if (r == 1)
3107 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3108
3109 r = si_update_scratch_buffer(sctx, tcs);
3110 if (r < 0)
3111 return false;
3112 if (r == 1)
3113 si_pm4_bind_state(sctx, hs, tcs->pm4);
3114
3115 /* VS can be bound as LS, ES, or VS. */
3116 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3117 if (r < 0)
3118 return false;
3119 if (r == 1) {
3120 if (sctx->tes_shader.current)
3121 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3122 else if (sctx->gs_shader.current)
3123 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3124 else
3125 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3126 }
3127
3128 /* TES can be bound as ES or VS. */
3129 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3130 if (r < 0)
3131 return false;
3132 if (r == 1) {
3133 if (sctx->gs_shader.current)
3134 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3135 else
3136 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3137 }
3138
3139 return true;
3140 }
3141
3142 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3143 {
3144 unsigned current_scratch_buffer_size =
3145 si_get_current_scratch_buffer_size(sctx);
3146 unsigned scratch_bytes_per_wave =
3147 si_get_max_scratch_bytes_per_wave(sctx);
3148 unsigned scratch_needed_size = scratch_bytes_per_wave *
3149 sctx->scratch_waves;
3150 unsigned spi_tmpring_size;
3151
3152 if (scratch_needed_size > 0) {
3153 if (scratch_needed_size > current_scratch_buffer_size) {
3154 /* Create a bigger scratch buffer */
3155 r600_resource_reference(&sctx->scratch_buffer, NULL);
3156
3157 sctx->scratch_buffer =
3158 si_aligned_buffer_create(&sctx->screen->b,
3159 SI_RESOURCE_FLAG_UNMAPPABLE,
3160 PIPE_USAGE_DEFAULT,
3161 scratch_needed_size, 256);
3162 if (!sctx->scratch_buffer)
3163 return false;
3164
3165 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3166 si_context_add_resource_size(sctx,
3167 &sctx->scratch_buffer->b.b);
3168 }
3169
3170 if (!si_update_scratch_relocs(sctx))
3171 return false;
3172 }
3173
3174 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3175 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3176 "scratch size should already be aligned correctly.");
3177
3178 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3179 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3180 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3181 sctx->spi_tmpring_size = spi_tmpring_size;
3182 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3183 }
3184 return true;
3185 }
3186
3187 static void si_init_tess_factor_ring(struct si_context *sctx)
3188 {
3189 assert(!sctx->tess_rings);
3190
3191 /* The address must be aligned to 2^19, because the shader only
3192 * receives the high 13 bits.
3193 */
3194 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3195 SI_RESOURCE_FLAG_32BIT,
3196 PIPE_USAGE_DEFAULT,
3197 sctx->screen->tess_offchip_ring_size +
3198 sctx->screen->tess_factor_ring_size,
3199 1 << 19);
3200 if (!sctx->tess_rings)
3201 return;
3202
3203 si_init_config_add_vgt_flush(sctx);
3204
3205 si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_rings),
3206 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3207
3208 uint64_t factor_va = r600_resource(sctx->tess_rings)->gpu_address +
3209 sctx->screen->tess_offchip_ring_size;
3210
3211 /* Append these registers to the init config state. */
3212 if (sctx->chip_class >= CIK) {
3213 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3214 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3215 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3216 factor_va >> 8);
3217 if (sctx->chip_class >= GFX9)
3218 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3219 S_030944_BASE_HI(factor_va >> 40));
3220 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3221 sctx->screen->vgt_hs_offchip_param);
3222 } else {
3223 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3224 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3225 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3226 factor_va >> 8);
3227 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3228 sctx->screen->vgt_hs_offchip_param);
3229 }
3230
3231 /* Flush the context to re-emit the init_config state.
3232 * This is done only once in a lifetime of a context.
3233 */
3234 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3235 sctx->initial_gfx_cs_size = 0; /* force flush */
3236 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3237 }
3238
3239 static void si_update_vgt_shader_config(struct si_context *sctx)
3240 {
3241 /* Calculate the index of the config.
3242 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3243 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
3244 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
3245
3246 if (!*pm4) {
3247 uint32_t stages = 0;
3248
3249 *pm4 = CALLOC_STRUCT(si_pm4_state);
3250
3251 if (sctx->tes_shader.cso) {
3252 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3253 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3254
3255 if (sctx->gs_shader.cso)
3256 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3257 S_028B54_GS_EN(1) |
3258 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3259 else
3260 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3261 } else if (sctx->gs_shader.cso) {
3262 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3263 S_028B54_GS_EN(1) |
3264 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3265 }
3266
3267 if (sctx->chip_class >= GFX9)
3268 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3269
3270 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3271 }
3272 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3273 }
3274
3275 bool si_update_shaders(struct si_context *sctx)
3276 {
3277 struct pipe_context *ctx = (struct pipe_context*)sctx;
3278 struct si_compiler_ctx_state compiler_state;
3279 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3280 struct si_shader *old_vs = si_get_vs_state(sctx);
3281 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3282 struct si_shader *old_ps = sctx->ps_shader.current;
3283 unsigned old_spi_shader_col_format =
3284 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3285 int r;
3286
3287 compiler_state.compiler = &sctx->compiler;
3288 compiler_state.debug = sctx->debug;
3289 compiler_state.is_debug_context = sctx->is_debug;
3290
3291 /* Update stages before GS. */
3292 if (sctx->tes_shader.cso) {
3293 if (!sctx->tess_rings) {
3294 si_init_tess_factor_ring(sctx);
3295 if (!sctx->tess_rings)
3296 return false;
3297 }
3298
3299 /* VS as LS */
3300 if (sctx->chip_class <= VI) {
3301 r = si_shader_select(ctx, &sctx->vs_shader,
3302 &compiler_state);
3303 if (r)
3304 return false;
3305 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3306 }
3307
3308 if (sctx->tcs_shader.cso) {
3309 r = si_shader_select(ctx, &sctx->tcs_shader,
3310 &compiler_state);
3311 if (r)
3312 return false;
3313 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3314 } else {
3315 if (!sctx->fixed_func_tcs_shader.cso) {
3316 sctx->fixed_func_tcs_shader.cso =
3317 si_create_fixed_func_tcs(sctx);
3318 if (!sctx->fixed_func_tcs_shader.cso)
3319 return false;
3320 }
3321
3322 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3323 &compiler_state);
3324 if (r)
3325 return false;
3326 si_pm4_bind_state(sctx, hs,
3327 sctx->fixed_func_tcs_shader.current->pm4);
3328 }
3329
3330 if (sctx->gs_shader.cso) {
3331 /* TES as ES */
3332 if (sctx->chip_class <= VI) {
3333 r = si_shader_select(ctx, &sctx->tes_shader,
3334 &compiler_state);
3335 if (r)
3336 return false;
3337 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3338 }
3339 } else {
3340 /* TES as VS */
3341 r = si_shader_select(ctx, &sctx->tes_shader,
3342 &compiler_state);
3343 if (r)
3344 return false;
3345 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3346 }
3347 } else if (sctx->gs_shader.cso) {
3348 if (sctx->chip_class <= VI) {
3349 /* VS as ES */
3350 r = si_shader_select(ctx, &sctx->vs_shader,
3351 &compiler_state);
3352 if (r)
3353 return false;
3354 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3355
3356 si_pm4_bind_state(sctx, ls, NULL);
3357 si_pm4_bind_state(sctx, hs, NULL);
3358 }
3359 } else {
3360 /* VS as VS */
3361 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
3362 if (r)
3363 return false;
3364 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3365 si_pm4_bind_state(sctx, ls, NULL);
3366 si_pm4_bind_state(sctx, hs, NULL);
3367 }
3368
3369 /* Update GS. */
3370 if (sctx->gs_shader.cso) {
3371 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
3372 if (r)
3373 return false;
3374 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3375 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3376
3377 if (!si_update_gs_ring_buffers(sctx))
3378 return false;
3379 } else {
3380 si_pm4_bind_state(sctx, gs, NULL);
3381 if (sctx->chip_class <= VI)
3382 si_pm4_bind_state(sctx, es, NULL);
3383 }
3384
3385 si_update_vgt_shader_config(sctx);
3386
3387 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3388 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3389
3390 if (sctx->ps_shader.cso) {
3391 unsigned db_shader_control;
3392
3393 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
3394 if (r)
3395 return false;
3396 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3397
3398 db_shader_control =
3399 sctx->ps_shader.cso->db_shader_control |
3400 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3401
3402 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3403 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3404 sctx->flatshade != rs->flatshade) {
3405 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3406 sctx->flatshade = rs->flatshade;
3407 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3408 }
3409
3410 if (sctx->screen->rbplus_allowed &&
3411 si_pm4_state_changed(sctx, ps) &&
3412 (!old_ps ||
3413 old_spi_shader_col_format !=
3414 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3415 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3416
3417 if (sctx->ps_db_shader_control != db_shader_control) {
3418 sctx->ps_db_shader_control = db_shader_control;
3419 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3420 if (sctx->screen->dpbb_allowed)
3421 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3422 }
3423
3424 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3425 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3426 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3427
3428 if (sctx->chip_class == SI)
3429 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3430
3431 if (sctx->framebuffer.nr_samples <= 1)
3432 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3433 }
3434 }
3435
3436 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3437 si_pm4_state_enabled_and_changed(sctx, hs) ||
3438 si_pm4_state_enabled_and_changed(sctx, es) ||
3439 si_pm4_state_enabled_and_changed(sctx, gs) ||
3440 si_pm4_state_enabled_and_changed(sctx, vs) ||
3441 si_pm4_state_enabled_and_changed(sctx, ps)) {
3442 if (!si_update_spi_tmpring_size(sctx))
3443 return false;
3444 }
3445
3446 if (sctx->chip_class >= CIK) {
3447 if (si_pm4_state_enabled_and_changed(sctx, ls))
3448 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3449 else if (!sctx->queued.named.ls)
3450 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3451
3452 if (si_pm4_state_enabled_and_changed(sctx, hs))
3453 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3454 else if (!sctx->queued.named.hs)
3455 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3456
3457 if (si_pm4_state_enabled_and_changed(sctx, es))
3458 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
3459 else if (!sctx->queued.named.es)
3460 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
3461
3462 if (si_pm4_state_enabled_and_changed(sctx, gs))
3463 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
3464 else if (!sctx->queued.named.gs)
3465 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
3466
3467 if (si_pm4_state_enabled_and_changed(sctx, vs))
3468 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
3469 else if (!sctx->queued.named.vs)
3470 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
3471
3472 if (si_pm4_state_enabled_and_changed(sctx, ps))
3473 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
3474 else if (!sctx->queued.named.ps)
3475 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
3476 }
3477
3478 sctx->do_update_shaders = false;
3479 return true;
3480 }
3481
3482 static void si_emit_scratch_state(struct si_context *sctx)
3483 {
3484 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3485
3486 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3487 sctx->spi_tmpring_size);
3488
3489 if (sctx->scratch_buffer) {
3490 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3491 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3492 RADEON_PRIO_SCRATCH_BUFFER);
3493 }
3494 }
3495
3496 void si_init_shader_functions(struct si_context *sctx)
3497 {
3498 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
3499 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
3500
3501 sctx->b.create_vs_state = si_create_shader_selector;
3502 sctx->b.create_tcs_state = si_create_shader_selector;
3503 sctx->b.create_tes_state = si_create_shader_selector;
3504 sctx->b.create_gs_state = si_create_shader_selector;
3505 sctx->b.create_fs_state = si_create_shader_selector;
3506
3507 sctx->b.bind_vs_state = si_bind_vs_shader;
3508 sctx->b.bind_tcs_state = si_bind_tcs_shader;
3509 sctx->b.bind_tes_state = si_bind_tes_shader;
3510 sctx->b.bind_gs_state = si_bind_gs_shader;
3511 sctx->b.bind_fs_state = si_bind_ps_shader;
3512
3513 sctx->b.delete_vs_state = si_delete_shader_selector;
3514 sctx->b.delete_tcs_state = si_delete_shader_selector;
3515 sctx->b.delete_tes_state = si_delete_shader_selector;
3516 sctx->b.delete_gs_state = si_delete_shader_selector;
3517 sctx->b.delete_fs_state = si_delete_shader_selector;
3518 }