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radeonsi: write all MRTs only if there is exactly one output
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "si_shader.h"
30 #include "sid.h"
31 #include "radeon/r600_cs.h"
32
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/u_memory.h"
36 #include "util/u_prim.h"
37 #include "util/u_simple_shaders.h"
38
39 static void si_set_tesseval_regs(struct si_shader *shader,
40 struct si_pm4_state *pm4)
41 {
42 struct tgsi_shader_info *info = &shader->selector->info;
43 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
44 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
45 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
46 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
47 unsigned type, partitioning, topology;
48
49 switch (tes_prim_mode) {
50 case PIPE_PRIM_LINES:
51 type = V_028B6C_TESS_ISOLINE;
52 break;
53 case PIPE_PRIM_TRIANGLES:
54 type = V_028B6C_TESS_TRIANGLE;
55 break;
56 case PIPE_PRIM_QUADS:
57 type = V_028B6C_TESS_QUAD;
58 break;
59 default:
60 assert(0);
61 return;
62 }
63
64 switch (tes_spacing) {
65 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
66 partitioning = V_028B6C_PART_FRAC_ODD;
67 break;
68 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
69 partitioning = V_028B6C_PART_FRAC_EVEN;
70 break;
71 case PIPE_TESS_SPACING_EQUAL:
72 partitioning = V_028B6C_PART_INTEGER;
73 break;
74 default:
75 assert(0);
76 return;
77 }
78
79 if (tes_point_mode)
80 topology = V_028B6C_OUTPUT_POINT;
81 else if (tes_prim_mode == PIPE_PRIM_LINES)
82 topology = V_028B6C_OUTPUT_LINE;
83 else if (tes_vertex_order_cw)
84 /* for some reason, this must be the other way around */
85 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
86 else
87 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
88
89 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
90 S_028B6C_TYPE(type) |
91 S_028B6C_PARTITIONING(partitioning) |
92 S_028B6C_TOPOLOGY(topology));
93 }
94
95 static void si_shader_ls(struct si_shader *shader)
96 {
97 struct si_pm4_state *pm4;
98 unsigned num_sgprs, num_user_sgprs;
99 unsigned vgpr_comp_cnt;
100 uint64_t va;
101
102 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
103 if (!pm4)
104 return;
105
106 va = shader->bo->gpu_address;
107 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
108
109 /* We need at least 2 components for LS.
110 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
111 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 1;
112
113 num_user_sgprs = SI_LS_NUM_USER_SGPR;
114 num_sgprs = shader->num_sgprs;
115 if (num_user_sgprs > num_sgprs) {
116 /* Last 2 reserved SGPRs are used for VCC */
117 num_sgprs = num_user_sgprs + 2;
118 }
119 assert(num_sgprs <= 104);
120
121 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
122 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
123
124 shader->rsrc1 = S_00B528_VGPRS((shader->num_vgprs - 1) / 4) |
125 S_00B528_SGPRS((num_sgprs - 1) / 8) |
126 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
127 S_00B528_DX10_CLAMP(shader->dx10_clamp_mode);
128 shader->rsrc2 = S_00B52C_USER_SGPR(num_user_sgprs) |
129 S_00B52C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0);
130 }
131
132 static void si_shader_hs(struct si_shader *shader)
133 {
134 struct si_pm4_state *pm4;
135 unsigned num_sgprs, num_user_sgprs;
136 uint64_t va;
137
138 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
139 if (!pm4)
140 return;
141
142 va = shader->bo->gpu_address;
143 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
144
145 num_user_sgprs = SI_TCS_NUM_USER_SGPR;
146 num_sgprs = shader->num_sgprs;
147 /* One SGPR after user SGPRs is pre-loaded with tessellation factor
148 * buffer offset. */
149 if ((num_user_sgprs + 1) > num_sgprs) {
150 /* Last 2 reserved SGPRs are used for VCC */
151 num_sgprs = num_user_sgprs + 1 + 2;
152 }
153 assert(num_sgprs <= 104);
154
155 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
156 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
157 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
158 S_00B428_VGPRS((shader->num_vgprs - 1) / 4) |
159 S_00B428_SGPRS((num_sgprs - 1) / 8) |
160 S_00B428_DX10_CLAMP(shader->dx10_clamp_mode));
161 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
162 S_00B42C_USER_SGPR(num_user_sgprs) |
163 S_00B42C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
164 }
165
166 static void si_shader_es(struct si_shader *shader)
167 {
168 struct si_pm4_state *pm4;
169 unsigned num_sgprs, num_user_sgprs;
170 unsigned vgpr_comp_cnt;
171 uint64_t va;
172
173 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
174
175 if (!pm4)
176 return;
177
178 va = shader->bo->gpu_address;
179 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
180
181 if (shader->selector->type == PIPE_SHADER_VERTEX) {
182 vgpr_comp_cnt = shader->uses_instanceid ? 3 : 0;
183 num_user_sgprs = SI_ES_NUM_USER_SGPR;
184 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
185 vgpr_comp_cnt = 3; /* all components are needed for TES */
186 num_user_sgprs = SI_TES_NUM_USER_SGPR;
187 } else
188 unreachable("invalid shader selector type");
189
190 num_sgprs = shader->num_sgprs;
191 /* One SGPR after user SGPRs is pre-loaded with es2gs_offset */
192 if ((num_user_sgprs + 1) > num_sgprs) {
193 /* Last 2 reserved SGPRs are used for VCC */
194 num_sgprs = num_user_sgprs + 1 + 2;
195 }
196 assert(num_sgprs <= 104);
197
198 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
199 shader->selector->esgs_itemsize / 4);
200 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
201 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
202 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
203 S_00B328_VGPRS((shader->num_vgprs - 1) / 4) |
204 S_00B328_SGPRS((num_sgprs - 1) / 8) |
205 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
206 S_00B328_DX10_CLAMP(shader->dx10_clamp_mode));
207 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
208 S_00B32C_USER_SGPR(num_user_sgprs) |
209 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
210
211 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
212 si_set_tesseval_regs(shader, pm4);
213 }
214
215 static void si_shader_gs(struct si_shader *shader)
216 {
217 unsigned gs_vert_itemsize = shader->selector->gsvs_vertex_size;
218 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
219 unsigned gsvs_itemsize = shader->selector->max_gsvs_emit_size >> 2;
220 unsigned gs_num_invocations = shader->selector->gs_num_invocations;
221 unsigned cut_mode;
222 struct si_pm4_state *pm4;
223 unsigned num_sgprs, num_user_sgprs;
224 uint64_t va;
225 unsigned max_stream = shader->selector->max_gs_stream;
226
227 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
228 assert(gsvs_itemsize < (1 << 15));
229
230 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
231
232 if (!pm4)
233 return;
234
235 if (gs_max_vert_out <= 128) {
236 cut_mode = V_028A40_GS_CUT_128;
237 } else if (gs_max_vert_out <= 256) {
238 cut_mode = V_028A40_GS_CUT_256;
239 } else if (gs_max_vert_out <= 512) {
240 cut_mode = V_028A40_GS_CUT_512;
241 } else {
242 assert(gs_max_vert_out <= 1024);
243 cut_mode = V_028A40_GS_CUT_1024;
244 }
245
246 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
247 S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
248 S_028A40_CUT_MODE(cut_mode)|
249 S_028A40_ES_WRITE_OPTIMIZE(1) |
250 S_028A40_GS_WRITE_OPTIMIZE(1));
251
252 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
253 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize * ((max_stream >= 2) ? 2 : 1));
254 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize * ((max_stream >= 3) ? 3 : 1));
255
256 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize * (max_stream + 1));
257
258 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, gs_max_vert_out);
259
260 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize >> 2);
261 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? gs_vert_itemsize >> 2 : 0);
262 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? gs_vert_itemsize >> 2 : 0);
263 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? gs_vert_itemsize >> 2 : 0);
264
265 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
266 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
267 S_028B90_ENABLE(gs_num_invocations > 0));
268
269 va = shader->bo->gpu_address;
270 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
271 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
272 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
273
274 num_user_sgprs = SI_GS_NUM_USER_SGPR;
275 num_sgprs = shader->num_sgprs;
276 /* Two SGPRs after user SGPRs are pre-loaded with gs2vs_offset, gs_wave_id */
277 if ((num_user_sgprs + 2) > num_sgprs) {
278 /* Last 2 reserved SGPRs are used for VCC */
279 num_sgprs = num_user_sgprs + 2 + 2;
280 }
281 assert(num_sgprs <= 104);
282
283 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
284 S_00B228_VGPRS((shader->num_vgprs - 1) / 4) |
285 S_00B228_SGPRS((num_sgprs - 1) / 8) |
286 S_00B228_DX10_CLAMP(shader->dx10_clamp_mode));
287 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
288 S_00B22C_USER_SGPR(num_user_sgprs) |
289 S_00B22C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
290 }
291
292 static void si_shader_vs(struct si_shader *shader)
293 {
294 struct si_pm4_state *pm4;
295 unsigned num_sgprs, num_user_sgprs;
296 unsigned nparams, vgpr_comp_cnt;
297 uint64_t va;
298 unsigned window_space =
299 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
300 bool enable_prim_id = si_vs_exports_prim_id(shader);
301
302 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
303
304 if (!pm4)
305 return;
306
307 /* If this is the GS copy shader, the GS state writes this register.
308 * Otherwise, the VS state writes it.
309 */
310 if (!shader->is_gs_copy_shader) {
311 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
312 S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
313 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
314 } else
315 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
316
317 va = shader->bo->gpu_address;
318 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
319
320 if (shader->is_gs_copy_shader) {
321 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
322 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
323 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
324 vgpr_comp_cnt = shader->uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
325 num_user_sgprs = SI_VS_NUM_USER_SGPR;
326 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
327 vgpr_comp_cnt = 3; /* all components are needed for TES */
328 num_user_sgprs = SI_TES_NUM_USER_SGPR;
329 } else
330 unreachable("invalid shader selector type");
331
332 num_sgprs = shader->num_sgprs;
333 if (num_user_sgprs > num_sgprs) {
334 /* Last 2 reserved SGPRs are used for VCC */
335 num_sgprs = num_user_sgprs + 2;
336 }
337 assert(num_sgprs <= 104);
338
339 /* VS is required to export at least one param. */
340 nparams = MAX2(shader->nr_param_exports, 1);
341 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
342 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
343
344 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
345 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
346 S_02870C_POS1_EXPORT_FORMAT(shader->nr_pos_exports > 1 ?
347 V_02870C_SPI_SHADER_4COMP :
348 V_02870C_SPI_SHADER_NONE) |
349 S_02870C_POS2_EXPORT_FORMAT(shader->nr_pos_exports > 2 ?
350 V_02870C_SPI_SHADER_4COMP :
351 V_02870C_SPI_SHADER_NONE) |
352 S_02870C_POS3_EXPORT_FORMAT(shader->nr_pos_exports > 3 ?
353 V_02870C_SPI_SHADER_4COMP :
354 V_02870C_SPI_SHADER_NONE));
355
356 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
357 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
358 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
359 S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
360 S_00B128_SGPRS((num_sgprs - 1) / 8) |
361 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
362 S_00B128_DX10_CLAMP(shader->dx10_clamp_mode));
363 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
364 S_00B12C_USER_SGPR(num_user_sgprs) |
365 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
366 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
367 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
368 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
369 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
370 S_00B12C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
371 if (window_space)
372 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
373 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
374 else
375 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
376 S_028818_VTX_W0_FMT(1) |
377 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
378 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
379 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
380
381 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
382 si_set_tesseval_regs(shader, pm4);
383 }
384
385 static void si_shader_ps(struct si_shader *shader)
386 {
387 struct tgsi_shader_info *info = &shader->selector->info;
388 struct si_pm4_state *pm4;
389 unsigned i, spi_ps_in_control;
390 unsigned num_sgprs, num_user_sgprs;
391 unsigned spi_baryc_cntl = 0;
392 uint64_t va;
393 bool has_centroid;
394
395 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
396
397 if (!pm4)
398 return;
399
400 for (i = 0; i < info->num_inputs; i++) {
401 switch (info->input_semantic_name[i]) {
402 case TGSI_SEMANTIC_POSITION:
403 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
404 * Possible vaules:
405 * 0 -> Position = pixel center (default)
406 * 1 -> Position = pixel centroid
407 * 2 -> Position = at sample position
408 */
409 switch (info->input_interpolate_loc[i]) {
410 case TGSI_INTERPOLATE_LOC_CENTROID:
411 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(1);
412 break;
413 case TGSI_INTERPOLATE_LOC_SAMPLE:
414 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
415 break;
416 }
417
418 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
419 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
420 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
421 break;
422 }
423 }
424
425 has_centroid = G_0286CC_PERSP_CENTROID_ENA(shader->spi_ps_input_ena) ||
426 G_0286CC_LINEAR_CENTROID_ENA(shader->spi_ps_input_ena);
427
428 spi_ps_in_control = S_0286D8_NUM_INTERP(shader->nparam) |
429 S_0286D8_BC_OPTIMIZE_DISABLE(has_centroid);
430
431 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
432 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
433
434 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
435 info->writes_samplemask ? V_028710_SPI_SHADER_32_ABGR :
436 info->writes_stencil ? V_028710_SPI_SHADER_32_GR :
437 info->writes_z ? V_028710_SPI_SHADER_32_R :
438 V_028710_SPI_SHADER_ZERO);
439
440 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
441 shader->spi_shader_col_format);
442 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
443
444 va = shader->bo->gpu_address;
445 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
446 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
447 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
448
449 num_user_sgprs = SI_PS_NUM_USER_SGPR;
450 num_sgprs = shader->num_sgprs;
451 /* One SGPR after user SGPRs is pre-loaded with {prim_mask, lds_offset} */
452 if ((num_user_sgprs + 1) > num_sgprs) {
453 /* Last 2 reserved SGPRs are used for VCC */
454 num_sgprs = num_user_sgprs + 1 + 2;
455 }
456 assert(num_sgprs <= 104);
457
458 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
459 S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
460 S_00B028_SGPRS((num_sgprs - 1) / 8) |
461 S_00B028_DX10_CLAMP(shader->dx10_clamp_mode));
462 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
463 S_00B02C_EXTRA_LDS_SIZE(shader->lds_size) |
464 S_00B02C_USER_SGPR(num_user_sgprs) |
465 S_00B32C_SCRATCH_EN(shader->scratch_bytes_per_wave > 0));
466 }
467
468 static void si_shader_init_pm4_state(struct si_shader *shader)
469 {
470
471 if (shader->pm4)
472 si_pm4_free_state_simple(shader->pm4);
473
474 switch (shader->selector->type) {
475 case PIPE_SHADER_VERTEX:
476 if (shader->key.vs.as_ls)
477 si_shader_ls(shader);
478 else if (shader->key.vs.as_es)
479 si_shader_es(shader);
480 else
481 si_shader_vs(shader);
482 break;
483 case PIPE_SHADER_TESS_CTRL:
484 si_shader_hs(shader);
485 break;
486 case PIPE_SHADER_TESS_EVAL:
487 if (shader->key.tes.as_es)
488 si_shader_es(shader);
489 else
490 si_shader_vs(shader);
491 break;
492 case PIPE_SHADER_GEOMETRY:
493 si_shader_gs(shader);
494 si_shader_vs(shader->gs_copy_shader);
495 break;
496 case PIPE_SHADER_FRAGMENT:
497 si_shader_ps(shader);
498 break;
499 default:
500 assert(0);
501 }
502 }
503
504 static unsigned si_get_alpha_test_func(struct si_context *sctx)
505 {
506 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
507 if (sctx->queued.named.dsa &&
508 !sctx->framebuffer.cb0_is_integer)
509 return sctx->queued.named.dsa->alpha_func;
510
511 return PIPE_FUNC_ALWAYS;
512 }
513
514 /* Compute the key for the hw shader variant */
515 static inline void si_shader_selector_key(struct pipe_context *ctx,
516 struct si_shader_selector *sel,
517 union si_shader_key *key)
518 {
519 struct si_context *sctx = (struct si_context *)ctx;
520 unsigned i;
521
522 memset(key, 0, sizeof(*key));
523
524 switch (sel->type) {
525 case PIPE_SHADER_VERTEX:
526 if (sctx->vertex_elements)
527 for (i = 0; i < sctx->vertex_elements->count; ++i)
528 key->vs.instance_divisors[i] =
529 sctx->vertex_elements->elements[i].instance_divisor;
530
531 if (sctx->tes_shader.cso)
532 key->vs.as_ls = 1;
533 else if (sctx->gs_shader.cso)
534 key->vs.as_es = 1;
535
536 if (!sctx->gs_shader.cso && sctx->ps_shader.cso &&
537 sctx->ps_shader.cso->info.uses_primid)
538 key->vs.export_prim_id = 1;
539 break;
540 case PIPE_SHADER_TESS_CTRL:
541 key->tcs.prim_mode =
542 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
543 break;
544 case PIPE_SHADER_TESS_EVAL:
545 if (sctx->gs_shader.cso)
546 key->tes.as_es = 1;
547 else if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
548 key->tes.export_prim_id = 1;
549 break;
550 case PIPE_SHADER_GEOMETRY:
551 break;
552 case PIPE_SHADER_FRAGMENT: {
553 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
554
555 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
556 sel->info.colors_written == 0x1)
557 key->ps.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
558
559 key->ps.export_16bpc = sctx->framebuffer.export_16bpc;
560
561 if (rs) {
562 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
563 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
564 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
565 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
566
567 key->ps.color_two_side = rs->two_side;
568
569 if (sctx->queued.named.blend) {
570 key->ps.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
571 rs->multisample_enable &&
572 !sctx->framebuffer.cb0_is_integer;
573 }
574
575 key->ps.poly_stipple = rs->poly_stipple_enable && is_poly;
576 key->ps.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
577 (is_line && rs->line_smooth)) &&
578 sctx->framebuffer.nr_samples <= 1;
579 key->ps.clamp_color = rs->clamp_fragment_color;
580 }
581
582 key->ps.alpha_func = si_get_alpha_test_func(sctx);
583 break;
584 }
585 default:
586 assert(0);
587 }
588 }
589
590 /* Select the hw shader variant depending on the current state. */
591 static int si_shader_select(struct pipe_context *ctx,
592 struct si_shader_ctx_state *state)
593 {
594 struct si_context *sctx = (struct si_context *)ctx;
595 struct si_shader_selector *sel = state->cso;
596 struct si_shader *current = state->current;
597 union si_shader_key key;
598 struct si_shader *iter, *shader = NULL;
599 int r;
600
601 si_shader_selector_key(ctx, sel, &key);
602
603 /* Check if we don't need to change anything.
604 * This path is also used for most shaders that don't need multiple
605 * variants, it will cost just a computation of the key and this
606 * test. */
607 if (likely(current && memcmp(&current->key, &key, sizeof(key)) == 0))
608 return 0;
609
610 pipe_mutex_lock(sel->mutex);
611
612 /* Find the shader variant. */
613 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
614 /* Don't check the "current" shader. We checked it above. */
615 if (current != iter &&
616 memcmp(&iter->key, &key, sizeof(key)) == 0) {
617 state->current = iter;
618 pipe_mutex_unlock(sel->mutex);
619 return 0;
620 }
621 }
622
623 /* Build a new shader. */
624 shader = CALLOC_STRUCT(si_shader);
625 if (!shader) {
626 pipe_mutex_unlock(sel->mutex);
627 return -ENOMEM;
628 }
629 shader->selector = sel;
630 shader->key = key;
631
632 r = si_shader_create(sctx->screen, sctx->tm, shader, &sctx->b.debug);
633 if (unlikely(r)) {
634 R600_ERR("Failed to build shader variant (type=%u) %d\n",
635 sel->type, r);
636 FREE(shader);
637 pipe_mutex_unlock(sel->mutex);
638 return r;
639 }
640 si_shader_init_pm4_state(shader);
641
642 if (!sel->last_variant) {
643 sel->first_variant = shader;
644 sel->last_variant = shader;
645 } else {
646 sel->last_variant->next_variant = shader;
647 sel->last_variant = shader;
648 }
649 state->current = shader;
650 pipe_mutex_unlock(sel->mutex);
651 return 0;
652 }
653
654 static void *si_create_shader_selector(struct pipe_context *ctx,
655 const struct pipe_shader_state *state)
656 {
657 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
658 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
659 int i;
660
661 if (!sel)
662 return NULL;
663
664 sel->tokens = tgsi_dup_tokens(state->tokens);
665 if (!sel->tokens) {
666 FREE(sel);
667 return NULL;
668 }
669
670 sel->so = state->stream_output;
671 tgsi_scan_shader(state->tokens, &sel->info);
672 sel->type = util_pipe_shader_from_tgsi_processor(sel->info.processor);
673 p_atomic_inc(&sscreen->b.num_shaders_created);
674
675 /* First set which opcode uses which (i,j) pair. */
676 if (sel->info.uses_persp_opcode_interp_centroid)
677 sel->info.uses_persp_centroid = true;
678
679 if (sel->info.uses_linear_opcode_interp_centroid)
680 sel->info.uses_linear_centroid = true;
681
682 if (sel->info.uses_persp_opcode_interp_offset ||
683 sel->info.uses_persp_opcode_interp_sample)
684 sel->info.uses_persp_center = true;
685
686 if (sel->info.uses_linear_opcode_interp_offset ||
687 sel->info.uses_linear_opcode_interp_sample)
688 sel->info.uses_linear_center = true;
689
690 /* Determine if the shader has to use a conditional assignment when
691 * emulating force_persample_interp.
692 */
693 sel->forces_persample_interp_for_persp =
694 sel->info.uses_persp_center +
695 sel->info.uses_persp_centroid +
696 sel->info.uses_persp_sample >= 2;
697
698 sel->forces_persample_interp_for_linear =
699 sel->info.uses_linear_center +
700 sel->info.uses_linear_centroid +
701 sel->info.uses_linear_sample >= 2;
702
703 switch (sel->type) {
704 case PIPE_SHADER_GEOMETRY:
705 sel->gs_output_prim =
706 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
707 sel->gs_max_out_vertices =
708 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
709 sel->gs_num_invocations =
710 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
711 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
712 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
713 sel->gs_max_out_vertices;
714
715 sel->max_gs_stream = 0;
716 for (i = 0; i < sel->so.num_outputs; i++)
717 sel->max_gs_stream = MAX2(sel->max_gs_stream,
718 sel->so.output[i].stream);
719
720 sel->gs_input_verts_per_prim =
721 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
722 break;
723
724 case PIPE_SHADER_VERTEX:
725 case PIPE_SHADER_TESS_CTRL:
726 case PIPE_SHADER_TESS_EVAL:
727 for (i = 0; i < sel->info.num_outputs; i++) {
728 unsigned name = sel->info.output_semantic_name[i];
729 unsigned index = sel->info.output_semantic_index[i];
730
731 switch (name) {
732 case TGSI_SEMANTIC_TESSINNER:
733 case TGSI_SEMANTIC_TESSOUTER:
734 case TGSI_SEMANTIC_PATCH:
735 sel->patch_outputs_written |=
736 1llu << si_shader_io_get_unique_index(name, index);
737 break;
738 default:
739 sel->outputs_written |=
740 1llu << si_shader_io_get_unique_index(name, index);
741 }
742 }
743 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
744 break;
745 }
746
747 /* DB_SHADER_CONTROL */
748 sel->db_shader_control =
749 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
750 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
751 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
752 S_02880C_KILL_ENABLE(sel->info.uses_kill);
753
754 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
755 case TGSI_FS_DEPTH_LAYOUT_GREATER:
756 sel->db_shader_control |=
757 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
758 break;
759 case TGSI_FS_DEPTH_LAYOUT_LESS:
760 sel->db_shader_control |=
761 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
762 break;
763 }
764
765 /* Pre-compilation. */
766 if (sscreen->b.debug_flags & DBG_PRECOMPILE) {
767 struct si_shader_ctx_state state = {sel};
768
769 if (si_shader_select(ctx, &state)) {
770 fprintf(stderr, "radeonsi: can't create a shader\n");
771 tgsi_free_tokens(sel->tokens);
772 FREE(sel);
773 return NULL;
774 }
775 }
776
777 pipe_mutex_init(sel->mutex);
778 return sel;
779 }
780
781 /**
782 * Normally, we only emit 1 viewport and 1 scissor if no shader is using
783 * the VIEWPORT_INDEX output, and emitting the other viewports and scissors
784 * is delayed. When a shader with VIEWPORT_INDEX appears, this should be
785 * called to emit the rest.
786 */
787 static void si_update_viewports_and_scissors(struct si_context *sctx)
788 {
789 struct tgsi_shader_info *info = si_get_vs_info(sctx);
790
791 if (!info || !info->writes_viewport_index)
792 return;
793
794 if (sctx->scissors.dirty_mask)
795 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
796 if (sctx->viewports.dirty_mask)
797 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
798 }
799
800 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
801 {
802 struct si_context *sctx = (struct si_context *)ctx;
803 struct si_shader_selector *sel = state;
804
805 if (sctx->vs_shader.cso == sel)
806 return;
807
808 sctx->vs_shader.cso = sel;
809 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
810 si_mark_atom_dirty(sctx, &sctx->clip_regs);
811 si_update_viewports_and_scissors(sctx);
812 }
813
814 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
815 {
816 struct si_context *sctx = (struct si_context *)ctx;
817 struct si_shader_selector *sel = state;
818 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
819
820 if (sctx->gs_shader.cso == sel)
821 return;
822
823 sctx->gs_shader.cso = sel;
824 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
825 si_mark_atom_dirty(sctx, &sctx->clip_regs);
826 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
827
828 if (enable_changed)
829 si_shader_change_notify(sctx);
830 si_update_viewports_and_scissors(sctx);
831 }
832
833 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
834 {
835 struct si_context *sctx = (struct si_context *)ctx;
836 struct si_shader_selector *sel = state;
837 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
838
839 if (sctx->tcs_shader.cso == sel)
840 return;
841
842 sctx->tcs_shader.cso = sel;
843 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
844
845 if (enable_changed)
846 sctx->last_tcs = NULL; /* invalidate derived tess state */
847 }
848
849 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
850 {
851 struct si_context *sctx = (struct si_context *)ctx;
852 struct si_shader_selector *sel = state;
853 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
854
855 if (sctx->tes_shader.cso == sel)
856 return;
857
858 sctx->tes_shader.cso = sel;
859 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
860 si_mark_atom_dirty(sctx, &sctx->clip_regs);
861 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
862
863 if (enable_changed) {
864 si_shader_change_notify(sctx);
865 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
866 }
867 si_update_viewports_and_scissors(sctx);
868 }
869
870 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
871 {
872 struct si_context *sctx = (struct si_context *)ctx;
873 struct si_shader_selector *sel = state;
874
875 /* skip if supplied shader is one already in use */
876 if (sctx->ps_shader.cso == sel)
877 return;
878
879 sctx->ps_shader.cso = sel;
880 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
881 si_mark_atom_dirty(sctx, &sctx->cb_target_mask);
882 }
883
884 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
885 {
886 struct si_context *sctx = (struct si_context *)ctx;
887 struct si_shader_selector *sel = (struct si_shader_selector *)state;
888 struct si_shader *p = sel->first_variant, *c;
889 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
890 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
891 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
892 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
893 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
894 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
895 };
896
897 if (current_shader[sel->type]->cso == sel) {
898 current_shader[sel->type]->cso = NULL;
899 current_shader[sel->type]->current = NULL;
900 }
901
902 while (p) {
903 c = p->next_variant;
904 switch (sel->type) {
905 case PIPE_SHADER_VERTEX:
906 if (p->key.vs.as_ls)
907 si_pm4_delete_state(sctx, ls, p->pm4);
908 else if (p->key.vs.as_es)
909 si_pm4_delete_state(sctx, es, p->pm4);
910 else
911 si_pm4_delete_state(sctx, vs, p->pm4);
912 break;
913 case PIPE_SHADER_TESS_CTRL:
914 si_pm4_delete_state(sctx, hs, p->pm4);
915 break;
916 case PIPE_SHADER_TESS_EVAL:
917 if (p->key.tes.as_es)
918 si_pm4_delete_state(sctx, es, p->pm4);
919 else
920 si_pm4_delete_state(sctx, vs, p->pm4);
921 break;
922 case PIPE_SHADER_GEOMETRY:
923 si_pm4_delete_state(sctx, gs, p->pm4);
924 si_pm4_delete_state(sctx, vs, p->gs_copy_shader->pm4);
925 break;
926 case PIPE_SHADER_FRAGMENT:
927 si_pm4_delete_state(sctx, ps, p->pm4);
928 break;
929 }
930
931 si_shader_destroy(p);
932 free(p);
933 p = c;
934 }
935
936 pipe_mutex_destroy(sel->mutex);
937 free(sel->tokens);
938 free(sel);
939 }
940
941 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
942 {
943 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
944 struct si_shader *ps = sctx->ps_shader.current;
945 struct si_shader *vs = si_get_vs_state(sctx);
946 struct tgsi_shader_info *psinfo;
947 struct tgsi_shader_info *vsinfo = &vs->selector->info;
948 unsigned i, j, tmp, num_written = 0;
949
950 if (!ps || !ps->nparam)
951 return;
952
953 psinfo = &ps->selector->info;
954
955 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, ps->nparam);
956
957 for (i = 0; i < psinfo->num_inputs; i++) {
958 unsigned name = psinfo->input_semantic_name[i];
959 unsigned index = psinfo->input_semantic_index[i];
960 unsigned interpolate = psinfo->input_interpolate[i];
961 unsigned param_offset = ps->ps_input_param_offset[i];
962
963 if (name == TGSI_SEMANTIC_POSITION ||
964 name == TGSI_SEMANTIC_FACE)
965 /* Read from preloaded VGPRs, not parameters */
966 continue;
967
968 bcolor:
969 tmp = 0;
970
971 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
972 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
973 tmp |= S_028644_FLAT_SHADE(1);
974
975 if (name == TGSI_SEMANTIC_PCOORD ||
976 (name == TGSI_SEMANTIC_TEXCOORD &&
977 sctx->sprite_coord_enable & (1 << index))) {
978 tmp |= S_028644_PT_SPRITE_TEX(1);
979 }
980
981 for (j = 0; j < vsinfo->num_outputs; j++) {
982 if (name == vsinfo->output_semantic_name[j] &&
983 index == vsinfo->output_semantic_index[j]) {
984 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[j]);
985 break;
986 }
987 }
988
989 if (name == TGSI_SEMANTIC_PRIMID)
990 /* PrimID is written after the last output. */
991 tmp |= S_028644_OFFSET(vs->vs_output_param_offset[vsinfo->num_outputs]);
992 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(tmp)) {
993 /* No corresponding output found, load defaults into input.
994 * Don't set any other bits.
995 * (FLAT_SHADE=1 completely changes behavior) */
996 tmp = S_028644_OFFSET(0x20);
997 }
998
999 assert(param_offset == num_written);
1000 radeon_emit(cs, tmp);
1001 num_written++;
1002
1003 if (name == TGSI_SEMANTIC_COLOR &&
1004 ps->key.ps.color_two_side) {
1005 name = TGSI_SEMANTIC_BCOLOR;
1006 param_offset++;
1007 goto bcolor;
1008 }
1009 }
1010 assert(ps->nparam == num_written);
1011 }
1012
1013 static void si_emit_spi_ps_input(struct si_context *sctx, struct r600_atom *atom)
1014 {
1015 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1016 struct si_shader *ps = sctx->ps_shader.current;
1017 unsigned input_ena;
1018
1019 if (!ps)
1020 return;
1021
1022 input_ena = ps->spi_ps_input_ena;
1023
1024 /* we need to enable at least one of them, otherwise we hang the GPU */
1025 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1026 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1027 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1028 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1029 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1030 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1031 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1032 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1033
1034 if (sctx->force_persample_interp) {
1035 unsigned num_persp = G_0286CC_PERSP_SAMPLE_ENA(input_ena) +
1036 G_0286CC_PERSP_CENTER_ENA(input_ena) +
1037 G_0286CC_PERSP_CENTROID_ENA(input_ena);
1038 unsigned num_linear = G_0286CC_LINEAR_SAMPLE_ENA(input_ena) +
1039 G_0286CC_LINEAR_CENTER_ENA(input_ena) +
1040 G_0286CC_LINEAR_CENTROID_ENA(input_ena);
1041
1042 /* If only one set of (i,j) coordinates is used, we can disable
1043 * CENTER/CENTROID, enable SAMPLE and it will load SAMPLE coordinates
1044 * where CENTER/CENTROID are expected, effectively forcing per-sample
1045 * interpolation.
1046 */
1047 if (num_persp == 1) {
1048 input_ena &= C_0286CC_PERSP_CENTER_ENA;
1049 input_ena &= C_0286CC_PERSP_CENTROID_ENA;
1050 input_ena |= G_0286CC_PERSP_SAMPLE_ENA(1);
1051 }
1052 if (num_linear == 1) {
1053 input_ena &= C_0286CC_LINEAR_CENTER_ENA;
1054 input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
1055 input_ena |= G_0286CC_LINEAR_SAMPLE_ENA(1);
1056 }
1057
1058 /* If at least 2 sets of coordinates are used, we can't use this
1059 * trick and have to select SAMPLE using a conditional assignment
1060 * in the shader with "force_persample_interp" being a shader constant.
1061 */
1062 }
1063
1064 radeon_set_context_reg_seq(cs, R_0286CC_SPI_PS_INPUT_ENA, 2);
1065 radeon_emit(cs, input_ena);
1066 radeon_emit(cs, input_ena);
1067
1068 if (ps->selector->forces_persample_interp_for_persp ||
1069 ps->selector->forces_persample_interp_for_linear)
1070 radeon_set_sh_reg(cs, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1071 SI_SGPR_PS_STATE_BITS * 4,
1072 sctx->force_persample_interp);
1073 }
1074
1075 /**
1076 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
1077 */
1078 static void si_init_config_add_vgt_flush(struct si_context *sctx)
1079 {
1080 if (sctx->init_config_has_vgt_flush)
1081 return;
1082
1083 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
1084 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
1085 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1086 si_pm4_cmd_end(sctx->init_config, false);
1087 sctx->init_config_has_vgt_flush = true;
1088 }
1089
1090 /* Initialize state related to ESGS / GSVS ring buffers */
1091 static bool si_update_gs_ring_buffers(struct si_context *sctx)
1092 {
1093 struct si_shader_selector *es =
1094 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
1095 struct si_shader_selector *gs = sctx->gs_shader.cso;
1096 struct si_pm4_state *pm4;
1097
1098 /* Chip constants. */
1099 unsigned num_se = sctx->screen->b.info.max_se;
1100 unsigned wave_size = 64;
1101 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1102 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1103 unsigned alignment = 256 * num_se;
1104 /* The maximum size is 63.999 MB per SE. */
1105 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1106
1107 /* Calculate the minimum size. */
1108 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
1109 wave_size, alignment);
1110
1111 /* These are recommended sizes, not minimum sizes. */
1112 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1113 es->esgs_itemsize * gs->gs_input_verts_per_prim;
1114 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1115 gs->max_gsvs_emit_size * (gs->max_gs_stream + 1);
1116
1117 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1118 esgs_ring_size = align(esgs_ring_size, alignment);
1119 gsvs_ring_size = align(gsvs_ring_size, alignment);
1120
1121 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1122 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1123
1124 /* Some rings don't have to be allocated if shaders don't use them.
1125 * (e.g. no varyings between ES and GS or GS and VS)
1126 */
1127 bool update_esgs = esgs_ring_size &&
1128 (!sctx->esgs_ring ||
1129 sctx->esgs_ring->width0 < esgs_ring_size);
1130 bool update_gsvs = gsvs_ring_size &&
1131 (!sctx->gsvs_ring ||
1132 sctx->gsvs_ring->width0 < gsvs_ring_size);
1133
1134 if (!update_esgs && !update_gsvs)
1135 return true;
1136
1137 if (update_esgs) {
1138 pipe_resource_reference(&sctx->esgs_ring, NULL);
1139 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1140 PIPE_USAGE_DEFAULT,
1141 esgs_ring_size);
1142 if (!sctx->esgs_ring)
1143 return false;
1144 }
1145
1146 if (update_gsvs) {
1147 pipe_resource_reference(&sctx->gsvs_ring, NULL);
1148 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1149 PIPE_USAGE_DEFAULT,
1150 gsvs_ring_size);
1151 if (!sctx->gsvs_ring)
1152 return false;
1153 }
1154
1155 /* Create the "init_config_gs_rings" state. */
1156 pm4 = CALLOC_STRUCT(si_pm4_state);
1157 if (!pm4)
1158 return false;
1159
1160 if (sctx->b.chip_class >= CIK) {
1161 if (sctx->esgs_ring)
1162 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
1163 sctx->esgs_ring->width0 / 256);
1164 if (sctx->gsvs_ring)
1165 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
1166 sctx->gsvs_ring->width0 / 256);
1167 } else {
1168 if (sctx->esgs_ring)
1169 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
1170 sctx->esgs_ring->width0 / 256);
1171 if (sctx->gsvs_ring)
1172 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
1173 sctx->gsvs_ring->width0 / 256);
1174 }
1175
1176 /* Set the state. */
1177 if (sctx->init_config_gs_rings)
1178 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
1179 sctx->init_config_gs_rings = pm4;
1180
1181 if (!sctx->init_config_has_vgt_flush) {
1182 si_init_config_add_vgt_flush(sctx);
1183 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1184 }
1185
1186 /* Flush the context to re-emit both init_config states. */
1187 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1188 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1189
1190 /* Set ring bindings. */
1191 if (sctx->esgs_ring) {
1192 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
1193 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1194 true, true, 4, 64, 0);
1195 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
1196 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1197 false, false, 0, 0, 0);
1198 }
1199 if (sctx->gsvs_ring)
1200 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
1201 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
1202 false, false, 0, 0, 0);
1203 return true;
1204 }
1205
1206 static void si_update_gsvs_ring_bindings(struct si_context *sctx)
1207 {
1208 unsigned gsvs_itemsize = sctx->gs_shader.cso->max_gsvs_emit_size;
1209 uint64_t offset;
1210
1211 if (!sctx->gsvs_ring || gsvs_itemsize == sctx->last_gsvs_itemsize)
1212 return;
1213
1214 sctx->last_gsvs_itemsize = gsvs_itemsize;
1215
1216 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
1217 sctx->gsvs_ring, gsvs_itemsize,
1218 64, true, true, 4, 16, 0);
1219
1220 offset = gsvs_itemsize * 64;
1221 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_1,
1222 sctx->gsvs_ring, gsvs_itemsize,
1223 64, true, true, 4, 16, offset);
1224
1225 offset = (gsvs_itemsize * 2) * 64;
1226 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_2,
1227 sctx->gsvs_ring, gsvs_itemsize,
1228 64, true, true, 4, 16, offset);
1229
1230 offset = (gsvs_itemsize * 3) * 64;
1231 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_GSVS_3,
1232 sctx->gsvs_ring, gsvs_itemsize,
1233 64, true, true, 4, 16, offset);
1234 }
1235
1236 /**
1237 * @returns 1 if \p sel has been updated to use a new scratch buffer
1238 * 0 if not
1239 * < 0 if there was a failure
1240 */
1241 static int si_update_scratch_buffer(struct si_context *sctx,
1242 struct si_shader *shader)
1243 {
1244 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
1245 int r;
1246
1247 if (!shader)
1248 return 0;
1249
1250 /* This shader doesn't need a scratch buffer */
1251 if (shader->scratch_bytes_per_wave == 0)
1252 return 0;
1253
1254 /* This shader is already configured to use the current
1255 * scratch buffer. */
1256 if (shader->scratch_bo == sctx->scratch_buffer)
1257 return 0;
1258
1259 assert(sctx->scratch_buffer);
1260
1261 si_shader_apply_scratch_relocs(sctx, shader, scratch_va);
1262
1263 /* Replace the shader bo with a new bo that has the relocs applied. */
1264 r = si_shader_binary_upload(sctx->screen, shader);
1265 if (r)
1266 return r;
1267
1268 /* Update the shader state to use the new shader bo. */
1269 si_shader_init_pm4_state(shader);
1270
1271 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
1272
1273 return 1;
1274 }
1275
1276 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
1277 {
1278 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
1279 }
1280
1281 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
1282 {
1283 return shader ? shader->scratch_bytes_per_wave : 0;
1284 }
1285
1286 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
1287 {
1288 unsigned bytes = 0;
1289
1290 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
1291 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
1292 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
1293 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tcs_shader.current));
1294 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
1295 return bytes;
1296 }
1297
1298 static bool si_update_spi_tmpring_size(struct si_context *sctx)
1299 {
1300 unsigned current_scratch_buffer_size =
1301 si_get_current_scratch_buffer_size(sctx);
1302 unsigned scratch_bytes_per_wave =
1303 si_get_max_scratch_bytes_per_wave(sctx);
1304 unsigned scratch_needed_size = scratch_bytes_per_wave *
1305 sctx->scratch_waves;
1306 int r;
1307
1308 if (scratch_needed_size > 0) {
1309 if (scratch_needed_size > current_scratch_buffer_size) {
1310 /* Create a bigger scratch buffer */
1311 pipe_resource_reference(
1312 (struct pipe_resource**)&sctx->scratch_buffer,
1313 NULL);
1314
1315 sctx->scratch_buffer =
1316 si_resource_create_custom(&sctx->screen->b.b,
1317 PIPE_USAGE_DEFAULT, scratch_needed_size);
1318 if (!sctx->scratch_buffer)
1319 return false;
1320 sctx->emit_scratch_reloc = true;
1321 }
1322
1323 /* Update the shaders, so they are using the latest scratch. The
1324 * scratch buffer may have been changed since these shaders were
1325 * last used, so we still need to try to update them, even if
1326 * they require scratch buffers smaller than the current size.
1327 */
1328 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
1329 if (r < 0)
1330 return false;
1331 if (r == 1)
1332 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
1333
1334 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
1335 if (r < 0)
1336 return false;
1337 if (r == 1)
1338 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1339
1340 r = si_update_scratch_buffer(sctx, sctx->tcs_shader.current);
1341 if (r < 0)
1342 return false;
1343 if (r == 1)
1344 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1345
1346 /* VS can be bound as LS, ES, or VS. */
1347 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
1348 if (r < 0)
1349 return false;
1350 if (r == 1) {
1351 if (sctx->tes_shader.current)
1352 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1353 else if (sctx->gs_shader.current)
1354 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1355 else
1356 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1357 }
1358
1359 /* TES can be bound as ES or VS. */
1360 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
1361 if (r < 0)
1362 return false;
1363 if (r == 1) {
1364 if (sctx->gs_shader.current)
1365 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1366 else
1367 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1368 }
1369 }
1370
1371 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
1372 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
1373 "scratch size should already be aligned correctly.");
1374
1375 sctx->spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
1376 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
1377 return true;
1378 }
1379
1380 static void si_init_tess_factor_ring(struct si_context *sctx)
1381 {
1382 assert(!sctx->tf_ring);
1383
1384 sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1385 PIPE_USAGE_DEFAULT,
1386 32768 * sctx->screen->b.info.max_se);
1387 if (!sctx->tf_ring)
1388 return;
1389
1390 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
1391
1392 si_init_config_add_vgt_flush(sctx);
1393
1394 /* Append these registers to the init config state. */
1395 if (sctx->b.chip_class >= CIK) {
1396 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
1397 S_030938_SIZE(sctx->tf_ring->width0 / 4));
1398 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
1399 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1400 } else {
1401 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
1402 S_008988_SIZE(sctx->tf_ring->width0 / 4));
1403 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
1404 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1405 }
1406
1407 /* Flush the context to re-emit the init_config state.
1408 * This is done only once in a lifetime of a context.
1409 */
1410 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1411 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1412 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1413
1414 si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_TESS_CTRL,
1415 SI_RING_TESS_FACTOR, sctx->tf_ring, 0,
1416 sctx->tf_ring->width0, false, false, 0, 0, 0);
1417 }
1418
1419 /**
1420 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
1421 * VS passes its outputs to TES directly, so the fixed-function shader only
1422 * has to write TESSOUTER and TESSINNER.
1423 */
1424 static void si_generate_fixed_func_tcs(struct si_context *sctx)
1425 {
1426 struct ureg_src const0, const1;
1427 struct ureg_dst tessouter, tessinner;
1428 struct ureg_program *ureg = ureg_create(TGSI_PROCESSOR_TESS_CTRL);
1429
1430 if (!ureg)
1431 return; /* if we get here, we're screwed */
1432
1433 assert(!sctx->fixed_func_tcs_shader.cso);
1434
1435 ureg_DECL_constant2D(ureg, 0, 1, SI_DRIVER_STATE_CONST_BUF);
1436 const0 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 0),
1437 SI_DRIVER_STATE_CONST_BUF);
1438 const1 = ureg_src_dimension(ureg_src_register(TGSI_FILE_CONSTANT, 1),
1439 SI_DRIVER_STATE_CONST_BUF);
1440
1441 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1442 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1443
1444 ureg_MOV(ureg, tessouter, const0);
1445 ureg_MOV(ureg, tessinner, const1);
1446 ureg_END(ureg);
1447
1448 sctx->fixed_func_tcs_shader.cso =
1449 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
1450 }
1451
1452 static void si_update_vgt_shader_config(struct si_context *sctx)
1453 {
1454 /* Calculate the index of the config.
1455 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
1456 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
1457 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
1458
1459 if (!*pm4) {
1460 uint32_t stages = 0;
1461
1462 *pm4 = CALLOC_STRUCT(si_pm4_state);
1463
1464 if (sctx->tes_shader.cso) {
1465 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
1466 S_028B54_HS_EN(1);
1467
1468 if (sctx->gs_shader.cso)
1469 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
1470 S_028B54_GS_EN(1) |
1471 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1472 else
1473 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
1474 } else if (sctx->gs_shader.cso) {
1475 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1476 S_028B54_GS_EN(1) |
1477 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1478 }
1479
1480 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
1481 }
1482 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
1483 }
1484
1485 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
1486 {
1487 struct pipe_stream_output_info *so = &shader->so;
1488 uint32_t enabled_stream_buffers_mask = 0;
1489 int i;
1490
1491 for (i = 0; i < so->num_outputs; i++)
1492 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
1493 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
1494 sctx->b.streamout.stride_in_dw = shader->so.stride;
1495 }
1496
1497 bool si_update_shaders(struct si_context *sctx)
1498 {
1499 struct pipe_context *ctx = (struct pipe_context*)sctx;
1500 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1501 int r;
1502
1503 /* Update stages before GS. */
1504 if (sctx->tes_shader.cso) {
1505 if (!sctx->tf_ring) {
1506 si_init_tess_factor_ring(sctx);
1507 if (!sctx->tf_ring)
1508 return false;
1509 }
1510
1511 /* VS as LS */
1512 r = si_shader_select(ctx, &sctx->vs_shader);
1513 if (r)
1514 return false;
1515 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1516
1517 if (sctx->tcs_shader.cso) {
1518 r = si_shader_select(ctx, &sctx->tcs_shader);
1519 if (r)
1520 return false;
1521 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1522 } else {
1523 if (!sctx->fixed_func_tcs_shader.cso) {
1524 si_generate_fixed_func_tcs(sctx);
1525 if (!sctx->fixed_func_tcs_shader.cso)
1526 return false;
1527 }
1528
1529 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader);
1530 if (r)
1531 return false;
1532 si_pm4_bind_state(sctx, hs,
1533 sctx->fixed_func_tcs_shader.current->pm4);
1534 }
1535
1536 r = si_shader_select(ctx, &sctx->tes_shader);
1537 if (r)
1538 return false;
1539
1540 if (sctx->gs_shader.cso) {
1541 /* TES as ES */
1542 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1543 } else {
1544 /* TES as VS */
1545 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1546 si_update_so(sctx, sctx->tes_shader.cso);
1547 }
1548 } else if (sctx->gs_shader.cso) {
1549 /* VS as ES */
1550 r = si_shader_select(ctx, &sctx->vs_shader);
1551 if (r)
1552 return false;
1553 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1554 } else {
1555 /* VS as VS */
1556 r = si_shader_select(ctx, &sctx->vs_shader);
1557 if (r)
1558 return false;
1559 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1560 si_update_so(sctx, sctx->vs_shader.cso);
1561 }
1562
1563 /* Update GS. */
1564 if (sctx->gs_shader.cso) {
1565 r = si_shader_select(ctx, &sctx->gs_shader);
1566 if (r)
1567 return false;
1568 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1569 si_pm4_bind_state(sctx, vs, sctx->gs_shader.current->gs_copy_shader->pm4);
1570 si_update_so(sctx, sctx->gs_shader.cso);
1571
1572 if (!si_update_gs_ring_buffers(sctx))
1573 return false;
1574
1575 si_update_gsvs_ring_bindings(sctx);
1576 } else {
1577 si_pm4_bind_state(sctx, gs, NULL);
1578 si_pm4_bind_state(sctx, es, NULL);
1579 }
1580
1581 si_update_vgt_shader_config(sctx);
1582
1583 if (sctx->ps_shader.cso) {
1584 unsigned db_shader_control =
1585 sctx->ps_shader.cso->db_shader_control |
1586 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
1587
1588 r = si_shader_select(ctx, &sctx->ps_shader);
1589 if (r)
1590 return false;
1591 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
1592
1593 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
1594 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
1595 sctx->flatshade != rs->flatshade) {
1596 sctx->sprite_coord_enable = rs->sprite_coord_enable;
1597 sctx->flatshade = rs->flatshade;
1598 si_mark_atom_dirty(sctx, &sctx->spi_map);
1599 }
1600
1601 if (si_pm4_state_changed(sctx, ps) ||
1602 sctx->force_persample_interp != rs->force_persample_interp) {
1603 sctx->force_persample_interp = rs->force_persample_interp;
1604 si_mark_atom_dirty(sctx, &sctx->spi_ps_input);
1605 }
1606
1607 if (sctx->ps_db_shader_control != db_shader_control) {
1608 sctx->ps_db_shader_control = db_shader_control;
1609 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1610 }
1611
1612 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.ps.poly_line_smoothing) {
1613 sctx->smoothing_enabled = sctx->ps_shader.current->key.ps.poly_line_smoothing;
1614 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1615
1616 if (sctx->b.chip_class == SI)
1617 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1618 }
1619 }
1620
1621 if (si_pm4_state_changed(sctx, ls) ||
1622 si_pm4_state_changed(sctx, hs) ||
1623 si_pm4_state_changed(sctx, es) ||
1624 si_pm4_state_changed(sctx, gs) ||
1625 si_pm4_state_changed(sctx, vs) ||
1626 si_pm4_state_changed(sctx, ps)) {
1627 if (!si_update_spi_tmpring_size(sctx))
1628 return false;
1629 }
1630 return true;
1631 }
1632
1633 void si_init_shader_functions(struct si_context *sctx)
1634 {
1635 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
1636 si_init_atom(sctx, &sctx->spi_ps_input, &sctx->atoms.s.spi_ps_input, si_emit_spi_ps_input);
1637
1638 sctx->b.b.create_vs_state = si_create_shader_selector;
1639 sctx->b.b.create_tcs_state = si_create_shader_selector;
1640 sctx->b.b.create_tes_state = si_create_shader_selector;
1641 sctx->b.b.create_gs_state = si_create_shader_selector;
1642 sctx->b.b.create_fs_state = si_create_shader_selector;
1643
1644 sctx->b.b.bind_vs_state = si_bind_vs_shader;
1645 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
1646 sctx->b.b.bind_tes_state = si_bind_tes_shader;
1647 sctx->b.b.bind_gs_state = si_bind_gs_shader;
1648 sctx->b.b.bind_fs_state = si_bind_ps_shader;
1649
1650 sctx->b.b.delete_vs_state = si_delete_shader_selector;
1651 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
1652 sctx->b.b.delete_tes_state = si_delete_shader_selector;
1653 sctx->b.b.delete_gs_state = si_delete_shader_selector;
1654 sctx->b.b.delete_fs_state = si_delete_shader_selector;
1655 }