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radeonsi: don't hang on shader compile failure
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "tgsi/tgsi_parse.h"
33 #include "tgsi/tgsi_ureg.h"
34 #include "util/hash_table.h"
35 #include "util/crc32.h"
36 #include "util/u_memory.h"
37 #include "util/u_prim.h"
38
39 #include "util/disk_cache.h"
40 #include "util/mesa-sha1.h"
41
42 /* SHADER_CACHE */
43
44 /**
45 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
46 * integer.
47 */
48 static void *si_get_tgsi_binary(struct si_shader_selector *sel)
49 {
50 unsigned tgsi_size = tgsi_num_tokens(sel->tokens) *
51 sizeof(struct tgsi_token);
52 unsigned size = 4 + tgsi_size + sizeof(sel->so);
53 char *result = (char*)MALLOC(size);
54
55 if (!result)
56 return NULL;
57
58 *((uint32_t*)result) = size;
59 memcpy(result + 4, sel->tokens, tgsi_size);
60 memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so));
61 return result;
62 }
63
64 /** Copy "data" to "ptr" and return the next dword following copied data. */
65 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
66 {
67 /* data may be NULL if size == 0 */
68 if (size)
69 memcpy(ptr, data, size);
70 ptr += DIV_ROUND_UP(size, 4);
71 return ptr;
72 }
73
74 /** Read data from "ptr". Return the next dword following the data. */
75 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
76 {
77 memcpy(data, ptr, size);
78 ptr += DIV_ROUND_UP(size, 4);
79 return ptr;
80 }
81
82 /**
83 * Write the size as uint followed by the data. Return the next dword
84 * following the copied data.
85 */
86 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
87 {
88 *ptr++ = size;
89 return write_data(ptr, data, size);
90 }
91
92 /**
93 * Read the size as uint followed by the data. Return both via parameters.
94 * Return the next dword following the data.
95 */
96 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
97 {
98 *size = *ptr++;
99 assert(*data == NULL);
100 if (!*size)
101 return ptr;
102 *data = malloc(*size);
103 return read_data(ptr, *data, *size);
104 }
105
106 /**
107 * Return the shader binary in a buffer. The first 4 bytes contain its size
108 * as integer.
109 */
110 static void *si_get_shader_binary(struct si_shader *shader)
111 {
112 /* There is always a size of data followed by the data itself. */
113 unsigned relocs_size = shader->binary.reloc_count *
114 sizeof(shader->binary.relocs[0]);
115 unsigned disasm_size = strlen(shader->binary.disasm_string) + 1;
116 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
117 strlen(shader->binary.llvm_ir_string) + 1 : 0;
118 unsigned size =
119 4 + /* total size */
120 4 + /* CRC32 of the data below */
121 align(sizeof(shader->config), 4) +
122 align(sizeof(shader->info), 4) +
123 4 + align(shader->binary.code_size, 4) +
124 4 + align(shader->binary.rodata_size, 4) +
125 4 + align(relocs_size, 4) +
126 4 + align(disasm_size, 4) +
127 4 + align(llvm_ir_size, 4);
128 void *buffer = CALLOC(1, size);
129 uint32_t *ptr = (uint32_t*)buffer;
130
131 if (!buffer)
132 return NULL;
133
134 *ptr++ = size;
135 ptr++; /* CRC32 is calculated at the end. */
136
137 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
138 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
139 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
140 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
141 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
142 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
143 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
144 assert((char *)ptr - (char *)buffer == size);
145
146 /* Compute CRC32. */
147 ptr = (uint32_t*)buffer;
148 ptr++;
149 *ptr = util_hash_crc32(ptr + 1, size - 8);
150
151 return buffer;
152 }
153
154 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
155 {
156 uint32_t *ptr = (uint32_t*)binary;
157 uint32_t size = *ptr++;
158 uint32_t crc32 = *ptr++;
159 unsigned chunk_size;
160
161 if (util_hash_crc32(ptr, size - 8) != crc32) {
162 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
163 return false;
164 }
165
166 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
167 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
168 ptr = read_chunk(ptr, (void**)&shader->binary.code,
169 &shader->binary.code_size);
170 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
171 &shader->binary.rodata_size);
172 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
173 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
174 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
175 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
176
177 return true;
178 }
179
180 /**
181 * Insert a shader into the cache. It's assumed the shader is not in the cache.
182 * Use si_shader_cache_load_shader before calling this.
183 *
184 * Returns false on failure, in which case the tgsi_binary should be freed.
185 */
186 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
187 void *tgsi_binary,
188 struct si_shader *shader,
189 bool insert_into_disk_cache)
190 {
191 void *hw_binary;
192 struct hash_entry *entry;
193 uint8_t key[CACHE_KEY_SIZE];
194
195 entry = _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
196 if (entry)
197 return false; /* already added */
198
199 hw_binary = si_get_shader_binary(shader);
200 if (!hw_binary)
201 return false;
202
203 if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
204 hw_binary) == NULL) {
205 FREE(hw_binary);
206 return false;
207 }
208
209 if (sscreen->b.disk_shader_cache && insert_into_disk_cache) {
210 disk_cache_compute_key(sscreen->b.disk_shader_cache, tgsi_binary,
211 *((uint32_t *)tgsi_binary), key);
212 disk_cache_put(sscreen->b.disk_shader_cache, key, hw_binary,
213 *((uint32_t *) hw_binary));
214 }
215
216 return true;
217 }
218
219 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
220 void *tgsi_binary,
221 struct si_shader *shader)
222 {
223 struct hash_entry *entry =
224 _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
225 if (!entry) {
226 if (sscreen->b.disk_shader_cache) {
227 unsigned char sha1[CACHE_KEY_SIZE];
228 size_t tg_size = *((uint32_t *) tgsi_binary);
229
230 disk_cache_compute_key(sscreen->b.disk_shader_cache,
231 tgsi_binary, tg_size, sha1);
232
233 size_t binary_size;
234 uint8_t *buffer =
235 disk_cache_get(sscreen->b.disk_shader_cache,
236 sha1, &binary_size);
237 if (!buffer)
238 return false;
239
240 if (binary_size < sizeof(uint32_t) ||
241 *((uint32_t*)buffer) != binary_size) {
242 /* Something has gone wrong discard the item
243 * from the cache and rebuild/link from
244 * source.
245 */
246 assert(!"Invalid radeonsi shader disk cache "
247 "item!");
248
249 disk_cache_remove(sscreen->b.disk_shader_cache,
250 sha1);
251 free(buffer);
252
253 return false;
254 }
255
256 if (!si_load_shader_binary(shader, buffer)) {
257 free(buffer);
258 return false;
259 }
260 free(buffer);
261
262 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary,
263 shader, false))
264 FREE(tgsi_binary);
265 } else {
266 return false;
267 }
268 } else {
269 if (si_load_shader_binary(shader, entry->data))
270 FREE(tgsi_binary);
271 else
272 return false;
273 }
274 p_atomic_inc(&sscreen->b.num_shader_cache_hits);
275 return true;
276 }
277
278 static uint32_t si_shader_cache_key_hash(const void *key)
279 {
280 /* The first dword is the key size. */
281 return util_hash_crc32(key, *(uint32_t*)key);
282 }
283
284 static bool si_shader_cache_key_equals(const void *a, const void *b)
285 {
286 uint32_t *keya = (uint32_t*)a;
287 uint32_t *keyb = (uint32_t*)b;
288
289 /* The first dword is the key size. */
290 if (*keya != *keyb)
291 return false;
292
293 return memcmp(keya, keyb, *keya) == 0;
294 }
295
296 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
297 {
298 FREE((void*)entry->key);
299 FREE(entry->data);
300 }
301
302 bool si_init_shader_cache(struct si_screen *sscreen)
303 {
304 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
305 sscreen->shader_cache =
306 _mesa_hash_table_create(NULL,
307 si_shader_cache_key_hash,
308 si_shader_cache_key_equals);
309
310 return sscreen->shader_cache != NULL;
311 }
312
313 void si_destroy_shader_cache(struct si_screen *sscreen)
314 {
315 if (sscreen->shader_cache)
316 _mesa_hash_table_destroy(sscreen->shader_cache,
317 si_destroy_shader_cache_entry);
318 mtx_destroy(&sscreen->shader_cache_mutex);
319 }
320
321 /* SHADER STATES */
322
323 static void si_set_tesseval_regs(struct si_screen *sscreen,
324 struct si_shader *shader,
325 struct si_pm4_state *pm4)
326 {
327 struct tgsi_shader_info *info = &shader->selector->info;
328 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
329 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
330 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
331 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
332 unsigned type, partitioning, topology, distribution_mode;
333
334 switch (tes_prim_mode) {
335 case PIPE_PRIM_LINES:
336 type = V_028B6C_TESS_ISOLINE;
337 break;
338 case PIPE_PRIM_TRIANGLES:
339 type = V_028B6C_TESS_TRIANGLE;
340 break;
341 case PIPE_PRIM_QUADS:
342 type = V_028B6C_TESS_QUAD;
343 break;
344 default:
345 assert(0);
346 return;
347 }
348
349 switch (tes_spacing) {
350 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
351 partitioning = V_028B6C_PART_FRAC_ODD;
352 break;
353 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
354 partitioning = V_028B6C_PART_FRAC_EVEN;
355 break;
356 case PIPE_TESS_SPACING_EQUAL:
357 partitioning = V_028B6C_PART_INTEGER;
358 break;
359 default:
360 assert(0);
361 return;
362 }
363
364 if (tes_point_mode)
365 topology = V_028B6C_OUTPUT_POINT;
366 else if (tes_prim_mode == PIPE_PRIM_LINES)
367 topology = V_028B6C_OUTPUT_LINE;
368 else if (tes_vertex_order_cw)
369 /* for some reason, this must be the other way around */
370 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
371 else
372 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
373
374 if (sscreen->has_distributed_tess) {
375 if (sscreen->b.family == CHIP_FIJI ||
376 sscreen->b.family >= CHIP_POLARIS10)
377 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
378 else
379 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
380 } else
381 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
382
383 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
384 S_028B6C_TYPE(type) |
385 S_028B6C_PARTITIONING(partitioning) |
386 S_028B6C_TOPOLOGY(topology) |
387 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
388 }
389
390 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
391 * whether the "fractional odd" tessellation spacing is used.
392 *
393 * Possible VGT configurations and which state should set the register:
394 *
395 * Reg set in | VGT shader configuration | Value
396 * ------------------------------------------------------
397 * VS as VS | VS | 30
398 * VS as ES | ES -> GS -> VS | 30
399 * TES as VS | LS -> HS -> VS | 14 or 30
400 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
401 */
402 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
403 struct si_shader *shader,
404 struct si_pm4_state *pm4)
405 {
406 unsigned type = shader->selector->type;
407
408 if (sscreen->b.family < CHIP_POLARIS10)
409 return;
410
411 /* VS as VS, or VS as ES: */
412 if ((type == PIPE_SHADER_VERTEX &&
413 !shader->key.as_ls &&
414 !shader->is_gs_copy_shader) ||
415 /* TES as VS, or TES as ES: */
416 type == PIPE_SHADER_TESS_EVAL) {
417 unsigned vtx_reuse_depth = 30;
418
419 if (type == PIPE_SHADER_TESS_EVAL &&
420 shader->selector->info.properties[TGSI_PROPERTY_TES_SPACING] ==
421 PIPE_TESS_SPACING_FRACTIONAL_ODD)
422 vtx_reuse_depth = 14;
423
424 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
425 vtx_reuse_depth);
426 }
427 }
428
429 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
430 {
431 if (shader->pm4)
432 si_pm4_clear_state(shader->pm4);
433 else
434 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
435
436 return shader->pm4;
437 }
438
439 static void si_shader_ls(struct si_shader *shader)
440 {
441 struct si_pm4_state *pm4;
442 unsigned vgpr_comp_cnt;
443 uint64_t va;
444
445 pm4 = si_get_shader_pm4_state(shader);
446 if (!pm4)
447 return;
448
449 va = shader->bo->gpu_address;
450 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
451
452 /* We need at least 2 components for LS.
453 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
454 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 1;
455
456 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
457 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
458
459 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
460 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
461 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
462 S_00B528_DX10_CLAMP(1) |
463 S_00B528_FLOAT_MODE(shader->config.float_mode);
464 shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_LS_NUM_USER_SGPR) |
465 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
466 }
467
468 static void si_shader_hs(struct si_shader *shader)
469 {
470 struct si_pm4_state *pm4;
471 uint64_t va;
472
473 pm4 = si_get_shader_pm4_state(shader);
474 if (!pm4)
475 return;
476
477 va = shader->bo->gpu_address;
478 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
479
480 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
481 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
482 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
483 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
484 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
485 S_00B428_DX10_CLAMP(1) |
486 S_00B428_FLOAT_MODE(shader->config.float_mode));
487 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
488 S_00B42C_USER_SGPR(SI_TCS_NUM_USER_SGPR) |
489 S_00B42C_OC_LDS_EN(1) |
490 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
491 }
492
493 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
494 {
495 struct si_pm4_state *pm4;
496 unsigned num_user_sgprs;
497 unsigned vgpr_comp_cnt;
498 uint64_t va;
499 unsigned oc_lds_en;
500
501 pm4 = si_get_shader_pm4_state(shader);
502 if (!pm4)
503 return;
504
505 va = shader->bo->gpu_address;
506 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
507
508 if (shader->selector->type == PIPE_SHADER_VERTEX) {
509 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
510 num_user_sgprs = SI_ES_NUM_USER_SGPR;
511 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
512 vgpr_comp_cnt = 3; /* all components are needed for TES */
513 num_user_sgprs = SI_TES_NUM_USER_SGPR;
514 } else
515 unreachable("invalid shader selector type");
516
517 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
518
519 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
520 shader->selector->esgs_itemsize / 4);
521 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
522 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
523 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
524 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
525 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
526 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
527 S_00B328_DX10_CLAMP(1) |
528 S_00B328_FLOAT_MODE(shader->config.float_mode));
529 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
530 S_00B32C_USER_SGPR(num_user_sgprs) |
531 S_00B32C_OC_LDS_EN(oc_lds_en) |
532 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
533
534 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
535 si_set_tesseval_regs(sscreen, shader, pm4);
536
537 polaris_set_vgt_vertex_reuse(sscreen, shader, pm4);
538 }
539
540 /**
541 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
542 * geometry shader.
543 */
544 static uint32_t si_vgt_gs_mode(struct si_shader_selector *sel)
545 {
546 unsigned gs_max_vert_out = sel->gs_max_out_vertices;
547 unsigned cut_mode;
548
549 if (gs_max_vert_out <= 128) {
550 cut_mode = V_028A40_GS_CUT_128;
551 } else if (gs_max_vert_out <= 256) {
552 cut_mode = V_028A40_GS_CUT_256;
553 } else if (gs_max_vert_out <= 512) {
554 cut_mode = V_028A40_GS_CUT_512;
555 } else {
556 assert(gs_max_vert_out <= 1024);
557 cut_mode = V_028A40_GS_CUT_1024;
558 }
559
560 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
561 S_028A40_CUT_MODE(cut_mode)|
562 S_028A40_ES_WRITE_OPTIMIZE(1) |
563 S_028A40_GS_WRITE_OPTIMIZE(1);
564 }
565
566 static void si_shader_gs(struct si_shader *shader)
567 {
568 struct si_shader_selector *sel = shader->selector;
569 const ubyte *num_components = sel->info.num_stream_output_components;
570 unsigned gs_num_invocations = sel->gs_num_invocations;
571 struct si_pm4_state *pm4;
572 uint64_t va;
573 unsigned max_stream = sel->max_gs_stream;
574 unsigned offset;
575
576 pm4 = si_get_shader_pm4_state(shader);
577 if (!pm4)
578 return;
579
580 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(shader->selector));
581
582 offset = num_components[0] * sel->gs_max_out_vertices;
583 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, offset);
584 if (max_stream >= 1)
585 offset += num_components[1] * sel->gs_max_out_vertices;
586 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, offset);
587 if (max_stream >= 2)
588 offset += num_components[2] * sel->gs_max_out_vertices;
589 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, offset);
590 if (max_stream >= 3)
591 offset += num_components[3] * sel->gs_max_out_vertices;
592 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
593
594 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
595 assert(offset < (1 << 15));
596
597 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, shader->selector->gs_max_out_vertices);
598
599 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, num_components[0]);
600 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? num_components[1] : 0);
601 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? num_components[2] : 0);
602 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? num_components[3] : 0);
603
604 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
605 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
606 S_028B90_ENABLE(gs_num_invocations > 0));
607
608 va = shader->bo->gpu_address;
609 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
610 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
611 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
612
613 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
614 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
615 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
616 S_00B228_DX10_CLAMP(1) |
617 S_00B228_FLOAT_MODE(shader->config.float_mode));
618 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
619 S_00B22C_USER_SGPR(SI_GS_NUM_USER_SGPR) |
620 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
621 }
622
623 /**
624 * Compute the state for \p shader, which will run as a vertex shader on the
625 * hardware.
626 *
627 * If \p gs is non-NULL, it points to the geometry shader for which this shader
628 * is the copy shader.
629 */
630 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
631 struct si_shader_selector *gs)
632 {
633 struct si_pm4_state *pm4;
634 unsigned num_user_sgprs;
635 unsigned nparams, vgpr_comp_cnt;
636 uint64_t va;
637 unsigned oc_lds_en;
638 unsigned window_space =
639 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
640 bool enable_prim_id = si_vs_exports_prim_id(shader);
641
642 pm4 = si_get_shader_pm4_state(shader);
643 if (!pm4)
644 return;
645
646 /* We always write VGT_GS_MODE in the VS state, because every switch
647 * between different shader pipelines involving a different GS or no
648 * GS at all involves a switch of the VS (different GS use different
649 * copy shaders). On the other hand, when the API switches from a GS to
650 * no GS and then back to the same GS used originally, the GS state is
651 * not sent again.
652 */
653 if (!gs) {
654 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
655 S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
656 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
657 } else {
658 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
659 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
660 }
661
662 va = shader->bo->gpu_address;
663 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
664
665 if (gs) {
666 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
667 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
668 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
669 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
670 num_user_sgprs = SI_VS_NUM_USER_SGPR;
671 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
672 vgpr_comp_cnt = 3; /* all components are needed for TES */
673 num_user_sgprs = SI_TES_NUM_USER_SGPR;
674 } else
675 unreachable("invalid shader selector type");
676
677 /* VS is required to export at least one param. */
678 nparams = MAX2(shader->info.nr_param_exports, 1);
679 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
680 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
681
682 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
683 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
684 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
685 V_02870C_SPI_SHADER_4COMP :
686 V_02870C_SPI_SHADER_NONE) |
687 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
688 V_02870C_SPI_SHADER_4COMP :
689 V_02870C_SPI_SHADER_NONE) |
690 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
691 V_02870C_SPI_SHADER_4COMP :
692 V_02870C_SPI_SHADER_NONE));
693
694 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
695
696 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
697 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
698 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
699 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
700 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
701 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
702 S_00B128_DX10_CLAMP(1) |
703 S_00B128_FLOAT_MODE(shader->config.float_mode));
704 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
705 S_00B12C_USER_SGPR(num_user_sgprs) |
706 S_00B12C_OC_LDS_EN(oc_lds_en) |
707 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
708 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
709 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
710 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
711 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
712 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
713 if (window_space)
714 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
715 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
716 else
717 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
718 S_028818_VTX_W0_FMT(1) |
719 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
720 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
721 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
722
723 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
724 si_set_tesseval_regs(sscreen, shader, pm4);
725
726 polaris_set_vgt_vertex_reuse(sscreen, shader, pm4);
727 }
728
729 static unsigned si_get_ps_num_interp(struct si_shader *ps)
730 {
731 struct tgsi_shader_info *info = &ps->selector->info;
732 unsigned num_colors = !!(info->colors_read & 0x0f) +
733 !!(info->colors_read & 0xf0);
734 unsigned num_interp = ps->selector->info.num_inputs +
735 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
736
737 assert(num_interp <= 32);
738 return MIN2(num_interp, 32);
739 }
740
741 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
742 {
743 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
744 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
745
746 /* If the i-th target format is set, all previous target formats must
747 * be non-zero to avoid hangs.
748 */
749 for (i = 0; i < num_targets; i++)
750 if (!(value & (0xf << (i * 4))))
751 value |= V_028714_SPI_SHADER_32_R << (i * 4);
752
753 return value;
754 }
755
756 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
757 {
758 unsigned i, cb_shader_mask = 0;
759
760 for (i = 0; i < 8; i++) {
761 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
762 case V_028714_SPI_SHADER_ZERO:
763 break;
764 case V_028714_SPI_SHADER_32_R:
765 cb_shader_mask |= 0x1 << (i * 4);
766 break;
767 case V_028714_SPI_SHADER_32_GR:
768 cb_shader_mask |= 0x3 << (i * 4);
769 break;
770 case V_028714_SPI_SHADER_32_AR:
771 cb_shader_mask |= 0x9 << (i * 4);
772 break;
773 case V_028714_SPI_SHADER_FP16_ABGR:
774 case V_028714_SPI_SHADER_UNORM16_ABGR:
775 case V_028714_SPI_SHADER_SNORM16_ABGR:
776 case V_028714_SPI_SHADER_UINT16_ABGR:
777 case V_028714_SPI_SHADER_SINT16_ABGR:
778 case V_028714_SPI_SHADER_32_ABGR:
779 cb_shader_mask |= 0xf << (i * 4);
780 break;
781 default:
782 assert(0);
783 }
784 }
785 return cb_shader_mask;
786 }
787
788 static void si_shader_ps(struct si_shader *shader)
789 {
790 struct tgsi_shader_info *info = &shader->selector->info;
791 struct si_pm4_state *pm4;
792 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
793 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
794 uint64_t va;
795 unsigned input_ena = shader->config.spi_ps_input_ena;
796
797 /* we need to enable at least one of them, otherwise we hang the GPU */
798 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
799 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
800 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
801 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
802 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
803 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
804 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
805 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
806 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
807 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
808 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
809 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
810 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
811 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
812
813 /* Validate interpolation optimization flags (read as implications). */
814 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
815 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
816 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
817 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
818 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
819 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
820 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
821 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
822 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
823 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
824 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
825 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
826 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
827 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
828 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
829 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
830 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
831 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
832
833 /* Validate cases when the optimizations are off (read as implications). */
834 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
835 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
836 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
837 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
838 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
839 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
840
841 pm4 = si_get_shader_pm4_state(shader);
842 if (!pm4)
843 return;
844
845 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
846 * Possible vaules:
847 * 0 -> Position = pixel center
848 * 1 -> Position = pixel centroid
849 * 2 -> Position = at sample position
850 *
851 * From GLSL 4.5 specification, section 7.1:
852 * "The variable gl_FragCoord is available as an input variable from
853 * within fragment shaders and it holds the window relative coordinates
854 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
855 * value can be for any location within the pixel, or one of the
856 * fragment samples. The use of centroid does not further restrict
857 * this value to be inside the current primitive."
858 *
859 * Meaning that centroid has no effect and we can return anything within
860 * the pixel. Thus, return the value at sample position, because that's
861 * the most accurate one shaders can get.
862 */
863 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
864
865 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
866 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
867 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
868
869 spi_shader_col_format = si_get_spi_shader_col_format(shader);
870 cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
871
872 /* Ensure that some export memory is always allocated, for two reasons:
873 *
874 * 1) Correctness: The hardware ignores the EXEC mask if no export
875 * memory is allocated, so KILL and alpha test do not work correctly
876 * without this.
877 * 2) Performance: Every shader needs at least a NULL export, even when
878 * it writes no color/depth output. The NULL export instruction
879 * stalls without this setting.
880 *
881 * Don't add this to CB_SHADER_MASK.
882 */
883 if (!spi_shader_col_format &&
884 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
885 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
886
887 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
888 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
889 shader->config.spi_ps_input_addr);
890
891 /* Set interpolation controls. */
892 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
893
894 /* Set registers. */
895 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
896 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
897
898 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
899 si_get_spi_shader_z_format(info->writes_z,
900 info->writes_stencil,
901 info->writes_samplemask));
902
903 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
904 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
905
906 va = shader->bo->gpu_address;
907 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
908 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
909 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
910
911 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
912 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
913 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
914 S_00B028_DX10_CLAMP(1) |
915 S_00B028_FLOAT_MODE(shader->config.float_mode));
916 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
917 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
918 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
919 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
920 }
921
922 static void si_shader_init_pm4_state(struct si_screen *sscreen,
923 struct si_shader *shader)
924 {
925 switch (shader->selector->type) {
926 case PIPE_SHADER_VERTEX:
927 if (shader->key.as_ls)
928 si_shader_ls(shader);
929 else if (shader->key.as_es)
930 si_shader_es(sscreen, shader);
931 else
932 si_shader_vs(sscreen, shader, NULL);
933 break;
934 case PIPE_SHADER_TESS_CTRL:
935 si_shader_hs(shader);
936 break;
937 case PIPE_SHADER_TESS_EVAL:
938 if (shader->key.as_es)
939 si_shader_es(sscreen, shader);
940 else
941 si_shader_vs(sscreen, shader, NULL);
942 break;
943 case PIPE_SHADER_GEOMETRY:
944 si_shader_gs(shader);
945 break;
946 case PIPE_SHADER_FRAGMENT:
947 si_shader_ps(shader);
948 break;
949 default:
950 assert(0);
951 }
952 }
953
954 static unsigned si_get_alpha_test_func(struct si_context *sctx)
955 {
956 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
957 if (sctx->queued.named.dsa)
958 return sctx->queued.named.dsa->alpha_func;
959
960 return PIPE_FUNC_ALWAYS;
961 }
962
963 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
964 struct si_shader_selector *vs,
965 struct si_shader_key *key)
966 {
967 struct si_shader_selector *ps = sctx->ps_shader.cso;
968
969 key->opt.hw_vs.clip_disable =
970 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
971 (vs->info.clipdist_writemask ||
972 vs->info.writes_clipvertex) &&
973 !vs->info.culldist_writemask;
974
975 /* Find out if PS is disabled. */
976 bool ps_disabled = true;
977 if (ps) {
978 bool ps_modifies_zs = ps->info.uses_kill ||
979 ps->info.writes_z ||
980 ps->info.writes_stencil ||
981 ps->info.writes_samplemask ||
982 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
983
984 unsigned ps_colormask = sctx->framebuffer.colorbuf_enabled_4bit &
985 sctx->queued.named.blend->cb_target_mask;
986 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
987 ps_colormask &= ps->colors_written_4bit;
988
989 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
990 (!ps_colormask &&
991 !ps_modifies_zs &&
992 !ps->info.writes_memory);
993 }
994
995 /* Find out which VS outputs aren't used by the PS. */
996 uint64_t outputs_written = vs->outputs_written;
997 uint32_t outputs_written2 = vs->outputs_written2;
998 uint64_t inputs_read = 0;
999 uint32_t inputs_read2 = 0;
1000
1001 outputs_written &= ~0x3; /* ignore POSITION, PSIZE */
1002
1003 if (!ps_disabled) {
1004 inputs_read = ps->inputs_read;
1005 inputs_read2 = ps->inputs_read2;
1006 }
1007
1008 uint64_t linked = outputs_written & inputs_read;
1009 uint32_t linked2 = outputs_written2 & inputs_read2;
1010
1011 key->opt.hw_vs.kill_outputs = ~linked & outputs_written;
1012 key->opt.hw_vs.kill_outputs2 = ~linked2 & outputs_written2;
1013 }
1014
1015 /* Compute the key for the hw shader variant */
1016 static inline void si_shader_selector_key(struct pipe_context *ctx,
1017 struct si_shader_selector *sel,
1018 struct si_shader_key *key)
1019 {
1020 struct si_context *sctx = (struct si_context *)ctx;
1021 unsigned i;
1022
1023 memset(key, 0, sizeof(*key));
1024
1025 switch (sel->type) {
1026 case PIPE_SHADER_VERTEX:
1027 if (sctx->vertex_elements) {
1028 unsigned count = MIN2(sel->info.num_inputs,
1029 sctx->vertex_elements->count);
1030 for (i = 0; i < count; ++i)
1031 key->part.vs.prolog.instance_divisors[i] =
1032 sctx->vertex_elements->elements[i].instance_divisor;
1033
1034 memcpy(key->mono.vs.fix_fetch,
1035 sctx->vertex_elements->fix_fetch, count);
1036 }
1037 if (sctx->tes_shader.cso)
1038 key->as_ls = 1;
1039 else if (sctx->gs_shader.cso)
1040 key->as_es = 1;
1041 else {
1042 si_shader_selector_key_hw_vs(sctx, sel, key);
1043
1044 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1045 key->part.vs.epilog.export_prim_id = 1;
1046 }
1047 break;
1048 case PIPE_SHADER_TESS_CTRL:
1049 key->part.tcs.epilog.prim_mode =
1050 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1051 key->part.tcs.epilog.tes_reads_tess_factors =
1052 sctx->tes_shader.cso->info.reads_tess_factors;
1053
1054 if (sel == sctx->fixed_func_tcs_shader.cso)
1055 key->mono.tcs.inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1056 break;
1057 case PIPE_SHADER_TESS_EVAL:
1058 if (sctx->gs_shader.cso)
1059 key->as_es = 1;
1060 else {
1061 si_shader_selector_key_hw_vs(sctx, sel, key);
1062
1063 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1064 key->part.tes.epilog.export_prim_id = 1;
1065 }
1066 break;
1067 case PIPE_SHADER_GEOMETRY:
1068 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1069 break;
1070 case PIPE_SHADER_FRAGMENT: {
1071 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1072 struct si_state_blend *blend = sctx->queued.named.blend;
1073
1074 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1075 sel->info.colors_written == 0x1)
1076 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1077
1078 if (blend) {
1079 /* Select the shader color format based on whether
1080 * blending or alpha are needed.
1081 */
1082 key->part.ps.epilog.spi_shader_col_format =
1083 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1084 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1085 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1086 sctx->framebuffer.spi_shader_col_format_blend) |
1087 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1088 sctx->framebuffer.spi_shader_col_format_alpha) |
1089 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1090 sctx->framebuffer.spi_shader_col_format);
1091
1092 /* The output for dual source blending should have
1093 * the same format as the first output.
1094 */
1095 if (blend->dual_src_blend)
1096 key->part.ps.epilog.spi_shader_col_format |=
1097 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1098 } else
1099 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1100
1101 /* If alpha-to-coverage is enabled, we have to export alpha
1102 * even if there is no color buffer.
1103 */
1104 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1105 blend && blend->alpha_to_coverage)
1106 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1107
1108 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1109 * to the range supported by the type if a channel has less
1110 * than 16 bits and the export format is 16_ABGR.
1111 */
1112 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII) {
1113 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1114 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1115 }
1116
1117 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1118 if (!key->part.ps.epilog.last_cbuf) {
1119 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1120 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1121 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1122 }
1123
1124 if (rs) {
1125 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
1126 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
1127 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
1128 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
1129
1130 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1131 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1132
1133 if (sctx->queued.named.blend) {
1134 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1135 rs->multisample_enable;
1136 }
1137
1138 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1139 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1140 (is_line && rs->line_smooth)) &&
1141 sctx->framebuffer.nr_samples <= 1;
1142 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1143
1144 if (rs->force_persample_interp &&
1145 rs->multisample_enable &&
1146 sctx->framebuffer.nr_samples > 1 &&
1147 sctx->ps_iter_samples > 1) {
1148 key->part.ps.prolog.force_persp_sample_interp =
1149 sel->info.uses_persp_center ||
1150 sel->info.uses_persp_centroid;
1151
1152 key->part.ps.prolog.force_linear_sample_interp =
1153 sel->info.uses_linear_center ||
1154 sel->info.uses_linear_centroid;
1155 } else if (rs->multisample_enable &&
1156 sctx->framebuffer.nr_samples > 1) {
1157 key->part.ps.prolog.bc_optimize_for_persp =
1158 sel->info.uses_persp_center &&
1159 sel->info.uses_persp_centroid;
1160 key->part.ps.prolog.bc_optimize_for_linear =
1161 sel->info.uses_linear_center &&
1162 sel->info.uses_linear_centroid;
1163 } else {
1164 /* Make sure SPI doesn't compute more than 1 pair
1165 * of (i,j), which is the optimization here. */
1166 key->part.ps.prolog.force_persp_center_interp =
1167 sel->info.uses_persp_center +
1168 sel->info.uses_persp_centroid +
1169 sel->info.uses_persp_sample > 1;
1170
1171 key->part.ps.prolog.force_linear_center_interp =
1172 sel->info.uses_linear_center +
1173 sel->info.uses_linear_centroid +
1174 sel->info.uses_linear_sample > 1;
1175 }
1176 }
1177
1178 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1179 break;
1180 }
1181 default:
1182 assert(0);
1183 }
1184 }
1185
1186 static void si_build_shader_variant(void *job, int thread_index)
1187 {
1188 struct si_shader *shader = (struct si_shader *)job;
1189 struct si_shader_selector *sel = shader->selector;
1190 struct si_screen *sscreen = sel->screen;
1191 LLVMTargetMachineRef tm;
1192 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1193 int r;
1194
1195 if (thread_index >= 0) {
1196 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1197 tm = sscreen->tm[thread_index];
1198 if (!debug->async)
1199 debug = NULL;
1200 } else {
1201 tm = shader->compiler_ctx_state.tm;
1202 }
1203
1204 r = si_shader_create(sscreen, tm, shader, debug);
1205 if (unlikely(r)) {
1206 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1207 sel->type, r);
1208 shader->compilation_failed = true;
1209 return;
1210 }
1211
1212 if (shader->compiler_ctx_state.is_debug_context) {
1213 FILE *f = open_memstream(&shader->shader_log,
1214 &shader->shader_log_size);
1215 if (f) {
1216 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1217 fclose(f);
1218 }
1219 }
1220
1221 si_shader_init_pm4_state(sscreen, shader);
1222 }
1223
1224 /* Select the hw shader variant depending on the current state. */
1225 static int si_shader_select_with_key(struct si_screen *sscreen,
1226 struct si_shader_ctx_state *state,
1227 struct si_compiler_ctx_state *compiler_state,
1228 struct si_shader_key *key,
1229 int thread_index)
1230 {
1231 static const struct si_shader_key zeroed;
1232 struct si_shader_selector *sel = state->cso;
1233 struct si_shader *current = state->current;
1234 struct si_shader *iter, *shader = NULL;
1235
1236 if (unlikely(sscreen->b.debug_flags & DBG_NO_OPT_VARIANT)) {
1237 memset(&key->opt, 0, sizeof(key->opt));
1238 }
1239
1240 again:
1241 /* Check if we don't need to change anything.
1242 * This path is also used for most shaders that don't need multiple
1243 * variants, it will cost just a computation of the key and this
1244 * test. */
1245 if (likely(current &&
1246 memcmp(&current->key, key, sizeof(*key)) == 0 &&
1247 (!current->is_optimized ||
1248 util_queue_fence_is_signalled(&current->optimized_ready))))
1249 return current->compilation_failed ? -1 : 0;
1250
1251 /* This must be done before the mutex is locked, because async GS
1252 * compilation calls this function too, and therefore must enter
1253 * the mutex first.
1254 *
1255 * Only wait if we are in a draw call. Don't wait if we are
1256 * in a compiler thread.
1257 */
1258 if (thread_index < 0)
1259 util_queue_fence_wait(&sel->ready);
1260
1261 mtx_lock(&sel->mutex);
1262
1263 /* Find the shader variant. */
1264 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1265 /* Don't check the "current" shader. We checked it above. */
1266 if (current != iter &&
1267 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1268 /* If it's an optimized shader and its compilation has
1269 * been started but isn't done, use the unoptimized
1270 * shader so as not to cause a stall due to compilation.
1271 */
1272 if (iter->is_optimized &&
1273 !util_queue_fence_is_signalled(&iter->optimized_ready)) {
1274 memset(&key->opt, 0, sizeof(key->opt));
1275 mtx_unlock(&sel->mutex);
1276 goto again;
1277 }
1278
1279 if (iter->compilation_failed) {
1280 mtx_unlock(&sel->mutex);
1281 return -1; /* skip the draw call */
1282 }
1283
1284 state->current = iter;
1285 mtx_unlock(&sel->mutex);
1286 return 0;
1287 }
1288 }
1289
1290 /* Build a new shader. */
1291 shader = CALLOC_STRUCT(si_shader);
1292 if (!shader) {
1293 mtx_unlock(&sel->mutex);
1294 return -ENOMEM;
1295 }
1296 shader->selector = sel;
1297 shader->key = *key;
1298 shader->compiler_ctx_state = *compiler_state;
1299
1300 /* Compile the main shader part if it doesn't exist. This can happen
1301 * if the initial guess was wrong. */
1302 struct si_shader **mainp = si_get_main_shader_part(sel, key);
1303 bool is_pure_monolithic =
1304 sscreen->use_monolithic_shaders ||
1305 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1306
1307 if (!*mainp && !is_pure_monolithic) {
1308 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1309
1310 if (!main_part) {
1311 FREE(shader);
1312 mtx_unlock(&sel->mutex);
1313 return -ENOMEM; /* skip the draw call */
1314 }
1315
1316 main_part->selector = sel;
1317 main_part->key.as_es = key->as_es;
1318 main_part->key.as_ls = key->as_ls;
1319
1320 if (si_compile_tgsi_shader(sscreen, compiler_state->tm,
1321 main_part, false,
1322 &compiler_state->debug) != 0) {
1323 FREE(main_part);
1324 FREE(shader);
1325 mtx_unlock(&sel->mutex);
1326 return -ENOMEM; /* skip the draw call */
1327 }
1328 *mainp = main_part;
1329 }
1330
1331 /* Monolithic-only shaders don't make a distinction between optimized
1332 * and unoptimized. */
1333 shader->is_monolithic =
1334 is_pure_monolithic ||
1335 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1336
1337 shader->is_optimized =
1338 !is_pure_monolithic &&
1339 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1340 if (shader->is_optimized)
1341 util_queue_fence_init(&shader->optimized_ready);
1342
1343 if (!sel->last_variant) {
1344 sel->first_variant = shader;
1345 sel->last_variant = shader;
1346 } else {
1347 sel->last_variant->next_variant = shader;
1348 sel->last_variant = shader;
1349 }
1350
1351 /* If it's an optimized shader, compile it asynchronously. */
1352 if (shader->is_optimized &&
1353 !is_pure_monolithic &&
1354 thread_index < 0) {
1355 /* Compile it asynchronously. */
1356 util_queue_add_job(&sscreen->shader_compiler_queue,
1357 shader, &shader->optimized_ready,
1358 si_build_shader_variant, NULL);
1359
1360 /* Use the default (unoptimized) shader for now. */
1361 memset(&key->opt, 0, sizeof(key->opt));
1362 mtx_unlock(&sel->mutex);
1363 goto again;
1364 }
1365
1366 assert(!shader->is_optimized);
1367 si_build_shader_variant(shader, thread_index);
1368
1369 if (!shader->compilation_failed)
1370 state->current = shader;
1371
1372 mtx_unlock(&sel->mutex);
1373 return shader->compilation_failed ? -1 : 0;
1374 }
1375
1376 static int si_shader_select(struct pipe_context *ctx,
1377 struct si_shader_ctx_state *state,
1378 struct si_compiler_ctx_state *compiler_state)
1379 {
1380 struct si_context *sctx = (struct si_context *)ctx;
1381 struct si_shader_key key;
1382
1383 si_shader_selector_key(ctx, state->cso, &key);
1384 return si_shader_select_with_key(sctx->screen, state, compiler_state,
1385 &key, -1);
1386 }
1387
1388 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1389 struct si_shader_key *key)
1390 {
1391 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1392
1393 switch (info->processor) {
1394 case PIPE_SHADER_VERTEX:
1395 switch (next_shader) {
1396 case PIPE_SHADER_GEOMETRY:
1397 key->as_es = 1;
1398 break;
1399 case PIPE_SHADER_TESS_CTRL:
1400 case PIPE_SHADER_TESS_EVAL:
1401 key->as_ls = 1;
1402 break;
1403 default:
1404 /* If POSITION isn't written, it can't be a HW VS.
1405 * Assume that it's a HW LS. (the next shader is TCS)
1406 * This heuristic is needed for separate shader objects.
1407 */
1408 if (!info->writes_position)
1409 key->as_ls = 1;
1410 }
1411 break;
1412
1413 case PIPE_SHADER_TESS_EVAL:
1414 if (next_shader == PIPE_SHADER_GEOMETRY ||
1415 !info->writes_position)
1416 key->as_es = 1;
1417 break;
1418 }
1419 }
1420
1421 /**
1422 * Compile the main shader part or the monolithic shader as part of
1423 * si_shader_selector initialization. Since it can be done asynchronously,
1424 * there is no way to report compile failures to applications.
1425 */
1426 void si_init_shader_selector_async(void *job, int thread_index)
1427 {
1428 struct si_shader_selector *sel = (struct si_shader_selector *)job;
1429 struct si_screen *sscreen = sel->screen;
1430 LLVMTargetMachineRef tm;
1431 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
1432 unsigned i;
1433
1434 if (thread_index >= 0) {
1435 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1436 tm = sscreen->tm[thread_index];
1437 if (!debug->async)
1438 debug = NULL;
1439 } else {
1440 tm = sel->compiler_ctx_state.tm;
1441 }
1442
1443 /* Compile the main shader part for use with a prolog and/or epilog.
1444 * If this fails, the driver will try to compile a monolithic shader
1445 * on demand.
1446 */
1447 if (!sscreen->use_monolithic_shaders) {
1448 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1449 void *tgsi_binary;
1450
1451 if (!shader) {
1452 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
1453 return;
1454 }
1455
1456 shader->selector = sel;
1457 si_parse_next_shader_property(&sel->info, &shader->key);
1458
1459 tgsi_binary = si_get_tgsi_binary(sel);
1460
1461 /* Try to load the shader from the shader cache. */
1462 mtx_lock(&sscreen->shader_cache_mutex);
1463
1464 if (tgsi_binary &&
1465 si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
1466 mtx_unlock(&sscreen->shader_cache_mutex);
1467 } else {
1468 mtx_unlock(&sscreen->shader_cache_mutex);
1469
1470 /* Compile the shader if it hasn't been loaded from the cache. */
1471 if (si_compile_tgsi_shader(sscreen, tm, shader, false,
1472 debug) != 0) {
1473 FREE(shader);
1474 FREE(tgsi_binary);
1475 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
1476 return;
1477 }
1478
1479 if (tgsi_binary) {
1480 mtx_lock(&sscreen->shader_cache_mutex);
1481 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary, shader, true))
1482 FREE(tgsi_binary);
1483 mtx_unlock(&sscreen->shader_cache_mutex);
1484 }
1485 }
1486
1487 *si_get_main_shader_part(sel, &shader->key) = shader;
1488
1489 /* Unset "outputs_written" flags for outputs converted to
1490 * DEFAULT_VAL, so that later inter-shader optimizations don't
1491 * try to eliminate outputs that don't exist in the final
1492 * shader.
1493 *
1494 * This is only done if non-monolithic shaders are enabled.
1495 */
1496 if ((sel->type == PIPE_SHADER_VERTEX ||
1497 sel->type == PIPE_SHADER_TESS_EVAL) &&
1498 !shader->key.as_ls &&
1499 !shader->key.as_es) {
1500 unsigned i;
1501
1502 for (i = 0; i < sel->info.num_outputs; i++) {
1503 unsigned offset = shader->info.vs_output_param_offset[i];
1504
1505 if (offset <= EXP_PARAM_OFFSET_31)
1506 continue;
1507
1508 unsigned name = sel->info.output_semantic_name[i];
1509 unsigned index = sel->info.output_semantic_index[i];
1510 unsigned id;
1511
1512 switch (name) {
1513 case TGSI_SEMANTIC_GENERIC:
1514 /* don't process indices the function can't handle */
1515 if (index >= 60)
1516 break;
1517 /* fall through */
1518 case TGSI_SEMANTIC_CLIPDIST:
1519 id = si_shader_io_get_unique_index(name, index);
1520 sel->outputs_written &= ~(1ull << id);
1521 break;
1522 case TGSI_SEMANTIC_POSITION: /* ignore these */
1523 case TGSI_SEMANTIC_PSIZE:
1524 case TGSI_SEMANTIC_CLIPVERTEX:
1525 case TGSI_SEMANTIC_EDGEFLAG:
1526 break;
1527 default:
1528 id = si_shader_io_get_unique_index2(name, index);
1529 sel->outputs_written2 &= ~(1u << id);
1530 }
1531 }
1532 }
1533 }
1534
1535 /* Pre-compilation. */
1536 if (sscreen->b.debug_flags & DBG_PRECOMPILE) {
1537 struct si_shader_ctx_state state = {sel};
1538 struct si_shader_key key;
1539
1540 memset(&key, 0, sizeof(key));
1541 si_parse_next_shader_property(&sel->info, &key);
1542
1543 /* Set reasonable defaults, so that the shader key doesn't
1544 * cause any code to be eliminated.
1545 */
1546 switch (sel->type) {
1547 case PIPE_SHADER_TESS_CTRL:
1548 key.part.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
1549 break;
1550 case PIPE_SHADER_FRAGMENT:
1551 key.part.ps.prolog.bc_optimize_for_persp =
1552 sel->info.uses_persp_center &&
1553 sel->info.uses_persp_centroid;
1554 key.part.ps.prolog.bc_optimize_for_linear =
1555 sel->info.uses_linear_center &&
1556 sel->info.uses_linear_centroid;
1557 key.part.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
1558 for (i = 0; i < 8; i++)
1559 if (sel->info.colors_written & (1 << i))
1560 key.part.ps.epilog.spi_shader_col_format |=
1561 V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
1562 break;
1563 }
1564
1565 if (si_shader_select_with_key(sscreen, &state,
1566 &sel->compiler_ctx_state, &key,
1567 thread_index))
1568 fprintf(stderr, "radeonsi: can't create a monolithic shader\n");
1569 }
1570
1571 /* The GS copy shader is always pre-compiled. */
1572 if (sel->type == PIPE_SHADER_GEOMETRY) {
1573 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, tm, sel, debug);
1574 if (!sel->gs_copy_shader) {
1575 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
1576 return;
1577 }
1578
1579 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
1580 }
1581 }
1582
1583 static void *si_create_shader_selector(struct pipe_context *ctx,
1584 const struct pipe_shader_state *state)
1585 {
1586 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
1587 struct si_context *sctx = (struct si_context*)ctx;
1588 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
1589 int i;
1590
1591 if (!sel)
1592 return NULL;
1593
1594 sel->screen = sscreen;
1595 sel->compiler_ctx_state.tm = sctx->tm;
1596 sel->compiler_ctx_state.debug = sctx->b.debug;
1597 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
1598 sel->tokens = tgsi_dup_tokens(state->tokens);
1599 if (!sel->tokens) {
1600 FREE(sel);
1601 return NULL;
1602 }
1603
1604 sel->so = state->stream_output;
1605 tgsi_scan_shader(state->tokens, &sel->info);
1606 sel->type = sel->info.processor;
1607 p_atomic_inc(&sscreen->b.num_shaders_created);
1608
1609 /* Set which opcode uses which (i,j) pair. */
1610 if (sel->info.uses_persp_opcode_interp_centroid)
1611 sel->info.uses_persp_centroid = true;
1612
1613 if (sel->info.uses_linear_opcode_interp_centroid)
1614 sel->info.uses_linear_centroid = true;
1615
1616 if (sel->info.uses_persp_opcode_interp_offset ||
1617 sel->info.uses_persp_opcode_interp_sample)
1618 sel->info.uses_persp_center = true;
1619
1620 if (sel->info.uses_linear_opcode_interp_offset ||
1621 sel->info.uses_linear_opcode_interp_sample)
1622 sel->info.uses_linear_center = true;
1623
1624 switch (sel->type) {
1625 case PIPE_SHADER_GEOMETRY:
1626 sel->gs_output_prim =
1627 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
1628 sel->gs_max_out_vertices =
1629 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
1630 sel->gs_num_invocations =
1631 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
1632 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
1633 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
1634 sel->gs_max_out_vertices;
1635
1636 sel->max_gs_stream = 0;
1637 for (i = 0; i < sel->so.num_outputs; i++)
1638 sel->max_gs_stream = MAX2(sel->max_gs_stream,
1639 sel->so.output[i].stream);
1640
1641 sel->gs_input_verts_per_prim =
1642 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
1643 break;
1644
1645 case PIPE_SHADER_TESS_CTRL:
1646 /* Always reserve space for these. */
1647 sel->patch_outputs_written |=
1648 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0)) |
1649 (1llu << si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0));
1650 /* fall through */
1651 case PIPE_SHADER_VERTEX:
1652 case PIPE_SHADER_TESS_EVAL:
1653 for (i = 0; i < sel->info.num_outputs; i++) {
1654 unsigned name = sel->info.output_semantic_name[i];
1655 unsigned index = sel->info.output_semantic_index[i];
1656
1657 switch (name) {
1658 case TGSI_SEMANTIC_TESSINNER:
1659 case TGSI_SEMANTIC_TESSOUTER:
1660 case TGSI_SEMANTIC_PATCH:
1661 sel->patch_outputs_written |=
1662 1llu << si_shader_io_get_unique_index(name, index);
1663 break;
1664
1665 case TGSI_SEMANTIC_GENERIC:
1666 /* don't process indices the function can't handle */
1667 if (index >= 60)
1668 break;
1669 /* fall through */
1670 case TGSI_SEMANTIC_POSITION:
1671 case TGSI_SEMANTIC_PSIZE:
1672 case TGSI_SEMANTIC_CLIPDIST:
1673 sel->outputs_written |=
1674 1llu << si_shader_io_get_unique_index(name, index);
1675 break;
1676 case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */
1677 case TGSI_SEMANTIC_EDGEFLAG:
1678 break;
1679 default:
1680 sel->outputs_written2 |=
1681 1u << si_shader_io_get_unique_index2(name, index);
1682 }
1683 }
1684 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
1685 break;
1686
1687 case PIPE_SHADER_FRAGMENT:
1688 for (i = 0; i < sel->info.num_inputs; i++) {
1689 unsigned name = sel->info.input_semantic_name[i];
1690 unsigned index = sel->info.input_semantic_index[i];
1691
1692 switch (name) {
1693 case TGSI_SEMANTIC_CLIPDIST:
1694 case TGSI_SEMANTIC_GENERIC:
1695 sel->inputs_read |=
1696 1llu << si_shader_io_get_unique_index(name, index);
1697 break;
1698 case TGSI_SEMANTIC_PCOORD: /* ignore this */
1699 break;
1700 default:
1701 sel->inputs_read2 |=
1702 1u << si_shader_io_get_unique_index2(name, index);
1703 }
1704 }
1705
1706 for (i = 0; i < 8; i++)
1707 if (sel->info.colors_written & (1 << i))
1708 sel->colors_written_4bit |= 0xf << (4 * i);
1709
1710 for (i = 0; i < sel->info.num_inputs; i++) {
1711 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
1712 int index = sel->info.input_semantic_index[i];
1713 sel->color_attr_index[index] = i;
1714 }
1715 }
1716 break;
1717 }
1718
1719 /* DB_SHADER_CONTROL */
1720 sel->db_shader_control =
1721 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
1722 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
1723 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
1724 S_02880C_KILL_ENABLE(sel->info.uses_kill);
1725
1726 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
1727 case TGSI_FS_DEPTH_LAYOUT_GREATER:
1728 sel->db_shader_control |=
1729 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
1730 break;
1731 case TGSI_FS_DEPTH_LAYOUT_LESS:
1732 sel->db_shader_control |=
1733 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
1734 break;
1735 }
1736
1737 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
1738 *
1739 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
1740 * --|-----------|------------|------------|--------------------|-------------------|-------------
1741 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
1742 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
1743 * 2 | false | true | n/a | LateZ | 1 | 0
1744 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
1745 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
1746 *
1747 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
1748 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
1749 *
1750 * Don't use ReZ without profiling !!!
1751 *
1752 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
1753 * shaders.
1754 */
1755 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
1756 /* Cases 3, 4. */
1757 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
1758 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
1759 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
1760 } else if (sel->info.writes_memory) {
1761 /* Case 2. */
1762 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
1763 S_02880C_EXEC_ON_HIER_FAIL(1);
1764 } else {
1765 /* Case 1. */
1766 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
1767 }
1768
1769 (void) mtx_init(&sel->mutex, mtx_plain);
1770 util_queue_fence_init(&sel->ready);
1771
1772 if ((sctx->b.debug.debug_message && !sctx->b.debug.async) ||
1773 sctx->is_debug ||
1774 r600_can_dump_shader(&sscreen->b, sel->info.processor))
1775 si_init_shader_selector_async(sel, -1);
1776 else
1777 util_queue_add_job(&sscreen->shader_compiler_queue, sel,
1778 &sel->ready, si_init_shader_selector_async,
1779 NULL);
1780
1781 return sel;
1782 }
1783
1784 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
1785 {
1786 struct si_context *sctx = (struct si_context *)ctx;
1787 struct si_shader_selector *sel = state;
1788
1789 if (sctx->vs_shader.cso == sel)
1790 return;
1791
1792 sctx->vs_shader.cso = sel;
1793 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
1794 sctx->do_update_shaders = true;
1795 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1796 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1797 }
1798
1799 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
1800 {
1801 struct si_context *sctx = (struct si_context *)ctx;
1802 struct si_shader_selector *sel = state;
1803 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
1804
1805 if (sctx->gs_shader.cso == sel)
1806 return;
1807
1808 sctx->gs_shader.cso = sel;
1809 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
1810 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
1811 sctx->do_update_shaders = true;
1812 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1813 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1814
1815 if (enable_changed)
1816 si_shader_change_notify(sctx);
1817 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1818 }
1819
1820 static void si_update_tcs_tes_uses_prim_id(struct si_context *sctx)
1821 {
1822 sctx->ia_multi_vgt_param_key.u.tcs_tes_uses_prim_id =
1823 (sctx->tes_shader.cso &&
1824 sctx->tes_shader.cso->info.uses_primid) ||
1825 (sctx->tcs_shader.cso &&
1826 sctx->tcs_shader.cso->info.uses_primid);
1827 }
1828
1829 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
1830 {
1831 struct si_context *sctx = (struct si_context *)ctx;
1832 struct si_shader_selector *sel = state;
1833 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
1834
1835 if (sctx->tcs_shader.cso == sel)
1836 return;
1837
1838 sctx->tcs_shader.cso = sel;
1839 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
1840 si_update_tcs_tes_uses_prim_id(sctx);
1841 sctx->do_update_shaders = true;
1842
1843 if (enable_changed)
1844 sctx->last_tcs = NULL; /* invalidate derived tess state */
1845 }
1846
1847 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
1848 {
1849 struct si_context *sctx = (struct si_context *)ctx;
1850 struct si_shader_selector *sel = state;
1851 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
1852
1853 if (sctx->tes_shader.cso == sel)
1854 return;
1855
1856 sctx->tes_shader.cso = sel;
1857 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
1858 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
1859 si_update_tcs_tes_uses_prim_id(sctx);
1860 sctx->do_update_shaders = true;
1861 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1862 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1863
1864 if (enable_changed) {
1865 si_shader_change_notify(sctx);
1866 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
1867 }
1868 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1869 }
1870
1871 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
1872 {
1873 struct si_context *sctx = (struct si_context *)ctx;
1874 struct si_shader_selector *sel = state;
1875
1876 /* skip if supplied shader is one already in use */
1877 if (sctx->ps_shader.cso == sel)
1878 return;
1879
1880 sctx->ps_shader.cso = sel;
1881 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
1882 sctx->do_update_shaders = true;
1883 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
1884 }
1885
1886 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
1887 {
1888 if (shader->is_optimized) {
1889 util_queue_fence_wait(&shader->optimized_ready);
1890 util_queue_fence_destroy(&shader->optimized_ready);
1891 }
1892
1893 if (shader->pm4) {
1894 switch (shader->selector->type) {
1895 case PIPE_SHADER_VERTEX:
1896 if (shader->key.as_ls)
1897 si_pm4_delete_state(sctx, ls, shader->pm4);
1898 else if (shader->key.as_es)
1899 si_pm4_delete_state(sctx, es, shader->pm4);
1900 else
1901 si_pm4_delete_state(sctx, vs, shader->pm4);
1902 break;
1903 case PIPE_SHADER_TESS_CTRL:
1904 si_pm4_delete_state(sctx, hs, shader->pm4);
1905 break;
1906 case PIPE_SHADER_TESS_EVAL:
1907 if (shader->key.as_es)
1908 si_pm4_delete_state(sctx, es, shader->pm4);
1909 else
1910 si_pm4_delete_state(sctx, vs, shader->pm4);
1911 break;
1912 case PIPE_SHADER_GEOMETRY:
1913 if (shader->is_gs_copy_shader)
1914 si_pm4_delete_state(sctx, vs, shader->pm4);
1915 else
1916 si_pm4_delete_state(sctx, gs, shader->pm4);
1917 break;
1918 case PIPE_SHADER_FRAGMENT:
1919 si_pm4_delete_state(sctx, ps, shader->pm4);
1920 break;
1921 }
1922 }
1923
1924 si_shader_destroy(shader);
1925 free(shader);
1926 }
1927
1928 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
1929 {
1930 struct si_context *sctx = (struct si_context *)ctx;
1931 struct si_shader_selector *sel = (struct si_shader_selector *)state;
1932 struct si_shader *p = sel->first_variant, *c;
1933 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
1934 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
1935 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
1936 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
1937 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
1938 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
1939 };
1940
1941 util_queue_fence_wait(&sel->ready);
1942
1943 if (current_shader[sel->type]->cso == sel) {
1944 current_shader[sel->type]->cso = NULL;
1945 current_shader[sel->type]->current = NULL;
1946 }
1947
1948 while (p) {
1949 c = p->next_variant;
1950 si_delete_shader(sctx, p);
1951 p = c;
1952 }
1953
1954 if (sel->main_shader_part)
1955 si_delete_shader(sctx, sel->main_shader_part);
1956 if (sel->main_shader_part_ls)
1957 si_delete_shader(sctx, sel->main_shader_part_ls);
1958 if (sel->main_shader_part_es)
1959 si_delete_shader(sctx, sel->main_shader_part_es);
1960 if (sel->gs_copy_shader)
1961 si_delete_shader(sctx, sel->gs_copy_shader);
1962
1963 util_queue_fence_destroy(&sel->ready);
1964 mtx_destroy(&sel->mutex);
1965 free(sel->tokens);
1966 free(sel);
1967 }
1968
1969 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
1970 struct si_shader *vs, unsigned name,
1971 unsigned index, unsigned interpolate)
1972 {
1973 struct tgsi_shader_info *vsinfo = &vs->selector->info;
1974 unsigned j, offset, ps_input_cntl = 0;
1975
1976 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
1977 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
1978 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1979
1980 if (name == TGSI_SEMANTIC_PCOORD ||
1981 (name == TGSI_SEMANTIC_TEXCOORD &&
1982 sctx->sprite_coord_enable & (1 << index))) {
1983 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
1984 }
1985
1986 for (j = 0; j < vsinfo->num_outputs; j++) {
1987 if (name == vsinfo->output_semantic_name[j] &&
1988 index == vsinfo->output_semantic_index[j]) {
1989 offset = vs->info.vs_output_param_offset[j];
1990
1991 if (offset <= EXP_PARAM_OFFSET_31) {
1992 /* The input is loaded from parameter memory. */
1993 ps_input_cntl |= S_028644_OFFSET(offset);
1994 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
1995 if (offset == EXP_PARAM_UNDEFINED) {
1996 /* This can happen with depth-only rendering. */
1997 offset = 0;
1998 } else {
1999 /* The input is a DEFAULT_VAL constant. */
2000 assert(offset >= EXP_PARAM_DEFAULT_VAL_0000 &&
2001 offset <= EXP_PARAM_DEFAULT_VAL_1111);
2002 offset -= EXP_PARAM_DEFAULT_VAL_0000;
2003 }
2004
2005 ps_input_cntl = S_028644_OFFSET(0x20) |
2006 S_028644_DEFAULT_VAL(offset);
2007 }
2008 break;
2009 }
2010 }
2011
2012 if (name == TGSI_SEMANTIC_PRIMID)
2013 /* PrimID is written after the last output. */
2014 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
2015 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2016 /* No corresponding output found, load defaults into input.
2017 * Don't set any other bits.
2018 * (FLAT_SHADE=1 completely changes behavior) */
2019 ps_input_cntl = S_028644_OFFSET(0x20);
2020 /* D3D 9 behaviour. GL is undefined */
2021 if (name == TGSI_SEMANTIC_COLOR && index == 0)
2022 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
2023 }
2024 return ps_input_cntl;
2025 }
2026
2027 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
2028 {
2029 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2030 struct si_shader *ps = sctx->ps_shader.current;
2031 struct si_shader *vs = si_get_vs_state(sctx);
2032 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
2033 unsigned i, num_interp, num_written = 0, bcol_interp[2];
2034
2035 if (!ps || !ps->selector->info.num_inputs)
2036 return;
2037
2038 num_interp = si_get_ps_num_interp(ps);
2039 assert(num_interp > 0);
2040 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
2041
2042 for (i = 0; i < psinfo->num_inputs; i++) {
2043 unsigned name = psinfo->input_semantic_name[i];
2044 unsigned index = psinfo->input_semantic_index[i];
2045 unsigned interpolate = psinfo->input_interpolate[i];
2046
2047 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
2048 interpolate));
2049 num_written++;
2050
2051 if (name == TGSI_SEMANTIC_COLOR) {
2052 assert(index < ARRAY_SIZE(bcol_interp));
2053 bcol_interp[index] = interpolate;
2054 }
2055 }
2056
2057 if (ps->key.part.ps.prolog.color_two_side) {
2058 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
2059
2060 for (i = 0; i < 2; i++) {
2061 if (!(psinfo->colors_read & (0xf << (i * 4))))
2062 continue;
2063
2064 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
2065 i, bcol_interp[i]));
2066 num_written++;
2067 }
2068 }
2069 assert(num_interp == num_written);
2070 }
2071
2072 /**
2073 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2074 */
2075 static void si_init_config_add_vgt_flush(struct si_context *sctx)
2076 {
2077 if (sctx->init_config_has_vgt_flush)
2078 return;
2079
2080 /* Done by Vulkan before VGT_FLUSH. */
2081 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2082 si_pm4_cmd_add(sctx->init_config,
2083 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2084 si_pm4_cmd_end(sctx->init_config, false);
2085
2086 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2087 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2088 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2089 si_pm4_cmd_end(sctx->init_config, false);
2090 sctx->init_config_has_vgt_flush = true;
2091 }
2092
2093 /* Initialize state related to ESGS / GSVS ring buffers */
2094 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2095 {
2096 struct si_shader_selector *es =
2097 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2098 struct si_shader_selector *gs = sctx->gs_shader.cso;
2099 struct si_pm4_state *pm4;
2100
2101 /* Chip constants. */
2102 unsigned num_se = sctx->screen->b.info.max_se;
2103 unsigned wave_size = 64;
2104 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2105 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
2106 unsigned alignment = 256 * num_se;
2107 /* The maximum size is 63.999 MB per SE. */
2108 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2109
2110 /* Calculate the minimum size. */
2111 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
2112 wave_size, alignment);
2113
2114 /* These are recommended sizes, not minimum sizes. */
2115 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2116 es->esgs_itemsize * gs->gs_input_verts_per_prim;
2117 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2118 gs->max_gsvs_emit_size;
2119
2120 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2121 esgs_ring_size = align(esgs_ring_size, alignment);
2122 gsvs_ring_size = align(gsvs_ring_size, alignment);
2123
2124 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2125 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2126
2127 /* Some rings don't have to be allocated if shaders don't use them.
2128 * (e.g. no varyings between ES and GS or GS and VS)
2129 */
2130 bool update_esgs = esgs_ring_size &&
2131 (!sctx->esgs_ring ||
2132 sctx->esgs_ring->width0 < esgs_ring_size);
2133 bool update_gsvs = gsvs_ring_size &&
2134 (!sctx->gsvs_ring ||
2135 sctx->gsvs_ring->width0 < gsvs_ring_size);
2136
2137 if (!update_esgs && !update_gsvs)
2138 return true;
2139
2140 if (update_esgs) {
2141 pipe_resource_reference(&sctx->esgs_ring, NULL);
2142 sctx->esgs_ring =
2143 r600_aligned_buffer_create(sctx->b.b.screen,
2144 R600_RESOURCE_FLAG_UNMAPPABLE,
2145 PIPE_USAGE_DEFAULT,
2146 esgs_ring_size, alignment);
2147 if (!sctx->esgs_ring)
2148 return false;
2149 }
2150
2151 if (update_gsvs) {
2152 pipe_resource_reference(&sctx->gsvs_ring, NULL);
2153 sctx->gsvs_ring =
2154 r600_aligned_buffer_create(sctx->b.b.screen,
2155 R600_RESOURCE_FLAG_UNMAPPABLE,
2156 PIPE_USAGE_DEFAULT,
2157 gsvs_ring_size, alignment);
2158 if (!sctx->gsvs_ring)
2159 return false;
2160 }
2161
2162 /* Create the "init_config_gs_rings" state. */
2163 pm4 = CALLOC_STRUCT(si_pm4_state);
2164 if (!pm4)
2165 return false;
2166
2167 if (sctx->b.chip_class >= CIK) {
2168 if (sctx->esgs_ring)
2169 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2170 sctx->esgs_ring->width0 / 256);
2171 if (sctx->gsvs_ring)
2172 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2173 sctx->gsvs_ring->width0 / 256);
2174 } else {
2175 if (sctx->esgs_ring)
2176 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2177 sctx->esgs_ring->width0 / 256);
2178 if (sctx->gsvs_ring)
2179 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2180 sctx->gsvs_ring->width0 / 256);
2181 }
2182
2183 /* Set the state. */
2184 if (sctx->init_config_gs_rings)
2185 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
2186 sctx->init_config_gs_rings = pm4;
2187
2188 if (!sctx->init_config_has_vgt_flush) {
2189 si_init_config_add_vgt_flush(sctx);
2190 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2191 }
2192
2193 /* Flush the context to re-emit both init_config states. */
2194 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2195 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2196
2197 /* Set ring bindings. */
2198 if (sctx->esgs_ring) {
2199 si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
2200 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2201 true, true, 4, 64, 0);
2202 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
2203 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2204 false, false, 0, 0, 0);
2205 }
2206 if (sctx->gsvs_ring) {
2207 si_set_ring_buffer(&sctx->b.b, SI_RING_GSVS,
2208 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
2209 false, false, 0, 0, 0);
2210 }
2211
2212 return true;
2213 }
2214
2215 /**
2216 * @returns 1 if \p sel has been updated to use a new scratch buffer
2217 * 0 if not
2218 * < 0 if there was a failure
2219 */
2220 static int si_update_scratch_buffer(struct si_context *sctx,
2221 struct si_shader *shader)
2222 {
2223 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
2224 int r;
2225
2226 if (!shader)
2227 return 0;
2228
2229 /* This shader doesn't need a scratch buffer */
2230 if (shader->config.scratch_bytes_per_wave == 0)
2231 return 0;
2232
2233 /* This shader is already configured to use the current
2234 * scratch buffer. */
2235 if (shader->scratch_bo == sctx->scratch_buffer)
2236 return 0;
2237
2238 assert(sctx->scratch_buffer);
2239
2240 si_shader_apply_scratch_relocs(sctx, shader, &shader->config, scratch_va);
2241
2242 /* Replace the shader bo with a new bo that has the relocs applied. */
2243 r = si_shader_binary_upload(sctx->screen, shader);
2244 if (r)
2245 return r;
2246
2247 /* Update the shader state to use the new shader bo. */
2248 si_shader_init_pm4_state(sctx->screen, shader);
2249
2250 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
2251
2252 return 1;
2253 }
2254
2255 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
2256 {
2257 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
2258 }
2259
2260 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
2261 {
2262 return shader ? shader->config.scratch_bytes_per_wave : 0;
2263 }
2264
2265 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
2266 {
2267 unsigned bytes = 0;
2268
2269 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
2270 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
2271 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
2272 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tcs_shader.current));
2273 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
2274 return bytes;
2275 }
2276
2277 static bool si_update_spi_tmpring_size(struct si_context *sctx)
2278 {
2279 unsigned current_scratch_buffer_size =
2280 si_get_current_scratch_buffer_size(sctx);
2281 unsigned scratch_bytes_per_wave =
2282 si_get_max_scratch_bytes_per_wave(sctx);
2283 unsigned scratch_needed_size = scratch_bytes_per_wave *
2284 sctx->scratch_waves;
2285 unsigned spi_tmpring_size;
2286 int r;
2287
2288 if (scratch_needed_size > 0) {
2289 if (scratch_needed_size > current_scratch_buffer_size) {
2290 /* Create a bigger scratch buffer */
2291 r600_resource_reference(&sctx->scratch_buffer, NULL);
2292
2293 sctx->scratch_buffer = (struct r600_resource*)
2294 r600_aligned_buffer_create(&sctx->screen->b.b,
2295 R600_RESOURCE_FLAG_UNMAPPABLE,
2296 PIPE_USAGE_DEFAULT,
2297 scratch_needed_size, 256);
2298 if (!sctx->scratch_buffer)
2299 return false;
2300
2301 si_mark_atom_dirty(sctx, &sctx->scratch_state);
2302 r600_context_add_resource_size(&sctx->b.b,
2303 &sctx->scratch_buffer->b.b);
2304 }
2305
2306 /* Update the shaders, so they are using the latest scratch. The
2307 * scratch buffer may have been changed since these shaders were
2308 * last used, so we still need to try to update them, even if
2309 * they require scratch buffers smaller than the current size.
2310 */
2311 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
2312 if (r < 0)
2313 return false;
2314 if (r == 1)
2315 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2316
2317 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
2318 if (r < 0)
2319 return false;
2320 if (r == 1)
2321 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2322
2323 r = si_update_scratch_buffer(sctx, sctx->tcs_shader.current);
2324 if (r < 0)
2325 return false;
2326 if (r == 1)
2327 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
2328
2329 /* VS can be bound as LS, ES, or VS. */
2330 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
2331 if (r < 0)
2332 return false;
2333 if (r == 1) {
2334 if (sctx->tes_shader.current)
2335 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2336 else if (sctx->gs_shader.current)
2337 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2338 else
2339 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2340 }
2341
2342 /* TES can be bound as ES or VS. */
2343 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
2344 if (r < 0)
2345 return false;
2346 if (r == 1) {
2347 if (sctx->gs_shader.current)
2348 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2349 else
2350 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2351 }
2352 }
2353
2354 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
2355 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
2356 "scratch size should already be aligned correctly.");
2357
2358 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
2359 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
2360 if (spi_tmpring_size != sctx->spi_tmpring_size) {
2361 sctx->spi_tmpring_size = spi_tmpring_size;
2362 si_mark_atom_dirty(sctx, &sctx->scratch_state);
2363 }
2364 return true;
2365 }
2366
2367 static void si_init_tess_factor_ring(struct si_context *sctx)
2368 {
2369 bool double_offchip_buffers = sctx->b.chip_class >= CIK &&
2370 sctx->b.family != CHIP_CARRIZO &&
2371 sctx->b.family != CHIP_STONEY;
2372 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2373 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
2374 sctx->screen->b.info.max_se;
2375 unsigned offchip_granularity;
2376
2377 switch (sctx->screen->tess_offchip_block_dw_size) {
2378 default:
2379 assert(0);
2380 /* fall through */
2381 case 8192:
2382 offchip_granularity = V_03093C_X_8K_DWORDS;
2383 break;
2384 case 4096:
2385 offchip_granularity = V_03093C_X_4K_DWORDS;
2386 break;
2387 }
2388
2389 switch (sctx->b.chip_class) {
2390 case SI:
2391 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2392 break;
2393 case CIK:
2394 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2395 break;
2396 case VI:
2397 default:
2398 max_offchip_buffers = MIN2(max_offchip_buffers, 512);
2399 break;
2400 }
2401
2402 assert(!sctx->tf_ring);
2403 sctx->tf_ring = r600_aligned_buffer_create(sctx->b.b.screen,
2404 R600_RESOURCE_FLAG_UNMAPPABLE,
2405 PIPE_USAGE_DEFAULT,
2406 32768 * sctx->screen->b.info.max_se,
2407 256);
2408 if (!sctx->tf_ring)
2409 return;
2410
2411 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
2412
2413 sctx->tess_offchip_ring =
2414 r600_aligned_buffer_create(sctx->b.b.screen,
2415 R600_RESOURCE_FLAG_UNMAPPABLE,
2416 PIPE_USAGE_DEFAULT,
2417 max_offchip_buffers *
2418 sctx->screen->tess_offchip_block_dw_size * 4,
2419 256);
2420 if (!sctx->tess_offchip_ring)
2421 return;
2422
2423 si_init_config_add_vgt_flush(sctx);
2424
2425 /* Append these registers to the init config state. */
2426 if (sctx->b.chip_class >= CIK) {
2427 if (sctx->b.chip_class >= VI)
2428 --max_offchip_buffers;
2429
2430 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
2431 S_030938_SIZE(sctx->tf_ring->width0 / 4));
2432 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
2433 r600_resource(sctx->tf_ring)->gpu_address >> 8);
2434 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
2435 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2436 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity));
2437 } else {
2438 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
2439 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
2440 S_008988_SIZE(sctx->tf_ring->width0 / 4));
2441 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
2442 r600_resource(sctx->tf_ring)->gpu_address >> 8);
2443 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2444 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers));
2445 }
2446
2447 /* Flush the context to re-emit the init_config state.
2448 * This is done only once in a lifetime of a context.
2449 */
2450 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2451 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2452 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2453
2454 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_FACTOR, sctx->tf_ring,
2455 0, sctx->tf_ring->width0, false, false, 0, 0, 0);
2456
2457 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_OFFCHIP,
2458 sctx->tess_offchip_ring, 0,
2459 sctx->tess_offchip_ring->width0, false, false, 0, 0, 0);
2460 }
2461
2462 /**
2463 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
2464 * VS passes its outputs to TES directly, so the fixed-function shader only
2465 * has to write TESSOUTER and TESSINNER.
2466 */
2467 static void si_generate_fixed_func_tcs(struct si_context *sctx)
2468 {
2469 struct ureg_src outer, inner;
2470 struct ureg_dst tessouter, tessinner;
2471 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
2472
2473 if (!ureg)
2474 return; /* if we get here, we're screwed */
2475
2476 assert(!sctx->fixed_func_tcs_shader.cso);
2477
2478 outer = ureg_DECL_system_value(ureg,
2479 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
2480 inner = ureg_DECL_system_value(ureg,
2481 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
2482
2483 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
2484 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
2485
2486 ureg_MOV(ureg, tessouter, outer);
2487 ureg_MOV(ureg, tessinner, inner);
2488 ureg_END(ureg);
2489
2490 sctx->fixed_func_tcs_shader.cso =
2491 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
2492 }
2493
2494 static void si_update_vgt_shader_config(struct si_context *sctx)
2495 {
2496 /* Calculate the index of the config.
2497 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
2498 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
2499 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
2500
2501 if (!*pm4) {
2502 uint32_t stages = 0;
2503
2504 *pm4 = CALLOC_STRUCT(si_pm4_state);
2505
2506 if (sctx->tes_shader.cso) {
2507 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
2508 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
2509
2510 if (sctx->gs_shader.cso)
2511 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
2512 S_028B54_GS_EN(1) |
2513 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2514 else
2515 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
2516 } else if (sctx->gs_shader.cso) {
2517 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
2518 S_028B54_GS_EN(1) |
2519 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
2520 }
2521
2522 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
2523 }
2524 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
2525 }
2526
2527 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
2528 {
2529 struct pipe_stream_output_info *so = &shader->so;
2530 uint32_t enabled_stream_buffers_mask = 0;
2531 int i;
2532
2533 for (i = 0; i < so->num_outputs; i++)
2534 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
2535 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
2536 sctx->b.streamout.stride_in_dw = shader->so.stride;
2537 }
2538
2539 bool si_update_shaders(struct si_context *sctx)
2540 {
2541 struct pipe_context *ctx = (struct pipe_context*)sctx;
2542 struct si_compiler_ctx_state compiler_state;
2543 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2544 struct si_shader *old_vs = si_get_vs_state(sctx);
2545 bool old_clip_disable = old_vs ? old_vs->key.opt.hw_vs.clip_disable : false;
2546 int r;
2547
2548 compiler_state.tm = sctx->tm;
2549 compiler_state.debug = sctx->b.debug;
2550 compiler_state.is_debug_context = sctx->is_debug;
2551
2552 /* Update stages before GS. */
2553 if (sctx->tes_shader.cso) {
2554 if (!sctx->tf_ring) {
2555 si_init_tess_factor_ring(sctx);
2556 if (!sctx->tf_ring)
2557 return false;
2558 }
2559
2560 /* VS as LS */
2561 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
2562 if (r)
2563 return false;
2564 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2565
2566 if (sctx->tcs_shader.cso) {
2567 r = si_shader_select(ctx, &sctx->tcs_shader,
2568 &compiler_state);
2569 if (r)
2570 return false;
2571 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
2572 } else {
2573 if (!sctx->fixed_func_tcs_shader.cso) {
2574 si_generate_fixed_func_tcs(sctx);
2575 if (!sctx->fixed_func_tcs_shader.cso)
2576 return false;
2577 }
2578
2579 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
2580 &compiler_state);
2581 if (r)
2582 return false;
2583 si_pm4_bind_state(sctx, hs,
2584 sctx->fixed_func_tcs_shader.current->pm4);
2585 }
2586
2587 r = si_shader_select(ctx, &sctx->tes_shader, &compiler_state);
2588 if (r)
2589 return false;
2590
2591 if (sctx->gs_shader.cso) {
2592 /* TES as ES */
2593 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2594 } else {
2595 /* TES as VS */
2596 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2597 si_update_so(sctx, sctx->tes_shader.cso);
2598 }
2599 } else if (sctx->gs_shader.cso) {
2600 /* VS as ES */
2601 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
2602 if (r)
2603 return false;
2604 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2605
2606 si_pm4_bind_state(sctx, ls, NULL);
2607 si_pm4_bind_state(sctx, hs, NULL);
2608 } else {
2609 /* VS as VS */
2610 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
2611 if (r)
2612 return false;
2613 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2614 si_update_so(sctx, sctx->vs_shader.cso);
2615
2616 si_pm4_bind_state(sctx, ls, NULL);
2617 si_pm4_bind_state(sctx, hs, NULL);
2618 }
2619
2620 /* Update GS. */
2621 if (sctx->gs_shader.cso) {
2622 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
2623 if (r)
2624 return false;
2625 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2626 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
2627 si_update_so(sctx, sctx->gs_shader.cso);
2628
2629 if (!si_update_gs_ring_buffers(sctx))
2630 return false;
2631 } else {
2632 si_pm4_bind_state(sctx, gs, NULL);
2633 si_pm4_bind_state(sctx, es, NULL);
2634 }
2635
2636 si_update_vgt_shader_config(sctx);
2637
2638 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.hw_vs.clip_disable)
2639 si_mark_atom_dirty(sctx, &sctx->clip_regs);
2640
2641 if (sctx->ps_shader.cso) {
2642 unsigned db_shader_control;
2643
2644 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
2645 if (r)
2646 return false;
2647 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2648
2649 db_shader_control =
2650 sctx->ps_shader.cso->db_shader_control |
2651 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
2652
2653 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
2654 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
2655 sctx->flatshade != rs->flatshade) {
2656 sctx->sprite_coord_enable = rs->sprite_coord_enable;
2657 sctx->flatshade = rs->flatshade;
2658 si_mark_atom_dirty(sctx, &sctx->spi_map);
2659 }
2660
2661 if (sctx->b.family == CHIP_STONEY && si_pm4_state_changed(sctx, ps))
2662 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2663
2664 if (sctx->ps_db_shader_control != db_shader_control) {
2665 sctx->ps_db_shader_control = db_shader_control;
2666 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2667 }
2668
2669 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
2670 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
2671 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2672
2673 if (sctx->b.chip_class == SI)
2674 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2675
2676 if (sctx->framebuffer.nr_samples <= 1)
2677 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2678 }
2679 }
2680
2681 if (si_pm4_state_changed(sctx, ls) ||
2682 si_pm4_state_changed(sctx, hs) ||
2683 si_pm4_state_changed(sctx, es) ||
2684 si_pm4_state_changed(sctx, gs) ||
2685 si_pm4_state_changed(sctx, vs) ||
2686 si_pm4_state_changed(sctx, ps)) {
2687 if (!si_update_spi_tmpring_size(sctx))
2688 return false;
2689 }
2690
2691 if (sctx->b.chip_class >= CIK)
2692 si_mark_atom_dirty(sctx, &sctx->prefetch_L2);
2693
2694 sctx->do_update_shaders = false;
2695 return true;
2696 }
2697
2698 static void si_emit_scratch_state(struct si_context *sctx,
2699 struct r600_atom *atom)
2700 {
2701 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2702
2703 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
2704 sctx->spi_tmpring_size);
2705
2706 if (sctx->scratch_buffer) {
2707 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2708 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
2709 RADEON_PRIO_SCRATCH_BUFFER);
2710 }
2711 }
2712
2713 void si_init_shader_functions(struct si_context *sctx)
2714 {
2715 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
2716 si_init_atom(sctx, &sctx->scratch_state, &sctx->atoms.s.scratch_state,
2717 si_emit_scratch_state);
2718
2719 sctx->b.b.create_vs_state = si_create_shader_selector;
2720 sctx->b.b.create_tcs_state = si_create_shader_selector;
2721 sctx->b.b.create_tes_state = si_create_shader_selector;
2722 sctx->b.b.create_gs_state = si_create_shader_selector;
2723 sctx->b.b.create_fs_state = si_create_shader_selector;
2724
2725 sctx->b.b.bind_vs_state = si_bind_vs_shader;
2726 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
2727 sctx->b.b.bind_tes_state = si_bind_tes_shader;
2728 sctx->b.b.bind_gs_state = si_bind_gs_shader;
2729 sctx->b.b.bind_fs_state = si_bind_ps_shader;
2730
2731 sctx->b.b.delete_vs_state = si_delete_shader_selector;
2732 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
2733 sctx->b.b.delete_tes_state = si_delete_shader_selector;
2734 sctx->b.b.delete_gs_state = si_delete_shader_selector;
2735 sctx->b.b.delete_fs_state = si_delete_shader_selector;
2736 }