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[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "sid.h"
26 #include "gfx9d.h"
27 #include "radeon/r600_cs.h"
28
29 #include "tgsi/tgsi_parse.h"
30 #include "tgsi/tgsi_ureg.h"
31 #include "util/hash_table.h"
32 #include "util/crc32.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39
40 /* SHADER_CACHE */
41
42 /**
43 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
44 * integer.
45 */
46 static void *si_get_tgsi_binary(struct si_shader_selector *sel)
47 {
48 unsigned tgsi_size = tgsi_num_tokens(sel->tokens) *
49 sizeof(struct tgsi_token);
50 unsigned size = 4 + tgsi_size + sizeof(sel->so);
51 char *result = (char*)MALLOC(size);
52
53 if (!result)
54 return NULL;
55
56 *((uint32_t*)result) = size;
57 memcpy(result + 4, sel->tokens, tgsi_size);
58 memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so));
59 return result;
60 }
61
62 /** Copy "data" to "ptr" and return the next dword following copied data. */
63 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
64 {
65 /* data may be NULL if size == 0 */
66 if (size)
67 memcpy(ptr, data, size);
68 ptr += DIV_ROUND_UP(size, 4);
69 return ptr;
70 }
71
72 /** Read data from "ptr". Return the next dword following the data. */
73 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
74 {
75 memcpy(data, ptr, size);
76 ptr += DIV_ROUND_UP(size, 4);
77 return ptr;
78 }
79
80 /**
81 * Write the size as uint followed by the data. Return the next dword
82 * following the copied data.
83 */
84 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
85 {
86 *ptr++ = size;
87 return write_data(ptr, data, size);
88 }
89
90 /**
91 * Read the size as uint followed by the data. Return both via parameters.
92 * Return the next dword following the data.
93 */
94 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
95 {
96 *size = *ptr++;
97 assert(*data == NULL);
98 if (!*size)
99 return ptr;
100 *data = malloc(*size);
101 return read_data(ptr, *data, *size);
102 }
103
104 /**
105 * Return the shader binary in a buffer. The first 4 bytes contain its size
106 * as integer.
107 */
108 static void *si_get_shader_binary(struct si_shader *shader)
109 {
110 /* There is always a size of data followed by the data itself. */
111 unsigned relocs_size = shader->binary.reloc_count *
112 sizeof(shader->binary.relocs[0]);
113 unsigned disasm_size = shader->binary.disasm_string ?
114 strlen(shader->binary.disasm_string) + 1 : 0;
115 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
116 strlen(shader->binary.llvm_ir_string) + 1 : 0;
117 unsigned size =
118 4 + /* total size */
119 4 + /* CRC32 of the data below */
120 align(sizeof(shader->config), 4) +
121 align(sizeof(shader->info), 4) +
122 4 + align(shader->binary.code_size, 4) +
123 4 + align(shader->binary.rodata_size, 4) +
124 4 + align(relocs_size, 4) +
125 4 + align(disasm_size, 4) +
126 4 + align(llvm_ir_size, 4);
127 void *buffer = CALLOC(1, size);
128 uint32_t *ptr = (uint32_t*)buffer;
129
130 if (!buffer)
131 return NULL;
132
133 *ptr++ = size;
134 ptr++; /* CRC32 is calculated at the end. */
135
136 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
137 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
138 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
139 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
140 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
141 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
142 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
143 assert((char *)ptr - (char *)buffer == size);
144
145 /* Compute CRC32. */
146 ptr = (uint32_t*)buffer;
147 ptr++;
148 *ptr = util_hash_crc32(ptr + 1, size - 8);
149
150 return buffer;
151 }
152
153 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
154 {
155 uint32_t *ptr = (uint32_t*)binary;
156 uint32_t size = *ptr++;
157 uint32_t crc32 = *ptr++;
158 unsigned chunk_size;
159
160 if (util_hash_crc32(ptr, size - 8) != crc32) {
161 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
162 return false;
163 }
164
165 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
166 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
167 ptr = read_chunk(ptr, (void**)&shader->binary.code,
168 &shader->binary.code_size);
169 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
170 &shader->binary.rodata_size);
171 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
172 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
173 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
174 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
175
176 return true;
177 }
178
179 /**
180 * Insert a shader into the cache. It's assumed the shader is not in the cache.
181 * Use si_shader_cache_load_shader before calling this.
182 *
183 * Returns false on failure, in which case the tgsi_binary should be freed.
184 */
185 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
186 void *tgsi_binary,
187 struct si_shader *shader,
188 bool insert_into_disk_cache)
189 {
190 void *hw_binary;
191 struct hash_entry *entry;
192 uint8_t key[CACHE_KEY_SIZE];
193
194 entry = _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
195 if (entry)
196 return false; /* already added */
197
198 hw_binary = si_get_shader_binary(shader);
199 if (!hw_binary)
200 return false;
201
202 if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
203 hw_binary) == NULL) {
204 FREE(hw_binary);
205 return false;
206 }
207
208 if (sscreen->b.disk_shader_cache && insert_into_disk_cache) {
209 disk_cache_compute_key(sscreen->b.disk_shader_cache, tgsi_binary,
210 *((uint32_t *)tgsi_binary), key);
211 disk_cache_put(sscreen->b.disk_shader_cache, key, hw_binary,
212 *((uint32_t *) hw_binary), NULL);
213 }
214
215 return true;
216 }
217
218 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
219 void *tgsi_binary,
220 struct si_shader *shader)
221 {
222 struct hash_entry *entry =
223 _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
224 if (!entry) {
225 if (sscreen->b.disk_shader_cache) {
226 unsigned char sha1[CACHE_KEY_SIZE];
227 size_t tg_size = *((uint32_t *) tgsi_binary);
228
229 disk_cache_compute_key(sscreen->b.disk_shader_cache,
230 tgsi_binary, tg_size, sha1);
231
232 size_t binary_size;
233 uint8_t *buffer =
234 disk_cache_get(sscreen->b.disk_shader_cache,
235 sha1, &binary_size);
236 if (!buffer)
237 return false;
238
239 if (binary_size < sizeof(uint32_t) ||
240 *((uint32_t*)buffer) != binary_size) {
241 /* Something has gone wrong discard the item
242 * from the cache and rebuild/link from
243 * source.
244 */
245 assert(!"Invalid radeonsi shader disk cache "
246 "item!");
247
248 disk_cache_remove(sscreen->b.disk_shader_cache,
249 sha1);
250 free(buffer);
251
252 return false;
253 }
254
255 if (!si_load_shader_binary(shader, buffer)) {
256 free(buffer);
257 return false;
258 }
259 free(buffer);
260
261 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary,
262 shader, false))
263 FREE(tgsi_binary);
264 } else {
265 return false;
266 }
267 } else {
268 if (si_load_shader_binary(shader, entry->data))
269 FREE(tgsi_binary);
270 else
271 return false;
272 }
273 p_atomic_inc(&sscreen->b.num_shader_cache_hits);
274 return true;
275 }
276
277 static uint32_t si_shader_cache_key_hash(const void *key)
278 {
279 /* The first dword is the key size. */
280 return util_hash_crc32(key, *(uint32_t*)key);
281 }
282
283 static bool si_shader_cache_key_equals(const void *a, const void *b)
284 {
285 uint32_t *keya = (uint32_t*)a;
286 uint32_t *keyb = (uint32_t*)b;
287
288 /* The first dword is the key size. */
289 if (*keya != *keyb)
290 return false;
291
292 return memcmp(keya, keyb, *keya) == 0;
293 }
294
295 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
296 {
297 FREE((void*)entry->key);
298 FREE(entry->data);
299 }
300
301 bool si_init_shader_cache(struct si_screen *sscreen)
302 {
303 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
304 sscreen->shader_cache =
305 _mesa_hash_table_create(NULL,
306 si_shader_cache_key_hash,
307 si_shader_cache_key_equals);
308
309 return sscreen->shader_cache != NULL;
310 }
311
312 void si_destroy_shader_cache(struct si_screen *sscreen)
313 {
314 if (sscreen->shader_cache)
315 _mesa_hash_table_destroy(sscreen->shader_cache,
316 si_destroy_shader_cache_entry);
317 mtx_destroy(&sscreen->shader_cache_mutex);
318 }
319
320 /* SHADER STATES */
321
322 static void si_set_tesseval_regs(struct si_screen *sscreen,
323 struct si_shader_selector *tes,
324 struct si_pm4_state *pm4)
325 {
326 struct tgsi_shader_info *info = &tes->info;
327 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
328 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
329 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
330 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
331 unsigned type, partitioning, topology, distribution_mode;
332
333 switch (tes_prim_mode) {
334 case PIPE_PRIM_LINES:
335 type = V_028B6C_TESS_ISOLINE;
336 break;
337 case PIPE_PRIM_TRIANGLES:
338 type = V_028B6C_TESS_TRIANGLE;
339 break;
340 case PIPE_PRIM_QUADS:
341 type = V_028B6C_TESS_QUAD;
342 break;
343 default:
344 assert(0);
345 return;
346 }
347
348 switch (tes_spacing) {
349 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
350 partitioning = V_028B6C_PART_FRAC_ODD;
351 break;
352 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
353 partitioning = V_028B6C_PART_FRAC_EVEN;
354 break;
355 case PIPE_TESS_SPACING_EQUAL:
356 partitioning = V_028B6C_PART_INTEGER;
357 break;
358 default:
359 assert(0);
360 return;
361 }
362
363 if (tes_point_mode)
364 topology = V_028B6C_OUTPUT_POINT;
365 else if (tes_prim_mode == PIPE_PRIM_LINES)
366 topology = V_028B6C_OUTPUT_LINE;
367 else if (tes_vertex_order_cw)
368 /* for some reason, this must be the other way around */
369 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
370 else
371 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
372
373 if (sscreen->has_distributed_tess) {
374 if (sscreen->b.family == CHIP_FIJI ||
375 sscreen->b.family >= CHIP_POLARIS10)
376 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
377 else
378 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
379 } else
380 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
381
382 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
383 S_028B6C_TYPE(type) |
384 S_028B6C_PARTITIONING(partitioning) |
385 S_028B6C_TOPOLOGY(topology) |
386 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
387 }
388
389 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
390 * whether the "fractional odd" tessellation spacing is used.
391 *
392 * Possible VGT configurations and which state should set the register:
393 *
394 * Reg set in | VGT shader configuration | Value
395 * ------------------------------------------------------
396 * VS as VS | VS | 30
397 * VS as ES | ES -> GS -> VS | 30
398 * TES as VS | LS -> HS -> VS | 14 or 30
399 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
400 *
401 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
402 */
403 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
404 struct si_shader_selector *sel,
405 struct si_shader *shader,
406 struct si_pm4_state *pm4)
407 {
408 unsigned type = sel->type;
409
410 if (sscreen->b.family < CHIP_POLARIS10)
411 return;
412
413 /* VS as VS, or VS as ES: */
414 if ((type == PIPE_SHADER_VERTEX &&
415 (!shader ||
416 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
417 /* TES as VS, or TES as ES: */
418 type == PIPE_SHADER_TESS_EVAL) {
419 unsigned vtx_reuse_depth = 30;
420
421 if (type == PIPE_SHADER_TESS_EVAL &&
422 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
423 PIPE_TESS_SPACING_FRACTIONAL_ODD)
424 vtx_reuse_depth = 14;
425
426 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
427 vtx_reuse_depth);
428 }
429 }
430
431 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
432 {
433 if (shader->pm4)
434 si_pm4_clear_state(shader->pm4);
435 else
436 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
437
438 return shader->pm4;
439 }
440
441 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
442 {
443 struct si_pm4_state *pm4;
444 unsigned vgpr_comp_cnt;
445 uint64_t va;
446
447 assert(sscreen->b.chip_class <= VI);
448
449 pm4 = si_get_shader_pm4_state(shader);
450 if (!pm4)
451 return;
452
453 va = shader->bo->gpu_address;
454 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
455
456 /* We need at least 2 components for LS.
457 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
458 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
459 */
460 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
461
462 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
463 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
464
465 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
466 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
467 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
468 S_00B528_DX10_CLAMP(1) |
469 S_00B528_FLOAT_MODE(shader->config.float_mode);
470 shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_VS_NUM_USER_SGPR) |
471 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
472 }
473
474 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
475 {
476 struct si_pm4_state *pm4;
477 uint64_t va;
478 unsigned ls_vgpr_comp_cnt = 0;
479
480 pm4 = si_get_shader_pm4_state(shader);
481 if (!pm4)
482 return;
483
484 va = shader->bo->gpu_address;
485 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
486
487 if (sscreen->b.chip_class >= GFX9) {
488 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
489 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, va >> 40);
490
491 /* We need at least 2 components for LS.
492 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
493 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
494 */
495 ls_vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
496
497 shader->config.rsrc2 =
498 S_00B42C_USER_SGPR(GFX9_TCS_NUM_USER_SGPR) |
499 S_00B42C_USER_SGPR_MSB(GFX9_TCS_NUM_USER_SGPR >> 5) |
500 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
501 } else {
502 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
503 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
504
505 shader->config.rsrc2 =
506 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
507 S_00B42C_OC_LDS_EN(1) |
508 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
509 }
510
511 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
512 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
513 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
514 S_00B428_DX10_CLAMP(1) |
515 S_00B428_FLOAT_MODE(shader->config.float_mode) |
516 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
517
518 if (sscreen->b.chip_class <= VI) {
519 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
520 shader->config.rsrc2);
521 }
522 }
523
524 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
525 {
526 struct si_pm4_state *pm4;
527 unsigned num_user_sgprs;
528 unsigned vgpr_comp_cnt;
529 uint64_t va;
530 unsigned oc_lds_en;
531
532 assert(sscreen->b.chip_class <= VI);
533
534 pm4 = si_get_shader_pm4_state(shader);
535 if (!pm4)
536 return;
537
538 va = shader->bo->gpu_address;
539 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
540
541 if (shader->selector->type == PIPE_SHADER_VERTEX) {
542 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
543 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
544 num_user_sgprs = SI_VS_NUM_USER_SGPR;
545 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
546 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
547 num_user_sgprs = SI_TES_NUM_USER_SGPR;
548 } else
549 unreachable("invalid shader selector type");
550
551 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
552
553 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
554 shader->selector->esgs_itemsize / 4);
555 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
556 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
557 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
558 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
559 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
560 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
561 S_00B328_DX10_CLAMP(1) |
562 S_00B328_FLOAT_MODE(shader->config.float_mode));
563 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
564 S_00B32C_USER_SGPR(num_user_sgprs) |
565 S_00B32C_OC_LDS_EN(oc_lds_en) |
566 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
567
568 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
569 si_set_tesseval_regs(sscreen, shader->selector, pm4);
570
571 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
572 }
573
574 /**
575 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
576 * geometry shader.
577 */
578 static uint32_t si_vgt_gs_mode(struct si_shader_selector *sel)
579 {
580 enum chip_class chip_class = sel->screen->b.chip_class;
581 unsigned gs_max_vert_out = sel->gs_max_out_vertices;
582 unsigned cut_mode;
583
584 if (gs_max_vert_out <= 128) {
585 cut_mode = V_028A40_GS_CUT_128;
586 } else if (gs_max_vert_out <= 256) {
587 cut_mode = V_028A40_GS_CUT_256;
588 } else if (gs_max_vert_out <= 512) {
589 cut_mode = V_028A40_GS_CUT_512;
590 } else {
591 assert(gs_max_vert_out <= 1024);
592 cut_mode = V_028A40_GS_CUT_1024;
593 }
594
595 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
596 S_028A40_CUT_MODE(cut_mode)|
597 S_028A40_ES_WRITE_OPTIMIZE(chip_class <= VI) |
598 S_028A40_GS_WRITE_OPTIMIZE(1) |
599 S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0);
600 }
601
602 struct gfx9_gs_info {
603 unsigned es_verts_per_subgroup;
604 unsigned gs_prims_per_subgroup;
605 unsigned gs_inst_prims_in_subgroup;
606 unsigned max_prims_per_subgroup;
607 unsigned lds_size;
608 };
609
610 static void gfx9_get_gs_info(struct si_shader_selector *es,
611 struct si_shader_selector *gs,
612 struct gfx9_gs_info *out)
613 {
614 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
615 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
616 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
617 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
618
619 /* All these are in dwords: */
620 /* We can't allow using the whole LDS, because GS waves compete with
621 * other shader stages for LDS space. */
622 const unsigned max_lds_size = 8 * 1024;
623 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
624 unsigned esgs_lds_size;
625
626 /* All these are per subgroup: */
627 const unsigned max_out_prims = 32 * 1024;
628 const unsigned max_es_verts = 255;
629 const unsigned ideal_gs_prims = 64;
630 unsigned max_gs_prims, gs_prims;
631 unsigned min_es_verts, es_verts, worst_case_es_verts;
632
633 assert(gs_num_invocations <= 32); /* GL maximum */
634
635 if (uses_adjacency || gs_num_invocations > 1)
636 max_gs_prims = 127 / gs_num_invocations;
637 else
638 max_gs_prims = 255;
639
640 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
641 * Make sure we don't go over the maximum value.
642 */
643 if (gs->gs_max_out_vertices > 0) {
644 max_gs_prims = MIN2(max_gs_prims,
645 max_out_prims /
646 (gs->gs_max_out_vertices * gs_num_invocations));
647 }
648 assert(max_gs_prims > 0);
649
650 /* If the primitive has adjacency, halve the number of vertices
651 * that will be reused in multiple primitives.
652 */
653 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
654
655 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
656 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
657
658 /* Compute ESGS LDS size based on the worst case number of ES vertices
659 * needed to create the target number of GS prims per subgroup.
660 */
661 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
662
663 /* If total LDS usage is too big, refactor partitions based on ratio
664 * of ESGS item sizes.
665 */
666 if (esgs_lds_size > max_lds_size) {
667 /* Our target GS Prims Per Subgroup was too large. Calculate
668 * the maximum number of GS Prims Per Subgroup that will fit
669 * into LDS, capped by the maximum that the hardware can support.
670 */
671 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
672 max_gs_prims);
673 assert(gs_prims > 0);
674 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
675 max_es_verts);
676
677 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
678 assert(esgs_lds_size <= max_lds_size);
679 }
680
681 /* Now calculate remaining ESGS information. */
682 if (esgs_lds_size)
683 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
684 else
685 es_verts = max_es_verts;
686
687 /* Vertices for adjacency primitives are not always reused, so restore
688 * it for ES_VERTS_PER_SUBGRP.
689 */
690 min_es_verts = gs->gs_input_verts_per_prim;
691
692 /* For normal primitives, the VGT only checks if they are past the ES
693 * verts per subgroup after allocating a full GS primitive and if they
694 * are, kick off a new subgroup. But if those additional ES verts are
695 * unique (e.g. not reused) we need to make sure there is enough LDS
696 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
697 */
698 es_verts -= min_es_verts - 1;
699
700 out->es_verts_per_subgroup = es_verts;
701 out->gs_prims_per_subgroup = gs_prims;
702 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
703 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
704 gs->gs_max_out_vertices;
705 out->lds_size = align(esgs_lds_size, 128) / 128;
706
707 assert(out->max_prims_per_subgroup <= max_out_prims);
708 }
709
710 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
711 {
712 struct si_shader_selector *sel = shader->selector;
713 const ubyte *num_components = sel->info.num_stream_output_components;
714 unsigned gs_num_invocations = sel->gs_num_invocations;
715 struct si_pm4_state *pm4;
716 uint64_t va;
717 unsigned max_stream = sel->max_gs_stream;
718 unsigned offset;
719
720 pm4 = si_get_shader_pm4_state(shader);
721 if (!pm4)
722 return;
723
724 offset = num_components[0] * sel->gs_max_out_vertices;
725 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, offset);
726 if (max_stream >= 1)
727 offset += num_components[1] * sel->gs_max_out_vertices;
728 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, offset);
729 if (max_stream >= 2)
730 offset += num_components[2] * sel->gs_max_out_vertices;
731 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, offset);
732 if (max_stream >= 3)
733 offset += num_components[3] * sel->gs_max_out_vertices;
734 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
735
736 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
737 assert(offset < (1 << 15));
738
739 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, sel->gs_max_out_vertices);
740
741 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, num_components[0]);
742 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? num_components[1] : 0);
743 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? num_components[2] : 0);
744 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? num_components[3] : 0);
745
746 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
747 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
748 S_028B90_ENABLE(gs_num_invocations > 0));
749
750 va = shader->bo->gpu_address;
751 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
752
753 if (sscreen->b.chip_class >= GFX9) {
754 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
755 unsigned es_type = shader->key.part.gs.es->type;
756 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
757 struct gfx9_gs_info gs_info;
758
759 if (es_type == PIPE_SHADER_VERTEX)
760 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
761 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
762 else if (es_type == PIPE_SHADER_TESS_EVAL)
763 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
764 else
765 unreachable("invalid shader selector type");
766
767 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
768 * VGPR[0:4] are always loaded.
769 */
770 if (sel->info.uses_invocationid)
771 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
772 else if (sel->info.uses_primid)
773 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
774 else if (input_prim >= PIPE_PRIM_TRIANGLES)
775 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
776 else
777 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
778
779 gfx9_get_gs_info(shader->key.part.gs.es, sel, &gs_info);
780
781 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
782 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, va >> 40);
783
784 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
785 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
786 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
787 S_00B228_DX10_CLAMP(1) |
788 S_00B228_FLOAT_MODE(shader->config.float_mode) |
789 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
790 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
791 S_00B22C_USER_SGPR(GFX9_GS_NUM_USER_SGPR) |
792 S_00B22C_USER_SGPR_MSB(GFX9_GS_NUM_USER_SGPR >> 5) |
793 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
794 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
795 S_00B22C_LDS_SIZE(gs_info.lds_size) |
796 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
797
798 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
799 S_028A44_ES_VERTS_PER_SUBGRP(gs_info.es_verts_per_subgroup) |
800 S_028A44_GS_PRIMS_PER_SUBGRP(gs_info.gs_prims_per_subgroup) |
801 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_info.gs_inst_prims_in_subgroup));
802 si_pm4_set_reg(pm4, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
803 S_028A94_MAX_PRIMS_PER_SUBGROUP(gs_info.max_prims_per_subgroup));
804 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
805 shader->key.part.gs.es->esgs_itemsize / 4);
806
807 if (es_type == PIPE_SHADER_TESS_EVAL)
808 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
809
810 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
811 NULL, pm4);
812 } else {
813 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
814 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
815
816 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
817 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
818 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
819 S_00B228_DX10_CLAMP(1) |
820 S_00B228_FLOAT_MODE(shader->config.float_mode));
821 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
822 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
823 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
824 }
825 }
826
827 /**
828 * Compute the state for \p shader, which will run as a vertex shader on the
829 * hardware.
830 *
831 * If \p gs is non-NULL, it points to the geometry shader for which this shader
832 * is the copy shader.
833 */
834 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
835 struct si_shader_selector *gs)
836 {
837 const struct tgsi_shader_info *info = &shader->selector->info;
838 struct si_pm4_state *pm4;
839 unsigned num_user_sgprs;
840 unsigned nparams, vgpr_comp_cnt;
841 uint64_t va;
842 unsigned oc_lds_en;
843 unsigned window_space =
844 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
845 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
846
847 pm4 = si_get_shader_pm4_state(shader);
848 if (!pm4)
849 return;
850
851 /* We always write VGT_GS_MODE in the VS state, because every switch
852 * between different shader pipelines involving a different GS or no
853 * GS at all involves a switch of the VS (different GS use different
854 * copy shaders). On the other hand, when the API switches from a GS to
855 * no GS and then back to the same GS used originally, the GS state is
856 * not sent again.
857 */
858 if (!gs) {
859 unsigned mode = V_028A40_GS_OFF;
860
861 /* PrimID needs GS scenario A. */
862 if (enable_prim_id)
863 mode = V_028A40_GS_SCENARIO_A;
864
865 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, S_028A40_MODE(mode));
866 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
867 } else {
868 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
869 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
870 }
871
872 if (sscreen->b.chip_class <= VI) {
873 /* Reuse needs to be set off if we write oViewport. */
874 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF,
875 S_028AB4_REUSE_OFF(info->writes_viewport_index));
876 }
877
878 va = shader->bo->gpu_address;
879 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
880
881 if (gs) {
882 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
883 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
884 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
885 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
886 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
887 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
888 */
889 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
890
891 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
892 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
893 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
894 } else {
895 num_user_sgprs = SI_VS_NUM_USER_SGPR;
896 }
897 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
898 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
899 num_user_sgprs = SI_TES_NUM_USER_SGPR;
900 } else
901 unreachable("invalid shader selector type");
902
903 /* VS is required to export at least one param. */
904 nparams = MAX2(shader->info.nr_param_exports, 1);
905 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
906 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
907
908 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
909 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
910 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
911 V_02870C_SPI_SHADER_4COMP :
912 V_02870C_SPI_SHADER_NONE) |
913 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
914 V_02870C_SPI_SHADER_4COMP :
915 V_02870C_SPI_SHADER_NONE) |
916 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
917 V_02870C_SPI_SHADER_4COMP :
918 V_02870C_SPI_SHADER_NONE));
919
920 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
921
922 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
923 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
924 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
925 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
926 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
927 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
928 S_00B128_DX10_CLAMP(1) |
929 S_00B128_FLOAT_MODE(shader->config.float_mode));
930 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
931 S_00B12C_USER_SGPR(num_user_sgprs) |
932 S_00B12C_OC_LDS_EN(oc_lds_en) |
933 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
934 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
935 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
936 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
937 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
938 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
939 if (window_space)
940 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
941 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
942 else
943 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
944 S_028818_VTX_W0_FMT(1) |
945 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
946 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
947 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
948
949 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
950 si_set_tesseval_regs(sscreen, shader->selector, pm4);
951
952 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
953 }
954
955 static unsigned si_get_ps_num_interp(struct si_shader *ps)
956 {
957 struct tgsi_shader_info *info = &ps->selector->info;
958 unsigned num_colors = !!(info->colors_read & 0x0f) +
959 !!(info->colors_read & 0xf0);
960 unsigned num_interp = ps->selector->info.num_inputs +
961 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
962
963 assert(num_interp <= 32);
964 return MIN2(num_interp, 32);
965 }
966
967 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
968 {
969 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
970 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
971
972 /* If the i-th target format is set, all previous target formats must
973 * be non-zero to avoid hangs.
974 */
975 for (i = 0; i < num_targets; i++)
976 if (!(value & (0xf << (i * 4))))
977 value |= V_028714_SPI_SHADER_32_R << (i * 4);
978
979 return value;
980 }
981
982 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
983 {
984 unsigned i, cb_shader_mask = 0;
985
986 for (i = 0; i < 8; i++) {
987 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
988 case V_028714_SPI_SHADER_ZERO:
989 break;
990 case V_028714_SPI_SHADER_32_R:
991 cb_shader_mask |= 0x1 << (i * 4);
992 break;
993 case V_028714_SPI_SHADER_32_GR:
994 cb_shader_mask |= 0x3 << (i * 4);
995 break;
996 case V_028714_SPI_SHADER_32_AR:
997 cb_shader_mask |= 0x9 << (i * 4);
998 break;
999 case V_028714_SPI_SHADER_FP16_ABGR:
1000 case V_028714_SPI_SHADER_UNORM16_ABGR:
1001 case V_028714_SPI_SHADER_SNORM16_ABGR:
1002 case V_028714_SPI_SHADER_UINT16_ABGR:
1003 case V_028714_SPI_SHADER_SINT16_ABGR:
1004 case V_028714_SPI_SHADER_32_ABGR:
1005 cb_shader_mask |= 0xf << (i * 4);
1006 break;
1007 default:
1008 assert(0);
1009 }
1010 }
1011 return cb_shader_mask;
1012 }
1013
1014 static void si_shader_ps(struct si_shader *shader)
1015 {
1016 struct tgsi_shader_info *info = &shader->selector->info;
1017 struct si_pm4_state *pm4;
1018 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1019 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1020 uint64_t va;
1021 unsigned input_ena = shader->config.spi_ps_input_ena;
1022
1023 /* we need to enable at least one of them, otherwise we hang the GPU */
1024 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1025 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1026 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1027 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1028 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1029 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1030 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1031 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1032 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1033 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1034 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1035 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1036 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1037 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1038
1039 /* Validate interpolation optimization flags (read as implications). */
1040 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1041 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1042 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1043 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1044 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1045 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1046 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1047 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1048 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1049 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1050 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1051 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1052 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1053 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1054 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1055 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1056 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1057 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1058
1059 /* Validate cases when the optimizations are off (read as implications). */
1060 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1061 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1062 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1063 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1064 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1065 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1066
1067 pm4 = si_get_shader_pm4_state(shader);
1068 if (!pm4)
1069 return;
1070
1071 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1072 * Possible vaules:
1073 * 0 -> Position = pixel center
1074 * 1 -> Position = pixel centroid
1075 * 2 -> Position = at sample position
1076 *
1077 * From GLSL 4.5 specification, section 7.1:
1078 * "The variable gl_FragCoord is available as an input variable from
1079 * within fragment shaders and it holds the window relative coordinates
1080 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1081 * value can be for any location within the pixel, or one of the
1082 * fragment samples. The use of centroid does not further restrict
1083 * this value to be inside the current primitive."
1084 *
1085 * Meaning that centroid has no effect and we can return anything within
1086 * the pixel. Thus, return the value at sample position, because that's
1087 * the most accurate one shaders can get.
1088 */
1089 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1090
1091 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1092 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1093 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1094
1095 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1096 cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
1097
1098 /* Ensure that some export memory is always allocated, for two reasons:
1099 *
1100 * 1) Correctness: The hardware ignores the EXEC mask if no export
1101 * memory is allocated, so KILL and alpha test do not work correctly
1102 * without this.
1103 * 2) Performance: Every shader needs at least a NULL export, even when
1104 * it writes no color/depth output. The NULL export instruction
1105 * stalls without this setting.
1106 *
1107 * Don't add this to CB_SHADER_MASK.
1108 */
1109 if (!spi_shader_col_format &&
1110 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1111 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1112
1113 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
1114 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
1115 shader->config.spi_ps_input_addr);
1116
1117 /* Set interpolation controls. */
1118 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1119
1120 /* Set registers. */
1121 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
1122 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
1123
1124 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
1125 si_get_spi_shader_z_format(info->writes_z,
1126 info->writes_stencil,
1127 info->writes_samplemask));
1128
1129 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
1130 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
1131
1132 va = shader->bo->gpu_address;
1133 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1134 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1135 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
1136
1137 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
1138 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1139 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
1140 S_00B028_DX10_CLAMP(1) |
1141 S_00B028_FLOAT_MODE(shader->config.float_mode));
1142 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1143 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1144 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1145 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1146 }
1147
1148 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1149 struct si_shader *shader)
1150 {
1151 switch (shader->selector->type) {
1152 case PIPE_SHADER_VERTEX:
1153 if (shader->key.as_ls)
1154 si_shader_ls(sscreen, shader);
1155 else if (shader->key.as_es)
1156 si_shader_es(sscreen, shader);
1157 else
1158 si_shader_vs(sscreen, shader, NULL);
1159 break;
1160 case PIPE_SHADER_TESS_CTRL:
1161 si_shader_hs(sscreen, shader);
1162 break;
1163 case PIPE_SHADER_TESS_EVAL:
1164 if (shader->key.as_es)
1165 si_shader_es(sscreen, shader);
1166 else
1167 si_shader_vs(sscreen, shader, NULL);
1168 break;
1169 case PIPE_SHADER_GEOMETRY:
1170 si_shader_gs(sscreen, shader);
1171 break;
1172 case PIPE_SHADER_FRAGMENT:
1173 si_shader_ps(shader);
1174 break;
1175 default:
1176 assert(0);
1177 }
1178 }
1179
1180 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1181 {
1182 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1183 if (sctx->queued.named.dsa)
1184 return sctx->queued.named.dsa->alpha_func;
1185
1186 return PIPE_FUNC_ALWAYS;
1187 }
1188
1189 static void si_shader_selector_key_vs(struct si_context *sctx,
1190 struct si_shader_selector *vs,
1191 struct si_shader_key *key,
1192 struct si_vs_prolog_bits *prolog_key)
1193 {
1194 if (!sctx->vertex_elements)
1195 return;
1196
1197 prolog_key->instance_divisor_is_one =
1198 sctx->vertex_elements->instance_divisor_is_one;
1199 prolog_key->instance_divisor_is_fetched =
1200 sctx->vertex_elements->instance_divisor_is_fetched;
1201
1202 /* Prefer a monolithic shader to allow scheduling divisions around
1203 * VBO loads. */
1204 if (prolog_key->instance_divisor_is_fetched)
1205 key->opt.prefer_mono = 1;
1206
1207 unsigned count = MIN2(vs->info.num_inputs,
1208 sctx->vertex_elements->count);
1209 memcpy(key->mono.vs_fix_fetch, sctx->vertex_elements->fix_fetch, count);
1210 }
1211
1212 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1213 struct si_shader_selector *vs,
1214 struct si_shader_key *key)
1215 {
1216 struct si_shader_selector *ps = sctx->ps_shader.cso;
1217
1218 key->opt.clip_disable =
1219 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1220 (vs->info.clipdist_writemask ||
1221 vs->info.writes_clipvertex) &&
1222 !vs->info.culldist_writemask;
1223
1224 /* Find out if PS is disabled. */
1225 bool ps_disabled = true;
1226 if (ps) {
1227 bool ps_modifies_zs = ps->info.uses_kill ||
1228 ps->info.writes_z ||
1229 ps->info.writes_stencil ||
1230 ps->info.writes_samplemask ||
1231 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1232
1233 unsigned ps_colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1234 sctx->queued.named.blend->cb_target_mask;
1235 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1236 ps_colormask &= ps->colors_written_4bit;
1237
1238 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1239 (!ps_colormask &&
1240 !ps_modifies_zs &&
1241 !ps->info.writes_memory);
1242 }
1243
1244 /* Find out which VS outputs aren't used by the PS. */
1245 uint64_t outputs_written = vs->outputs_written;
1246 uint64_t inputs_read = 0;
1247
1248 /* ignore POSITION, PSIZE */
1249 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0) |
1250 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0))));
1251
1252 if (!ps_disabled) {
1253 inputs_read = ps->inputs_read;
1254 }
1255
1256 uint64_t linked = outputs_written & inputs_read;
1257
1258 key->opt.kill_outputs = ~linked & outputs_written;
1259 }
1260
1261 /* Compute the key for the hw shader variant */
1262 static inline void si_shader_selector_key(struct pipe_context *ctx,
1263 struct si_shader_selector *sel,
1264 struct si_shader_key *key)
1265 {
1266 struct si_context *sctx = (struct si_context *)ctx;
1267
1268 memset(key, 0, sizeof(*key));
1269
1270 switch (sel->type) {
1271 case PIPE_SHADER_VERTEX:
1272 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1273
1274 if (sctx->tes_shader.cso)
1275 key->as_ls = 1;
1276 else if (sctx->gs_shader.cso)
1277 key->as_es = 1;
1278 else {
1279 si_shader_selector_key_hw_vs(sctx, sel, key);
1280
1281 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1282 key->mono.u.vs_export_prim_id = 1;
1283 }
1284 break;
1285 case PIPE_SHADER_TESS_CTRL:
1286 if (sctx->b.chip_class >= GFX9) {
1287 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1288 key, &key->part.tcs.ls_prolog);
1289 key->part.tcs.ls = sctx->vs_shader.cso;
1290
1291 /* When the LS VGPR fix is needed, monolithic shaders
1292 * can:
1293 * - avoid initializing EXEC in both the LS prolog
1294 * and the LS main part when !vs_needs_prolog
1295 * - remove the fixup for unused input VGPRs
1296 */
1297 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1298
1299 /* The LS output / HS input layout can be communicated
1300 * directly instead of via user SGPRs for merged LS-HS.
1301 * The LS VGPR fix prefers this too.
1302 */
1303 key->opt.prefer_mono = 1;
1304 }
1305
1306 key->part.tcs.epilog.prim_mode =
1307 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1308 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1309 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1310 key->part.tcs.epilog.tes_reads_tess_factors =
1311 sctx->tes_shader.cso->info.reads_tess_factors;
1312
1313 if (sel == sctx->fixed_func_tcs_shader.cso)
1314 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1315 break;
1316 case PIPE_SHADER_TESS_EVAL:
1317 if (sctx->gs_shader.cso)
1318 key->as_es = 1;
1319 else {
1320 si_shader_selector_key_hw_vs(sctx, sel, key);
1321
1322 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1323 key->mono.u.vs_export_prim_id = 1;
1324 }
1325 break;
1326 case PIPE_SHADER_GEOMETRY:
1327 if (sctx->b.chip_class >= GFX9) {
1328 if (sctx->tes_shader.cso) {
1329 key->part.gs.es = sctx->tes_shader.cso;
1330 } else {
1331 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1332 key, &key->part.gs.vs_prolog);
1333 key->part.gs.es = sctx->vs_shader.cso;
1334 }
1335
1336 /* Merged ES-GS can have unbalanced wave usage.
1337 *
1338 * ES threads are per-vertex, while GS threads are
1339 * per-primitive. So without any amplification, there
1340 * are fewer GS threads than ES threads, which can result
1341 * in empty (no-op) GS waves. With too much amplification,
1342 * there are more GS threads than ES threads, which
1343 * can result in empty (no-op) ES waves.
1344 *
1345 * Non-monolithic shaders are implemented by setting EXEC
1346 * at the beginning of shader parts, and don't jump to
1347 * the end if EXEC is 0.
1348 *
1349 * Monolithic shaders use conditional blocks, so they can
1350 * jump and skip empty waves of ES or GS. So set this to
1351 * always use optimized variants, which are monolithic.
1352 */
1353 key->opt.prefer_mono = 1;
1354 }
1355 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1356 break;
1357 case PIPE_SHADER_FRAGMENT: {
1358 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1359 struct si_state_blend *blend = sctx->queued.named.blend;
1360
1361 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1362 sel->info.colors_written == 0x1)
1363 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1364
1365 if (blend) {
1366 /* Select the shader color format based on whether
1367 * blending or alpha are needed.
1368 */
1369 key->part.ps.epilog.spi_shader_col_format =
1370 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1371 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1372 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1373 sctx->framebuffer.spi_shader_col_format_blend) |
1374 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1375 sctx->framebuffer.spi_shader_col_format_alpha) |
1376 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1377 sctx->framebuffer.spi_shader_col_format);
1378 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1379
1380 /* The output for dual source blending should have
1381 * the same format as the first output.
1382 */
1383 if (blend->dual_src_blend)
1384 key->part.ps.epilog.spi_shader_col_format |=
1385 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1386 } else
1387 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1388
1389 /* If alpha-to-coverage is enabled, we have to export alpha
1390 * even if there is no color buffer.
1391 */
1392 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1393 blend && blend->alpha_to_coverage)
1394 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1395
1396 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
1397 * to the range supported by the type if a channel has less
1398 * than 16 bits and the export format is 16_ABGR.
1399 */
1400 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII) {
1401 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1402 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1403 }
1404
1405 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1406 if (!key->part.ps.epilog.last_cbuf) {
1407 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1408 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1409 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1410 }
1411
1412 if (rs) {
1413 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
1414 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
1415 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
1416 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
1417
1418 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1419 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1420
1421 if (sctx->queued.named.blend) {
1422 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1423 rs->multisample_enable;
1424 }
1425
1426 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1427 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1428 (is_line && rs->line_smooth)) &&
1429 sctx->framebuffer.nr_samples <= 1;
1430 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1431
1432 if (sctx->ps_iter_samples > 1 &&
1433 sel->info.reads_samplemask) {
1434 key->part.ps.prolog.samplemask_log_ps_iter =
1435 util_logbase2(util_next_power_of_two(sctx->ps_iter_samples));
1436 }
1437
1438 if (rs->force_persample_interp &&
1439 rs->multisample_enable &&
1440 sctx->framebuffer.nr_samples > 1 &&
1441 sctx->ps_iter_samples > 1) {
1442 key->part.ps.prolog.force_persp_sample_interp =
1443 sel->info.uses_persp_center ||
1444 sel->info.uses_persp_centroid;
1445
1446 key->part.ps.prolog.force_linear_sample_interp =
1447 sel->info.uses_linear_center ||
1448 sel->info.uses_linear_centroid;
1449 } else if (rs->multisample_enable &&
1450 sctx->framebuffer.nr_samples > 1) {
1451 key->part.ps.prolog.bc_optimize_for_persp =
1452 sel->info.uses_persp_center &&
1453 sel->info.uses_persp_centroid;
1454 key->part.ps.prolog.bc_optimize_for_linear =
1455 sel->info.uses_linear_center &&
1456 sel->info.uses_linear_centroid;
1457 } else {
1458 /* Make sure SPI doesn't compute more than 1 pair
1459 * of (i,j), which is the optimization here. */
1460 key->part.ps.prolog.force_persp_center_interp =
1461 sel->info.uses_persp_center +
1462 sel->info.uses_persp_centroid +
1463 sel->info.uses_persp_sample > 1;
1464
1465 key->part.ps.prolog.force_linear_center_interp =
1466 sel->info.uses_linear_center +
1467 sel->info.uses_linear_centroid +
1468 sel->info.uses_linear_sample > 1;
1469
1470 if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
1471 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1472 }
1473 }
1474
1475 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1476 break;
1477 }
1478 default:
1479 assert(0);
1480 }
1481
1482 if (unlikely(sctx->screen->b.debug_flags & DBG(NO_OPT_VARIANT)))
1483 memset(&key->opt, 0, sizeof(key->opt));
1484 }
1485
1486 static void si_build_shader_variant(struct si_shader *shader,
1487 int thread_index,
1488 bool low_priority)
1489 {
1490 struct si_shader_selector *sel = shader->selector;
1491 struct si_screen *sscreen = sel->screen;
1492 LLVMTargetMachineRef tm;
1493 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
1494 int r;
1495
1496 if (thread_index >= 0) {
1497 if (low_priority) {
1498 assert(thread_index < ARRAY_SIZE(sscreen->tm_low_priority));
1499 tm = sscreen->tm_low_priority[thread_index];
1500 } else {
1501 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1502 tm = sscreen->tm[thread_index];
1503 }
1504 if (!debug->async)
1505 debug = NULL;
1506 } else {
1507 assert(!low_priority);
1508 tm = shader->compiler_ctx_state.tm;
1509 }
1510
1511 r = si_shader_create(sscreen, tm, shader, debug);
1512 if (unlikely(r)) {
1513 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1514 sel->type, r);
1515 shader->compilation_failed = true;
1516 return;
1517 }
1518
1519 if (shader->compiler_ctx_state.is_debug_context) {
1520 FILE *f = open_memstream(&shader->shader_log,
1521 &shader->shader_log_size);
1522 if (f) {
1523 si_shader_dump(sscreen, shader, NULL, sel->type, f, false);
1524 fclose(f);
1525 }
1526 }
1527
1528 si_shader_init_pm4_state(sscreen, shader);
1529 }
1530
1531 static void si_build_shader_variant_low_priority(void *job, int thread_index)
1532 {
1533 struct si_shader *shader = (struct si_shader *)job;
1534
1535 assert(thread_index >= 0);
1536
1537 si_build_shader_variant(shader, thread_index, true);
1538 }
1539
1540 static const struct si_shader_key zeroed;
1541
1542 static bool si_check_missing_main_part(struct si_screen *sscreen,
1543 struct si_shader_selector *sel,
1544 struct si_compiler_ctx_state *compiler_state,
1545 struct si_shader_key *key)
1546 {
1547 struct si_shader **mainp = si_get_main_shader_part(sel, key);
1548
1549 if (!*mainp) {
1550 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
1551
1552 if (!main_part)
1553 return false;
1554
1555 main_part->selector = sel;
1556 main_part->key.as_es = key->as_es;
1557 main_part->key.as_ls = key->as_ls;
1558
1559 if (si_compile_tgsi_shader(sscreen, compiler_state->tm,
1560 main_part, false,
1561 &compiler_state->debug) != 0) {
1562 FREE(main_part);
1563 return false;
1564 }
1565 *mainp = main_part;
1566 }
1567 return true;
1568 }
1569
1570 /* Select the hw shader variant depending on the current state. */
1571 static int si_shader_select_with_key(struct si_screen *sscreen,
1572 struct si_shader_ctx_state *state,
1573 struct si_compiler_ctx_state *compiler_state,
1574 struct si_shader_key *key,
1575 int thread_index)
1576 {
1577 struct si_shader_selector *sel = state->cso;
1578 struct si_shader_selector *previous_stage_sel = NULL;
1579 struct si_shader *current = state->current;
1580 struct si_shader *iter, *shader = NULL;
1581
1582 again:
1583 /* Check if we don't need to change anything.
1584 * This path is also used for most shaders that don't need multiple
1585 * variants, it will cost just a computation of the key and this
1586 * test. */
1587 if (likely(current &&
1588 memcmp(&current->key, key, sizeof(*key)) == 0 &&
1589 (!current->is_optimized ||
1590 util_queue_fence_is_signalled(&current->optimized_ready))))
1591 return current->compilation_failed ? -1 : 0;
1592
1593 /* This must be done before the mutex is locked, because async GS
1594 * compilation calls this function too, and therefore must enter
1595 * the mutex first.
1596 *
1597 * Only wait if we are in a draw call. Don't wait if we are
1598 * in a compiler thread.
1599 */
1600 if (thread_index < 0)
1601 util_queue_fence_wait(&sel->ready);
1602
1603 mtx_lock(&sel->mutex);
1604
1605 /* Find the shader variant. */
1606 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
1607 /* Don't check the "current" shader. We checked it above. */
1608 if (current != iter &&
1609 memcmp(&iter->key, key, sizeof(*key)) == 0) {
1610 /* If it's an optimized shader and its compilation has
1611 * been started but isn't done, use the unoptimized
1612 * shader so as not to cause a stall due to compilation.
1613 */
1614 if (iter->is_optimized &&
1615 !util_queue_fence_is_signalled(&iter->optimized_ready)) {
1616 memset(&key->opt, 0, sizeof(key->opt));
1617 mtx_unlock(&sel->mutex);
1618 goto again;
1619 }
1620
1621 if (iter->compilation_failed) {
1622 mtx_unlock(&sel->mutex);
1623 return -1; /* skip the draw call */
1624 }
1625
1626 state->current = iter;
1627 mtx_unlock(&sel->mutex);
1628 return 0;
1629 }
1630 }
1631
1632 /* Build a new shader. */
1633 shader = CALLOC_STRUCT(si_shader);
1634 if (!shader) {
1635 mtx_unlock(&sel->mutex);
1636 return -ENOMEM;
1637 }
1638 shader->selector = sel;
1639 shader->key = *key;
1640 shader->compiler_ctx_state = *compiler_state;
1641
1642 /* If this is a merged shader, get the first shader's selector. */
1643 if (sscreen->b.chip_class >= GFX9) {
1644 if (sel->type == PIPE_SHADER_TESS_CTRL)
1645 previous_stage_sel = key->part.tcs.ls;
1646 else if (sel->type == PIPE_SHADER_GEOMETRY)
1647 previous_stage_sel = key->part.gs.es;
1648
1649 /* We need to wait for the previous shader. */
1650 if (previous_stage_sel && thread_index < 0)
1651 util_queue_fence_wait(&previous_stage_sel->ready);
1652 }
1653
1654 /* Compile the main shader part if it doesn't exist. This can happen
1655 * if the initial guess was wrong. */
1656 bool is_pure_monolithic =
1657 sscreen->use_monolithic_shaders ||
1658 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
1659
1660 if (!is_pure_monolithic) {
1661 bool ok;
1662
1663 /* Make sure the main shader part is present. This is needed
1664 * for shaders that can be compiled as VS, LS, or ES, and only
1665 * one of them is compiled at creation.
1666 *
1667 * For merged shaders, check that the starting shader's main
1668 * part is present.
1669 */
1670 if (previous_stage_sel) {
1671 struct si_shader_key shader1_key = zeroed;
1672
1673 if (sel->type == PIPE_SHADER_TESS_CTRL)
1674 shader1_key.as_ls = 1;
1675 else if (sel->type == PIPE_SHADER_GEOMETRY)
1676 shader1_key.as_es = 1;
1677 else
1678 assert(0);
1679
1680 mtx_lock(&previous_stage_sel->mutex);
1681 ok = si_check_missing_main_part(sscreen,
1682 previous_stage_sel,
1683 compiler_state, &shader1_key);
1684 mtx_unlock(&previous_stage_sel->mutex);
1685 } else {
1686 ok = si_check_missing_main_part(sscreen, sel,
1687 compiler_state, key);
1688 }
1689 if (!ok) {
1690 FREE(shader);
1691 mtx_unlock(&sel->mutex);
1692 return -ENOMEM; /* skip the draw call */
1693 }
1694 }
1695
1696 /* Keep the reference to the 1st shader of merged shaders, so that
1697 * Gallium can't destroy it before we destroy the 2nd shader.
1698 *
1699 * Set sctx = NULL, because it's unused if we're not releasing
1700 * the shader, and we don't have any sctx here.
1701 */
1702 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
1703 previous_stage_sel);
1704
1705 /* Monolithic-only shaders don't make a distinction between optimized
1706 * and unoptimized. */
1707 shader->is_monolithic =
1708 is_pure_monolithic ||
1709 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1710
1711 shader->is_optimized =
1712 !is_pure_monolithic &&
1713 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
1714 if (shader->is_optimized)
1715 util_queue_fence_init(&shader->optimized_ready);
1716
1717 if (!sel->last_variant) {
1718 sel->first_variant = shader;
1719 sel->last_variant = shader;
1720 } else {
1721 sel->last_variant->next_variant = shader;
1722 sel->last_variant = shader;
1723 }
1724
1725 /* If it's an optimized shader, compile it asynchronously. */
1726 if (shader->is_optimized &&
1727 !is_pure_monolithic &&
1728 thread_index < 0) {
1729 /* Compile it asynchronously. */
1730 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
1731 shader, &shader->optimized_ready,
1732 si_build_shader_variant_low_priority, NULL);
1733
1734 /* Use the default (unoptimized) shader for now. */
1735 memset(&key->opt, 0, sizeof(key->opt));
1736 mtx_unlock(&sel->mutex);
1737 goto again;
1738 }
1739
1740 assert(!shader->is_optimized);
1741 si_build_shader_variant(shader, thread_index, false);
1742
1743 if (!shader->compilation_failed)
1744 state->current = shader;
1745
1746 mtx_unlock(&sel->mutex);
1747 return shader->compilation_failed ? -1 : 0;
1748 }
1749
1750 static int si_shader_select(struct pipe_context *ctx,
1751 struct si_shader_ctx_state *state,
1752 struct si_compiler_ctx_state *compiler_state)
1753 {
1754 struct si_context *sctx = (struct si_context *)ctx;
1755 struct si_shader_key key;
1756
1757 si_shader_selector_key(ctx, state->cso, &key);
1758 return si_shader_select_with_key(sctx->screen, state, compiler_state,
1759 &key, -1);
1760 }
1761
1762 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1763 bool streamout,
1764 struct si_shader_key *key)
1765 {
1766 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1767
1768 switch (info->processor) {
1769 case PIPE_SHADER_VERTEX:
1770 switch (next_shader) {
1771 case PIPE_SHADER_GEOMETRY:
1772 key->as_es = 1;
1773 break;
1774 case PIPE_SHADER_TESS_CTRL:
1775 case PIPE_SHADER_TESS_EVAL:
1776 key->as_ls = 1;
1777 break;
1778 default:
1779 /* If POSITION isn't written, it can only be a HW VS
1780 * if streamout is used. If streamout isn't used,
1781 * assume that it's a HW LS. (the next shader is TCS)
1782 * This heuristic is needed for separate shader objects.
1783 */
1784 if (!info->writes_position && !streamout)
1785 key->as_ls = 1;
1786 }
1787 break;
1788
1789 case PIPE_SHADER_TESS_EVAL:
1790 if (next_shader == PIPE_SHADER_GEOMETRY ||
1791 !info->writes_position)
1792 key->as_es = 1;
1793 break;
1794 }
1795 }
1796
1797 /**
1798 * Compile the main shader part or the monolithic shader as part of
1799 * si_shader_selector initialization. Since it can be done asynchronously,
1800 * there is no way to report compile failures to applications.
1801 */
1802 static void si_init_shader_selector_async(void *job, int thread_index)
1803 {
1804 struct si_shader_selector *sel = (struct si_shader_selector *)job;
1805 struct si_screen *sscreen = sel->screen;
1806 LLVMTargetMachineRef tm;
1807 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
1808 unsigned i;
1809
1810 if (thread_index >= 0) {
1811 assert(thread_index < ARRAY_SIZE(sscreen->tm));
1812 tm = sscreen->tm[thread_index];
1813 if (!debug->async)
1814 debug = NULL;
1815 } else {
1816 tm = sel->compiler_ctx_state.tm;
1817 }
1818
1819 /* Compile the main shader part for use with a prolog and/or epilog.
1820 * If this fails, the driver will try to compile a monolithic shader
1821 * on demand.
1822 */
1823 if (!sscreen->use_monolithic_shaders) {
1824 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1825 void *tgsi_binary = NULL;
1826
1827 if (!shader) {
1828 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
1829 return;
1830 }
1831
1832 shader->selector = sel;
1833 si_parse_next_shader_property(&sel->info,
1834 sel->so.num_outputs != 0,
1835 &shader->key);
1836
1837 if (sel->tokens)
1838 tgsi_binary = si_get_tgsi_binary(sel);
1839
1840 /* Try to load the shader from the shader cache. */
1841 mtx_lock(&sscreen->shader_cache_mutex);
1842
1843 if (tgsi_binary &&
1844 si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
1845 mtx_unlock(&sscreen->shader_cache_mutex);
1846 } else {
1847 mtx_unlock(&sscreen->shader_cache_mutex);
1848
1849 /* Compile the shader if it hasn't been loaded from the cache. */
1850 if (si_compile_tgsi_shader(sscreen, tm, shader, false,
1851 debug) != 0) {
1852 FREE(shader);
1853 FREE(tgsi_binary);
1854 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
1855 return;
1856 }
1857
1858 if (tgsi_binary) {
1859 mtx_lock(&sscreen->shader_cache_mutex);
1860 if (!si_shader_cache_insert_shader(sscreen, tgsi_binary, shader, true))
1861 FREE(tgsi_binary);
1862 mtx_unlock(&sscreen->shader_cache_mutex);
1863 }
1864 }
1865
1866 *si_get_main_shader_part(sel, &shader->key) = shader;
1867
1868 /* Unset "outputs_written" flags for outputs converted to
1869 * DEFAULT_VAL, so that later inter-shader optimizations don't
1870 * try to eliminate outputs that don't exist in the final
1871 * shader.
1872 *
1873 * This is only done if non-monolithic shaders are enabled.
1874 */
1875 if ((sel->type == PIPE_SHADER_VERTEX ||
1876 sel->type == PIPE_SHADER_TESS_EVAL) &&
1877 !shader->key.as_ls &&
1878 !shader->key.as_es) {
1879 unsigned i;
1880
1881 for (i = 0; i < sel->info.num_outputs; i++) {
1882 unsigned offset = shader->info.vs_output_param_offset[i];
1883
1884 if (offset <= AC_EXP_PARAM_OFFSET_31)
1885 continue;
1886
1887 unsigned name = sel->info.output_semantic_name[i];
1888 unsigned index = sel->info.output_semantic_index[i];
1889 unsigned id;
1890
1891 switch (name) {
1892 case TGSI_SEMANTIC_GENERIC:
1893 /* don't process indices the function can't handle */
1894 if (index >= SI_MAX_IO_GENERIC)
1895 break;
1896 /* fall through */
1897 default:
1898 id = si_shader_io_get_unique_index(name, index);
1899 sel->outputs_written &= ~(1ull << id);
1900 break;
1901 case TGSI_SEMANTIC_POSITION: /* ignore these */
1902 case TGSI_SEMANTIC_PSIZE:
1903 case TGSI_SEMANTIC_CLIPVERTEX:
1904 case TGSI_SEMANTIC_EDGEFLAG:
1905 break;
1906 }
1907 }
1908 }
1909 }
1910
1911 /* Pre-compilation. */
1912 if (sscreen->b.debug_flags & DBG(PRECOMPILE) &&
1913 /* GFX9 needs LS or ES for compilation, which we don't have here. */
1914 (sscreen->b.chip_class <= VI ||
1915 (sel->type != PIPE_SHADER_TESS_CTRL &&
1916 sel->type != PIPE_SHADER_GEOMETRY))) {
1917 struct si_shader_ctx_state state = {sel};
1918 struct si_shader_key key;
1919
1920 memset(&key, 0, sizeof(key));
1921 si_parse_next_shader_property(&sel->info,
1922 sel->so.num_outputs != 0,
1923 &key);
1924
1925 /* GFX9 doesn't have LS and ES. */
1926 if (sscreen->b.chip_class >= GFX9) {
1927 key.as_ls = 0;
1928 key.as_es = 0;
1929 }
1930
1931 /* Set reasonable defaults, so that the shader key doesn't
1932 * cause any code to be eliminated.
1933 */
1934 switch (sel->type) {
1935 case PIPE_SHADER_TESS_CTRL:
1936 key.part.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
1937 break;
1938 case PIPE_SHADER_FRAGMENT:
1939 key.part.ps.prolog.bc_optimize_for_persp =
1940 sel->info.uses_persp_center &&
1941 sel->info.uses_persp_centroid;
1942 key.part.ps.prolog.bc_optimize_for_linear =
1943 sel->info.uses_linear_center &&
1944 sel->info.uses_linear_centroid;
1945 key.part.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
1946 for (i = 0; i < 8; i++)
1947 if (sel->info.colors_written & (1 << i))
1948 key.part.ps.epilog.spi_shader_col_format |=
1949 V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
1950 break;
1951 }
1952
1953 if (si_shader_select_with_key(sscreen, &state,
1954 &sel->compiler_ctx_state, &key,
1955 thread_index))
1956 fprintf(stderr, "radeonsi: can't create a monolithic shader\n");
1957 }
1958
1959 /* The GS copy shader is always pre-compiled. */
1960 if (sel->type == PIPE_SHADER_GEOMETRY) {
1961 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, tm, sel, debug);
1962 if (!sel->gs_copy_shader) {
1963 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
1964 return;
1965 }
1966
1967 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
1968 }
1969 }
1970
1971 /* Return descriptor slot usage masks from the given shader info. */
1972 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
1973 uint32_t *const_and_shader_buffers,
1974 uint64_t *samplers_and_images)
1975 {
1976 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
1977
1978 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
1979 num_constbufs = util_last_bit(info->const_buffers_declared);
1980 /* two 8-byte images share one 16-byte slot */
1981 num_images = align(util_last_bit(info->images_declared), 2);
1982 num_samplers = util_last_bit(info->samplers_declared);
1983
1984 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
1985 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
1986 *const_and_shader_buffers =
1987 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
1988
1989 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
1990 start = si_get_image_slot(num_images - 1) / 2;
1991 *samplers_and_images =
1992 u_bit_consecutive64(start, num_images / 2 + num_samplers);
1993 }
1994
1995 static void *si_create_shader_selector(struct pipe_context *ctx,
1996 const struct pipe_shader_state *state)
1997 {
1998 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
1999 struct si_context *sctx = (struct si_context*)ctx;
2000 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2001 int i;
2002
2003 if (!sel)
2004 return NULL;
2005
2006 pipe_reference_init(&sel->reference, 1);
2007 sel->screen = sscreen;
2008 sel->compiler_ctx_state.tm = sctx->tm;
2009 sel->compiler_ctx_state.debug = sctx->b.debug;
2010 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2011
2012 sel->so = state->stream_output;
2013
2014 if (state->type == PIPE_SHADER_IR_TGSI) {
2015 sel->tokens = tgsi_dup_tokens(state->tokens);
2016 if (!sel->tokens) {
2017 FREE(sel);
2018 return NULL;
2019 }
2020
2021 tgsi_scan_shader(state->tokens, &sel->info);
2022 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2023 } else {
2024 assert(state->type == PIPE_SHADER_IR_NIR);
2025
2026 sel->nir = state->ir.nir;
2027
2028 si_nir_scan_shader(sel->nir, &sel->info);
2029
2030 si_lower_nir(sel);
2031 }
2032
2033 sel->type = sel->info.processor;
2034 p_atomic_inc(&sscreen->b.num_shaders_created);
2035 si_get_active_slot_masks(&sel->info,
2036 &sel->active_const_and_shader_buffers,
2037 &sel->active_samplers_and_images);
2038
2039 /* Record which streamout buffers are enabled. */
2040 for (i = 0; i < sel->so.num_outputs; i++) {
2041 sel->enabled_streamout_buffer_mask |=
2042 (1 << sel->so.output[i].output_buffer) <<
2043 (sel->so.output[i].stream * 4);
2044 }
2045
2046 /* The prolog is a no-op if there are no inputs. */
2047 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2048 sel->info.num_inputs &&
2049 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2050
2051 sel->force_correct_derivs_after_kill =
2052 sel->type == PIPE_SHADER_FRAGMENT &&
2053 sel->info.uses_derivatives &&
2054 sel->info.uses_kill &&
2055 sctx->screen->b.debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2056
2057 /* Set which opcode uses which (i,j) pair. */
2058 if (sel->info.uses_persp_opcode_interp_centroid)
2059 sel->info.uses_persp_centroid = true;
2060
2061 if (sel->info.uses_linear_opcode_interp_centroid)
2062 sel->info.uses_linear_centroid = true;
2063
2064 if (sel->info.uses_persp_opcode_interp_offset ||
2065 sel->info.uses_persp_opcode_interp_sample)
2066 sel->info.uses_persp_center = true;
2067
2068 if (sel->info.uses_linear_opcode_interp_offset ||
2069 sel->info.uses_linear_opcode_interp_sample)
2070 sel->info.uses_linear_center = true;
2071
2072 switch (sel->type) {
2073 case PIPE_SHADER_GEOMETRY:
2074 sel->gs_output_prim =
2075 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2076 sel->gs_max_out_vertices =
2077 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2078 sel->gs_num_invocations =
2079 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2080 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2081 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2082 sel->gs_max_out_vertices;
2083
2084 sel->max_gs_stream = 0;
2085 for (i = 0; i < sel->so.num_outputs; i++)
2086 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2087 sel->so.output[i].stream);
2088
2089 sel->gs_input_verts_per_prim =
2090 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2091 break;
2092
2093 case PIPE_SHADER_TESS_CTRL:
2094 /* Always reserve space for these. */
2095 sel->patch_outputs_written |=
2096 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2097 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2098 /* fall through */
2099 case PIPE_SHADER_VERTEX:
2100 case PIPE_SHADER_TESS_EVAL:
2101 for (i = 0; i < sel->info.num_outputs; i++) {
2102 unsigned name = sel->info.output_semantic_name[i];
2103 unsigned index = sel->info.output_semantic_index[i];
2104
2105 switch (name) {
2106 case TGSI_SEMANTIC_TESSINNER:
2107 case TGSI_SEMANTIC_TESSOUTER:
2108 case TGSI_SEMANTIC_PATCH:
2109 sel->patch_outputs_written |=
2110 1ull << si_shader_io_get_unique_index_patch(name, index);
2111 break;
2112
2113 case TGSI_SEMANTIC_GENERIC:
2114 /* don't process indices the function can't handle */
2115 if (index >= SI_MAX_IO_GENERIC)
2116 break;
2117 /* fall through */
2118 default:
2119 sel->outputs_written |=
2120 1ull << si_shader_io_get_unique_index(name, index);
2121 break;
2122 case TGSI_SEMANTIC_CLIPVERTEX: /* ignore these */
2123 case TGSI_SEMANTIC_EDGEFLAG:
2124 break;
2125 }
2126 }
2127 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2128
2129 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2130 * conflicts, i.e. each vertex will start at a different bank.
2131 */
2132 if (sctx->b.chip_class >= GFX9)
2133 sel->esgs_itemsize += 4;
2134 break;
2135
2136 case PIPE_SHADER_FRAGMENT:
2137 for (i = 0; i < sel->info.num_inputs; i++) {
2138 unsigned name = sel->info.input_semantic_name[i];
2139 unsigned index = sel->info.input_semantic_index[i];
2140
2141 switch (name) {
2142 case TGSI_SEMANTIC_GENERIC:
2143 /* don't process indices the function can't handle */
2144 if (index >= SI_MAX_IO_GENERIC)
2145 break;
2146 /* fall through */
2147 default:
2148 sel->inputs_read |=
2149 1ull << si_shader_io_get_unique_index(name, index);
2150 break;
2151 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2152 break;
2153 }
2154 }
2155
2156 for (i = 0; i < 8; i++)
2157 if (sel->info.colors_written & (1 << i))
2158 sel->colors_written_4bit |= 0xf << (4 * i);
2159
2160 for (i = 0; i < sel->info.num_inputs; i++) {
2161 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2162 int index = sel->info.input_semantic_index[i];
2163 sel->color_attr_index[index] = i;
2164 }
2165 }
2166 break;
2167 }
2168
2169 /* PA_CL_VS_OUT_CNTL */
2170 bool misc_vec_ena =
2171 sel->info.writes_psize || sel->info.writes_edgeflag ||
2172 sel->info.writes_layer || sel->info.writes_viewport_index;
2173 sel->pa_cl_vs_out_cntl =
2174 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2175 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2176 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2177 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2178 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2179 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2180 sel->clipdist_mask = sel->info.writes_clipvertex ?
2181 SIX_BITS : sel->info.clipdist_writemask;
2182 sel->culldist_mask = sel->info.culldist_writemask <<
2183 sel->info.num_written_clipdistance;
2184
2185 /* DB_SHADER_CONTROL */
2186 sel->db_shader_control =
2187 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2188 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2189 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2190 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2191
2192 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2193 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2194 sel->db_shader_control |=
2195 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2196 break;
2197 case TGSI_FS_DEPTH_LAYOUT_LESS:
2198 sel->db_shader_control |=
2199 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2200 break;
2201 }
2202
2203 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2204 *
2205 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2206 * --|-----------|------------|------------|--------------------|-------------------|-------------
2207 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2208 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2209 * 2 | false | true | n/a | LateZ | 1 | 0
2210 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2211 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2212 *
2213 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2214 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2215 *
2216 * Don't use ReZ without profiling !!!
2217 *
2218 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2219 * shaders.
2220 */
2221 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2222 /* Cases 3, 4. */
2223 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2224 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2225 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2226 } else if (sel->info.writes_memory) {
2227 /* Case 2. */
2228 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2229 S_02880C_EXEC_ON_HIER_FAIL(1);
2230 } else {
2231 /* Case 1. */
2232 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2233 }
2234
2235 (void) mtx_init(&sel->mutex, mtx_plain);
2236 util_queue_fence_init(&sel->ready);
2237
2238 if ((sctx->b.debug.debug_message && !sctx->b.debug.async) ||
2239 sctx->is_debug ||
2240 si_can_dump_shader(&sscreen->b, sel->info.processor))
2241 si_init_shader_selector_async(sel, -1);
2242 else
2243 util_queue_add_job(&sscreen->shader_compiler_queue, sel,
2244 &sel->ready, si_init_shader_selector_async,
2245 NULL);
2246
2247 return sel;
2248 }
2249
2250 static void si_update_streamout_state(struct si_context *sctx)
2251 {
2252 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2253
2254 if (!shader_with_so)
2255 return;
2256
2257 sctx->streamout.enabled_stream_buffers_mask =
2258 shader_with_so->enabled_streamout_buffer_mask;
2259 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2260 }
2261
2262 static void si_update_clip_regs(struct si_context *sctx,
2263 struct si_shader_selector *old_hw_vs,
2264 struct si_shader *old_hw_vs_variant,
2265 struct si_shader_selector *next_hw_vs,
2266 struct si_shader *next_hw_vs_variant)
2267 {
2268 if (next_hw_vs &&
2269 (!old_hw_vs ||
2270 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2271 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2272 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2273 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2274 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2275 !old_hw_vs_variant ||
2276 !next_hw_vs_variant ||
2277 old_hw_vs_variant->key.opt.clip_disable !=
2278 next_hw_vs_variant->key.opt.clip_disable))
2279 si_mark_atom_dirty(sctx, &sctx->clip_regs);
2280 }
2281
2282 static void si_update_common_shader_state(struct si_context *sctx)
2283 {
2284 sctx->uses_bindless_samplers =
2285 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2286 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2287 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2288 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2289 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2290 sctx->uses_bindless_images =
2291 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2292 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2293 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2294 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2295 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2296 sctx->do_update_shaders = true;
2297 }
2298
2299 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2300 {
2301 struct si_context *sctx = (struct si_context *)ctx;
2302 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2303 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2304 struct si_shader_selector *sel = state;
2305
2306 if (sctx->vs_shader.cso == sel)
2307 return;
2308
2309 sctx->vs_shader.cso = sel;
2310 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2311 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2312
2313 si_update_common_shader_state(sctx);
2314 si_update_vs_viewport_state(sctx);
2315 si_set_active_descriptors_for_shader(sctx, sel);
2316 si_update_streamout_state(sctx);
2317 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2318 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2319 }
2320
2321 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2322 {
2323 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2324 (sctx->tes_shader.cso &&
2325 sctx->tes_shader.cso->info.uses_primid) ||
2326 (sctx->tcs_shader.cso &&
2327 sctx->tcs_shader.cso->info.uses_primid) ||
2328 (sctx->gs_shader.cso &&
2329 sctx->gs_shader.cso->info.uses_primid) ||
2330 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2331 sctx->ps_shader.cso->info.uses_primid);
2332 }
2333
2334 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2335 {
2336 struct si_context *sctx = (struct si_context *)ctx;
2337 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2338 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2339 struct si_shader_selector *sel = state;
2340 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2341
2342 if (sctx->gs_shader.cso == sel)
2343 return;
2344
2345 sctx->gs_shader.cso = sel;
2346 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2347 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2348
2349 si_update_common_shader_state(sctx);
2350 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2351
2352 if (enable_changed) {
2353 si_shader_change_notify(sctx);
2354 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2355 si_update_tess_uses_prim_id(sctx);
2356 }
2357 si_update_vs_viewport_state(sctx);
2358 si_set_active_descriptors_for_shader(sctx, sel);
2359 si_update_streamout_state(sctx);
2360 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2361 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2362 }
2363
2364 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2365 {
2366 struct si_context *sctx = (struct si_context *)ctx;
2367 struct si_shader_selector *sel = state;
2368 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2369
2370 if (sctx->tcs_shader.cso == sel)
2371 return;
2372
2373 sctx->tcs_shader.cso = sel;
2374 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
2375 si_update_tess_uses_prim_id(sctx);
2376
2377 si_update_common_shader_state(sctx);
2378
2379 if (enable_changed)
2380 sctx->last_tcs = NULL; /* invalidate derived tess state */
2381
2382 si_set_active_descriptors_for_shader(sctx, sel);
2383 }
2384
2385 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
2386 {
2387 struct si_context *sctx = (struct si_context *)ctx;
2388 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2389 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2390 struct si_shader_selector *sel = state;
2391 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
2392
2393 if (sctx->tes_shader.cso == sel)
2394 return;
2395
2396 sctx->tes_shader.cso = sel;
2397 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
2398 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
2399 si_update_tess_uses_prim_id(sctx);
2400
2401 si_update_common_shader_state(sctx);
2402 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2403
2404 if (enable_changed) {
2405 si_shader_change_notify(sctx);
2406 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
2407 }
2408 si_update_vs_viewport_state(sctx);
2409 si_set_active_descriptors_for_shader(sctx, sel);
2410 si_update_streamout_state(sctx);
2411 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2412 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2413 }
2414
2415 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2416 {
2417 struct si_context *sctx = (struct si_context *)ctx;
2418 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
2419 struct si_shader_selector *sel = state;
2420
2421 /* skip if supplied shader is one already in use */
2422 if (old_sel == sel)
2423 return;
2424
2425 sctx->ps_shader.cso = sel;
2426 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
2427
2428 si_update_common_shader_state(sctx);
2429 if (sel) {
2430 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2431 si_update_tess_uses_prim_id(sctx);
2432
2433 if (!old_sel ||
2434 old_sel->info.colors_written != sel->info.colors_written)
2435 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2436
2437 if (sctx->screen->has_out_of_order_rast &&
2438 (!old_sel ||
2439 old_sel->info.writes_memory != sel->info.writes_memory ||
2440 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
2441 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
2442 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2443 }
2444 si_set_active_descriptors_for_shader(sctx, sel);
2445 }
2446
2447 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
2448 {
2449 if (shader->is_optimized) {
2450 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
2451 &shader->optimized_ready);
2452 util_queue_fence_destroy(&shader->optimized_ready);
2453 }
2454
2455 if (shader->pm4) {
2456 switch (shader->selector->type) {
2457 case PIPE_SHADER_VERTEX:
2458 if (shader->key.as_ls) {
2459 assert(sctx->b.chip_class <= VI);
2460 si_pm4_delete_state(sctx, ls, shader->pm4);
2461 } else if (shader->key.as_es) {
2462 assert(sctx->b.chip_class <= VI);
2463 si_pm4_delete_state(sctx, es, shader->pm4);
2464 } else {
2465 si_pm4_delete_state(sctx, vs, shader->pm4);
2466 }
2467 break;
2468 case PIPE_SHADER_TESS_CTRL:
2469 si_pm4_delete_state(sctx, hs, shader->pm4);
2470 break;
2471 case PIPE_SHADER_TESS_EVAL:
2472 if (shader->key.as_es) {
2473 assert(sctx->b.chip_class <= VI);
2474 si_pm4_delete_state(sctx, es, shader->pm4);
2475 } else {
2476 si_pm4_delete_state(sctx, vs, shader->pm4);
2477 }
2478 break;
2479 case PIPE_SHADER_GEOMETRY:
2480 if (shader->is_gs_copy_shader)
2481 si_pm4_delete_state(sctx, vs, shader->pm4);
2482 else
2483 si_pm4_delete_state(sctx, gs, shader->pm4);
2484 break;
2485 case PIPE_SHADER_FRAGMENT:
2486 si_pm4_delete_state(sctx, ps, shader->pm4);
2487 break;
2488 }
2489 }
2490
2491 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
2492 si_shader_destroy(shader);
2493 free(shader);
2494 }
2495
2496 void si_destroy_shader_selector(struct si_context *sctx,
2497 struct si_shader_selector *sel)
2498 {
2499 struct si_shader *p = sel->first_variant, *c;
2500 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
2501 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
2502 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
2503 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
2504 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
2505 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
2506 };
2507
2508 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
2509
2510 if (current_shader[sel->type]->cso == sel) {
2511 current_shader[sel->type]->cso = NULL;
2512 current_shader[sel->type]->current = NULL;
2513 }
2514
2515 while (p) {
2516 c = p->next_variant;
2517 si_delete_shader(sctx, p);
2518 p = c;
2519 }
2520
2521 if (sel->main_shader_part)
2522 si_delete_shader(sctx, sel->main_shader_part);
2523 if (sel->main_shader_part_ls)
2524 si_delete_shader(sctx, sel->main_shader_part_ls);
2525 if (sel->main_shader_part_es)
2526 si_delete_shader(sctx, sel->main_shader_part_es);
2527 if (sel->gs_copy_shader)
2528 si_delete_shader(sctx, sel->gs_copy_shader);
2529
2530 util_queue_fence_destroy(&sel->ready);
2531 mtx_destroy(&sel->mutex);
2532 free(sel->tokens);
2533 ralloc_free(sel->nir);
2534 free(sel);
2535 }
2536
2537 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
2538 {
2539 struct si_context *sctx = (struct si_context *)ctx;
2540 struct si_shader_selector *sel = (struct si_shader_selector *)state;
2541
2542 si_shader_selector_reference(sctx, &sel, NULL);
2543 }
2544
2545 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
2546 struct si_shader *vs, unsigned name,
2547 unsigned index, unsigned interpolate)
2548 {
2549 struct tgsi_shader_info *vsinfo = &vs->selector->info;
2550 unsigned j, offset, ps_input_cntl = 0;
2551
2552 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
2553 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
2554 ps_input_cntl |= S_028644_FLAT_SHADE(1);
2555
2556 if (name == TGSI_SEMANTIC_PCOORD ||
2557 (name == TGSI_SEMANTIC_TEXCOORD &&
2558 sctx->sprite_coord_enable & (1 << index))) {
2559 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
2560 }
2561
2562 for (j = 0; j < vsinfo->num_outputs; j++) {
2563 if (name == vsinfo->output_semantic_name[j] &&
2564 index == vsinfo->output_semantic_index[j]) {
2565 offset = vs->info.vs_output_param_offset[j];
2566
2567 if (offset <= AC_EXP_PARAM_OFFSET_31) {
2568 /* The input is loaded from parameter memory. */
2569 ps_input_cntl |= S_028644_OFFSET(offset);
2570 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2571 if (offset == AC_EXP_PARAM_UNDEFINED) {
2572 /* This can happen with depth-only rendering. */
2573 offset = 0;
2574 } else {
2575 /* The input is a DEFAULT_VAL constant. */
2576 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
2577 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
2578 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
2579 }
2580
2581 ps_input_cntl = S_028644_OFFSET(0x20) |
2582 S_028644_DEFAULT_VAL(offset);
2583 }
2584 break;
2585 }
2586 }
2587
2588 if (name == TGSI_SEMANTIC_PRIMID)
2589 /* PrimID is written after the last output. */
2590 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
2591 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
2592 /* No corresponding output found, load defaults into input.
2593 * Don't set any other bits.
2594 * (FLAT_SHADE=1 completely changes behavior) */
2595 ps_input_cntl = S_028644_OFFSET(0x20);
2596 /* D3D 9 behaviour. GL is undefined */
2597 if (name == TGSI_SEMANTIC_COLOR && index == 0)
2598 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
2599 }
2600 return ps_input_cntl;
2601 }
2602
2603 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
2604 {
2605 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2606 struct si_shader *ps = sctx->ps_shader.current;
2607 struct si_shader *vs = si_get_vs_state(sctx);
2608 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
2609 unsigned i, num_interp, num_written = 0, bcol_interp[2];
2610
2611 if (!ps || !ps->selector->info.num_inputs)
2612 return;
2613
2614 num_interp = si_get_ps_num_interp(ps);
2615 assert(num_interp > 0);
2616 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
2617
2618 for (i = 0; i < psinfo->num_inputs; i++) {
2619 unsigned name = psinfo->input_semantic_name[i];
2620 unsigned index = psinfo->input_semantic_index[i];
2621 unsigned interpolate = psinfo->input_interpolate[i];
2622
2623 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
2624 interpolate));
2625 num_written++;
2626
2627 if (name == TGSI_SEMANTIC_COLOR) {
2628 assert(index < ARRAY_SIZE(bcol_interp));
2629 bcol_interp[index] = interpolate;
2630 }
2631 }
2632
2633 if (ps->key.part.ps.prolog.color_two_side) {
2634 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
2635
2636 for (i = 0; i < 2; i++) {
2637 if (!(psinfo->colors_read & (0xf << (i * 4))))
2638 continue;
2639
2640 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
2641 i, bcol_interp[i]));
2642 num_written++;
2643 }
2644 }
2645 assert(num_interp == num_written);
2646 }
2647
2648 /**
2649 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
2650 */
2651 static void si_init_config_add_vgt_flush(struct si_context *sctx)
2652 {
2653 if (sctx->init_config_has_vgt_flush)
2654 return;
2655
2656 /* Done by Vulkan before VGT_FLUSH. */
2657 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2658 si_pm4_cmd_add(sctx->init_config,
2659 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2660 si_pm4_cmd_end(sctx->init_config, false);
2661
2662 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
2663 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
2664 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2665 si_pm4_cmd_end(sctx->init_config, false);
2666 sctx->init_config_has_vgt_flush = true;
2667 }
2668
2669 /* Initialize state related to ESGS / GSVS ring buffers */
2670 static bool si_update_gs_ring_buffers(struct si_context *sctx)
2671 {
2672 struct si_shader_selector *es =
2673 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
2674 struct si_shader_selector *gs = sctx->gs_shader.cso;
2675 struct si_pm4_state *pm4;
2676
2677 /* Chip constants. */
2678 unsigned num_se = sctx->screen->b.info.max_se;
2679 unsigned wave_size = 64;
2680 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2681 /* On SI-CI, the value comes from VGT_GS_VERTEX_REUSE = 16.
2682 * On VI+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2683 */
2684 unsigned gs_vertex_reuse = (sctx->b.chip_class >= VI ? 32 : 16) * num_se;
2685 unsigned alignment = 256 * num_se;
2686 /* The maximum size is 63.999 MB per SE. */
2687 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2688
2689 /* Calculate the minimum size. */
2690 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
2691 wave_size, alignment);
2692
2693 /* These are recommended sizes, not minimum sizes. */
2694 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2695 es->esgs_itemsize * gs->gs_input_verts_per_prim;
2696 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2697 gs->max_gsvs_emit_size;
2698
2699 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2700 esgs_ring_size = align(esgs_ring_size, alignment);
2701 gsvs_ring_size = align(gsvs_ring_size, alignment);
2702
2703 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2704 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2705
2706 /* Some rings don't have to be allocated if shaders don't use them.
2707 * (e.g. no varyings between ES and GS or GS and VS)
2708 *
2709 * GFX9 doesn't have the ESGS ring.
2710 */
2711 bool update_esgs = sctx->b.chip_class <= VI &&
2712 esgs_ring_size &&
2713 (!sctx->esgs_ring ||
2714 sctx->esgs_ring->width0 < esgs_ring_size);
2715 bool update_gsvs = gsvs_ring_size &&
2716 (!sctx->gsvs_ring ||
2717 sctx->gsvs_ring->width0 < gsvs_ring_size);
2718
2719 if (!update_esgs && !update_gsvs)
2720 return true;
2721
2722 if (update_esgs) {
2723 pipe_resource_reference(&sctx->esgs_ring, NULL);
2724 sctx->esgs_ring =
2725 si_aligned_buffer_create(sctx->b.b.screen,
2726 R600_RESOURCE_FLAG_UNMAPPABLE,
2727 PIPE_USAGE_DEFAULT,
2728 esgs_ring_size, alignment);
2729 if (!sctx->esgs_ring)
2730 return false;
2731 }
2732
2733 if (update_gsvs) {
2734 pipe_resource_reference(&sctx->gsvs_ring, NULL);
2735 sctx->gsvs_ring =
2736 si_aligned_buffer_create(sctx->b.b.screen,
2737 R600_RESOURCE_FLAG_UNMAPPABLE,
2738 PIPE_USAGE_DEFAULT,
2739 gsvs_ring_size, alignment);
2740 if (!sctx->gsvs_ring)
2741 return false;
2742 }
2743
2744 /* Create the "init_config_gs_rings" state. */
2745 pm4 = CALLOC_STRUCT(si_pm4_state);
2746 if (!pm4)
2747 return false;
2748
2749 if (sctx->b.chip_class >= CIK) {
2750 if (sctx->esgs_ring) {
2751 assert(sctx->b.chip_class <= VI);
2752 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
2753 sctx->esgs_ring->width0 / 256);
2754 }
2755 if (sctx->gsvs_ring)
2756 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
2757 sctx->gsvs_ring->width0 / 256);
2758 } else {
2759 if (sctx->esgs_ring)
2760 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
2761 sctx->esgs_ring->width0 / 256);
2762 if (sctx->gsvs_ring)
2763 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
2764 sctx->gsvs_ring->width0 / 256);
2765 }
2766
2767 /* Set the state. */
2768 if (sctx->init_config_gs_rings)
2769 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
2770 sctx->init_config_gs_rings = pm4;
2771
2772 if (!sctx->init_config_has_vgt_flush) {
2773 si_init_config_add_vgt_flush(sctx);
2774 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
2775 }
2776
2777 /* Flush the context to re-emit both init_config states. */
2778 sctx->b.initial_gfx_cs_size = 0; /* force flush */
2779 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
2780
2781 /* Set ring bindings. */
2782 if (sctx->esgs_ring) {
2783 assert(sctx->b.chip_class <= VI);
2784 si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
2785 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2786 true, true, 4, 64, 0);
2787 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
2788 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
2789 false, false, 0, 0, 0);
2790 }
2791 if (sctx->gsvs_ring) {
2792 si_set_ring_buffer(&sctx->b.b, SI_RING_GSVS,
2793 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
2794 false, false, 0, 0, 0);
2795 }
2796
2797 return true;
2798 }
2799
2800 static void si_shader_lock(struct si_shader *shader)
2801 {
2802 mtx_lock(&shader->selector->mutex);
2803 if (shader->previous_stage_sel) {
2804 assert(shader->previous_stage_sel != shader->selector);
2805 mtx_lock(&shader->previous_stage_sel->mutex);
2806 }
2807 }
2808
2809 static void si_shader_unlock(struct si_shader *shader)
2810 {
2811 if (shader->previous_stage_sel)
2812 mtx_unlock(&shader->previous_stage_sel->mutex);
2813 mtx_unlock(&shader->selector->mutex);
2814 }
2815
2816 /**
2817 * @returns 1 if \p sel has been updated to use a new scratch buffer
2818 * 0 if not
2819 * < 0 if there was a failure
2820 */
2821 static int si_update_scratch_buffer(struct si_context *sctx,
2822 struct si_shader *shader)
2823 {
2824 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
2825 int r;
2826
2827 if (!shader)
2828 return 0;
2829
2830 /* This shader doesn't need a scratch buffer */
2831 if (shader->config.scratch_bytes_per_wave == 0)
2832 return 0;
2833
2834 /* Prevent race conditions when updating:
2835 * - si_shader::scratch_bo
2836 * - si_shader::binary::code
2837 * - si_shader::previous_stage::binary::code.
2838 */
2839 si_shader_lock(shader);
2840
2841 /* This shader is already configured to use the current
2842 * scratch buffer. */
2843 if (shader->scratch_bo == sctx->scratch_buffer) {
2844 si_shader_unlock(shader);
2845 return 0;
2846 }
2847
2848 assert(sctx->scratch_buffer);
2849
2850 if (shader->previous_stage)
2851 si_shader_apply_scratch_relocs(shader->previous_stage, scratch_va);
2852
2853 si_shader_apply_scratch_relocs(shader, scratch_va);
2854
2855 /* Replace the shader bo with a new bo that has the relocs applied. */
2856 r = si_shader_binary_upload(sctx->screen, shader);
2857 if (r) {
2858 si_shader_unlock(shader);
2859 return r;
2860 }
2861
2862 /* Update the shader state to use the new shader bo. */
2863 si_shader_init_pm4_state(sctx->screen, shader);
2864
2865 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
2866
2867 si_shader_unlock(shader);
2868 return 1;
2869 }
2870
2871 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
2872 {
2873 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
2874 }
2875
2876 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
2877 {
2878 return shader ? shader->config.scratch_bytes_per_wave : 0;
2879 }
2880
2881 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
2882 {
2883 if (!sctx->tes_shader.cso)
2884 return NULL; /* tessellation disabled */
2885
2886 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
2887 sctx->fixed_func_tcs_shader.current;
2888 }
2889
2890 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
2891 {
2892 unsigned bytes = 0;
2893
2894 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
2895 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
2896 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
2897 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
2898
2899 if (sctx->tes_shader.cso) {
2900 struct si_shader *tcs = si_get_tcs_current(sctx);
2901
2902 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
2903 }
2904 return bytes;
2905 }
2906
2907 static bool si_update_scratch_relocs(struct si_context *sctx)
2908 {
2909 struct si_shader *tcs = si_get_tcs_current(sctx);
2910 int r;
2911
2912 /* Update the shaders, so that they are using the latest scratch.
2913 * The scratch buffer may have been changed since these shaders were
2914 * last used, so we still need to try to update them, even if they
2915 * require scratch buffers smaller than the current size.
2916 */
2917 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
2918 if (r < 0)
2919 return false;
2920 if (r == 1)
2921 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2922
2923 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
2924 if (r < 0)
2925 return false;
2926 if (r == 1)
2927 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
2928
2929 r = si_update_scratch_buffer(sctx, tcs);
2930 if (r < 0)
2931 return false;
2932 if (r == 1)
2933 si_pm4_bind_state(sctx, hs, tcs->pm4);
2934
2935 /* VS can be bound as LS, ES, or VS. */
2936 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
2937 if (r < 0)
2938 return false;
2939 if (r == 1) {
2940 if (sctx->tes_shader.current)
2941 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
2942 else if (sctx->gs_shader.current)
2943 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
2944 else
2945 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
2946 }
2947
2948 /* TES can be bound as ES or VS. */
2949 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
2950 if (r < 0)
2951 return false;
2952 if (r == 1) {
2953 if (sctx->gs_shader.current)
2954 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
2955 else
2956 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
2957 }
2958
2959 return true;
2960 }
2961
2962 static bool si_update_spi_tmpring_size(struct si_context *sctx)
2963 {
2964 unsigned current_scratch_buffer_size =
2965 si_get_current_scratch_buffer_size(sctx);
2966 unsigned scratch_bytes_per_wave =
2967 si_get_max_scratch_bytes_per_wave(sctx);
2968 unsigned scratch_needed_size = scratch_bytes_per_wave *
2969 sctx->scratch_waves;
2970 unsigned spi_tmpring_size;
2971
2972 if (scratch_needed_size > 0) {
2973 if (scratch_needed_size > current_scratch_buffer_size) {
2974 /* Create a bigger scratch buffer */
2975 r600_resource_reference(&sctx->scratch_buffer, NULL);
2976
2977 sctx->scratch_buffer = (struct r600_resource*)
2978 si_aligned_buffer_create(&sctx->screen->b.b,
2979 R600_RESOURCE_FLAG_UNMAPPABLE,
2980 PIPE_USAGE_DEFAULT,
2981 scratch_needed_size, 256);
2982 if (!sctx->scratch_buffer)
2983 return false;
2984
2985 si_mark_atom_dirty(sctx, &sctx->scratch_state);
2986 r600_context_add_resource_size(&sctx->b.b,
2987 &sctx->scratch_buffer->b.b);
2988 }
2989
2990 if (!si_update_scratch_relocs(sctx))
2991 return false;
2992 }
2993
2994 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
2995 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
2996 "scratch size should already be aligned correctly.");
2997
2998 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
2999 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3000 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3001 sctx->spi_tmpring_size = spi_tmpring_size;
3002 si_mark_atom_dirty(sctx, &sctx->scratch_state);
3003 }
3004 return true;
3005 }
3006
3007 static void si_init_tess_factor_ring(struct si_context *sctx)
3008 {
3009 bool double_offchip_buffers = sctx->b.chip_class >= CIK &&
3010 sctx->b.family != CHIP_CARRIZO &&
3011 sctx->b.family != CHIP_STONEY;
3012 /* This must be one less than the maximum number due to a hw limitation.
3013 * Various hardware bugs in SI, CIK, and GFX9 need this.
3014 */
3015 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
3016 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
3017 sctx->screen->b.info.max_se;
3018 unsigned offchip_granularity;
3019
3020 switch (sctx->screen->tess_offchip_block_dw_size) {
3021 default:
3022 assert(0);
3023 /* fall through */
3024 case 8192:
3025 offchip_granularity = V_03093C_X_8K_DWORDS;
3026 break;
3027 case 4096:
3028 offchip_granularity = V_03093C_X_4K_DWORDS;
3029 break;
3030 }
3031
3032 assert(!sctx->tf_ring);
3033 /* Use 64K alignment for both rings, so that we can pass the address
3034 * to shaders as one SGPR containing bits [16:47].
3035 */
3036 sctx->tf_ring = si_aligned_buffer_create(sctx->b.b.screen,
3037 R600_RESOURCE_FLAG_UNMAPPABLE,
3038 PIPE_USAGE_DEFAULT,
3039 32768 * sctx->screen->b.info.max_se,
3040 64 * 1024);
3041 if (!sctx->tf_ring)
3042 return;
3043
3044 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
3045
3046 sctx->tess_offchip_ring =
3047 si_aligned_buffer_create(sctx->b.b.screen,
3048 R600_RESOURCE_FLAG_UNMAPPABLE,
3049 PIPE_USAGE_DEFAULT,
3050 max_offchip_buffers *
3051 sctx->screen->tess_offchip_block_dw_size * 4,
3052 64 * 1024);
3053 if (!sctx->tess_offchip_ring)
3054 return;
3055
3056 si_init_config_add_vgt_flush(sctx);
3057
3058 uint64_t offchip_va = r600_resource(sctx->tess_offchip_ring)->gpu_address;
3059 uint64_t factor_va = r600_resource(sctx->tf_ring)->gpu_address;
3060 assert((offchip_va & 0xffff) == 0);
3061 assert((factor_va & 0xffff) == 0);
3062
3063 si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tess_offchip_ring),
3064 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3065 si_pm4_add_bo(sctx->init_config, r600_resource(sctx->tf_ring),
3066 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3067
3068 /* Append these registers to the init config state. */
3069 if (sctx->b.chip_class >= CIK) {
3070 if (sctx->b.chip_class >= VI)
3071 --max_offchip_buffers;
3072
3073 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3074 S_030938_SIZE(sctx->tf_ring->width0 / 4));
3075 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3076 factor_va >> 8);
3077 if (sctx->b.chip_class >= GFX9)
3078 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3079 factor_va >> 40);
3080 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3081 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
3082 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity));
3083 } else {
3084 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
3085 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3086 S_008988_SIZE(sctx->tf_ring->width0 / 4));
3087 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3088 factor_va >> 8);
3089 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3090 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers));
3091 }
3092
3093 if (sctx->b.chip_class >= GFX9) {
3094 si_pm4_set_reg(sctx->init_config,
3095 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
3096 GFX9_SGPR_TCS_OFFCHIP_ADDR_BASE64K * 4,
3097 offchip_va >> 16);
3098 si_pm4_set_reg(sctx->init_config,
3099 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
3100 GFX9_SGPR_TCS_FACTOR_ADDR_BASE64K * 4,
3101 factor_va >> 16);
3102 } else {
3103 si_pm4_set_reg(sctx->init_config,
3104 R_00B430_SPI_SHADER_USER_DATA_HS_0 +
3105 GFX6_SGPR_TCS_OFFCHIP_ADDR_BASE64K * 4,
3106 offchip_va >> 16);
3107 si_pm4_set_reg(sctx->init_config,
3108 R_00B430_SPI_SHADER_USER_DATA_HS_0 +
3109 GFX6_SGPR_TCS_FACTOR_ADDR_BASE64K * 4,
3110 factor_va >> 16);
3111 }
3112
3113 /* Flush the context to re-emit the init_config state.
3114 * This is done only once in a lifetime of a context.
3115 */
3116 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3117 sctx->b.initial_gfx_cs_size = 0; /* force flush */
3118 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
3119 }
3120
3121 /**
3122 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
3123 * VS passes its outputs to TES directly, so the fixed-function shader only
3124 * has to write TESSOUTER and TESSINNER.
3125 */
3126 static void si_generate_fixed_func_tcs(struct si_context *sctx)
3127 {
3128 struct ureg_src outer, inner;
3129 struct ureg_dst tessouter, tessinner;
3130 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
3131
3132 if (!ureg)
3133 return; /* if we get here, we're screwed */
3134
3135 assert(!sctx->fixed_func_tcs_shader.cso);
3136
3137 outer = ureg_DECL_system_value(ureg,
3138 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
3139 inner = ureg_DECL_system_value(ureg,
3140 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
3141
3142 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
3143 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
3144
3145 ureg_MOV(ureg, tessouter, outer);
3146 ureg_MOV(ureg, tessinner, inner);
3147 ureg_END(ureg);
3148
3149 sctx->fixed_func_tcs_shader.cso =
3150 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
3151 }
3152
3153 static void si_update_vgt_shader_config(struct si_context *sctx)
3154 {
3155 /* Calculate the index of the config.
3156 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
3157 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
3158 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
3159
3160 if (!*pm4) {
3161 uint32_t stages = 0;
3162
3163 *pm4 = CALLOC_STRUCT(si_pm4_state);
3164
3165 if (sctx->tes_shader.cso) {
3166 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3167 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3168
3169 if (sctx->gs_shader.cso)
3170 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3171 S_028B54_GS_EN(1) |
3172 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3173 else
3174 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3175 } else if (sctx->gs_shader.cso) {
3176 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3177 S_028B54_GS_EN(1) |
3178 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3179 }
3180
3181 if (sctx->b.chip_class >= GFX9)
3182 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3183
3184 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3185 }
3186 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3187 }
3188
3189 bool si_update_shaders(struct si_context *sctx)
3190 {
3191 struct pipe_context *ctx = (struct pipe_context*)sctx;
3192 struct si_compiler_ctx_state compiler_state;
3193 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3194 struct si_shader *old_vs = si_get_vs_state(sctx);
3195 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3196 struct si_shader *old_ps = sctx->ps_shader.current;
3197 unsigned old_spi_shader_col_format =
3198 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3199 int r;
3200
3201 compiler_state.tm = sctx->tm;
3202 compiler_state.debug = sctx->b.debug;
3203 compiler_state.is_debug_context = sctx->is_debug;
3204
3205 /* Update stages before GS. */
3206 if (sctx->tes_shader.cso) {
3207 if (!sctx->tf_ring) {
3208 si_init_tess_factor_ring(sctx);
3209 if (!sctx->tf_ring)
3210 return false;
3211 }
3212
3213 /* VS as LS */
3214 if (sctx->b.chip_class <= VI) {
3215 r = si_shader_select(ctx, &sctx->vs_shader,
3216 &compiler_state);
3217 if (r)
3218 return false;
3219 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3220 }
3221
3222 if (sctx->tcs_shader.cso) {
3223 r = si_shader_select(ctx, &sctx->tcs_shader,
3224 &compiler_state);
3225 if (r)
3226 return false;
3227 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3228 } else {
3229 if (!sctx->fixed_func_tcs_shader.cso) {
3230 si_generate_fixed_func_tcs(sctx);
3231 if (!sctx->fixed_func_tcs_shader.cso)
3232 return false;
3233 }
3234
3235 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3236 &compiler_state);
3237 if (r)
3238 return false;
3239 si_pm4_bind_state(sctx, hs,
3240 sctx->fixed_func_tcs_shader.current->pm4);
3241 }
3242
3243 if (sctx->gs_shader.cso) {
3244 /* TES as ES */
3245 if (sctx->b.chip_class <= VI) {
3246 r = si_shader_select(ctx, &sctx->tes_shader,
3247 &compiler_state);
3248 if (r)
3249 return false;
3250 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3251 }
3252 } else {
3253 /* TES as VS */
3254 r = si_shader_select(ctx, &sctx->tes_shader,
3255 &compiler_state);
3256 if (r)
3257 return false;
3258 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3259 }
3260 } else if (sctx->gs_shader.cso) {
3261 if (sctx->b.chip_class <= VI) {
3262 /* VS as ES */
3263 r = si_shader_select(ctx, &sctx->vs_shader,
3264 &compiler_state);
3265 if (r)
3266 return false;
3267 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3268
3269 si_pm4_bind_state(sctx, ls, NULL);
3270 si_pm4_bind_state(sctx, hs, NULL);
3271 }
3272 } else {
3273 /* VS as VS */
3274 r = si_shader_select(ctx, &sctx->vs_shader, &compiler_state);
3275 if (r)
3276 return false;
3277 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3278 si_pm4_bind_state(sctx, ls, NULL);
3279 si_pm4_bind_state(sctx, hs, NULL);
3280 }
3281
3282 /* Update GS. */
3283 if (sctx->gs_shader.cso) {
3284 r = si_shader_select(ctx, &sctx->gs_shader, &compiler_state);
3285 if (r)
3286 return false;
3287 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3288 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3289
3290 if (!si_update_gs_ring_buffers(sctx))
3291 return false;
3292 } else {
3293 si_pm4_bind_state(sctx, gs, NULL);
3294 if (sctx->b.chip_class <= VI)
3295 si_pm4_bind_state(sctx, es, NULL);
3296 }
3297
3298 si_update_vgt_shader_config(sctx);
3299
3300 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3301 si_mark_atom_dirty(sctx, &sctx->clip_regs);
3302
3303 if (sctx->ps_shader.cso) {
3304 unsigned db_shader_control;
3305
3306 r = si_shader_select(ctx, &sctx->ps_shader, &compiler_state);
3307 if (r)
3308 return false;
3309 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3310
3311 db_shader_control =
3312 sctx->ps_shader.cso->db_shader_control |
3313 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3314
3315 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3316 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3317 sctx->flatshade != rs->flatshade) {
3318 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3319 sctx->flatshade = rs->flatshade;
3320 si_mark_atom_dirty(sctx, &sctx->spi_map);
3321 }
3322
3323 if (sctx->screen->b.rbplus_allowed &&
3324 si_pm4_state_changed(sctx, ps) &&
3325 (!old_ps ||
3326 old_spi_shader_col_format !=
3327 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3328 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
3329
3330 if (sctx->ps_db_shader_control != db_shader_control) {
3331 sctx->ps_db_shader_control = db_shader_control;
3332 si_mark_atom_dirty(sctx, &sctx->db_render_state);
3333 if (sctx->screen->dpbb_allowed)
3334 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
3335 }
3336
3337 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3338 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3339 si_mark_atom_dirty(sctx, &sctx->msaa_config);
3340
3341 if (sctx->b.chip_class == SI)
3342 si_mark_atom_dirty(sctx, &sctx->db_render_state);
3343
3344 if (sctx->framebuffer.nr_samples <= 1)
3345 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
3346 }
3347 }
3348
3349 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3350 si_pm4_state_enabled_and_changed(sctx, hs) ||
3351 si_pm4_state_enabled_and_changed(sctx, es) ||
3352 si_pm4_state_enabled_and_changed(sctx, gs) ||
3353 si_pm4_state_enabled_and_changed(sctx, vs) ||
3354 si_pm4_state_enabled_and_changed(sctx, ps)) {
3355 if (!si_update_spi_tmpring_size(sctx))
3356 return false;
3357 }
3358
3359 if (sctx->b.chip_class >= CIK) {
3360 if (si_pm4_state_enabled_and_changed(sctx, ls))
3361 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3362 else if (!sctx->queued.named.ls)
3363 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3364
3365 if (si_pm4_state_enabled_and_changed(sctx, hs))
3366 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3367 else if (!sctx->queued.named.hs)
3368 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3369
3370 if (si_pm4_state_enabled_and_changed(sctx, es))
3371 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
3372 else if (!sctx->queued.named.es)
3373 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
3374
3375 if (si_pm4_state_enabled_and_changed(sctx, gs))
3376 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
3377 else if (!sctx->queued.named.gs)
3378 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
3379
3380 if (si_pm4_state_enabled_and_changed(sctx, vs))
3381 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
3382 else if (!sctx->queued.named.vs)
3383 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
3384
3385 if (si_pm4_state_enabled_and_changed(sctx, ps))
3386 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
3387 else if (!sctx->queued.named.ps)
3388 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
3389 }
3390
3391 sctx->do_update_shaders = false;
3392 return true;
3393 }
3394
3395 static void si_emit_scratch_state(struct si_context *sctx,
3396 struct r600_atom *atom)
3397 {
3398 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3399
3400 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3401 sctx->spi_tmpring_size);
3402
3403 if (sctx->scratch_buffer) {
3404 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
3405 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3406 RADEON_PRIO_SCRATCH_BUFFER);
3407 }
3408 }
3409
3410 void *si_get_blit_vs(struct si_context *sctx, enum blitter_attrib_type type,
3411 unsigned num_layers)
3412 {
3413 struct pipe_context *pipe = &sctx->b.b;
3414 unsigned vs_blit_property;
3415 void **vs;
3416
3417 switch (type) {
3418 case UTIL_BLITTER_ATTRIB_NONE:
3419 vs = num_layers > 1 ? &sctx->vs_blit_pos_layered :
3420 &sctx->vs_blit_pos;
3421 vs_blit_property = SI_VS_BLIT_SGPRS_POS;
3422 break;
3423 case UTIL_BLITTER_ATTRIB_COLOR:
3424 vs = num_layers > 1 ? &sctx->vs_blit_color_layered :
3425 &sctx->vs_blit_color;
3426 vs_blit_property = SI_VS_BLIT_SGPRS_POS_COLOR;
3427 break;
3428 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
3429 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
3430 assert(num_layers == 1);
3431 vs = &sctx->vs_blit_texcoord;
3432 vs_blit_property = SI_VS_BLIT_SGPRS_POS_TEXCOORD;
3433 break;
3434 default:
3435 assert(0);
3436 return NULL;
3437 }
3438 if (*vs)
3439 return *vs;
3440
3441 struct ureg_program *ureg = ureg_create(PIPE_SHADER_VERTEX);
3442 if (!ureg)
3443 return NULL;
3444
3445 /* Tell the shader to load VS inputs from SGPRs: */
3446 ureg_property(ureg, TGSI_PROPERTY_VS_BLIT_SGPRS, vs_blit_property);
3447 ureg_property(ureg, TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION, true);
3448
3449 /* This is just a pass-through shader with 1-3 MOV instructions. */
3450 ureg_MOV(ureg,
3451 ureg_DECL_output(ureg, TGSI_SEMANTIC_POSITION, 0),
3452 ureg_DECL_vs_input(ureg, 0));
3453
3454 if (type != UTIL_BLITTER_ATTRIB_NONE) {
3455 ureg_MOV(ureg,
3456 ureg_DECL_output(ureg, TGSI_SEMANTIC_GENERIC, 0),
3457 ureg_DECL_vs_input(ureg, 1));
3458 }
3459
3460 if (num_layers > 1) {
3461 struct ureg_src instance_id =
3462 ureg_DECL_system_value(ureg, TGSI_SEMANTIC_INSTANCEID, 0);
3463 struct ureg_dst layer =
3464 ureg_DECL_output(ureg, TGSI_SEMANTIC_LAYER, 0);
3465
3466 ureg_MOV(ureg, ureg_writemask(layer, TGSI_WRITEMASK_X),
3467 ureg_scalar(instance_id, TGSI_SWIZZLE_X));
3468 }
3469 ureg_END(ureg);
3470
3471 *vs = ureg_create_shader_and_destroy(ureg, pipe);
3472 return *vs;
3473 }
3474
3475 void si_init_shader_functions(struct si_context *sctx)
3476 {
3477 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
3478 si_init_atom(sctx, &sctx->scratch_state, &sctx->atoms.s.scratch_state,
3479 si_emit_scratch_state);
3480
3481 sctx->b.b.create_vs_state = si_create_shader_selector;
3482 sctx->b.b.create_tcs_state = si_create_shader_selector;
3483 sctx->b.b.create_tes_state = si_create_shader_selector;
3484 sctx->b.b.create_gs_state = si_create_shader_selector;
3485 sctx->b.b.create_fs_state = si_create_shader_selector;
3486
3487 sctx->b.b.bind_vs_state = si_bind_vs_shader;
3488 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
3489 sctx->b.b.bind_tes_state = si_bind_tes_shader;
3490 sctx->b.b.bind_gs_state = si_bind_gs_shader;
3491 sctx->b.b.bind_fs_state = si_bind_ps_shader;
3492
3493 sctx->b.b.delete_vs_state = si_delete_shader_selector;
3494 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
3495 sctx->b.b.delete_tes_state = si_delete_shader_selector;
3496 sctx->b.b.delete_gs_state = si_delete_shader_selector;
3497 sctx->b.b.delete_fs_state = si_delete_shader_selector;
3498 }